drivers/gpu/drm/etnaviv/etnaviv_gpu.c

   1 /*
   2  * Copyright (C) 2015 Etnaviv Project
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License version 2 as published by
   6  * the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program.  If not, see <http://www.gnu.org/licenses/>.
  15  */
  16
  17 #include <linux/component.h>
  18 #include <linux/dma-fence.h>
  19 #include <linux/moduleparam.h>
  20 #include <linux/of_device.h>
  21 #include <linux/thermal.h>
  22
  23 #include "etnaviv_cmdbuf.h"
  24 #include "etnaviv_dump.h"
  25 #include "etnaviv_gpu.h"
  26 #include "etnaviv_gem.h"
  27 #include "etnaviv_mmu.h"
  28 #include "common.xml.h"
  29 #include "state.xml.h"
  30 #include "state_hi.xml.h"
  31 #include "cmdstream.xml.h"
  32
  33 static const struct platform_device_id gpu_ids[] = {
  34         { .name = "etnaviv-gpu,2d" },
  35         { },
  36 };
  37
  38 static bool etnaviv_dump_core = true;
  39 module_param_named(dump_core, etnaviv_dump_core, bool, 0600);
  40
  41 /*
  42  * Driver functions:
  43  */
  44
  45 int etnaviv_gpu_get_param(struct etnaviv_gpu *gpu, u32 param, u64 *value)
  46 {
  47         switch (param) {
  48         case ETNAVIV_PARAM_GPU_MODEL:
  49                 *value = gpu->identity.model;
  50                 break;
  51
  52         case ETNAVIV_PARAM_GPU_REVISION:
  53                 *value = gpu->identity.revision;
  54                 break;
  55
  56         case ETNAVIV_PARAM_GPU_FEATURES_0:
  57                 *value = gpu->identity.features;
  58                 break;
  59
  60         case ETNAVIV_PARAM_GPU_FEATURES_1:
  61                 *value = gpu->identity.minor_features0;
  62                 break;
  63
  64         case ETNAVIV_PARAM_GPU_FEATURES_2:
  65                 *value = gpu->identity.minor_features1;
  66                 break;
  67
  68         case ETNAVIV_PARAM_GPU_FEATURES_3:
  69                 *value = gpu->identity.minor_features2;
  70                 break;
  71
  72         case ETNAVIV_PARAM_GPU_FEATURES_4:
  73                 *value = gpu->identity.minor_features3;
  74                 break;
  75
  76         case ETNAVIV_PARAM_GPU_FEATURES_5:
  77                 *value = gpu->identity.minor_features4;
  78                 break;
  79
  80         case ETNAVIV_PARAM_GPU_FEATURES_6:
  81                 *value = gpu->identity.minor_features5;
  82                 break;
  83
  84         case ETNAVIV_PARAM_GPU_STREAM_COUNT:
  85                 *value = gpu->identity.stream_count;
  86                 break;
  87
  88         case ETNAVIV_PARAM_GPU_REGISTER_MAX:
  89                 *value = gpu->identity.register_max;
  90                 break;
  91
  92         case ETNAVIV_PARAM_GPU_THREAD_COUNT:
  93                 *value = gpu->identity.thread_count;
  94                 break;
  95
  96         case ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE:
  97                 *value = gpu->identity.vertex_cache_size;
  98                 break;
  99
 100         case ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT:
 101                 *value = gpu->identity.shader_core_count;
 102                 break;
 103
 104         case ETNAVIV_PARAM_GPU_PIXEL_PIPES:
 105                 *value = gpu->identity.pixel_pipes;
 106                 break;
 107
 108         case ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE:
 109                 *value = gpu->identity.vertex_output_buffer_size;
 110                 break;
 111
 112         case ETNAVIV_PARAM_GPU_BUFFER_SIZE:
 113                 *value = gpu->identity.buffer_size;
 114                 break;
 115
 116         case ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT:
 117                 *value = gpu->identity.instruction_count;
 118                 break;
 119
 120         case ETNAVIV_PARAM_GPU_NUM_CONSTANTS:
 121                 *value = gpu->identity.num_constants;
 122                 break;
 123
 124         case ETNAVIV_PARAM_GPU_NUM_VARYINGS:
 125                 *value = gpu->identity.varyings_count;
 126                 break;
 127
 128         default:
 129                 DBG("%s: invalid param: %u", dev_name(gpu->dev), param);
 130                 return -EINVAL;
 131         }
 132
 133         return 0;
 134 }
 135
 136
 137 #define etnaviv_is_model_rev(gpu, mod, rev) \
 138         ((gpu)->identity.model == chipModel_##mod && \
 139          (gpu)->identity.revision == rev)
 140 #define etnaviv_field(val, field) \
 141         (((val) & field##__MASK) >> field##__SHIFT)
 142
 143 static void etnaviv_hw_specs(struct etnaviv_gpu *gpu)
 144 {
 145         if (gpu->identity.minor_features0 &
 146             chipMinorFeatures0_MORE_MINOR_FEATURES) {
 147                 u32 specs[4];
 148                 unsigned int streams;
 149
 150                 specs[0] = gpu_read(gpu, VIVS_HI_CHIP_SPECS);
 151                 specs[1] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_2);
 152                 specs[2] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_3);
 153                 specs[3] = gpu_read(gpu, VIVS_HI_CHIP_SPECS_4);
 154
 155                 gpu->identity.stream_count = etnaviv_field(specs[0],
 156                                         VIVS_HI_CHIP_SPECS_STREAM_COUNT);
 157                 gpu->identity.register_max = etnaviv_field(specs[0],
 158                                         VIVS_HI_CHIP_SPECS_REGISTER_MAX);
 159                 gpu->identity.thread_count = etnaviv_field(specs[0],
 160                                         VIVS_HI_CHIP_SPECS_THREAD_COUNT);
 161                 gpu->identity.vertex_cache_size = etnaviv_field(specs[0],
 162                                         VIVS_HI_CHIP_SPECS_VERTEX_CACHE_SIZE);
 163                 gpu->identity.shader_core_count = etnaviv_field(specs[0],
 164                                         VIVS_HI_CHIP_SPECS_SHADER_CORE_COUNT);
 165                 gpu->identity.pixel_pipes = etnaviv_field(specs[0],
 166                                         VIVS_HI_CHIP_SPECS_PIXEL_PIPES);
 167                 gpu->identity.vertex_output_buffer_size =
 168                         etnaviv_field(specs[0],
 169                                 VIVS_HI_CHIP_SPECS_VERTEX_OUTPUT_BUFFER_SIZE);
 170
 171                 gpu->identity.buffer_size = etnaviv_field(specs[1],
 172                                         VIVS_HI_CHIP_SPECS_2_BUFFER_SIZE);
 173                 gpu->identity.instruction_count = etnaviv_field(specs[1],
 174                                         VIVS_HI_CHIP_SPECS_2_INSTRUCTION_COUNT);
 175                 gpu->identity.num_constants = etnaviv_field(specs[1],
 176                                         VIVS_HI_CHIP_SPECS_2_NUM_CONSTANTS);
 177
 178                 gpu->identity.varyings_count = etnaviv_field(specs[2],
 179                                         VIVS_HI_CHIP_SPECS_3_VARYINGS_COUNT);
 180
 181                 /* This overrides the value from older register if non-zero */
 182                 streams = etnaviv_field(specs[3],
 183                                         VIVS_HI_CHIP_SPECS_4_STREAM_COUNT);
 184                 if (streams)
 185                         gpu->identity.stream_count = streams;
 186         }
 187
 188         /* Fill in the stream count if not specified */
 189         if (gpu->identity.stream_count == 0) {
 190                 if (gpu->identity.model >= 0x1000)
 191                         gpu->identity.stream_count = 4;
 192                 else
 193                         gpu->identity.stream_count = 1;
 194         }
 195
 196         /* Convert the register max value */
 197         if (gpu->identity.register_max)
 198                 gpu->identity.register_max = 1 << gpu->identity.register_max;
 199         else if (gpu->identity.model == chipModel_GC400)
 200                 gpu->identity.register_max = 32;
 201         else
 202                 gpu->identity.register_max = 64;
 203
 204         /* Convert thread count */
 205         if (gpu->identity.thread_count)
 206                 gpu->identity.thread_count = 1 << gpu->identity.thread_count;
 207         else if (gpu->identity.model == chipModel_GC400)
 208                 gpu->identity.thread_count = 64;
 209         else if (gpu->identity.model == chipModel_GC500 ||
 210                  gpu->identity.model == chipModel_GC530)
 211                 gpu->identity.thread_count = 128;
 212         else
 213                 gpu->identity.thread_count = 256;
 214
 215         if (gpu->identity.vertex_cache_size == 0)
 216                 gpu->identity.vertex_cache_size = 8;
 217
 218         if (gpu->identity.shader_core_count == 0) {
 219                 if (gpu->identity.model >= 0x1000)
 220                         gpu->identity.shader_core_count = 2;
 221                 else
 222                         gpu->identity.shader_core_count = 1;
 223         }
 224
 225         if (gpu->identity.pixel_pipes == 0)
 226                 gpu->identity.pixel_pipes = 1;
 227
 228         /* Convert virtex buffer size */
 229         if (gpu->identity.vertex_output_buffer_size) {
 230                 gpu->identity.vertex_output_buffer_size =
 231                         1 << gpu->identity.vertex_output_buffer_size;
 232         } else if (gpu->identity.model == chipModel_GC400) {
 233                 if (gpu->identity.revision < 0x4000)
 234                         gpu->identity.vertex_output_buffer_size = 512;
 235                 else if (gpu->identity.revision < 0x4200)
 236                         gpu->identity.vertex_output_buffer_size = 256;
 237                 else
 238                         gpu->identity.vertex_output_buffer_size = 128;
 239         } else {
 240                 gpu->identity.vertex_output_buffer_size = 512;
 241         }
 242
 243         switch (gpu->identity.instruction_count) {
 244         case 0:
 245                 if (etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
 246                     gpu->identity.model == chipModel_GC880)
 247                         gpu->identity.instruction_count = 512;
 248                 else
 249                         gpu->identity.instruction_count = 256;
 250                 break;
 251
 252         case 1:
 253                 gpu->identity.instruction_count = 1024;
 254                 break;
 255
 256         case 2:
 257                 gpu->identity.instruction_count = 2048;
 258                 break;
 259
 260         default:
 261                 gpu->identity.instruction_count = 256;
 262                 break;
 263         }
 264
 265         if (gpu->identity.num_constants == 0)
 266                 gpu->identity.num_constants = 168;
 267
 268         if (gpu->identity.varyings_count == 0) {
 269                 if (gpu->identity.minor_features1 & chipMinorFeatures1_HALTI0)
 270                         gpu->identity.varyings_count = 12;
 271                 else
 272                         gpu->identity.varyings_count = 8;
 273         }
 274
 275         /*
 276          * For some cores, two varyings are consumed for position, so the
 277          * maximum varying count needs to be reduced by one.
 278          */
 279         if (etnaviv_is_model_rev(gpu, GC5000, 0x5434) ||
 280             etnaviv_is_model_rev(gpu, GC4000, 0x5222) ||
 281             etnaviv_is_model_rev(gpu, GC4000, 0x5245) ||
 282             etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
 283             etnaviv_is_model_rev(gpu, GC3000, 0x5435) ||
 284             etnaviv_is_model_rev(gpu, GC2200, 0x5244) ||
 285             etnaviv_is_model_rev(gpu, GC2100, 0x5108) ||
 286             etnaviv_is_model_rev(gpu, GC2000, 0x5108) ||
 287             etnaviv_is_model_rev(gpu, GC1500, 0x5246) ||
 288             etnaviv_is_model_rev(gpu, GC880, 0x5107) ||
 289             etnaviv_is_model_rev(gpu, GC880, 0x5106))
 290                 gpu->identity.varyings_count -= 1;
 291 }
 292
 293 static void etnaviv_hw_identify(struct etnaviv_gpu *gpu)
 294 {
 295         u32 chipIdentity;
 296
 297         chipIdentity = gpu_read(gpu, VIVS_HI_CHIP_IDENTITY);
 298
 299         /* Special case for older graphic cores. */
 300         if (etnaviv_field(chipIdentity, VIVS_HI_CHIP_IDENTITY_FAMILY) == 0x01) {
 301                 gpu->identity.model    = chipModel_GC500;
 302                 gpu->identity.revision = etnaviv_field(chipIdentity,
 303                                          VIVS_HI_CHIP_IDENTITY_REVISION);
 304         } else {
 305
 306                 gpu->identity.model = gpu_read(gpu, VIVS_HI_CHIP_MODEL);
 307                 gpu->identity.revision = gpu_read(gpu, VIVS_HI_CHIP_REV);
 308
 309                 /*
 310                  * !!!! HACK ALERT !!!!
 311                  * Because people change device IDs without letting software
 312                  * know about it - here is the hack to make it all look the
 313                  * same.  Only for GC400 family.
 314                  */
 315                 if ((gpu->identity.model & 0xff00) == 0x0400 &&
 316                     gpu->identity.model != chipModel_GC420) {
 317                         gpu->identity.model = gpu->identity.model & 0x0400;
 318                 }
 319
 320                 /* Another special case */
 321                 if (etnaviv_is_model_rev(gpu, GC300, 0x2201)) {
 322                         u32 chipDate = gpu_read(gpu, VIVS_HI_CHIP_DATE);
 323                         u32 chipTime = gpu_read(gpu, VIVS_HI_CHIP_TIME);
 324
 325                         if (chipDate == 0x20080814 && chipTime == 0x12051100) {
 326                                 /*
 327                                  * This IP has an ECO; put the correct
 328                                  * revision in it.
 329                                  */
 330                                 gpu->identity.revision = 0x1051;
 331                         }
 332                 }
 333
 334                 /*
 335                  * NXP likes to call the GPU on the i.MX6QP GC2000+, but in
 336                  * reality it's just a re-branded GC3000. We can identify this
 337                  * core by the upper half of the revision register being all 1.
 338                  * Fix model/rev here, so all other places can refer to this
 339                  * core by its real identity.
 340                  */
 341                 if (etnaviv_is_model_rev(gpu, GC2000, 0xffff5450)) {
 342                         gpu->identity.model = chipModel_GC3000;
 343                         gpu->identity.revision &= 0xffff;
 344                 }
 345         }
 346
 347         dev_info(gpu->dev, "model: GC%x, revision: %x\n",
 348                  gpu->identity.model, gpu->identity.revision);
 349
 350         gpu->identity.features = gpu_read(gpu, VIVS_HI_CHIP_FEATURE);
 351
 352         /* Disable fast clear on GC700. */
 353         if (gpu->identity.model == chipModel_GC700)
 354                 gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
 355
 356         if ((gpu->identity.model == chipModel_GC500 &&
 357              gpu->identity.revision < 2) ||
 358             (gpu->identity.model == chipModel_GC300 &&
 359              gpu->identity.revision < 0x2000)) {
 360
 361                 /*
 362                  * GC500 rev 1.x and GC300 rev < 2.0 doesn't have these
 363                  * registers.
 364                  */
 365                 gpu->identity.minor_features0 = 0;
 366                 gpu->identity.minor_features1 = 0;
 367                 gpu->identity.minor_features2 = 0;
 368                 gpu->identity.minor_features3 = 0;
 369                 gpu->identity.minor_features4 = 0;
 370                 gpu->identity.minor_features5 = 0;
 371         } else
 372                 gpu->identity.minor_features0 =
 373                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_0);
 374
 375         if (gpu->identity.minor_features0 &
 376             chipMinorFeatures0_MORE_MINOR_FEATURES) {
 377                 gpu->identity.minor_features1 =
 378                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_1);
 379                 gpu->identity.minor_features2 =
 380                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_2);
 381                 gpu->identity.minor_features3 =
 382                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_3);
 383                 gpu->identity.minor_features4 =
 384                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_4);
 385                 gpu->identity.minor_features5 =
 386                                 gpu_read(gpu, VIVS_HI_CHIP_MINOR_FEATURE_5);
 387         }
 388
 389         /* GC600 idle register reports zero bits where modules aren't present */
 390         if (gpu->identity.model == chipModel_GC600) {
 391                 gpu->idle_mask = VIVS_HI_IDLE_STATE_TX |
 392                                  VIVS_HI_IDLE_STATE_RA |
 393                                  VIVS_HI_IDLE_STATE_SE |
 394                                  VIVS_HI_IDLE_STATE_PA |
 395                                  VIVS_HI_IDLE_STATE_SH |
 396                                  VIVS_HI_IDLE_STATE_PE |
 397                                  VIVS_HI_IDLE_STATE_DE |
 398                                  VIVS_HI_IDLE_STATE_FE;
 399         } else {
 400                 gpu->idle_mask = ~VIVS_HI_IDLE_STATE_AXI_LP;
 401         }
 402
 403         etnaviv_hw_specs(gpu);
 404 }
 405
 406 static void etnaviv_gpu_load_clock(struct etnaviv_gpu *gpu, u32 clock)
 407 {
 408         gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock |
 409                   VIVS_HI_CLOCK_CONTROL_FSCALE_CMD_LOAD);
 410         gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, clock);
 411 }
 412
 413 static void etnaviv_gpu_update_clock(struct etnaviv_gpu *gpu)
 414 {
 415         unsigned int fscale = 1 << (6 - gpu->freq_scale);
 416         u32 clock;
 417
 418         clock = VIVS_HI_CLOCK_CONTROL_DISABLE_DEBUG_REGISTERS |
 419                 VIVS_HI_CLOCK_CONTROL_FSCALE_VAL(fscale);
 420
 421         etnaviv_gpu_load_clock(gpu, clock);
 422 }
 423
 424 static int etnaviv_hw_reset(struct etnaviv_gpu *gpu)
 425 {
 426         u32 control, idle;
 427         unsigned long timeout;
 428         bool failed = true;
 429
 430         /* TODO
 431          *
 432          * - clock gating
 433          * - puls eater
 434          * - what about VG?
 435          */
 436
 437         /* We hope that the GPU resets in under one second */
 438         timeout = jiffies + msecs_to_jiffies(1000);
 439
 440         while (time_is_after_jiffies(timeout)) {
 441                 /* enable clock */
 442                 etnaviv_gpu_update_clock(gpu);
 443
 444                 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
 445
 446                 /* Wait for stable clock.  Vivante's code waited for 1ms */
 447                 usleep_range(1000, 10000);
 448
 449                 /* isolate the GPU. */
 450                 control |= VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
 451                 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 452
 453                 /* set soft reset. */
 454                 control |= VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
 455                 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 456
 457                 /* wait for reset. */
 458                 msleep(1);
 459
 460                 /* reset soft reset bit. */
 461                 control &= ~VIVS_HI_CLOCK_CONTROL_SOFT_RESET;
 462                 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 463
 464                 /* reset GPU isolation. */
 465                 control &= ~VIVS_HI_CLOCK_CONTROL_ISOLATE_GPU;
 466                 gpu_write(gpu, VIVS_HI_CLOCK_CONTROL, control);
 467
 468                 /* read idle register. */
 469                 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
 470
 471                 /* try reseting again if FE it not idle */
 472                 if ((idle & VIVS_HI_IDLE_STATE_FE) == 0) {
 473                         dev_dbg(gpu->dev, "FE is not idle\n");
 474                         continue;
 475                 }
 476
 477                 /* read reset register. */
 478                 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
 479
 480                 /* is the GPU idle? */
 481                 if (((control & VIVS_HI_CLOCK_CONTROL_IDLE_3D) == 0) ||
 482                     ((control & VIVS_HI_CLOCK_CONTROL_IDLE_2D) == 0)) {
 483                         dev_dbg(gpu->dev, "GPU is not idle\n");
 484                         continue;
 485                 }
 486
 487                 failed = false;
 488                 break;
 489         }
 490
 491         if (failed) {
 492                 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
 493                 control = gpu_read(gpu, VIVS_HI_CLOCK_CONTROL);
 494
 495                 dev_err(gpu->dev, "GPU failed to reset: FE %sidle, 3D %sidle, 2D %sidle\n",
 496                         idle & VIVS_HI_IDLE_STATE_FE ? "" : "not ",
 497                         control & VIVS_HI_CLOCK_CONTROL_IDLE_3D ? "" : "not ",
 498                         control & VIVS_HI_CLOCK_CONTROL_IDLE_2D ? "" : "not ");
 499
 500                 return -EBUSY;
 501         }
 502
 503         /* We rely on the GPU running, so program the clock */
 504         etnaviv_gpu_update_clock(gpu);
 505
 506         return 0;
 507 }
 508
 509 static void etnaviv_gpu_enable_mlcg(struct etnaviv_gpu *gpu)
 510 {
 511         u32 pmc, ppc;
 512
 513         /* enable clock gating */
 514         ppc = gpu_read(gpu, VIVS_PM_POWER_CONTROLS);
 515         ppc |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING;
 516
 517         /* Disable stall module clock gating for 4.3.0.1 and 4.3.0.2 revs */
 518         if (gpu->identity.revision == 0x4301 ||
 519             gpu->identity.revision == 0x4302)
 520                 ppc |= VIVS_PM_POWER_CONTROLS_DISABLE_STALL_MODULE_CLOCK_GATING;
 521
 522         gpu_write(gpu, VIVS_PM_POWER_CONTROLS, ppc);
 523
 524         pmc = gpu_read(gpu, VIVS_PM_MODULE_CONTROLS);
 525
 526         /* Disable PA clock gating for GC400+ except for GC420 */
 527         if (gpu->identity.model >= chipModel_GC400 &&
 528             gpu->identity.model != chipModel_GC420)
 529                 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PA;
 530
 531         /*
 532          * Disable PE clock gating on revs < 5.0.0.0 when HZ is
 533          * present without a bug fix.
 534          */
 535         if (gpu->identity.revision < 0x5000 &&
 536             gpu->identity.minor_features0 & chipMinorFeatures0_HZ &&
 537             !(gpu->identity.minor_features1 &
 538               chipMinorFeatures1_DISABLE_PE_GATING))
 539                 pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_PE;
 540
 541         if (gpu->identity.revision < 0x5422)
 542                 pmc |= BIT(15); /* Unknown bit */
 543
 544         pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_HZ;
 545         pmc |= VIVS_PM_MODULE_CONTROLS_DISABLE_MODULE_CLOCK_GATING_RA_EZ;
 546
 547         gpu_write(gpu, VIVS_PM_MODULE_CONTROLS, pmc);
 548 }
 549
 550 void etnaviv_gpu_start_fe(struct etnaviv_gpu *gpu, u32 address, u16 prefetch)
 551 {
 552         gpu_write(gpu, VIVS_FE_COMMAND_ADDRESS, address);
 553         gpu_write(gpu, VIVS_FE_COMMAND_CONTROL,
 554                   VIVS_FE_COMMAND_CONTROL_ENABLE |
 555                   VIVS_FE_COMMAND_CONTROL_PREFETCH(prefetch));
 556 }
 557
 558 static void etnaviv_gpu_setup_pulse_eater(struct etnaviv_gpu *gpu)
 559 {
 560         /*
 561          * Base value for VIVS_PM_PULSE_EATER register on models where it
 562          * cannot be read, extracted from vivante kernel driver.
 563          */
 564         u32 pulse_eater = 0x01590880;
 565
 566         if (etnaviv_is_model_rev(gpu, GC4000, 0x5208) ||
 567             etnaviv_is_model_rev(gpu, GC4000, 0x5222)) {
 568                 pulse_eater |= BIT(23);
 569
 570         }
 571
 572         if (etnaviv_is_model_rev(gpu, GC1000, 0x5039) ||
 573             etnaviv_is_model_rev(gpu, GC1000, 0x5040)) {
 574                 pulse_eater &= ~BIT(16);
 575                 pulse_eater |= BIT(17);
 576         }
 577
 578         if ((gpu->identity.revision > 0x5420) &&
 579             (gpu->identity.features & chipFeatures_PIPE_3D))
 580         {
 581                 /* Performance fix: disable internal DFS */
 582                 pulse_eater = gpu_read(gpu, VIVS_PM_PULSE_EATER);
 583                 pulse_eater |= BIT(18);
 584         }
 585
 586         gpu_write(gpu, VIVS_PM_PULSE_EATER, pulse_eater);
 587 }
 588
 589 static void etnaviv_gpu_hw_init(struct etnaviv_gpu *gpu)
 590 {
 591         u16 prefetch;
 592
 593         if ((etnaviv_is_model_rev(gpu, GC320, 0x5007) ||
 594              etnaviv_is_model_rev(gpu, GC320, 0x5220)) &&
 595             gpu_read(gpu, VIVS_HI_CHIP_TIME) != 0x2062400) {
 596                 u32 mc_memory_debug;
 597
 598                 mc_memory_debug = gpu_read(gpu, VIVS_MC_DEBUG_MEMORY) & ~0xff;
 599
 600                 if (gpu->identity.revision == 0x5007)
 601                         mc_memory_debug |= 0x0c;
 602                 else
 603                         mc_memory_debug |= 0x08;
 604
 605                 gpu_write(gpu, VIVS_MC_DEBUG_MEMORY, mc_memory_debug);
 606         }
 607
 608         /* enable module-level clock gating */
 609         etnaviv_gpu_enable_mlcg(gpu);
 610
 611         /*
 612          * Update GPU AXI cache atttribute to "cacheable, no allocate".
 613          * This is necessary to prevent the iMX6 SoC locking up.
 614          */
 615         gpu_write(gpu, VIVS_HI_AXI_CONFIG,
 616                   VIVS_HI_AXI_CONFIG_AWCACHE(2) |
 617                   VIVS_HI_AXI_CONFIG_ARCACHE(2));
 618
 619         /* GC2000 rev 5108 needs a special bus config */
 620         if (etnaviv_is_model_rev(gpu, GC2000, 0x5108)) {
 621                 u32 bus_config = gpu_read(gpu, VIVS_MC_BUS_CONFIG);
 622                 bus_config &= ~(VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG__MASK |
 623                                 VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG__MASK);
 624                 bus_config |= VIVS_MC_BUS_CONFIG_FE_BUS_CONFIG(1) |
 625                               VIVS_MC_BUS_CONFIG_TX_BUS_CONFIG(0);
 626                 gpu_write(gpu, VIVS_MC_BUS_CONFIG, bus_config);
 627         }
 628
 629         /* setup the pulse eater */
 630         etnaviv_gpu_setup_pulse_eater(gpu);
 631
 632         /* setup the MMU */
 633         etnaviv_iommu_restore(gpu);
 634
 635         /* Start command processor */
 636         prefetch = etnaviv_buffer_init(gpu);
 637
 638         gpu_write(gpu, VIVS_HI_INTR_ENBL, ~0U);
 639         etnaviv_gpu_start_fe(gpu, etnaviv_cmdbuf_get_va(gpu->buffer),
 640                              prefetch);
 641 }
 642
 643 int etnaviv_gpu_init(struct etnaviv_gpu *gpu)
 644 {
 645         int ret, i;
 646
 647         ret = pm_runtime_get_sync(gpu->dev);
 648         if (ret < 0) {
 649                 dev_err(gpu->dev, "Failed to enable GPU power domain\n");
 650                 return ret;
 651         }
 652
 653         etnaviv_hw_identify(gpu);
 654
 655         if (gpu->identity.model == 0) {
 656                 dev_err(gpu->dev, "Unknown GPU model\n");
 657                 ret = -ENXIO;
 658                 goto fail;
 659         }
 660
 661         /* Exclude VG cores with FE2.0 */
 662         if (gpu->identity.features & chipFeatures_PIPE_VG &&
 663             gpu->identity.features & chipFeatures_FE20) {
 664                 dev_info(gpu->dev, "Ignoring GPU with VG and FE2.0\n");
 665                 ret = -ENXIO;
 666                 goto fail;
 667         }
 668
 669         /*
 670          * Set the GPU linear window to be at the end of the DMA window, where
 671          * the CMA area is likely to reside. This ensures that we are able to
 672          * map the command buffers while having the linear window overlap as
 673          * much RAM as possible, so we can optimize mappings for other buffers.
 674          *
 675          * For 3D cores only do this if MC2.0 is present, as with MC1.0 it leads
 676          * to different views of the memory on the individual engines.
 677          */
 678         if (!(gpu->identity.features & chipFeatures_PIPE_3D) ||
 679             (gpu->identity.minor_features0 & chipMinorFeatures0_MC20)) {
 680                 u32 dma_mask = (u32)dma_get_required_mask(gpu->dev);
 681                 if (dma_mask < PHYS_OFFSET + SZ_2G)
 682                         gpu->memory_base = PHYS_OFFSET;
 683                 else
 684                         gpu->memory_base = dma_mask - SZ_2G + 1;
 685         } else if (PHYS_OFFSET >= SZ_2G) {
 686                 dev_info(gpu->dev, "Need to move linear window on MC1.0, disabling TS\n");
 687                 gpu->memory_base = PHYS_OFFSET;
 688                 gpu->identity.features &= ~chipFeatures_FAST_CLEAR;
 689         }
 690
 691         ret = etnaviv_hw_reset(gpu);
 692         if (ret) {
 693                 dev_err(gpu->dev, "GPU reset failed\n");
 694                 goto fail;
 695         }
 696
 697         gpu->mmu = etnaviv_iommu_new(gpu);
 698         if (IS_ERR(gpu->mmu)) {
 699                 dev_err(gpu->dev, "Failed to instantiate GPU IOMMU\n");
 700                 ret = PTR_ERR(gpu->mmu);
 701                 goto fail;
 702         }
 703
 704         gpu->cmdbuf_suballoc = etnaviv_cmdbuf_suballoc_new(gpu);
 705         if (IS_ERR(gpu->cmdbuf_suballoc)) {
 706                 dev_err(gpu->dev, "Failed to create cmdbuf suballocator\n");
 707                 ret = PTR_ERR(gpu->cmdbuf_suballoc);
 708                 goto fail;
 709         }
 710
 711         /* Create buffer: */
 712         gpu->buffer = etnaviv_cmdbuf_new(gpu->cmdbuf_suballoc, PAGE_SIZE, 0);
 713         if (!gpu->buffer) {
 714                 ret = -ENOMEM;
 715                 dev_err(gpu->dev, "could not create command buffer\n");
 716                 goto destroy_iommu;
 717         }
 718
 719         if (gpu->mmu->version == ETNAVIV_IOMMU_V1 &&
 720             etnaviv_cmdbuf_get_va(gpu->buffer) > 0x80000000) {
 721                 ret = -EINVAL;
 722                 dev_err(gpu->dev,
 723                         "command buffer outside valid memory window\n");
 724                 goto free_buffer;
 725         }
 726
 727         /* Setup event management */
 728         spin_lock_init(&gpu->event_spinlock);
 729         init_completion(&gpu->event_free);
 730         for (i = 0; i < ARRAY_SIZE(gpu->event); i++) {
 731                 gpu->event[i].used = false;
 732                 complete(&gpu->event_free);
 733         }
 734
 735         /* Now program the hardware */
 736         mutex_lock(&gpu->lock);
 737         etnaviv_gpu_hw_init(gpu);
 738         gpu->exec_state = -1;
 739         mutex_unlock(&gpu->lock);
 740
 741         pm_runtime_mark_last_busy(gpu->dev);
 742         pm_runtime_put_autosuspend(gpu->dev);
 743
 744         return 0;
 745
 746 free_buffer:
 747         etnaviv_cmdbuf_free(gpu->buffer);
 748         gpu->buffer = NULL;
 749 destroy_iommu:
 750         etnaviv_iommu_destroy(gpu->mmu);
 751         gpu->mmu = NULL;
 752 fail:
 753         pm_runtime_mark_last_busy(gpu->dev);
 754         pm_runtime_put_autosuspend(gpu->dev);
 755
 756         return ret;
 757 }
 758
 759 #ifdef CONFIG_DEBUG_FS
 760 struct dma_debug {
 761         u32 address[2];
 762         u32 state[2];
 763 };
 764
 765 static void verify_dma(struct etnaviv_gpu *gpu, struct dma_debug *debug)
 766 {
 767         u32 i;
 768
 769         debug->address[0] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
 770         debug->state[0]   = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
 771
 772         for (i = 0; i < 500; i++) {
 773                 debug->address[1] = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
 774                 debug->state[1]   = gpu_read(gpu, VIVS_FE_DMA_DEBUG_STATE);
 775
 776                 if (debug->address[0] != debug->address[1])
 777                         break;
 778
 779                 if (debug->state[0] != debug->state[1])
 780                         break;
 781         }
 782 }
 783
 784 int etnaviv_gpu_debugfs(struct etnaviv_gpu *gpu, struct seq_file *m)
 785 {
 786         struct dma_debug debug;
 787         u32 dma_lo, dma_hi, axi, idle;
 788         int ret;
 789
 790         seq_printf(m, "%s Status:\n", dev_name(gpu->dev));
 791
 792         ret = pm_runtime_get_sync(gpu->dev);
 793         if (ret < 0)
 794                 return ret;
 795
 796         dma_lo = gpu_read(gpu, VIVS_FE_DMA_LOW);
 797         dma_hi = gpu_read(gpu, VIVS_FE_DMA_HIGH);
 798         axi = gpu_read(gpu, VIVS_HI_AXI_STATUS);
 799         idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
 800
 801         verify_dma(gpu, &debug);
 802
 803         seq_puts(m, "\tfeatures\n");
 804         seq_printf(m, "\t minor_features0: 0x%08x\n",
 805                    gpu->identity.minor_features0);
 806         seq_printf(m, "\t minor_features1: 0x%08x\n",
 807                    gpu->identity.minor_features1);
 808         seq_printf(m, "\t minor_features2: 0x%08x\n",
 809                    gpu->identity.minor_features2);
 810         seq_printf(m, "\t minor_features3: 0x%08x\n",
 811                    gpu->identity.minor_features3);
 812         seq_printf(m, "\t minor_features4: 0x%08x\n",
 813                    gpu->identity.minor_features4);
 814         seq_printf(m, "\t minor_features5: 0x%08x\n",
 815                    gpu->identity.minor_features5);
 816
 817         seq_puts(m, "\tspecs\n");
 818         seq_printf(m, "\t stream_count:  %d\n",
 819                         gpu->identity.stream_count);
 820         seq_printf(m, "\t register_max: %d\n",
 821                         gpu->identity.register_max);
 822         seq_printf(m, "\t thread_count: %d\n",
 823                         gpu->identity.thread_count);
 824         seq_printf(m, "\t vertex_cache_size: %d\n",
 825                         gpu->identity.vertex_cache_size);
 826         seq_printf(m, "\t shader_core_count: %d\n",
 827                         gpu->identity.shader_core_count);
 828         seq_printf(m, "\t pixel_pipes: %d\n",
 829                         gpu->identity.pixel_pipes);
 830         seq_printf(m, "\t vertex_output_buffer_size: %d\n",
 831                         gpu->identity.vertex_output_buffer_size);
 832         seq_printf(m, "\t buffer_size: %d\n",
 833                         gpu->identity.buffer_size);
 834         seq_printf(m, "\t instruction_count: %d\n",
 835                         gpu->identity.instruction_count);
 836         seq_printf(m, "\t num_constants: %d\n",
 837                         gpu->identity.num_constants);
 838         seq_printf(m, "\t varyings_count: %d\n",
 839                         gpu->identity.varyings_count);
 840
 841         seq_printf(m, "\taxi: 0x%08x\n", axi);
 842         seq_printf(m, "\tidle: 0x%08x\n", idle);
 843         idle |= ~gpu->idle_mask & ~VIVS_HI_IDLE_STATE_AXI_LP;
 844         if ((idle & VIVS_HI_IDLE_STATE_FE) == 0)
 845                 seq_puts(m, "\t FE is not idle\n");
 846         if ((idle & VIVS_HI_IDLE_STATE_DE) == 0)
 847                 seq_puts(m, "\t DE is not idle\n");
 848         if ((idle & VIVS_HI_IDLE_STATE_PE) == 0)
 849                 seq_puts(m, "\t PE is not idle\n");
 850         if ((idle & VIVS_HI_IDLE_STATE_SH) == 0)
 851                 seq_puts(m, "\t SH is not idle\n");
 852         if ((idle & VIVS_HI_IDLE_STATE_PA) == 0)
 853                 seq_puts(m, "\t PA is not idle\n");
 854         if ((idle & VIVS_HI_IDLE_STATE_SE) == 0)
 855                 seq_puts(m, "\t SE is not idle\n");
 856         if ((idle & VIVS_HI_IDLE_STATE_RA) == 0)
 857                 seq_puts(m, "\t RA is not idle\n");
 858         if ((idle & VIVS_HI_IDLE_STATE_TX) == 0)
 859                 seq_puts(m, "\t TX is not idle\n");
 860         if ((idle & VIVS_HI_IDLE_STATE_VG) == 0)
 861                 seq_puts(m, "\t VG is not idle\n");
 862         if ((idle & VIVS_HI_IDLE_STATE_IM) == 0)
 863                 seq_puts(m, "\t IM is not idle\n");
 864         if ((idle & VIVS_HI_IDLE_STATE_FP) == 0)
 865                 seq_puts(m, "\t FP is not idle\n");
 866         if ((idle & VIVS_HI_IDLE_STATE_TS) == 0)
 867                 seq_puts(m, "\t TS is not idle\n");
 868         if (idle & VIVS_HI_IDLE_STATE_AXI_LP)
 869                 seq_puts(m, "\t AXI low power mode\n");
 870
 871         if (gpu->identity.features & chipFeatures_DEBUG_MODE) {
 872                 u32 read0 = gpu_read(gpu, VIVS_MC_DEBUG_READ0);
 873                 u32 read1 = gpu_read(gpu, VIVS_MC_DEBUG_READ1);
 874                 u32 write = gpu_read(gpu, VIVS_MC_DEBUG_WRITE);
 875
 876                 seq_puts(m, "\tMC\n");
 877                 seq_printf(m, "\t read0: 0x%08x\n", read0);
 878                 seq_printf(m, "\t read1: 0x%08x\n", read1);
 879                 seq_printf(m, "\t write: 0x%08x\n", write);
 880         }
 881
 882         seq_puts(m, "\tDMA ");
 883
 884         if (debug.address[0] == debug.address[1] &&
 885             debug.state[0] == debug.state[1]) {
 886                 seq_puts(m, "seems to be stuck\n");
 887         } else if (debug.address[0] == debug.address[1]) {
 888                 seq_puts(m, "address is constant\n");
 889         } else {
 890                 seq_puts(m, "is running\n");
 891         }
 892
 893         seq_printf(m, "\t address 0: 0x%08x\n", debug.address[0]);
 894         seq_printf(m, "\t address 1: 0x%08x\n", debug.address[1]);
 895         seq_printf(m, "\t state 0: 0x%08x\n", debug.state[0]);
 896         seq_printf(m, "\t state 1: 0x%08x\n", debug.state[1]);
 897         seq_printf(m, "\t last fetch 64 bit word: 0x%08x 0x%08x\n",
 898                    dma_lo, dma_hi);
 899
 900         ret = 0;
 901
 902         pm_runtime_mark_last_busy(gpu->dev);
 903         pm_runtime_put_autosuspend(gpu->dev);
 904
 905         return ret;
 906 }
 907 #endif
 908
 909 /*
 910  * Hangcheck detection for locked gpu:
 911  */
 912 static void recover_worker(struct work_struct *work)
 913 {
 914         struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu,
 915                                                recover_work);
 916         unsigned long flags;
 917         unsigned int i;
 918
 919         dev_err(gpu->dev, "hangcheck recover!\n");
 920
 921         if (pm_runtime_get_sync(gpu->dev) < 0)
 922                 return;
 923
 924         mutex_lock(&gpu->lock);
 925
 926         /* Only catch the first event, or when manually re-armed */
 927         if (etnaviv_dump_core) {
 928                 etnaviv_core_dump(gpu);
 929                 etnaviv_dump_core = false;
 930         }
 931
 932         etnaviv_hw_reset(gpu);
 933
 934         /* complete all events, the GPU won't do it after the reset */
 935         spin_lock_irqsave(&gpu->event_spinlock, flags);
 936         for (i = 0; i < ARRAY_SIZE(gpu->event); i++) {
 937                 if (!gpu->event[i].used)
 938                         continue;
 939                 dma_fence_signal(gpu->event[i].fence);
 940                 gpu->event[i].fence = NULL;
 941                 gpu->event[i].used = false;
 942                 complete(&gpu->event_free);
 943         }
 944         spin_unlock_irqrestore(&gpu->event_spinlock, flags);
 945         gpu->completed_fence = gpu->active_fence;
 946
 947         etnaviv_gpu_hw_init(gpu);
 948         gpu->lastctx = NULL;
 949         gpu->exec_state = -1;
 950
 951         mutex_unlock(&gpu->lock);
 952         pm_runtime_mark_last_busy(gpu->dev);
 953         pm_runtime_put_autosuspend(gpu->dev);
 954
 955         /* Retire the buffer objects in a work */
 956         etnaviv_queue_work(gpu->drm, &gpu->retire_work);
 957 }
 958
 959 static void hangcheck_timer_reset(struct etnaviv_gpu *gpu)
 960 {
 961         DBG("%s", dev_name(gpu->dev));
 962         mod_timer(&gpu->hangcheck_timer,
 963                   round_jiffies_up(jiffies + DRM_ETNAVIV_HANGCHECK_JIFFIES));
 964 }
 965
 966 static void hangcheck_handler(unsigned long data)
 967 {
 968         struct etnaviv_gpu *gpu = (struct etnaviv_gpu *)data;
 969         u32 fence = gpu->completed_fence;
 970         bool progress = false;
 971
 972         if (fence != gpu->hangcheck_fence) {
 973                 gpu->hangcheck_fence = fence;
 974                 progress = true;
 975         }
 976
 977         if (!progress) {
 978                 u32 dma_addr = gpu_read(gpu, VIVS_FE_DMA_ADDRESS);
 979                 int change = dma_addr - gpu->hangcheck_dma_addr;
 980
 981                 if (change < 0 || change > 16) {
 982                         gpu->hangcheck_dma_addr = dma_addr;
 983                         progress = true;
 984                 }
 985         }
 986
 987         if (!progress && fence_after(gpu->active_fence, fence)) {
 988                 dev_err(gpu->dev, "hangcheck detected gpu lockup!\n");
 989                 dev_err(gpu->dev, "     completed fence: %u\n", fence);
 990                 dev_err(gpu->dev, "     active fence: %u\n",
 991                         gpu->active_fence);
 992                 etnaviv_queue_work(gpu->drm, &gpu->recover_work);
 993         }
 994
 995         /* if still more pending work, reset the hangcheck timer: */
 996         if (fence_after(gpu->active_fence, gpu->hangcheck_fence))
 997                 hangcheck_timer_reset(gpu);
 998 }
 999
1000 static void hangcheck_disable(struct etnaviv_gpu *gpu)
1001 {
1002         del_timer_sync(&gpu->hangcheck_timer);
1003         cancel_work_sync(&gpu->recover_work);
1004 }
1005
1006 /* fence object management */
1007 struct etnaviv_fence {
1008         struct etnaviv_gpu *gpu;
1009         struct dma_fence base;
1010 };
1011
1012 static inline struct etnaviv_fence *to_etnaviv_fence(struct dma_fence *fence)
1013 {
1014         return container_of(fence, struct etnaviv_fence, base);
1015 }
1016
1017 static const char *etnaviv_fence_get_driver_name(struct dma_fence *fence)
1018 {
1019         return "etnaviv";
1020 }
1021
1022 static const char *etnaviv_fence_get_timeline_name(struct dma_fence *fence)
1023 {
1024         struct etnaviv_fence *f = to_etnaviv_fence(fence);
1025
1026         return dev_name(f->gpu->dev);
1027 }
1028
1029 static bool etnaviv_fence_enable_signaling(struct dma_fence *fence)
1030 {
1031         return true;
1032 }
1033
1034 static bool etnaviv_fence_signaled(struct dma_fence *fence)
1035 {
1036         struct etnaviv_fence *f = to_etnaviv_fence(fence);
1037
1038         return fence_completed(f->gpu, f->base.seqno);
1039 }
1040
1041 static void etnaviv_fence_release(struct dma_fence *fence)
1042 {
1043         struct etnaviv_fence *f = to_etnaviv_fence(fence);
1044
1045         kfree_rcu(f, base.rcu);
1046 }
1047
1048 static const struct dma_fence_ops etnaviv_fence_ops = {
1049         .get_driver_name = etnaviv_fence_get_driver_name,
1050         .get_timeline_name = etnaviv_fence_get_timeline_name,
1051         .enable_signaling = etnaviv_fence_enable_signaling,
1052         .signaled = etnaviv_fence_signaled,
1053         .wait = dma_fence_default_wait,
1054         .release = etnaviv_fence_release,
1055 };
1056
1057 static struct dma_fence *etnaviv_gpu_fence_alloc(struct etnaviv_gpu *gpu)
1058 {
1059         struct etnaviv_fence *f;
1060
1061         /*
1062          * GPU lock must already be held, otherwise fence completion order might
1063          * not match the seqno order assigned here.
1064          */
1065         lockdep_assert_held(&gpu->lock);
1066
1067         f = kzalloc(sizeof(*f), GFP_KERNEL);
1068         if (!f)
1069                 return NULL;
1070
1071         f->gpu = gpu;
1072
1073         dma_fence_init(&f->base, &etnaviv_fence_ops, &gpu->fence_spinlock,
1074                        gpu->fence_context, ++gpu->next_fence);
1075
1076         return &f->base;
1077 }
1078
1079 int etnaviv_gpu_fence_sync_obj(struct etnaviv_gem_object *etnaviv_obj,
1080         unsigned int context, bool exclusive, bool explicit)
1081 {
1082         struct reservation_object *robj = etnaviv_obj->resv;
1083         struct reservation_object_list *fobj;
1084         struct dma_fence *fence;
1085         int i, ret;
1086
1087         if (!exclusive) {
1088                 ret = reservation_object_reserve_shared(robj);
1089                 if (ret)
1090                         return ret;
1091         }
1092
1093         if (explicit)
1094                 return 0;
1095
1096         /*
1097          * If we have any shared fences, then the exclusive fence
1098          * should be ignored as it will already have been signalled.
1099          */
1100         fobj = reservation_object_get_list(robj);
1101         if (!fobj || fobj->shared_count == 0) {
1102                 /* Wait on any existing exclusive fence which isn't our own */
1103                 fence = reservation_object_get_excl(robj);
1104                 if (fence && fence->context != context) {
1105                         ret = dma_fence_wait(fence, true);
1106                         if (ret)
1107                                 return ret;
1108                 }
1109         }
1110
1111         if (!exclusive || !fobj)
1112                 return 0;
1113
1114         for (i = 0; i < fobj->shared_count; i++) {
1115                 fence = rcu_dereference_protected(fobj->shared[i],
1116                                                 reservation_object_held(robj));
1117                 if (fence->context != context) {
1118                         ret = dma_fence_wait(fence, true);
1119                         if (ret)
1120                                 return ret;
1121                 }
1122         }
1123
1124         return 0;
1125 }
1126
1127 /*
1128  * event management:
1129  */
1130
1131 static unsigned int event_alloc(struct etnaviv_gpu *gpu)
1132 {
1133         unsigned long ret, flags;
1134         unsigned int i, event = ~0U;
1135
1136         ret = wait_for_completion_timeout(&gpu->event_free,
1137                                           msecs_to_jiffies(10 * 10000));
1138         if (!ret)
1139                 dev_err(gpu->dev, "wait_for_completion_timeout failed");
1140
1141         spin_lock_irqsave(&gpu->event_spinlock, flags);
1142
1143         /* find first free event */
1144         for (i = 0; i < ARRAY_SIZE(gpu->event); i++) {
1145                 if (gpu->event[i].used == false) {
1146                         gpu->event[i].used = true;
1147                         event = i;
1148                         break;
1149                 }
1150         }
1151
1152         spin_unlock_irqrestore(&gpu->event_spinlock, flags);
1153
1154         return event;
1155 }
1156
1157 static void event_free(struct etnaviv_gpu *gpu, unsigned int event)
1158 {
1159         unsigned long flags;
1160
1161         spin_lock_irqsave(&gpu->event_spinlock, flags);
1162
1163         if (gpu->event[event].used == false) {
1164                 dev_warn(gpu->dev, "event %u is already marked as free",
1165                          event);
1166                 spin_unlock_irqrestore(&gpu->event_spinlock, flags);
1167         } else {
1168                 gpu->event[event].used = false;
1169                 spin_unlock_irqrestore(&gpu->event_spinlock, flags);
1170
1171                 complete(&gpu->event_free);
1172         }
1173 }
1174
1175 /*
1176  * Cmdstream submission/retirement:
1177  */
1178
1179 static void retire_worker(struct work_struct *work)
1180 {
1181         struct etnaviv_gpu *gpu = container_of(work, struct etnaviv_gpu,
1182                                                retire_work);
1183         u32 fence = gpu->completed_fence;
1184         struct etnaviv_cmdbuf *cmdbuf, *tmp;
1185         unsigned int i;
1186
1187         mutex_lock(&gpu->lock);
1188         list_for_each_entry_safe(cmdbuf, tmp, &gpu->active_cmd_list, node) {
1189                 if (!dma_fence_is_signaled(cmdbuf->fence))
1190                         break;
1191
1192                 list_del(&cmdbuf->node);
1193                 dma_fence_put(cmdbuf->fence);
1194
1195                 for (i = 0; i < cmdbuf->nr_bos; i++) {
1196                         struct etnaviv_vram_mapping *mapping = cmdbuf->bo_map[i];
1197                         struct etnaviv_gem_object *etnaviv_obj = mapping->object;
1198
1199                         atomic_dec(&etnaviv_obj->gpu_active);
1200                         /* drop the refcount taken in etnaviv_gpu_submit */
1201                         etnaviv_gem_mapping_unreference(mapping);
1202                 }
1203
1204                 etnaviv_cmdbuf_free(cmdbuf);
1205                 /*
1206                  * We need to balance the runtime PM count caused by
1207                  * each submission.  Upon submission, we increment
1208                  * the runtime PM counter, and allocate one event.
1209                  * So here, we put the runtime PM count for each
1210                  * completed event.
1211                  */
1212                 pm_runtime_put_autosuspend(gpu->dev);
1213         }
1214
1215         gpu->retired_fence = fence;
1216
1217         mutex_unlock(&gpu->lock);
1218
1219         wake_up_all(&gpu->fence_event);
1220 }
1221
1222 int etnaviv_gpu_wait_fence_interruptible(struct etnaviv_gpu *gpu,
1223         u32 fence, struct timespec *timeout)
1224 {
1225         int ret;
1226
1227         if (fence_after(fence, gpu->next_fence)) {
1228                 DRM_ERROR("waiting on invalid fence: %u (of %u)\n",
1229                                 fence, gpu->next_fence);
1230                 return -EINVAL;
1231         }
1232
1233         if (!timeout) {
1234                 /* No timeout was requested: just test for completion */
1235                 ret = fence_completed(gpu, fence) ? 0 : -EBUSY;
1236         } else {
1237                 unsigned long remaining = etnaviv_timeout_to_jiffies(timeout);
1238
1239                 ret = wait_event_interruptible_timeout(gpu->fence_event,
1240                                                 fence_completed(gpu, fence),
1241                                                 remaining);
1242                 if (ret == 0) {
1243                         DBG("timeout waiting for fence: %u (retired: %u completed: %u)",
1244                                 fence, gpu->retired_fence,
1245                                 gpu->completed_fence);
1246                         ret = -ETIMEDOUT;
1247                 } else if (ret != -ERESTARTSYS) {
1248                         ret = 0;
1249                 }
1250         }
1251
1252         return ret;
1253 }
1254
1255 /*
1256  * Wait for an object to become inactive.  This, on it's own, is not race
1257  * free: the object is moved by the retire worker off the active list, and
1258  * then the iova is put.  Moreover, the object could be re-submitted just
1259  * after we notice that it's become inactive.
1260  *
1261  * Although the retirement happens under the gpu lock, we don't want to hold
1262  * that lock in this function while waiting.
1263  */
1264 int etnaviv_gpu_wait_obj_inactive(struct etnaviv_gpu *gpu,
1265         struct etnaviv_gem_object *etnaviv_obj, struct timespec *timeout)
1266 {
1267         unsigned long remaining;
1268         long ret;
1269
1270         if (!timeout)
1271                 return !is_active(etnaviv_obj) ? 0 : -EBUSY;
1272
1273         remaining = etnaviv_timeout_to_jiffies(timeout);
1274
1275         ret = wait_event_interruptible_timeout(gpu->fence_event,
1276                                                !is_active(etnaviv_obj),
1277                                                remaining);
1278         if (ret > 0) {
1279                 struct etnaviv_drm_private *priv = gpu->drm->dev_private;
1280
1281                 /* Synchronise with the retire worker */
1282                 flush_workqueue(priv->wq);
1283                 return 0;
1284         } else if (ret == -ERESTARTSYS) {
1285                 return -ERESTARTSYS;
1286         } else {
1287                 return -ETIMEDOUT;
1288         }
1289 }
1290
1291 int etnaviv_gpu_pm_get_sync(struct etnaviv_gpu *gpu)
1292 {
1293         return pm_runtime_get_sync(gpu->dev);
1294 }
1295
1296 void etnaviv_gpu_pm_put(struct etnaviv_gpu *gpu)
1297 {
1298         pm_runtime_mark_last_busy(gpu->dev);
1299         pm_runtime_put_autosuspend(gpu->dev);
1300 }
1301
1302 /* add bo's to gpu's ring, and kick gpu: */
1303 int etnaviv_gpu_submit(struct etnaviv_gpu *gpu,
1304         struct etnaviv_gem_submit *submit, struct etnaviv_cmdbuf *cmdbuf)
1305 {
1306         struct dma_fence *fence;
1307         unsigned int event, i;
1308         int ret;
1309
1310         ret = etnaviv_gpu_pm_get_sync(gpu);
1311         if (ret < 0)
1312                 return ret;
1313
1314         /*
1315          * TODO
1316          *
1317          * - flush
1318          * - data endian
1319          * - prefetch
1320          *
1321          */
1322
1323         event = event_alloc(gpu);
1324         if (unlikely(event == ~0U)) {
1325                 DRM_ERROR("no free event\n");
1326                 ret = -EBUSY;
1327                 goto out_pm_put;
1328         }
1329
1330         mutex_lock(&gpu->lock);
1331
1332         fence = etnaviv_gpu_fence_alloc(gpu);
1333         if (!fence) {
1334                 event_free(gpu, event);
1335                 ret = -ENOMEM;
1336                 goto out_unlock;
1337         }
1338
1339         gpu->event[event].fence = fence;
1340         submit->fence = dma_fence_get(fence);
1341         gpu->active_fence = submit->fence->seqno;
1342
1343         if (gpu->lastctx != cmdbuf->ctx) {
1344                 gpu->mmu->need_flush = true;
1345                 gpu->switch_context = true;
1346                 gpu->lastctx = cmdbuf->ctx;
1347         }
1348
1349         etnaviv_buffer_queue(gpu, event, cmdbuf);
1350
1351         cmdbuf->fence = fence;
1352         list_add_tail(&cmdbuf->node, &gpu->active_cmd_list);
1353
1354         /* We're committed to adding this command buffer, hold a PM reference */
1355         pm_runtime_get_noresume(gpu->dev);
1356
1357         for (i = 0; i < submit->nr_bos; i++) {
1358                 struct etnaviv_gem_object *etnaviv_obj = submit->bos[i].obj;
1359
1360                 /* Each cmdbuf takes a refcount on the mapping */
1361                 etnaviv_gem_mapping_reference(submit->bos[i].mapping);
1362                 cmdbuf->bo_map[i] = submit->bos[i].mapping;
1363                 atomic_inc(&etnaviv_obj->gpu_active);
1364
1365                 if (submit->bos[i].flags & ETNA_SUBMIT_BO_WRITE)
1366                         reservation_object_add_excl_fence(etnaviv_obj->resv,
1367                                                           fence);
1368                 else
1369                         reservation_object_add_shared_fence(etnaviv_obj->resv,
1370                                                             fence);
1371         }
1372         cmdbuf->nr_bos = submit->nr_bos;
1373         hangcheck_timer_reset(gpu);
1374         ret = 0;
1375
1376 out_unlock:
1377         mutex_unlock(&gpu->lock);
1378
1379 out_pm_put:
1380         etnaviv_gpu_pm_put(gpu);
1381
1382         return ret;
1383 }
1384
1385 /*
1386  * Init/Cleanup:
1387  */
1388 static irqreturn_t irq_handler(int irq, void *data)
1389 {
1390         struct etnaviv_gpu *gpu = data;
1391         irqreturn_t ret = IRQ_NONE;
1392
1393         u32 intr = gpu_read(gpu, VIVS_HI_INTR_ACKNOWLEDGE);
1394
1395         if (intr != 0) {
1396                 int event;
1397
1398                 pm_runtime_mark_last_busy(gpu->dev);
1399
1400                 dev_dbg(gpu->dev, "intr 0x%08x\n", intr);
1401
1402                 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR) {
1403                         dev_err(gpu->dev, "AXI bus error\n");
1404                         intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_AXI_BUS_ERROR;
1405                 }
1406
1407                 if (intr & VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION) {
1408                         int i;
1409
1410                         dev_err_ratelimited(gpu->dev,
1411                                 "MMU fault status 0x%08x\n",
1412                                 gpu_read(gpu, VIVS_MMUv2_STATUS));
1413                         for (i = 0; i < 4; i++) {
1414                                 dev_err_ratelimited(gpu->dev,
1415                                         "MMU %d fault addr 0x%08x\n",
1416                                         i, gpu_read(gpu,
1417                                         VIVS_MMUv2_EXCEPTION_ADDR(i)));
1418                         }
1419                         intr &= ~VIVS_HI_INTR_ACKNOWLEDGE_MMU_EXCEPTION;
1420                 }
1421
1422                 while ((event = ffs(intr)) != 0) {
1423                         struct dma_fence *fence;
1424
1425                         event -= 1;
1426
1427                         intr &= ~(1 << event);
1428
1429                         dev_dbg(gpu->dev, "event %u\n", event);
1430
1431                         fence = gpu->event[event].fence;
1432                         gpu->event[event].fence = NULL;
1433                         dma_fence_signal(fence);
1434
1435                         /*
1436                          * Events can be processed out of order.  Eg,
1437                          * - allocate and queue event 0
1438                          * - allocate event 1
1439                          * - event 0 completes, we process it
1440                          * - allocate and queue event 0
1441                          * - event 1 and event 0 complete
1442                          * we can end up processing event 0 first, then 1.
1443                          */
1444                         if (fence_after(fence->seqno, gpu->completed_fence))
1445                                 gpu->completed_fence = fence->seqno;
1446
1447                         event_free(gpu, event);
1448                 }
1449
1450                 /* Retire the buffer objects in a work */
1451                 etnaviv_queue_work(gpu->drm, &gpu->retire_work);
1452
1453                 ret = IRQ_HANDLED;
1454         }
1455
1456         return ret;
1457 }
1458
1459 static int etnaviv_gpu_clk_enable(struct etnaviv_gpu *gpu)
1460 {
1461         int ret;
1462
1463         if (gpu->clk_bus) {
1464                 ret = clk_prepare_enable(gpu->clk_bus);
1465                 if (ret)
1466                         return ret;
1467         }
1468
1469         if (gpu->clk_core) {
1470                 ret = clk_prepare_enable(gpu->clk_core);
1471                 if (ret)
1472                         goto disable_clk_bus;
1473         }
1474
1475         if (gpu->clk_shader) {
1476                 ret = clk_prepare_enable(gpu->clk_shader);
1477                 if (ret)
1478                         goto disable_clk_core;
1479         }
1480
1481         return 0;
1482
1483 disable_clk_core:
1484         if (gpu->clk_core)
1485                 clk_disable_unprepare(gpu->clk_core);
1486 disable_clk_bus:
1487         if (gpu->clk_bus)
1488                 clk_disable_unprepare(gpu->clk_bus);
1489
1490         return ret;
1491 }
1492
1493 static int etnaviv_gpu_clk_disable(struct etnaviv_gpu *gpu)
1494 {
1495         if (gpu->clk_shader)
1496                 clk_disable_unprepare(gpu->clk_shader);
1497         if (gpu->clk_core)
1498                 clk_disable_unprepare(gpu->clk_core);
1499         if (gpu->clk_bus)
1500                 clk_disable_unprepare(gpu->clk_bus);
1501
1502         return 0;
1503 }
1504
1505 int etnaviv_gpu_wait_idle(struct etnaviv_gpu *gpu, unsigned int timeout_ms)
1506 {
1507         unsigned long timeout = jiffies + msecs_to_jiffies(timeout_ms);
1508
1509         do {
1510                 u32 idle = gpu_read(gpu, VIVS_HI_IDLE_STATE);
1511
1512                 if ((idle & gpu->idle_mask) == gpu->idle_mask)
1513                         return 0;
1514
1515                 if (time_is_before_jiffies(timeout)) {
1516                         dev_warn(gpu->dev,
1517                                  "timed out waiting for idle: idle=0x%x\n",
1518                                  idle);
1519                         return -ETIMEDOUT;
1520                 }
1521
1522                 udelay(5);
1523         } while (1);
1524 }
1525
1526 static int etnaviv_gpu_hw_suspend(struct etnaviv_gpu *gpu)
1527 {
1528         if (gpu->buffer) {
1529                 /* Replace the last WAIT with END */
1530                 etnaviv_buffer_end(gpu);
1531
1532                 /*
1533                  * We know that only the FE is busy here, this should
1534                  * happen quickly (as the WAIT is only 200 cycles).  If
1535                  * we fail, just warn and continue.
1536                  */
1537                 etnaviv_gpu_wait_idle(gpu, 100);
1538         }
1539
1540         return etnaviv_gpu_clk_disable(gpu);
1541 }
1542
1543 #ifdef CONFIG_PM
1544 static int etnaviv_gpu_hw_resume(struct etnaviv_gpu *gpu)
1545 {
1546         int ret;
1547
1548         ret = mutex_lock_killable(&gpu->lock);
1549         if (ret)
1550                 return ret;
1551
1552         etnaviv_gpu_update_clock(gpu);
1553         etnaviv_gpu_hw_init(gpu);
1554
1555         gpu->switch_context = true;
1556         gpu->exec_state = -1;
1557
1558         mutex_unlock(&gpu->lock);
1559
1560         return 0;
1561 }
1562 #endif
1563
1564 static int
1565 etnaviv_gpu_cooling_get_max_state(struct thermal_cooling_device *cdev,
1566                                   unsigned long *state)
1567 {
1568         *state = 6;
1569
1570         return 0;
1571 }
1572
1573 static int
1574 etnaviv_gpu_cooling_get_cur_state(struct thermal_cooling_device *cdev,
1575                                   unsigned long *state)
1576 {
1577         struct etnaviv_gpu *gpu = cdev->devdata;
1578
1579         *state = gpu->freq_scale;
1580
1581         return 0;
1582 }
1583
1584 static int
1585 etnaviv_gpu_cooling_set_cur_state(struct thermal_cooling_device *cdev,
1586                                   unsigned long state)
1587 {
1588         struct etnaviv_gpu *gpu = cdev->devdata;
1589
1590         mutex_lock(&gpu->lock);
1591         gpu->freq_scale = state;
1592         if (!pm_runtime_suspended(gpu->dev))
1593                 etnaviv_gpu_update_clock(gpu);
1594         mutex_unlock(&gpu->lock);
1595
1596         return 0;
1597 }
1598
1599 static struct thermal_cooling_device_ops cooling_ops = {
1600         .get_max_state = etnaviv_gpu_cooling_get_max_state,
1601         .get_cur_state = etnaviv_gpu_cooling_get_cur_state,
1602         .set_cur_state = etnaviv_gpu_cooling_set_cur_state,
1603 };
1604
1605 static int etnaviv_gpu_bind(struct device *dev, struct device *master,
1606         void *data)
1607 {
1608         struct drm_device *drm = data;
1609         struct etnaviv_drm_private *priv = drm->dev_private;
1610         struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1611         int ret;
1612
1613         gpu->cooling = thermal_of_cooling_device_register(dev->of_node,
1614                                 (char *)dev_name(dev), gpu, &cooling_ops);
1615         if (IS_ERR(gpu->cooling))
1616                 return PTR_ERR(gpu->cooling);
1617
1618 #ifdef CONFIG_PM
1619         ret = pm_runtime_get_sync(gpu->dev);
1620 #else
1621         ret = etnaviv_gpu_clk_enable(gpu);
1622 #endif
1623         if (ret < 0) {
1624                 thermal_cooling_device_unregister(gpu->cooling);
1625                 return ret;
1626         }
1627
1628         gpu->drm = drm;
1629         gpu->fence_context = dma_fence_context_alloc(1);
1630         spin_lock_init(&gpu->fence_spinlock);
1631
1632         INIT_LIST_HEAD(&gpu->active_cmd_list);
1633         INIT_WORK(&gpu->retire_work, retire_worker);
1634         INIT_WORK(&gpu->recover_work, recover_worker);
1635         init_waitqueue_head(&gpu->fence_event);
1636
1637         setup_deferrable_timer(&gpu->hangcheck_timer, hangcheck_handler,
1638                                (unsigned long)gpu);
1639
1640         priv->gpu[priv->num_gpus++] = gpu;
1641
1642         pm_runtime_mark_last_busy(gpu->dev);
1643         pm_runtime_put_autosuspend(gpu->dev);
1644
1645         return 0;
1646 }
1647
1648 static void etnaviv_gpu_unbind(struct device *dev, struct device *master,
1649         void *data)
1650 {
1651         struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1652
1653         DBG("%s", dev_name(gpu->dev));
1654
1655         hangcheck_disable(gpu);
1656
1657 #ifdef CONFIG_PM
1658         pm_runtime_get_sync(gpu->dev);
1659         pm_runtime_put_sync_suspend(gpu->dev);
1660 #else
1661         etnaviv_gpu_hw_suspend(gpu);
1662 #endif
1663
1664         if (gpu->buffer) {
1665                 etnaviv_cmdbuf_free(gpu->buffer);
1666                 gpu->buffer = NULL;
1667         }
1668
1669         if (gpu->cmdbuf_suballoc) {
1670                 etnaviv_cmdbuf_suballoc_destroy(gpu->cmdbuf_suballoc);
1671                 gpu->cmdbuf_suballoc = NULL;
1672         }
1673
1674         if (gpu->mmu) {
1675                 etnaviv_iommu_destroy(gpu->mmu);
1676                 gpu->mmu = NULL;
1677         }
1678
1679         gpu->drm = NULL;
1680
1681         thermal_cooling_device_unregister(gpu->cooling);
1682         gpu->cooling = NULL;
1683 }
1684
1685 static const struct component_ops gpu_ops = {
1686         .bind = etnaviv_gpu_bind,
1687         .unbind = etnaviv_gpu_unbind,
1688 };
1689
1690 static const struct of_device_id etnaviv_gpu_match[] = {
1691         {
1692                 .compatible = "vivante,gc"
1693         },
1694         { /* sentinel */ }
1695 };
1696
1697 static int etnaviv_gpu_platform_probe(struct platform_device *pdev)
1698 {
1699         struct device *dev = &pdev->dev;
1700         struct etnaviv_gpu *gpu;
1701         int err;
1702
1703         gpu = devm_kzalloc(dev, sizeof(*gpu), GFP_KERNEL);
1704         if (!gpu)
1705                 return -ENOMEM;
1706
1707         gpu->dev = &pdev->dev;
1708         mutex_init(&gpu->lock);
1709
1710         /* Map registers: */
1711         gpu->mmio = etnaviv_ioremap(pdev, NULL, dev_name(gpu->dev));
1712         if (IS_ERR(gpu->mmio))
1713                 return PTR_ERR(gpu->mmio);
1714
1715         /* Get Interrupt: */
1716         gpu->irq = platform_get_irq(pdev, 0);
1717         if (gpu->irq < 0) {
1718                 dev_err(dev, "failed to get irq: %d\n", gpu->irq);
1719                 return gpu->irq;
1720         }
1721
1722         err = devm_request_irq(&pdev->dev, gpu->irq, irq_handler, 0,
1723                                dev_name(gpu->dev), gpu);
1724         if (err) {
1725                 dev_err(dev, "failed to request IRQ%u: %d\n", gpu->irq, err);
1726                 return err;
1727         }
1728
1729         /* Get Clocks: */
1730         gpu->clk_bus = devm_clk_get(&pdev->dev, "bus");
1731         DBG("clk_bus: %p", gpu->clk_bus);
1732         if (IS_ERR(gpu->clk_bus))
1733                 gpu->clk_bus = NULL;
1734
1735         gpu->clk_core = devm_clk_get(&pdev->dev, "core");
1736         DBG("clk_core: %p", gpu->clk_core);
1737         if (IS_ERR(gpu->clk_core))
1738                 gpu->clk_core = NULL;
1739
1740         gpu->clk_shader = devm_clk_get(&pdev->dev, "shader");
1741         DBG("clk_shader: %p", gpu->clk_shader);
1742         if (IS_ERR(gpu->clk_shader))
1743                 gpu->clk_shader = NULL;
1744
1745         /* TODO: figure out max mapped size */
1746         dev_set_drvdata(dev, gpu);
1747
1748         /*
1749          * We treat the device as initially suspended.  The runtime PM
1750          * autosuspend delay is rather arbitary: no measurements have
1751          * yet been performed to determine an appropriate value.
1752          */
1753         pm_runtime_use_autosuspend(gpu->dev);
1754         pm_runtime_set_autosuspend_delay(gpu->dev, 200);
1755         pm_runtime_enable(gpu->dev);
1756
1757         err = component_add(&pdev->dev, &gpu_ops);
1758         if (err < 0) {
1759                 dev_err(&pdev->dev, "failed to register component: %d\n", err);
1760                 return err;
1761         }
1762
1763         return 0;
1764 }
1765
1766 static int etnaviv_gpu_platform_remove(struct platform_device *pdev)
1767 {
1768         component_del(&pdev->dev, &gpu_ops);
1769         pm_runtime_disable(&pdev->dev);
1770         return 0;
1771 }
1772
1773 #ifdef CONFIG_PM
1774 static int etnaviv_gpu_rpm_suspend(struct device *dev)
1775 {
1776         struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1777         u32 idle, mask;
1778
1779         /* If we have outstanding fences, we're not idle */
1780         if (gpu->completed_fence != gpu->active_fence)
1781                 return -EBUSY;
1782
1783         /* Check whether the hardware (except FE) is idle */
1784         mask = gpu->idle_mask & ~VIVS_HI_IDLE_STATE_FE;
1785         idle = gpu_read(gpu, VIVS_HI_IDLE_STATE) & mask;
1786         if (idle != mask)
1787                 return -EBUSY;
1788
1789         return etnaviv_gpu_hw_suspend(gpu);
1790 }
1791
1792 static int etnaviv_gpu_rpm_resume(struct device *dev)
1793 {
1794         struct etnaviv_gpu *gpu = dev_get_drvdata(dev);
1795         int ret;
1796
1797         ret = etnaviv_gpu_clk_enable(gpu);
1798         if (ret)
1799                 return ret;
1800
1801         /* Re-initialise the basic hardware state */
1802         if (gpu->drm && gpu->buffer) {
1803                 ret = etnaviv_gpu_hw_resume(gpu);
1804                 if (ret) {
1805                         etnaviv_gpu_clk_disable(gpu);
1806                         return ret;
1807                 }
1808         }
1809
1810         return 0;
1811 }
1812 #endif
1813
1814 static const struct dev_pm_ops etnaviv_gpu_pm_ops = {
1815         SET_RUNTIME_PM_OPS(etnaviv_gpu_rpm_suspend, etnaviv_gpu_rpm_resume,
1816                            NULL)
1817 };
1818
1819 struct platform_driver etnaviv_gpu_driver = {
1820         .driver = {
1821                 .name = "etnaviv-gpu",
1822                 .owner = THIS_MODULE,
1823                 .pm = &etnaviv_gpu_pm_ops,
1824                 .of_match_table = etnaviv_gpu_match,
1825         },
1826         .probe = etnaviv_gpu_platform_probe,
1827         .remove = etnaviv_gpu_platform_remove,
1828         .id_table = gpu_ids,
1829 };