drivers/gpu/drm/exynos/exynos5433_drm_decon.c

   1 /* drivers/gpu/drm/exynos5433_drm_decon.c
   2  *
   3  * Copyright (C) 2015 Samsung Electronics Co.Ltd
   4  * Authors:
   5  *      Joonyoung Shim <jy0922.shim@samsung.com>
   6  *      Hyungwon Hwang <human.hwang@samsung.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundationr
  11  */
  12
  13 #include <linux/platform_device.h>
  14 #include <linux/clk.h>
  15 #include <linux/component.h>
  16 #include <linux/mfd/syscon.h>
  17 #include <linux/of_device.h>
  18 #include <linux/of_gpio.h>
  19 #include <linux/pm_runtime.h>
  20 #include <linux/regmap.h>
  21
  22 #include <video/exynos5433_decon.h>
  23
  24 #include "exynos_drm_drv.h"
  25 #include "exynos_drm_crtc.h"
  26 #include "exynos_drm_fb.h"
  27 #include "exynos_drm_plane.h"
  28 #include "exynos_drm_iommu.h"
  29
  30 #define DSD_CFG_MUX 0x1004
  31 #define DSD_CFG_MUX_TE_UNMASK_GLOBAL BIT(13)
  32
  33 #define WINDOWS_NR      3
  34 #define MIN_FB_WIDTH_FOR_16WORD_BURST   128
  35
  36 #define IFTYPE_I80      (1 << 0)
  37 #define I80_HW_TRG      (1 << 1)
  38 #define IFTYPE_HDMI     (1 << 2)
  39
  40 static const char * const decon_clks_name[] = {
  41         "pclk",
  42         "aclk_decon",
  43         "aclk_smmu_decon0x",
  44         "aclk_xiu_decon0x",
  45         "pclk_smmu_decon0x",
  46         "sclk_decon_vclk",
  47         "sclk_decon_eclk",
  48 };
  49
  50 enum decon_flag_bits {
  51         BIT_CLKS_ENABLED,
  52         BIT_WIN_UPDATED,
  53         BIT_SUSPENDED
  54 };
  55
  56 struct decon_context {
  57         struct device                   *dev;
  58         struct drm_device               *drm_dev;
  59         struct exynos_drm_crtc          *crtc;
  60         struct exynos_drm_plane         planes[WINDOWS_NR];
  61         struct exynos_drm_plane_config  configs[WINDOWS_NR];
  62         void __iomem                    *addr;
  63         struct regmap                   *sysreg;
  64         struct clk                      *clks[ARRAY_SIZE(decon_clks_name)];
  65         unsigned long                   flags;
  66         unsigned long                   out_type;
  67         int                             first_win;
  68         spinlock_t                      vblank_lock;
  69         u32                             frame_id;
  70 };
  71
  72 static const uint32_t decon_formats[] = {
  73         DRM_FORMAT_XRGB1555,
  74         DRM_FORMAT_RGB565,
  75         DRM_FORMAT_XRGB8888,
  76         DRM_FORMAT_ARGB8888,
  77 };
  78
  79 static const enum drm_plane_type decon_win_types[WINDOWS_NR] = {
  80         DRM_PLANE_TYPE_PRIMARY,
  81         DRM_PLANE_TYPE_OVERLAY,
  82         DRM_PLANE_TYPE_CURSOR,
  83 };
  84
  85 static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask,
  86                                   u32 val)
  87 {
  88         val = (val & mask) | (readl(ctx->addr + reg) & ~mask);
  89         writel(val, ctx->addr + reg);
  90 }
  91
  92 static int decon_enable_vblank(struct exynos_drm_crtc *crtc)
  93 {
  94         struct decon_context *ctx = crtc->ctx;
  95         u32 val;
  96
  97         if (test_bit(BIT_SUSPENDED, &ctx->flags))
  98                 return -EPERM;
  99
 100         val = VIDINTCON0_INTEN;
 101         if (ctx->out_type & IFTYPE_I80)
 102                 val |= VIDINTCON0_FRAMEDONE;
 103         else
 104                 val |= VIDINTCON0_INTFRMEN | VIDINTCON0_FRAMESEL_FP;
 105
 106         writel(val, ctx->addr + DECON_VIDINTCON0);
 107
 108         return 0;
 109 }
 110
 111 static void decon_disable_vblank(struct exynos_drm_crtc *crtc)
 112 {
 113         struct decon_context *ctx = crtc->ctx;
 114
 115         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 116                 return;
 117
 118         writel(0, ctx->addr + DECON_VIDINTCON0);
 119 }
 120
 121 /* return number of starts/ends of frame transmissions since reset */
 122 static u32 decon_get_frame_count(struct decon_context *ctx, bool end)
 123 {
 124         u32 frm, pfrm, status, cnt = 2;
 125
 126         /* To get consistent result repeat read until frame id is stable.
 127          * Usually the loop will be executed once, in rare cases when the loop
 128          * is executed at frame change time 2nd pass will be needed.
 129          */
 130         frm = readl(ctx->addr + DECON_CRFMID);
 131         do {
 132                 status = readl(ctx->addr + DECON_VIDCON1);
 133                 pfrm = frm;
 134                 frm = readl(ctx->addr + DECON_CRFMID);
 135         } while (frm != pfrm && --cnt);
 136
 137         /* CRFMID is incremented on BPORCH in case of I80 and on VSYNC in case
 138          * of RGB, it should be taken into account.
 139          */
 140         if (!frm)
 141                 return 0;
 142
 143         switch (status & (VIDCON1_VSTATUS_MASK | VIDCON1_I80_ACTIVE)) {
 144         case VIDCON1_VSTATUS_VS:
 145                 if (!(ctx->out_type & IFTYPE_I80))
 146                         --frm;
 147                 break;
 148         case VIDCON1_VSTATUS_BP:
 149                 --frm;
 150                 break;
 151         case VIDCON1_I80_ACTIVE:
 152         case VIDCON1_VSTATUS_AC:
 153                 if (end)
 154                         --frm;
 155                 break;
 156         default:
 157                 break;
 158         }
 159
 160         return frm;
 161 }
 162
 163 static u32 decon_get_vblank_counter(struct exynos_drm_crtc *crtc)
 164 {
 165         struct decon_context *ctx = crtc->ctx;
 166
 167         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 168                 return 0;
 169
 170         return decon_get_frame_count(ctx, false);
 171 }
 172
 173 static void decon_setup_trigger(struct decon_context *ctx)
 174 {
 175         if (!(ctx->out_type & (IFTYPE_I80 | I80_HW_TRG)))
 176                 return;
 177
 178         if (!(ctx->out_type & I80_HW_TRG)) {
 179                 writel(TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
 180                        TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN,
 181                        ctx->addr + DECON_TRIGCON);
 182                 return;
 183         }
 184
 185         writel(TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F | TRIGCON_HWTRIGMASK
 186                | TRIGCON_HWTRIGEN, ctx->addr + DECON_TRIGCON);
 187
 188         if (regmap_update_bits(ctx->sysreg, DSD_CFG_MUX,
 189                                DSD_CFG_MUX_TE_UNMASK_GLOBAL, ~0))
 190                 DRM_ERROR("Cannot update sysreg.\n");
 191 }
 192
 193 static void decon_commit(struct exynos_drm_crtc *crtc)
 194 {
 195         struct decon_context *ctx = crtc->ctx;
 196         struct drm_display_mode *m = &crtc->base.mode;
 197         bool interlaced = false;
 198         u32 val;
 199
 200         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 201                 return;
 202
 203         if (ctx->out_type & IFTYPE_HDMI) {
 204                 m->crtc_hsync_start = m->crtc_hdisplay + 10;
 205                 m->crtc_hsync_end = m->crtc_htotal - 92;
 206                 m->crtc_vsync_start = m->crtc_vdisplay + 1;
 207                 m->crtc_vsync_end = m->crtc_vsync_start + 1;
 208                 if (m->flags & DRM_MODE_FLAG_INTERLACE)
 209                         interlaced = true;
 210         }
 211
 212         decon_setup_trigger(ctx);
 213
 214         /* lcd on and use command if */
 215         val = VIDOUT_LCD_ON;
 216         if (interlaced)
 217                 val |= VIDOUT_INTERLACE_EN_F;
 218         if (ctx->out_type & IFTYPE_I80) {
 219                 val |= VIDOUT_COMMAND_IF;
 220         } else {
 221                 val |= VIDOUT_RGB_IF;
 222         }
 223
 224         writel(val, ctx->addr + DECON_VIDOUTCON0);
 225
 226         if (interlaced)
 227                 val = VIDTCON2_LINEVAL(m->vdisplay / 2 - 1) |
 228                         VIDTCON2_HOZVAL(m->hdisplay - 1);
 229         else
 230                 val = VIDTCON2_LINEVAL(m->vdisplay - 1) |
 231                         VIDTCON2_HOZVAL(m->hdisplay - 1);
 232         writel(val, ctx->addr + DECON_VIDTCON2);
 233
 234         if (!(ctx->out_type & IFTYPE_I80)) {
 235                 int vbp = m->crtc_vtotal - m->crtc_vsync_end;
 236                 int vfp = m->crtc_vsync_start - m->crtc_vdisplay;
 237
 238                 if (interlaced)
 239                         vbp = vbp / 2 - 1;
 240                 val = VIDTCON00_VBPD_F(vbp - 1) | VIDTCON00_VFPD_F(vfp - 1);
 241                 writel(val, ctx->addr + DECON_VIDTCON00);
 242
 243                 val = VIDTCON01_VSPW_F(
 244                                 m->crtc_vsync_end - m->crtc_vsync_start - 1);
 245                 writel(val, ctx->addr + DECON_VIDTCON01);
 246
 247                 val = VIDTCON10_HBPD_F(
 248                                 m->crtc_htotal - m->crtc_hsync_end - 1) |
 249                         VIDTCON10_HFPD_F(
 250                                 m->crtc_hsync_start - m->crtc_hdisplay - 1);
 251                 writel(val, ctx->addr + DECON_VIDTCON10);
 252
 253                 val = VIDTCON11_HSPW_F(
 254                                 m->crtc_hsync_end - m->crtc_hsync_start - 1);
 255                 writel(val, ctx->addr + DECON_VIDTCON11);
 256         }
 257
 258         /* enable output and display signal */
 259         decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID | VIDCON0_ENVID_F, ~0);
 260
 261         decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
 262 }
 263
 264 static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win,
 265                                  struct drm_framebuffer *fb)
 266 {
 267         unsigned long val;
 268
 269         val = readl(ctx->addr + DECON_WINCONx(win));
 270         val &= ~WINCONx_BPPMODE_MASK;
 271
 272         switch (fb->format->format) {
 273         case DRM_FORMAT_XRGB1555:
 274                 val |= WINCONx_BPPMODE_16BPP_I1555;
 275                 val |= WINCONx_HAWSWP_F;
 276                 val |= WINCONx_BURSTLEN_16WORD;
 277                 break;
 278         case DRM_FORMAT_RGB565:
 279                 val |= WINCONx_BPPMODE_16BPP_565;
 280                 val |= WINCONx_HAWSWP_F;
 281                 val |= WINCONx_BURSTLEN_16WORD;
 282                 break;
 283         case DRM_FORMAT_XRGB8888:
 284                 val |= WINCONx_BPPMODE_24BPP_888;
 285                 val |= WINCONx_WSWP_F;
 286                 val |= WINCONx_BURSTLEN_16WORD;
 287                 break;
 288         case DRM_FORMAT_ARGB8888:
 289                 val |= WINCONx_BPPMODE_32BPP_A8888;
 290                 val |= WINCONx_WSWP_F | WINCONx_BLD_PIX_F | WINCONx_ALPHA_SEL_F;
 291                 val |= WINCONx_BURSTLEN_16WORD;
 292                 break;
 293         default:
 294                 DRM_ERROR("Proper pixel format is not set\n");
 295                 return;
 296         }
 297
 298         DRM_DEBUG_KMS("bpp = %u\n", fb->format->cpp[0] * 8);
 299
 300         /*
 301          * In case of exynos, setting dma-burst to 16Word causes permanent
 302          * tearing for very small buffers, e.g. cursor buffer. Burst Mode
 303          * switching which is based on plane size is not recommended as
 304          * plane size varies a lot towards the end of the screen and rapid
 305          * movement causes unstable DMA which results into iommu crash/tear.
 306          */
 307
 308         if (fb->width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
 309                 val &= ~WINCONx_BURSTLEN_MASK;
 310                 val |= WINCONx_BURSTLEN_8WORD;
 311         }
 312
 313         writel(val, ctx->addr + DECON_WINCONx(win));
 314 }
 315
 316 static void decon_shadow_protect_win(struct decon_context *ctx, int win,
 317                                         bool protect)
 318 {
 319         decon_set_bits(ctx, DECON_SHADOWCON, SHADOWCON_Wx_PROTECT(win),
 320                        protect ? ~0 : 0);
 321 }
 322
 323 static void decon_atomic_begin(struct exynos_drm_crtc *crtc)
 324 {
 325         struct decon_context *ctx = crtc->ctx;
 326         int i;
 327
 328         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 329                 return;
 330
 331         for (i = ctx->first_win; i < WINDOWS_NR; i++)
 332                 decon_shadow_protect_win(ctx, i, true);
 333 }
 334
 335 #define BIT_VAL(x, e, s) (((x) & ((1 << ((e) - (s) + 1)) - 1)) << (s))
 336 #define COORDINATE_X(x) BIT_VAL((x), 23, 12)
 337 #define COORDINATE_Y(x) BIT_VAL((x), 11, 0)
 338
 339 static void decon_update_plane(struct exynos_drm_crtc *crtc,
 340                                struct exynos_drm_plane *plane)
 341 {
 342         struct exynos_drm_plane_state *state =
 343                                 to_exynos_plane_state(plane->base.state);
 344         struct decon_context *ctx = crtc->ctx;
 345         struct drm_framebuffer *fb = state->base.fb;
 346         unsigned int win = plane->index;
 347         unsigned int bpp = fb->format->cpp[0];
 348         unsigned int pitch = fb->pitches[0];
 349         dma_addr_t dma_addr = exynos_drm_fb_dma_addr(fb, 0);
 350         u32 val;
 351
 352         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 353                 return;
 354
 355         if (crtc->base.mode.flags & DRM_MODE_FLAG_INTERLACE) {
 356                 val = COORDINATE_X(state->crtc.x) |
 357                         COORDINATE_Y(state->crtc.y / 2);
 358                 writel(val, ctx->addr + DECON_VIDOSDxA(win));
 359
 360                 val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) |
 361                         COORDINATE_Y((state->crtc.y + state->crtc.h) / 2 - 1);
 362                 writel(val, ctx->addr + DECON_VIDOSDxB(win));
 363         } else {
 364                 val = COORDINATE_X(state->crtc.x) | COORDINATE_Y(state->crtc.y);
 365                 writel(val, ctx->addr + DECON_VIDOSDxA(win));
 366
 367                 val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) |
 368                                 COORDINATE_Y(state->crtc.y + state->crtc.h - 1);
 369                 writel(val, ctx->addr + DECON_VIDOSDxB(win));
 370         }
 371
 372         val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) |
 373                 VIDOSD_Wx_ALPHA_B_F(0x0);
 374         writel(val, ctx->addr + DECON_VIDOSDxC(win));
 375
 376         val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) |
 377                 VIDOSD_Wx_ALPHA_B_F(0x0);
 378         writel(val, ctx->addr + DECON_VIDOSDxD(win));
 379
 380         writel(dma_addr, ctx->addr + DECON_VIDW0xADD0B0(win));
 381
 382         val = dma_addr + pitch * state->src.h;
 383         writel(val, ctx->addr + DECON_VIDW0xADD1B0(win));
 384
 385         if (!(ctx->out_type & IFTYPE_HDMI))
 386                 val = BIT_VAL(pitch - state->crtc.w * bpp, 27, 14)
 387                         | BIT_VAL(state->crtc.w * bpp, 13, 0);
 388         else
 389                 val = BIT_VAL(pitch - state->crtc.w * bpp, 29, 15)
 390                         | BIT_VAL(state->crtc.w * bpp, 14, 0);
 391         writel(val, ctx->addr + DECON_VIDW0xADD2(win));
 392
 393         decon_win_set_pixfmt(ctx, win, fb);
 394
 395         /* window enable */
 396         decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, ~0);
 397 }
 398
 399 static void decon_disable_plane(struct exynos_drm_crtc *crtc,
 400                                 struct exynos_drm_plane *plane)
 401 {
 402         struct decon_context *ctx = crtc->ctx;
 403         unsigned int win = plane->index;
 404
 405         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 406                 return;
 407
 408         decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
 409 }
 410
 411 static void decon_atomic_flush(struct exynos_drm_crtc *crtc)
 412 {
 413         struct decon_context *ctx = crtc->ctx;
 414         unsigned long flags;
 415         int i;
 416
 417         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 418                 return;
 419
 420         spin_lock_irqsave(&ctx->vblank_lock, flags);
 421
 422         for (i = ctx->first_win; i < WINDOWS_NR; i++)
 423                 decon_shadow_protect_win(ctx, i, false);
 424
 425         decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
 426
 427         if (ctx->out_type & IFTYPE_I80)
 428                 set_bit(BIT_WIN_UPDATED, &ctx->flags);
 429
 430         ctx->frame_id = decon_get_frame_count(ctx, true);
 431
 432         exynos_crtc_handle_event(crtc);
 433
 434         spin_unlock_irqrestore(&ctx->vblank_lock, flags);
 435 }
 436
 437 static void decon_swreset(struct decon_context *ctx)
 438 {
 439         unsigned int tries;
 440         unsigned long flags;
 441
 442         writel(0, ctx->addr + DECON_VIDCON0);
 443         for (tries = 2000; tries; --tries) {
 444                 if (~readl(ctx->addr + DECON_VIDCON0) & VIDCON0_STOP_STATUS)
 445                         break;
 446                 udelay(10);
 447         }
 448
 449         writel(VIDCON0_SWRESET, ctx->addr + DECON_VIDCON0);
 450         for (tries = 2000; tries; --tries) {
 451                 if (~readl(ctx->addr + DECON_VIDCON0) & VIDCON0_SWRESET)
 452                         break;
 453                 udelay(10);
 454         }
 455
 456         WARN(tries == 0, "failed to software reset DECON\n");
 457
 458         spin_lock_irqsave(&ctx->vblank_lock, flags);
 459         ctx->frame_id = 0;
 460         spin_unlock_irqrestore(&ctx->vblank_lock, flags);
 461
 462         if (!(ctx->out_type & IFTYPE_HDMI))
 463                 return;
 464
 465         writel(VIDCON0_CLKVALUP | VIDCON0_VLCKFREE, ctx->addr + DECON_VIDCON0);
 466         decon_set_bits(ctx, DECON_CMU,
 467                        CMU_CLKGAGE_MODE_SFR_F | CMU_CLKGAGE_MODE_MEM_F, ~0);
 468         writel(VIDCON1_VCLK_RUN_VDEN_DISABLE, ctx->addr + DECON_VIDCON1);
 469         writel(CRCCTRL_CRCEN | CRCCTRL_CRCSTART_F | CRCCTRL_CRCCLKEN,
 470                ctx->addr + DECON_CRCCTRL);
 471 }
 472
 473 static void decon_enable(struct exynos_drm_crtc *crtc)
 474 {
 475         struct decon_context *ctx = crtc->ctx;
 476
 477         if (!test_and_clear_bit(BIT_SUSPENDED, &ctx->flags))
 478                 return;
 479
 480         pm_runtime_get_sync(ctx->dev);
 481
 482         exynos_drm_pipe_clk_enable(crtc, true);
 483
 484         set_bit(BIT_CLKS_ENABLED, &ctx->flags);
 485
 486         decon_swreset(ctx);
 487
 488         decon_commit(ctx->crtc);
 489 }
 490
 491 static void decon_disable(struct exynos_drm_crtc *crtc)
 492 {
 493         struct decon_context *ctx = crtc->ctx;
 494         int i;
 495
 496         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 497                 return;
 498
 499         /*
 500          * We need to make sure that all windows are disabled before we
 501          * suspend that connector. Otherwise we might try to scan from
 502          * a destroyed buffer later.
 503          */
 504         for (i = ctx->first_win; i < WINDOWS_NR; i++)
 505                 decon_disable_plane(crtc, &ctx->planes[i]);
 506
 507         decon_swreset(ctx);
 508
 509         clear_bit(BIT_CLKS_ENABLED, &ctx->flags);
 510
 511         exynos_drm_pipe_clk_enable(crtc, false);
 512
 513         pm_runtime_put_sync(ctx->dev);
 514
 515         set_bit(BIT_SUSPENDED, &ctx->flags);
 516 }
 517
 518 static void decon_te_irq_handler(struct exynos_drm_crtc *crtc)
 519 {
 520         struct decon_context *ctx = crtc->ctx;
 521
 522         if (!test_bit(BIT_CLKS_ENABLED, &ctx->flags) ||
 523             (ctx->out_type & I80_HW_TRG))
 524                 return;
 525
 526         if (test_and_clear_bit(BIT_WIN_UPDATED, &ctx->flags))
 527                 decon_set_bits(ctx, DECON_TRIGCON, TRIGCON_SWTRIGCMD, ~0);
 528 }
 529
 530 static void decon_clear_channels(struct exynos_drm_crtc *crtc)
 531 {
 532         struct decon_context *ctx = crtc->ctx;
 533         int win, i, ret;
 534
 535         DRM_DEBUG_KMS("%s\n", __FILE__);
 536
 537         for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
 538                 ret = clk_prepare_enable(ctx->clks[i]);
 539                 if (ret < 0)
 540                         goto err;
 541         }
 542
 543         for (win = 0; win < WINDOWS_NR; win++) {
 544                 decon_shadow_protect_win(ctx, win, true);
 545                 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
 546                 decon_shadow_protect_win(ctx, win, false);
 547         }
 548
 549         decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
 550
 551         /* TODO: wait for possible vsync */
 552         msleep(50);
 553
 554 err:
 555         while (--i >= 0)
 556                 clk_disable_unprepare(ctx->clks[i]);
 557 }
 558
 559 static const struct exynos_drm_crtc_ops decon_crtc_ops = {
 560         .enable                 = decon_enable,
 561         .disable                = decon_disable,
 562         .enable_vblank          = decon_enable_vblank,
 563         .disable_vblank         = decon_disable_vblank,
 564         .get_vblank_counter     = decon_get_vblank_counter,
 565         .atomic_begin           = decon_atomic_begin,
 566         .update_plane           = decon_update_plane,
 567         .disable_plane          = decon_disable_plane,
 568         .atomic_flush           = decon_atomic_flush,
 569         .te_handler             = decon_te_irq_handler,
 570 };
 571
 572 static int decon_bind(struct device *dev, struct device *master, void *data)
 573 {
 574         struct decon_context *ctx = dev_get_drvdata(dev);
 575         struct drm_device *drm_dev = data;
 576         struct exynos_drm_plane *exynos_plane;
 577         enum exynos_drm_output_type out_type;
 578         unsigned int win;
 579         int ret;
 580
 581         ctx->drm_dev = drm_dev;
 582         drm_dev->max_vblank_count = 0xffffffff;
 583
 584         for (win = ctx->first_win; win < WINDOWS_NR; win++) {
 585                 int tmp = (win == ctx->first_win) ? 0 : win;
 586
 587                 ctx->configs[win].pixel_formats = decon_formats;
 588                 ctx->configs[win].num_pixel_formats = ARRAY_SIZE(decon_formats);
 589                 ctx->configs[win].zpos = win;
 590                 ctx->configs[win].type = decon_win_types[tmp];
 591
 592                 ret = exynos_plane_init(drm_dev, &ctx->planes[win], win,
 593                                         &ctx->configs[win]);
 594                 if (ret)
 595                         return ret;
 596         }
 597
 598         exynos_plane = &ctx->planes[ctx->first_win];
 599         out_type = (ctx->out_type & IFTYPE_HDMI) ? EXYNOS_DISPLAY_TYPE_HDMI
 600                                                   : EXYNOS_DISPLAY_TYPE_LCD;
 601         ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
 602                         out_type, &decon_crtc_ops, ctx);
 603         if (IS_ERR(ctx->crtc))
 604                 return PTR_ERR(ctx->crtc);
 605
 606         decon_clear_channels(ctx->crtc);
 607
 608         return drm_iommu_attach_device(drm_dev, dev);
 609 }
 610
 611 static void decon_unbind(struct device *dev, struct device *master, void *data)
 612 {
 613         struct decon_context *ctx = dev_get_drvdata(dev);
 614
 615         decon_disable(ctx->crtc);
 616
 617         /* detach this sub driver from iommu mapping if supported. */
 618         drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
 619 }
 620
 621 static const struct component_ops decon_component_ops = {
 622         .bind   = decon_bind,
 623         .unbind = decon_unbind,
 624 };
 625
 626 static void decon_handle_vblank(struct decon_context *ctx)
 627 {
 628         u32 frm;
 629
 630         spin_lock(&ctx->vblank_lock);
 631
 632         frm = decon_get_frame_count(ctx, true);
 633
 634         if (frm != ctx->frame_id) {
 635                 /* handle only if incremented, take care of wrap-around */
 636                 if ((s32)(frm - ctx->frame_id) > 0)
 637                         drm_crtc_handle_vblank(&ctx->crtc->base);
 638                 ctx->frame_id = frm;
 639         }
 640
 641         spin_unlock(&ctx->vblank_lock);
 642 }
 643
 644 static irqreturn_t decon_irq_handler(int irq, void *dev_id)
 645 {
 646         struct decon_context *ctx = dev_id;
 647         u32 val;
 648
 649         if (!test_bit(BIT_CLKS_ENABLED, &ctx->flags))
 650                 goto out;
 651
 652         val = readl(ctx->addr + DECON_VIDINTCON1);
 653         val &= VIDINTCON1_INTFRMDONEPEND | VIDINTCON1_INTFRMPEND;
 654
 655         if (val) {
 656                 writel(val, ctx->addr + DECON_VIDINTCON1);
 657                 if (ctx->out_type & IFTYPE_HDMI) {
 658                         val = readl(ctx->addr + DECON_VIDOUTCON0);
 659                         val &= VIDOUT_INTERLACE_EN_F | VIDOUT_INTERLACE_FIELD_F;
 660                         if (val ==
 661                             (VIDOUT_INTERLACE_EN_F | VIDOUT_INTERLACE_FIELD_F))
 662                                 return IRQ_HANDLED;
 663                 }
 664                 decon_handle_vblank(ctx);
 665         }
 666
 667 out:
 668         return IRQ_HANDLED;
 669 }
 670
 671 #ifdef CONFIG_PM
 672 static int exynos5433_decon_suspend(struct device *dev)
 673 {
 674         struct decon_context *ctx = dev_get_drvdata(dev);
 675         int i = ARRAY_SIZE(decon_clks_name);
 676
 677         while (--i >= 0)
 678                 clk_disable_unprepare(ctx->clks[i]);
 679
 680         return 0;
 681 }
 682
 683 static int exynos5433_decon_resume(struct device *dev)
 684 {
 685         struct decon_context *ctx = dev_get_drvdata(dev);
 686         int i, ret;
 687
 688         for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
 689                 ret = clk_prepare_enable(ctx->clks[i]);
 690                 if (ret < 0)
 691                         goto err;
 692         }
 693
 694         return 0;
 695
 696 err:
 697         while (--i >= 0)
 698                 clk_disable_unprepare(ctx->clks[i]);
 699
 700         return ret;
 701 }
 702 #endif
 703
 704 static const struct dev_pm_ops exynos5433_decon_pm_ops = {
 705         SET_RUNTIME_PM_OPS(exynos5433_decon_suspend, exynos5433_decon_resume,
 706                            NULL)
 707 };
 708
 709 static const struct of_device_id exynos5433_decon_driver_dt_match[] = {
 710         {
 711                 .compatible = "samsung,exynos5433-decon",
 712                 .data = (void *)I80_HW_TRG
 713         },
 714         {
 715                 .compatible = "samsung,exynos5433-decon-tv",
 716                 .data = (void *)(I80_HW_TRG | IFTYPE_HDMI)
 717         },
 718         {},
 719 };
 720 MODULE_DEVICE_TABLE(of, exynos5433_decon_driver_dt_match);
 721
 722 static int exynos5433_decon_probe(struct platform_device *pdev)
 723 {
 724         struct device *dev = &pdev->dev;
 725         struct decon_context *ctx;
 726         struct resource *res;
 727         int ret;
 728         int i;
 729
 730         ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
 731         if (!ctx)
 732                 return -ENOMEM;
 733
 734         __set_bit(BIT_SUSPENDED, &ctx->flags);
 735         ctx->dev = dev;
 736         ctx->out_type = (unsigned long)of_device_get_match_data(dev);
 737         spin_lock_init(&ctx->vblank_lock);
 738
 739         if (ctx->out_type & IFTYPE_HDMI) {
 740                 ctx->first_win = 1;
 741         } else if (of_get_child_by_name(dev->of_node, "i80-if-timings")) {
 742                 ctx->out_type |= IFTYPE_I80;
 743         }
 744
 745         if (ctx->out_type & I80_HW_TRG) {
 746                 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
 747                                                         "samsung,disp-sysreg");
 748                 if (IS_ERR(ctx->sysreg)) {
 749                         dev_err(dev, "failed to get system register\n");
 750                         return PTR_ERR(ctx->sysreg);
 751                 }
 752         }
 753
 754         for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
 755                 struct clk *clk;
 756
 757                 clk = devm_clk_get(ctx->dev, decon_clks_name[i]);
 758                 if (IS_ERR(clk))
 759                         return PTR_ERR(clk);
 760
 761                 ctx->clks[i] = clk;
 762         }
 763
 764         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 765         if (!res) {
 766                 dev_err(dev, "cannot find IO resource\n");
 767                 return -ENXIO;
 768         }
 769
 770         ctx->addr = devm_ioremap_resource(dev, res);
 771         if (IS_ERR(ctx->addr)) {
 772                 dev_err(dev, "ioremap failed\n");
 773                 return PTR_ERR(ctx->addr);
 774         }
 775
 776         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
 777                         (ctx->out_type & IFTYPE_I80) ? "lcd_sys" : "vsync");
 778         if (!res) {
 779                 dev_err(dev, "cannot find IRQ resource\n");
 780                 return -ENXIO;
 781         }
 782
 783         ret = devm_request_irq(dev, res->start, decon_irq_handler, 0,
 784                                "drm_decon", ctx);
 785         if (ret < 0) {
 786                 dev_err(dev, "lcd_sys irq request failed\n");
 787                 return ret;
 788         }
 789
 790         platform_set_drvdata(pdev, ctx);
 791
 792         pm_runtime_enable(dev);
 793
 794         ret = component_add(dev, &decon_component_ops);
 795         if (ret)
 796                 goto err_disable_pm_runtime;
 797
 798         return 0;
 799
 800 err_disable_pm_runtime:
 801         pm_runtime_disable(dev);
 802
 803         return ret;
 804 }
 805
 806 static int exynos5433_decon_remove(struct platform_device *pdev)
 807 {
 808         pm_runtime_disable(&pdev->dev);
 809
 810         component_del(&pdev->dev, &decon_component_ops);
 811
 812         return 0;
 813 }
 814
 815 struct platform_driver exynos5433_decon_driver = {
 816         .probe          = exynos5433_decon_probe,
 817         .remove         = exynos5433_decon_remove,
 818         .driver         = {
 819                 .name   = "exynos5433-decon",
 820                 .pm     = &exynos5433_decon_pm_ops,
 821                 .of_match_table = exynos5433_decon_driver_dt_match,
 822         },
 823 };