drivers/gpu/drm/exynos/exynos5433_drm_decon.c

   1 /* drivers/gpu/drm/exynos5433_drm_decon.c
   2  *
   3  * Copyright (C) 2015 Samsung Electronics Co.Ltd
   4  * Authors:
   5  *      Joonyoung Shim <jy0922.shim@samsung.com>
   6  *      Hyungwon Hwang <human.hwang@samsung.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundationr
  11  */
  12
  13 #include <linux/platform_device.h>
  14 #include <linux/clk.h>
  15 #include <linux/component.h>
  16 #include <linux/of_device.h>
  17 #include <linux/of_gpio.h>
  18 #include <linux/pm_runtime.h>
  19
  20 #include <video/exynos5433_decon.h>
  21
  22 #include "exynos_drm_drv.h"
  23 #include "exynos_drm_crtc.h"
  24 #include "exynos_drm_fb.h"
  25 #include "exynos_drm_plane.h"
  26 #include "exynos_drm_iommu.h"
  27
  28 #define WINDOWS_NR      3
  29 #define MIN_FB_WIDTH_FOR_16WORD_BURST   128
  30
  31 #define IFTYPE_I80      (1 << 0)
  32 #define I80_HW_TRG      (1 << 1)
  33 #define IFTYPE_HDMI     (1 << 2)
  34
  35 static const char * const decon_clks_name[] = {
  36         "pclk",
  37         "aclk_decon",
  38         "aclk_smmu_decon0x",
  39         "aclk_xiu_decon0x",
  40         "pclk_smmu_decon0x",
  41         "sclk_decon_vclk",
  42         "sclk_decon_eclk",
  43 };
  44
  45 enum decon_flag_bits {
  46         BIT_CLKS_ENABLED,
  47         BIT_IRQS_ENABLED,
  48         BIT_WIN_UPDATED,
  49         BIT_SUSPENDED
  50 };
  51
  52 struct decon_context {
  53         struct device                   *dev;
  54         struct drm_device               *drm_dev;
  55         struct exynos_drm_crtc          *crtc;
  56         struct exynos_drm_plane         planes[WINDOWS_NR];
  57         struct exynos_drm_plane_config  configs[WINDOWS_NR];
  58         void __iomem                    *addr;
  59         struct clk                      *clks[ARRAY_SIZE(decon_clks_name)];
  60         int                             pipe;
  61         unsigned long                   flags;
  62         unsigned long                   out_type;
  63         int                             first_win;
  64 };
  65
  66 static const uint32_t decon_formats[] = {
  67         DRM_FORMAT_XRGB1555,
  68         DRM_FORMAT_RGB565,
  69         DRM_FORMAT_XRGB8888,
  70         DRM_FORMAT_ARGB8888,
  71 };
  72
  73 static const enum drm_plane_type decon_win_types[WINDOWS_NR] = {
  74         DRM_PLANE_TYPE_PRIMARY,
  75         DRM_PLANE_TYPE_OVERLAY,
  76         DRM_PLANE_TYPE_CURSOR,
  77 };
  78
  79 static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask,
  80                                   u32 val)
  81 {
  82         val = (val & mask) | (readl(ctx->addr + reg) & ~mask);
  83         writel(val, ctx->addr + reg);
  84 }
  85
  86 static int decon_enable_vblank(struct exynos_drm_crtc *crtc)
  87 {
  88         struct decon_context *ctx = crtc->ctx;
  89         u32 val;
  90
  91         if (test_bit(BIT_SUSPENDED, &ctx->flags))
  92                 return -EPERM;
  93
  94         if (!test_and_set_bit(BIT_IRQS_ENABLED, &ctx->flags)) {
  95                 val = VIDINTCON0_INTEN;
  96                 if (ctx->out_type & IFTYPE_I80)
  97                         val |= VIDINTCON0_FRAMEDONE;
  98                 else
  99                         val |= VIDINTCON0_INTFRMEN;
 100
 101                 writel(val, ctx->addr + DECON_VIDINTCON0);
 102         }
 103
 104         return 0;
 105 }
 106
 107 static void decon_disable_vblank(struct exynos_drm_crtc *crtc)
 108 {
 109         struct decon_context *ctx = crtc->ctx;
 110
 111         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 112                 return;
 113
 114         if (test_and_clear_bit(BIT_IRQS_ENABLED, &ctx->flags))
 115                 writel(0, ctx->addr + DECON_VIDINTCON0);
 116 }
 117
 118 static void decon_setup_trigger(struct decon_context *ctx)
 119 {
 120         u32 val = !(ctx->out_type & I80_HW_TRG)
 121                 ? TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
 122                   TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN
 123                 : TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
 124                   TRIGCON_HWTRIGMASK | TRIGCON_HWTRIGEN;
 125         writel(val, ctx->addr + DECON_TRIGCON);
 126 }
 127
 128 static void decon_commit(struct exynos_drm_crtc *crtc)
 129 {
 130         struct decon_context *ctx = crtc->ctx;
 131         struct drm_display_mode *m = &crtc->base.mode;
 132         u32 val;
 133
 134         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 135                 return;
 136
 137         if (ctx->out_type & IFTYPE_HDMI) {
 138                 m->crtc_hsync_start = m->crtc_hdisplay + 10;
 139                 m->crtc_hsync_end = m->crtc_htotal - 92;
 140                 m->crtc_vsync_start = m->crtc_vdisplay + 1;
 141                 m->crtc_vsync_end = m->crtc_vsync_start + 1;
 142         }
 143
 144         decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID, 0);
 145
 146         /* enable clock gate */
 147         val = CMU_CLKGAGE_MODE_SFR_F | CMU_CLKGAGE_MODE_MEM_F;
 148         writel(val, ctx->addr + DECON_CMU);
 149
 150         /* lcd on and use command if */
 151         val = VIDOUT_LCD_ON;
 152         if (ctx->out_type & IFTYPE_I80) {
 153                 val |= VIDOUT_COMMAND_IF;
 154                 decon_setup_trigger(ctx);
 155         } else {
 156                 val |= VIDOUT_RGB_IF;
 157         }
 158
 159         writel(val, ctx->addr + DECON_VIDOUTCON0);
 160
 161         val = VIDTCON2_LINEVAL(m->vdisplay - 1) |
 162                 VIDTCON2_HOZVAL(m->hdisplay - 1);
 163         writel(val, ctx->addr + DECON_VIDTCON2);
 164
 165         if (!(ctx->out_type & IFTYPE_I80)) {
 166                 val = VIDTCON00_VBPD_F(
 167                                 m->crtc_vtotal - m->crtc_vsync_end - 1) |
 168                         VIDTCON00_VFPD_F(
 169                                 m->crtc_vsync_start - m->crtc_vdisplay - 1);
 170                 writel(val, ctx->addr + DECON_VIDTCON00);
 171
 172                 val = VIDTCON01_VSPW_F(
 173                                 m->crtc_vsync_end - m->crtc_vsync_start - 1);
 174                 writel(val, ctx->addr + DECON_VIDTCON01);
 175
 176                 val = VIDTCON10_HBPD_F(
 177                                 m->crtc_htotal - m->crtc_hsync_end - 1) |
 178                         VIDTCON10_HFPD_F(
 179                                 m->crtc_hsync_start - m->crtc_hdisplay - 1);
 180                 writel(val, ctx->addr + DECON_VIDTCON10);
 181
 182                 val = VIDTCON11_HSPW_F(
 183                                 m->crtc_hsync_end - m->crtc_hsync_start - 1);
 184                 writel(val, ctx->addr + DECON_VIDTCON11);
 185         }
 186
 187         /* enable output and display signal */
 188         decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID | VIDCON0_ENVID_F, ~0);
 189
 190         decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
 191 }
 192
 193 static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win,
 194                                  struct drm_framebuffer *fb)
 195 {
 196         unsigned long val;
 197
 198         val = readl(ctx->addr + DECON_WINCONx(win));
 199         val &= ~WINCONx_BPPMODE_MASK;
 200
 201         switch (fb->pixel_format) {
 202         case DRM_FORMAT_XRGB1555:
 203                 val |= WINCONx_BPPMODE_16BPP_I1555;
 204                 val |= WINCONx_HAWSWP_F;
 205                 val |= WINCONx_BURSTLEN_16WORD;
 206                 break;
 207         case DRM_FORMAT_RGB565:
 208                 val |= WINCONx_BPPMODE_16BPP_565;
 209                 val |= WINCONx_HAWSWP_F;
 210                 val |= WINCONx_BURSTLEN_16WORD;
 211                 break;
 212         case DRM_FORMAT_XRGB8888:
 213                 val |= WINCONx_BPPMODE_24BPP_888;
 214                 val |= WINCONx_WSWP_F;
 215                 val |= WINCONx_BURSTLEN_16WORD;
 216                 break;
 217         case DRM_FORMAT_ARGB8888:
 218                 val |= WINCONx_BPPMODE_32BPP_A8888;
 219                 val |= WINCONx_WSWP_F | WINCONx_BLD_PIX_F | WINCONx_ALPHA_SEL_F;
 220                 val |= WINCONx_BURSTLEN_16WORD;
 221                 break;
 222         default:
 223                 DRM_ERROR("Proper pixel format is not set\n");
 224                 return;
 225         }
 226
 227         DRM_DEBUG_KMS("bpp = %u\n", fb->bits_per_pixel);
 228
 229         /*
 230          * In case of exynos, setting dma-burst to 16Word causes permanent
 231          * tearing for very small buffers, e.g. cursor buffer. Burst Mode
 232          * switching which is based on plane size is not recommended as
 233          * plane size varies a lot towards the end of the screen and rapid
 234          * movement causes unstable DMA which results into iommu crash/tear.
 235          */
 236
 237         if (fb->width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
 238                 val &= ~WINCONx_BURSTLEN_MASK;
 239                 val |= WINCONx_BURSTLEN_8WORD;
 240         }
 241
 242         writel(val, ctx->addr + DECON_WINCONx(win));
 243 }
 244
 245 static void decon_shadow_protect_win(struct decon_context *ctx, int win,
 246                                         bool protect)
 247 {
 248         decon_set_bits(ctx, DECON_SHADOWCON, SHADOWCON_Wx_PROTECT(win),
 249                        protect ? ~0 : 0);
 250 }
 251
 252 static void decon_atomic_begin(struct exynos_drm_crtc *crtc)
 253 {
 254         struct decon_context *ctx = crtc->ctx;
 255         int i;
 256
 257         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 258                 return;
 259
 260         for (i = ctx->first_win; i < WINDOWS_NR; i++)
 261                 decon_shadow_protect_win(ctx, i, true);
 262 }
 263
 264 #define BIT_VAL(x, e, s) (((x) & ((1 << ((e) - (s) + 1)) - 1)) << (s))
 265 #define COORDINATE_X(x) BIT_VAL((x), 23, 12)
 266 #define COORDINATE_Y(x) BIT_VAL((x), 11, 0)
 267
 268 static void decon_update_plane(struct exynos_drm_crtc *crtc,
 269                                struct exynos_drm_plane *plane)
 270 {
 271         struct exynos_drm_plane_state *state =
 272                                 to_exynos_plane_state(plane->base.state);
 273         struct decon_context *ctx = crtc->ctx;
 274         struct drm_framebuffer *fb = state->base.fb;
 275         unsigned int win = plane->index;
 276         unsigned int bpp = fb->bits_per_pixel >> 3;
 277         unsigned int pitch = fb->pitches[0];
 278         dma_addr_t dma_addr = exynos_drm_fb_dma_addr(fb, 0);
 279         u32 val;
 280
 281         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 282                 return;
 283
 284         val = COORDINATE_X(state->crtc.x) | COORDINATE_Y(state->crtc.y);
 285         writel(val, ctx->addr + DECON_VIDOSDxA(win));
 286
 287         val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) |
 288                 COORDINATE_Y(state->crtc.y + state->crtc.h - 1);
 289         writel(val, ctx->addr + DECON_VIDOSDxB(win));
 290
 291         val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) |
 292                 VIDOSD_Wx_ALPHA_B_F(0x0);
 293         writel(val, ctx->addr + DECON_VIDOSDxC(win));
 294
 295         val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) |
 296                 VIDOSD_Wx_ALPHA_B_F(0x0);
 297         writel(val, ctx->addr + DECON_VIDOSDxD(win));
 298
 299         writel(dma_addr, ctx->addr + DECON_VIDW0xADD0B0(win));
 300
 301         val = dma_addr + pitch * state->src.h;
 302         writel(val, ctx->addr + DECON_VIDW0xADD1B0(win));
 303
 304         if (!(ctx->out_type & IFTYPE_HDMI))
 305                 val = BIT_VAL(pitch - state->crtc.w * bpp, 27, 14)
 306                         | BIT_VAL(state->crtc.w * bpp, 13, 0);
 307         else
 308                 val = BIT_VAL(pitch - state->crtc.w * bpp, 29, 15)
 309                         | BIT_VAL(state->crtc.w * bpp, 14, 0);
 310         writel(val, ctx->addr + DECON_VIDW0xADD2(win));
 311
 312         decon_win_set_pixfmt(ctx, win, fb);
 313
 314         /* window enable */
 315         decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, ~0);
 316 }
 317
 318 static void decon_disable_plane(struct exynos_drm_crtc *crtc,
 319                                 struct exynos_drm_plane *plane)
 320 {
 321         struct decon_context *ctx = crtc->ctx;
 322         unsigned int win = plane->index;
 323
 324         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 325                 return;
 326
 327         decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
 328 }
 329
 330 static void decon_atomic_flush(struct exynos_drm_crtc *crtc)
 331 {
 332         struct decon_context *ctx = crtc->ctx;
 333         int i;
 334
 335         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 336                 return;
 337
 338         for (i = ctx->first_win; i < WINDOWS_NR; i++)
 339                 decon_shadow_protect_win(ctx, i, false);
 340
 341         /* standalone update */
 342         decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
 343
 344         if (ctx->out_type & IFTYPE_I80)
 345                 set_bit(BIT_WIN_UPDATED, &ctx->flags);
 346 }
 347
 348 static void decon_swreset(struct decon_context *ctx)
 349 {
 350         unsigned int tries;
 351
 352         writel(0, ctx->addr + DECON_VIDCON0);
 353         for (tries = 2000; tries; --tries) {
 354                 if (~readl(ctx->addr + DECON_VIDCON0) & VIDCON0_STOP_STATUS)
 355                         break;
 356                 udelay(10);
 357         }
 358
 359         WARN(tries == 0, "failed to disable DECON\n");
 360
 361         writel(VIDCON0_SWRESET, ctx->addr + DECON_VIDCON0);
 362         for (tries = 2000; tries; --tries) {
 363                 if (~readl(ctx->addr + DECON_VIDCON0) & VIDCON0_SWRESET)
 364                         break;
 365                 udelay(10);
 366         }
 367
 368         WARN(tries == 0, "failed to software reset DECON\n");
 369
 370         if (!(ctx->out_type & IFTYPE_HDMI))
 371                 return;
 372
 373         writel(VIDCON0_CLKVALUP | VIDCON0_VLCKFREE, ctx->addr + DECON_VIDCON0);
 374         decon_set_bits(ctx, DECON_CMU,
 375                        CMU_CLKGAGE_MODE_SFR_F | CMU_CLKGAGE_MODE_MEM_F, ~0);
 376         writel(VIDCON1_VCLK_RUN_VDEN_DISABLE, ctx->addr + DECON_VIDCON1);
 377         writel(CRCCTRL_CRCEN | CRCCTRL_CRCSTART_F | CRCCTRL_CRCCLKEN,
 378                ctx->addr + DECON_CRCCTRL);
 379
 380         if (ctx->out_type & IFTYPE_I80)
 381                 decon_setup_trigger(ctx);
 382 }
 383
 384 static void decon_enable(struct exynos_drm_crtc *crtc)
 385 {
 386         struct decon_context *ctx = crtc->ctx;
 387
 388         if (!test_and_clear_bit(BIT_SUSPENDED, &ctx->flags))
 389                 return;
 390
 391         pm_runtime_get_sync(ctx->dev);
 392
 393         exynos_drm_pipe_clk_enable(crtc, true);
 394
 395         set_bit(BIT_CLKS_ENABLED, &ctx->flags);
 396
 397         decon_swreset(ctx);
 398
 399         /* if vblank was enabled status, enable it again. */
 400         if (test_and_clear_bit(BIT_IRQS_ENABLED, &ctx->flags))
 401                 decon_enable_vblank(ctx->crtc);
 402
 403         decon_commit(ctx->crtc);
 404 }
 405
 406 static void decon_disable(struct exynos_drm_crtc *crtc)
 407 {
 408         struct decon_context *ctx = crtc->ctx;
 409         int i;
 410
 411         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 412                 return;
 413
 414         /*
 415          * We need to make sure that all windows are disabled before we
 416          * suspend that connector. Otherwise we might try to scan from
 417          * a destroyed buffer later.
 418          */
 419         for (i = ctx->first_win; i < WINDOWS_NR; i++)
 420                 decon_disable_plane(crtc, &ctx->planes[i]);
 421
 422         decon_swreset(ctx);
 423
 424         clear_bit(BIT_CLKS_ENABLED, &ctx->flags);
 425
 426         exynos_drm_pipe_clk_enable(crtc, false);
 427
 428         pm_runtime_put_sync(ctx->dev);
 429
 430         set_bit(BIT_SUSPENDED, &ctx->flags);
 431 }
 432
 433 static void decon_te_irq_handler(struct exynos_drm_crtc *crtc)
 434 {
 435         struct decon_context *ctx = crtc->ctx;
 436
 437         if (!test_bit(BIT_CLKS_ENABLED, &ctx->flags) ||
 438             (ctx->out_type & I80_HW_TRG))
 439                 return;
 440
 441         if (test_and_clear_bit(BIT_WIN_UPDATED, &ctx->flags))
 442                 decon_set_bits(ctx, DECON_TRIGCON, TRIGCON_SWTRIGCMD, ~0);
 443 }
 444
 445 static void decon_clear_channels(struct exynos_drm_crtc *crtc)
 446 {
 447         struct decon_context *ctx = crtc->ctx;
 448         int win, i, ret;
 449
 450         DRM_DEBUG_KMS("%s\n", __FILE__);
 451
 452         for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
 453                 ret = clk_prepare_enable(ctx->clks[i]);
 454                 if (ret < 0)
 455                         goto err;
 456         }
 457
 458         for (win = 0; win < WINDOWS_NR; win++) {
 459                 decon_shadow_protect_win(ctx, win, true);
 460                 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
 461                 decon_shadow_protect_win(ctx, win, false);
 462         }
 463
 464         decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
 465
 466         /* TODO: wait for possible vsync */
 467         msleep(50);
 468
 469 err:
 470         while (--i >= 0)
 471                 clk_disable_unprepare(ctx->clks[i]);
 472 }
 473
 474 static struct exynos_drm_crtc_ops decon_crtc_ops = {
 475         .enable                 = decon_enable,
 476         .disable                = decon_disable,
 477         .enable_vblank          = decon_enable_vblank,
 478         .disable_vblank         = decon_disable_vblank,
 479         .atomic_begin           = decon_atomic_begin,
 480         .update_plane           = decon_update_plane,
 481         .disable_plane          = decon_disable_plane,
 482         .atomic_flush           = decon_atomic_flush,
 483         .te_handler             = decon_te_irq_handler,
 484 };
 485
 486 static int decon_bind(struct device *dev, struct device *master, void *data)
 487 {
 488         struct decon_context *ctx = dev_get_drvdata(dev);
 489         struct drm_device *drm_dev = data;
 490         struct exynos_drm_private *priv = drm_dev->dev_private;
 491         struct exynos_drm_plane *exynos_plane;
 492         enum exynos_drm_output_type out_type;
 493         unsigned int win;
 494         int ret;
 495
 496         ctx->drm_dev = drm_dev;
 497         ctx->pipe = priv->pipe++;
 498
 499         for (win = ctx->first_win; win < WINDOWS_NR; win++) {
 500                 int tmp = (win == ctx->first_win) ? 0 : win;
 501
 502                 ctx->configs[win].pixel_formats = decon_formats;
 503                 ctx->configs[win].num_pixel_formats = ARRAY_SIZE(decon_formats);
 504                 ctx->configs[win].zpos = win;
 505                 ctx->configs[win].type = decon_win_types[tmp];
 506
 507                 ret = exynos_plane_init(drm_dev, &ctx->planes[win], win,
 508                                         1 << ctx->pipe, &ctx->configs[win]);
 509                 if (ret)
 510                         return ret;
 511         }
 512
 513         exynos_plane = &ctx->planes[ctx->first_win];
 514         out_type = (ctx->out_type & IFTYPE_HDMI) ? EXYNOS_DISPLAY_TYPE_HDMI
 515                                                   : EXYNOS_DISPLAY_TYPE_LCD;
 516         ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
 517                                         ctx->pipe, out_type,
 518                                         &decon_crtc_ops, ctx);
 519         if (IS_ERR(ctx->crtc)) {
 520                 ret = PTR_ERR(ctx->crtc);
 521                 goto err;
 522         }
 523
 524         decon_clear_channels(ctx->crtc);
 525
 526         ret = drm_iommu_attach_device(drm_dev, dev);
 527         if (ret)
 528                 goto err;
 529
 530         return ret;
 531 err:
 532         priv->pipe--;
 533         return ret;
 534 }
 535
 536 static void decon_unbind(struct device *dev, struct device *master, void *data)
 537 {
 538         struct decon_context *ctx = dev_get_drvdata(dev);
 539
 540         decon_disable(ctx->crtc);
 541
 542         /* detach this sub driver from iommu mapping if supported. */
 543         drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
 544 }
 545
 546 static const struct component_ops decon_component_ops = {
 547         .bind   = decon_bind,
 548         .unbind = decon_unbind,
 549 };
 550
 551 static irqreturn_t decon_irq_handler(int irq, void *dev_id)
 552 {
 553         struct decon_context *ctx = dev_id;
 554         u32 val;
 555         int win;
 556
 557         if (!test_bit(BIT_CLKS_ENABLED, &ctx->flags))
 558                 goto out;
 559
 560         val = readl(ctx->addr + DECON_VIDINTCON1);
 561         val &= VIDINTCON1_INTFRMDONEPEND | VIDINTCON1_INTFRMPEND;
 562
 563         if (val) {
 564                 for (win = ctx->first_win; win < WINDOWS_NR ; win++) {
 565                         struct exynos_drm_plane *plane = &ctx->planes[win];
 566
 567                         if (!plane->pending_fb)
 568                                 continue;
 569
 570                         exynos_drm_crtc_finish_update(ctx->crtc, plane);
 571                 }
 572
 573                 /* clear */
 574                 writel(val, ctx->addr + DECON_VIDINTCON1);
 575                 drm_crtc_handle_vblank(&ctx->crtc->base);
 576         }
 577
 578 out:
 579         return IRQ_HANDLED;
 580 }
 581
 582 #ifdef CONFIG_PM
 583 static int exynos5433_decon_suspend(struct device *dev)
 584 {
 585         struct decon_context *ctx = dev_get_drvdata(dev);
 586         int i = ARRAY_SIZE(decon_clks_name);
 587
 588         while (--i >= 0)
 589                 clk_disable_unprepare(ctx->clks[i]);
 590
 591         return 0;
 592 }
 593
 594 static int exynos5433_decon_resume(struct device *dev)
 595 {
 596         struct decon_context *ctx = dev_get_drvdata(dev);
 597         int i, ret;
 598
 599         for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
 600                 ret = clk_prepare_enable(ctx->clks[i]);
 601                 if (ret < 0)
 602                         goto err;
 603         }
 604
 605         return 0;
 606
 607 err:
 608         while (--i >= 0)
 609                 clk_disable_unprepare(ctx->clks[i]);
 610
 611         return ret;
 612 }
 613 #endif
 614
 615 static const struct dev_pm_ops exynos5433_decon_pm_ops = {
 616         SET_RUNTIME_PM_OPS(exynos5433_decon_suspend, exynos5433_decon_resume,
 617                            NULL)
 618 };
 619
 620 static const struct of_device_id exynos5433_decon_driver_dt_match[] = {
 621         {
 622                 .compatible = "samsung,exynos5433-decon",
 623                 .data = (void *)I80_HW_TRG
 624         },
 625         {
 626                 .compatible = "samsung,exynos5433-decon-tv",
 627                 .data = (void *)(I80_HW_TRG | IFTYPE_HDMI)
 628         },
 629         {},
 630 };
 631 MODULE_DEVICE_TABLE(of, exynos5433_decon_driver_dt_match);
 632
 633 static int exynos5433_decon_probe(struct platform_device *pdev)
 634 {
 635         struct device *dev = &pdev->dev;
 636         struct decon_context *ctx;
 637         struct resource *res;
 638         int ret;
 639         int i;
 640
 641         ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
 642         if (!ctx)
 643                 return -ENOMEM;
 644
 645         __set_bit(BIT_SUSPENDED, &ctx->flags);
 646         ctx->dev = dev;
 647         ctx->out_type = (unsigned long)of_device_get_match_data(dev);
 648
 649         if (ctx->out_type & IFTYPE_HDMI) {
 650                 ctx->first_win = 1;
 651                 ctx->out_type = IFTYPE_I80;
 652         } else if (of_get_child_by_name(dev->of_node, "i80-if-timings")) {
 653                 ctx->out_type = IFTYPE_I80;
 654         }
 655
 656         for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
 657                 struct clk *clk;
 658
 659                 clk = devm_clk_get(ctx->dev, decon_clks_name[i]);
 660                 if (IS_ERR(clk))
 661                         return PTR_ERR(clk);
 662
 663                 ctx->clks[i] = clk;
 664         }
 665
 666         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 667         if (!res) {
 668                 dev_err(dev, "cannot find IO resource\n");
 669                 return -ENXIO;
 670         }
 671
 672         ctx->addr = devm_ioremap_resource(dev, res);
 673         if (IS_ERR(ctx->addr)) {
 674                 dev_err(dev, "ioremap failed\n");
 675                 return PTR_ERR(ctx->addr);
 676         }
 677
 678         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
 679                         (ctx->out_type & IFTYPE_I80) ? "lcd_sys" : "vsync");
 680         if (!res) {
 681                 dev_err(dev, "cannot find IRQ resource\n");
 682                 return -ENXIO;
 683         }
 684
 685         ret = devm_request_irq(dev, res->start, decon_irq_handler, 0,
 686                                "drm_decon", ctx);
 687         if (ret < 0) {
 688                 dev_err(dev, "lcd_sys irq request failed\n");
 689                 return ret;
 690         }
 691
 692         platform_set_drvdata(pdev, ctx);
 693
 694         pm_runtime_enable(dev);
 695
 696         ret = component_add(dev, &decon_component_ops);
 697         if (ret)
 698                 goto err_disable_pm_runtime;
 699
 700         return 0;
 701
 702 err_disable_pm_runtime:
 703         pm_runtime_disable(dev);
 704
 705         return ret;
 706 }
 707
 708 static int exynos5433_decon_remove(struct platform_device *pdev)
 709 {
 710         pm_runtime_disable(&pdev->dev);
 711
 712         component_del(&pdev->dev, &decon_component_ops);
 713
 714         return 0;
 715 }
 716
 717 struct platform_driver exynos5433_decon_driver = {
 718         .probe          = exynos5433_decon_probe,
 719         .remove         = exynos5433_decon_remove,
 720         .driver         = {
 721                 .name   = "exynos5433-decon",
 722                 .pm     = &exynos5433_decon_pm_ops,
 723                 .of_match_table = exynos5433_decon_driver_dt_match,
 724         },
 725 };