drivers/gpu/drm/exynos/exynos5433_drm_decon.c

   1 /* drivers/gpu/drm/exynos5433_drm_decon.c
   2  *
   3  * Copyright (C) 2015 Samsung Electronics Co.Ltd
   4  * Authors:
   5  *      Joonyoung Shim <jy0922.shim@samsung.com>
   6  *      Hyungwon Hwang <human.hwang@samsung.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundationr
  11  */
  12
  13 #include <linux/platform_device.h>
  14 #include <linux/clk.h>
  15 #include <linux/component.h>
  16 #include <linux/mfd/syscon.h>
  17 #include <linux/of_device.h>
  18 #include <linux/of_gpio.h>
  19 #include <linux/pm_runtime.h>
  20 #include <linux/regmap.h>
  21
  22 #include <video/exynos5433_decon.h>
  23
  24 #include "exynos_drm_drv.h"
  25 #include "exynos_drm_crtc.h"
  26 #include "exynos_drm_fb.h"
  27 #include "exynos_drm_plane.h"
  28 #include "exynos_drm_iommu.h"
  29
  30 #define DSD_CFG_MUX 0x1004
  31 #define DSD_CFG_MUX_TE_UNMASK_GLOBAL BIT(13)
  32
  33 #define WINDOWS_NR      3
  34 #define MIN_FB_WIDTH_FOR_16WORD_BURST   128
  35
  36 #define IFTYPE_I80      (1 << 0)
  37 #define I80_HW_TRG      (1 << 1)
  38 #define IFTYPE_HDMI     (1 << 2)
  39
  40 static const char * const decon_clks_name[] = {
  41         "pclk",
  42         "aclk_decon",
  43         "aclk_smmu_decon0x",
  44         "aclk_xiu_decon0x",
  45         "pclk_smmu_decon0x",
  46         "sclk_decon_vclk",
  47         "sclk_decon_eclk",
  48 };
  49
  50 enum decon_flag_bits {
  51         BIT_CLKS_ENABLED,
  52         BIT_IRQS_ENABLED,
  53         BIT_WIN_UPDATED,
  54         BIT_SUSPENDED,
  55         BIT_REQUEST_UPDATE
  56 };
  57
  58 struct decon_context {
  59         struct device                   *dev;
  60         struct drm_device               *drm_dev;
  61         struct exynos_drm_crtc          *crtc;
  62         struct exynos_drm_plane         planes[WINDOWS_NR];
  63         struct exynos_drm_plane_config  configs[WINDOWS_NR];
  64         void __iomem                    *addr;
  65         struct regmap                   *sysreg;
  66         struct clk                      *clks[ARRAY_SIZE(decon_clks_name)];
  67         int                             pipe;
  68         unsigned long                   flags;
  69         unsigned long                   out_type;
  70         int                             first_win;
  71 };
  72
  73 static const uint32_t decon_formats[] = {
  74         DRM_FORMAT_XRGB1555,
  75         DRM_FORMAT_RGB565,
  76         DRM_FORMAT_XRGB8888,
  77         DRM_FORMAT_ARGB8888,
  78 };
  79
  80 static const enum drm_plane_type decon_win_types[WINDOWS_NR] = {
  81         DRM_PLANE_TYPE_PRIMARY,
  82         DRM_PLANE_TYPE_OVERLAY,
  83         DRM_PLANE_TYPE_CURSOR,
  84 };
  85
  86 static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask,
  87                                   u32 val)
  88 {
  89         val = (val & mask) | (readl(ctx->addr + reg) & ~mask);
  90         writel(val, ctx->addr + reg);
  91 }
  92
  93 static int decon_enable_vblank(struct exynos_drm_crtc *crtc)
  94 {
  95         struct decon_context *ctx = crtc->ctx;
  96         u32 val;
  97
  98         if (test_bit(BIT_SUSPENDED, &ctx->flags))
  99                 return -EPERM;
 100
 101         if (!test_and_set_bit(BIT_IRQS_ENABLED, &ctx->flags)) {
 102                 val = VIDINTCON0_INTEN;
 103                 if (ctx->out_type & IFTYPE_I80)
 104                         val |= VIDINTCON0_FRAMEDONE;
 105                 else
 106                         val |= VIDINTCON0_INTFRMEN;
 107
 108                 writel(val, ctx->addr + DECON_VIDINTCON0);
 109         }
 110
 111         return 0;
 112 }
 113
 114 static void decon_disable_vblank(struct exynos_drm_crtc *crtc)
 115 {
 116         struct decon_context *ctx = crtc->ctx;
 117
 118         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 119                 return;
 120
 121         if (test_and_clear_bit(BIT_IRQS_ENABLED, &ctx->flags))
 122                 writel(0, ctx->addr + DECON_VIDINTCON0);
 123 }
 124
 125 static void decon_setup_trigger(struct decon_context *ctx)
 126 {
 127         if (!(ctx->out_type & (IFTYPE_I80 | I80_HW_TRG)))
 128                 return;
 129
 130         if (!(ctx->out_type & I80_HW_TRG)) {
 131                 writel(TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN
 132                        | TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN,
 133                        ctx->addr + DECON_TRIGCON);
 134                 return;
 135         }
 136
 137         writel(TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F | TRIGCON_HWTRIGMASK
 138                | TRIGCON_HWTRIGEN, ctx->addr + DECON_TRIGCON);
 139
 140         if (regmap_update_bits(ctx->sysreg, DSD_CFG_MUX,
 141                                DSD_CFG_MUX_TE_UNMASK_GLOBAL, ~0))
 142                 DRM_ERROR("Cannot update sysreg.\n");
 143 }
 144
 145 static void decon_commit(struct exynos_drm_crtc *crtc)
 146 {
 147         struct decon_context *ctx = crtc->ctx;
 148         struct drm_display_mode *m = &crtc->base.mode;
 149         u32 val;
 150
 151         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 152                 return;
 153
 154         if (ctx->out_type & IFTYPE_HDMI) {
 155                 m->crtc_hsync_start = m->crtc_hdisplay + 10;
 156                 m->crtc_hsync_end = m->crtc_htotal - 92;
 157                 m->crtc_vsync_start = m->crtc_vdisplay + 1;
 158                 m->crtc_vsync_end = m->crtc_vsync_start + 1;
 159         }
 160
 161         decon_setup_trigger(ctx);
 162
 163         /* lcd on and use command if */
 164         val = VIDOUT_LCD_ON;
 165         if (ctx->out_type & IFTYPE_I80) {
 166                 val |= VIDOUT_COMMAND_IF;
 167         } else {
 168                 val |= VIDOUT_RGB_IF;
 169         }
 170
 171         writel(val, ctx->addr + DECON_VIDOUTCON0);
 172
 173         val = VIDTCON2_LINEVAL(m->vdisplay - 1) |
 174                 VIDTCON2_HOZVAL(m->hdisplay - 1);
 175         writel(val, ctx->addr + DECON_VIDTCON2);
 176
 177         if (!(ctx->out_type & IFTYPE_I80)) {
 178                 val = VIDTCON00_VBPD_F(
 179                                 m->crtc_vtotal - m->crtc_vsync_end - 1) |
 180                         VIDTCON00_VFPD_F(
 181                                 m->crtc_vsync_start - m->crtc_vdisplay - 1);
 182                 writel(val, ctx->addr + DECON_VIDTCON00);
 183
 184                 val = VIDTCON01_VSPW_F(
 185                                 m->crtc_vsync_end - m->crtc_vsync_start - 1);
 186                 writel(val, ctx->addr + DECON_VIDTCON01);
 187
 188                 val = VIDTCON10_HBPD_F(
 189                                 m->crtc_htotal - m->crtc_hsync_end - 1) |
 190                         VIDTCON10_HFPD_F(
 191                                 m->crtc_hsync_start - m->crtc_hdisplay - 1);
 192                 writel(val, ctx->addr + DECON_VIDTCON10);
 193
 194                 val = VIDTCON11_HSPW_F(
 195                                 m->crtc_hsync_end - m->crtc_hsync_start - 1);
 196                 writel(val, ctx->addr + DECON_VIDTCON11);
 197         }
 198
 199         /* enable output and display signal */
 200         decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID | VIDCON0_ENVID_F, ~0);
 201
 202         decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
 203 }
 204
 205 static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win,
 206                                  struct drm_framebuffer *fb)
 207 {
 208         unsigned long val;
 209
 210         val = readl(ctx->addr + DECON_WINCONx(win));
 211         val &= ~WINCONx_BPPMODE_MASK;
 212
 213         switch (fb->format->format) {
 214         case DRM_FORMAT_XRGB1555:
 215                 val |= WINCONx_BPPMODE_16BPP_I1555;
 216                 val |= WINCONx_HAWSWP_F;
 217                 val |= WINCONx_BURSTLEN_16WORD;
 218                 break;
 219         case DRM_FORMAT_RGB565:
 220                 val |= WINCONx_BPPMODE_16BPP_565;
 221                 val |= WINCONx_HAWSWP_F;
 222                 val |= WINCONx_BURSTLEN_16WORD;
 223                 break;
 224         case DRM_FORMAT_XRGB8888:
 225                 val |= WINCONx_BPPMODE_24BPP_888;
 226                 val |= WINCONx_WSWP_F;
 227                 val |= WINCONx_BURSTLEN_16WORD;
 228                 break;
 229         case DRM_FORMAT_ARGB8888:
 230                 val |= WINCONx_BPPMODE_32BPP_A8888;
 231                 val |= WINCONx_WSWP_F | WINCONx_BLD_PIX_F | WINCONx_ALPHA_SEL_F;
 232                 val |= WINCONx_BURSTLEN_16WORD;
 233                 break;
 234         default:
 235                 DRM_ERROR("Proper pixel format is not set\n");
 236                 return;
 237         }
 238
 239         DRM_DEBUG_KMS("bpp = %u\n", fb->format->cpp[0] * 8);
 240
 241         /*
 242          * In case of exynos, setting dma-burst to 16Word causes permanent
 243          * tearing for very small buffers, e.g. cursor buffer. Burst Mode
 244          * switching which is based on plane size is not recommended as
 245          * plane size varies a lot towards the end of the screen and rapid
 246          * movement causes unstable DMA which results into iommu crash/tear.
 247          */
 248
 249         if (fb->width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
 250                 val &= ~WINCONx_BURSTLEN_MASK;
 251                 val |= WINCONx_BURSTLEN_8WORD;
 252         }
 253
 254         writel(val, ctx->addr + DECON_WINCONx(win));
 255 }
 256
 257 static void decon_shadow_protect_win(struct decon_context *ctx, int win,
 258                                         bool protect)
 259 {
 260         decon_set_bits(ctx, DECON_SHADOWCON, SHADOWCON_Wx_PROTECT(win),
 261                        protect ? ~0 : 0);
 262 }
 263
 264 static void decon_atomic_begin(struct exynos_drm_crtc *crtc)
 265 {
 266         struct decon_context *ctx = crtc->ctx;
 267         int i;
 268
 269         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 270                 return;
 271
 272         for (i = ctx->first_win; i < WINDOWS_NR; i++)
 273                 decon_shadow_protect_win(ctx, i, true);
 274 }
 275
 276 #define BIT_VAL(x, e, s) (((x) & ((1 << ((e) - (s) + 1)) - 1)) << (s))
 277 #define COORDINATE_X(x) BIT_VAL((x), 23, 12)
 278 #define COORDINATE_Y(x) BIT_VAL((x), 11, 0)
 279
 280 static void decon_update_plane(struct exynos_drm_crtc *crtc,
 281                                struct exynos_drm_plane *plane)
 282 {
 283         struct exynos_drm_plane_state *state =
 284                                 to_exynos_plane_state(plane->base.state);
 285         struct decon_context *ctx = crtc->ctx;
 286         struct drm_framebuffer *fb = state->base.fb;
 287         unsigned int win = plane->index;
 288         unsigned int bpp = fb->format->cpp[0];
 289         unsigned int pitch = fb->pitches[0];
 290         dma_addr_t dma_addr = exynos_drm_fb_dma_addr(fb, 0);
 291         u32 val;
 292
 293         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 294                 return;
 295
 296         val = COORDINATE_X(state->crtc.x) | COORDINATE_Y(state->crtc.y);
 297         writel(val, ctx->addr + DECON_VIDOSDxA(win));
 298
 299         val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) |
 300                 COORDINATE_Y(state->crtc.y + state->crtc.h - 1);
 301         writel(val, ctx->addr + DECON_VIDOSDxB(win));
 302
 303         val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) |
 304                 VIDOSD_Wx_ALPHA_B_F(0x0);
 305         writel(val, ctx->addr + DECON_VIDOSDxC(win));
 306
 307         val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) |
 308                 VIDOSD_Wx_ALPHA_B_F(0x0);
 309         writel(val, ctx->addr + DECON_VIDOSDxD(win));
 310
 311         writel(dma_addr, ctx->addr + DECON_VIDW0xADD0B0(win));
 312
 313         val = dma_addr + pitch * state->src.h;
 314         writel(val, ctx->addr + DECON_VIDW0xADD1B0(win));
 315
 316         if (!(ctx->out_type & IFTYPE_HDMI))
 317                 val = BIT_VAL(pitch - state->crtc.w * bpp, 27, 14)
 318                         | BIT_VAL(state->crtc.w * bpp, 13, 0);
 319         else
 320                 val = BIT_VAL(pitch - state->crtc.w * bpp, 29, 15)
 321                         | BIT_VAL(state->crtc.w * bpp, 14, 0);
 322         writel(val, ctx->addr + DECON_VIDW0xADD2(win));
 323
 324         decon_win_set_pixfmt(ctx, win, fb);
 325
 326         /* window enable */
 327         decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, ~0);
 328         set_bit(BIT_REQUEST_UPDATE, &ctx->flags);
 329 }
 330
 331 static void decon_disable_plane(struct exynos_drm_crtc *crtc,
 332                                 struct exynos_drm_plane *plane)
 333 {
 334         struct decon_context *ctx = crtc->ctx;
 335         unsigned int win = plane->index;
 336
 337         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 338                 return;
 339
 340         decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
 341         set_bit(BIT_REQUEST_UPDATE, &ctx->flags);
 342 }
 343
 344 static void decon_atomic_flush(struct exynos_drm_crtc *crtc)
 345 {
 346         struct decon_context *ctx = crtc->ctx;
 347         int i;
 348
 349         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 350                 return;
 351
 352         for (i = ctx->first_win; i < WINDOWS_NR; i++)
 353                 decon_shadow_protect_win(ctx, i, false);
 354
 355         if (test_and_clear_bit(BIT_REQUEST_UPDATE, &ctx->flags))
 356                 decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
 357
 358         if (ctx->out_type & IFTYPE_I80)
 359                 set_bit(BIT_WIN_UPDATED, &ctx->flags);
 360 }
 361
 362 static void decon_swreset(struct decon_context *ctx)
 363 {
 364         unsigned int tries;
 365
 366         writel(0, ctx->addr + DECON_VIDCON0);
 367         for (tries = 2000; tries; --tries) {
 368                 if (~readl(ctx->addr + DECON_VIDCON0) & VIDCON0_STOP_STATUS)
 369                         break;
 370                 udelay(10);
 371         }
 372
 373         WARN(tries == 0, "failed to disable DECON\n");
 374
 375         writel(VIDCON0_SWRESET, ctx->addr + DECON_VIDCON0);
 376         for (tries = 2000; tries; --tries) {
 377                 if (~readl(ctx->addr + DECON_VIDCON0) & VIDCON0_SWRESET)
 378                         break;
 379                 udelay(10);
 380         }
 381
 382         WARN(tries == 0, "failed to software reset DECON\n");
 383
 384         if (!(ctx->out_type & IFTYPE_HDMI))
 385                 return;
 386
 387         writel(VIDCON0_CLKVALUP | VIDCON0_VLCKFREE, ctx->addr + DECON_VIDCON0);
 388         decon_set_bits(ctx, DECON_CMU,
 389                        CMU_CLKGAGE_MODE_SFR_F | CMU_CLKGAGE_MODE_MEM_F, ~0);
 390         writel(VIDCON1_VCLK_RUN_VDEN_DISABLE, ctx->addr + DECON_VIDCON1);
 391         writel(CRCCTRL_CRCEN | CRCCTRL_CRCSTART_F | CRCCTRL_CRCCLKEN,
 392                ctx->addr + DECON_CRCCTRL);
 393 }
 394
 395 static void decon_enable(struct exynos_drm_crtc *crtc)
 396 {
 397         struct decon_context *ctx = crtc->ctx;
 398
 399         if (!test_and_clear_bit(BIT_SUSPENDED, &ctx->flags))
 400                 return;
 401
 402         pm_runtime_get_sync(ctx->dev);
 403
 404         exynos_drm_pipe_clk_enable(crtc, true);
 405
 406         set_bit(BIT_CLKS_ENABLED, &ctx->flags);
 407
 408         decon_swreset(ctx);
 409
 410         /* if vblank was enabled status, enable it again. */
 411         if (test_and_clear_bit(BIT_IRQS_ENABLED, &ctx->flags))
 412                 decon_enable_vblank(ctx->crtc);
 413
 414         decon_commit(ctx->crtc);
 415 }
 416
 417 static void decon_disable(struct exynos_drm_crtc *crtc)
 418 {
 419         struct decon_context *ctx = crtc->ctx;
 420         int i;
 421
 422         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 423                 return;
 424
 425         /*
 426          * We need to make sure that all windows are disabled before we
 427          * suspend that connector. Otherwise we might try to scan from
 428          * a destroyed buffer later.
 429          */
 430         for (i = ctx->first_win; i < WINDOWS_NR; i++)
 431                 decon_disable_plane(crtc, &ctx->planes[i]);
 432
 433         decon_swreset(ctx);
 434
 435         clear_bit(BIT_CLKS_ENABLED, &ctx->flags);
 436
 437         exynos_drm_pipe_clk_enable(crtc, false);
 438
 439         pm_runtime_put_sync(ctx->dev);
 440
 441         set_bit(BIT_SUSPENDED, &ctx->flags);
 442 }
 443
 444 static void decon_te_irq_handler(struct exynos_drm_crtc *crtc)
 445 {
 446         struct decon_context *ctx = crtc->ctx;
 447
 448         if (!test_bit(BIT_CLKS_ENABLED, &ctx->flags) ||
 449             (ctx->out_type & I80_HW_TRG))
 450                 return;
 451
 452         if (test_and_clear_bit(BIT_WIN_UPDATED, &ctx->flags))
 453                 decon_set_bits(ctx, DECON_TRIGCON, TRIGCON_SWTRIGCMD, ~0);
 454 }
 455
 456 static void decon_clear_channels(struct exynos_drm_crtc *crtc)
 457 {
 458         struct decon_context *ctx = crtc->ctx;
 459         int win, i, ret;
 460
 461         DRM_DEBUG_KMS("%s\n", __FILE__);
 462
 463         for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
 464                 ret = clk_prepare_enable(ctx->clks[i]);
 465                 if (ret < 0)
 466                         goto err;
 467         }
 468
 469         for (win = 0; win < WINDOWS_NR; win++) {
 470                 decon_shadow_protect_win(ctx, win, true);
 471                 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
 472                 decon_shadow_protect_win(ctx, win, false);
 473         }
 474
 475         decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
 476
 477         /* TODO: wait for possible vsync */
 478         msleep(50);
 479
 480 err:
 481         while (--i >= 0)
 482                 clk_disable_unprepare(ctx->clks[i]);
 483 }
 484
 485 static const struct exynos_drm_crtc_ops decon_crtc_ops = {
 486         .enable                 = decon_enable,
 487         .disable                = decon_disable,
 488         .enable_vblank          = decon_enable_vblank,
 489         .disable_vblank         = decon_disable_vblank,
 490         .atomic_begin           = decon_atomic_begin,
 491         .update_plane           = decon_update_plane,
 492         .disable_plane          = decon_disable_plane,
 493         .atomic_flush           = decon_atomic_flush,
 494         .te_handler             = decon_te_irq_handler,
 495 };
 496
 497 static int decon_bind(struct device *dev, struct device *master, void *data)
 498 {
 499         struct decon_context *ctx = dev_get_drvdata(dev);
 500         struct drm_device *drm_dev = data;
 501         struct exynos_drm_private *priv = drm_dev->dev_private;
 502         struct exynos_drm_plane *exynos_plane;
 503         enum exynos_drm_output_type out_type;
 504         unsigned int win;
 505         int ret;
 506
 507         ctx->drm_dev = drm_dev;
 508         ctx->pipe = priv->pipe++;
 509
 510         for (win = ctx->first_win; win < WINDOWS_NR; win++) {
 511                 int tmp = (win == ctx->first_win) ? 0 : win;
 512
 513                 ctx->configs[win].pixel_formats = decon_formats;
 514                 ctx->configs[win].num_pixel_formats = ARRAY_SIZE(decon_formats);
 515                 ctx->configs[win].zpos = win;
 516                 ctx->configs[win].type = decon_win_types[tmp];
 517
 518                 ret = exynos_plane_init(drm_dev, &ctx->planes[win], win,
 519                                         1 << ctx->pipe, &ctx->configs[win]);
 520                 if (ret)
 521                         return ret;
 522         }
 523
 524         exynos_plane = &ctx->planes[ctx->first_win];
 525         out_type = (ctx->out_type & IFTYPE_HDMI) ? EXYNOS_DISPLAY_TYPE_HDMI
 526                                                   : EXYNOS_DISPLAY_TYPE_LCD;
 527         ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
 528                                         ctx->pipe, out_type,
 529                                         &decon_crtc_ops, ctx);
 530         if (IS_ERR(ctx->crtc)) {
 531                 ret = PTR_ERR(ctx->crtc);
 532                 goto err;
 533         }
 534
 535         decon_clear_channels(ctx->crtc);
 536
 537         ret = drm_iommu_attach_device(drm_dev, dev);
 538         if (ret)
 539                 goto err;
 540
 541         return ret;
 542 err:
 543         priv->pipe--;
 544         return ret;
 545 }
 546
 547 static void decon_unbind(struct device *dev, struct device *master, void *data)
 548 {
 549         struct decon_context *ctx = dev_get_drvdata(dev);
 550
 551         decon_disable(ctx->crtc);
 552
 553         /* detach this sub driver from iommu mapping if supported. */
 554         drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
 555 }
 556
 557 static const struct component_ops decon_component_ops = {
 558         .bind   = decon_bind,
 559         .unbind = decon_unbind,
 560 };
 561
 562 static irqreturn_t decon_irq_handler(int irq, void *dev_id)
 563 {
 564         struct decon_context *ctx = dev_id;
 565         u32 val;
 566
 567         if (!test_bit(BIT_CLKS_ENABLED, &ctx->flags))
 568                 goto out;
 569
 570         val = readl(ctx->addr + DECON_VIDINTCON1);
 571         val &= VIDINTCON1_INTFRMDONEPEND | VIDINTCON1_INTFRMPEND;
 572
 573         if (val) {
 574                 writel(val, ctx->addr + DECON_VIDINTCON1);
 575                 drm_crtc_handle_vblank(&ctx->crtc->base);
 576         }
 577
 578 out:
 579         return IRQ_HANDLED;
 580 }
 581
 582 #ifdef CONFIG_PM
 583 static int exynos5433_decon_suspend(struct device *dev)
 584 {
 585         struct decon_context *ctx = dev_get_drvdata(dev);
 586         int i = ARRAY_SIZE(decon_clks_name);
 587
 588         while (--i >= 0)
 589                 clk_disable_unprepare(ctx->clks[i]);
 590
 591         return 0;
 592 }
 593
 594 static int exynos5433_decon_resume(struct device *dev)
 595 {
 596         struct decon_context *ctx = dev_get_drvdata(dev);
 597         int i, ret;
 598
 599         for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
 600                 ret = clk_prepare_enable(ctx->clks[i]);
 601                 if (ret < 0)
 602                         goto err;
 603         }
 604
 605         return 0;
 606
 607 err:
 608         while (--i >= 0)
 609                 clk_disable_unprepare(ctx->clks[i]);
 610
 611         return ret;
 612 }
 613 #endif
 614
 615 static const struct dev_pm_ops exynos5433_decon_pm_ops = {
 616         SET_RUNTIME_PM_OPS(exynos5433_decon_suspend, exynos5433_decon_resume,
 617                            NULL)
 618 };
 619
 620 static const struct of_device_id exynos5433_decon_driver_dt_match[] = {
 621         {
 622                 .compatible = "samsung,exynos5433-decon",
 623                 .data = (void *)I80_HW_TRG
 624         },
 625         {
 626                 .compatible = "samsung,exynos5433-decon-tv",
 627                 .data = (void *)(I80_HW_TRG | IFTYPE_HDMI)
 628         },
 629         {},
 630 };
 631 MODULE_DEVICE_TABLE(of, exynos5433_decon_driver_dt_match);
 632
 633 static int exynos5433_decon_probe(struct platform_device *pdev)
 634 {
 635         struct device *dev = &pdev->dev;
 636         struct decon_context *ctx;
 637         struct resource *res;
 638         int ret;
 639         int i;
 640
 641         ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
 642         if (!ctx)
 643                 return -ENOMEM;
 644
 645         __set_bit(BIT_SUSPENDED, &ctx->flags);
 646         ctx->dev = dev;
 647         ctx->out_type = (unsigned long)of_device_get_match_data(dev);
 648
 649         if (ctx->out_type & IFTYPE_HDMI) {
 650                 ctx->first_win = 1;
 651         } else if (of_get_child_by_name(dev->of_node, "i80-if-timings")) {
 652                 ctx->out_type |= IFTYPE_I80;
 653         }
 654
 655         if (ctx->out_type | I80_HW_TRG) {
 656                 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
 657                                                         "samsung,disp-sysreg");
 658                 if (IS_ERR(ctx->sysreg)) {
 659                         dev_err(dev, "failed to get system register\n");
 660                         return PTR_ERR(ctx->sysreg);
 661                 }
 662         }
 663
 664         for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
 665                 struct clk *clk;
 666
 667                 clk = devm_clk_get(ctx->dev, decon_clks_name[i]);
 668                 if (IS_ERR(clk))
 669                         return PTR_ERR(clk);
 670
 671                 ctx->clks[i] = clk;
 672         }
 673
 674         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 675         if (!res) {
 676                 dev_err(dev, "cannot find IO resource\n");
 677                 return -ENXIO;
 678         }
 679
 680         ctx->addr = devm_ioremap_resource(dev, res);
 681         if (IS_ERR(ctx->addr)) {
 682                 dev_err(dev, "ioremap failed\n");
 683                 return PTR_ERR(ctx->addr);
 684         }
 685
 686         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
 687                         (ctx->out_type & IFTYPE_I80) ? "lcd_sys" : "vsync");
 688         if (!res) {
 689                 dev_err(dev, "cannot find IRQ resource\n");
 690                 return -ENXIO;
 691         }
 692
 693         ret = devm_request_irq(dev, res->start, decon_irq_handler, 0,
 694                                "drm_decon", ctx);
 695         if (ret < 0) {
 696                 dev_err(dev, "lcd_sys irq request failed\n");
 697                 return ret;
 698         }
 699
 700         platform_set_drvdata(pdev, ctx);
 701
 702         pm_runtime_enable(dev);
 703
 704         ret = component_add(dev, &decon_component_ops);
 705         if (ret)
 706                 goto err_disable_pm_runtime;
 707
 708         return 0;
 709
 710 err_disable_pm_runtime:
 711         pm_runtime_disable(dev);
 712
 713         return ret;
 714 }
 715
 716 static int exynos5433_decon_remove(struct platform_device *pdev)
 717 {
 718         pm_runtime_disable(&pdev->dev);
 719
 720         component_del(&pdev->dev, &decon_component_ops);
 721
 722         return 0;
 723 }
 724
 725 struct platform_driver exynos5433_decon_driver = {
 726         .probe          = exynos5433_decon_probe,
 727         .remove         = exynos5433_decon_remove,
 728         .driver         = {
 729                 .name   = "exynos5433-decon",
 730                 .pm     = &exynos5433_decon_pm_ops,
 731                 .of_match_table = exynos5433_decon_driver_dt_match,
 732         },
 733 };