drivers/gpu/drm/exynos/exynos5433_drm_decon.c

   1 /* drivers/gpu/drm/exynos5433_drm_decon.c
   2  *
   3  * Copyright (C) 2015 Samsung Electronics Co.Ltd
   4  * Authors:
   5  *      Joonyoung Shim <jy0922.shim@samsung.com>
   6  *      Hyungwon Hwang <human.hwang@samsung.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundationr
  11  */
  12
  13 #include <linux/platform_device.h>
  14 #include <linux/clk.h>
  15 #include <linux/component.h>
  16 #include <linux/of_device.h>
  17 #include <linux/of_gpio.h>
  18 #include <linux/pm_runtime.h>
  19
  20 #include <video/exynos5433_decon.h>
  21
  22 #include "exynos_drm_drv.h"
  23 #include "exynos_drm_crtc.h"
  24 #include "exynos_drm_fb.h"
  25 #include "exynos_drm_plane.h"
  26 #include "exynos_drm_iommu.h"
  27
  28 #define WINDOWS_NR      3
  29 #define MIN_FB_WIDTH_FOR_16WORD_BURST   128
  30
  31 static const char * const decon_clks_name[] = {
  32         "pclk",
  33         "aclk_decon",
  34         "aclk_smmu_decon0x",
  35         "aclk_xiu_decon0x",
  36         "pclk_smmu_decon0x",
  37         "sclk_decon_vclk",
  38         "sclk_decon_eclk",
  39 };
  40
  41 enum decon_iftype {
  42         IFTYPE_RGB,
  43         IFTYPE_I80,
  44         IFTYPE_HDMI
  45 };
  46
  47 enum decon_flag_bits {
  48         BIT_CLKS_ENABLED,
  49         BIT_IRQS_ENABLED,
  50         BIT_WIN_UPDATED,
  51         BIT_SUSPENDED
  52 };
  53
  54 struct decon_context {
  55         struct device                   *dev;
  56         struct drm_device               *drm_dev;
  57         struct exynos_drm_crtc          *crtc;
  58         struct exynos_drm_plane         planes[WINDOWS_NR];
  59         struct exynos_drm_plane_config  configs[WINDOWS_NR];
  60         void __iomem                    *addr;
  61         struct clk                      *clks[ARRAY_SIZE(decon_clks_name)];
  62         int                             pipe;
  63         unsigned long                   flags;
  64         enum decon_iftype               out_type;
  65         int                             first_win;
  66 };
  67
  68 static const uint32_t decon_formats[] = {
  69         DRM_FORMAT_XRGB1555,
  70         DRM_FORMAT_RGB565,
  71         DRM_FORMAT_XRGB8888,
  72         DRM_FORMAT_ARGB8888,
  73 };
  74
  75 static const enum drm_plane_type decon_win_types[WINDOWS_NR] = {
  76         DRM_PLANE_TYPE_PRIMARY,
  77         DRM_PLANE_TYPE_OVERLAY,
  78         DRM_PLANE_TYPE_CURSOR,
  79 };
  80
  81 static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask,
  82                                   u32 val)
  83 {
  84         val = (val & mask) | (readl(ctx->addr + reg) & ~mask);
  85         writel(val, ctx->addr + reg);
  86 }
  87
  88 static int decon_enable_vblank(struct exynos_drm_crtc *crtc)
  89 {
  90         struct decon_context *ctx = crtc->ctx;
  91         u32 val;
  92
  93         if (test_bit(BIT_SUSPENDED, &ctx->flags))
  94                 return -EPERM;
  95
  96         if (!test_and_set_bit(BIT_IRQS_ENABLED, &ctx->flags)) {
  97                 val = VIDINTCON0_INTEN;
  98                 if (ctx->out_type == IFTYPE_I80)
  99                         val |= VIDINTCON0_FRAMEDONE;
 100                 else
 101                         val |= VIDINTCON0_INTFRMEN;
 102
 103                 writel(val, ctx->addr + DECON_VIDINTCON0);
 104         }
 105
 106         return 0;
 107 }
 108
 109 static void decon_disable_vblank(struct exynos_drm_crtc *crtc)
 110 {
 111         struct decon_context *ctx = crtc->ctx;
 112
 113         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 114                 return;
 115
 116         if (test_and_clear_bit(BIT_IRQS_ENABLED, &ctx->flags))
 117                 writel(0, ctx->addr + DECON_VIDINTCON0);
 118 }
 119
 120 static void decon_setup_trigger(struct decon_context *ctx)
 121 {
 122         u32 val = (ctx->out_type != IFTYPE_HDMI)
 123                 ? TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
 124                   TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN
 125                 : TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
 126                   TRIGCON_HWTRIGMASK_I80_RGB | TRIGCON_HWTRIGEN_I80_RGB;
 127         writel(val, ctx->addr + DECON_TRIGCON);
 128 }
 129
 130 static void decon_commit(struct exynos_drm_crtc *crtc)
 131 {
 132         struct decon_context *ctx = crtc->ctx;
 133         struct drm_display_mode *m = &crtc->base.mode;
 134         u32 val;
 135
 136         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 137                 return;
 138
 139         if (ctx->out_type == IFTYPE_HDMI) {
 140                 m->crtc_hsync_start = m->crtc_hdisplay + 10;
 141                 m->crtc_hsync_end = m->crtc_htotal - 92;
 142                 m->crtc_vsync_start = m->crtc_vdisplay + 1;
 143                 m->crtc_vsync_end = m->crtc_vsync_start + 1;
 144         }
 145
 146         decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID, 0);
 147
 148         /* enable clock gate */
 149         val = CMU_CLKGAGE_MODE_SFR_F | CMU_CLKGAGE_MODE_MEM_F;
 150         writel(val, ctx->addr + DECON_CMU);
 151
 152         /* lcd on and use command if */
 153         val = VIDOUT_LCD_ON;
 154         if (ctx->out_type == IFTYPE_I80)
 155                 val |= VIDOUT_COMMAND_IF;
 156         else
 157                 val |= VIDOUT_RGB_IF;
 158         writel(val, ctx->addr + DECON_VIDOUTCON0);
 159
 160         val = VIDTCON2_LINEVAL(m->vdisplay - 1) |
 161                 VIDTCON2_HOZVAL(m->hdisplay - 1);
 162         writel(val, ctx->addr + DECON_VIDTCON2);
 163
 164         if (ctx->out_type != IFTYPE_I80) {
 165                 val = VIDTCON00_VBPD_F(
 166                                 m->crtc_vtotal - m->crtc_vsync_end - 1) |
 167                         VIDTCON00_VFPD_F(
 168                                 m->crtc_vsync_start - m->crtc_vdisplay - 1);
 169                 writel(val, ctx->addr + DECON_VIDTCON00);
 170
 171                 val = VIDTCON01_VSPW_F(
 172                                 m->crtc_vsync_end - m->crtc_vsync_start - 1);
 173                 writel(val, ctx->addr + DECON_VIDTCON01);
 174
 175                 val = VIDTCON10_HBPD_F(
 176                                 m->crtc_htotal - m->crtc_hsync_end - 1) |
 177                         VIDTCON10_HFPD_F(
 178                                 m->crtc_hsync_start - m->crtc_hdisplay - 1);
 179                 writel(val, ctx->addr + DECON_VIDTCON10);
 180
 181                 val = VIDTCON11_HSPW_F(
 182                                 m->crtc_hsync_end - m->crtc_hsync_start - 1);
 183                 writel(val, ctx->addr + DECON_VIDTCON11);
 184         }
 185
 186         decon_setup_trigger(ctx);
 187
 188         /* enable output and display signal */
 189         decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID | VIDCON0_ENVID_F, ~0);
 190
 191         decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
 192 }
 193
 194 static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win,
 195                                  struct drm_framebuffer *fb)
 196 {
 197         unsigned long val;
 198
 199         val = readl(ctx->addr + DECON_WINCONx(win));
 200         val &= ~WINCONx_BPPMODE_MASK;
 201
 202         switch (fb->pixel_format) {
 203         case DRM_FORMAT_XRGB1555:
 204                 val |= WINCONx_BPPMODE_16BPP_I1555;
 205                 val |= WINCONx_HAWSWP_F;
 206                 val |= WINCONx_BURSTLEN_16WORD;
 207                 break;
 208         case DRM_FORMAT_RGB565:
 209                 val |= WINCONx_BPPMODE_16BPP_565;
 210                 val |= WINCONx_HAWSWP_F;
 211                 val |= WINCONx_BURSTLEN_16WORD;
 212                 break;
 213         case DRM_FORMAT_XRGB8888:
 214                 val |= WINCONx_BPPMODE_24BPP_888;
 215                 val |= WINCONx_WSWP_F;
 216                 val |= WINCONx_BURSTLEN_16WORD;
 217                 break;
 218         case DRM_FORMAT_ARGB8888:
 219                 val |= WINCONx_BPPMODE_32BPP_A8888;
 220                 val |= WINCONx_WSWP_F | WINCONx_BLD_PIX_F | WINCONx_ALPHA_SEL_F;
 221                 val |= WINCONx_BURSTLEN_16WORD;
 222                 break;
 223         default:
 224                 DRM_ERROR("Proper pixel format is not set\n");
 225                 return;
 226         }
 227
 228         DRM_DEBUG_KMS("bpp = %u\n", fb->bits_per_pixel);
 229
 230         /*
 231          * In case of exynos, setting dma-burst to 16Word causes permanent
 232          * tearing for very small buffers, e.g. cursor buffer. Burst Mode
 233          * switching which is based on plane size is not recommended as
 234          * plane size varies a lot towards the end of the screen and rapid
 235          * movement causes unstable DMA which results into iommu crash/tear.
 236          */
 237
 238         if (fb->width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
 239                 val &= ~WINCONx_BURSTLEN_MASK;
 240                 val |= WINCONx_BURSTLEN_8WORD;
 241         }
 242
 243         writel(val, ctx->addr + DECON_WINCONx(win));
 244 }
 245
 246 static void decon_shadow_protect_win(struct decon_context *ctx, int win,
 247                                         bool protect)
 248 {
 249         decon_set_bits(ctx, DECON_SHADOWCON, SHADOWCON_Wx_PROTECT(win),
 250                        protect ? ~0 : 0);
 251 }
 252
 253 static void decon_atomic_begin(struct exynos_drm_crtc *crtc)
 254 {
 255         struct decon_context *ctx = crtc->ctx;
 256         int i;
 257
 258         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 259                 return;
 260
 261         for (i = ctx->first_win; i < WINDOWS_NR; i++)
 262                 decon_shadow_protect_win(ctx, i, true);
 263 }
 264
 265 #define BIT_VAL(x, e, s) (((x) & ((1 << ((e) - (s) + 1)) - 1)) << (s))
 266 #define COORDINATE_X(x) BIT_VAL((x), 23, 12)
 267 #define COORDINATE_Y(x) BIT_VAL((x), 11, 0)
 268
 269 static void decon_update_plane(struct exynos_drm_crtc *crtc,
 270                                struct exynos_drm_plane *plane)
 271 {
 272         struct exynos_drm_plane_state *state =
 273                                 to_exynos_plane_state(plane->base.state);
 274         struct decon_context *ctx = crtc->ctx;
 275         struct drm_framebuffer *fb = state->base.fb;
 276         unsigned int win = plane->index;
 277         unsigned int bpp = fb->bits_per_pixel >> 3;
 278         unsigned int pitch = fb->pitches[0];
 279         dma_addr_t dma_addr = exynos_drm_fb_dma_addr(fb, 0);
 280         u32 val;
 281
 282         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 283                 return;
 284
 285         val = COORDINATE_X(state->crtc.x) | COORDINATE_Y(state->crtc.y);
 286         writel(val, ctx->addr + DECON_VIDOSDxA(win));
 287
 288         val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) |
 289                 COORDINATE_Y(state->crtc.y + state->crtc.h - 1);
 290         writel(val, ctx->addr + DECON_VIDOSDxB(win));
 291
 292         val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) |
 293                 VIDOSD_Wx_ALPHA_B_F(0x0);
 294         writel(val, ctx->addr + DECON_VIDOSDxC(win));
 295
 296         val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) |
 297                 VIDOSD_Wx_ALPHA_B_F(0x0);
 298         writel(val, ctx->addr + DECON_VIDOSDxD(win));
 299
 300         writel(dma_addr, ctx->addr + DECON_VIDW0xADD0B0(win));
 301
 302         val = dma_addr + pitch * state->src.h;
 303         writel(val, ctx->addr + DECON_VIDW0xADD1B0(win));
 304
 305         if (ctx->out_type != IFTYPE_HDMI)
 306                 val = BIT_VAL(pitch - state->crtc.w * bpp, 27, 14)
 307                         | BIT_VAL(state->crtc.w * bpp, 13, 0);
 308         else
 309                 val = BIT_VAL(pitch - state->crtc.w * bpp, 29, 15)
 310                         | BIT_VAL(state->crtc.w * bpp, 14, 0);
 311         writel(val, ctx->addr + DECON_VIDW0xADD2(win));
 312
 313         decon_win_set_pixfmt(ctx, win, fb);
 314
 315         /* window enable */
 316         decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, ~0);
 317 }
 318
 319 static void decon_disable_plane(struct exynos_drm_crtc *crtc,
 320                                 struct exynos_drm_plane *plane)
 321 {
 322         struct decon_context *ctx = crtc->ctx;
 323         unsigned int win = plane->index;
 324
 325         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 326                 return;
 327
 328         decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
 329 }
 330
 331 static void decon_atomic_flush(struct exynos_drm_crtc *crtc)
 332 {
 333         struct decon_context *ctx = crtc->ctx;
 334         int i;
 335
 336         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 337                 return;
 338
 339         for (i = ctx->first_win; i < WINDOWS_NR; i++)
 340                 decon_shadow_protect_win(ctx, i, false);
 341
 342         /* standalone update */
 343         decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
 344
 345         if (ctx->out_type == IFTYPE_I80)
 346                 set_bit(BIT_WIN_UPDATED, &ctx->flags);
 347 }
 348
 349 static void decon_swreset(struct decon_context *ctx)
 350 {
 351         unsigned int tries;
 352
 353         writel(0, ctx->addr + DECON_VIDCON0);
 354         for (tries = 2000; tries; --tries) {
 355                 if (~readl(ctx->addr + DECON_VIDCON0) & VIDCON0_STOP_STATUS)
 356                         break;
 357                 udelay(10);
 358         }
 359
 360         WARN(tries == 0, "failed to disable DECON\n");
 361
 362         writel(VIDCON0_SWRESET, ctx->addr + DECON_VIDCON0);
 363         for (tries = 2000; tries; --tries) {
 364                 if (~readl(ctx->addr + DECON_VIDCON0) & VIDCON0_SWRESET)
 365                         break;
 366                 udelay(10);
 367         }
 368
 369         WARN(tries == 0, "failed to software reset DECON\n");
 370
 371         if (ctx->out_type != IFTYPE_HDMI)
 372                 return;
 373
 374         writel(VIDCON0_CLKVALUP | VIDCON0_VLCKFREE, ctx->addr + DECON_VIDCON0);
 375         decon_set_bits(ctx, DECON_CMU,
 376                        CMU_CLKGAGE_MODE_SFR_F | CMU_CLKGAGE_MODE_MEM_F, ~0);
 377         writel(VIDCON1_VCLK_RUN_VDEN_DISABLE, ctx->addr + DECON_VIDCON1);
 378         writel(CRCCTRL_CRCEN | CRCCTRL_CRCSTART_F | CRCCTRL_CRCCLKEN,
 379                ctx->addr + DECON_CRCCTRL);
 380         decon_setup_trigger(ctx);
 381 }
 382
 383 static void decon_enable(struct exynos_drm_crtc *crtc)
 384 {
 385         struct decon_context *ctx = crtc->ctx;
 386
 387         if (!test_and_clear_bit(BIT_SUSPENDED, &ctx->flags))
 388                 return;
 389
 390         pm_runtime_get_sync(ctx->dev);
 391
 392         set_bit(BIT_CLKS_ENABLED, &ctx->flags);
 393
 394         decon_swreset(ctx);
 395
 396         /* if vblank was enabled status, enable it again. */
 397         if (test_and_clear_bit(BIT_IRQS_ENABLED, &ctx->flags))
 398                 decon_enable_vblank(ctx->crtc);
 399
 400         decon_commit(ctx->crtc);
 401 }
 402
 403 static void decon_disable(struct exynos_drm_crtc *crtc)
 404 {
 405         struct decon_context *ctx = crtc->ctx;
 406         int i;
 407
 408         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 409                 return;
 410
 411         /*
 412          * We need to make sure that all windows are disabled before we
 413          * suspend that connector. Otherwise we might try to scan from
 414          * a destroyed buffer later.
 415          */
 416         for (i = ctx->first_win; i < WINDOWS_NR; i++)
 417                 decon_disable_plane(crtc, &ctx->planes[i]);
 418
 419         decon_swreset(ctx);
 420
 421         clear_bit(BIT_CLKS_ENABLED, &ctx->flags);
 422
 423         pm_runtime_put_sync(ctx->dev);
 424
 425         set_bit(BIT_SUSPENDED, &ctx->flags);
 426 }
 427
 428 static void decon_te_irq_handler(struct exynos_drm_crtc *crtc)
 429 {
 430         struct decon_context *ctx = crtc->ctx;
 431
 432         if (!test_bit(BIT_CLKS_ENABLED, &ctx->flags))
 433                 return;
 434
 435         if (test_and_clear_bit(BIT_WIN_UPDATED, &ctx->flags))
 436                 decon_set_bits(ctx, DECON_TRIGCON, TRIGCON_SWTRIGCMD, ~0);
 437
 438         drm_crtc_handle_vblank(&ctx->crtc->base);
 439 }
 440
 441 static void decon_clear_channels(struct exynos_drm_crtc *crtc)
 442 {
 443         struct decon_context *ctx = crtc->ctx;
 444         int win, i, ret;
 445
 446         DRM_DEBUG_KMS("%s\n", __FILE__);
 447
 448         for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
 449                 ret = clk_prepare_enable(ctx->clks[i]);
 450                 if (ret < 0)
 451                         goto err;
 452         }
 453
 454         for (win = 0; win < WINDOWS_NR; win++) {
 455                 decon_shadow_protect_win(ctx, win, true);
 456                 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
 457                 decon_shadow_protect_win(ctx, win, false);
 458         }
 459
 460         decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
 461
 462         /* TODO: wait for possible vsync */
 463         msleep(50);
 464
 465 err:
 466         while (--i >= 0)
 467                 clk_disable_unprepare(ctx->clks[i]);
 468 }
 469
 470 static struct exynos_drm_crtc_ops decon_crtc_ops = {
 471         .enable                 = decon_enable,
 472         .disable                = decon_disable,
 473         .enable_vblank          = decon_enable_vblank,
 474         .disable_vblank         = decon_disable_vblank,
 475         .atomic_begin           = decon_atomic_begin,
 476         .update_plane           = decon_update_plane,
 477         .disable_plane          = decon_disable_plane,
 478         .atomic_flush           = decon_atomic_flush,
 479         .te_handler             = decon_te_irq_handler,
 480 };
 481
 482 static int decon_bind(struct device *dev, struct device *master, void *data)
 483 {
 484         struct decon_context *ctx = dev_get_drvdata(dev);
 485         struct drm_device *drm_dev = data;
 486         struct exynos_drm_private *priv = drm_dev->dev_private;
 487         struct exynos_drm_plane *exynos_plane;
 488         enum exynos_drm_output_type out_type;
 489         unsigned int win;
 490         int ret;
 491
 492         ctx->drm_dev = drm_dev;
 493         ctx->pipe = priv->pipe++;
 494
 495         for (win = ctx->first_win; win < WINDOWS_NR; win++) {
 496                 int tmp = (win == ctx->first_win) ? 0 : win;
 497
 498                 ctx->configs[win].pixel_formats = decon_formats;
 499                 ctx->configs[win].num_pixel_formats = ARRAY_SIZE(decon_formats);
 500                 ctx->configs[win].zpos = win;
 501                 ctx->configs[win].type = decon_win_types[tmp];
 502
 503                 ret = exynos_plane_init(drm_dev, &ctx->planes[win], win,
 504                                         1 << ctx->pipe, &ctx->configs[win]);
 505                 if (ret)
 506                         return ret;
 507         }
 508
 509         exynos_plane = &ctx->planes[ctx->first_win];
 510         out_type = (ctx->out_type == IFTYPE_HDMI) ? EXYNOS_DISPLAY_TYPE_HDMI
 511                                                   : EXYNOS_DISPLAY_TYPE_LCD;
 512         ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
 513                                         ctx->pipe, out_type,
 514                                         &decon_crtc_ops, ctx);
 515         if (IS_ERR(ctx->crtc)) {
 516                 ret = PTR_ERR(ctx->crtc);
 517                 goto err;
 518         }
 519
 520         decon_clear_channels(ctx->crtc);
 521
 522         ret = drm_iommu_attach_device(drm_dev, dev);
 523         if (ret)
 524                 goto err;
 525
 526         return ret;
 527 err:
 528         priv->pipe--;
 529         return ret;
 530 }
 531
 532 static void decon_unbind(struct device *dev, struct device *master, void *data)
 533 {
 534         struct decon_context *ctx = dev_get_drvdata(dev);
 535
 536         decon_disable(ctx->crtc);
 537
 538         /* detach this sub driver from iommu mapping if supported. */
 539         drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
 540 }
 541
 542 static const struct component_ops decon_component_ops = {
 543         .bind   = decon_bind,
 544         .unbind = decon_unbind,
 545 };
 546
 547 static irqreturn_t decon_irq_handler(int irq, void *dev_id)
 548 {
 549         struct decon_context *ctx = dev_id;
 550         u32 val;
 551         int win;
 552
 553         if (!test_bit(BIT_CLKS_ENABLED, &ctx->flags))
 554                 goto out;
 555
 556         val = readl(ctx->addr + DECON_VIDINTCON1);
 557         val &= VIDINTCON1_INTFRMDONEPEND | VIDINTCON1_INTFRMPEND;
 558
 559         if (val) {
 560                 for (win = ctx->first_win; win < WINDOWS_NR ; win++) {
 561                         struct exynos_drm_plane *plane = &ctx->planes[win];
 562
 563                         if (!plane->pending_fb)
 564                                 continue;
 565
 566                         exynos_drm_crtc_finish_update(ctx->crtc, plane);
 567                 }
 568
 569                 /* clear */
 570                 writel(val, ctx->addr + DECON_VIDINTCON1);
 571         }
 572
 573 out:
 574         return IRQ_HANDLED;
 575 }
 576
 577 #ifdef CONFIG_PM
 578 static int exynos5433_decon_suspend(struct device *dev)
 579 {
 580         struct decon_context *ctx = dev_get_drvdata(dev);
 581         int i = ARRAY_SIZE(decon_clks_name);
 582
 583         while (--i >= 0)
 584                 clk_disable_unprepare(ctx->clks[i]);
 585
 586         return 0;
 587 }
 588
 589 static int exynos5433_decon_resume(struct device *dev)
 590 {
 591         struct decon_context *ctx = dev_get_drvdata(dev);
 592         int i, ret;
 593
 594         for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
 595                 ret = clk_prepare_enable(ctx->clks[i]);
 596                 if (ret < 0)
 597                         goto err;
 598         }
 599
 600         return 0;
 601
 602 err:
 603         while (--i >= 0)
 604                 clk_disable_unprepare(ctx->clks[i]);
 605
 606         return ret;
 607 }
 608 #endif
 609
 610 static const struct dev_pm_ops exynos5433_decon_pm_ops = {
 611         SET_RUNTIME_PM_OPS(exynos5433_decon_suspend, exynos5433_decon_resume,
 612                            NULL)
 613 };
 614
 615 static const struct of_device_id exynos5433_decon_driver_dt_match[] = {
 616         {
 617                 .compatible = "samsung,exynos5433-decon",
 618                 .data = (void *)IFTYPE_RGB
 619         },
 620         {
 621                 .compatible = "samsung,exynos5433-decon-tv",
 622                 .data = (void *)IFTYPE_HDMI
 623         },
 624         {},
 625 };
 626 MODULE_DEVICE_TABLE(of, exynos5433_decon_driver_dt_match);
 627
 628 static int exynos5433_decon_probe(struct platform_device *pdev)
 629 {
 630         const struct of_device_id *of_id;
 631         struct device *dev = &pdev->dev;
 632         struct decon_context *ctx;
 633         struct resource *res;
 634         int ret;
 635         int i;
 636
 637         ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
 638         if (!ctx)
 639                 return -ENOMEM;
 640
 641         __set_bit(BIT_SUSPENDED, &ctx->flags);
 642         ctx->dev = dev;
 643
 644         of_id = of_match_device(exynos5433_decon_driver_dt_match, &pdev->dev);
 645         ctx->out_type = (enum decon_iftype)of_id->data;
 646
 647         if (ctx->out_type == IFTYPE_HDMI)
 648                 ctx->first_win = 1;
 649         else if (of_get_child_by_name(dev->of_node, "i80-if-timings"))
 650                 ctx->out_type = IFTYPE_I80;
 651
 652         for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
 653                 struct clk *clk;
 654
 655                 clk = devm_clk_get(ctx->dev, decon_clks_name[i]);
 656                 if (IS_ERR(clk))
 657                         return PTR_ERR(clk);
 658
 659                 ctx->clks[i] = clk;
 660         }
 661
 662         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 663         if (!res) {
 664                 dev_err(dev, "cannot find IO resource\n");
 665                 return -ENXIO;
 666         }
 667
 668         ctx->addr = devm_ioremap_resource(dev, res);
 669         if (IS_ERR(ctx->addr)) {
 670                 dev_err(dev, "ioremap failed\n");
 671                 return PTR_ERR(ctx->addr);
 672         }
 673
 674         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
 675                         (ctx->out_type == IFTYPE_I80) ? "lcd_sys" : "vsync");
 676         if (!res) {
 677                 dev_err(dev, "cannot find IRQ resource\n");
 678                 return -ENXIO;
 679         }
 680
 681         ret = devm_request_irq(dev, res->start, decon_irq_handler, 0,
 682                                "drm_decon", ctx);
 683         if (ret < 0) {
 684                 dev_err(dev, "lcd_sys irq request failed\n");
 685                 return ret;
 686         }
 687
 688         platform_set_drvdata(pdev, ctx);
 689
 690         pm_runtime_enable(dev);
 691
 692         ret = component_add(dev, &decon_component_ops);
 693         if (ret)
 694                 goto err_disable_pm_runtime;
 695
 696         return 0;
 697
 698 err_disable_pm_runtime:
 699         pm_runtime_disable(dev);
 700
 701         return ret;
 702 }
 703
 704 static int exynos5433_decon_remove(struct platform_device *pdev)
 705 {
 706         pm_runtime_disable(&pdev->dev);
 707
 708         component_del(&pdev->dev, &decon_component_ops);
 709
 710         return 0;
 711 }
 712
 713 struct platform_driver exynos5433_decon_driver = {
 714         .probe          = exynos5433_decon_probe,
 715         .remove         = exynos5433_decon_remove,
 716         .driver         = {
 717                 .name   = "exynos5433-decon",
 718                 .pm     = &exynos5433_decon_pm_ops,
 719                 .of_match_table = exynos5433_decon_driver_dt_match,
 720         },
 721 };