drivers/gpu/drm/exynos/exynos5433_drm_decon.c

   1 /* drivers/gpu/drm/exynos5433_drm_decon.c
   2  *
   3  * Copyright (C) 2015 Samsung Electronics Co.Ltd
   4  * Authors:
   5  *      Joonyoung Shim <jy0922.shim@samsung.com>
   6  *      Hyungwon Hwang <human.hwang@samsung.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundationr
  11  */
  12
  13 #include <linux/platform_device.h>
  14 #include <linux/clk.h>
  15 #include <linux/component.h>
  16 #include <linux/mfd/syscon.h>
  17 #include <linux/of_device.h>
  18 #include <linux/of_gpio.h>
  19 #include <linux/pm_runtime.h>
  20 #include <linux/regmap.h>
  21
  22 #include <video/exynos5433_decon.h>
  23
  24 #include "exynos_drm_drv.h"
  25 #include "exynos_drm_crtc.h"
  26 #include "exynos_drm_fb.h"
  27 #include "exynos_drm_plane.h"
  28 #include "exynos_drm_iommu.h"
  29
  30 #define DSD_CFG_MUX 0x1004
  31 #define DSD_CFG_MUX_TE_UNMASK_GLOBAL BIT(13)
  32
  33 #define WINDOWS_NR      3
  34 #define MIN_FB_WIDTH_FOR_16WORD_BURST   128
  35
  36 #define IFTYPE_I80      (1 << 0)
  37 #define I80_HW_TRG      (1 << 1)
  38 #define IFTYPE_HDMI     (1 << 2)
  39
  40 static const char * const decon_clks_name[] = {
  41         "pclk",
  42         "aclk_decon",
  43         "aclk_smmu_decon0x",
  44         "aclk_xiu_decon0x",
  45         "pclk_smmu_decon0x",
  46         "sclk_decon_vclk",
  47         "sclk_decon_eclk",
  48 };
  49
  50 enum decon_flag_bits {
  51         BIT_CLKS_ENABLED,
  52         BIT_IRQS_ENABLED,
  53         BIT_WIN_UPDATED,
  54         BIT_SUSPENDED
  55 };
  56
  57 struct decon_context {
  58         struct device                   *dev;
  59         struct drm_device               *drm_dev;
  60         struct exynos_drm_crtc          *crtc;
  61         struct exynos_drm_plane         planes[WINDOWS_NR];
  62         struct exynos_drm_plane_config  configs[WINDOWS_NR];
  63         void __iomem                    *addr;
  64         struct regmap                   *sysreg;
  65         struct clk                      *clks[ARRAY_SIZE(decon_clks_name)];
  66         unsigned long                   flags;
  67         unsigned long                   out_type;
  68         int                             first_win;
  69         spinlock_t                      vblank_lock;
  70         u32                             frame_id;
  71 };
  72
  73 static const uint32_t decon_formats[] = {
  74         DRM_FORMAT_XRGB1555,
  75         DRM_FORMAT_RGB565,
  76         DRM_FORMAT_XRGB8888,
  77         DRM_FORMAT_ARGB8888,
  78 };
  79
  80 static const enum drm_plane_type decon_win_types[WINDOWS_NR] = {
  81         DRM_PLANE_TYPE_PRIMARY,
  82         DRM_PLANE_TYPE_OVERLAY,
  83         DRM_PLANE_TYPE_CURSOR,
  84 };
  85
  86 static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask,
  87                                   u32 val)
  88 {
  89         val = (val & mask) | (readl(ctx->addr + reg) & ~mask);
  90         writel(val, ctx->addr + reg);
  91 }
  92
  93 static int decon_enable_vblank(struct exynos_drm_crtc *crtc)
  94 {
  95         struct decon_context *ctx = crtc->ctx;
  96         u32 val;
  97
  98         if (test_bit(BIT_SUSPENDED, &ctx->flags))
  99                 return -EPERM;
 100
 101         if (!test_and_set_bit(BIT_IRQS_ENABLED, &ctx->flags)) {
 102                 val = VIDINTCON0_INTEN;
 103                 if (ctx->out_type & IFTYPE_I80)
 104                         val |= VIDINTCON0_FRAMEDONE;
 105                 else
 106                         val |= VIDINTCON0_INTFRMEN | VIDINTCON0_FRAMESEL_FP;
 107
 108                 writel(val, ctx->addr + DECON_VIDINTCON0);
 109         }
 110
 111         return 0;
 112 }
 113
 114 static void decon_disable_vblank(struct exynos_drm_crtc *crtc)
 115 {
 116         struct decon_context *ctx = crtc->ctx;
 117
 118         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 119                 return;
 120
 121         if (test_and_clear_bit(BIT_IRQS_ENABLED, &ctx->flags))
 122                 writel(0, ctx->addr + DECON_VIDINTCON0);
 123 }
 124
 125 /* return number of starts/ends of frame transmissions since reset */
 126 static u32 decon_get_frame_count(struct decon_context *ctx, bool end)
 127 {
 128         u32 frm, pfrm, status, cnt = 2;
 129
 130         /* To get consistent result repeat read until frame id is stable.
 131          * Usually the loop will be executed once, in rare cases when the loop
 132          * is executed at frame change time 2nd pass will be needed.
 133          */
 134         frm = readl(ctx->addr + DECON_CRFMID);
 135         do {
 136                 status = readl(ctx->addr + DECON_VIDCON1);
 137                 pfrm = frm;
 138                 frm = readl(ctx->addr + DECON_CRFMID);
 139         } while (frm != pfrm && --cnt);
 140
 141         /* CRFMID is incremented on BPORCH in case of I80 and on VSYNC in case
 142          * of RGB, it should be taken into account.
 143          */
 144         if (!frm)
 145                 return 0;
 146
 147         switch (status & (VIDCON1_VSTATUS_MASK | VIDCON1_I80_ACTIVE)) {
 148         case VIDCON1_VSTATUS_VS:
 149                 if (!(ctx->out_type & IFTYPE_I80))
 150                         --frm;
 151                 break;
 152         case VIDCON1_VSTATUS_BP:
 153                 --frm;
 154                 break;
 155         case VIDCON1_I80_ACTIVE:
 156         case VIDCON1_VSTATUS_AC:
 157                 if (end)
 158                         --frm;
 159                 break;
 160         default:
 161                 break;
 162         }
 163
 164         return frm;
 165 }
 166
 167 static u32 decon_get_vblank_counter(struct exynos_drm_crtc *crtc)
 168 {
 169         struct decon_context *ctx = crtc->ctx;
 170
 171         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 172                 return 0;
 173
 174         return decon_get_frame_count(ctx, false);
 175 }
 176
 177 static void decon_setup_trigger(struct decon_context *ctx)
 178 {
 179         if (!(ctx->out_type & (IFTYPE_I80 | I80_HW_TRG)))
 180                 return;
 181
 182         if (!(ctx->out_type & I80_HW_TRG)) {
 183                 writel(TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
 184                        TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN,
 185                        ctx->addr + DECON_TRIGCON);
 186                 return;
 187         }
 188
 189         writel(TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F | TRIGCON_HWTRIGMASK
 190                | TRIGCON_HWTRIGEN, ctx->addr + DECON_TRIGCON);
 191
 192         if (regmap_update_bits(ctx->sysreg, DSD_CFG_MUX,
 193                                DSD_CFG_MUX_TE_UNMASK_GLOBAL, ~0))
 194                 DRM_ERROR("Cannot update sysreg.\n");
 195 }
 196
 197 static void decon_commit(struct exynos_drm_crtc *crtc)
 198 {
 199         struct decon_context *ctx = crtc->ctx;
 200         struct drm_display_mode *m = &crtc->base.mode;
 201         bool interlaced = false;
 202         u32 val;
 203
 204         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 205                 return;
 206
 207         if (ctx->out_type & IFTYPE_HDMI) {
 208                 m->crtc_hsync_start = m->crtc_hdisplay + 10;
 209                 m->crtc_hsync_end = m->crtc_htotal - 92;
 210                 m->crtc_vsync_start = m->crtc_vdisplay + 1;
 211                 m->crtc_vsync_end = m->crtc_vsync_start + 1;
 212                 if (m->flags & DRM_MODE_FLAG_INTERLACE)
 213                         interlaced = true;
 214         }
 215
 216         decon_setup_trigger(ctx);
 217
 218         /* lcd on and use command if */
 219         val = VIDOUT_LCD_ON;
 220         if (interlaced)
 221                 val |= VIDOUT_INTERLACE_EN_F;
 222         if (ctx->out_type & IFTYPE_I80) {
 223                 val |= VIDOUT_COMMAND_IF;
 224         } else {
 225                 val |= VIDOUT_RGB_IF;
 226         }
 227
 228         writel(val, ctx->addr + DECON_VIDOUTCON0);
 229
 230         if (interlaced)
 231                 val = VIDTCON2_LINEVAL(m->vdisplay / 2 - 1) |
 232                         VIDTCON2_HOZVAL(m->hdisplay - 1);
 233         else
 234                 val = VIDTCON2_LINEVAL(m->vdisplay - 1) |
 235                         VIDTCON2_HOZVAL(m->hdisplay - 1);
 236         writel(val, ctx->addr + DECON_VIDTCON2);
 237
 238         if (!(ctx->out_type & IFTYPE_I80)) {
 239                 int vbp = m->crtc_vtotal - m->crtc_vsync_end;
 240                 int vfp = m->crtc_vsync_start - m->crtc_vdisplay;
 241
 242                 if (interlaced)
 243                         vbp = vbp / 2 - 1;
 244                 val = VIDTCON00_VBPD_F(vbp - 1) | VIDTCON00_VFPD_F(vfp - 1);
 245                 writel(val, ctx->addr + DECON_VIDTCON00);
 246
 247                 val = VIDTCON01_VSPW_F(
 248                                 m->crtc_vsync_end - m->crtc_vsync_start - 1);
 249                 writel(val, ctx->addr + DECON_VIDTCON01);
 250
 251                 val = VIDTCON10_HBPD_F(
 252                                 m->crtc_htotal - m->crtc_hsync_end - 1) |
 253                         VIDTCON10_HFPD_F(
 254                                 m->crtc_hsync_start - m->crtc_hdisplay - 1);
 255                 writel(val, ctx->addr + DECON_VIDTCON10);
 256
 257                 val = VIDTCON11_HSPW_F(
 258                                 m->crtc_hsync_end - m->crtc_hsync_start - 1);
 259                 writel(val, ctx->addr + DECON_VIDTCON11);
 260         }
 261
 262         /* enable output and display signal */
 263         decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID | VIDCON0_ENVID_F, ~0);
 264
 265         decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
 266 }
 267
 268 static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win,
 269                                  struct drm_framebuffer *fb)
 270 {
 271         unsigned long val;
 272
 273         val = readl(ctx->addr + DECON_WINCONx(win));
 274         val &= ~WINCONx_BPPMODE_MASK;
 275
 276         switch (fb->format->format) {
 277         case DRM_FORMAT_XRGB1555:
 278                 val |= WINCONx_BPPMODE_16BPP_I1555;
 279                 val |= WINCONx_HAWSWP_F;
 280                 val |= WINCONx_BURSTLEN_16WORD;
 281                 break;
 282         case DRM_FORMAT_RGB565:
 283                 val |= WINCONx_BPPMODE_16BPP_565;
 284                 val |= WINCONx_HAWSWP_F;
 285                 val |= WINCONx_BURSTLEN_16WORD;
 286                 break;
 287         case DRM_FORMAT_XRGB8888:
 288                 val |= WINCONx_BPPMODE_24BPP_888;
 289                 val |= WINCONx_WSWP_F;
 290                 val |= WINCONx_BURSTLEN_16WORD;
 291                 break;
 292         case DRM_FORMAT_ARGB8888:
 293                 val |= WINCONx_BPPMODE_32BPP_A8888;
 294                 val |= WINCONx_WSWP_F | WINCONx_BLD_PIX_F | WINCONx_ALPHA_SEL_F;
 295                 val |= WINCONx_BURSTLEN_16WORD;
 296                 break;
 297         default:
 298                 DRM_ERROR("Proper pixel format is not set\n");
 299                 return;
 300         }
 301
 302         DRM_DEBUG_KMS("bpp = %u\n", fb->format->cpp[0] * 8);
 303
 304         /*
 305          * In case of exynos, setting dma-burst to 16Word causes permanent
 306          * tearing for very small buffers, e.g. cursor buffer. Burst Mode
 307          * switching which is based on plane size is not recommended as
 308          * plane size varies a lot towards the end of the screen and rapid
 309          * movement causes unstable DMA which results into iommu crash/tear.
 310          */
 311
 312         if (fb->width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
 313                 val &= ~WINCONx_BURSTLEN_MASK;
 314                 val |= WINCONx_BURSTLEN_8WORD;
 315         }
 316
 317         writel(val, ctx->addr + DECON_WINCONx(win));
 318 }
 319
 320 static void decon_shadow_protect_win(struct decon_context *ctx, int win,
 321                                         bool protect)
 322 {
 323         decon_set_bits(ctx, DECON_SHADOWCON, SHADOWCON_Wx_PROTECT(win),
 324                        protect ? ~0 : 0);
 325 }
 326
 327 static void decon_atomic_begin(struct exynos_drm_crtc *crtc)
 328 {
 329         struct decon_context *ctx = crtc->ctx;
 330         int i;
 331
 332         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 333                 return;
 334
 335         for (i = ctx->first_win; i < WINDOWS_NR; i++)
 336                 decon_shadow_protect_win(ctx, i, true);
 337 }
 338
 339 #define BIT_VAL(x, e, s) (((x) & ((1 << ((e) - (s) + 1)) - 1)) << (s))
 340 #define COORDINATE_X(x) BIT_VAL((x), 23, 12)
 341 #define COORDINATE_Y(x) BIT_VAL((x), 11, 0)
 342
 343 static void decon_update_plane(struct exynos_drm_crtc *crtc,
 344                                struct exynos_drm_plane *plane)
 345 {
 346         struct exynos_drm_plane_state *state =
 347                                 to_exynos_plane_state(plane->base.state);
 348         struct decon_context *ctx = crtc->ctx;
 349         struct drm_framebuffer *fb = state->base.fb;
 350         unsigned int win = plane->index;
 351         unsigned int bpp = fb->format->cpp[0];
 352         unsigned int pitch = fb->pitches[0];
 353         dma_addr_t dma_addr = exynos_drm_fb_dma_addr(fb, 0);
 354         u32 val;
 355
 356         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 357                 return;
 358
 359         if (crtc->base.mode.flags & DRM_MODE_FLAG_INTERLACE) {
 360                 val = COORDINATE_X(state->crtc.x) |
 361                         COORDINATE_Y(state->crtc.y / 2);
 362                 writel(val, ctx->addr + DECON_VIDOSDxA(win));
 363
 364                 val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) |
 365                         COORDINATE_Y((state->crtc.y + state->crtc.h) / 2 - 1);
 366                 writel(val, ctx->addr + DECON_VIDOSDxB(win));
 367         } else {
 368                 val = COORDINATE_X(state->crtc.x) | COORDINATE_Y(state->crtc.y);
 369                 writel(val, ctx->addr + DECON_VIDOSDxA(win));
 370
 371                 val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) |
 372                                 COORDINATE_Y(state->crtc.y + state->crtc.h - 1);
 373                 writel(val, ctx->addr + DECON_VIDOSDxB(win));
 374         }
 375
 376         val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) |
 377                 VIDOSD_Wx_ALPHA_B_F(0x0);
 378         writel(val, ctx->addr + DECON_VIDOSDxC(win));
 379
 380         val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) |
 381                 VIDOSD_Wx_ALPHA_B_F(0x0);
 382         writel(val, ctx->addr + DECON_VIDOSDxD(win));
 383
 384         writel(dma_addr, ctx->addr + DECON_VIDW0xADD0B0(win));
 385
 386         val = dma_addr + pitch * state->src.h;
 387         writel(val, ctx->addr + DECON_VIDW0xADD1B0(win));
 388
 389         if (!(ctx->out_type & IFTYPE_HDMI))
 390                 val = BIT_VAL(pitch - state->crtc.w * bpp, 27, 14)
 391                         | BIT_VAL(state->crtc.w * bpp, 13, 0);
 392         else
 393                 val = BIT_VAL(pitch - state->crtc.w * bpp, 29, 15)
 394                         | BIT_VAL(state->crtc.w * bpp, 14, 0);
 395         writel(val, ctx->addr + DECON_VIDW0xADD2(win));
 396
 397         decon_win_set_pixfmt(ctx, win, fb);
 398
 399         /* window enable */
 400         decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, ~0);
 401 }
 402
 403 static void decon_disable_plane(struct exynos_drm_crtc *crtc,
 404                                 struct exynos_drm_plane *plane)
 405 {
 406         struct decon_context *ctx = crtc->ctx;
 407         unsigned int win = plane->index;
 408
 409         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 410                 return;
 411
 412         decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
 413 }
 414
 415 static void decon_atomic_flush(struct exynos_drm_crtc *crtc)
 416 {
 417         struct decon_context *ctx = crtc->ctx;
 418         unsigned long flags;
 419         int i;
 420
 421         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 422                 return;
 423
 424         spin_lock_irqsave(&ctx->vblank_lock, flags);
 425
 426         for (i = ctx->first_win; i < WINDOWS_NR; i++)
 427                 decon_shadow_protect_win(ctx, i, false);
 428
 429         decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
 430
 431         if (ctx->out_type & IFTYPE_I80)
 432                 set_bit(BIT_WIN_UPDATED, &ctx->flags);
 433
 434         ctx->frame_id = decon_get_frame_count(ctx, true);
 435
 436         exynos_crtc_handle_event(crtc);
 437
 438         spin_unlock_irqrestore(&ctx->vblank_lock, flags);
 439 }
 440
 441 static void decon_swreset(struct decon_context *ctx)
 442 {
 443         unsigned int tries;
 444         unsigned long flags;
 445
 446         writel(0, ctx->addr + DECON_VIDCON0);
 447         for (tries = 2000; tries; --tries) {
 448                 if (~readl(ctx->addr + DECON_VIDCON0) & VIDCON0_STOP_STATUS)
 449                         break;
 450                 udelay(10);
 451         }
 452
 453         writel(VIDCON0_SWRESET, ctx->addr + DECON_VIDCON0);
 454         for (tries = 2000; tries; --tries) {
 455                 if (~readl(ctx->addr + DECON_VIDCON0) & VIDCON0_SWRESET)
 456                         break;
 457                 udelay(10);
 458         }
 459
 460         WARN(tries == 0, "failed to software reset DECON\n");
 461
 462         spin_lock_irqsave(&ctx->vblank_lock, flags);
 463         ctx->frame_id = 0;
 464         spin_unlock_irqrestore(&ctx->vblank_lock, flags);
 465
 466         if (!(ctx->out_type & IFTYPE_HDMI))
 467                 return;
 468
 469         writel(VIDCON0_CLKVALUP | VIDCON0_VLCKFREE, ctx->addr + DECON_VIDCON0);
 470         decon_set_bits(ctx, DECON_CMU,
 471                        CMU_CLKGAGE_MODE_SFR_F | CMU_CLKGAGE_MODE_MEM_F, ~0);
 472         writel(VIDCON1_VCLK_RUN_VDEN_DISABLE, ctx->addr + DECON_VIDCON1);
 473         writel(CRCCTRL_CRCEN | CRCCTRL_CRCSTART_F | CRCCTRL_CRCCLKEN,
 474                ctx->addr + DECON_CRCCTRL);
 475 }
 476
 477 static void decon_enable(struct exynos_drm_crtc *crtc)
 478 {
 479         struct decon_context *ctx = crtc->ctx;
 480
 481         if (!test_and_clear_bit(BIT_SUSPENDED, &ctx->flags))
 482                 return;
 483
 484         pm_runtime_get_sync(ctx->dev);
 485
 486         exynos_drm_pipe_clk_enable(crtc, true);
 487
 488         set_bit(BIT_CLKS_ENABLED, &ctx->flags);
 489
 490         decon_swreset(ctx);
 491
 492         /* if vblank was enabled status, enable it again. */
 493         if (test_and_clear_bit(BIT_IRQS_ENABLED, &ctx->flags))
 494                 decon_enable_vblank(ctx->crtc);
 495
 496         decon_commit(ctx->crtc);
 497 }
 498
 499 static void decon_disable(struct exynos_drm_crtc *crtc)
 500 {
 501         struct decon_context *ctx = crtc->ctx;
 502         int i;
 503
 504         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 505                 return;
 506
 507         /*
 508          * We need to make sure that all windows are disabled before we
 509          * suspend that connector. Otherwise we might try to scan from
 510          * a destroyed buffer later.
 511          */
 512         for (i = ctx->first_win; i < WINDOWS_NR; i++)
 513                 decon_disable_plane(crtc, &ctx->planes[i]);
 514
 515         decon_swreset(ctx);
 516
 517         clear_bit(BIT_CLKS_ENABLED, &ctx->flags);
 518
 519         exynos_drm_pipe_clk_enable(crtc, false);
 520
 521         pm_runtime_put_sync(ctx->dev);
 522
 523         set_bit(BIT_SUSPENDED, &ctx->flags);
 524 }
 525
 526 static void decon_te_irq_handler(struct exynos_drm_crtc *crtc)
 527 {
 528         struct decon_context *ctx = crtc->ctx;
 529
 530         if (!test_bit(BIT_CLKS_ENABLED, &ctx->flags) ||
 531             (ctx->out_type & I80_HW_TRG))
 532                 return;
 533
 534         if (test_and_clear_bit(BIT_WIN_UPDATED, &ctx->flags))
 535                 decon_set_bits(ctx, DECON_TRIGCON, TRIGCON_SWTRIGCMD, ~0);
 536 }
 537
 538 static void decon_clear_channels(struct exynos_drm_crtc *crtc)
 539 {
 540         struct decon_context *ctx = crtc->ctx;
 541         int win, i, ret;
 542
 543         DRM_DEBUG_KMS("%s\n", __FILE__);
 544
 545         for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
 546                 ret = clk_prepare_enable(ctx->clks[i]);
 547                 if (ret < 0)
 548                         goto err;
 549         }
 550
 551         for (win = 0; win < WINDOWS_NR; win++) {
 552                 decon_shadow_protect_win(ctx, win, true);
 553                 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
 554                 decon_shadow_protect_win(ctx, win, false);
 555         }
 556
 557         decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
 558
 559         /* TODO: wait for possible vsync */
 560         msleep(50);
 561
 562 err:
 563         while (--i >= 0)
 564                 clk_disable_unprepare(ctx->clks[i]);
 565 }
 566
 567 static const struct exynos_drm_crtc_ops decon_crtc_ops = {
 568         .enable                 = decon_enable,
 569         .disable                = decon_disable,
 570         .enable_vblank          = decon_enable_vblank,
 571         .disable_vblank         = decon_disable_vblank,
 572         .get_vblank_counter     = decon_get_vblank_counter,
 573         .atomic_begin           = decon_atomic_begin,
 574         .update_plane           = decon_update_plane,
 575         .disable_plane          = decon_disable_plane,
 576         .atomic_flush           = decon_atomic_flush,
 577         .te_handler             = decon_te_irq_handler,
 578 };
 579
 580 static int decon_bind(struct device *dev, struct device *master, void *data)
 581 {
 582         struct decon_context *ctx = dev_get_drvdata(dev);
 583         struct drm_device *drm_dev = data;
 584         struct exynos_drm_plane *exynos_plane;
 585         enum exynos_drm_output_type out_type;
 586         unsigned int win;
 587         int ret;
 588
 589         ctx->drm_dev = drm_dev;
 590         drm_dev->max_vblank_count = 0xffffffff;
 591
 592         for (win = ctx->first_win; win < WINDOWS_NR; win++) {
 593                 int tmp = (win == ctx->first_win) ? 0 : win;
 594
 595                 ctx->configs[win].pixel_formats = decon_formats;
 596                 ctx->configs[win].num_pixel_formats = ARRAY_SIZE(decon_formats);
 597                 ctx->configs[win].zpos = win;
 598                 ctx->configs[win].type = decon_win_types[tmp];
 599
 600                 ret = exynos_plane_init(drm_dev, &ctx->planes[win], win,
 601                                         &ctx->configs[win]);
 602                 if (ret)
 603                         return ret;
 604         }
 605
 606         exynos_plane = &ctx->planes[ctx->first_win];
 607         out_type = (ctx->out_type & IFTYPE_HDMI) ? EXYNOS_DISPLAY_TYPE_HDMI
 608                                                   : EXYNOS_DISPLAY_TYPE_LCD;
 609         ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
 610                         out_type, &decon_crtc_ops, ctx);
 611         if (IS_ERR(ctx->crtc))
 612                 return PTR_ERR(ctx->crtc);
 613
 614         decon_clear_channels(ctx->crtc);
 615
 616         return drm_iommu_attach_device(drm_dev, dev);
 617 }
 618
 619 static void decon_unbind(struct device *dev, struct device *master, void *data)
 620 {
 621         struct decon_context *ctx = dev_get_drvdata(dev);
 622
 623         decon_disable(ctx->crtc);
 624
 625         /* detach this sub driver from iommu mapping if supported. */
 626         drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
 627 }
 628
 629 static const struct component_ops decon_component_ops = {
 630         .bind   = decon_bind,
 631         .unbind = decon_unbind,
 632 };
 633
 634 static void decon_handle_vblank(struct decon_context *ctx)
 635 {
 636         u32 frm;
 637
 638         spin_lock(&ctx->vblank_lock);
 639
 640         frm = decon_get_frame_count(ctx, true);
 641
 642         if (frm != ctx->frame_id) {
 643                 /* handle only if incremented, take care of wrap-around */
 644                 if ((s32)(frm - ctx->frame_id) > 0)
 645                         drm_crtc_handle_vblank(&ctx->crtc->base);
 646                 ctx->frame_id = frm;
 647         }
 648
 649         spin_unlock(&ctx->vblank_lock);
 650 }
 651
 652 static irqreturn_t decon_irq_handler(int irq, void *dev_id)
 653 {
 654         struct decon_context *ctx = dev_id;
 655         u32 val;
 656
 657         if (!test_bit(BIT_CLKS_ENABLED, &ctx->flags))
 658                 goto out;
 659
 660         val = readl(ctx->addr + DECON_VIDINTCON1);
 661         val &= VIDINTCON1_INTFRMDONEPEND | VIDINTCON1_INTFRMPEND;
 662
 663         if (val) {
 664                 writel(val, ctx->addr + DECON_VIDINTCON1);
 665                 if (ctx->out_type & IFTYPE_HDMI) {
 666                         val = readl(ctx->addr + DECON_VIDOUTCON0);
 667                         val &= VIDOUT_INTERLACE_EN_F | VIDOUT_INTERLACE_FIELD_F;
 668                         if (val ==
 669                             (VIDOUT_INTERLACE_EN_F | VIDOUT_INTERLACE_FIELD_F))
 670                                 return IRQ_HANDLED;
 671                 }
 672                 decon_handle_vblank(ctx);
 673         }
 674
 675 out:
 676         return IRQ_HANDLED;
 677 }
 678
 679 #ifdef CONFIG_PM
 680 static int exynos5433_decon_suspend(struct device *dev)
 681 {
 682         struct decon_context *ctx = dev_get_drvdata(dev);
 683         int i = ARRAY_SIZE(decon_clks_name);
 684
 685         while (--i >= 0)
 686                 clk_disable_unprepare(ctx->clks[i]);
 687
 688         return 0;
 689 }
 690
 691 static int exynos5433_decon_resume(struct device *dev)
 692 {
 693         struct decon_context *ctx = dev_get_drvdata(dev);
 694         int i, ret;
 695
 696         for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
 697                 ret = clk_prepare_enable(ctx->clks[i]);
 698                 if (ret < 0)
 699                         goto err;
 700         }
 701
 702         return 0;
 703
 704 err:
 705         while (--i >= 0)
 706                 clk_disable_unprepare(ctx->clks[i]);
 707
 708         return ret;
 709 }
 710 #endif
 711
 712 static const struct dev_pm_ops exynos5433_decon_pm_ops = {
 713         SET_RUNTIME_PM_OPS(exynos5433_decon_suspend, exynos5433_decon_resume,
 714                            NULL)
 715 };
 716
 717 static const struct of_device_id exynos5433_decon_driver_dt_match[] = {
 718         {
 719                 .compatible = "samsung,exynos5433-decon",
 720                 .data = (void *)I80_HW_TRG
 721         },
 722         {
 723                 .compatible = "samsung,exynos5433-decon-tv",
 724                 .data = (void *)(I80_HW_TRG | IFTYPE_HDMI)
 725         },
 726         {},
 727 };
 728 MODULE_DEVICE_TABLE(of, exynos5433_decon_driver_dt_match);
 729
 730 static int exynos5433_decon_probe(struct platform_device *pdev)
 731 {
 732         struct device *dev = &pdev->dev;
 733         struct decon_context *ctx;
 734         struct resource *res;
 735         int ret;
 736         int i;
 737
 738         ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
 739         if (!ctx)
 740                 return -ENOMEM;
 741
 742         __set_bit(BIT_SUSPENDED, &ctx->flags);
 743         ctx->dev = dev;
 744         ctx->out_type = (unsigned long)of_device_get_match_data(dev);
 745         spin_lock_init(&ctx->vblank_lock);
 746
 747         if (ctx->out_type & IFTYPE_HDMI) {
 748                 ctx->first_win = 1;
 749         } else if (of_get_child_by_name(dev->of_node, "i80-if-timings")) {
 750                 ctx->out_type |= IFTYPE_I80;
 751         }
 752
 753         if (ctx->out_type & I80_HW_TRG) {
 754                 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
 755                                                         "samsung,disp-sysreg");
 756                 if (IS_ERR(ctx->sysreg)) {
 757                         dev_err(dev, "failed to get system register\n");
 758                         return PTR_ERR(ctx->sysreg);
 759                 }
 760         }
 761
 762         for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
 763                 struct clk *clk;
 764
 765                 clk = devm_clk_get(ctx->dev, decon_clks_name[i]);
 766                 if (IS_ERR(clk))
 767                         return PTR_ERR(clk);
 768
 769                 ctx->clks[i] = clk;
 770         }
 771
 772         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 773         if (!res) {
 774                 dev_err(dev, "cannot find IO resource\n");
 775                 return -ENXIO;
 776         }
 777
 778         ctx->addr = devm_ioremap_resource(dev, res);
 779         if (IS_ERR(ctx->addr)) {
 780                 dev_err(dev, "ioremap failed\n");
 781                 return PTR_ERR(ctx->addr);
 782         }
 783
 784         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
 785                         (ctx->out_type & IFTYPE_I80) ? "lcd_sys" : "vsync");
 786         if (!res) {
 787                 dev_err(dev, "cannot find IRQ resource\n");
 788                 return -ENXIO;
 789         }
 790
 791         ret = devm_request_irq(dev, res->start, decon_irq_handler, 0,
 792                                "drm_decon", ctx);
 793         if (ret < 0) {
 794                 dev_err(dev, "lcd_sys irq request failed\n");
 795                 return ret;
 796         }
 797
 798         platform_set_drvdata(pdev, ctx);
 799
 800         pm_runtime_enable(dev);
 801
 802         ret = component_add(dev, &decon_component_ops);
 803         if (ret)
 804                 goto err_disable_pm_runtime;
 805
 806         return 0;
 807
 808 err_disable_pm_runtime:
 809         pm_runtime_disable(dev);
 810
 811         return ret;
 812 }
 813
 814 static int exynos5433_decon_remove(struct platform_device *pdev)
 815 {
 816         pm_runtime_disable(&pdev->dev);
 817
 818         component_del(&pdev->dev, &decon_component_ops);
 819
 820         return 0;
 821 }
 822
 823 struct platform_driver exynos5433_decon_driver = {
 824         .probe          = exynos5433_decon_probe,
 825         .remove         = exynos5433_decon_remove,
 826         .driver         = {
 827                 .name   = "exynos5433-decon",
 828                 .pm     = &exynos5433_decon_pm_ops,
 829                 .of_match_table = exynos5433_decon_driver_dt_match,
 830         },
 831 };