drivers/gpu/drm/exynos/exynos5433_drm_decon.c

   1 /* drivers/gpu/drm/exynos5433_drm_decon.c
   2  *
   3  * Copyright (C) 2015 Samsung Electronics Co.Ltd
   4  * Authors:
   5  *      Joonyoung Shim <jy0922.shim@samsung.com>
   6  *      Hyungwon Hwang <human.hwang@samsung.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundationr
  11  */
  12
  13 #include <linux/platform_device.h>
  14 #include <linux/clk.h>
  15 #include <linux/component.h>
  16 #include <linux/mfd/syscon.h>
  17 #include <linux/of_device.h>
  18 #include <linux/of_gpio.h>
  19 #include <linux/pm_runtime.h>
  20 #include <linux/regmap.h>
  21
  22 #include <video/exynos5433_decon.h>
  23
  24 #include "exynos_drm_drv.h"
  25 #include "exynos_drm_crtc.h"
  26 #include "exynos_drm_fb.h"
  27 #include "exynos_drm_plane.h"
  28 #include "exynos_drm_iommu.h"
  29
  30 #define DSD_CFG_MUX 0x1004
  31 #define DSD_CFG_MUX_TE_UNMASK_GLOBAL BIT(13)
  32
  33 #define WINDOWS_NR      3
  34 #define MIN_FB_WIDTH_FOR_16WORD_BURST   128
  35
  36 #define IFTYPE_I80      (1 << 0)
  37 #define I80_HW_TRG      (1 << 1)
  38 #define IFTYPE_HDMI     (1 << 2)
  39
  40 static const char * const decon_clks_name[] = {
  41         "pclk",
  42         "aclk_decon",
  43         "aclk_smmu_decon0x",
  44         "aclk_xiu_decon0x",
  45         "pclk_smmu_decon0x",
  46         "sclk_decon_vclk",
  47         "sclk_decon_eclk",
  48 };
  49
  50 enum decon_flag_bits {
  51         BIT_CLKS_ENABLED,
  52         BIT_WIN_UPDATED,
  53         BIT_SUSPENDED
  54 };
  55
  56 struct decon_context {
  57         struct device                   *dev;
  58         struct drm_device               *drm_dev;
  59         struct exynos_drm_crtc          *crtc;
  60         struct exynos_drm_plane         planes[WINDOWS_NR];
  61         struct exynos_drm_plane_config  configs[WINDOWS_NR];
  62         void __iomem                    *addr;
  63         struct regmap                   *sysreg;
  64         struct clk                      *clks[ARRAY_SIZE(decon_clks_name)];
  65         unsigned int                    irq;
  66         unsigned int                    te_irq;
  67         unsigned long                   flags;
  68         unsigned long                   out_type;
  69         int                             first_win;
  70         spinlock_t                      vblank_lock;
  71         u32                             frame_id;
  72 };
  73
  74 static const uint32_t decon_formats[] = {
  75         DRM_FORMAT_XRGB1555,
  76         DRM_FORMAT_RGB565,
  77         DRM_FORMAT_XRGB8888,
  78         DRM_FORMAT_ARGB8888,
  79 };
  80
  81 static const enum drm_plane_type decon_win_types[WINDOWS_NR] = {
  82         DRM_PLANE_TYPE_PRIMARY,
  83         DRM_PLANE_TYPE_OVERLAY,
  84         DRM_PLANE_TYPE_CURSOR,
  85 };
  86
  87 static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask,
  88                                   u32 val)
  89 {
  90         val = (val & mask) | (readl(ctx->addr + reg) & ~mask);
  91         writel(val, ctx->addr + reg);
  92 }
  93
  94 static int decon_enable_vblank(struct exynos_drm_crtc *crtc)
  95 {
  96         struct decon_context *ctx = crtc->ctx;
  97         u32 val;
  98
  99         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 100                 return -EPERM;
 101
 102         val = VIDINTCON0_INTEN;
 103         if (ctx->out_type & IFTYPE_I80)
 104                 val |= VIDINTCON0_FRAMEDONE;
 105         else
 106                 val |= VIDINTCON0_INTFRMEN | VIDINTCON0_FRAMESEL_FP;
 107
 108         writel(val, ctx->addr + DECON_VIDINTCON0);
 109
 110         enable_irq(ctx->irq);
 111         if (!(ctx->out_type & I80_HW_TRG))
 112                 enable_irq(ctx->te_irq);
 113
 114         return 0;
 115 }
 116
 117 static void decon_disable_vblank(struct exynos_drm_crtc *crtc)
 118 {
 119         struct decon_context *ctx = crtc->ctx;
 120
 121         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 122                 return;
 123
 124         if (!(ctx->out_type & I80_HW_TRG))
 125                 disable_irq_nosync(ctx->te_irq);
 126         disable_irq_nosync(ctx->irq);
 127
 128         writel(0, ctx->addr + DECON_VIDINTCON0);
 129 }
 130
 131 /* return number of starts/ends of frame transmissions since reset */
 132 static u32 decon_get_frame_count(struct decon_context *ctx, bool end)
 133 {
 134         u32 frm, pfrm, status, cnt = 2;
 135
 136         /* To get consistent result repeat read until frame id is stable.
 137          * Usually the loop will be executed once, in rare cases when the loop
 138          * is executed at frame change time 2nd pass will be needed.
 139          */
 140         frm = readl(ctx->addr + DECON_CRFMID);
 141         do {
 142                 status = readl(ctx->addr + DECON_VIDCON1);
 143                 pfrm = frm;
 144                 frm = readl(ctx->addr + DECON_CRFMID);
 145         } while (frm != pfrm && --cnt);
 146
 147         /* CRFMID is incremented on BPORCH in case of I80 and on VSYNC in case
 148          * of RGB, it should be taken into account.
 149          */
 150         if (!frm)
 151                 return 0;
 152
 153         switch (status & (VIDCON1_VSTATUS_MASK | VIDCON1_I80_ACTIVE)) {
 154         case VIDCON1_VSTATUS_VS:
 155                 if (!(ctx->out_type & IFTYPE_I80))
 156                         --frm;
 157                 break;
 158         case VIDCON1_VSTATUS_BP:
 159                 --frm;
 160                 break;
 161         case VIDCON1_I80_ACTIVE:
 162         case VIDCON1_VSTATUS_AC:
 163                 if (end)
 164                         --frm;
 165                 break;
 166         default:
 167                 break;
 168         }
 169
 170         return frm;
 171 }
 172
 173 static u32 decon_get_vblank_counter(struct exynos_drm_crtc *crtc)
 174 {
 175         struct decon_context *ctx = crtc->ctx;
 176
 177         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 178                 return 0;
 179
 180         return decon_get_frame_count(ctx, false);
 181 }
 182
 183 static void decon_setup_trigger(struct decon_context *ctx)
 184 {
 185         if (!(ctx->out_type & (IFTYPE_I80 | I80_HW_TRG)))
 186                 return;
 187
 188         if (!(ctx->out_type & I80_HW_TRG)) {
 189                 writel(TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F |
 190                        TRIGCON_TE_AUTO_MASK | TRIGCON_SWTRIGEN,
 191                        ctx->addr + DECON_TRIGCON);
 192                 return;
 193         }
 194
 195         writel(TRIGCON_TRIGEN_PER_F | TRIGCON_TRIGEN_F | TRIGCON_HWTRIGMASK
 196                | TRIGCON_HWTRIGEN, ctx->addr + DECON_TRIGCON);
 197
 198         if (regmap_update_bits(ctx->sysreg, DSD_CFG_MUX,
 199                                DSD_CFG_MUX_TE_UNMASK_GLOBAL, ~0))
 200                 DRM_ERROR("Cannot update sysreg.\n");
 201 }
 202
 203 static void decon_commit(struct exynos_drm_crtc *crtc)
 204 {
 205         struct decon_context *ctx = crtc->ctx;
 206         struct drm_display_mode *m = &crtc->base.mode;
 207         bool interlaced = false;
 208         u32 val;
 209
 210         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 211                 return;
 212
 213         if (ctx->out_type & IFTYPE_HDMI) {
 214                 m->crtc_hsync_start = m->crtc_hdisplay + 10;
 215                 m->crtc_hsync_end = m->crtc_htotal - 92;
 216                 m->crtc_vsync_start = m->crtc_vdisplay + 1;
 217                 m->crtc_vsync_end = m->crtc_vsync_start + 1;
 218                 if (m->flags & DRM_MODE_FLAG_INTERLACE)
 219                         interlaced = true;
 220         }
 221
 222         decon_setup_trigger(ctx);
 223
 224         /* lcd on and use command if */
 225         val = VIDOUT_LCD_ON;
 226         if (interlaced)
 227                 val |= VIDOUT_INTERLACE_EN_F;
 228         if (ctx->out_type & IFTYPE_I80) {
 229                 val |= VIDOUT_COMMAND_IF;
 230         } else {
 231                 val |= VIDOUT_RGB_IF;
 232         }
 233
 234         writel(val, ctx->addr + DECON_VIDOUTCON0);
 235
 236         if (interlaced)
 237                 val = VIDTCON2_LINEVAL(m->vdisplay / 2 - 1) |
 238                         VIDTCON2_HOZVAL(m->hdisplay - 1);
 239         else
 240                 val = VIDTCON2_LINEVAL(m->vdisplay - 1) |
 241                         VIDTCON2_HOZVAL(m->hdisplay - 1);
 242         writel(val, ctx->addr + DECON_VIDTCON2);
 243
 244         if (!(ctx->out_type & IFTYPE_I80)) {
 245                 int vbp = m->crtc_vtotal - m->crtc_vsync_end;
 246                 int vfp = m->crtc_vsync_start - m->crtc_vdisplay;
 247
 248                 if (interlaced)
 249                         vbp = vbp / 2 - 1;
 250                 val = VIDTCON00_VBPD_F(vbp - 1) | VIDTCON00_VFPD_F(vfp - 1);
 251                 writel(val, ctx->addr + DECON_VIDTCON00);
 252
 253                 val = VIDTCON01_VSPW_F(
 254                                 m->crtc_vsync_end - m->crtc_vsync_start - 1);
 255                 writel(val, ctx->addr + DECON_VIDTCON01);
 256
 257                 val = VIDTCON10_HBPD_F(
 258                                 m->crtc_htotal - m->crtc_hsync_end - 1) |
 259                         VIDTCON10_HFPD_F(
 260                                 m->crtc_hsync_start - m->crtc_hdisplay - 1);
 261                 writel(val, ctx->addr + DECON_VIDTCON10);
 262
 263                 val = VIDTCON11_HSPW_F(
 264                                 m->crtc_hsync_end - m->crtc_hsync_start - 1);
 265                 writel(val, ctx->addr + DECON_VIDTCON11);
 266         }
 267
 268         /* enable output and display signal */
 269         decon_set_bits(ctx, DECON_VIDCON0, VIDCON0_ENVID | VIDCON0_ENVID_F, ~0);
 270
 271         decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
 272 }
 273
 274 static void decon_win_set_pixfmt(struct decon_context *ctx, unsigned int win,
 275                                  struct drm_framebuffer *fb)
 276 {
 277         unsigned long val;
 278
 279         val = readl(ctx->addr + DECON_WINCONx(win));
 280         val &= ~WINCONx_BPPMODE_MASK;
 281
 282         switch (fb->format->format) {
 283         case DRM_FORMAT_XRGB1555:
 284                 val |= WINCONx_BPPMODE_16BPP_I1555;
 285                 val |= WINCONx_HAWSWP_F;
 286                 val |= WINCONx_BURSTLEN_16WORD;
 287                 break;
 288         case DRM_FORMAT_RGB565:
 289                 val |= WINCONx_BPPMODE_16BPP_565;
 290                 val |= WINCONx_HAWSWP_F;
 291                 val |= WINCONx_BURSTLEN_16WORD;
 292                 break;
 293         case DRM_FORMAT_XRGB8888:
 294                 val |= WINCONx_BPPMODE_24BPP_888;
 295                 val |= WINCONx_WSWP_F;
 296                 val |= WINCONx_BURSTLEN_16WORD;
 297                 break;
 298         case DRM_FORMAT_ARGB8888:
 299                 val |= WINCONx_BPPMODE_32BPP_A8888;
 300                 val |= WINCONx_WSWP_F | WINCONx_BLD_PIX_F | WINCONx_ALPHA_SEL_F;
 301                 val |= WINCONx_BURSTLEN_16WORD;
 302                 break;
 303         default:
 304                 DRM_ERROR("Proper pixel format is not set\n");
 305                 return;
 306         }
 307
 308         DRM_DEBUG_KMS("bpp = %u\n", fb->format->cpp[0] * 8);
 309
 310         /*
 311          * In case of exynos, setting dma-burst to 16Word causes permanent
 312          * tearing for very small buffers, e.g. cursor buffer. Burst Mode
 313          * switching which is based on plane size is not recommended as
 314          * plane size varies a lot towards the end of the screen and rapid
 315          * movement causes unstable DMA which results into iommu crash/tear.
 316          */
 317
 318         if (fb->width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
 319                 val &= ~WINCONx_BURSTLEN_MASK;
 320                 val |= WINCONx_BURSTLEN_8WORD;
 321         }
 322
 323         writel(val, ctx->addr + DECON_WINCONx(win));
 324 }
 325
 326 static void decon_shadow_protect(struct decon_context *ctx, bool protect)
 327 {
 328         decon_set_bits(ctx, DECON_SHADOWCON, SHADOWCON_PROTECT_MASK,
 329                        protect ? ~0 : 0);
 330 }
 331
 332 static void decon_atomic_begin(struct exynos_drm_crtc *crtc)
 333 {
 334         struct decon_context *ctx = crtc->ctx;
 335
 336         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 337                 return;
 338
 339         decon_shadow_protect(ctx, true);
 340 }
 341
 342 #define BIT_VAL(x, e, s) (((x) & ((1 << ((e) - (s) + 1)) - 1)) << (s))
 343 #define COORDINATE_X(x) BIT_VAL((x), 23, 12)
 344 #define COORDINATE_Y(x) BIT_VAL((x), 11, 0)
 345
 346 static void decon_update_plane(struct exynos_drm_crtc *crtc,
 347                                struct exynos_drm_plane *plane)
 348 {
 349         struct exynos_drm_plane_state *state =
 350                                 to_exynos_plane_state(plane->base.state);
 351         struct decon_context *ctx = crtc->ctx;
 352         struct drm_framebuffer *fb = state->base.fb;
 353         unsigned int win = plane->index;
 354         unsigned int bpp = fb->format->cpp[0];
 355         unsigned int pitch = fb->pitches[0];
 356         dma_addr_t dma_addr = exynos_drm_fb_dma_addr(fb, 0);
 357         u32 val;
 358
 359         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 360                 return;
 361
 362         if (crtc->base.mode.flags & DRM_MODE_FLAG_INTERLACE) {
 363                 val = COORDINATE_X(state->crtc.x) |
 364                         COORDINATE_Y(state->crtc.y / 2);
 365                 writel(val, ctx->addr + DECON_VIDOSDxA(win));
 366
 367                 val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) |
 368                         COORDINATE_Y((state->crtc.y + state->crtc.h) / 2 - 1);
 369                 writel(val, ctx->addr + DECON_VIDOSDxB(win));
 370         } else {
 371                 val = COORDINATE_X(state->crtc.x) | COORDINATE_Y(state->crtc.y);
 372                 writel(val, ctx->addr + DECON_VIDOSDxA(win));
 373
 374                 val = COORDINATE_X(state->crtc.x + state->crtc.w - 1) |
 375                                 COORDINATE_Y(state->crtc.y + state->crtc.h - 1);
 376                 writel(val, ctx->addr + DECON_VIDOSDxB(win));
 377         }
 378
 379         val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) |
 380                 VIDOSD_Wx_ALPHA_B_F(0x0);
 381         writel(val, ctx->addr + DECON_VIDOSDxC(win));
 382
 383         val = VIDOSD_Wx_ALPHA_R_F(0x0) | VIDOSD_Wx_ALPHA_G_F(0x0) |
 384                 VIDOSD_Wx_ALPHA_B_F(0x0);
 385         writel(val, ctx->addr + DECON_VIDOSDxD(win));
 386
 387         writel(dma_addr, ctx->addr + DECON_VIDW0xADD0B0(win));
 388
 389         val = dma_addr + pitch * state->src.h;
 390         writel(val, ctx->addr + DECON_VIDW0xADD1B0(win));
 391
 392         if (!(ctx->out_type & IFTYPE_HDMI))
 393                 val = BIT_VAL(pitch - state->crtc.w * bpp, 27, 14)
 394                         | BIT_VAL(state->crtc.w * bpp, 13, 0);
 395         else
 396                 val = BIT_VAL(pitch - state->crtc.w * bpp, 29, 15)
 397                         | BIT_VAL(state->crtc.w * bpp, 14, 0);
 398         writel(val, ctx->addr + DECON_VIDW0xADD2(win));
 399
 400         decon_win_set_pixfmt(ctx, win, fb);
 401
 402         /* window enable */
 403         decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, ~0);
 404 }
 405
 406 static void decon_disable_plane(struct exynos_drm_crtc *crtc,
 407                                 struct exynos_drm_plane *plane)
 408 {
 409         struct decon_context *ctx = crtc->ctx;
 410         unsigned int win = plane->index;
 411
 412         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 413                 return;
 414
 415         decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
 416 }
 417
 418 static void decon_atomic_flush(struct exynos_drm_crtc *crtc)
 419 {
 420         struct decon_context *ctx = crtc->ctx;
 421         unsigned long flags;
 422
 423         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 424                 return;
 425
 426         spin_lock_irqsave(&ctx->vblank_lock, flags);
 427
 428         decon_shadow_protect(ctx, false);
 429
 430         decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
 431
 432         if (ctx->out_type & IFTYPE_I80)
 433                 set_bit(BIT_WIN_UPDATED, &ctx->flags);
 434
 435         ctx->frame_id = decon_get_frame_count(ctx, true);
 436
 437         exynos_crtc_handle_event(crtc);
 438
 439         spin_unlock_irqrestore(&ctx->vblank_lock, flags);
 440 }
 441
 442 static void decon_swreset(struct decon_context *ctx)
 443 {
 444         unsigned int tries;
 445         unsigned long flags;
 446
 447         writel(0, ctx->addr + DECON_VIDCON0);
 448         for (tries = 2000; tries; --tries) {
 449                 if (~readl(ctx->addr + DECON_VIDCON0) & VIDCON0_STOP_STATUS)
 450                         break;
 451                 udelay(10);
 452         }
 453
 454         writel(VIDCON0_SWRESET, ctx->addr + DECON_VIDCON0);
 455         for (tries = 2000; tries; --tries) {
 456                 if (~readl(ctx->addr + DECON_VIDCON0) & VIDCON0_SWRESET)
 457                         break;
 458                 udelay(10);
 459         }
 460
 461         WARN(tries == 0, "failed to software reset DECON\n");
 462
 463         spin_lock_irqsave(&ctx->vblank_lock, flags);
 464         ctx->frame_id = 0;
 465         spin_unlock_irqrestore(&ctx->vblank_lock, flags);
 466
 467         if (!(ctx->out_type & IFTYPE_HDMI))
 468                 return;
 469
 470         writel(VIDCON0_CLKVALUP | VIDCON0_VLCKFREE, ctx->addr + DECON_VIDCON0);
 471         decon_set_bits(ctx, DECON_CMU,
 472                        CMU_CLKGAGE_MODE_SFR_F | CMU_CLKGAGE_MODE_MEM_F, ~0);
 473         writel(VIDCON1_VCLK_RUN_VDEN_DISABLE, ctx->addr + DECON_VIDCON1);
 474         writel(CRCCTRL_CRCEN | CRCCTRL_CRCSTART_F | CRCCTRL_CRCCLKEN,
 475                ctx->addr + DECON_CRCCTRL);
 476 }
 477
 478 static void decon_enable(struct exynos_drm_crtc *crtc)
 479 {
 480         struct decon_context *ctx = crtc->ctx;
 481
 482         if (!test_and_clear_bit(BIT_SUSPENDED, &ctx->flags))
 483                 return;
 484
 485         pm_runtime_get_sync(ctx->dev);
 486
 487         exynos_drm_pipe_clk_enable(crtc, true);
 488
 489         set_bit(BIT_CLKS_ENABLED, &ctx->flags);
 490
 491         decon_swreset(ctx);
 492
 493         decon_commit(ctx->crtc);
 494 }
 495
 496 static void decon_disable(struct exynos_drm_crtc *crtc)
 497 {
 498         struct decon_context *ctx = crtc->ctx;
 499         int i;
 500
 501         if (!(ctx->out_type & I80_HW_TRG))
 502                 synchronize_irq(ctx->te_irq);
 503         synchronize_irq(ctx->irq);
 504
 505         if (test_bit(BIT_SUSPENDED, &ctx->flags))
 506                 return;
 507
 508         /*
 509          * We need to make sure that all windows are disabled before we
 510          * suspend that connector. Otherwise we might try to scan from
 511          * a destroyed buffer later.
 512          */
 513         for (i = ctx->first_win; i < WINDOWS_NR; i++)
 514                 decon_disable_plane(crtc, &ctx->planes[i]);
 515
 516         decon_swreset(ctx);
 517
 518         clear_bit(BIT_CLKS_ENABLED, &ctx->flags);
 519
 520         exynos_drm_pipe_clk_enable(crtc, false);
 521
 522         pm_runtime_put_sync(ctx->dev);
 523
 524         set_bit(BIT_SUSPENDED, &ctx->flags);
 525 }
 526
 527 static irqreturn_t decon_te_irq_handler(int irq, void *dev_id)
 528 {
 529         struct decon_context *ctx = dev_id;
 530
 531         if (!test_bit(BIT_CLKS_ENABLED, &ctx->flags) ||
 532             (ctx->out_type & I80_HW_TRG))
 533                 return IRQ_HANDLED;
 534
 535         decon_set_bits(ctx, DECON_TRIGCON, TRIGCON_SWTRIGCMD, ~0);
 536
 537         return IRQ_HANDLED;
 538 }
 539
 540 static void decon_clear_channels(struct exynos_drm_crtc *crtc)
 541 {
 542         struct decon_context *ctx = crtc->ctx;
 543         int win, i, ret;
 544
 545         DRM_DEBUG_KMS("%s\n", __FILE__);
 546
 547         for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
 548                 ret = clk_prepare_enable(ctx->clks[i]);
 549                 if (ret < 0)
 550                         goto err;
 551         }
 552
 553         decon_shadow_protect(ctx, true);
 554         for (win = 0; win < WINDOWS_NR; win++)
 555                 decon_set_bits(ctx, DECON_WINCONx(win), WINCONx_ENWIN_F, 0);
 556         decon_shadow_protect(ctx, false);
 557
 558         decon_set_bits(ctx, DECON_UPDATE, STANDALONE_UPDATE_F, ~0);
 559
 560         /* TODO: wait for possible vsync */
 561         msleep(50);
 562
 563 err:
 564         while (--i >= 0)
 565                 clk_disable_unprepare(ctx->clks[i]);
 566 }
 567
 568 static const struct exynos_drm_crtc_ops decon_crtc_ops = {
 569         .enable                 = decon_enable,
 570         .disable                = decon_disable,
 571         .enable_vblank          = decon_enable_vblank,
 572         .disable_vblank         = decon_disable_vblank,
 573         .get_vblank_counter     = decon_get_vblank_counter,
 574         .atomic_begin           = decon_atomic_begin,
 575         .update_plane           = decon_update_plane,
 576         .disable_plane          = decon_disable_plane,
 577         .atomic_flush           = decon_atomic_flush,
 578 };
 579
 580 static int decon_bind(struct device *dev, struct device *master, void *data)
 581 {
 582         struct decon_context *ctx = dev_get_drvdata(dev);
 583         struct drm_device *drm_dev = data;
 584         struct exynos_drm_plane *exynos_plane;
 585         enum exynos_drm_output_type out_type;
 586         unsigned int win;
 587         int ret;
 588
 589         ctx->drm_dev = drm_dev;
 590         drm_dev->max_vblank_count = 0xffffffff;
 591
 592         for (win = ctx->first_win; win < WINDOWS_NR; win++) {
 593                 int tmp = (win == ctx->first_win) ? 0 : win;
 594
 595                 ctx->configs[win].pixel_formats = decon_formats;
 596                 ctx->configs[win].num_pixel_formats = ARRAY_SIZE(decon_formats);
 597                 ctx->configs[win].zpos = win;
 598                 ctx->configs[win].type = decon_win_types[tmp];
 599
 600                 ret = exynos_plane_init(drm_dev, &ctx->planes[win], win,
 601                                         &ctx->configs[win]);
 602                 if (ret)
 603                         return ret;
 604         }
 605
 606         exynos_plane = &ctx->planes[ctx->first_win];
 607         out_type = (ctx->out_type & IFTYPE_HDMI) ? EXYNOS_DISPLAY_TYPE_HDMI
 608                                                   : EXYNOS_DISPLAY_TYPE_LCD;
 609         ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
 610                         out_type, &decon_crtc_ops, ctx);
 611         if (IS_ERR(ctx->crtc))
 612                 return PTR_ERR(ctx->crtc);
 613
 614         decon_clear_channels(ctx->crtc);
 615
 616         return drm_iommu_attach_device(drm_dev, dev);
 617 }
 618
 619 static void decon_unbind(struct device *dev, struct device *master, void *data)
 620 {
 621         struct decon_context *ctx = dev_get_drvdata(dev);
 622
 623         decon_disable(ctx->crtc);
 624
 625         /* detach this sub driver from iommu mapping if supported. */
 626         drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
 627 }
 628
 629 static const struct component_ops decon_component_ops = {
 630         .bind   = decon_bind,
 631         .unbind = decon_unbind,
 632 };
 633
 634 static void decon_handle_vblank(struct decon_context *ctx)
 635 {
 636         u32 frm;
 637
 638         spin_lock(&ctx->vblank_lock);
 639
 640         frm = decon_get_frame_count(ctx, true);
 641
 642         if (frm != ctx->frame_id) {
 643                 /* handle only if incremented, take care of wrap-around */
 644                 if ((s32)(frm - ctx->frame_id) > 0)
 645                         drm_crtc_handle_vblank(&ctx->crtc->base);
 646                 ctx->frame_id = frm;
 647         }
 648
 649         spin_unlock(&ctx->vblank_lock);
 650 }
 651
 652 static irqreturn_t decon_irq_handler(int irq, void *dev_id)
 653 {
 654         struct decon_context *ctx = dev_id;
 655         u32 val;
 656
 657         if (!test_bit(BIT_CLKS_ENABLED, &ctx->flags))
 658                 goto out;
 659
 660         val = readl(ctx->addr + DECON_VIDINTCON1);
 661         val &= VIDINTCON1_INTFRMDONEPEND | VIDINTCON1_INTFRMPEND;
 662
 663         if (val) {
 664                 writel(val, ctx->addr + DECON_VIDINTCON1);
 665                 if (ctx->out_type & IFTYPE_HDMI) {
 666                         val = readl(ctx->addr + DECON_VIDOUTCON0);
 667                         val &= VIDOUT_INTERLACE_EN_F | VIDOUT_INTERLACE_FIELD_F;
 668                         if (val ==
 669                             (VIDOUT_INTERLACE_EN_F | VIDOUT_INTERLACE_FIELD_F))
 670                                 return IRQ_HANDLED;
 671                 }
 672                 decon_handle_vblank(ctx);
 673         }
 674
 675 out:
 676         return IRQ_HANDLED;
 677 }
 678
 679 #ifdef CONFIG_PM
 680 static int exynos5433_decon_suspend(struct device *dev)
 681 {
 682         struct decon_context *ctx = dev_get_drvdata(dev);
 683         int i = ARRAY_SIZE(decon_clks_name);
 684
 685         while (--i >= 0)
 686                 clk_disable_unprepare(ctx->clks[i]);
 687
 688         return 0;
 689 }
 690
 691 static int exynos5433_decon_resume(struct device *dev)
 692 {
 693         struct decon_context *ctx = dev_get_drvdata(dev);
 694         int i, ret;
 695
 696         for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
 697                 ret = clk_prepare_enable(ctx->clks[i]);
 698                 if (ret < 0)
 699                         goto err;
 700         }
 701
 702         return 0;
 703
 704 err:
 705         while (--i >= 0)
 706                 clk_disable_unprepare(ctx->clks[i]);
 707
 708         return ret;
 709 }
 710 #endif
 711
 712 static const struct dev_pm_ops exynos5433_decon_pm_ops = {
 713         SET_RUNTIME_PM_OPS(exynos5433_decon_suspend, exynos5433_decon_resume,
 714                            NULL)
 715 };
 716
 717 static const struct of_device_id exynos5433_decon_driver_dt_match[] = {
 718         {
 719                 .compatible = "samsung,exynos5433-decon",
 720                 .data = (void *)I80_HW_TRG
 721         },
 722         {
 723                 .compatible = "samsung,exynos5433-decon-tv",
 724                 .data = (void *)(I80_HW_TRG | IFTYPE_HDMI)
 725         },
 726         {},
 727 };
 728 MODULE_DEVICE_TABLE(of, exynos5433_decon_driver_dt_match);
 729
 730 static int decon_conf_irq(struct decon_context *ctx, const char *name,
 731                 irq_handler_t handler, unsigned long int flags, bool required)
 732 {
 733         struct platform_device *pdev = to_platform_device(ctx->dev);
 734         int ret, irq = platform_get_irq_byname(pdev, name);
 735
 736         if (irq < 0) {
 737                 if (irq == -EPROBE_DEFER)
 738                         return irq;
 739                 if (required)
 740                         dev_err(ctx->dev, "cannot get %s IRQ\n", name);
 741                 else
 742                         irq = 0;
 743                 return irq;
 744         }
 745         irq_set_status_flags(irq, IRQ_NOAUTOEN);
 746         ret = devm_request_irq(ctx->dev, irq, handler, flags, "drm_decon", ctx);
 747         if (ret < 0) {
 748                 dev_err(ctx->dev, "IRQ %s request failed\n", name);
 749                 return ret;
 750         }
 751
 752         return irq;
 753 }
 754
 755 static int exynos5433_decon_probe(struct platform_device *pdev)
 756 {
 757         struct device *dev = &pdev->dev;
 758         struct decon_context *ctx;
 759         struct resource *res;
 760         int ret;
 761         int i;
 762
 763         ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
 764         if (!ctx)
 765                 return -ENOMEM;
 766
 767         __set_bit(BIT_SUSPENDED, &ctx->flags);
 768         ctx->dev = dev;
 769         ctx->out_type = (unsigned long)of_device_get_match_data(dev);
 770         spin_lock_init(&ctx->vblank_lock);
 771
 772         if (ctx->out_type & IFTYPE_HDMI) {
 773                 ctx->first_win = 1;
 774         } else if (of_get_child_by_name(dev->of_node, "i80-if-timings")) {
 775                 ctx->out_type |= IFTYPE_I80;
 776         }
 777
 778         for (i = 0; i < ARRAY_SIZE(decon_clks_name); i++) {
 779                 struct clk *clk;
 780
 781                 clk = devm_clk_get(ctx->dev, decon_clks_name[i]);
 782                 if (IS_ERR(clk))
 783                         return PTR_ERR(clk);
 784
 785                 ctx->clks[i] = clk;
 786         }
 787
 788         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 789         if (!res) {
 790                 dev_err(dev, "cannot find IO resource\n");
 791                 return -ENXIO;
 792         }
 793
 794         ctx->addr = devm_ioremap_resource(dev, res);
 795         if (IS_ERR(ctx->addr)) {
 796                 dev_err(dev, "ioremap failed\n");
 797                 return PTR_ERR(ctx->addr);
 798         }
 799
 800         if (ctx->out_type & IFTYPE_I80) {
 801                 ret = decon_conf_irq(ctx, "lcd_sys", decon_irq_handler, 0, true);
 802                 if (ret < 0)
 803                         return ret;
 804                 ctx->irq = ret;
 805
 806                 ret = decon_conf_irq(ctx, "te", decon_te_irq_handler,
 807                                      IRQF_TRIGGER_RISING, false);
 808                 if (ret < 0)
 809                         return ret;
 810                 if (ret) {
 811                         ctx->te_irq = ret;
 812                         ctx->out_type &= ~I80_HW_TRG;
 813                 }
 814         } else {
 815                 ret = decon_conf_irq(ctx, "vsync", decon_irq_handler, 0, true);
 816                 if (ret < 0)
 817                         return ret;
 818                 ctx->irq = ret;
 819         }
 820
 821         if (ctx->out_type & I80_HW_TRG) {
 822                 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
 823                                                         "samsung,disp-sysreg");
 824                 if (IS_ERR(ctx->sysreg)) {
 825                         dev_err(dev, "failed to get system register\n");
 826                         return PTR_ERR(ctx->sysreg);
 827                 }
 828         }
 829
 830         platform_set_drvdata(pdev, ctx);
 831
 832         pm_runtime_enable(dev);
 833
 834         ret = component_add(dev, &decon_component_ops);
 835         if (ret)
 836                 goto err_disable_pm_runtime;
 837
 838         return 0;
 839
 840 err_disable_pm_runtime:
 841         pm_runtime_disable(dev);
 842
 843         return ret;
 844 }
 845
 846 static int exynos5433_decon_remove(struct platform_device *pdev)
 847 {
 848         pm_runtime_disable(&pdev->dev);
 849
 850         component_del(&pdev->dev, &decon_component_ops);
 851
 852         return 0;
 853 }
 854
 855 struct platform_driver exynos5433_decon_driver = {
 856         .probe          = exynos5433_decon_probe,
 857         .remove         = exynos5433_decon_remove,
 858         .driver         = {
 859                 .name   = "exynos5433-decon",
 860                 .pm     = &exynos5433_decon_pm_ops,
 861                 .of_match_table = exynos5433_decon_driver_dt_match,
 862         },
 863 };