2 * Header file for Samsung DP (Display Port) interface driver.
4 * Copyright (C) 2012 Samsung Electronics Co., Ltd.
5 * Author: Jingoo Han <jg1.han@samsung.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
13 #ifndef _EXYNOS_DP_CORE_H
14 #define _EXYNOS_DP_CORE_H
16 #include <drm/drm_crtc.h>
17 #include <drm/exynos_drm.h>
19 #define DP_TIMEOUT_LOOP_COUNT 100
24 LINK_RATE_1_62GBPS = 0x06,
25 LINK_RATE_2_70GBPS = 0x0a
28 enum link_lane_count_type {
34 enum link_training_state {
42 enum voltage_swing_level {
49 enum pre_emphasis_level {
77 enum color_coefficient {
92 enum clock_recovery_m_value_type {
97 enum video_timing_recognition_type {
98 VIDEO_TIMING_FROM_CAPTURE,
99 VIDEO_TIMING_FROM_REGISTER
102 enum analog_power_block {
113 DP_IRQ_TYPE_HP_CABLE_IN,
114 DP_IRQ_TYPE_HP_CABLE_OUT,
115 DP_IRQ_TYPE_HP_CHANGE,
122 bool h_sync_polarity;
123 bool v_sync_polarity;
126 enum color_space color_space;
127 enum dynamic_range dynamic_range;
128 enum color_coefficient ycbcr_coeff;
129 enum color_depth color_depth;
131 enum link_rate_type link_rate;
132 enum link_lane_count_type lane_count;
143 enum link_training_state lt_state;
146 struct exynos_dp_device {
148 struct drm_device *drm_dev;
149 struct drm_connector connector;
150 struct drm_encoder *encoder;
153 void __iomem *reg_base;
154 void __iomem *phy_addr;
155 unsigned int enable_mask;
157 struct video_info *video_info;
158 struct link_train link_train;
159 struct work_struct hotplug_work;
163 struct exynos_drm_panel_info panel;
166 /* exynos_dp_reg.c */
167 void exynos_dp_enable_video_mute(struct exynos_dp_device *dp, bool enable);
168 void exynos_dp_stop_video(struct exynos_dp_device *dp);
169 void exynos_dp_lane_swap(struct exynos_dp_device *dp, bool enable);
170 void exynos_dp_init_analog_param(struct exynos_dp_device *dp);
171 void exynos_dp_init_interrupt(struct exynos_dp_device *dp);
172 void exynos_dp_reset(struct exynos_dp_device *dp);
173 void exynos_dp_swreset(struct exynos_dp_device *dp);
174 void exynos_dp_config_interrupt(struct exynos_dp_device *dp);
175 enum pll_status exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp);
176 void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable);
177 void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
178 enum analog_power_block block,
180 void exynos_dp_init_analog_func(struct exynos_dp_device *dp);
181 void exynos_dp_init_hpd(struct exynos_dp_device *dp);
182 enum dp_irq_type exynos_dp_get_irq_type(struct exynos_dp_device *dp);
183 void exynos_dp_clear_hotplug_interrupts(struct exynos_dp_device *dp);
184 void exynos_dp_reset_aux(struct exynos_dp_device *dp);
185 void exynos_dp_init_aux(struct exynos_dp_device *dp);
186 int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp);
187 void exynos_dp_enable_sw_function(struct exynos_dp_device *dp);
188 int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp);
189 int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
190 unsigned int reg_addr,
192 int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
193 unsigned int reg_addr,
194 unsigned char *data);
195 int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
196 unsigned int reg_addr,
198 unsigned char data[]);
199 int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
200 unsigned int reg_addr,
202 unsigned char data[]);
203 int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
204 unsigned int device_addr,
205 unsigned int reg_addr);
206 int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
207 unsigned int device_addr,
208 unsigned int reg_addr,
210 int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
211 unsigned int device_addr,
212 unsigned int reg_addr,
214 unsigned char edid[]);
215 void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype);
216 void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype);
217 void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count);
218 void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count);
219 void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable);
220 void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
221 enum pattern_set pattern);
222 void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level);
223 void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level);
224 void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level);
225 void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level);
226 void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
228 void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
230 void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
232 void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
234 u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp);
235 u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp);
236 u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp);
237 u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp);
238 void exynos_dp_reset_macro(struct exynos_dp_device *dp);
239 void exynos_dp_init_video(struct exynos_dp_device *dp);
241 void exynos_dp_set_video_color_format(struct exynos_dp_device *dp);
242 int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp);
243 void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
244 enum clock_recovery_m_value_type type,
247 void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type);
248 void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable);
249 void exynos_dp_start_video(struct exynos_dp_device *dp);
250 int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp);
251 void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp);
252 void exynos_dp_enable_scrambling(struct exynos_dp_device *dp);
253 void exynos_dp_disable_scrambling(struct exynos_dp_device *dp);
255 /* I2C EDID Chip ID, Slave Address */
256 #define I2C_EDID_DEVICE_ADDR 0x50
257 #define I2C_E_EDID_DEVICE_ADDR 0x30
259 #define EDID_BLOCK_LENGTH 0x80
260 #define EDID_HEADER_PATTERN 0x00
261 #define EDID_EXTENSION_FLAG 0x7e
262 #define EDID_CHECKSUM 0x7f
264 /* Definition for DPCD Register */
265 #define DPCD_ADDR_DPCD_REV 0x0000
266 #define DPCD_ADDR_MAX_LINK_RATE 0x0001
267 #define DPCD_ADDR_MAX_LANE_COUNT 0x0002
268 #define DPCD_ADDR_LINK_BW_SET 0x0100
269 #define DPCD_ADDR_LANE_COUNT_SET 0x0101
270 #define DPCD_ADDR_TRAINING_PATTERN_SET 0x0102
271 #define DPCD_ADDR_TRAINING_LANE0_SET 0x0103
272 #define DPCD_ADDR_LANE0_1_STATUS 0x0202
273 #define DPCD_ADDR_LANE_ALIGN_STATUS_UPDATED 0x0204
274 #define DPCD_ADDR_ADJUST_REQUEST_LANE0_1 0x0206
275 #define DPCD_ADDR_ADJUST_REQUEST_LANE2_3 0x0207
276 #define DPCD_ADDR_TEST_REQUEST 0x0218
277 #define DPCD_ADDR_TEST_RESPONSE 0x0260
278 #define DPCD_ADDR_TEST_EDID_CHECKSUM 0x0261
279 #define DPCD_ADDR_SINK_POWER_STATE 0x0600
281 /* DPCD_ADDR_MAX_LANE_COUNT */
282 #define DPCD_ENHANCED_FRAME_CAP(x) (((x) >> 7) & 0x1)
283 #define DPCD_MAX_LANE_COUNT(x) ((x) & 0x1f)
285 /* DPCD_ADDR_LANE_COUNT_SET */
286 #define DPCD_ENHANCED_FRAME_EN (0x1 << 7)
287 #define DPCD_LANE_COUNT_SET(x) ((x) & 0x1f)
289 /* DPCD_ADDR_TRAINING_PATTERN_SET */
290 #define DPCD_SCRAMBLING_DISABLED (0x1 << 5)
291 #define DPCD_SCRAMBLING_ENABLED (0x0 << 5)
292 #define DPCD_TRAINING_PATTERN_2 (0x2 << 0)
293 #define DPCD_TRAINING_PATTERN_1 (0x1 << 0)
294 #define DPCD_TRAINING_PATTERN_DISABLED (0x0 << 0)
296 /* DPCD_ADDR_TRAINING_LANE0_SET */
297 #define DPCD_MAX_PRE_EMPHASIS_REACHED (0x1 << 5)
298 #define DPCD_PRE_EMPHASIS_SET(x) (((x) & 0x3) << 3)
299 #define DPCD_PRE_EMPHASIS_GET(x) (((x) >> 3) & 0x3)
300 #define DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 (0x0 << 3)
301 #define DPCD_MAX_SWING_REACHED (0x1 << 2)
302 #define DPCD_VOLTAGE_SWING_SET(x) (((x) & 0x3) << 0)
303 #define DPCD_VOLTAGE_SWING_GET(x) (((x) >> 0) & 0x3)
304 #define DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0 (0x0 << 0)
306 /* DPCD_ADDR_LANE0_1_STATUS */
307 #define DPCD_LANE_SYMBOL_LOCKED (0x1 << 2)
308 #define DPCD_LANE_CHANNEL_EQ_DONE (0x1 << 1)
309 #define DPCD_LANE_CR_DONE (0x1 << 0)
310 #define DPCD_CHANNEL_EQ_BITS (DPCD_LANE_CR_DONE| \
311 DPCD_LANE_CHANNEL_EQ_DONE|\
312 DPCD_LANE_SYMBOL_LOCKED)
314 /* DPCD_ADDR_LANE_ALIGN__STATUS_UPDATED */
315 #define DPCD_LINK_STATUS_UPDATED (0x1 << 7)
316 #define DPCD_DOWNSTREAM_PORT_STATUS_CHANGED (0x1 << 6)
317 #define DPCD_INTERLANE_ALIGN_DONE (0x1 << 0)
319 /* DPCD_ADDR_TEST_REQUEST */
320 #define DPCD_TEST_EDID_READ (0x1 << 2)
322 /* DPCD_ADDR_TEST_RESPONSE */
323 #define DPCD_TEST_EDID_CHECKSUM_WRITE (0x1 << 2)
325 /* DPCD_ADDR_SINK_POWER_STATE */
326 #define DPCD_SET_POWER_STATE_D0 (0x1 << 0)
327 #define DPCD_SET_POWER_STATE_D4 (0x2 << 0)
329 #endif /* _EXYNOS_DP_CORE_H */