2 * Samsung SoC MIPI DSI Master driver.
4 * Copyright (c) 2014 Samsung Electronics Co., Ltd
6 * Contacts: Tomasz Figa <t.figa@samsung.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
14 #include <drm/drm_crtc_helper.h>
15 #include <drm/drm_mipi_dsi.h>
16 #include <drm/drm_panel.h>
18 #include <linux/clk.h>
19 #include <linux/irq.h>
20 #include <linux/phy/phy.h>
21 #include <linux/regulator/consumer.h>
23 #include <video/mipi_display.h>
24 #include <video/videomode.h>
26 #include "exynos_drm_drv.h"
28 /* returns true iff both arguments logically differs */
29 #define NEQV(a, b) (!(a) ^ !(b))
31 #define DSIM_STATUS_REG 0x0 /* Status register */
32 #define DSIM_SWRST_REG 0x4 /* Software reset register */
33 #define DSIM_CLKCTRL_REG 0x8 /* Clock control register */
34 #define DSIM_TIMEOUT_REG 0xc /* Time out register */
35 #define DSIM_CONFIG_REG 0x10 /* Configuration register */
36 #define DSIM_ESCMODE_REG 0x14 /* Escape mode register */
38 /* Main display image resolution register */
39 #define DSIM_MDRESOL_REG 0x18
40 #define DSIM_MVPORCH_REG 0x1c /* Main display Vporch register */
41 #define DSIM_MHPORCH_REG 0x20 /* Main display Hporch register */
42 #define DSIM_MSYNC_REG 0x24 /* Main display sync area register */
44 /* Sub display image resolution register */
45 #define DSIM_SDRESOL_REG 0x28
46 #define DSIM_INTSRC_REG 0x2c /* Interrupt source register */
47 #define DSIM_INTMSK_REG 0x30 /* Interrupt mask register */
48 #define DSIM_PKTHDR_REG 0x34 /* Packet Header FIFO register */
49 #define DSIM_PAYLOAD_REG 0x38 /* Payload FIFO register */
50 #define DSIM_RXFIFO_REG 0x3c /* Read FIFO register */
51 #define DSIM_FIFOTHLD_REG 0x40 /* FIFO threshold level register */
52 #define DSIM_FIFOCTRL_REG 0x44 /* FIFO status and control register */
54 /* FIFO memory AC characteristic register */
55 #define DSIM_PLLCTRL_REG 0x4c /* PLL control register */
56 #define DSIM_PLLTMR_REG 0x50 /* PLL timer register */
57 #define DSIM_PHYACCHR_REG 0x54 /* D-PHY AC characteristic register */
58 #define DSIM_PHYACCHR1_REG 0x58 /* D-PHY AC characteristic register1 */
61 #define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0)
62 #define DSIM_STOP_STATE_CLK (1 << 8)
63 #define DSIM_TX_READY_HS_CLK (1 << 10)
64 #define DSIM_PLL_STABLE (1 << 31)
67 #define DSIM_FUNCRST (1 << 16)
68 #define DSIM_SWRST (1 << 0)
71 #define DSIM_LPDR_TIMEOUT(x) ((x) << 0)
72 #define DSIM_BTA_TIMEOUT(x) ((x) << 16)
75 #define DSIM_ESC_PRESCALER(x) (((x) & 0xffff) << 0)
76 #define DSIM_ESC_PRESCALER_MASK (0xffff << 0)
77 #define DSIM_LANE_ESC_CLK_EN_CLK (1 << 19)
78 #define DSIM_LANE_ESC_CLK_EN_DATA(x) (((x) & 0xf) << 20)
79 #define DSIM_LANE_ESC_CLK_EN_DATA_MASK (0xf << 20)
80 #define DSIM_BYTE_CLKEN (1 << 24)
81 #define DSIM_BYTE_CLK_SRC(x) (((x) & 0x3) << 25)
82 #define DSIM_BYTE_CLK_SRC_MASK (0x3 << 25)
83 #define DSIM_PLL_BYPASS (1 << 27)
84 #define DSIM_ESC_CLKEN (1 << 28)
85 #define DSIM_TX_REQUEST_HSCLK (1 << 31)
88 #define DSIM_LANE_EN_CLK (1 << 0)
89 #define DSIM_LANE_EN(x) (((x) & 0xf) << 1)
90 #define DSIM_NUM_OF_DATA_LANE(x) (((x) & 0x3) << 5)
91 #define DSIM_SUB_PIX_FORMAT(x) (((x) & 0x7) << 8)
92 #define DSIM_MAIN_PIX_FORMAT_MASK (0x7 << 12)
93 #define DSIM_MAIN_PIX_FORMAT_RGB888 (0x7 << 12)
94 #define DSIM_MAIN_PIX_FORMAT_RGB666 (0x6 << 12)
95 #define DSIM_MAIN_PIX_FORMAT_RGB666_P (0x5 << 12)
96 #define DSIM_MAIN_PIX_FORMAT_RGB565 (0x4 << 12)
97 #define DSIM_SUB_VC (((x) & 0x3) << 16)
98 #define DSIM_MAIN_VC (((x) & 0x3) << 18)
99 #define DSIM_HSA_MODE (1 << 20)
100 #define DSIM_HBP_MODE (1 << 21)
101 #define DSIM_HFP_MODE (1 << 22)
102 #define DSIM_HSE_MODE (1 << 23)
103 #define DSIM_AUTO_MODE (1 << 24)
104 #define DSIM_VIDEO_MODE (1 << 25)
105 #define DSIM_BURST_MODE (1 << 26)
106 #define DSIM_SYNC_INFORM (1 << 27)
107 #define DSIM_EOT_DISABLE (1 << 28)
108 #define DSIM_MFLUSH_VS (1 << 29)
111 #define DSIM_TX_TRIGGER_RST (1 << 4)
112 #define DSIM_TX_LPDT_LP (1 << 6)
113 #define DSIM_CMD_LPDT_LP (1 << 7)
114 #define DSIM_FORCE_BTA (1 << 16)
115 #define DSIM_FORCE_STOP_STATE (1 << 20)
116 #define DSIM_STOP_STATE_CNT(x) (((x) & 0x7ff) << 21)
117 #define DSIM_STOP_STATE_CNT_MASK (0x7ff << 21)
120 #define DSIM_MAIN_STAND_BY (1 << 31)
121 #define DSIM_MAIN_VRESOL(x) (((x) & 0x7ff) << 16)
122 #define DSIM_MAIN_HRESOL(x) (((x) & 0X7ff) << 0)
125 #define DSIM_CMD_ALLOW(x) ((x) << 28)
126 #define DSIM_STABLE_VFP(x) ((x) << 16)
127 #define DSIM_MAIN_VBP(x) ((x) << 0)
128 #define DSIM_CMD_ALLOW_MASK (0xf << 28)
129 #define DSIM_STABLE_VFP_MASK (0x7ff << 16)
130 #define DSIM_MAIN_VBP_MASK (0x7ff << 0)
133 #define DSIM_MAIN_HFP(x) ((x) << 16)
134 #define DSIM_MAIN_HBP(x) ((x) << 0)
135 #define DSIM_MAIN_HFP_MASK ((0xffff) << 16)
136 #define DSIM_MAIN_HBP_MASK ((0xffff) << 0)
139 #define DSIM_MAIN_VSA(x) ((x) << 22)
140 #define DSIM_MAIN_HSA(x) ((x) << 0)
141 #define DSIM_MAIN_VSA_MASK ((0x3ff) << 22)
142 #define DSIM_MAIN_HSA_MASK ((0xffff) << 0)
145 #define DSIM_SUB_STANDY(x) ((x) << 31)
146 #define DSIM_SUB_VRESOL(x) ((x) << 16)
147 #define DSIM_SUB_HRESOL(x) ((x) << 0)
148 #define DSIM_SUB_STANDY_MASK ((0x1) << 31)
149 #define DSIM_SUB_VRESOL_MASK ((0x7ff) << 16)
150 #define DSIM_SUB_HRESOL_MASK ((0x7ff) << 0)
153 #define DSIM_INT_PLL_STABLE (1 << 31)
154 #define DSIM_INT_SW_RST_RELEASE (1 << 30)
155 #define DSIM_INT_SFR_FIFO_EMPTY (1 << 29)
156 #define DSIM_INT_BTA (1 << 25)
157 #define DSIM_INT_FRAME_DONE (1 << 24)
158 #define DSIM_INT_RX_TIMEOUT (1 << 21)
159 #define DSIM_INT_BTA_TIMEOUT (1 << 20)
160 #define DSIM_INT_RX_DONE (1 << 18)
161 #define DSIM_INT_RX_TE (1 << 17)
162 #define DSIM_INT_RX_ACK (1 << 16)
163 #define DSIM_INT_RX_ECC_ERR (1 << 15)
164 #define DSIM_INT_RX_CRC_ERR (1 << 14)
167 #define DSIM_RX_DATA_FULL (1 << 25)
168 #define DSIM_RX_DATA_EMPTY (1 << 24)
169 #define DSIM_SFR_HEADER_FULL (1 << 23)
170 #define DSIM_SFR_HEADER_EMPTY (1 << 22)
171 #define DSIM_SFR_PAYLOAD_FULL (1 << 21)
172 #define DSIM_SFR_PAYLOAD_EMPTY (1 << 20)
173 #define DSIM_I80_HEADER_FULL (1 << 19)
174 #define DSIM_I80_HEADER_EMPTY (1 << 18)
175 #define DSIM_I80_PAYLOAD_FULL (1 << 17)
176 #define DSIM_I80_PAYLOAD_EMPTY (1 << 16)
177 #define DSIM_SD_HEADER_FULL (1 << 15)
178 #define DSIM_SD_HEADER_EMPTY (1 << 14)
179 #define DSIM_SD_PAYLOAD_FULL (1 << 13)
180 #define DSIM_SD_PAYLOAD_EMPTY (1 << 12)
181 #define DSIM_MD_HEADER_FULL (1 << 11)
182 #define DSIM_MD_HEADER_EMPTY (1 << 10)
183 #define DSIM_MD_PAYLOAD_FULL (1 << 9)
184 #define DSIM_MD_PAYLOAD_EMPTY (1 << 8)
185 #define DSIM_RX_FIFO (1 << 4)
186 #define DSIM_SFR_FIFO (1 << 3)
187 #define DSIM_I80_FIFO (1 << 2)
188 #define DSIM_SD_FIFO (1 << 1)
189 #define DSIM_MD_FIFO (1 << 0)
192 #define DSIM_AFC_EN (1 << 14)
193 #define DSIM_AFC_CTL(x) (((x) & 0x7) << 5)
196 #define DSIM_FREQ_BAND(x) ((x) << 24)
197 #define DSIM_PLL_EN (1 << 23)
198 #define DSIM_PLL_P(x) ((x) << 13)
199 #define DSIM_PLL_M(x) ((x) << 4)
200 #define DSIM_PLL_S(x) ((x) << 1)
202 #define DSI_MAX_BUS_WIDTH 4
203 #define DSI_NUM_VIRTUAL_CHANNELS 4
204 #define DSI_TX_FIFO_SIZE 2048
205 #define DSI_RX_FIFO_SIZE 256
206 #define DSI_XFER_TIMEOUT_MS 100
207 #define DSI_RX_FIFO_EMPTY 0x30800002
209 enum exynos_dsi_transfer_type {
214 struct exynos_dsi_transfer {
215 struct list_head list;
216 struct completion completed;
222 const u8 *tx_payload;
231 #define DSIM_STATE_ENABLED BIT(0)
232 #define DSIM_STATE_INITIALIZED BIT(1)
233 #define DSIM_STATE_CMD_LPM BIT(2)
236 struct mipi_dsi_host dsi_host;
237 struct drm_connector connector;
238 struct drm_encoder *encoder;
239 struct device_node *panel_node;
240 struct drm_panel *panel;
243 void __iomem *reg_base;
247 struct regulator_bulk_data supplies[2];
259 struct drm_property *brightness;
260 struct completion completed;
262 spinlock_t transfer_lock; /* protects transfer_list */
263 struct list_head transfer_list;
266 #define host_to_dsi(host) container_of(host, struct exynos_dsi, dsi_host)
267 #define connector_to_dsi(c) container_of(c, struct exynos_dsi, connector)
269 static void exynos_dsi_wait_for_reset(struct exynos_dsi *dsi)
271 if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300)))
274 dev_err(dsi->dev, "timeout waiting for reset\n");
277 static void exynos_dsi_reset(struct exynos_dsi *dsi)
279 reinit_completion(&dsi->completed);
280 writel(DSIM_SWRST, dsi->reg_base + DSIM_SWRST_REG);
284 #define MHZ (1000*1000)
287 static unsigned long exynos_dsi_pll_find_pms(struct exynos_dsi *dsi,
288 unsigned long fin, unsigned long fout, u8 *p, u16 *m, u8 *s)
290 unsigned long best_freq = 0;
291 u32 min_delta = 0xffffffff;
293 u8 _p, uninitialized_var(best_p);
294 u16 _m, uninitialized_var(best_m);
295 u8 _s, uninitialized_var(best_s);
297 p_min = DIV_ROUND_UP(fin, (12 * MHZ));
298 p_max = fin / (6 * MHZ);
300 for (_p = p_min; _p <= p_max; ++_p) {
301 for (_s = 0; _s <= 5; ++_s) {
305 tmp = (u64)fout * (_p << _s);
308 if (_m < 41 || _m > 125)
313 if (tmp < 500 * MHZ || tmp > 1000 * MHZ)
317 do_div(tmp, _p << _s);
319 delta = abs(fout - tmp);
320 if (delta < min_delta) {
339 static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi,
342 static const unsigned long freq_bands[] = {
343 100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ,
344 270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ,
345 510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ,
346 770 * MHZ, 870 * MHZ, 950 * MHZ,
348 unsigned long fin, fout;
354 clk_set_rate(dsi->pll_clk, dsi->pll_clk_rate);
356 fin = clk_get_rate(dsi->pll_clk);
358 dev_err(dsi->dev, "failed to get PLL clock frequency\n");
362 dev_dbg(dsi->dev, "PLL input frequency: %lu\n", fin);
364 fout = exynos_dsi_pll_find_pms(dsi, fin, freq, &p, &m, &s);
367 "failed to find PLL PMS for requested frequency\n");
371 for (band = 0; band < ARRAY_SIZE(freq_bands); ++band)
372 if (fout < freq_bands[band])
375 dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d), band %d\n", fout,
378 writel(500, dsi->reg_base + DSIM_PLLTMR_REG);
380 reg = DSIM_FREQ_BAND(band) | DSIM_PLL_EN
381 | DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s);
382 writel(reg, dsi->reg_base + DSIM_PLLCTRL_REG);
386 if (timeout-- == 0) {
387 dev_err(dsi->dev, "PLL failed to stabilize\n");
390 reg = readl(dsi->reg_base + DSIM_STATUS_REG);
391 } while ((reg & DSIM_PLL_STABLE) == 0);
396 static int exynos_dsi_enable_clock(struct exynos_dsi *dsi)
398 unsigned long hs_clk, byte_clk, esc_clk;
399 unsigned long esc_div;
402 hs_clk = exynos_dsi_set_pll(dsi, dsi->burst_clk_rate);
404 dev_err(dsi->dev, "failed to configure DSI PLL\n");
408 byte_clk = hs_clk / 8;
409 esc_div = DIV_ROUND_UP(byte_clk, dsi->esc_clk_rate);
410 esc_clk = byte_clk / esc_div;
412 if (esc_clk > 20 * MHZ) {
414 esc_clk = byte_clk / esc_div;
417 dev_dbg(dsi->dev, "hs_clk = %lu, byte_clk = %lu, esc_clk = %lu\n",
418 hs_clk, byte_clk, esc_clk);
420 reg = readl(dsi->reg_base + DSIM_CLKCTRL_REG);
421 reg &= ~(DSIM_ESC_PRESCALER_MASK | DSIM_LANE_ESC_CLK_EN_CLK
422 | DSIM_LANE_ESC_CLK_EN_DATA_MASK | DSIM_PLL_BYPASS
423 | DSIM_BYTE_CLK_SRC_MASK);
424 reg |= DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN
425 | DSIM_ESC_PRESCALER(esc_div)
426 | DSIM_LANE_ESC_CLK_EN_CLK
427 | DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1)
428 | DSIM_BYTE_CLK_SRC(0)
429 | DSIM_TX_REQUEST_HSCLK;
430 writel(reg, dsi->reg_base + DSIM_CLKCTRL_REG);
435 static void exynos_dsi_disable_clock(struct exynos_dsi *dsi)
439 reg = readl(dsi->reg_base + DSIM_CLKCTRL_REG);
440 reg &= ~(DSIM_LANE_ESC_CLK_EN_CLK | DSIM_LANE_ESC_CLK_EN_DATA_MASK
441 | DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN);
442 writel(reg, dsi->reg_base + DSIM_CLKCTRL_REG);
444 reg = readl(dsi->reg_base + DSIM_PLLCTRL_REG);
446 writel(reg, dsi->reg_base + DSIM_PLLCTRL_REG);
449 static int exynos_dsi_init_link(struct exynos_dsi *dsi)
455 /* Initialize FIFO pointers */
456 reg = readl(dsi->reg_base + DSIM_FIFOCTRL_REG);
458 writel(reg, dsi->reg_base + DSIM_FIFOCTRL_REG);
460 usleep_range(9000, 11000);
463 writel(reg, dsi->reg_base + DSIM_FIFOCTRL_REG);
465 usleep_range(9000, 11000);
467 /* DSI configuration */
470 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
471 reg |= DSIM_VIDEO_MODE;
473 if (!(dsi->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH))
474 reg |= DSIM_MFLUSH_VS;
475 if (!(dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET))
476 reg |= DSIM_EOT_DISABLE;
477 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
478 reg |= DSIM_SYNC_INFORM;
479 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
480 reg |= DSIM_BURST_MODE;
481 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT)
482 reg |= DSIM_AUTO_MODE;
483 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE)
484 reg |= DSIM_HSE_MODE;
485 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP))
486 reg |= DSIM_HFP_MODE;
487 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP))
488 reg |= DSIM_HBP_MODE;
489 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSA))
490 reg |= DSIM_HSA_MODE;
493 switch (dsi->format) {
494 case MIPI_DSI_FMT_RGB888:
495 reg |= DSIM_MAIN_PIX_FORMAT_RGB888;
497 case MIPI_DSI_FMT_RGB666:
498 reg |= DSIM_MAIN_PIX_FORMAT_RGB666;
500 case MIPI_DSI_FMT_RGB666_PACKED:
501 reg |= DSIM_MAIN_PIX_FORMAT_RGB666_P;
503 case MIPI_DSI_FMT_RGB565:
504 reg |= DSIM_MAIN_PIX_FORMAT_RGB565;
507 dev_err(dsi->dev, "invalid pixel format\n");
511 reg |= DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1);
513 writel(reg, dsi->reg_base + DSIM_CONFIG_REG);
515 reg |= DSIM_LANE_EN_CLK;
516 writel(reg, dsi->reg_base + DSIM_CONFIG_REG);
518 lanes_mask = BIT(dsi->lanes) - 1;
519 reg |= DSIM_LANE_EN(lanes_mask);
520 writel(reg, dsi->reg_base + DSIM_CONFIG_REG);
522 /* Check clock and data lane state are stop state */
525 if (timeout-- == 0) {
526 dev_err(dsi->dev, "waiting for bus lanes timed out\n");
530 reg = readl(dsi->reg_base + DSIM_STATUS_REG);
531 if ((reg & DSIM_STOP_STATE_DAT(lanes_mask))
532 != DSIM_STOP_STATE_DAT(lanes_mask))
534 } while (!(reg & (DSIM_STOP_STATE_CLK | DSIM_TX_READY_HS_CLK)));
536 reg = readl(dsi->reg_base + DSIM_ESCMODE_REG);
537 reg &= ~DSIM_STOP_STATE_CNT_MASK;
538 reg |= DSIM_STOP_STATE_CNT(0xf);
539 writel(reg, dsi->reg_base + DSIM_ESCMODE_REG);
541 reg = DSIM_BTA_TIMEOUT(0xff) | DSIM_LPDR_TIMEOUT(0xffff);
542 writel(reg, dsi->reg_base + DSIM_TIMEOUT_REG);
547 static void exynos_dsi_set_display_mode(struct exynos_dsi *dsi)
549 struct videomode *vm = &dsi->vm;
552 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
553 reg = DSIM_CMD_ALLOW(0xf)
554 | DSIM_STABLE_VFP(vm->vfront_porch)
555 | DSIM_MAIN_VBP(vm->vback_porch);
556 writel(reg, dsi->reg_base + DSIM_MVPORCH_REG);
558 reg = DSIM_MAIN_HFP(vm->hfront_porch)
559 | DSIM_MAIN_HBP(vm->hback_porch);
560 writel(reg, dsi->reg_base + DSIM_MHPORCH_REG);
562 reg = DSIM_MAIN_VSA(vm->vsync_len)
563 | DSIM_MAIN_HSA(vm->hsync_len);
564 writel(reg, dsi->reg_base + DSIM_MSYNC_REG);
567 reg = DSIM_MAIN_HRESOL(vm->hactive) | DSIM_MAIN_VRESOL(vm->vactive);
568 writel(reg, dsi->reg_base + DSIM_MDRESOL_REG);
570 dev_dbg(dsi->dev, "LCD size = %dx%d\n", vm->hactive, vm->vactive);
573 static void exynos_dsi_set_display_enable(struct exynos_dsi *dsi, bool enable)
577 reg = readl(dsi->reg_base + DSIM_MDRESOL_REG);
579 reg |= DSIM_MAIN_STAND_BY;
581 reg &= ~DSIM_MAIN_STAND_BY;
582 writel(reg, dsi->reg_base + DSIM_MDRESOL_REG);
585 static int exynos_dsi_wait_for_hdr_fifo(struct exynos_dsi *dsi)
590 u32 reg = readl(dsi->reg_base + DSIM_FIFOCTRL_REG);
592 if (!(reg & DSIM_SFR_HEADER_FULL))
596 usleep_range(950, 1050);
602 static void exynos_dsi_set_cmd_lpm(struct exynos_dsi *dsi, bool lpm)
604 u32 v = readl(dsi->reg_base + DSIM_ESCMODE_REG);
607 v |= DSIM_CMD_LPDT_LP;
609 v &= ~DSIM_CMD_LPDT_LP;
611 writel(v, dsi->reg_base + DSIM_ESCMODE_REG);
614 static void exynos_dsi_force_bta(struct exynos_dsi *dsi)
616 u32 v = readl(dsi->reg_base + DSIM_ESCMODE_REG);
619 writel(v, dsi->reg_base + DSIM_ESCMODE_REG);
622 static void exynos_dsi_send_to_fifo(struct exynos_dsi *dsi,
623 struct exynos_dsi_transfer *xfer)
625 struct device *dev = dsi->dev;
626 const u8 *payload = xfer->tx_payload + xfer->tx_done;
627 u16 length = xfer->tx_len - xfer->tx_done;
628 bool first = !xfer->tx_done;
631 dev_dbg(dev, "< xfer %p: tx len %u, done %u, rx len %u, done %u\n",
632 xfer, xfer->tx_len, xfer->tx_done, xfer->rx_len, xfer->rx_done);
634 if (length > DSI_TX_FIFO_SIZE)
635 length = DSI_TX_FIFO_SIZE;
637 xfer->tx_done += length;
640 while (length >= 4) {
641 reg = (payload[3] << 24) | (payload[2] << 16)
642 | (payload[1] << 8) | payload[0];
643 writel(reg, dsi->reg_base + DSIM_PAYLOAD_REG);
651 reg |= payload[2] << 16;
654 reg |= payload[1] << 8;
658 writel(reg, dsi->reg_base + DSIM_PAYLOAD_REG);
665 /* Send packet header */
669 reg = (xfer->data[1] << 16) | (xfer->data[0] << 8) | xfer->data_id;
670 if (exynos_dsi_wait_for_hdr_fifo(dsi)) {
671 dev_err(dev, "waiting for header FIFO timed out\n");
675 if (NEQV(xfer->flags & MIPI_DSI_MSG_USE_LPM,
676 dsi->state & DSIM_STATE_CMD_LPM)) {
677 exynos_dsi_set_cmd_lpm(dsi, xfer->flags & MIPI_DSI_MSG_USE_LPM);
678 dsi->state ^= DSIM_STATE_CMD_LPM;
681 writel(reg, dsi->reg_base + DSIM_PKTHDR_REG);
683 if (xfer->flags & MIPI_DSI_MSG_REQ_ACK)
684 exynos_dsi_force_bta(dsi);
687 static void exynos_dsi_read_from_fifo(struct exynos_dsi *dsi,
688 struct exynos_dsi_transfer *xfer)
690 u8 *payload = xfer->rx_payload + xfer->rx_done;
691 bool first = !xfer->rx_done;
692 struct device *dev = dsi->dev;
697 reg = readl(dsi->reg_base + DSIM_RXFIFO_REG);
699 switch (reg & 0x3f) {
700 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
701 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
702 if (xfer->rx_len >= 2) {
703 payload[1] = reg >> 16;
707 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
708 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
709 payload[0] = reg >> 8;
711 xfer->rx_len = xfer->rx_done;
714 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
715 dev_err(dev, "DSI Error Report: 0x%04x\n",
716 (reg >> 8) & 0xffff);
721 length = (reg >> 8) & 0xffff;
722 if (length > xfer->rx_len) {
724 "response too long (%u > %u bytes), stripping\n",
725 xfer->rx_len, length);
726 length = xfer->rx_len;
727 } else if (length < xfer->rx_len)
728 xfer->rx_len = length;
731 length = xfer->rx_len - xfer->rx_done;
732 xfer->rx_done += length;
734 /* Receive payload */
735 while (length >= 4) {
736 reg = readl(dsi->reg_base + DSIM_RXFIFO_REG);
737 payload[0] = (reg >> 0) & 0xff;
738 payload[1] = (reg >> 8) & 0xff;
739 payload[2] = (reg >> 16) & 0xff;
740 payload[3] = (reg >> 24) & 0xff;
746 reg = readl(dsi->reg_base + DSIM_RXFIFO_REG);
749 payload[2] = (reg >> 16) & 0xff;
752 payload[1] = (reg >> 8) & 0xff;
755 payload[0] = reg & 0xff;
759 if (xfer->rx_done == xfer->rx_len)
763 length = DSI_RX_FIFO_SIZE / 4;
765 reg = readl(dsi->reg_base + DSIM_RXFIFO_REG);
766 if (reg == DSI_RX_FIFO_EMPTY)
771 static void exynos_dsi_transfer_start(struct exynos_dsi *dsi)
774 struct exynos_dsi_transfer *xfer;
778 spin_lock_irqsave(&dsi->transfer_lock, flags);
780 if (list_empty(&dsi->transfer_list)) {
781 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
785 xfer = list_first_entry(&dsi->transfer_list,
786 struct exynos_dsi_transfer, list);
788 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
790 if (xfer->tx_len && xfer->tx_done == xfer->tx_len)
794 exynos_dsi_send_to_fifo(dsi, xfer);
796 if (xfer->tx_len || xfer->rx_len)
800 complete(&xfer->completed);
802 spin_lock_irqsave(&dsi->transfer_lock, flags);
804 list_del_init(&xfer->list);
805 start = !list_empty(&dsi->transfer_list);
807 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
813 static bool exynos_dsi_transfer_finish(struct exynos_dsi *dsi)
815 struct exynos_dsi_transfer *xfer;
819 spin_lock_irqsave(&dsi->transfer_lock, flags);
821 if (list_empty(&dsi->transfer_list)) {
822 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
826 xfer = list_first_entry(&dsi->transfer_list,
827 struct exynos_dsi_transfer, list);
829 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
832 "> xfer %p, tx_len %u, tx_done %u, rx_len %u, rx_done %u\n",
833 xfer, xfer->tx_len, xfer->tx_done, xfer->rx_len, xfer->rx_done);
835 if (xfer->tx_done != xfer->tx_len)
838 if (xfer->rx_done != xfer->rx_len)
839 exynos_dsi_read_from_fifo(dsi, xfer);
841 if (xfer->rx_done != xfer->rx_len)
844 spin_lock_irqsave(&dsi->transfer_lock, flags);
846 list_del_init(&xfer->list);
847 start = !list_empty(&dsi->transfer_list);
849 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
853 complete(&xfer->completed);
858 static void exynos_dsi_remove_transfer(struct exynos_dsi *dsi,
859 struct exynos_dsi_transfer *xfer)
864 spin_lock_irqsave(&dsi->transfer_lock, flags);
866 if (!list_empty(&dsi->transfer_list) &&
867 xfer == list_first_entry(&dsi->transfer_list,
868 struct exynos_dsi_transfer, list)) {
869 list_del_init(&xfer->list);
870 start = !list_empty(&dsi->transfer_list);
871 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
873 exynos_dsi_transfer_start(dsi);
877 list_del_init(&xfer->list);
879 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
882 static int exynos_dsi_transfer(struct exynos_dsi *dsi,
883 struct exynos_dsi_transfer *xfer)
890 xfer->result = -ETIMEDOUT;
891 init_completion(&xfer->completed);
893 spin_lock_irqsave(&dsi->transfer_lock, flags);
895 stopped = list_empty(&dsi->transfer_list);
896 list_add_tail(&xfer->list, &dsi->transfer_list);
898 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
901 exynos_dsi_transfer_start(dsi);
903 wait_for_completion_timeout(&xfer->completed,
904 msecs_to_jiffies(DSI_XFER_TIMEOUT_MS));
905 if (xfer->result == -ETIMEDOUT) {
906 exynos_dsi_remove_transfer(dsi, xfer);
907 dev_err(dsi->dev, "xfer timed out: %*ph %*ph\n", 2, xfer->data,
908 xfer->tx_len, xfer->tx_payload);
912 /* Also covers hardware timeout condition */
916 static irqreturn_t exynos_dsi_irq(int irq, void *dev_id)
918 struct exynos_dsi *dsi = dev_id;
921 status = readl(dsi->reg_base + DSIM_INTSRC_REG);
923 static unsigned long int j;
924 if (printk_timed_ratelimit(&j, 500))
925 dev_warn(dsi->dev, "spurious interrupt\n");
928 writel(status, dsi->reg_base + DSIM_INTSRC_REG);
930 if (status & DSIM_INT_SW_RST_RELEASE) {
931 u32 mask = ~(DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY);
932 writel(mask, dsi->reg_base + DSIM_INTMSK_REG);
933 complete(&dsi->completed);
937 if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY)))
940 if (exynos_dsi_transfer_finish(dsi))
941 exynos_dsi_transfer_start(dsi);
946 static int exynos_dsi_init(struct exynos_dsi *dsi)
948 exynos_dsi_enable_clock(dsi);
949 exynos_dsi_reset(dsi);
950 enable_irq(dsi->irq);
951 exynos_dsi_wait_for_reset(dsi);
952 exynos_dsi_init_link(dsi);
957 static int exynos_dsi_host_attach(struct mipi_dsi_host *host,
958 struct mipi_dsi_device *device)
960 struct exynos_dsi *dsi = host_to_dsi(host);
962 dsi->lanes = device->lanes;
963 dsi->format = device->format;
964 dsi->mode_flags = device->mode_flags;
965 dsi->panel_node = device->dev.of_node;
967 if (dsi->connector.dev)
968 drm_helper_hpd_irq_event(dsi->connector.dev);
973 static int exynos_dsi_host_detach(struct mipi_dsi_host *host,
974 struct mipi_dsi_device *device)
976 struct exynos_dsi *dsi = host_to_dsi(host);
978 dsi->panel_node = NULL;
980 if (dsi->connector.dev)
981 drm_helper_hpd_irq_event(dsi->connector.dev);
986 /* distinguish between short and long DSI packet types */
987 static bool exynos_dsi_is_short_dsi_type(u8 type)
989 return (type & 0x0f) <= 8;
992 static ssize_t exynos_dsi_host_transfer(struct mipi_dsi_host *host,
993 struct mipi_dsi_msg *msg)
995 struct exynos_dsi *dsi = host_to_dsi(host);
996 struct exynos_dsi_transfer xfer;
999 if (!(dsi->state & DSIM_STATE_INITIALIZED)) {
1000 ret = exynos_dsi_init(dsi);
1003 dsi->state |= DSIM_STATE_INITIALIZED;
1006 if (msg->tx_len == 0)
1009 xfer.data_id = msg->type | (msg->channel << 6);
1011 if (exynos_dsi_is_short_dsi_type(msg->type)) {
1012 const char *tx_buf = msg->tx_buf;
1014 if (msg->tx_len > 2)
1017 xfer.data[0] = tx_buf[0];
1018 xfer.data[1] = (msg->tx_len == 2) ? tx_buf[1] : 0;
1020 xfer.tx_len = msg->tx_len;
1021 xfer.data[0] = msg->tx_len & 0xff;
1022 xfer.data[1] = msg->tx_len >> 8;
1023 xfer.tx_payload = msg->tx_buf;
1026 xfer.rx_len = msg->rx_len;
1027 xfer.rx_payload = msg->rx_buf;
1028 xfer.flags = msg->flags;
1030 ret = exynos_dsi_transfer(dsi, &xfer);
1031 return (ret < 0) ? ret : xfer.rx_done;
1034 static const struct mipi_dsi_host_ops exynos_dsi_ops = {
1035 .attach = exynos_dsi_host_attach,
1036 .detach = exynos_dsi_host_detach,
1037 .transfer = exynos_dsi_host_transfer,
1040 static int exynos_dsi_poweron(struct exynos_dsi *dsi)
1044 ret = regulator_bulk_enable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
1046 dev_err(dsi->dev, "cannot enable regulators %d\n", ret);
1050 ret = clk_prepare_enable(dsi->bus_clk);
1052 dev_err(dsi->dev, "cannot enable bus clock %d\n", ret);
1056 ret = clk_prepare_enable(dsi->pll_clk);
1058 dev_err(dsi->dev, "cannot enable pll clock %d\n", ret);
1062 ret = phy_power_on(dsi->phy);
1064 dev_err(dsi->dev, "cannot enable phy %d\n", ret);
1071 clk_disable_unprepare(dsi->pll_clk);
1073 clk_disable_unprepare(dsi->bus_clk);
1075 regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
1080 static void exynos_dsi_poweroff(struct exynos_dsi *dsi)
1084 usleep_range(10000, 20000);
1086 if (dsi->state & DSIM_STATE_INITIALIZED) {
1087 dsi->state &= ~DSIM_STATE_INITIALIZED;
1089 exynos_dsi_disable_clock(dsi);
1091 disable_irq(dsi->irq);
1094 dsi->state &= ~DSIM_STATE_CMD_LPM;
1096 phy_power_off(dsi->phy);
1098 clk_disable_unprepare(dsi->pll_clk);
1099 clk_disable_unprepare(dsi->bus_clk);
1101 ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
1103 dev_err(dsi->dev, "cannot disable regulators %d\n", ret);
1106 static int exynos_dsi_enable(struct exynos_dsi *dsi)
1110 if (dsi->state & DSIM_STATE_ENABLED)
1113 ret = exynos_dsi_poweron(dsi);
1117 ret = drm_panel_enable(dsi->panel);
1119 exynos_dsi_poweroff(dsi);
1123 exynos_dsi_set_display_mode(dsi);
1124 exynos_dsi_set_display_enable(dsi, true);
1126 dsi->state |= DSIM_STATE_ENABLED;
1131 static void exynos_dsi_disable(struct exynos_dsi *dsi)
1133 if (!(dsi->state & DSIM_STATE_ENABLED))
1136 exynos_dsi_set_display_enable(dsi, false);
1137 drm_panel_disable(dsi->panel);
1138 exynos_dsi_poweroff(dsi);
1140 dsi->state &= ~DSIM_STATE_ENABLED;
1143 static void exynos_dsi_dpms(struct exynos_drm_display *display, int mode)
1145 struct exynos_dsi *dsi = display->ctx;
1149 case DRM_MODE_DPMS_ON:
1150 exynos_dsi_enable(dsi);
1152 case DRM_MODE_DPMS_STANDBY:
1153 case DRM_MODE_DPMS_SUSPEND:
1154 case DRM_MODE_DPMS_OFF:
1155 exynos_dsi_disable(dsi);
1163 static enum drm_connector_status
1164 exynos_dsi_detect(struct drm_connector *connector, bool force)
1166 struct exynos_dsi *dsi = connector_to_dsi(connector);
1169 dsi->panel = of_drm_find_panel(dsi->panel_node);
1171 drm_panel_attach(dsi->panel, &dsi->connector);
1172 } else if (!dsi->panel_node) {
1173 struct exynos_drm_display *display;
1175 display = platform_get_drvdata(to_platform_device(dsi->dev));
1176 exynos_dsi_dpms(display, DRM_MODE_DPMS_OFF);
1177 drm_panel_detach(dsi->panel);
1182 return connector_status_connected;
1184 return connector_status_disconnected;
1187 static void exynos_dsi_connector_destroy(struct drm_connector *connector)
1191 static struct drm_connector_funcs exynos_dsi_connector_funcs = {
1192 .dpms = drm_helper_connector_dpms,
1193 .detect = exynos_dsi_detect,
1194 .fill_modes = drm_helper_probe_single_connector_modes,
1195 .destroy = exynos_dsi_connector_destroy,
1198 static int exynos_dsi_get_modes(struct drm_connector *connector)
1200 struct exynos_dsi *dsi = connector_to_dsi(connector);
1203 return dsi->panel->funcs->get_modes(dsi->panel);
1208 static int exynos_dsi_mode_valid(struct drm_connector *connector,
1209 struct drm_display_mode *mode)
1214 static struct drm_encoder *
1215 exynos_dsi_best_encoder(struct drm_connector *connector)
1217 struct exynos_dsi *dsi = connector_to_dsi(connector);
1219 return dsi->encoder;
1222 static struct drm_connector_helper_funcs exynos_dsi_connector_helper_funcs = {
1223 .get_modes = exynos_dsi_get_modes,
1224 .mode_valid = exynos_dsi_mode_valid,
1225 .best_encoder = exynos_dsi_best_encoder,
1228 static int exynos_dsi_create_connector(struct exynos_drm_display *display,
1229 struct drm_encoder *encoder)
1231 struct exynos_dsi *dsi = display->ctx;
1232 struct drm_connector *connector = &dsi->connector;
1235 dsi->encoder = encoder;
1237 connector->polled = DRM_CONNECTOR_POLL_HPD;
1239 ret = drm_connector_init(encoder->dev, connector,
1240 &exynos_dsi_connector_funcs,
1241 DRM_MODE_CONNECTOR_DSI);
1243 DRM_ERROR("Failed to initialize connector with drm\n");
1247 drm_connector_helper_add(connector, &exynos_dsi_connector_helper_funcs);
1248 drm_sysfs_connector_add(connector);
1249 drm_mode_connector_attach_encoder(connector, encoder);
1254 static void exynos_dsi_mode_set(struct exynos_drm_display *display,
1255 struct drm_display_mode *mode)
1257 struct exynos_dsi *dsi = display->ctx;
1258 struct videomode *vm = &dsi->vm;
1260 vm->hactive = mode->hdisplay;
1261 vm->vactive = mode->vdisplay;
1262 vm->vfront_porch = mode->vsync_start - mode->vdisplay;
1263 vm->vback_porch = mode->vtotal - mode->vsync_end;
1264 vm->vsync_len = mode->vsync_end - mode->vsync_start;
1265 vm->hfront_porch = mode->hsync_start - mode->hdisplay;
1266 vm->hback_porch = mode->htotal - mode->hsync_end;
1267 vm->hsync_len = mode->hsync_end - mode->hsync_start;
1270 static struct exynos_drm_display_ops exynos_dsi_display_ops = {
1271 .create_connector = exynos_dsi_create_connector,
1272 .mode_set = exynos_dsi_mode_set,
1273 .dpms = exynos_dsi_dpms
1276 static struct exynos_drm_display exynos_dsi_display = {
1277 .type = EXYNOS_DISPLAY_TYPE_LCD,
1278 .ops = &exynos_dsi_display_ops,
1281 /* of_* functions will be removed after merge of of_graph patches */
1282 static struct device_node *
1283 of_get_child_by_name_reg(struct device_node *parent, const char *name, u32 reg)
1285 struct device_node *np;
1287 for_each_child_of_node(parent, np) {
1290 if (!np->name || of_node_cmp(np->name, name))
1293 if (of_property_read_u32(np, "reg", &r) < 0)
1303 static struct device_node *of_graph_get_port_by_reg(struct device_node *parent,
1306 struct device_node *ports, *port;
1308 ports = of_get_child_by_name(parent, "ports");
1312 port = of_get_child_by_name_reg(parent, "port", reg);
1319 static struct device_node *
1320 of_graph_get_endpoint_by_reg(struct device_node *port, u32 reg)
1322 return of_get_child_by_name_reg(port, "endpoint", reg);
1325 static int exynos_dsi_of_read_u32(const struct device_node *np,
1326 const char *propname, u32 *out_value)
1328 int ret = of_property_read_u32(np, propname, out_value);
1331 pr_err("%s: failed to get '%s' property\n", np->full_name,
1342 static int exynos_dsi_parse_dt(struct exynos_dsi *dsi)
1344 struct device *dev = dsi->dev;
1345 struct device_node *node = dev->of_node;
1346 struct device_node *port, *ep;
1349 ret = exynos_dsi_of_read_u32(node, "samsung,pll-clock-frequency",
1350 &dsi->pll_clk_rate);
1354 port = of_graph_get_port_by_reg(node, DSI_PORT_OUT);
1356 dev_err(dev, "no output port specified\n");
1360 ep = of_graph_get_endpoint_by_reg(port, 0);
1363 dev_err(dev, "no endpoint specified in output port\n");
1367 ret = exynos_dsi_of_read_u32(ep, "samsung,burst-clock-frequency",
1368 &dsi->burst_clk_rate);
1372 ret = exynos_dsi_of_read_u32(ep, "samsung,esc-clock-frequency",
1373 &dsi->esc_clk_rate);
1381 static int exynos_dsi_probe(struct platform_device *pdev)
1383 struct resource *res;
1384 struct exynos_dsi *dsi;
1387 dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
1389 dev_err(&pdev->dev, "failed to allocate dsi object.\n");
1393 init_completion(&dsi->completed);
1394 spin_lock_init(&dsi->transfer_lock);
1395 INIT_LIST_HEAD(&dsi->transfer_list);
1397 dsi->dsi_host.ops = &exynos_dsi_ops;
1398 dsi->dsi_host.dev = &pdev->dev;
1400 dsi->dev = &pdev->dev;
1402 ret = exynos_dsi_parse_dt(dsi);
1406 dsi->supplies[0].supply = "vddcore";
1407 dsi->supplies[1].supply = "vddio";
1408 ret = devm_regulator_bulk_get(&pdev->dev, ARRAY_SIZE(dsi->supplies),
1411 dev_info(&pdev->dev, "failed to get regulators: %d\n", ret);
1412 return -EPROBE_DEFER;
1415 dsi->pll_clk = devm_clk_get(&pdev->dev, "pll_clk");
1416 if (IS_ERR(dsi->pll_clk)) {
1417 dev_info(&pdev->dev, "failed to get dsi pll input clock\n");
1418 return -EPROBE_DEFER;
1421 dsi->bus_clk = devm_clk_get(&pdev->dev, "bus_clk");
1422 if (IS_ERR(dsi->bus_clk)) {
1423 dev_info(&pdev->dev, "failed to get dsi bus clock\n");
1424 return -EPROBE_DEFER;
1427 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1428 dsi->reg_base = devm_ioremap_resource(&pdev->dev, res);
1429 if (!dsi->reg_base) {
1430 dev_err(&pdev->dev, "failed to remap io region\n");
1431 return -EADDRNOTAVAIL;
1434 dsi->phy = devm_phy_get(&pdev->dev, "dsim");
1435 if (IS_ERR(dsi->phy)) {
1436 dev_info(&pdev->dev, "failed to get dsim phy\n");
1437 return -EPROBE_DEFER;
1440 dsi->irq = platform_get_irq(pdev, 0);
1442 dev_err(&pdev->dev, "failed to request dsi irq resource\n");
1446 irq_set_status_flags(dsi->irq, IRQ_NOAUTOEN);
1447 ret = devm_request_threaded_irq(&pdev->dev, dsi->irq, NULL,
1448 exynos_dsi_irq, IRQF_ONESHOT,
1449 dev_name(&pdev->dev), dsi);
1451 dev_err(&pdev->dev, "failed to request dsi irq\n");
1455 exynos_dsi_display.ctx = dsi;
1457 platform_set_drvdata(pdev, &exynos_dsi_display);
1458 exynos_drm_display_register(&exynos_dsi_display);
1460 return mipi_dsi_host_register(&dsi->dsi_host);
1463 static int exynos_dsi_remove(struct platform_device *pdev)
1465 struct exynos_dsi *dsi = exynos_dsi_display.ctx;
1467 exynos_dsi_dpms(&exynos_dsi_display, DRM_MODE_DPMS_OFF);
1469 exynos_drm_display_unregister(&exynos_dsi_display);
1470 mipi_dsi_host_unregister(&dsi->dsi_host);
1476 static int exynos_dsi_resume(struct device *dev)
1478 struct exynos_dsi *dsi = exynos_dsi_display.ctx;
1480 if (dsi->state & DSIM_STATE_ENABLED) {
1481 dsi->state &= ~DSIM_STATE_ENABLED;
1482 exynos_dsi_enable(dsi);
1488 static int exynos_dsi_suspend(struct device *dev)
1490 struct exynos_dsi *dsi = exynos_dsi_display.ctx;
1492 if (dsi->state & DSIM_STATE_ENABLED) {
1493 exynos_dsi_disable(dsi);
1494 dsi->state |= DSIM_STATE_ENABLED;
1501 static const struct dev_pm_ops exynos_dsi_pm_ops = {
1502 SET_SYSTEM_SLEEP_PM_OPS(exynos_dsi_suspend, exynos_dsi_resume)
1505 static struct of_device_id exynos_dsi_of_match[] = {
1506 { .compatible = "samsung,exynos4210-mipi-dsi" },
1510 struct platform_driver dsi_driver = {
1511 .probe = exynos_dsi_probe,
1512 .remove = exynos_dsi_remove,
1514 .name = "exynos-dsi",
1515 .owner = THIS_MODULE,
1516 .pm = &exynos_dsi_pm_ops,
1517 .of_match_table = exynos_dsi_of_match,
1521 MODULE_AUTHOR("Tomasz Figa <t.figa@samsung.com>");
1522 MODULE_AUTHOR("Andrzej Hajda <a.hajda@samsung.com>");
1523 MODULE_DESCRIPTION("Samsung SoC MIPI DSI Master");
1524 MODULE_LICENSE("GPL v2");