2 * Samsung SoC MIPI DSI Master driver.
4 * Copyright (c) 2014 Samsung Electronics Co., Ltd
6 * Contacts: Tomasz Figa <t.figa@samsung.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
14 #include <drm/drm_crtc_helper.h>
15 #include <drm/drm_mipi_dsi.h>
16 #include <drm/drm_panel.h>
18 #include <linux/clk.h>
19 #include <linux/irq.h>
20 #include <linux/phy/phy.h>
21 #include <linux/regulator/consumer.h>
22 #include <linux/component.h>
24 #include <video/mipi_display.h>
25 #include <video/videomode.h>
27 #include "exynos_drm_drv.h"
29 /* returns true iff both arguments logically differs */
30 #define NEQV(a, b) (!(a) ^ !(b))
32 #define DSIM_STATUS_REG 0x0 /* Status register */
33 #define DSIM_SWRST_REG 0x4 /* Software reset register */
34 #define DSIM_CLKCTRL_REG 0x8 /* Clock control register */
35 #define DSIM_TIMEOUT_REG 0xc /* Time out register */
36 #define DSIM_CONFIG_REG 0x10 /* Configuration register */
37 #define DSIM_ESCMODE_REG 0x14 /* Escape mode register */
39 /* Main display image resolution register */
40 #define DSIM_MDRESOL_REG 0x18
41 #define DSIM_MVPORCH_REG 0x1c /* Main display Vporch register */
42 #define DSIM_MHPORCH_REG 0x20 /* Main display Hporch register */
43 #define DSIM_MSYNC_REG 0x24 /* Main display sync area register */
45 /* Sub display image resolution register */
46 #define DSIM_SDRESOL_REG 0x28
47 #define DSIM_INTSRC_REG 0x2c /* Interrupt source register */
48 #define DSIM_INTMSK_REG 0x30 /* Interrupt mask register */
49 #define DSIM_PKTHDR_REG 0x34 /* Packet Header FIFO register */
50 #define DSIM_PAYLOAD_REG 0x38 /* Payload FIFO register */
51 #define DSIM_RXFIFO_REG 0x3c /* Read FIFO register */
52 #define DSIM_FIFOTHLD_REG 0x40 /* FIFO threshold level register */
53 #define DSIM_FIFOCTRL_REG 0x44 /* FIFO status and control register */
55 /* FIFO memory AC characteristic register */
56 #define DSIM_PLLCTRL_REG 0x4c /* PLL control register */
57 #define DSIM_PLLTMR_REG 0x50 /* PLL timer register */
58 #define DSIM_PHYACCHR_REG 0x54 /* D-PHY AC characteristic register */
59 #define DSIM_PHYACCHR1_REG 0x58 /* D-PHY AC characteristic register1 */
62 #define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0)
63 #define DSIM_STOP_STATE_CLK (1 << 8)
64 #define DSIM_TX_READY_HS_CLK (1 << 10)
65 #define DSIM_PLL_STABLE (1 << 31)
68 #define DSIM_FUNCRST (1 << 16)
69 #define DSIM_SWRST (1 << 0)
72 #define DSIM_LPDR_TIMEOUT(x) ((x) << 0)
73 #define DSIM_BTA_TIMEOUT(x) ((x) << 16)
76 #define DSIM_ESC_PRESCALER(x) (((x) & 0xffff) << 0)
77 #define DSIM_ESC_PRESCALER_MASK (0xffff << 0)
78 #define DSIM_LANE_ESC_CLK_EN_CLK (1 << 19)
79 #define DSIM_LANE_ESC_CLK_EN_DATA(x) (((x) & 0xf) << 20)
80 #define DSIM_LANE_ESC_CLK_EN_DATA_MASK (0xf << 20)
81 #define DSIM_BYTE_CLKEN (1 << 24)
82 #define DSIM_BYTE_CLK_SRC(x) (((x) & 0x3) << 25)
83 #define DSIM_BYTE_CLK_SRC_MASK (0x3 << 25)
84 #define DSIM_PLL_BYPASS (1 << 27)
85 #define DSIM_ESC_CLKEN (1 << 28)
86 #define DSIM_TX_REQUEST_HSCLK (1 << 31)
89 #define DSIM_LANE_EN_CLK (1 << 0)
90 #define DSIM_LANE_EN(x) (((x) & 0xf) << 1)
91 #define DSIM_NUM_OF_DATA_LANE(x) (((x) & 0x3) << 5)
92 #define DSIM_SUB_PIX_FORMAT(x) (((x) & 0x7) << 8)
93 #define DSIM_MAIN_PIX_FORMAT_MASK (0x7 << 12)
94 #define DSIM_MAIN_PIX_FORMAT_RGB888 (0x7 << 12)
95 #define DSIM_MAIN_PIX_FORMAT_RGB666 (0x6 << 12)
96 #define DSIM_MAIN_PIX_FORMAT_RGB666_P (0x5 << 12)
97 #define DSIM_MAIN_PIX_FORMAT_RGB565 (0x4 << 12)
98 #define DSIM_SUB_VC (((x) & 0x3) << 16)
99 #define DSIM_MAIN_VC (((x) & 0x3) << 18)
100 #define DSIM_HSA_MODE (1 << 20)
101 #define DSIM_HBP_MODE (1 << 21)
102 #define DSIM_HFP_MODE (1 << 22)
103 #define DSIM_HSE_MODE (1 << 23)
104 #define DSIM_AUTO_MODE (1 << 24)
105 #define DSIM_VIDEO_MODE (1 << 25)
106 #define DSIM_BURST_MODE (1 << 26)
107 #define DSIM_SYNC_INFORM (1 << 27)
108 #define DSIM_EOT_DISABLE (1 << 28)
109 #define DSIM_MFLUSH_VS (1 << 29)
112 #define DSIM_TX_TRIGGER_RST (1 << 4)
113 #define DSIM_TX_LPDT_LP (1 << 6)
114 #define DSIM_CMD_LPDT_LP (1 << 7)
115 #define DSIM_FORCE_BTA (1 << 16)
116 #define DSIM_FORCE_STOP_STATE (1 << 20)
117 #define DSIM_STOP_STATE_CNT(x) (((x) & 0x7ff) << 21)
118 #define DSIM_STOP_STATE_CNT_MASK (0x7ff << 21)
121 #define DSIM_MAIN_STAND_BY (1 << 31)
122 #define DSIM_MAIN_VRESOL(x) (((x) & 0x7ff) << 16)
123 #define DSIM_MAIN_HRESOL(x) (((x) & 0X7ff) << 0)
126 #define DSIM_CMD_ALLOW(x) ((x) << 28)
127 #define DSIM_STABLE_VFP(x) ((x) << 16)
128 #define DSIM_MAIN_VBP(x) ((x) << 0)
129 #define DSIM_CMD_ALLOW_MASK (0xf << 28)
130 #define DSIM_STABLE_VFP_MASK (0x7ff << 16)
131 #define DSIM_MAIN_VBP_MASK (0x7ff << 0)
134 #define DSIM_MAIN_HFP(x) ((x) << 16)
135 #define DSIM_MAIN_HBP(x) ((x) << 0)
136 #define DSIM_MAIN_HFP_MASK ((0xffff) << 16)
137 #define DSIM_MAIN_HBP_MASK ((0xffff) << 0)
140 #define DSIM_MAIN_VSA(x) ((x) << 22)
141 #define DSIM_MAIN_HSA(x) ((x) << 0)
142 #define DSIM_MAIN_VSA_MASK ((0x3ff) << 22)
143 #define DSIM_MAIN_HSA_MASK ((0xffff) << 0)
146 #define DSIM_SUB_STANDY(x) ((x) << 31)
147 #define DSIM_SUB_VRESOL(x) ((x) << 16)
148 #define DSIM_SUB_HRESOL(x) ((x) << 0)
149 #define DSIM_SUB_STANDY_MASK ((0x1) << 31)
150 #define DSIM_SUB_VRESOL_MASK ((0x7ff) << 16)
151 #define DSIM_SUB_HRESOL_MASK ((0x7ff) << 0)
154 #define DSIM_INT_PLL_STABLE (1 << 31)
155 #define DSIM_INT_SW_RST_RELEASE (1 << 30)
156 #define DSIM_INT_SFR_FIFO_EMPTY (1 << 29)
157 #define DSIM_INT_BTA (1 << 25)
158 #define DSIM_INT_FRAME_DONE (1 << 24)
159 #define DSIM_INT_RX_TIMEOUT (1 << 21)
160 #define DSIM_INT_BTA_TIMEOUT (1 << 20)
161 #define DSIM_INT_RX_DONE (1 << 18)
162 #define DSIM_INT_RX_TE (1 << 17)
163 #define DSIM_INT_RX_ACK (1 << 16)
164 #define DSIM_INT_RX_ECC_ERR (1 << 15)
165 #define DSIM_INT_RX_CRC_ERR (1 << 14)
168 #define DSIM_RX_DATA_FULL (1 << 25)
169 #define DSIM_RX_DATA_EMPTY (1 << 24)
170 #define DSIM_SFR_HEADER_FULL (1 << 23)
171 #define DSIM_SFR_HEADER_EMPTY (1 << 22)
172 #define DSIM_SFR_PAYLOAD_FULL (1 << 21)
173 #define DSIM_SFR_PAYLOAD_EMPTY (1 << 20)
174 #define DSIM_I80_HEADER_FULL (1 << 19)
175 #define DSIM_I80_HEADER_EMPTY (1 << 18)
176 #define DSIM_I80_PAYLOAD_FULL (1 << 17)
177 #define DSIM_I80_PAYLOAD_EMPTY (1 << 16)
178 #define DSIM_SD_HEADER_FULL (1 << 15)
179 #define DSIM_SD_HEADER_EMPTY (1 << 14)
180 #define DSIM_SD_PAYLOAD_FULL (1 << 13)
181 #define DSIM_SD_PAYLOAD_EMPTY (1 << 12)
182 #define DSIM_MD_HEADER_FULL (1 << 11)
183 #define DSIM_MD_HEADER_EMPTY (1 << 10)
184 #define DSIM_MD_PAYLOAD_FULL (1 << 9)
185 #define DSIM_MD_PAYLOAD_EMPTY (1 << 8)
186 #define DSIM_RX_FIFO (1 << 4)
187 #define DSIM_SFR_FIFO (1 << 3)
188 #define DSIM_I80_FIFO (1 << 2)
189 #define DSIM_SD_FIFO (1 << 1)
190 #define DSIM_MD_FIFO (1 << 0)
193 #define DSIM_AFC_EN (1 << 14)
194 #define DSIM_AFC_CTL(x) (((x) & 0x7) << 5)
197 #define DSIM_FREQ_BAND(x) ((x) << 24)
198 #define DSIM_PLL_EN (1 << 23)
199 #define DSIM_PLL_P(x) ((x) << 13)
200 #define DSIM_PLL_M(x) ((x) << 4)
201 #define DSIM_PLL_S(x) ((x) << 1)
203 #define DSI_MAX_BUS_WIDTH 4
204 #define DSI_NUM_VIRTUAL_CHANNELS 4
205 #define DSI_TX_FIFO_SIZE 2048
206 #define DSI_RX_FIFO_SIZE 256
207 #define DSI_XFER_TIMEOUT_MS 100
208 #define DSI_RX_FIFO_EMPTY 0x30800002
210 enum exynos_dsi_transfer_type {
215 struct exynos_dsi_transfer {
216 struct list_head list;
217 struct completion completed;
223 const u8 *tx_payload;
232 #define DSIM_STATE_ENABLED BIT(0)
233 #define DSIM_STATE_INITIALIZED BIT(1)
234 #define DSIM_STATE_CMD_LPM BIT(2)
237 struct mipi_dsi_host dsi_host;
238 struct drm_connector connector;
239 struct drm_encoder *encoder;
240 struct device_node *panel_node;
241 struct drm_panel *panel;
244 void __iomem *reg_base;
248 struct regulator_bulk_data supplies[2];
260 struct drm_property *brightness;
261 struct completion completed;
263 spinlock_t transfer_lock; /* protects transfer_list */
264 struct list_head transfer_list;
267 #define host_to_dsi(host) container_of(host, struct exynos_dsi, dsi_host)
268 #define connector_to_dsi(c) container_of(c, struct exynos_dsi, connector)
270 static void exynos_dsi_wait_for_reset(struct exynos_dsi *dsi)
272 if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300)))
275 dev_err(dsi->dev, "timeout waiting for reset\n");
278 static void exynos_dsi_reset(struct exynos_dsi *dsi)
280 reinit_completion(&dsi->completed);
281 writel(DSIM_SWRST, dsi->reg_base + DSIM_SWRST_REG);
285 #define MHZ (1000*1000)
288 static unsigned long exynos_dsi_pll_find_pms(struct exynos_dsi *dsi,
289 unsigned long fin, unsigned long fout, u8 *p, u16 *m, u8 *s)
291 unsigned long best_freq = 0;
292 u32 min_delta = 0xffffffff;
294 u8 _p, uninitialized_var(best_p);
295 u16 _m, uninitialized_var(best_m);
296 u8 _s, uninitialized_var(best_s);
298 p_min = DIV_ROUND_UP(fin, (12 * MHZ));
299 p_max = fin / (6 * MHZ);
301 for (_p = p_min; _p <= p_max; ++_p) {
302 for (_s = 0; _s <= 5; ++_s) {
306 tmp = (u64)fout * (_p << _s);
309 if (_m < 41 || _m > 125)
314 if (tmp < 500 * MHZ || tmp > 1000 * MHZ)
318 do_div(tmp, _p << _s);
320 delta = abs(fout - tmp);
321 if (delta < min_delta) {
340 static unsigned long exynos_dsi_set_pll(struct exynos_dsi *dsi,
343 static const unsigned long freq_bands[] = {
344 100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ,
345 270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ,
346 510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ,
347 770 * MHZ, 870 * MHZ, 950 * MHZ,
349 unsigned long fin, fout;
355 clk_set_rate(dsi->pll_clk, dsi->pll_clk_rate);
357 fin = clk_get_rate(dsi->pll_clk);
359 dev_err(dsi->dev, "failed to get PLL clock frequency\n");
363 dev_dbg(dsi->dev, "PLL input frequency: %lu\n", fin);
365 fout = exynos_dsi_pll_find_pms(dsi, fin, freq, &p, &m, &s);
368 "failed to find PLL PMS for requested frequency\n");
372 for (band = 0; band < ARRAY_SIZE(freq_bands); ++band)
373 if (fout < freq_bands[band])
376 dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d), band %d\n", fout,
379 writel(500, dsi->reg_base + DSIM_PLLTMR_REG);
381 reg = DSIM_FREQ_BAND(band) | DSIM_PLL_EN
382 | DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s);
383 writel(reg, dsi->reg_base + DSIM_PLLCTRL_REG);
387 if (timeout-- == 0) {
388 dev_err(dsi->dev, "PLL failed to stabilize\n");
391 reg = readl(dsi->reg_base + DSIM_STATUS_REG);
392 } while ((reg & DSIM_PLL_STABLE) == 0);
397 static int exynos_dsi_enable_clock(struct exynos_dsi *dsi)
399 unsigned long hs_clk, byte_clk, esc_clk;
400 unsigned long esc_div;
403 hs_clk = exynos_dsi_set_pll(dsi, dsi->burst_clk_rate);
405 dev_err(dsi->dev, "failed to configure DSI PLL\n");
409 byte_clk = hs_clk / 8;
410 esc_div = DIV_ROUND_UP(byte_clk, dsi->esc_clk_rate);
411 esc_clk = byte_clk / esc_div;
413 if (esc_clk > 20 * MHZ) {
415 esc_clk = byte_clk / esc_div;
418 dev_dbg(dsi->dev, "hs_clk = %lu, byte_clk = %lu, esc_clk = %lu\n",
419 hs_clk, byte_clk, esc_clk);
421 reg = readl(dsi->reg_base + DSIM_CLKCTRL_REG);
422 reg &= ~(DSIM_ESC_PRESCALER_MASK | DSIM_LANE_ESC_CLK_EN_CLK
423 | DSIM_LANE_ESC_CLK_EN_DATA_MASK | DSIM_PLL_BYPASS
424 | DSIM_BYTE_CLK_SRC_MASK);
425 reg |= DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN
426 | DSIM_ESC_PRESCALER(esc_div)
427 | DSIM_LANE_ESC_CLK_EN_CLK
428 | DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1)
429 | DSIM_BYTE_CLK_SRC(0)
430 | DSIM_TX_REQUEST_HSCLK;
431 writel(reg, dsi->reg_base + DSIM_CLKCTRL_REG);
436 static void exynos_dsi_disable_clock(struct exynos_dsi *dsi)
440 reg = readl(dsi->reg_base + DSIM_CLKCTRL_REG);
441 reg &= ~(DSIM_LANE_ESC_CLK_EN_CLK | DSIM_LANE_ESC_CLK_EN_DATA_MASK
442 | DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN);
443 writel(reg, dsi->reg_base + DSIM_CLKCTRL_REG);
445 reg = readl(dsi->reg_base + DSIM_PLLCTRL_REG);
447 writel(reg, dsi->reg_base + DSIM_PLLCTRL_REG);
450 static int exynos_dsi_init_link(struct exynos_dsi *dsi)
456 /* Initialize FIFO pointers */
457 reg = readl(dsi->reg_base + DSIM_FIFOCTRL_REG);
459 writel(reg, dsi->reg_base + DSIM_FIFOCTRL_REG);
461 usleep_range(9000, 11000);
464 writel(reg, dsi->reg_base + DSIM_FIFOCTRL_REG);
466 usleep_range(9000, 11000);
468 /* DSI configuration */
471 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
472 reg |= DSIM_VIDEO_MODE;
474 if (!(dsi->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH))
475 reg |= DSIM_MFLUSH_VS;
476 if (!(dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET))
477 reg |= DSIM_EOT_DISABLE;
478 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
479 reg |= DSIM_SYNC_INFORM;
480 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
481 reg |= DSIM_BURST_MODE;
482 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT)
483 reg |= DSIM_AUTO_MODE;
484 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE)
485 reg |= DSIM_HSE_MODE;
486 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HFP))
487 reg |= DSIM_HFP_MODE;
488 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HBP))
489 reg |= DSIM_HBP_MODE;
490 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSA))
491 reg |= DSIM_HSA_MODE;
494 switch (dsi->format) {
495 case MIPI_DSI_FMT_RGB888:
496 reg |= DSIM_MAIN_PIX_FORMAT_RGB888;
498 case MIPI_DSI_FMT_RGB666:
499 reg |= DSIM_MAIN_PIX_FORMAT_RGB666;
501 case MIPI_DSI_FMT_RGB666_PACKED:
502 reg |= DSIM_MAIN_PIX_FORMAT_RGB666_P;
504 case MIPI_DSI_FMT_RGB565:
505 reg |= DSIM_MAIN_PIX_FORMAT_RGB565;
508 dev_err(dsi->dev, "invalid pixel format\n");
512 reg |= DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1);
514 writel(reg, dsi->reg_base + DSIM_CONFIG_REG);
516 reg |= DSIM_LANE_EN_CLK;
517 writel(reg, dsi->reg_base + DSIM_CONFIG_REG);
519 lanes_mask = BIT(dsi->lanes) - 1;
520 reg |= DSIM_LANE_EN(lanes_mask);
521 writel(reg, dsi->reg_base + DSIM_CONFIG_REG);
523 /* Check clock and data lane state are stop state */
526 if (timeout-- == 0) {
527 dev_err(dsi->dev, "waiting for bus lanes timed out\n");
531 reg = readl(dsi->reg_base + DSIM_STATUS_REG);
532 if ((reg & DSIM_STOP_STATE_DAT(lanes_mask))
533 != DSIM_STOP_STATE_DAT(lanes_mask))
535 } while (!(reg & (DSIM_STOP_STATE_CLK | DSIM_TX_READY_HS_CLK)));
537 reg = readl(dsi->reg_base + DSIM_ESCMODE_REG);
538 reg &= ~DSIM_STOP_STATE_CNT_MASK;
539 reg |= DSIM_STOP_STATE_CNT(0xf);
540 writel(reg, dsi->reg_base + DSIM_ESCMODE_REG);
542 reg = DSIM_BTA_TIMEOUT(0xff) | DSIM_LPDR_TIMEOUT(0xffff);
543 writel(reg, dsi->reg_base + DSIM_TIMEOUT_REG);
548 static void exynos_dsi_set_display_mode(struct exynos_dsi *dsi)
550 struct videomode *vm = &dsi->vm;
553 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
554 reg = DSIM_CMD_ALLOW(0xf)
555 | DSIM_STABLE_VFP(vm->vfront_porch)
556 | DSIM_MAIN_VBP(vm->vback_porch);
557 writel(reg, dsi->reg_base + DSIM_MVPORCH_REG);
559 reg = DSIM_MAIN_HFP(vm->hfront_porch)
560 | DSIM_MAIN_HBP(vm->hback_porch);
561 writel(reg, dsi->reg_base + DSIM_MHPORCH_REG);
563 reg = DSIM_MAIN_VSA(vm->vsync_len)
564 | DSIM_MAIN_HSA(vm->hsync_len);
565 writel(reg, dsi->reg_base + DSIM_MSYNC_REG);
568 reg = DSIM_MAIN_HRESOL(vm->hactive) | DSIM_MAIN_VRESOL(vm->vactive);
569 writel(reg, dsi->reg_base + DSIM_MDRESOL_REG);
571 dev_dbg(dsi->dev, "LCD size = %dx%d\n", vm->hactive, vm->vactive);
574 static void exynos_dsi_set_display_enable(struct exynos_dsi *dsi, bool enable)
578 reg = readl(dsi->reg_base + DSIM_MDRESOL_REG);
580 reg |= DSIM_MAIN_STAND_BY;
582 reg &= ~DSIM_MAIN_STAND_BY;
583 writel(reg, dsi->reg_base + DSIM_MDRESOL_REG);
586 static int exynos_dsi_wait_for_hdr_fifo(struct exynos_dsi *dsi)
591 u32 reg = readl(dsi->reg_base + DSIM_FIFOCTRL_REG);
593 if (!(reg & DSIM_SFR_HEADER_FULL))
597 usleep_range(950, 1050);
603 static void exynos_dsi_set_cmd_lpm(struct exynos_dsi *dsi, bool lpm)
605 u32 v = readl(dsi->reg_base + DSIM_ESCMODE_REG);
608 v |= DSIM_CMD_LPDT_LP;
610 v &= ~DSIM_CMD_LPDT_LP;
612 writel(v, dsi->reg_base + DSIM_ESCMODE_REG);
615 static void exynos_dsi_force_bta(struct exynos_dsi *dsi)
617 u32 v = readl(dsi->reg_base + DSIM_ESCMODE_REG);
620 writel(v, dsi->reg_base + DSIM_ESCMODE_REG);
623 static void exynos_dsi_send_to_fifo(struct exynos_dsi *dsi,
624 struct exynos_dsi_transfer *xfer)
626 struct device *dev = dsi->dev;
627 const u8 *payload = xfer->tx_payload + xfer->tx_done;
628 u16 length = xfer->tx_len - xfer->tx_done;
629 bool first = !xfer->tx_done;
632 dev_dbg(dev, "< xfer %p: tx len %u, done %u, rx len %u, done %u\n",
633 xfer, xfer->tx_len, xfer->tx_done, xfer->rx_len, xfer->rx_done);
635 if (length > DSI_TX_FIFO_SIZE)
636 length = DSI_TX_FIFO_SIZE;
638 xfer->tx_done += length;
641 while (length >= 4) {
642 reg = (payload[3] << 24) | (payload[2] << 16)
643 | (payload[1] << 8) | payload[0];
644 writel(reg, dsi->reg_base + DSIM_PAYLOAD_REG);
652 reg |= payload[2] << 16;
655 reg |= payload[1] << 8;
659 writel(reg, dsi->reg_base + DSIM_PAYLOAD_REG);
666 /* Send packet header */
670 reg = (xfer->data[1] << 16) | (xfer->data[0] << 8) | xfer->data_id;
671 if (exynos_dsi_wait_for_hdr_fifo(dsi)) {
672 dev_err(dev, "waiting for header FIFO timed out\n");
676 if (NEQV(xfer->flags & MIPI_DSI_MSG_USE_LPM,
677 dsi->state & DSIM_STATE_CMD_LPM)) {
678 exynos_dsi_set_cmd_lpm(dsi, xfer->flags & MIPI_DSI_MSG_USE_LPM);
679 dsi->state ^= DSIM_STATE_CMD_LPM;
682 writel(reg, dsi->reg_base + DSIM_PKTHDR_REG);
684 if (xfer->flags & MIPI_DSI_MSG_REQ_ACK)
685 exynos_dsi_force_bta(dsi);
688 static void exynos_dsi_read_from_fifo(struct exynos_dsi *dsi,
689 struct exynos_dsi_transfer *xfer)
691 u8 *payload = xfer->rx_payload + xfer->rx_done;
692 bool first = !xfer->rx_done;
693 struct device *dev = dsi->dev;
698 reg = readl(dsi->reg_base + DSIM_RXFIFO_REG);
700 switch (reg & 0x3f) {
701 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
702 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
703 if (xfer->rx_len >= 2) {
704 payload[1] = reg >> 16;
708 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
709 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
710 payload[0] = reg >> 8;
712 xfer->rx_len = xfer->rx_done;
715 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
716 dev_err(dev, "DSI Error Report: 0x%04x\n",
717 (reg >> 8) & 0xffff);
722 length = (reg >> 8) & 0xffff;
723 if (length > xfer->rx_len) {
725 "response too long (%u > %u bytes), stripping\n",
726 xfer->rx_len, length);
727 length = xfer->rx_len;
728 } else if (length < xfer->rx_len)
729 xfer->rx_len = length;
732 length = xfer->rx_len - xfer->rx_done;
733 xfer->rx_done += length;
735 /* Receive payload */
736 while (length >= 4) {
737 reg = readl(dsi->reg_base + DSIM_RXFIFO_REG);
738 payload[0] = (reg >> 0) & 0xff;
739 payload[1] = (reg >> 8) & 0xff;
740 payload[2] = (reg >> 16) & 0xff;
741 payload[3] = (reg >> 24) & 0xff;
747 reg = readl(dsi->reg_base + DSIM_RXFIFO_REG);
750 payload[2] = (reg >> 16) & 0xff;
753 payload[1] = (reg >> 8) & 0xff;
756 payload[0] = reg & 0xff;
760 if (xfer->rx_done == xfer->rx_len)
764 length = DSI_RX_FIFO_SIZE / 4;
766 reg = readl(dsi->reg_base + DSIM_RXFIFO_REG);
767 if (reg == DSI_RX_FIFO_EMPTY)
772 static void exynos_dsi_transfer_start(struct exynos_dsi *dsi)
775 struct exynos_dsi_transfer *xfer;
779 spin_lock_irqsave(&dsi->transfer_lock, flags);
781 if (list_empty(&dsi->transfer_list)) {
782 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
786 xfer = list_first_entry(&dsi->transfer_list,
787 struct exynos_dsi_transfer, list);
789 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
791 if (xfer->tx_len && xfer->tx_done == xfer->tx_len)
795 exynos_dsi_send_to_fifo(dsi, xfer);
797 if (xfer->tx_len || xfer->rx_len)
801 complete(&xfer->completed);
803 spin_lock_irqsave(&dsi->transfer_lock, flags);
805 list_del_init(&xfer->list);
806 start = !list_empty(&dsi->transfer_list);
808 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
814 static bool exynos_dsi_transfer_finish(struct exynos_dsi *dsi)
816 struct exynos_dsi_transfer *xfer;
820 spin_lock_irqsave(&dsi->transfer_lock, flags);
822 if (list_empty(&dsi->transfer_list)) {
823 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
827 xfer = list_first_entry(&dsi->transfer_list,
828 struct exynos_dsi_transfer, list);
830 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
833 "> xfer %p, tx_len %u, tx_done %u, rx_len %u, rx_done %u\n",
834 xfer, xfer->tx_len, xfer->tx_done, xfer->rx_len, xfer->rx_done);
836 if (xfer->tx_done != xfer->tx_len)
839 if (xfer->rx_done != xfer->rx_len)
840 exynos_dsi_read_from_fifo(dsi, xfer);
842 if (xfer->rx_done != xfer->rx_len)
845 spin_lock_irqsave(&dsi->transfer_lock, flags);
847 list_del_init(&xfer->list);
848 start = !list_empty(&dsi->transfer_list);
850 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
854 complete(&xfer->completed);
859 static void exynos_dsi_remove_transfer(struct exynos_dsi *dsi,
860 struct exynos_dsi_transfer *xfer)
865 spin_lock_irqsave(&dsi->transfer_lock, flags);
867 if (!list_empty(&dsi->transfer_list) &&
868 xfer == list_first_entry(&dsi->transfer_list,
869 struct exynos_dsi_transfer, list)) {
870 list_del_init(&xfer->list);
871 start = !list_empty(&dsi->transfer_list);
872 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
874 exynos_dsi_transfer_start(dsi);
878 list_del_init(&xfer->list);
880 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
883 static int exynos_dsi_transfer(struct exynos_dsi *dsi,
884 struct exynos_dsi_transfer *xfer)
891 xfer->result = -ETIMEDOUT;
892 init_completion(&xfer->completed);
894 spin_lock_irqsave(&dsi->transfer_lock, flags);
896 stopped = list_empty(&dsi->transfer_list);
897 list_add_tail(&xfer->list, &dsi->transfer_list);
899 spin_unlock_irqrestore(&dsi->transfer_lock, flags);
902 exynos_dsi_transfer_start(dsi);
904 wait_for_completion_timeout(&xfer->completed,
905 msecs_to_jiffies(DSI_XFER_TIMEOUT_MS));
906 if (xfer->result == -ETIMEDOUT) {
907 exynos_dsi_remove_transfer(dsi, xfer);
908 dev_err(dsi->dev, "xfer timed out: %*ph %*ph\n", 2, xfer->data,
909 xfer->tx_len, xfer->tx_payload);
913 /* Also covers hardware timeout condition */
917 static irqreturn_t exynos_dsi_irq(int irq, void *dev_id)
919 struct exynos_dsi *dsi = dev_id;
922 status = readl(dsi->reg_base + DSIM_INTSRC_REG);
924 static unsigned long int j;
925 if (printk_timed_ratelimit(&j, 500))
926 dev_warn(dsi->dev, "spurious interrupt\n");
929 writel(status, dsi->reg_base + DSIM_INTSRC_REG);
931 if (status & DSIM_INT_SW_RST_RELEASE) {
932 u32 mask = ~(DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY);
933 writel(mask, dsi->reg_base + DSIM_INTMSK_REG);
934 complete(&dsi->completed);
938 if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY)))
941 if (exynos_dsi_transfer_finish(dsi))
942 exynos_dsi_transfer_start(dsi);
947 static int exynos_dsi_init(struct exynos_dsi *dsi)
949 exynos_dsi_enable_clock(dsi);
950 exynos_dsi_reset(dsi);
951 enable_irq(dsi->irq);
952 exynos_dsi_wait_for_reset(dsi);
953 exynos_dsi_init_link(dsi);
958 static int exynos_dsi_host_attach(struct mipi_dsi_host *host,
959 struct mipi_dsi_device *device)
961 struct exynos_dsi *dsi = host_to_dsi(host);
963 dsi->lanes = device->lanes;
964 dsi->format = device->format;
965 dsi->mode_flags = device->mode_flags;
966 dsi->panel_node = device->dev.of_node;
968 if (dsi->connector.dev)
969 drm_helper_hpd_irq_event(dsi->connector.dev);
974 static int exynos_dsi_host_detach(struct mipi_dsi_host *host,
975 struct mipi_dsi_device *device)
977 struct exynos_dsi *dsi = host_to_dsi(host);
979 dsi->panel_node = NULL;
981 if (dsi->connector.dev)
982 drm_helper_hpd_irq_event(dsi->connector.dev);
987 /* distinguish between short and long DSI packet types */
988 static bool exynos_dsi_is_short_dsi_type(u8 type)
990 return (type & 0x0f) <= 8;
993 static ssize_t exynos_dsi_host_transfer(struct mipi_dsi_host *host,
994 struct mipi_dsi_msg *msg)
996 struct exynos_dsi *dsi = host_to_dsi(host);
997 struct exynos_dsi_transfer xfer;
1000 if (!(dsi->state & DSIM_STATE_INITIALIZED)) {
1001 ret = exynos_dsi_init(dsi);
1004 dsi->state |= DSIM_STATE_INITIALIZED;
1007 if (msg->tx_len == 0)
1010 xfer.data_id = msg->type | (msg->channel << 6);
1012 if (exynos_dsi_is_short_dsi_type(msg->type)) {
1013 const char *tx_buf = msg->tx_buf;
1015 if (msg->tx_len > 2)
1018 xfer.data[0] = tx_buf[0];
1019 xfer.data[1] = (msg->tx_len == 2) ? tx_buf[1] : 0;
1021 xfer.tx_len = msg->tx_len;
1022 xfer.data[0] = msg->tx_len & 0xff;
1023 xfer.data[1] = msg->tx_len >> 8;
1024 xfer.tx_payload = msg->tx_buf;
1027 xfer.rx_len = msg->rx_len;
1028 xfer.rx_payload = msg->rx_buf;
1029 xfer.flags = msg->flags;
1031 ret = exynos_dsi_transfer(dsi, &xfer);
1032 return (ret < 0) ? ret : xfer.rx_done;
1035 static const struct mipi_dsi_host_ops exynos_dsi_ops = {
1036 .attach = exynos_dsi_host_attach,
1037 .detach = exynos_dsi_host_detach,
1038 .transfer = exynos_dsi_host_transfer,
1041 static int exynos_dsi_poweron(struct exynos_dsi *dsi)
1045 ret = regulator_bulk_enable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
1047 dev_err(dsi->dev, "cannot enable regulators %d\n", ret);
1051 ret = clk_prepare_enable(dsi->bus_clk);
1053 dev_err(dsi->dev, "cannot enable bus clock %d\n", ret);
1057 ret = clk_prepare_enable(dsi->pll_clk);
1059 dev_err(dsi->dev, "cannot enable pll clock %d\n", ret);
1063 ret = phy_power_on(dsi->phy);
1065 dev_err(dsi->dev, "cannot enable phy %d\n", ret);
1072 clk_disable_unprepare(dsi->pll_clk);
1074 clk_disable_unprepare(dsi->bus_clk);
1076 regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
1081 static void exynos_dsi_poweroff(struct exynos_dsi *dsi)
1085 usleep_range(10000, 20000);
1087 if (dsi->state & DSIM_STATE_INITIALIZED) {
1088 dsi->state &= ~DSIM_STATE_INITIALIZED;
1090 exynos_dsi_disable_clock(dsi);
1092 disable_irq(dsi->irq);
1095 dsi->state &= ~DSIM_STATE_CMD_LPM;
1097 phy_power_off(dsi->phy);
1099 clk_disable_unprepare(dsi->pll_clk);
1100 clk_disable_unprepare(dsi->bus_clk);
1102 ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies);
1104 dev_err(dsi->dev, "cannot disable regulators %d\n", ret);
1107 static int exynos_dsi_enable(struct exynos_dsi *dsi)
1111 if (dsi->state & DSIM_STATE_ENABLED)
1114 ret = exynos_dsi_poweron(dsi);
1118 ret = drm_panel_enable(dsi->panel);
1120 exynos_dsi_poweroff(dsi);
1124 exynos_dsi_set_display_mode(dsi);
1125 exynos_dsi_set_display_enable(dsi, true);
1127 dsi->state |= DSIM_STATE_ENABLED;
1132 static void exynos_dsi_disable(struct exynos_dsi *dsi)
1134 if (!(dsi->state & DSIM_STATE_ENABLED))
1137 exynos_dsi_set_display_enable(dsi, false);
1138 drm_panel_disable(dsi->panel);
1139 exynos_dsi_poweroff(dsi);
1141 dsi->state &= ~DSIM_STATE_ENABLED;
1144 static void exynos_dsi_dpms(struct exynos_drm_display *display, int mode)
1146 struct exynos_dsi *dsi = display->ctx;
1150 case DRM_MODE_DPMS_ON:
1151 exynos_dsi_enable(dsi);
1153 case DRM_MODE_DPMS_STANDBY:
1154 case DRM_MODE_DPMS_SUSPEND:
1155 case DRM_MODE_DPMS_OFF:
1156 exynos_dsi_disable(dsi);
1164 static enum drm_connector_status
1165 exynos_dsi_detect(struct drm_connector *connector, bool force)
1167 struct exynos_dsi *dsi = connector_to_dsi(connector);
1170 dsi->panel = of_drm_find_panel(dsi->panel_node);
1172 drm_panel_attach(dsi->panel, &dsi->connector);
1173 } else if (!dsi->panel_node) {
1174 struct exynos_drm_display *display;
1176 display = platform_get_drvdata(to_platform_device(dsi->dev));
1177 exynos_dsi_dpms(display, DRM_MODE_DPMS_OFF);
1178 drm_panel_detach(dsi->panel);
1183 return connector_status_connected;
1185 return connector_status_disconnected;
1188 static void exynos_dsi_connector_destroy(struct drm_connector *connector)
1192 static struct drm_connector_funcs exynos_dsi_connector_funcs = {
1193 .dpms = drm_helper_connector_dpms,
1194 .detect = exynos_dsi_detect,
1195 .fill_modes = drm_helper_probe_single_connector_modes,
1196 .destroy = exynos_dsi_connector_destroy,
1199 static int exynos_dsi_get_modes(struct drm_connector *connector)
1201 struct exynos_dsi *dsi = connector_to_dsi(connector);
1204 return dsi->panel->funcs->get_modes(dsi->panel);
1209 static int exynos_dsi_mode_valid(struct drm_connector *connector,
1210 struct drm_display_mode *mode)
1215 static struct drm_encoder *
1216 exynos_dsi_best_encoder(struct drm_connector *connector)
1218 struct exynos_dsi *dsi = connector_to_dsi(connector);
1220 return dsi->encoder;
1223 static struct drm_connector_helper_funcs exynos_dsi_connector_helper_funcs = {
1224 .get_modes = exynos_dsi_get_modes,
1225 .mode_valid = exynos_dsi_mode_valid,
1226 .best_encoder = exynos_dsi_best_encoder,
1229 static int exynos_dsi_create_connector(struct exynos_drm_display *display,
1230 struct drm_encoder *encoder)
1232 struct exynos_dsi *dsi = display->ctx;
1233 struct drm_connector *connector = &dsi->connector;
1236 dsi->encoder = encoder;
1238 connector->polled = DRM_CONNECTOR_POLL_HPD;
1240 ret = drm_connector_init(encoder->dev, connector,
1241 &exynos_dsi_connector_funcs,
1242 DRM_MODE_CONNECTOR_DSI);
1244 DRM_ERROR("Failed to initialize connector with drm\n");
1248 drm_connector_helper_add(connector, &exynos_dsi_connector_helper_funcs);
1249 drm_connector_register(connector);
1250 drm_mode_connector_attach_encoder(connector, encoder);
1255 static void exynos_dsi_mode_set(struct exynos_drm_display *display,
1256 struct drm_display_mode *mode)
1258 struct exynos_dsi *dsi = display->ctx;
1259 struct videomode *vm = &dsi->vm;
1261 vm->hactive = mode->hdisplay;
1262 vm->vactive = mode->vdisplay;
1263 vm->vfront_porch = mode->vsync_start - mode->vdisplay;
1264 vm->vback_porch = mode->vtotal - mode->vsync_end;
1265 vm->vsync_len = mode->vsync_end - mode->vsync_start;
1266 vm->hfront_porch = mode->hsync_start - mode->hdisplay;
1267 vm->hback_porch = mode->htotal - mode->hsync_end;
1268 vm->hsync_len = mode->hsync_end - mode->hsync_start;
1271 static struct exynos_drm_display_ops exynos_dsi_display_ops = {
1272 .create_connector = exynos_dsi_create_connector,
1273 .mode_set = exynos_dsi_mode_set,
1274 .dpms = exynos_dsi_dpms
1277 static struct exynos_drm_display exynos_dsi_display = {
1278 .type = EXYNOS_DISPLAY_TYPE_LCD,
1279 .ops = &exynos_dsi_display_ops,
1282 /* of_* functions will be removed after merge of of_graph patches */
1283 static struct device_node *
1284 of_get_child_by_name_reg(struct device_node *parent, const char *name, u32 reg)
1286 struct device_node *np;
1288 for_each_child_of_node(parent, np) {
1291 if (!np->name || of_node_cmp(np->name, name))
1294 if (of_property_read_u32(np, "reg", &r) < 0)
1304 static struct device_node *of_graph_get_port_by_reg(struct device_node *parent,
1307 struct device_node *ports, *port;
1309 ports = of_get_child_by_name(parent, "ports");
1313 port = of_get_child_by_name_reg(parent, "port", reg);
1320 static struct device_node *
1321 of_graph_get_endpoint_by_reg(struct device_node *port, u32 reg)
1323 return of_get_child_by_name_reg(port, "endpoint", reg);
1326 static int exynos_dsi_of_read_u32(const struct device_node *np,
1327 const char *propname, u32 *out_value)
1329 int ret = of_property_read_u32(np, propname, out_value);
1332 pr_err("%s: failed to get '%s' property\n", np->full_name,
1343 static int exynos_dsi_parse_dt(struct exynos_dsi *dsi)
1345 struct device *dev = dsi->dev;
1346 struct device_node *node = dev->of_node;
1347 struct device_node *port, *ep;
1350 ret = exynos_dsi_of_read_u32(node, "samsung,pll-clock-frequency",
1351 &dsi->pll_clk_rate);
1355 port = of_graph_get_port_by_reg(node, DSI_PORT_OUT);
1357 dev_err(dev, "no output port specified\n");
1361 ep = of_graph_get_endpoint_by_reg(port, 0);
1364 dev_err(dev, "no endpoint specified in output port\n");
1368 ret = exynos_dsi_of_read_u32(ep, "samsung,burst-clock-frequency",
1369 &dsi->burst_clk_rate);
1373 ret = exynos_dsi_of_read_u32(ep, "samsung,esc-clock-frequency",
1374 &dsi->esc_clk_rate);
1382 static int exynos_dsi_bind(struct device *dev, struct device *master,
1385 struct drm_device *drm_dev = data;
1386 struct exynos_dsi *dsi;
1389 ret = exynos_drm_create_enc_conn(drm_dev, &exynos_dsi_display);
1391 DRM_ERROR("Encoder create [%d] failed with %d\n",
1392 exynos_dsi_display.type, ret);
1396 dsi = exynos_dsi_display.ctx;
1398 return mipi_dsi_host_register(&dsi->dsi_host);
1401 static void exynos_dsi_unbind(struct device *dev, struct device *master,
1404 struct exynos_dsi *dsi = exynos_dsi_display.ctx;
1405 struct drm_encoder *encoder = dsi->encoder;
1407 exynos_dsi_dpms(&exynos_dsi_display, DRM_MODE_DPMS_OFF);
1409 mipi_dsi_host_unregister(&dsi->dsi_host);
1411 encoder->funcs->destroy(encoder);
1412 drm_connector_cleanup(&dsi->connector);
1415 static const struct component_ops exynos_dsi_component_ops = {
1416 .bind = exynos_dsi_bind,
1417 .unbind = exynos_dsi_unbind,
1420 static int exynos_dsi_probe(struct platform_device *pdev)
1422 struct resource *res;
1423 struct exynos_dsi *dsi;
1426 ret = exynos_drm_component_add(&pdev->dev, EXYNOS_DEVICE_TYPE_CONNECTOR,
1427 exynos_dsi_display.type);
1431 dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
1433 dev_err(&pdev->dev, "failed to allocate dsi object.\n");
1435 goto err_del_component;
1438 init_completion(&dsi->completed);
1439 spin_lock_init(&dsi->transfer_lock);
1440 INIT_LIST_HEAD(&dsi->transfer_list);
1442 dsi->dsi_host.ops = &exynos_dsi_ops;
1443 dsi->dsi_host.dev = &pdev->dev;
1445 dsi->dev = &pdev->dev;
1447 ret = exynos_dsi_parse_dt(dsi);
1449 goto err_del_component;
1451 dsi->supplies[0].supply = "vddcore";
1452 dsi->supplies[1].supply = "vddio";
1453 ret = devm_regulator_bulk_get(&pdev->dev, ARRAY_SIZE(dsi->supplies),
1456 dev_info(&pdev->dev, "failed to get regulators: %d\n", ret);
1457 return -EPROBE_DEFER;
1460 dsi->pll_clk = devm_clk_get(&pdev->dev, "pll_clk");
1461 if (IS_ERR(dsi->pll_clk)) {
1462 dev_info(&pdev->dev, "failed to get dsi pll input clock\n");
1463 ret = PTR_ERR(dsi->pll_clk);
1464 goto err_del_component;
1467 dsi->bus_clk = devm_clk_get(&pdev->dev, "bus_clk");
1468 if (IS_ERR(dsi->bus_clk)) {
1469 dev_info(&pdev->dev, "failed to get dsi bus clock\n");
1470 ret = PTR_ERR(dsi->bus_clk);
1471 goto err_del_component;
1474 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1475 dsi->reg_base = devm_ioremap_resource(&pdev->dev, res);
1476 if (IS_ERR(dsi->reg_base)) {
1477 dev_err(&pdev->dev, "failed to remap io region\n");
1478 ret = PTR_ERR(dsi->reg_base);
1479 goto err_del_component;
1482 dsi->phy = devm_phy_get(&pdev->dev, "dsim");
1483 if (IS_ERR(dsi->phy)) {
1484 dev_info(&pdev->dev, "failed to get dsim phy\n");
1485 ret = PTR_ERR(dsi->phy);
1486 goto err_del_component;
1489 dsi->irq = platform_get_irq(pdev, 0);
1491 dev_err(&pdev->dev, "failed to request dsi irq resource\n");
1493 goto err_del_component;
1496 irq_set_status_flags(dsi->irq, IRQ_NOAUTOEN);
1497 ret = devm_request_threaded_irq(&pdev->dev, dsi->irq, NULL,
1498 exynos_dsi_irq, IRQF_ONESHOT,
1499 dev_name(&pdev->dev), dsi);
1501 dev_err(&pdev->dev, "failed to request dsi irq\n");
1502 goto err_del_component;
1505 exynos_dsi_display.ctx = dsi;
1507 platform_set_drvdata(pdev, &exynos_dsi_display);
1509 ret = component_add(&pdev->dev, &exynos_dsi_component_ops);
1511 goto err_del_component;
1516 exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CONNECTOR);
1520 static int exynos_dsi_remove(struct platform_device *pdev)
1522 component_del(&pdev->dev, &exynos_dsi_component_ops);
1523 exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CONNECTOR);
1528 static struct of_device_id exynos_dsi_of_match[] = {
1529 { .compatible = "samsung,exynos4210-mipi-dsi" },
1533 struct platform_driver dsi_driver = {
1534 .probe = exynos_dsi_probe,
1535 .remove = exynos_dsi_remove,
1537 .name = "exynos-dsi",
1538 .owner = THIS_MODULE,
1539 .of_match_table = exynos_dsi_of_match,
1543 MODULE_AUTHOR("Tomasz Figa <t.figa@samsung.com>");
1544 MODULE_AUTHOR("Andrzej Hajda <a.hajda@samsung.com>");
1545 MODULE_DESCRIPTION("Samsung SoC MIPI DSI Master");
1546 MODULE_LICENSE("GPL v2");