drivers/gpu/drm/exynos/exynos_drm_fimc.c

   1 /*
   2  * Copyright (C) 2012 Samsung Electronics Co.Ltd
   3  * Authors:
   4  *      Eunchul Kim <chulspro.kim@samsung.com>
   5  *      Jinyoung Jeon <jy0.jeon@samsung.com>
   6  *      Sangmin Lee <lsmin.lee@samsung.com>
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  *
  13  */
  14 #include <linux/kernel.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/mfd/syscon.h>
  17 #include <linux/regmap.h>
  18 #include <linux/clk.h>
  19 #include <linux/pm_runtime.h>
  20 #include <linux/of.h>
  21 #include <linux/spinlock.h>
  22
  23 #include <drm/drmP.h>
  24 #include <drm/exynos_drm.h>
  25 #include "regs-fimc.h"
  26 #include "exynos_drm_drv.h"
  27 #include "exynos_drm_ipp.h"
  28 #include "exynos_drm_fimc.h"
  29
  30 /*
  31  * FIMC stands for Fully Interactive Mobile Camera and
  32  * supports image scaler/rotator and input/output DMA operations.
  33  * input DMA reads image data from the memory.
  34  * output DMA writes image data to memory.
  35  * FIMC supports image rotation and image effect functions.
  36  *
  37  * M2M operation : supports crop/scale/rotation/csc so on.
  38  * Memory ----> FIMC H/W ----> Memory.
  39  * Writeback operation : supports cloned screen with FIMD.
  40  * FIMD ----> FIMC H/W ----> Memory.
  41  * Output operation : supports direct display using local path.
  42  * Memory ----> FIMC H/W ----> FIMD.
  43  */
  44
  45 /*
  46  * TODO
  47  * 1. check suspend/resume api if needed.
  48  * 2. need to check use case platform_device_id.
  49  * 3. check src/dst size with, height.
  50  * 4. added check_prepare api for right register.
  51  * 5. need to add supported list in prop_list.
  52  * 6. check prescaler/scaler optimization.
  53  */
  54
  55 #define FIMC_MAX_DEVS   4
  56 #define FIMC_MAX_SRC    2
  57 #define FIMC_MAX_DST    32
  58 #define FIMC_SHFACTOR   10
  59 #define FIMC_BUF_STOP   1
  60 #define FIMC_BUF_START  2
  61 #define FIMC_REG_SZ             32
  62 #define FIMC_WIDTH_ITU_709      1280
  63 #define FIMC_REFRESH_MAX        60
  64 #define FIMC_REFRESH_MIN        12
  65 #define FIMC_CROP_MAX   8192
  66 #define FIMC_CROP_MIN   32
  67 #define FIMC_SCALE_MAX  4224
  68 #define FIMC_SCALE_MIN  32
  69
  70 #define get_fimc_context(dev)   platform_get_drvdata(to_platform_device(dev))
  71 #define get_ctx_from_ippdrv(ippdrv)     container_of(ippdrv,\
  72                                         struct fimc_context, ippdrv);
  73 enum fimc_wb {
  74         FIMC_WB_NONE,
  75         FIMC_WB_A,
  76         FIMC_WB_B,
  77 };
  78
  79 enum {
  80         FIMC_CLK_LCLK,
  81         FIMC_CLK_GATE,
  82         FIMC_CLK_WB_A,
  83         FIMC_CLK_WB_B,
  84         FIMC_CLK_MUX,
  85         FIMC_CLK_PARENT,
  86         FIMC_CLKS_MAX
  87 };
  88
  89 static const char * const fimc_clock_names[] = {
  90         [FIMC_CLK_LCLK]   = "sclk_fimc",
  91         [FIMC_CLK_GATE]   = "fimc",
  92         [FIMC_CLK_WB_A]   = "pxl_async0",
  93         [FIMC_CLK_WB_B]   = "pxl_async1",
  94         [FIMC_CLK_MUX]    = "mux",
  95         [FIMC_CLK_PARENT] = "parent",
  96 };
  97
  98 #define FIMC_DEFAULT_LCLK_FREQUENCY 133000000UL
  99
 100 /*
 101  * A structure of scaler.
 102  *
 103  * @range: narrow, wide.
 104  * @bypass: unused scaler path.
 105  * @up_h: horizontal scale up.
 106  * @up_v: vertical scale up.
 107  * @hratio: horizontal ratio.
 108  * @vratio: vertical ratio.
 109  */
 110 struct fimc_scaler {
 111         bool    range;
 112         bool bypass;
 113         bool up_h;
 114         bool up_v;
 115         u32 hratio;
 116         u32 vratio;
 117 };
 118
 119 /*
 120  * A structure of scaler capability.
 121  *
 122  * find user manual table 43-1.
 123  * @in_hori: scaler input horizontal size.
 124  * @bypass: scaler bypass mode.
 125  * @dst_h_wo_rot: target horizontal size without output rotation.
 126  * @dst_h_rot: target horizontal size with output rotation.
 127  * @rl_w_wo_rot: real width without input rotation.
 128  * @rl_h_rot: real height without output rotation.
 129  */
 130 struct fimc_capability {
 131         /* scaler */
 132         u32     in_hori;
 133         u32     bypass;
 134         /* output rotator */
 135         u32     dst_h_wo_rot;
 136         u32     dst_h_rot;
 137         /* input rotator */
 138         u32     rl_w_wo_rot;
 139         u32     rl_h_rot;
 140 };
 141
 142 /*
 143  * A structure of fimc context.
 144  *
 145  * @ippdrv: prepare initialization using ippdrv.
 146  * @regs_res: register resources.
 147  * @regs: memory mapped io registers.
 148  * @lock: locking of operations.
 149  * @clocks: fimc clocks.
 150  * @clk_frequency: LCLK clock frequency.
 151  * @sysreg: handle to SYSREG block regmap.
 152  * @sc: scaler infomations.
 153  * @pol: porarity of writeback.
 154  * @id: fimc id.
 155  * @irq: irq number.
 156  * @suspended: qos operations.
 157  */
 158 struct fimc_context {
 159         struct exynos_drm_ippdrv        ippdrv;
 160         struct resource *regs_res;
 161         void __iomem    *regs;
 162         spinlock_t      lock;
 163         struct clk      *clocks[FIMC_CLKS_MAX];
 164         u32             clk_frequency;
 165         struct regmap   *sysreg;
 166         struct fimc_scaler      sc;
 167         struct exynos_drm_ipp_pol       pol;
 168         int     id;
 169         int     irq;
 170         bool    suspended;
 171 };
 172
 173 static u32 fimc_read(struct fimc_context *ctx, u32 reg)
 174 {
 175         return readl(ctx->regs + reg);
 176 }
 177
 178 static void fimc_write(struct fimc_context *ctx, u32 val, u32 reg)
 179 {
 180         writel(val, ctx->regs + reg);
 181 }
 182
 183 static void fimc_set_bits(struct fimc_context *ctx, u32 reg, u32 bits)
 184 {
 185         void __iomem *r = ctx->regs + reg;
 186
 187         writel(readl(r) | bits, r);
 188 }
 189
 190 static void fimc_clear_bits(struct fimc_context *ctx, u32 reg, u32 bits)
 191 {
 192         void __iomem *r = ctx->regs + reg;
 193
 194         writel(readl(r) & ~bits, r);
 195 }
 196
 197 static void fimc_sw_reset(struct fimc_context *ctx)
 198 {
 199         u32 cfg;
 200
 201         /* stop dma operation */
 202         cfg = fimc_read(ctx, EXYNOS_CISTATUS);
 203         if (EXYNOS_CISTATUS_GET_ENVID_STATUS(cfg))
 204                 fimc_clear_bits(ctx, EXYNOS_MSCTRL, EXYNOS_MSCTRL_ENVID);
 205
 206         fimc_set_bits(ctx, EXYNOS_CISRCFMT, EXYNOS_CISRCFMT_ITU601_8BIT);
 207
 208         /* disable image capture */
 209         fimc_clear_bits(ctx, EXYNOS_CIIMGCPT,
 210                 EXYNOS_CIIMGCPT_IMGCPTEN_SC | EXYNOS_CIIMGCPT_IMGCPTEN);
 211
 212         /* s/w reset */
 213         fimc_set_bits(ctx, EXYNOS_CIGCTRL, EXYNOS_CIGCTRL_SWRST);
 214
 215         /* s/w reset complete */
 216         fimc_clear_bits(ctx, EXYNOS_CIGCTRL, EXYNOS_CIGCTRL_SWRST);
 217
 218         /* reset sequence */
 219         fimc_write(ctx, 0x0, EXYNOS_CIFCNTSEQ);
 220 }
 221
 222 static int fimc_set_camblk_fimd0_wb(struct fimc_context *ctx)
 223 {
 224         return regmap_update_bits(ctx->sysreg, SYSREG_CAMERA_BLK,
 225                                   SYSREG_FIMD0WB_DEST_MASK,
 226                                   ctx->id << SYSREG_FIMD0WB_DEST_SHIFT);
 227 }
 228
 229 static void fimc_set_type_ctrl(struct fimc_context *ctx, enum fimc_wb wb)
 230 {
 231         u32 cfg;
 232
 233         DRM_DEBUG_KMS("wb[%d]\n", wb);
 234
 235         cfg = fimc_read(ctx, EXYNOS_CIGCTRL);
 236         cfg &= ~(EXYNOS_CIGCTRL_TESTPATTERN_MASK |
 237                 EXYNOS_CIGCTRL_SELCAM_ITU_MASK |
 238                 EXYNOS_CIGCTRL_SELCAM_MIPI_MASK |
 239                 EXYNOS_CIGCTRL_SELCAM_FIMC_MASK |
 240                 EXYNOS_CIGCTRL_SELWB_CAMIF_MASK |
 241                 EXYNOS_CIGCTRL_SELWRITEBACK_MASK);
 242
 243         switch (wb) {
 244         case FIMC_WB_A:
 245                 cfg |= (EXYNOS_CIGCTRL_SELWRITEBACK_A |
 246                         EXYNOS_CIGCTRL_SELWB_CAMIF_WRITEBACK);
 247                 break;
 248         case FIMC_WB_B:
 249                 cfg |= (EXYNOS_CIGCTRL_SELWRITEBACK_B |
 250                         EXYNOS_CIGCTRL_SELWB_CAMIF_WRITEBACK);
 251                 break;
 252         case FIMC_WB_NONE:
 253         default:
 254                 cfg |= (EXYNOS_CIGCTRL_SELCAM_ITU_A |
 255                         EXYNOS_CIGCTRL_SELWRITEBACK_A |
 256                         EXYNOS_CIGCTRL_SELCAM_MIPI_A |
 257                         EXYNOS_CIGCTRL_SELCAM_FIMC_ITU);
 258                 break;
 259         }
 260
 261         fimc_write(ctx, cfg, EXYNOS_CIGCTRL);
 262 }
 263
 264 static void fimc_set_polarity(struct fimc_context *ctx,
 265                 struct exynos_drm_ipp_pol *pol)
 266 {
 267         u32 cfg;
 268
 269         DRM_DEBUG_KMS("inv_pclk[%d]inv_vsync[%d]\n",
 270                 pol->inv_pclk, pol->inv_vsync);
 271         DRM_DEBUG_KMS("inv_href[%d]inv_hsync[%d]\n",
 272                 pol->inv_href, pol->inv_hsync);
 273
 274         cfg = fimc_read(ctx, EXYNOS_CIGCTRL);
 275         cfg &= ~(EXYNOS_CIGCTRL_INVPOLPCLK | EXYNOS_CIGCTRL_INVPOLVSYNC |
 276                  EXYNOS_CIGCTRL_INVPOLHREF | EXYNOS_CIGCTRL_INVPOLHSYNC);
 277
 278         if (pol->inv_pclk)
 279                 cfg |= EXYNOS_CIGCTRL_INVPOLPCLK;
 280         if (pol->inv_vsync)
 281                 cfg |= EXYNOS_CIGCTRL_INVPOLVSYNC;
 282         if (pol->inv_href)
 283                 cfg |= EXYNOS_CIGCTRL_INVPOLHREF;
 284         if (pol->inv_hsync)
 285                 cfg |= EXYNOS_CIGCTRL_INVPOLHSYNC;
 286
 287         fimc_write(ctx, cfg, EXYNOS_CIGCTRL);
 288 }
 289
 290 static void fimc_handle_jpeg(struct fimc_context *ctx, bool enable)
 291 {
 292         u32 cfg;
 293
 294         DRM_DEBUG_KMS("enable[%d]\n", enable);
 295
 296         cfg = fimc_read(ctx, EXYNOS_CIGCTRL);
 297         if (enable)
 298                 cfg |= EXYNOS_CIGCTRL_CAM_JPEG;
 299         else
 300                 cfg &= ~EXYNOS_CIGCTRL_CAM_JPEG;
 301
 302         fimc_write(ctx, cfg, EXYNOS_CIGCTRL);
 303 }
 304
 305 static void fimc_mask_irq(struct fimc_context *ctx, bool enable)
 306 {
 307         u32 cfg;
 308
 309         DRM_DEBUG_KMS("enable[%d]\n", enable);
 310
 311         cfg = fimc_read(ctx, EXYNOS_CIGCTRL);
 312         if (enable) {
 313                 cfg &= ~EXYNOS_CIGCTRL_IRQ_OVFEN;
 314                 cfg |= EXYNOS_CIGCTRL_IRQ_ENABLE | EXYNOS_CIGCTRL_IRQ_LEVEL;
 315         } else
 316                 cfg &= ~EXYNOS_CIGCTRL_IRQ_ENABLE;
 317         fimc_write(ctx, cfg, EXYNOS_CIGCTRL);
 318 }
 319
 320 static void fimc_clear_irq(struct fimc_context *ctx)
 321 {
 322         fimc_set_bits(ctx, EXYNOS_CIGCTRL, EXYNOS_CIGCTRL_IRQ_CLR);
 323 }
 324
 325 static bool fimc_check_ovf(struct fimc_context *ctx)
 326 {
 327         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
 328         u32 status, flag;
 329
 330         status = fimc_read(ctx, EXYNOS_CISTATUS);
 331         flag = EXYNOS_CISTATUS_OVFIY | EXYNOS_CISTATUS_OVFICB |
 332                 EXYNOS_CISTATUS_OVFICR;
 333
 334         DRM_DEBUG_KMS("flag[0x%x]\n", flag);
 335
 336         if (status & flag) {
 337                 fimc_set_bits(ctx, EXYNOS_CIWDOFST,
 338                         EXYNOS_CIWDOFST_CLROVFIY | EXYNOS_CIWDOFST_CLROVFICB |
 339                         EXYNOS_CIWDOFST_CLROVFICR);
 340                 fimc_clear_bits(ctx, EXYNOS_CIWDOFST,
 341                         EXYNOS_CIWDOFST_CLROVFIY | EXYNOS_CIWDOFST_CLROVFICB |
 342                         EXYNOS_CIWDOFST_CLROVFICR);
 343
 344                 dev_err(ippdrv->dev, "occurred overflow at %d, status 0x%x.\n",
 345                         ctx->id, status);
 346                 return true;
 347         }
 348
 349         return false;
 350 }
 351
 352 static bool fimc_check_frame_end(struct fimc_context *ctx)
 353 {
 354         u32 cfg;
 355
 356         cfg = fimc_read(ctx, EXYNOS_CISTATUS);
 357
 358         DRM_DEBUG_KMS("cfg[0x%x]\n", cfg);
 359
 360         if (!(cfg & EXYNOS_CISTATUS_FRAMEEND))
 361                 return false;
 362
 363         cfg &= ~(EXYNOS_CISTATUS_FRAMEEND);
 364         fimc_write(ctx, cfg, EXYNOS_CISTATUS);
 365
 366         return true;
 367 }
 368
 369 static int fimc_get_buf_id(struct fimc_context *ctx)
 370 {
 371         u32 cfg;
 372         int frame_cnt, buf_id;
 373
 374         cfg = fimc_read(ctx, EXYNOS_CISTATUS2);
 375         frame_cnt = EXYNOS_CISTATUS2_GET_FRAMECOUNT_BEFORE(cfg);
 376
 377         if (frame_cnt == 0)
 378                 frame_cnt = EXYNOS_CISTATUS2_GET_FRAMECOUNT_PRESENT(cfg);
 379
 380         DRM_DEBUG_KMS("present[%d]before[%d]\n",
 381                 EXYNOS_CISTATUS2_GET_FRAMECOUNT_PRESENT(cfg),
 382                 EXYNOS_CISTATUS2_GET_FRAMECOUNT_BEFORE(cfg));
 383
 384         if (frame_cnt == 0) {
 385                 DRM_ERROR("failed to get frame count.\n");
 386                 return -EIO;
 387         }
 388
 389         buf_id = frame_cnt - 1;
 390         DRM_DEBUG_KMS("buf_id[%d]\n", buf_id);
 391
 392         return buf_id;
 393 }
 394
 395 static void fimc_handle_lastend(struct fimc_context *ctx, bool enable)
 396 {
 397         u32 cfg;
 398
 399         DRM_DEBUG_KMS("enable[%d]\n", enable);
 400
 401         cfg = fimc_read(ctx, EXYNOS_CIOCTRL);
 402         if (enable)
 403                 cfg |= EXYNOS_CIOCTRL_LASTENDEN;
 404         else
 405                 cfg &= ~EXYNOS_CIOCTRL_LASTENDEN;
 406
 407         fimc_write(ctx, cfg, EXYNOS_CIOCTRL);
 408 }
 409
 410
 411 static int fimc_src_set_fmt_order(struct fimc_context *ctx, u32 fmt)
 412 {
 413         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
 414         u32 cfg;
 415
 416         DRM_DEBUG_KMS("fmt[0x%x]\n", fmt);
 417
 418         /* RGB */
 419         cfg = fimc_read(ctx, EXYNOS_CISCCTRL);
 420         cfg &= ~EXYNOS_CISCCTRL_INRGB_FMT_RGB_MASK;
 421
 422         switch (fmt) {
 423         case DRM_FORMAT_RGB565:
 424                 cfg |= EXYNOS_CISCCTRL_INRGB_FMT_RGB565;
 425                 fimc_write(ctx, cfg, EXYNOS_CISCCTRL);
 426                 return 0;
 427         case DRM_FORMAT_RGB888:
 428         case DRM_FORMAT_XRGB8888:
 429                 cfg |= EXYNOS_CISCCTRL_INRGB_FMT_RGB888;
 430                 fimc_write(ctx, cfg, EXYNOS_CISCCTRL);
 431                 return 0;
 432         default:
 433                 /* bypass */
 434                 break;
 435         }
 436
 437         /* YUV */
 438         cfg = fimc_read(ctx, EXYNOS_MSCTRL);
 439         cfg &= ~(EXYNOS_MSCTRL_ORDER2P_SHIFT_MASK |
 440                 EXYNOS_MSCTRL_C_INT_IN_2PLANE |
 441                 EXYNOS_MSCTRL_ORDER422_YCBYCR);
 442
 443         switch (fmt) {
 444         case DRM_FORMAT_YUYV:
 445                 cfg |= EXYNOS_MSCTRL_ORDER422_YCBYCR;
 446                 break;
 447         case DRM_FORMAT_YVYU:
 448                 cfg |= EXYNOS_MSCTRL_ORDER422_YCRYCB;
 449                 break;
 450         case DRM_FORMAT_UYVY:
 451                 cfg |= EXYNOS_MSCTRL_ORDER422_CBYCRY;
 452                 break;
 453         case DRM_FORMAT_VYUY:
 454         case DRM_FORMAT_YUV444:
 455                 cfg |= EXYNOS_MSCTRL_ORDER422_CRYCBY;
 456                 break;
 457         case DRM_FORMAT_NV21:
 458         case DRM_FORMAT_NV61:
 459                 cfg |= (EXYNOS_MSCTRL_ORDER2P_LSB_CRCB |
 460                         EXYNOS_MSCTRL_C_INT_IN_2PLANE);
 461                 break;
 462         case DRM_FORMAT_YUV422:
 463         case DRM_FORMAT_YUV420:
 464         case DRM_FORMAT_YVU420:
 465                 cfg |= EXYNOS_MSCTRL_C_INT_IN_3PLANE;
 466                 break;
 467         case DRM_FORMAT_NV12:
 468         case DRM_FORMAT_NV12MT:
 469         case DRM_FORMAT_NV16:
 470                 cfg |= (EXYNOS_MSCTRL_ORDER2P_LSB_CBCR |
 471                         EXYNOS_MSCTRL_C_INT_IN_2PLANE);
 472                 break;
 473         default:
 474                 dev_err(ippdrv->dev, "inavlid source yuv order 0x%x.\n", fmt);
 475                 return -EINVAL;
 476         }
 477
 478         fimc_write(ctx, cfg, EXYNOS_MSCTRL);
 479
 480         return 0;
 481 }
 482
 483 static int fimc_src_set_fmt(struct device *dev, u32 fmt)
 484 {
 485         struct fimc_context *ctx = get_fimc_context(dev);
 486         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
 487         u32 cfg;
 488
 489         DRM_DEBUG_KMS("fmt[0x%x]\n", fmt);
 490
 491         cfg = fimc_read(ctx, EXYNOS_MSCTRL);
 492         cfg &= ~EXYNOS_MSCTRL_INFORMAT_RGB;
 493
 494         switch (fmt) {
 495         case DRM_FORMAT_RGB565:
 496         case DRM_FORMAT_RGB888:
 497         case DRM_FORMAT_XRGB8888:
 498                 cfg |= EXYNOS_MSCTRL_INFORMAT_RGB;
 499                 break;
 500         case DRM_FORMAT_YUV444:
 501                 cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR420;
 502                 break;
 503         case DRM_FORMAT_YUYV:
 504         case DRM_FORMAT_YVYU:
 505         case DRM_FORMAT_UYVY:
 506         case DRM_FORMAT_VYUY:
 507                 cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR422_1PLANE;
 508                 break;
 509         case DRM_FORMAT_NV16:
 510         case DRM_FORMAT_NV61:
 511         case DRM_FORMAT_YUV422:
 512                 cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR422;
 513                 break;
 514         case DRM_FORMAT_YUV420:
 515         case DRM_FORMAT_YVU420:
 516         case DRM_FORMAT_NV12:
 517         case DRM_FORMAT_NV21:
 518         case DRM_FORMAT_NV12MT:
 519                 cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR420;
 520                 break;
 521         default:
 522                 dev_err(ippdrv->dev, "inavlid source format 0x%x.\n", fmt);
 523                 return -EINVAL;
 524         }
 525
 526         fimc_write(ctx, cfg, EXYNOS_MSCTRL);
 527
 528         cfg = fimc_read(ctx, EXYNOS_CIDMAPARAM);
 529         cfg &= ~EXYNOS_CIDMAPARAM_R_MODE_MASK;
 530
 531         if (fmt == DRM_FORMAT_NV12MT)
 532                 cfg |= EXYNOS_CIDMAPARAM_R_MODE_64X32;
 533         else
 534                 cfg |= EXYNOS_CIDMAPARAM_R_MODE_LINEAR;
 535
 536         fimc_write(ctx, cfg, EXYNOS_CIDMAPARAM);
 537
 538         return fimc_src_set_fmt_order(ctx, fmt);
 539 }
 540
 541 static int fimc_src_set_transf(struct device *dev,
 542                 enum drm_exynos_degree degree,
 543                 enum drm_exynos_flip flip, bool *swap)
 544 {
 545         struct fimc_context *ctx = get_fimc_context(dev);
 546         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
 547         u32 cfg1, cfg2;
 548
 549         DRM_DEBUG_KMS("degree[%d]flip[0x%x]\n", degree, flip);
 550
 551         cfg1 = fimc_read(ctx, EXYNOS_MSCTRL);
 552         cfg1 &= ~(EXYNOS_MSCTRL_FLIP_X_MIRROR |
 553                 EXYNOS_MSCTRL_FLIP_Y_MIRROR);
 554
 555         cfg2 = fimc_read(ctx, EXYNOS_CITRGFMT);
 556         cfg2 &= ~EXYNOS_CITRGFMT_INROT90_CLOCKWISE;
 557
 558         switch (degree) {
 559         case EXYNOS_DRM_DEGREE_0:
 560                 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
 561                         cfg1 |= EXYNOS_MSCTRL_FLIP_X_MIRROR;
 562                 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
 563                         cfg1 |= EXYNOS_MSCTRL_FLIP_Y_MIRROR;
 564                 break;
 565         case EXYNOS_DRM_DEGREE_90:
 566                 cfg2 |= EXYNOS_CITRGFMT_INROT90_CLOCKWISE;
 567                 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
 568                         cfg1 |= EXYNOS_MSCTRL_FLIP_X_MIRROR;
 569                 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
 570                         cfg1 |= EXYNOS_MSCTRL_FLIP_Y_MIRROR;
 571                 break;
 572         case EXYNOS_DRM_DEGREE_180:
 573                 cfg1 |= (EXYNOS_MSCTRL_FLIP_X_MIRROR |
 574                         EXYNOS_MSCTRL_FLIP_Y_MIRROR);
 575                 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
 576                         cfg1 &= ~EXYNOS_MSCTRL_FLIP_X_MIRROR;
 577                 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
 578                         cfg1 &= ~EXYNOS_MSCTRL_FLIP_Y_MIRROR;
 579                 break;
 580         case EXYNOS_DRM_DEGREE_270:
 581                 cfg1 |= (EXYNOS_MSCTRL_FLIP_X_MIRROR |
 582                         EXYNOS_MSCTRL_FLIP_Y_MIRROR);
 583                 cfg2 |= EXYNOS_CITRGFMT_INROT90_CLOCKWISE;
 584                 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
 585                         cfg1 &= ~EXYNOS_MSCTRL_FLIP_X_MIRROR;
 586                 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
 587                         cfg1 &= ~EXYNOS_MSCTRL_FLIP_Y_MIRROR;
 588                 break;
 589         default:
 590                 dev_err(ippdrv->dev, "inavlid degree value %d.\n", degree);
 591                 return -EINVAL;
 592         }
 593
 594         fimc_write(ctx, cfg1, EXYNOS_MSCTRL);
 595         fimc_write(ctx, cfg2, EXYNOS_CITRGFMT);
 596         *swap = (cfg2 & EXYNOS_CITRGFMT_INROT90_CLOCKWISE) ? 1 : 0;
 597
 598         return 0;
 599 }
 600
 601 static int fimc_set_window(struct fimc_context *ctx,
 602                 struct drm_exynos_pos *pos, struct drm_exynos_sz *sz)
 603 {
 604         u32 cfg, h1, h2, v1, v2;
 605
 606         /* cropped image */
 607         h1 = pos->x;
 608         h2 = sz->hsize - pos->w - pos->x;
 609         v1 = pos->y;
 610         v2 = sz->vsize - pos->h - pos->y;
 611
 612         DRM_DEBUG_KMS("x[%d]y[%d]w[%d]h[%d]hsize[%d]vsize[%d]\n",
 613                 pos->x, pos->y, pos->w, pos->h, sz->hsize, sz->vsize);
 614         DRM_DEBUG_KMS("h1[%d]h2[%d]v1[%d]v2[%d]\n", h1, h2, v1, v2);
 615
 616         /*
 617          * set window offset 1, 2 size
 618          * check figure 43-21 in user manual
 619          */
 620         cfg = fimc_read(ctx, EXYNOS_CIWDOFST);
 621         cfg &= ~(EXYNOS_CIWDOFST_WINHOROFST_MASK |
 622                 EXYNOS_CIWDOFST_WINVEROFST_MASK);
 623         cfg |= (EXYNOS_CIWDOFST_WINHOROFST(h1) |
 624                 EXYNOS_CIWDOFST_WINVEROFST(v1));
 625         cfg |= EXYNOS_CIWDOFST_WINOFSEN;
 626         fimc_write(ctx, cfg, EXYNOS_CIWDOFST);
 627
 628         cfg = (EXYNOS_CIWDOFST2_WINHOROFST2(h2) |
 629                 EXYNOS_CIWDOFST2_WINVEROFST2(v2));
 630         fimc_write(ctx, cfg, EXYNOS_CIWDOFST2);
 631
 632         return 0;
 633 }
 634
 635 static int fimc_src_set_size(struct device *dev, int swap,
 636                 struct drm_exynos_pos *pos, struct drm_exynos_sz *sz)
 637 {
 638         struct fimc_context *ctx = get_fimc_context(dev);
 639         struct drm_exynos_pos img_pos = *pos;
 640         struct drm_exynos_sz img_sz = *sz;
 641         u32 cfg;
 642
 643         DRM_DEBUG_KMS("swap[%d]hsize[%d]vsize[%d]\n",
 644                 swap, sz->hsize, sz->vsize);
 645
 646         /* original size */
 647         cfg = (EXYNOS_ORGISIZE_HORIZONTAL(img_sz.hsize) |
 648                 EXYNOS_ORGISIZE_VERTICAL(img_sz.vsize));
 649
 650         fimc_write(ctx, cfg, EXYNOS_ORGISIZE);
 651
 652         DRM_DEBUG_KMS("x[%d]y[%d]w[%d]h[%d]\n", pos->x, pos->y, pos->w, pos->h);
 653
 654         if (swap) {
 655                 img_pos.w = pos->h;
 656                 img_pos.h = pos->w;
 657                 img_sz.hsize = sz->vsize;
 658                 img_sz.vsize = sz->hsize;
 659         }
 660
 661         /* set input DMA image size */
 662         cfg = fimc_read(ctx, EXYNOS_CIREAL_ISIZE);
 663         cfg &= ~(EXYNOS_CIREAL_ISIZE_HEIGHT_MASK |
 664                 EXYNOS_CIREAL_ISIZE_WIDTH_MASK);
 665         cfg |= (EXYNOS_CIREAL_ISIZE_WIDTH(img_pos.w) |
 666                 EXYNOS_CIREAL_ISIZE_HEIGHT(img_pos.h));
 667         fimc_write(ctx, cfg, EXYNOS_CIREAL_ISIZE);
 668
 669         /*
 670          * set input FIFO image size
 671          * for now, we support only ITU601 8 bit mode
 672          */
 673         cfg = (EXYNOS_CISRCFMT_ITU601_8BIT |
 674                 EXYNOS_CISRCFMT_SOURCEHSIZE(img_sz.hsize) |
 675                 EXYNOS_CISRCFMT_SOURCEVSIZE(img_sz.vsize));
 676         fimc_write(ctx, cfg, EXYNOS_CISRCFMT);
 677
 678         /* offset Y(RGB), Cb, Cr */
 679         cfg = (EXYNOS_CIIYOFF_HORIZONTAL(img_pos.x) |
 680                 EXYNOS_CIIYOFF_VERTICAL(img_pos.y));
 681         fimc_write(ctx, cfg, EXYNOS_CIIYOFF);
 682         cfg = (EXYNOS_CIICBOFF_HORIZONTAL(img_pos.x) |
 683                 EXYNOS_CIICBOFF_VERTICAL(img_pos.y));
 684         fimc_write(ctx, cfg, EXYNOS_CIICBOFF);
 685         cfg = (EXYNOS_CIICROFF_HORIZONTAL(img_pos.x) |
 686                 EXYNOS_CIICROFF_VERTICAL(img_pos.y));
 687         fimc_write(ctx, cfg, EXYNOS_CIICROFF);
 688
 689         return fimc_set_window(ctx, &img_pos, &img_sz);
 690 }
 691
 692 static int fimc_src_set_addr(struct device *dev,
 693                 struct drm_exynos_ipp_buf_info *buf_info, u32 buf_id,
 694                 enum drm_exynos_ipp_buf_type buf_type)
 695 {
 696         struct fimc_context *ctx = get_fimc_context(dev);
 697         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
 698         struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
 699         struct drm_exynos_ipp_property *property;
 700         struct drm_exynos_ipp_config *config;
 701
 702         if (!c_node) {
 703                 DRM_ERROR("failed to get c_node.\n");
 704                 return -EINVAL;
 705         }
 706
 707         property = &c_node->property;
 708
 709         DRM_DEBUG_KMS("prop_id[%d]buf_id[%d]buf_type[%d]\n",
 710                 property->prop_id, buf_id, buf_type);
 711
 712         if (buf_id > FIMC_MAX_SRC) {
 713                 dev_info(ippdrv->dev, "inavlid buf_id %d.\n", buf_id);
 714                 return -ENOMEM;
 715         }
 716
 717         /* address register set */
 718         switch (buf_type) {
 719         case IPP_BUF_ENQUEUE:
 720                 config = &property->config[EXYNOS_DRM_OPS_SRC];
 721                 fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_Y],
 722                         EXYNOS_CIIYSA(buf_id));
 723
 724                 if (config->fmt == DRM_FORMAT_YVU420) {
 725                         fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CR],
 726                                 EXYNOS_CIICBSA(buf_id));
 727                         fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CB],
 728                                 EXYNOS_CIICRSA(buf_id));
 729                 } else {
 730                         fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CB],
 731                                 EXYNOS_CIICBSA(buf_id));
 732                         fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CR],
 733                                 EXYNOS_CIICRSA(buf_id));
 734                 }
 735                 break;
 736         case IPP_BUF_DEQUEUE:
 737                 fimc_write(ctx, 0x0, EXYNOS_CIIYSA(buf_id));
 738                 fimc_write(ctx, 0x0, EXYNOS_CIICBSA(buf_id));
 739                 fimc_write(ctx, 0x0, EXYNOS_CIICRSA(buf_id));
 740                 break;
 741         default:
 742                 /* bypass */
 743                 break;
 744         }
 745
 746         return 0;
 747 }
 748
 749 static struct exynos_drm_ipp_ops fimc_src_ops = {
 750         .set_fmt = fimc_src_set_fmt,
 751         .set_transf = fimc_src_set_transf,
 752         .set_size = fimc_src_set_size,
 753         .set_addr = fimc_src_set_addr,
 754 };
 755
 756 static int fimc_dst_set_fmt_order(struct fimc_context *ctx, u32 fmt)
 757 {
 758         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
 759         u32 cfg;
 760
 761         DRM_DEBUG_KMS("fmt[0x%x]\n", fmt);
 762
 763         /* RGB */
 764         cfg = fimc_read(ctx, EXYNOS_CISCCTRL);
 765         cfg &= ~EXYNOS_CISCCTRL_OUTRGB_FMT_RGB_MASK;
 766
 767         switch (fmt) {
 768         case DRM_FORMAT_RGB565:
 769                 cfg |= EXYNOS_CISCCTRL_OUTRGB_FMT_RGB565;
 770                 fimc_write(ctx, cfg, EXYNOS_CISCCTRL);
 771                 return 0;
 772         case DRM_FORMAT_RGB888:
 773                 cfg |= EXYNOS_CISCCTRL_OUTRGB_FMT_RGB888;
 774                 fimc_write(ctx, cfg, EXYNOS_CISCCTRL);
 775                 return 0;
 776         case DRM_FORMAT_XRGB8888:
 777                 cfg |= (EXYNOS_CISCCTRL_OUTRGB_FMT_RGB888 |
 778                         EXYNOS_CISCCTRL_EXTRGB_EXTENSION);
 779                 fimc_write(ctx, cfg, EXYNOS_CISCCTRL);
 780                 break;
 781         default:
 782                 /* bypass */
 783                 break;
 784         }
 785
 786         /* YUV */
 787         cfg = fimc_read(ctx, EXYNOS_CIOCTRL);
 788         cfg &= ~(EXYNOS_CIOCTRL_ORDER2P_MASK |
 789                 EXYNOS_CIOCTRL_ORDER422_MASK |
 790                 EXYNOS_CIOCTRL_YCBCR_PLANE_MASK);
 791
 792         switch (fmt) {
 793         case DRM_FORMAT_XRGB8888:
 794                 cfg |= EXYNOS_CIOCTRL_ALPHA_OUT;
 795                 break;
 796         case DRM_FORMAT_YUYV:
 797                 cfg |= EXYNOS_CIOCTRL_ORDER422_YCBYCR;
 798                 break;
 799         case DRM_FORMAT_YVYU:
 800                 cfg |= EXYNOS_CIOCTRL_ORDER422_YCRYCB;
 801                 break;
 802         case DRM_FORMAT_UYVY:
 803                 cfg |= EXYNOS_CIOCTRL_ORDER422_CBYCRY;
 804                 break;
 805         case DRM_FORMAT_VYUY:
 806                 cfg |= EXYNOS_CIOCTRL_ORDER422_CRYCBY;
 807                 break;
 808         case DRM_FORMAT_NV21:
 809         case DRM_FORMAT_NV61:
 810                 cfg |= EXYNOS_CIOCTRL_ORDER2P_LSB_CRCB;
 811                 cfg |= EXYNOS_CIOCTRL_YCBCR_2PLANE;
 812                 break;
 813         case DRM_FORMAT_YUV422:
 814         case DRM_FORMAT_YUV420:
 815         case DRM_FORMAT_YVU420:
 816                 cfg |= EXYNOS_CIOCTRL_YCBCR_3PLANE;
 817                 break;
 818         case DRM_FORMAT_NV12:
 819         case DRM_FORMAT_NV12MT:
 820         case DRM_FORMAT_NV16:
 821                 cfg |= EXYNOS_CIOCTRL_ORDER2P_LSB_CBCR;
 822                 cfg |= EXYNOS_CIOCTRL_YCBCR_2PLANE;
 823                 break;
 824         default:
 825                 dev_err(ippdrv->dev, "inavlid target yuv order 0x%x.\n", fmt);
 826                 return -EINVAL;
 827         }
 828
 829         fimc_write(ctx, cfg, EXYNOS_CIOCTRL);
 830
 831         return 0;
 832 }
 833
 834 static int fimc_dst_set_fmt(struct device *dev, u32 fmt)
 835 {
 836         struct fimc_context *ctx = get_fimc_context(dev);
 837         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
 838         u32 cfg;
 839
 840         DRM_DEBUG_KMS("fmt[0x%x]\n", fmt);
 841
 842         cfg = fimc_read(ctx, EXYNOS_CIEXTEN);
 843
 844         if (fmt == DRM_FORMAT_AYUV) {
 845                 cfg |= EXYNOS_CIEXTEN_YUV444_OUT;
 846                 fimc_write(ctx, cfg, EXYNOS_CIEXTEN);
 847         } else {
 848                 cfg &= ~EXYNOS_CIEXTEN_YUV444_OUT;
 849                 fimc_write(ctx, cfg, EXYNOS_CIEXTEN);
 850
 851                 cfg = fimc_read(ctx, EXYNOS_CITRGFMT);
 852                 cfg &= ~EXYNOS_CITRGFMT_OUTFORMAT_MASK;
 853
 854                 switch (fmt) {
 855                 case DRM_FORMAT_RGB565:
 856                 case DRM_FORMAT_RGB888:
 857                 case DRM_FORMAT_XRGB8888:
 858                         cfg |= EXYNOS_CITRGFMT_OUTFORMAT_RGB;
 859                         break;
 860                 case DRM_FORMAT_YUYV:
 861                 case DRM_FORMAT_YVYU:
 862                 case DRM_FORMAT_UYVY:
 863                 case DRM_FORMAT_VYUY:
 864                         cfg |= EXYNOS_CITRGFMT_OUTFORMAT_YCBCR422_1PLANE;
 865                         break;
 866                 case DRM_FORMAT_NV16:
 867                 case DRM_FORMAT_NV61:
 868                 case DRM_FORMAT_YUV422:
 869                         cfg |= EXYNOS_CITRGFMT_OUTFORMAT_YCBCR422;
 870                         break;
 871                 case DRM_FORMAT_YUV420:
 872                 case DRM_FORMAT_YVU420:
 873                 case DRM_FORMAT_NV12:
 874                 case DRM_FORMAT_NV12MT:
 875                 case DRM_FORMAT_NV21:
 876                         cfg |= EXYNOS_CITRGFMT_OUTFORMAT_YCBCR420;
 877                         break;
 878                 default:
 879                         dev_err(ippdrv->dev, "inavlid target format 0x%x.\n",
 880                                 fmt);
 881                         return -EINVAL;
 882                 }
 883
 884                 fimc_write(ctx, cfg, EXYNOS_CITRGFMT);
 885         }
 886
 887         cfg = fimc_read(ctx, EXYNOS_CIDMAPARAM);
 888         cfg &= ~EXYNOS_CIDMAPARAM_W_MODE_MASK;
 889
 890         if (fmt == DRM_FORMAT_NV12MT)
 891                 cfg |= EXYNOS_CIDMAPARAM_W_MODE_64X32;
 892         else
 893                 cfg |= EXYNOS_CIDMAPARAM_W_MODE_LINEAR;
 894
 895         fimc_write(ctx, cfg, EXYNOS_CIDMAPARAM);
 896
 897         return fimc_dst_set_fmt_order(ctx, fmt);
 898 }
 899
 900 static int fimc_dst_set_transf(struct device *dev,
 901                 enum drm_exynos_degree degree,
 902                 enum drm_exynos_flip flip, bool *swap)
 903 {
 904         struct fimc_context *ctx = get_fimc_context(dev);
 905         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
 906         u32 cfg;
 907
 908         DRM_DEBUG_KMS("degree[%d]flip[0x%x]\n", degree, flip);
 909
 910         cfg = fimc_read(ctx, EXYNOS_CITRGFMT);
 911         cfg &= ~EXYNOS_CITRGFMT_FLIP_MASK;
 912         cfg &= ~EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE;
 913
 914         switch (degree) {
 915         case EXYNOS_DRM_DEGREE_0:
 916                 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
 917                         cfg |= EXYNOS_CITRGFMT_FLIP_X_MIRROR;
 918                 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
 919                         cfg |= EXYNOS_CITRGFMT_FLIP_Y_MIRROR;
 920                 break;
 921         case EXYNOS_DRM_DEGREE_90:
 922                 cfg |= EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE;
 923                 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
 924                         cfg |= EXYNOS_CITRGFMT_FLIP_X_MIRROR;
 925                 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
 926                         cfg |= EXYNOS_CITRGFMT_FLIP_Y_MIRROR;
 927                 break;
 928         case EXYNOS_DRM_DEGREE_180:
 929                 cfg |= (EXYNOS_CITRGFMT_FLIP_X_MIRROR |
 930                         EXYNOS_CITRGFMT_FLIP_Y_MIRROR);
 931                 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
 932                         cfg &= ~EXYNOS_CITRGFMT_FLIP_X_MIRROR;
 933                 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
 934                         cfg &= ~EXYNOS_CITRGFMT_FLIP_Y_MIRROR;
 935                 break;
 936         case EXYNOS_DRM_DEGREE_270:
 937                 cfg |= (EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE |
 938                         EXYNOS_CITRGFMT_FLIP_X_MIRROR |
 939                         EXYNOS_CITRGFMT_FLIP_Y_MIRROR);
 940                 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
 941                         cfg &= ~EXYNOS_CITRGFMT_FLIP_X_MIRROR;
 942                 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
 943                         cfg &= ~EXYNOS_CITRGFMT_FLIP_Y_MIRROR;
 944                 break;
 945         default:
 946                 dev_err(ippdrv->dev, "inavlid degree value %d.\n", degree);
 947                 return -EINVAL;
 948         }
 949
 950         fimc_write(ctx, cfg, EXYNOS_CITRGFMT);
 951         *swap = (cfg & EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE) ? 1 : 0;
 952
 953         return 0;
 954 }
 955
 956 static int fimc_set_prescaler(struct fimc_context *ctx, struct fimc_scaler *sc,
 957                 struct drm_exynos_pos *src, struct drm_exynos_pos *dst)
 958 {
 959         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
 960         u32 cfg, cfg_ext, shfactor;
 961         u32 pre_dst_width, pre_dst_height;
 962         u32 hfactor, vfactor;
 963         int ret = 0;
 964         u32 src_w, src_h, dst_w, dst_h;
 965
 966         cfg_ext = fimc_read(ctx, EXYNOS_CITRGFMT);
 967         if (cfg_ext & EXYNOS_CITRGFMT_INROT90_CLOCKWISE) {
 968                 src_w = src->h;
 969                 src_h = src->w;
 970         } else {
 971                 src_w = src->w;
 972                 src_h = src->h;
 973         }
 974
 975         if (cfg_ext & EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE) {
 976                 dst_w = dst->h;
 977                 dst_h = dst->w;
 978         } else {
 979                 dst_w = dst->w;
 980                 dst_h = dst->h;
 981         }
 982
 983         /* fimc_ippdrv_check_property assures that dividers are not null */
 984         hfactor = fls(src_w / dst_w / 2);
 985         if (hfactor > FIMC_SHFACTOR / 2) {
 986                 dev_err(ippdrv->dev, "failed to get ratio horizontal.\n");
 987                 return -EINVAL;
 988         }
 989
 990         vfactor = fls(src_h / dst_h / 2);
 991         if (vfactor > FIMC_SHFACTOR / 2) {
 992                 dev_err(ippdrv->dev, "failed to get ratio vertical.\n");
 993                 return -EINVAL;
 994         }
 995
 996         pre_dst_width = src_w >> hfactor;
 997         pre_dst_height = src_h >> vfactor;
 998         DRM_DEBUG_KMS("pre_dst_width[%d]pre_dst_height[%d]\n",
 999                 pre_dst_width, pre_dst_height);
1000         DRM_DEBUG_KMS("hfactor[%d]vfactor[%d]\n", hfactor, vfactor);
1001
1002         sc->hratio = (src_w << 14) / (dst_w << hfactor);
1003         sc->vratio = (src_h << 14) / (dst_h << vfactor);
1004         sc->up_h = (dst_w >= src_w) ? true : false;
1005         sc->up_v = (dst_h >= src_h) ? true : false;
1006         DRM_DEBUG_KMS("hratio[%d]vratio[%d]up_h[%d]up_v[%d]\n",
1007                 sc->hratio, sc->vratio, sc->up_h, sc->up_v);
1008
1009         shfactor = FIMC_SHFACTOR - (hfactor + vfactor);
1010         DRM_DEBUG_KMS("shfactor[%d]\n", shfactor);
1011
1012         cfg = (EXYNOS_CISCPRERATIO_SHFACTOR(shfactor) |
1013                 EXYNOS_CISCPRERATIO_PREHORRATIO(1 << hfactor) |
1014                 EXYNOS_CISCPRERATIO_PREVERRATIO(1 << vfactor));
1015         fimc_write(ctx, cfg, EXYNOS_CISCPRERATIO);
1016
1017         cfg = (EXYNOS_CISCPREDST_PREDSTWIDTH(pre_dst_width) |
1018                 EXYNOS_CISCPREDST_PREDSTHEIGHT(pre_dst_height));
1019         fimc_write(ctx, cfg, EXYNOS_CISCPREDST);
1020
1021         return ret;
1022 }
1023
1024 static void fimc_set_scaler(struct fimc_context *ctx, struct fimc_scaler *sc)
1025 {
1026         u32 cfg, cfg_ext;
1027
1028         DRM_DEBUG_KMS("range[%d]bypass[%d]up_h[%d]up_v[%d]\n",
1029                 sc->range, sc->bypass, sc->up_h, sc->up_v);
1030         DRM_DEBUG_KMS("hratio[%d]vratio[%d]\n",
1031                 sc->hratio, sc->vratio);
1032
1033         cfg = fimc_read(ctx, EXYNOS_CISCCTRL);
1034         cfg &= ~(EXYNOS_CISCCTRL_SCALERBYPASS |
1035                 EXYNOS_CISCCTRL_SCALEUP_H | EXYNOS_CISCCTRL_SCALEUP_V |
1036                 EXYNOS_CISCCTRL_MAIN_V_RATIO_MASK |
1037                 EXYNOS_CISCCTRL_MAIN_H_RATIO_MASK |
1038                 EXYNOS_CISCCTRL_CSCR2Y_WIDE |
1039                 EXYNOS_CISCCTRL_CSCY2R_WIDE);
1040
1041         if (sc->range)
1042                 cfg |= (EXYNOS_CISCCTRL_CSCR2Y_WIDE |
1043                         EXYNOS_CISCCTRL_CSCY2R_WIDE);
1044         if (sc->bypass)
1045                 cfg |= EXYNOS_CISCCTRL_SCALERBYPASS;
1046         if (sc->up_h)
1047                 cfg |= EXYNOS_CISCCTRL_SCALEUP_H;
1048         if (sc->up_v)
1049                 cfg |= EXYNOS_CISCCTRL_SCALEUP_V;
1050
1051         cfg |= (EXYNOS_CISCCTRL_MAINHORRATIO((sc->hratio >> 6)) |
1052                 EXYNOS_CISCCTRL_MAINVERRATIO((sc->vratio >> 6)));
1053         fimc_write(ctx, cfg, EXYNOS_CISCCTRL);
1054
1055         cfg_ext = fimc_read(ctx, EXYNOS_CIEXTEN);
1056         cfg_ext &= ~EXYNOS_CIEXTEN_MAINHORRATIO_EXT_MASK;
1057         cfg_ext &= ~EXYNOS_CIEXTEN_MAINVERRATIO_EXT_MASK;
1058         cfg_ext |= (EXYNOS_CIEXTEN_MAINHORRATIO_EXT(sc->hratio) |
1059                 EXYNOS_CIEXTEN_MAINVERRATIO_EXT(sc->vratio));
1060         fimc_write(ctx, cfg_ext, EXYNOS_CIEXTEN);
1061 }
1062
1063 static int fimc_dst_set_size(struct device *dev, int swap,
1064                 struct drm_exynos_pos *pos, struct drm_exynos_sz *sz)
1065 {
1066         struct fimc_context *ctx = get_fimc_context(dev);
1067         struct drm_exynos_pos img_pos = *pos;
1068         struct drm_exynos_sz img_sz = *sz;
1069         u32 cfg;
1070
1071         DRM_DEBUG_KMS("swap[%d]hsize[%d]vsize[%d]\n",
1072                 swap, sz->hsize, sz->vsize);
1073
1074         /* original size */
1075         cfg = (EXYNOS_ORGOSIZE_HORIZONTAL(img_sz.hsize) |
1076                 EXYNOS_ORGOSIZE_VERTICAL(img_sz.vsize));
1077
1078         fimc_write(ctx, cfg, EXYNOS_ORGOSIZE);
1079
1080         DRM_DEBUG_KMS("x[%d]y[%d]w[%d]h[%d]\n", pos->x, pos->y, pos->w, pos->h);
1081
1082         /* CSC ITU */
1083         cfg = fimc_read(ctx, EXYNOS_CIGCTRL);
1084         cfg &= ~EXYNOS_CIGCTRL_CSC_MASK;
1085
1086         if (sz->hsize >= FIMC_WIDTH_ITU_709)
1087                 cfg |= EXYNOS_CIGCTRL_CSC_ITU709;
1088         else
1089                 cfg |= EXYNOS_CIGCTRL_CSC_ITU601;
1090
1091         fimc_write(ctx, cfg, EXYNOS_CIGCTRL);
1092
1093         if (swap) {
1094                 img_pos.w = pos->h;
1095                 img_pos.h = pos->w;
1096                 img_sz.hsize = sz->vsize;
1097                 img_sz.vsize = sz->hsize;
1098         }
1099
1100         /* target image size */
1101         cfg = fimc_read(ctx, EXYNOS_CITRGFMT);
1102         cfg &= ~(EXYNOS_CITRGFMT_TARGETH_MASK |
1103                 EXYNOS_CITRGFMT_TARGETV_MASK);
1104         cfg |= (EXYNOS_CITRGFMT_TARGETHSIZE(img_pos.w) |
1105                 EXYNOS_CITRGFMT_TARGETVSIZE(img_pos.h));
1106         fimc_write(ctx, cfg, EXYNOS_CITRGFMT);
1107
1108         /* target area */
1109         cfg = EXYNOS_CITAREA_TARGET_AREA(img_pos.w * img_pos.h);
1110         fimc_write(ctx, cfg, EXYNOS_CITAREA);
1111
1112         /* offset Y(RGB), Cb, Cr */
1113         cfg = (EXYNOS_CIOYOFF_HORIZONTAL(img_pos.x) |
1114                 EXYNOS_CIOYOFF_VERTICAL(img_pos.y));
1115         fimc_write(ctx, cfg, EXYNOS_CIOYOFF);
1116         cfg = (EXYNOS_CIOCBOFF_HORIZONTAL(img_pos.x) |
1117                 EXYNOS_CIOCBOFF_VERTICAL(img_pos.y));
1118         fimc_write(ctx, cfg, EXYNOS_CIOCBOFF);
1119         cfg = (EXYNOS_CIOCROFF_HORIZONTAL(img_pos.x) |
1120                 EXYNOS_CIOCROFF_VERTICAL(img_pos.y));
1121         fimc_write(ctx, cfg, EXYNOS_CIOCROFF);
1122
1123         return 0;
1124 }
1125
1126 static int fimc_dst_get_buf_seq(struct fimc_context *ctx)
1127 {
1128         u32 cfg, i, buf_num = 0;
1129         u32 mask = 0x00000001;
1130
1131         cfg = fimc_read(ctx, EXYNOS_CIFCNTSEQ);
1132
1133         for (i = 0; i < FIMC_REG_SZ; i++)
1134                 if (cfg & (mask << i))
1135                         buf_num++;
1136
1137         DRM_DEBUG_KMS("buf_num[%d]\n", buf_num);
1138
1139         return buf_num;
1140 }
1141
1142 static int fimc_dst_set_buf_seq(struct fimc_context *ctx, u32 buf_id,
1143                 enum drm_exynos_ipp_buf_type buf_type)
1144 {
1145         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1146         bool enable;
1147         u32 cfg;
1148         u32 mask = 0x00000001 << buf_id;
1149         int ret = 0;
1150         unsigned long flags;
1151
1152         DRM_DEBUG_KMS("buf_id[%d]buf_type[%d]\n", buf_id, buf_type);
1153
1154         spin_lock_irqsave(&ctx->lock, flags);
1155
1156         /* mask register set */
1157         cfg = fimc_read(ctx, EXYNOS_CIFCNTSEQ);
1158
1159         switch (buf_type) {
1160         case IPP_BUF_ENQUEUE:
1161                 enable = true;
1162                 break;
1163         case IPP_BUF_DEQUEUE:
1164                 enable = false;
1165                 break;
1166         default:
1167                 dev_err(ippdrv->dev, "invalid buf ctrl parameter.\n");
1168                 ret =  -EINVAL;
1169                 goto err_unlock;
1170         }
1171
1172         /* sequence id */
1173         cfg &= ~mask;
1174         cfg |= (enable << buf_id);
1175         fimc_write(ctx, cfg, EXYNOS_CIFCNTSEQ);
1176
1177         /* interrupt enable */
1178         if (buf_type == IPP_BUF_ENQUEUE &&
1179             fimc_dst_get_buf_seq(ctx) >= FIMC_BUF_START)
1180                 fimc_mask_irq(ctx, true);
1181
1182         /* interrupt disable */
1183         if (buf_type == IPP_BUF_DEQUEUE &&
1184             fimc_dst_get_buf_seq(ctx) <= FIMC_BUF_STOP)
1185                 fimc_mask_irq(ctx, false);
1186
1187 err_unlock:
1188         spin_unlock_irqrestore(&ctx->lock, flags);
1189         return ret;
1190 }
1191
1192 static int fimc_dst_set_addr(struct device *dev,
1193                 struct drm_exynos_ipp_buf_info *buf_info, u32 buf_id,
1194                 enum drm_exynos_ipp_buf_type buf_type)
1195 {
1196         struct fimc_context *ctx = get_fimc_context(dev);
1197         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1198         struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
1199         struct drm_exynos_ipp_property *property;
1200         struct drm_exynos_ipp_config *config;
1201
1202         if (!c_node) {
1203                 DRM_ERROR("failed to get c_node.\n");
1204                 return -EINVAL;
1205         }
1206
1207         property = &c_node->property;
1208
1209         DRM_DEBUG_KMS("prop_id[%d]buf_id[%d]buf_type[%d]\n",
1210                 property->prop_id, buf_id, buf_type);
1211
1212         if (buf_id > FIMC_MAX_DST) {
1213                 dev_info(ippdrv->dev, "inavlid buf_id %d.\n", buf_id);
1214                 return -ENOMEM;
1215         }
1216
1217         /* address register set */
1218         switch (buf_type) {
1219         case IPP_BUF_ENQUEUE:
1220                 config = &property->config[EXYNOS_DRM_OPS_DST];
1221
1222                 fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_Y],
1223                         EXYNOS_CIOYSA(buf_id));
1224
1225                 if (config->fmt == DRM_FORMAT_YVU420) {
1226                         fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CR],
1227                                 EXYNOS_CIOCBSA(buf_id));
1228                         fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CB],
1229                                 EXYNOS_CIOCRSA(buf_id));
1230                 } else {
1231                         fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CB],
1232                                 EXYNOS_CIOCBSA(buf_id));
1233                         fimc_write(ctx, buf_info->base[EXYNOS_DRM_PLANAR_CR],
1234                                 EXYNOS_CIOCRSA(buf_id));
1235                 }
1236                 break;
1237         case IPP_BUF_DEQUEUE:
1238                 fimc_write(ctx, 0x0, EXYNOS_CIOYSA(buf_id));
1239                 fimc_write(ctx, 0x0, EXYNOS_CIOCBSA(buf_id));
1240                 fimc_write(ctx, 0x0, EXYNOS_CIOCRSA(buf_id));
1241                 break;
1242         default:
1243                 /* bypass */
1244                 break;
1245         }
1246
1247         return fimc_dst_set_buf_seq(ctx, buf_id, buf_type);
1248 }
1249
1250 static struct exynos_drm_ipp_ops fimc_dst_ops = {
1251         .set_fmt = fimc_dst_set_fmt,
1252         .set_transf = fimc_dst_set_transf,
1253         .set_size = fimc_dst_set_size,
1254         .set_addr = fimc_dst_set_addr,
1255 };
1256
1257 static int fimc_clk_ctrl(struct fimc_context *ctx, bool enable)
1258 {
1259         DRM_DEBUG_KMS("enable[%d]\n", enable);
1260
1261         if (enable) {
1262                 clk_prepare_enable(ctx->clocks[FIMC_CLK_GATE]);
1263                 clk_prepare_enable(ctx->clocks[FIMC_CLK_WB_A]);
1264                 ctx->suspended = false;
1265         } else {
1266                 clk_disable_unprepare(ctx->clocks[FIMC_CLK_GATE]);
1267                 clk_disable_unprepare(ctx->clocks[FIMC_CLK_WB_A]);
1268                 ctx->suspended = true;
1269         }
1270
1271         return 0;
1272 }
1273
1274 static irqreturn_t fimc_irq_handler(int irq, void *dev_id)
1275 {
1276         struct fimc_context *ctx = dev_id;
1277         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1278         struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
1279         struct drm_exynos_ipp_event_work *event_work =
1280                 c_node->event_work;
1281         int buf_id;
1282
1283         DRM_DEBUG_KMS("fimc id[%d]\n", ctx->id);
1284
1285         fimc_clear_irq(ctx);
1286         if (fimc_check_ovf(ctx))
1287                 return IRQ_NONE;
1288
1289         if (!fimc_check_frame_end(ctx))
1290                 return IRQ_NONE;
1291
1292         buf_id = fimc_get_buf_id(ctx);
1293         if (buf_id < 0)
1294                 return IRQ_HANDLED;
1295
1296         DRM_DEBUG_KMS("buf_id[%d]\n", buf_id);
1297
1298         if (fimc_dst_set_buf_seq(ctx, buf_id, IPP_BUF_DEQUEUE) < 0) {
1299                 DRM_ERROR("failed to dequeue.\n");
1300                 return IRQ_HANDLED;
1301         }
1302
1303         event_work->ippdrv = ippdrv;
1304         event_work->buf_id[EXYNOS_DRM_OPS_DST] = buf_id;
1305         queue_work(ippdrv->event_workq, (struct work_struct *)event_work);
1306
1307         return IRQ_HANDLED;
1308 }
1309
1310 static int fimc_init_prop_list(struct exynos_drm_ippdrv *ippdrv)
1311 {
1312         struct drm_exynos_ipp_prop_list *prop_list = &ippdrv->prop_list;
1313
1314         prop_list->version = 1;
1315         prop_list->writeback = 1;
1316         prop_list->refresh_min = FIMC_REFRESH_MIN;
1317         prop_list->refresh_max = FIMC_REFRESH_MAX;
1318         prop_list->flip = (1 << EXYNOS_DRM_FLIP_NONE) |
1319                                 (1 << EXYNOS_DRM_FLIP_VERTICAL) |
1320                                 (1 << EXYNOS_DRM_FLIP_HORIZONTAL);
1321         prop_list->degree = (1 << EXYNOS_DRM_DEGREE_0) |
1322                                 (1 << EXYNOS_DRM_DEGREE_90) |
1323                                 (1 << EXYNOS_DRM_DEGREE_180) |
1324                                 (1 << EXYNOS_DRM_DEGREE_270);
1325         prop_list->csc = 1;
1326         prop_list->crop = 1;
1327         prop_list->crop_max.hsize = FIMC_CROP_MAX;
1328         prop_list->crop_max.vsize = FIMC_CROP_MAX;
1329         prop_list->crop_min.hsize = FIMC_CROP_MIN;
1330         prop_list->crop_min.vsize = FIMC_CROP_MIN;
1331         prop_list->scale = 1;
1332         prop_list->scale_max.hsize = FIMC_SCALE_MAX;
1333         prop_list->scale_max.vsize = FIMC_SCALE_MAX;
1334         prop_list->scale_min.hsize = FIMC_SCALE_MIN;
1335         prop_list->scale_min.vsize = FIMC_SCALE_MIN;
1336
1337         return 0;
1338 }
1339
1340 static inline bool fimc_check_drm_flip(enum drm_exynos_flip flip)
1341 {
1342         switch (flip) {
1343         case EXYNOS_DRM_FLIP_NONE:
1344         case EXYNOS_DRM_FLIP_VERTICAL:
1345         case EXYNOS_DRM_FLIP_HORIZONTAL:
1346         case EXYNOS_DRM_FLIP_BOTH:
1347                 return true;
1348         default:
1349                 DRM_DEBUG_KMS("invalid flip\n");
1350                 return false;
1351         }
1352 }
1353
1354 static int fimc_ippdrv_check_property(struct device *dev,
1355                 struct drm_exynos_ipp_property *property)
1356 {
1357         struct fimc_context *ctx = get_fimc_context(dev);
1358         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1359         struct drm_exynos_ipp_prop_list *pp = &ippdrv->prop_list;
1360         struct drm_exynos_ipp_config *config;
1361         struct drm_exynos_pos *pos;
1362         struct drm_exynos_sz *sz;
1363         bool swap;
1364         int i;
1365
1366         for_each_ipp_ops(i) {
1367                 if ((i == EXYNOS_DRM_OPS_SRC) &&
1368                         (property->cmd == IPP_CMD_WB))
1369                         continue;
1370
1371                 config = &property->config[i];
1372                 pos = &config->pos;
1373                 sz = &config->sz;
1374
1375                 /* check for flip */
1376                 if (!fimc_check_drm_flip(config->flip)) {
1377                         DRM_ERROR("invalid flip.\n");
1378                         goto err_property;
1379                 }
1380
1381                 /* check for degree */
1382                 switch (config->degree) {
1383                 case EXYNOS_DRM_DEGREE_90:
1384                 case EXYNOS_DRM_DEGREE_270:
1385                         swap = true;
1386                         break;
1387                 case EXYNOS_DRM_DEGREE_0:
1388                 case EXYNOS_DRM_DEGREE_180:
1389                         swap = false;
1390                         break;
1391                 default:
1392                         DRM_ERROR("invalid degree.\n");
1393                         goto err_property;
1394                 }
1395
1396                 /* check for buffer bound */
1397                 if ((pos->x + pos->w > sz->hsize) ||
1398                         (pos->y + pos->h > sz->vsize)) {
1399                         DRM_ERROR("out of buf bound.\n");
1400                         goto err_property;
1401                 }
1402
1403                 /* check for crop */
1404                 if ((i == EXYNOS_DRM_OPS_SRC) && (pp->crop)) {
1405                         if (swap) {
1406                                 if ((pos->h < pp->crop_min.hsize) ||
1407                                         (sz->vsize > pp->crop_max.hsize) ||
1408                                         (pos->w < pp->crop_min.vsize) ||
1409                                         (sz->hsize > pp->crop_max.vsize)) {
1410                                         DRM_ERROR("out of crop size.\n");
1411                                         goto err_property;
1412                                 }
1413                         } else {
1414                                 if ((pos->w < pp->crop_min.hsize) ||
1415                                         (sz->hsize > pp->crop_max.hsize) ||
1416                                         (pos->h < pp->crop_min.vsize) ||
1417                                         (sz->vsize > pp->crop_max.vsize)) {
1418                                         DRM_ERROR("out of crop size.\n");
1419                                         goto err_property;
1420                                 }
1421                         }
1422                 }
1423
1424                 /* check for scale */
1425                 if ((i == EXYNOS_DRM_OPS_DST) && (pp->scale)) {
1426                         if (swap) {
1427                                 if ((pos->h < pp->scale_min.hsize) ||
1428                                         (sz->vsize > pp->scale_max.hsize) ||
1429                                         (pos->w < pp->scale_min.vsize) ||
1430                                         (sz->hsize > pp->scale_max.vsize)) {
1431                                         DRM_ERROR("out of scale size.\n");
1432                                         goto err_property;
1433                                 }
1434                         } else {
1435                                 if ((pos->w < pp->scale_min.hsize) ||
1436                                         (sz->hsize > pp->scale_max.hsize) ||
1437                                         (pos->h < pp->scale_min.vsize) ||
1438                                         (sz->vsize > pp->scale_max.vsize)) {
1439                                         DRM_ERROR("out of scale size.\n");
1440                                         goto err_property;
1441                                 }
1442                         }
1443                 }
1444         }
1445
1446         return 0;
1447
1448 err_property:
1449         for_each_ipp_ops(i) {
1450                 if ((i == EXYNOS_DRM_OPS_SRC) &&
1451                         (property->cmd == IPP_CMD_WB))
1452                         continue;
1453
1454                 config = &property->config[i];
1455                 pos = &config->pos;
1456                 sz = &config->sz;
1457
1458                 DRM_ERROR("[%s]f[%d]r[%d]pos[%d %d %d %d]sz[%d %d]\n",
1459                         i ? "dst" : "src", config->flip, config->degree,
1460                         pos->x, pos->y, pos->w, pos->h,
1461                         sz->hsize, sz->vsize);
1462         }
1463
1464         return -EINVAL;
1465 }
1466
1467 static void fimc_clear_addr(struct fimc_context *ctx)
1468 {
1469         int i;
1470
1471         for (i = 0; i < FIMC_MAX_SRC; i++) {
1472                 fimc_write(ctx, 0, EXYNOS_CIIYSA(i));
1473                 fimc_write(ctx, 0, EXYNOS_CIICBSA(i));
1474                 fimc_write(ctx, 0, EXYNOS_CIICRSA(i));
1475         }
1476
1477         for (i = 0; i < FIMC_MAX_DST; i++) {
1478                 fimc_write(ctx, 0, EXYNOS_CIOYSA(i));
1479                 fimc_write(ctx, 0, EXYNOS_CIOCBSA(i));
1480                 fimc_write(ctx, 0, EXYNOS_CIOCRSA(i));
1481         }
1482 }
1483
1484 static int fimc_ippdrv_reset(struct device *dev)
1485 {
1486         struct fimc_context *ctx = get_fimc_context(dev);
1487
1488         /* reset h/w block */
1489         fimc_sw_reset(ctx);
1490
1491         /* reset scaler capability */
1492         memset(&ctx->sc, 0x0, sizeof(ctx->sc));
1493
1494         fimc_clear_addr(ctx);
1495
1496         return 0;
1497 }
1498
1499 static int fimc_ippdrv_start(struct device *dev, enum drm_exynos_ipp_cmd cmd)
1500 {
1501         struct fimc_context *ctx = get_fimc_context(dev);
1502         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1503         struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
1504         struct drm_exynos_ipp_property *property;
1505         struct drm_exynos_ipp_config *config;
1506         struct drm_exynos_pos   img_pos[EXYNOS_DRM_OPS_MAX];
1507         struct drm_exynos_ipp_set_wb set_wb;
1508         int ret, i;
1509         u32 cfg0, cfg1;
1510
1511         DRM_DEBUG_KMS("cmd[%d]\n", cmd);
1512
1513         if (!c_node) {
1514                 DRM_ERROR("failed to get c_node.\n");
1515                 return -EINVAL;
1516         }
1517
1518         property = &c_node->property;
1519
1520         fimc_mask_irq(ctx, true);
1521
1522         for_each_ipp_ops(i) {
1523                 config = &property->config[i];
1524                 img_pos[i] = config->pos;
1525         }
1526
1527         ret = fimc_set_prescaler(ctx, &ctx->sc,
1528                 &img_pos[EXYNOS_DRM_OPS_SRC],
1529                 &img_pos[EXYNOS_DRM_OPS_DST]);
1530         if (ret) {
1531                 dev_err(dev, "failed to set precalser.\n");
1532                 return ret;
1533         }
1534
1535         /* If set ture, we can save jpeg about screen */
1536         fimc_handle_jpeg(ctx, false);
1537         fimc_set_scaler(ctx, &ctx->sc);
1538         fimc_set_polarity(ctx, &ctx->pol);
1539
1540         switch (cmd) {
1541         case IPP_CMD_M2M:
1542                 fimc_set_type_ctrl(ctx, FIMC_WB_NONE);
1543                 fimc_handle_lastend(ctx, false);
1544
1545                 /* setup dma */
1546                 cfg0 = fimc_read(ctx, EXYNOS_MSCTRL);
1547                 cfg0 &= ~EXYNOS_MSCTRL_INPUT_MASK;
1548                 cfg0 |= EXYNOS_MSCTRL_INPUT_MEMORY;
1549                 fimc_write(ctx, cfg0, EXYNOS_MSCTRL);
1550                 break;
1551         case IPP_CMD_WB:
1552                 fimc_set_type_ctrl(ctx, FIMC_WB_A);
1553                 fimc_handle_lastend(ctx, true);
1554
1555                 /* setup FIMD */
1556                 ret = fimc_set_camblk_fimd0_wb(ctx);
1557                 if (ret < 0) {
1558                         dev_err(dev, "camblk setup failed.\n");
1559                         return ret;
1560                 }
1561
1562                 set_wb.enable = 1;
1563                 set_wb.refresh = property->refresh_rate;
1564                 exynos_drm_ippnb_send_event(IPP_SET_WRITEBACK, (void *)&set_wb);
1565                 break;
1566         case IPP_CMD_OUTPUT:
1567         default:
1568                 ret = -EINVAL;
1569                 dev_err(dev, "invalid operations.\n");
1570                 return ret;
1571         }
1572
1573         /* Reset status */
1574         fimc_write(ctx, 0x0, EXYNOS_CISTATUS);
1575
1576         cfg0 = fimc_read(ctx, EXYNOS_CIIMGCPT);
1577         cfg0 &= ~EXYNOS_CIIMGCPT_IMGCPTEN_SC;
1578         cfg0 |= EXYNOS_CIIMGCPT_IMGCPTEN_SC;
1579
1580         /* Scaler */
1581         cfg1 = fimc_read(ctx, EXYNOS_CISCCTRL);
1582         cfg1 &= ~EXYNOS_CISCCTRL_SCAN_MASK;
1583         cfg1 |= (EXYNOS_CISCCTRL_PROGRESSIVE |
1584                 EXYNOS_CISCCTRL_SCALERSTART);
1585
1586         fimc_write(ctx, cfg1, EXYNOS_CISCCTRL);
1587
1588         /* Enable image capture*/
1589         cfg0 |= EXYNOS_CIIMGCPT_IMGCPTEN;
1590         fimc_write(ctx, cfg0, EXYNOS_CIIMGCPT);
1591
1592         /* Disable frame end irq */
1593         fimc_clear_bits(ctx, EXYNOS_CIGCTRL, EXYNOS_CIGCTRL_IRQ_END_DISABLE);
1594
1595         fimc_clear_bits(ctx, EXYNOS_CIOCTRL, EXYNOS_CIOCTRL_WEAVE_MASK);
1596
1597         if (cmd == IPP_CMD_M2M) {
1598                 fimc_set_bits(ctx, EXYNOS_MSCTRL, EXYNOS_MSCTRL_ENVID);
1599
1600                 fimc_set_bits(ctx, EXYNOS_MSCTRL, EXYNOS_MSCTRL_ENVID);
1601         }
1602
1603         return 0;
1604 }
1605
1606 static void fimc_ippdrv_stop(struct device *dev, enum drm_exynos_ipp_cmd cmd)
1607 {
1608         struct fimc_context *ctx = get_fimc_context(dev);
1609         struct drm_exynos_ipp_set_wb set_wb = {0, 0};
1610         u32 cfg;
1611
1612         DRM_DEBUG_KMS("cmd[%d]\n", cmd);
1613
1614         switch (cmd) {
1615         case IPP_CMD_M2M:
1616                 /* Source clear */
1617                 cfg = fimc_read(ctx, EXYNOS_MSCTRL);
1618                 cfg &= ~EXYNOS_MSCTRL_INPUT_MASK;
1619                 cfg &= ~EXYNOS_MSCTRL_ENVID;
1620                 fimc_write(ctx, cfg, EXYNOS_MSCTRL);
1621                 break;
1622         case IPP_CMD_WB:
1623                 exynos_drm_ippnb_send_event(IPP_SET_WRITEBACK, (void *)&set_wb);
1624                 break;
1625         case IPP_CMD_OUTPUT:
1626         default:
1627                 dev_err(dev, "invalid operations.\n");
1628                 break;
1629         }
1630
1631         fimc_mask_irq(ctx, false);
1632
1633         /* reset sequence */
1634         fimc_write(ctx, 0x0, EXYNOS_CIFCNTSEQ);
1635
1636         /* Scaler disable */
1637         fimc_clear_bits(ctx, EXYNOS_CISCCTRL, EXYNOS_CISCCTRL_SCALERSTART);
1638
1639         /* Disable image capture */
1640         fimc_clear_bits(ctx, EXYNOS_CIIMGCPT,
1641                 EXYNOS_CIIMGCPT_IMGCPTEN_SC | EXYNOS_CIIMGCPT_IMGCPTEN);
1642
1643         /* Enable frame end irq */
1644         fimc_set_bits(ctx, EXYNOS_CIGCTRL, EXYNOS_CIGCTRL_IRQ_END_DISABLE);
1645 }
1646
1647 static void fimc_put_clocks(struct fimc_context *ctx)
1648 {
1649         int i;
1650
1651         for (i = 0; i < FIMC_CLKS_MAX; i++) {
1652                 if (IS_ERR(ctx->clocks[i]))
1653                         continue;
1654                 clk_put(ctx->clocks[i]);
1655                 ctx->clocks[i] = ERR_PTR(-EINVAL);
1656         }
1657 }
1658
1659 static int fimc_setup_clocks(struct fimc_context *ctx)
1660 {
1661         struct device *fimc_dev = ctx->ippdrv.dev;
1662         struct device *dev;
1663         int ret, i;
1664
1665         for (i = 0; i < FIMC_CLKS_MAX; i++)
1666                 ctx->clocks[i] = ERR_PTR(-EINVAL);
1667
1668         for (i = 0; i < FIMC_CLKS_MAX; i++) {
1669                 if (i == FIMC_CLK_WB_A || i == FIMC_CLK_WB_B)
1670                         dev = fimc_dev->parent;
1671                 else
1672                         dev = fimc_dev;
1673
1674                 ctx->clocks[i] = clk_get(dev, fimc_clock_names[i]);
1675                 if (IS_ERR(ctx->clocks[i])) {
1676                         if (i >= FIMC_CLK_MUX)
1677                                 break;
1678                         ret = PTR_ERR(ctx->clocks[i]);
1679                         dev_err(fimc_dev, "failed to get clock: %s\n",
1680                                                 fimc_clock_names[i]);
1681                         goto e_clk_free;
1682                 }
1683         }
1684
1685         /* Optional FIMC LCLK parent clock setting */
1686         if (!IS_ERR(ctx->clocks[FIMC_CLK_PARENT])) {
1687                 ret = clk_set_parent(ctx->clocks[FIMC_CLK_MUX],
1688                                      ctx->clocks[FIMC_CLK_PARENT]);
1689                 if (ret < 0) {
1690                         dev_err(fimc_dev, "failed to set parent.\n");
1691                         goto e_clk_free;
1692                 }
1693         }
1694
1695         ret = clk_set_rate(ctx->clocks[FIMC_CLK_LCLK], ctx->clk_frequency);
1696         if (ret < 0)
1697                 goto e_clk_free;
1698
1699         ret = clk_prepare_enable(ctx->clocks[FIMC_CLK_LCLK]);
1700         if (!ret)
1701                 return ret;
1702 e_clk_free:
1703         fimc_put_clocks(ctx);
1704         return ret;
1705 }
1706
1707 static int fimc_parse_dt(struct fimc_context *ctx)
1708 {
1709         struct device_node *node = ctx->ippdrv.dev->of_node;
1710
1711         /* Handle only devices that support the LCD Writeback data path */
1712         if (!of_property_read_bool(node, "samsung,lcd-wb"))
1713                 return -ENODEV;
1714
1715         if (of_property_read_u32(node, "clock-frequency",
1716                                         &ctx->clk_frequency))
1717                 ctx->clk_frequency = FIMC_DEFAULT_LCLK_FREQUENCY;
1718
1719         ctx->id = of_alias_get_id(node, "fimc");
1720
1721         if (ctx->id < 0) {
1722                 dev_err(ctx->ippdrv.dev, "failed to get node alias id.\n");
1723                 return -EINVAL;
1724         }
1725
1726         return 0;
1727 }
1728
1729 static int fimc_probe(struct platform_device *pdev)
1730 {
1731         struct device *dev = &pdev->dev;
1732         struct fimc_context *ctx;
1733         struct resource *res;
1734         struct exynos_drm_ippdrv *ippdrv;
1735         int ret;
1736
1737         if (!dev->of_node) {
1738                 dev_err(dev, "device tree node not found.\n");
1739                 return -ENODEV;
1740         }
1741
1742         ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1743         if (!ctx)
1744                 return -ENOMEM;
1745
1746         ctx->ippdrv.dev = dev;
1747
1748         ret = fimc_parse_dt(ctx);
1749         if (ret < 0)
1750                 return ret;
1751
1752         ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
1753                                                 "samsung,sysreg");
1754         if (IS_ERR(ctx->sysreg)) {
1755                 dev_err(dev, "syscon regmap lookup failed.\n");
1756                 return PTR_ERR(ctx->sysreg);
1757         }
1758
1759         /* resource memory */
1760         ctx->regs_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1761         ctx->regs = devm_ioremap_resource(dev, ctx->regs_res);
1762         if (IS_ERR(ctx->regs))
1763                 return PTR_ERR(ctx->regs);
1764
1765         /* resource irq */
1766         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1767         if (!res) {
1768                 dev_err(dev, "failed to request irq resource.\n");
1769                 return -ENOENT;
1770         }
1771
1772         ctx->irq = res->start;
1773         ret = devm_request_threaded_irq(dev, ctx->irq, NULL, fimc_irq_handler,
1774                 IRQF_ONESHOT, "drm_fimc", ctx);
1775         if (ret < 0) {
1776                 dev_err(dev, "failed to request irq.\n");
1777                 return ret;
1778         }
1779
1780         ret = fimc_setup_clocks(ctx);
1781         if (ret < 0)
1782                 return ret;
1783
1784         ippdrv = &ctx->ippdrv;
1785         ippdrv->ops[EXYNOS_DRM_OPS_SRC] = &fimc_src_ops;
1786         ippdrv->ops[EXYNOS_DRM_OPS_DST] = &fimc_dst_ops;
1787         ippdrv->check_property = fimc_ippdrv_check_property;
1788         ippdrv->reset = fimc_ippdrv_reset;
1789         ippdrv->start = fimc_ippdrv_start;
1790         ippdrv->stop = fimc_ippdrv_stop;
1791         ret = fimc_init_prop_list(ippdrv);
1792         if (ret < 0) {
1793                 dev_err(dev, "failed to init property list.\n");
1794                 goto err_put_clk;
1795         }
1796
1797         DRM_DEBUG_KMS("id[%d]ippdrv[0x%x]\n", ctx->id, (int)ippdrv);
1798
1799         spin_lock_init(&ctx->lock);
1800         platform_set_drvdata(pdev, ctx);
1801
1802         pm_runtime_set_active(dev);
1803         pm_runtime_enable(dev);
1804
1805         ret = exynos_drm_ippdrv_register(ippdrv);
1806         if (ret < 0) {
1807                 dev_err(dev, "failed to register drm fimc device.\n");
1808                 goto err_pm_dis;
1809         }
1810
1811         dev_info(dev, "drm fimc registered successfully.\n");
1812
1813         return 0;
1814
1815 err_pm_dis:
1816         pm_runtime_disable(dev);
1817 err_put_clk:
1818         fimc_put_clocks(ctx);
1819
1820         return ret;
1821 }
1822
1823 static int fimc_remove(struct platform_device *pdev)
1824 {
1825         struct device *dev = &pdev->dev;
1826         struct fimc_context *ctx = get_fimc_context(dev);
1827         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1828
1829         exynos_drm_ippdrv_unregister(ippdrv);
1830
1831         fimc_put_clocks(ctx);
1832         pm_runtime_set_suspended(dev);
1833         pm_runtime_disable(dev);
1834
1835         return 0;
1836 }
1837
1838 #ifdef CONFIG_PM_SLEEP
1839 static int fimc_suspend(struct device *dev)
1840 {
1841         struct fimc_context *ctx = get_fimc_context(dev);
1842
1843         DRM_DEBUG_KMS("id[%d]\n", ctx->id);
1844
1845         if (pm_runtime_suspended(dev))
1846                 return 0;
1847
1848         return fimc_clk_ctrl(ctx, false);
1849 }
1850
1851 static int fimc_resume(struct device *dev)
1852 {
1853         struct fimc_context *ctx = get_fimc_context(dev);
1854
1855         DRM_DEBUG_KMS("id[%d]\n", ctx->id);
1856
1857         if (!pm_runtime_suspended(dev))
1858                 return fimc_clk_ctrl(ctx, true);
1859
1860         return 0;
1861 }
1862 #endif
1863
1864 #ifdef CONFIG_PM_RUNTIME
1865 static int fimc_runtime_suspend(struct device *dev)
1866 {
1867         struct fimc_context *ctx = get_fimc_context(dev);
1868
1869         DRM_DEBUG_KMS("id[%d]\n", ctx->id);
1870
1871         return  fimc_clk_ctrl(ctx, false);
1872 }
1873
1874 static int fimc_runtime_resume(struct device *dev)
1875 {
1876         struct fimc_context *ctx = get_fimc_context(dev);
1877
1878         DRM_DEBUG_KMS("id[%d]\n", ctx->id);
1879
1880         return  fimc_clk_ctrl(ctx, true);
1881 }
1882 #endif
1883
1884 static const struct dev_pm_ops fimc_pm_ops = {
1885         SET_SYSTEM_SLEEP_PM_OPS(fimc_suspend, fimc_resume)
1886         SET_RUNTIME_PM_OPS(fimc_runtime_suspend, fimc_runtime_resume, NULL)
1887 };
1888
1889 static const struct of_device_id fimc_of_match[] = {
1890         { .compatible = "samsung,exynos4210-fimc" },
1891         { .compatible = "samsung,exynos4212-fimc" },
1892         { },
1893 };
1894
1895 struct platform_driver fimc_driver = {
1896         .probe          = fimc_probe,
1897         .remove         = fimc_remove,
1898         .driver         = {
1899                 .of_match_table = fimc_of_match,
1900                 .name   = "exynos-drm-fimc",
1901                 .owner  = THIS_MODULE,
1902                 .pm     = &fimc_pm_ops,
1903         },
1904 };
1905