drivers/gpu/drm/exynos/exynos_drm_fimc.c

   1 /*
   2  * Copyright (C) 2012 Samsung Electronics Co.Ltd
   3  * Authors:
   4  *      Eunchul Kim <chulspro.kim@samsung.com>
   5  *      Jinyoung Jeon <jy0.jeon@samsung.com>
   6  *      Sangmin Lee <lsmin.lee@samsung.com>
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  *
  13  */
  14 #include <linux/kernel.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/mfd/syscon.h>
  17 #include <linux/regmap.h>
  18 #include <linux/clk.h>
  19 #include <linux/pm_runtime.h>
  20 #include <linux/of.h>
  21
  22 #include <drm/drmP.h>
  23 #include <drm/exynos_drm.h>
  24 #include "regs-fimc.h"
  25 #include "exynos_drm_drv.h"
  26 #include "exynos_drm_ipp.h"
  27 #include "exynos_drm_fimc.h"
  28
  29 /*
  30  * FIMC stands for Fully Interactive Mobile Camera and
  31  * supports image scaler/rotator and input/output DMA operations.
  32  * input DMA reads image data from the memory.
  33  * output DMA writes image data to memory.
  34  * FIMC supports image rotation and image effect functions.
  35  *
  36  * M2M operation : supports crop/scale/rotation/csc so on.
  37  * Memory ----> FIMC H/W ----> Memory.
  38  * Writeback operation : supports cloned screen with FIMD.
  39  * FIMD ----> FIMC H/W ----> Memory.
  40  * Output operation : supports direct display using local path.
  41  * Memory ----> FIMC H/W ----> FIMD.
  42  */
  43
  44 /*
  45  * TODO
  46  * 1. check suspend/resume api if needed.
  47  * 2. need to check use case platform_device_id.
  48  * 3. check src/dst size with, height.
  49  * 4. added check_prepare api for right register.
  50  * 5. need to add supported list in prop_list.
  51  * 6. check prescaler/scaler optimization.
  52  */
  53
  54 #define FIMC_MAX_DEVS   4
  55 #define FIMC_MAX_SRC    2
  56 #define FIMC_MAX_DST    32
  57 #define FIMC_SHFACTOR   10
  58 #define FIMC_BUF_STOP   1
  59 #define FIMC_BUF_START  2
  60 #define FIMC_REG_SZ             32
  61 #define FIMC_WIDTH_ITU_709      1280
  62 #define FIMC_REFRESH_MAX        60
  63 #define FIMC_REFRESH_MIN        12
  64 #define FIMC_CROP_MAX   8192
  65 #define FIMC_CROP_MIN   32
  66 #define FIMC_SCALE_MAX  4224
  67 #define FIMC_SCALE_MIN  32
  68
  69 #define get_fimc_context(dev)   platform_get_drvdata(to_platform_device(dev))
  70 #define get_ctx_from_ippdrv(ippdrv)     container_of(ippdrv,\
  71                                         struct fimc_context, ippdrv);
  72 #define fimc_read(offset)               readl(ctx->regs + (offset))
  73 #define fimc_write(cfg, offset) writel(cfg, ctx->regs + (offset))
  74
  75 enum fimc_wb {
  76         FIMC_WB_NONE,
  77         FIMC_WB_A,
  78         FIMC_WB_B,
  79 };
  80
  81 enum {
  82         FIMC_CLK_LCLK,
  83         FIMC_CLK_GATE,
  84         FIMC_CLK_WB_A,
  85         FIMC_CLK_WB_B,
  86         FIMC_CLK_MUX,
  87         FIMC_CLK_PARENT,
  88         FIMC_CLKS_MAX
  89 };
  90
  91 static const char * const fimc_clock_names[] = {
  92         [FIMC_CLK_LCLK]   = "sclk_fimc",
  93         [FIMC_CLK_GATE]   = "fimc",
  94         [FIMC_CLK_WB_A]   = "pxl_async0",
  95         [FIMC_CLK_WB_B]   = "pxl_async1",
  96         [FIMC_CLK_MUX]    = "mux",
  97         [FIMC_CLK_PARENT] = "parent",
  98 };
  99
 100 #define FIMC_DEFAULT_LCLK_FREQUENCY 133000000UL
 101
 102 /*
 103  * A structure of scaler.
 104  *
 105  * @range: narrow, wide.
 106  * @bypass: unused scaler path.
 107  * @up_h: horizontal scale up.
 108  * @up_v: vertical scale up.
 109  * @hratio: horizontal ratio.
 110  * @vratio: vertical ratio.
 111  */
 112 struct fimc_scaler {
 113         bool    range;
 114         bool bypass;
 115         bool up_h;
 116         bool up_v;
 117         u32 hratio;
 118         u32 vratio;
 119 };
 120
 121 /*
 122  * A structure of scaler capability.
 123  *
 124  * find user manual table 43-1.
 125  * @in_hori: scaler input horizontal size.
 126  * @bypass: scaler bypass mode.
 127  * @dst_h_wo_rot: target horizontal size without output rotation.
 128  * @dst_h_rot: target horizontal size with output rotation.
 129  * @rl_w_wo_rot: real width without input rotation.
 130  * @rl_h_rot: real height without output rotation.
 131  */
 132 struct fimc_capability {
 133         /* scaler */
 134         u32     in_hori;
 135         u32     bypass;
 136         /* output rotator */
 137         u32     dst_h_wo_rot;
 138         u32     dst_h_rot;
 139         /* input rotator */
 140         u32     rl_w_wo_rot;
 141         u32     rl_h_rot;
 142 };
 143
 144 /*
 145  * A structure of fimc context.
 146  *
 147  * @ippdrv: prepare initialization using ippdrv.
 148  * @regs_res: register resources.
 149  * @regs: memory mapped io registers.
 150  * @lock: locking of operations.
 151  * @clocks: fimc clocks.
 152  * @clk_frequency: LCLK clock frequency.
 153  * @sysreg: handle to SYSREG block regmap.
 154  * @sc: scaler infomations.
 155  * @pol: porarity of writeback.
 156  * @id: fimc id.
 157  * @irq: irq number.
 158  * @suspended: qos operations.
 159  */
 160 struct fimc_context {
 161         struct exynos_drm_ippdrv        ippdrv;
 162         struct resource *regs_res;
 163         void __iomem    *regs;
 164         struct mutex    lock;
 165         struct clk      *clocks[FIMC_CLKS_MAX];
 166         u32             clk_frequency;
 167         struct regmap   *sysreg;
 168         struct fimc_scaler      sc;
 169         struct exynos_drm_ipp_pol       pol;
 170         int     id;
 171         int     irq;
 172         bool    suspended;
 173 };
 174
 175 static void fimc_sw_reset(struct fimc_context *ctx)
 176 {
 177         u32 cfg;
 178
 179         /* stop dma operation */
 180         cfg = fimc_read(EXYNOS_CISTATUS);
 181         if (EXYNOS_CISTATUS_GET_ENVID_STATUS(cfg)) {
 182                 cfg = fimc_read(EXYNOS_MSCTRL);
 183                 cfg &= ~EXYNOS_MSCTRL_ENVID;
 184                 fimc_write(cfg, EXYNOS_MSCTRL);
 185         }
 186
 187         cfg = fimc_read(EXYNOS_CISRCFMT);
 188         cfg |= EXYNOS_CISRCFMT_ITU601_8BIT;
 189         fimc_write(cfg, EXYNOS_CISRCFMT);
 190
 191         /* disable image capture */
 192         cfg = fimc_read(EXYNOS_CIIMGCPT);
 193         cfg &= ~(EXYNOS_CIIMGCPT_IMGCPTEN_SC | EXYNOS_CIIMGCPT_IMGCPTEN);
 194         fimc_write(cfg, EXYNOS_CIIMGCPT);
 195
 196         /* s/w reset */
 197         cfg = fimc_read(EXYNOS_CIGCTRL);
 198         cfg |= (EXYNOS_CIGCTRL_SWRST);
 199         fimc_write(cfg, EXYNOS_CIGCTRL);
 200
 201         /* s/w reset complete */
 202         cfg = fimc_read(EXYNOS_CIGCTRL);
 203         cfg &= ~EXYNOS_CIGCTRL_SWRST;
 204         fimc_write(cfg, EXYNOS_CIGCTRL);
 205
 206         /* reset sequence */
 207         fimc_write(0x0, EXYNOS_CIFCNTSEQ);
 208 }
 209
 210 static int fimc_set_camblk_fimd0_wb(struct fimc_context *ctx)
 211 {
 212         return regmap_update_bits(ctx->sysreg, SYSREG_CAMERA_BLK,
 213                                   SYSREG_FIMD0WB_DEST_MASK,
 214                                   ctx->id << SYSREG_FIMD0WB_DEST_SHIFT);
 215 }
 216
 217 static void fimc_set_type_ctrl(struct fimc_context *ctx, enum fimc_wb wb)
 218 {
 219         u32 cfg;
 220
 221         DRM_DEBUG_KMS("wb[%d]\n", wb);
 222
 223         cfg = fimc_read(EXYNOS_CIGCTRL);
 224         cfg &= ~(EXYNOS_CIGCTRL_TESTPATTERN_MASK |
 225                 EXYNOS_CIGCTRL_SELCAM_ITU_MASK |
 226                 EXYNOS_CIGCTRL_SELCAM_MIPI_MASK |
 227                 EXYNOS_CIGCTRL_SELCAM_FIMC_MASK |
 228                 EXYNOS_CIGCTRL_SELWB_CAMIF_MASK |
 229                 EXYNOS_CIGCTRL_SELWRITEBACK_MASK);
 230
 231         switch (wb) {
 232         case FIMC_WB_A:
 233                 cfg |= (EXYNOS_CIGCTRL_SELWRITEBACK_A |
 234                         EXYNOS_CIGCTRL_SELWB_CAMIF_WRITEBACK);
 235                 break;
 236         case FIMC_WB_B:
 237                 cfg |= (EXYNOS_CIGCTRL_SELWRITEBACK_B |
 238                         EXYNOS_CIGCTRL_SELWB_CAMIF_WRITEBACK);
 239                 break;
 240         case FIMC_WB_NONE:
 241         default:
 242                 cfg |= (EXYNOS_CIGCTRL_SELCAM_ITU_A |
 243                         EXYNOS_CIGCTRL_SELWRITEBACK_A |
 244                         EXYNOS_CIGCTRL_SELCAM_MIPI_A |
 245                         EXYNOS_CIGCTRL_SELCAM_FIMC_ITU);
 246                 break;
 247         }
 248
 249         fimc_write(cfg, EXYNOS_CIGCTRL);
 250 }
 251
 252 static void fimc_set_polarity(struct fimc_context *ctx,
 253                 struct exynos_drm_ipp_pol *pol)
 254 {
 255         u32 cfg;
 256
 257         DRM_DEBUG_KMS("inv_pclk[%d]inv_vsync[%d]\n",
 258                 pol->inv_pclk, pol->inv_vsync);
 259         DRM_DEBUG_KMS("inv_href[%d]inv_hsync[%d]\n",
 260                 pol->inv_href, pol->inv_hsync);
 261
 262         cfg = fimc_read(EXYNOS_CIGCTRL);
 263         cfg &= ~(EXYNOS_CIGCTRL_INVPOLPCLK | EXYNOS_CIGCTRL_INVPOLVSYNC |
 264                  EXYNOS_CIGCTRL_INVPOLHREF | EXYNOS_CIGCTRL_INVPOLHSYNC);
 265
 266         if (pol->inv_pclk)
 267                 cfg |= EXYNOS_CIGCTRL_INVPOLPCLK;
 268         if (pol->inv_vsync)
 269                 cfg |= EXYNOS_CIGCTRL_INVPOLVSYNC;
 270         if (pol->inv_href)
 271                 cfg |= EXYNOS_CIGCTRL_INVPOLHREF;
 272         if (pol->inv_hsync)
 273                 cfg |= EXYNOS_CIGCTRL_INVPOLHSYNC;
 274
 275         fimc_write(cfg, EXYNOS_CIGCTRL);
 276 }
 277
 278 static void fimc_handle_jpeg(struct fimc_context *ctx, bool enable)
 279 {
 280         u32 cfg;
 281
 282         DRM_DEBUG_KMS("enable[%d]\n", enable);
 283
 284         cfg = fimc_read(EXYNOS_CIGCTRL);
 285         if (enable)
 286                 cfg |= EXYNOS_CIGCTRL_CAM_JPEG;
 287         else
 288                 cfg &= ~EXYNOS_CIGCTRL_CAM_JPEG;
 289
 290         fimc_write(cfg, EXYNOS_CIGCTRL);
 291 }
 292
 293 static void fimc_handle_irq(struct fimc_context *ctx, bool enable,
 294                 bool overflow, bool level)
 295 {
 296         u32 cfg;
 297
 298         DRM_DEBUG_KMS("enable[%d]overflow[%d]level[%d]\n",
 299                         enable, overflow, level);
 300
 301         cfg = fimc_read(EXYNOS_CIGCTRL);
 302         if (enable) {
 303                 cfg &= ~(EXYNOS_CIGCTRL_IRQ_OVFEN | EXYNOS_CIGCTRL_IRQ_LEVEL);
 304                 cfg |= EXYNOS_CIGCTRL_IRQ_ENABLE;
 305                 if (overflow)
 306                         cfg |= EXYNOS_CIGCTRL_IRQ_OVFEN;
 307                 if (level)
 308                         cfg |= EXYNOS_CIGCTRL_IRQ_LEVEL;
 309         } else
 310                 cfg &= ~(EXYNOS_CIGCTRL_IRQ_OVFEN | EXYNOS_CIGCTRL_IRQ_ENABLE);
 311
 312         fimc_write(cfg, EXYNOS_CIGCTRL);
 313 }
 314
 315 static void fimc_clear_irq(struct fimc_context *ctx)
 316 {
 317         u32 cfg;
 318
 319         cfg = fimc_read(EXYNOS_CIGCTRL);
 320         cfg |= EXYNOS_CIGCTRL_IRQ_CLR;
 321         fimc_write(cfg, EXYNOS_CIGCTRL);
 322 }
 323
 324 static bool fimc_check_ovf(struct fimc_context *ctx)
 325 {
 326         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
 327         u32 cfg, status, flag;
 328
 329         status = fimc_read(EXYNOS_CISTATUS);
 330         flag = EXYNOS_CISTATUS_OVFIY | EXYNOS_CISTATUS_OVFICB |
 331                 EXYNOS_CISTATUS_OVFICR;
 332
 333         DRM_DEBUG_KMS("flag[0x%x]\n", flag);
 334
 335         if (status & flag) {
 336                 cfg = fimc_read(EXYNOS_CIWDOFST);
 337                 cfg |= (EXYNOS_CIWDOFST_CLROVFIY | EXYNOS_CIWDOFST_CLROVFICB |
 338                         EXYNOS_CIWDOFST_CLROVFICR);
 339
 340                 fimc_write(cfg, EXYNOS_CIWDOFST);
 341
 342                 cfg = fimc_read(EXYNOS_CIWDOFST);
 343                 cfg &= ~(EXYNOS_CIWDOFST_CLROVFIY | EXYNOS_CIWDOFST_CLROVFICB |
 344                         EXYNOS_CIWDOFST_CLROVFICR);
 345
 346                 fimc_write(cfg, EXYNOS_CIWDOFST);
 347
 348                 dev_err(ippdrv->dev, "occurred overflow at %d, status 0x%x.\n",
 349                         ctx->id, status);
 350                 return true;
 351         }
 352
 353         return false;
 354 }
 355
 356 static bool fimc_check_frame_end(struct fimc_context *ctx)
 357 {
 358         u32 cfg;
 359
 360         cfg = fimc_read(EXYNOS_CISTATUS);
 361
 362         DRM_DEBUG_KMS("cfg[0x%x]\n", cfg);
 363
 364         if (!(cfg & EXYNOS_CISTATUS_FRAMEEND))
 365                 return false;
 366
 367         cfg &= ~(EXYNOS_CISTATUS_FRAMEEND);
 368         fimc_write(cfg, EXYNOS_CISTATUS);
 369
 370         return true;
 371 }
 372
 373 static int fimc_get_buf_id(struct fimc_context *ctx)
 374 {
 375         u32 cfg;
 376         int frame_cnt, buf_id;
 377
 378         cfg = fimc_read(EXYNOS_CISTATUS2);
 379         frame_cnt = EXYNOS_CISTATUS2_GET_FRAMECOUNT_BEFORE(cfg);
 380
 381         if (frame_cnt == 0)
 382                 frame_cnt = EXYNOS_CISTATUS2_GET_FRAMECOUNT_PRESENT(cfg);
 383
 384         DRM_DEBUG_KMS("present[%d]before[%d]\n",
 385                 EXYNOS_CISTATUS2_GET_FRAMECOUNT_PRESENT(cfg),
 386                 EXYNOS_CISTATUS2_GET_FRAMECOUNT_BEFORE(cfg));
 387
 388         if (frame_cnt == 0) {
 389                 DRM_ERROR("failed to get frame count.\n");
 390                 return -EIO;
 391         }
 392
 393         buf_id = frame_cnt - 1;
 394         DRM_DEBUG_KMS("buf_id[%d]\n", buf_id);
 395
 396         return buf_id;
 397 }
 398
 399 static void fimc_handle_lastend(struct fimc_context *ctx, bool enable)
 400 {
 401         u32 cfg;
 402
 403         DRM_DEBUG_KMS("enable[%d]\n", enable);
 404
 405         cfg = fimc_read(EXYNOS_CIOCTRL);
 406         if (enable)
 407                 cfg |= EXYNOS_CIOCTRL_LASTENDEN;
 408         else
 409                 cfg &= ~EXYNOS_CIOCTRL_LASTENDEN;
 410
 411         fimc_write(cfg, EXYNOS_CIOCTRL);
 412 }
 413
 414
 415 static int fimc_src_set_fmt_order(struct fimc_context *ctx, u32 fmt)
 416 {
 417         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
 418         u32 cfg;
 419
 420         DRM_DEBUG_KMS("fmt[0x%x]\n", fmt);
 421
 422         /* RGB */
 423         cfg = fimc_read(EXYNOS_CISCCTRL);
 424         cfg &= ~EXYNOS_CISCCTRL_INRGB_FMT_RGB_MASK;
 425
 426         switch (fmt) {
 427         case DRM_FORMAT_RGB565:
 428                 cfg |= EXYNOS_CISCCTRL_INRGB_FMT_RGB565;
 429                 fimc_write(cfg, EXYNOS_CISCCTRL);
 430                 return 0;
 431         case DRM_FORMAT_RGB888:
 432         case DRM_FORMAT_XRGB8888:
 433                 cfg |= EXYNOS_CISCCTRL_INRGB_FMT_RGB888;
 434                 fimc_write(cfg, EXYNOS_CISCCTRL);
 435                 return 0;
 436         default:
 437                 /* bypass */
 438                 break;
 439         }
 440
 441         /* YUV */
 442         cfg = fimc_read(EXYNOS_MSCTRL);
 443         cfg &= ~(EXYNOS_MSCTRL_ORDER2P_SHIFT_MASK |
 444                 EXYNOS_MSCTRL_C_INT_IN_2PLANE |
 445                 EXYNOS_MSCTRL_ORDER422_YCBYCR);
 446
 447         switch (fmt) {
 448         case DRM_FORMAT_YUYV:
 449                 cfg |= EXYNOS_MSCTRL_ORDER422_YCBYCR;
 450                 break;
 451         case DRM_FORMAT_YVYU:
 452                 cfg |= EXYNOS_MSCTRL_ORDER422_YCRYCB;
 453                 break;
 454         case DRM_FORMAT_UYVY:
 455                 cfg |= EXYNOS_MSCTRL_ORDER422_CBYCRY;
 456                 break;
 457         case DRM_FORMAT_VYUY:
 458         case DRM_FORMAT_YUV444:
 459                 cfg |= EXYNOS_MSCTRL_ORDER422_CRYCBY;
 460                 break;
 461         case DRM_FORMAT_NV21:
 462         case DRM_FORMAT_NV61:
 463                 cfg |= (EXYNOS_MSCTRL_ORDER2P_LSB_CRCB |
 464                         EXYNOS_MSCTRL_C_INT_IN_2PLANE);
 465                 break;
 466         case DRM_FORMAT_YUV422:
 467         case DRM_FORMAT_YUV420:
 468         case DRM_FORMAT_YVU420:
 469                 cfg |= EXYNOS_MSCTRL_C_INT_IN_3PLANE;
 470                 break;
 471         case DRM_FORMAT_NV12:
 472         case DRM_FORMAT_NV12MT:
 473         case DRM_FORMAT_NV16:
 474                 cfg |= (EXYNOS_MSCTRL_ORDER2P_LSB_CBCR |
 475                         EXYNOS_MSCTRL_C_INT_IN_2PLANE);
 476                 break;
 477         default:
 478                 dev_err(ippdrv->dev, "inavlid source yuv order 0x%x.\n", fmt);
 479                 return -EINVAL;
 480         }
 481
 482         fimc_write(cfg, EXYNOS_MSCTRL);
 483
 484         return 0;
 485 }
 486
 487 static int fimc_src_set_fmt(struct device *dev, u32 fmt)
 488 {
 489         struct fimc_context *ctx = get_fimc_context(dev);
 490         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
 491         u32 cfg;
 492
 493         DRM_DEBUG_KMS("fmt[0x%x]\n", fmt);
 494
 495         cfg = fimc_read(EXYNOS_MSCTRL);
 496         cfg &= ~EXYNOS_MSCTRL_INFORMAT_RGB;
 497
 498         switch (fmt) {
 499         case DRM_FORMAT_RGB565:
 500         case DRM_FORMAT_RGB888:
 501         case DRM_FORMAT_XRGB8888:
 502                 cfg |= EXYNOS_MSCTRL_INFORMAT_RGB;
 503                 break;
 504         case DRM_FORMAT_YUV444:
 505                 cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR420;
 506                 break;
 507         case DRM_FORMAT_YUYV:
 508         case DRM_FORMAT_YVYU:
 509         case DRM_FORMAT_UYVY:
 510         case DRM_FORMAT_VYUY:
 511                 cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR422_1PLANE;
 512                 break;
 513         case DRM_FORMAT_NV16:
 514         case DRM_FORMAT_NV61:
 515         case DRM_FORMAT_YUV422:
 516                 cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR422;
 517                 break;
 518         case DRM_FORMAT_YUV420:
 519         case DRM_FORMAT_YVU420:
 520         case DRM_FORMAT_NV12:
 521         case DRM_FORMAT_NV21:
 522         case DRM_FORMAT_NV12MT:
 523                 cfg |= EXYNOS_MSCTRL_INFORMAT_YCBCR420;
 524                 break;
 525         default:
 526                 dev_err(ippdrv->dev, "inavlid source format 0x%x.\n", fmt);
 527                 return -EINVAL;
 528         }
 529
 530         fimc_write(cfg, EXYNOS_MSCTRL);
 531
 532         cfg = fimc_read(EXYNOS_CIDMAPARAM);
 533         cfg &= ~EXYNOS_CIDMAPARAM_R_MODE_MASK;
 534
 535         if (fmt == DRM_FORMAT_NV12MT)
 536                 cfg |= EXYNOS_CIDMAPARAM_R_MODE_64X32;
 537         else
 538                 cfg |= EXYNOS_CIDMAPARAM_R_MODE_LINEAR;
 539
 540         fimc_write(cfg, EXYNOS_CIDMAPARAM);
 541
 542         return fimc_src_set_fmt_order(ctx, fmt);
 543 }
 544
 545 static int fimc_src_set_transf(struct device *dev,
 546                 enum drm_exynos_degree degree,
 547                 enum drm_exynos_flip flip, bool *swap)
 548 {
 549         struct fimc_context *ctx = get_fimc_context(dev);
 550         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
 551         u32 cfg1, cfg2;
 552
 553         DRM_DEBUG_KMS("degree[%d]flip[0x%x]\n", degree, flip);
 554
 555         cfg1 = fimc_read(EXYNOS_MSCTRL);
 556         cfg1 &= ~(EXYNOS_MSCTRL_FLIP_X_MIRROR |
 557                 EXYNOS_MSCTRL_FLIP_Y_MIRROR);
 558
 559         cfg2 = fimc_read(EXYNOS_CITRGFMT);
 560         cfg2 &= ~EXYNOS_CITRGFMT_INROT90_CLOCKWISE;
 561
 562         switch (degree) {
 563         case EXYNOS_DRM_DEGREE_0:
 564                 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
 565                         cfg1 |= EXYNOS_MSCTRL_FLIP_X_MIRROR;
 566                 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
 567                         cfg1 |= EXYNOS_MSCTRL_FLIP_Y_MIRROR;
 568                 break;
 569         case EXYNOS_DRM_DEGREE_90:
 570                 cfg2 |= EXYNOS_CITRGFMT_INROT90_CLOCKWISE;
 571                 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
 572                         cfg1 |= EXYNOS_MSCTRL_FLIP_X_MIRROR;
 573                 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
 574                         cfg1 |= EXYNOS_MSCTRL_FLIP_Y_MIRROR;
 575                 break;
 576         case EXYNOS_DRM_DEGREE_180:
 577                 cfg1 |= (EXYNOS_MSCTRL_FLIP_X_MIRROR |
 578                         EXYNOS_MSCTRL_FLIP_Y_MIRROR);
 579                 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
 580                         cfg1 &= ~EXYNOS_MSCTRL_FLIP_X_MIRROR;
 581                 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
 582                         cfg1 &= ~EXYNOS_MSCTRL_FLIP_Y_MIRROR;
 583                 break;
 584         case EXYNOS_DRM_DEGREE_270:
 585                 cfg1 |= (EXYNOS_MSCTRL_FLIP_X_MIRROR |
 586                         EXYNOS_MSCTRL_FLIP_Y_MIRROR);
 587                 cfg2 |= EXYNOS_CITRGFMT_INROT90_CLOCKWISE;
 588                 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
 589                         cfg1 &= ~EXYNOS_MSCTRL_FLIP_X_MIRROR;
 590                 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
 591                         cfg1 &= ~EXYNOS_MSCTRL_FLIP_Y_MIRROR;
 592                 break;
 593         default:
 594                 dev_err(ippdrv->dev, "inavlid degree value %d.\n", degree);
 595                 return -EINVAL;
 596         }
 597
 598         fimc_write(cfg1, EXYNOS_MSCTRL);
 599         fimc_write(cfg2, EXYNOS_CITRGFMT);
 600         *swap = (cfg2 & EXYNOS_CITRGFMT_INROT90_CLOCKWISE) ? 1 : 0;
 601
 602         return 0;
 603 }
 604
 605 static int fimc_set_window(struct fimc_context *ctx,
 606                 struct drm_exynos_pos *pos, struct drm_exynos_sz *sz)
 607 {
 608         u32 cfg, h1, h2, v1, v2;
 609
 610         /* cropped image */
 611         h1 = pos->x;
 612         h2 = sz->hsize - pos->w - pos->x;
 613         v1 = pos->y;
 614         v2 = sz->vsize - pos->h - pos->y;
 615
 616         DRM_DEBUG_KMS("x[%d]y[%d]w[%d]h[%d]hsize[%d]vsize[%d]\n",
 617                 pos->x, pos->y, pos->w, pos->h, sz->hsize, sz->vsize);
 618         DRM_DEBUG_KMS("h1[%d]h2[%d]v1[%d]v2[%d]\n", h1, h2, v1, v2);
 619
 620         /*
 621          * set window offset 1, 2 size
 622          * check figure 43-21 in user manual
 623          */
 624         cfg = fimc_read(EXYNOS_CIWDOFST);
 625         cfg &= ~(EXYNOS_CIWDOFST_WINHOROFST_MASK |
 626                 EXYNOS_CIWDOFST_WINVEROFST_MASK);
 627         cfg |= (EXYNOS_CIWDOFST_WINHOROFST(h1) |
 628                 EXYNOS_CIWDOFST_WINVEROFST(v1));
 629         cfg |= EXYNOS_CIWDOFST_WINOFSEN;
 630         fimc_write(cfg, EXYNOS_CIWDOFST);
 631
 632         cfg = (EXYNOS_CIWDOFST2_WINHOROFST2(h2) |
 633                 EXYNOS_CIWDOFST2_WINVEROFST2(v2));
 634         fimc_write(cfg, EXYNOS_CIWDOFST2);
 635
 636         return 0;
 637 }
 638
 639 static int fimc_src_set_size(struct device *dev, int swap,
 640                 struct drm_exynos_pos *pos, struct drm_exynos_sz *sz)
 641 {
 642         struct fimc_context *ctx = get_fimc_context(dev);
 643         struct drm_exynos_pos img_pos = *pos;
 644         struct drm_exynos_sz img_sz = *sz;
 645         u32 cfg;
 646
 647         DRM_DEBUG_KMS("swap[%d]hsize[%d]vsize[%d]\n",
 648                 swap, sz->hsize, sz->vsize);
 649
 650         /* original size */
 651         cfg = (EXYNOS_ORGISIZE_HORIZONTAL(img_sz.hsize) |
 652                 EXYNOS_ORGISIZE_VERTICAL(img_sz.vsize));
 653
 654         fimc_write(cfg, EXYNOS_ORGISIZE);
 655
 656         DRM_DEBUG_KMS("x[%d]y[%d]w[%d]h[%d]\n", pos->x, pos->y, pos->w, pos->h);
 657
 658         if (swap) {
 659                 img_pos.w = pos->h;
 660                 img_pos.h = pos->w;
 661                 img_sz.hsize = sz->vsize;
 662                 img_sz.vsize = sz->hsize;
 663         }
 664
 665         /* set input DMA image size */
 666         cfg = fimc_read(EXYNOS_CIREAL_ISIZE);
 667         cfg &= ~(EXYNOS_CIREAL_ISIZE_HEIGHT_MASK |
 668                 EXYNOS_CIREAL_ISIZE_WIDTH_MASK);
 669         cfg |= (EXYNOS_CIREAL_ISIZE_WIDTH(img_pos.w) |
 670                 EXYNOS_CIREAL_ISIZE_HEIGHT(img_pos.h));
 671         fimc_write(cfg, EXYNOS_CIREAL_ISIZE);
 672
 673         /*
 674          * set input FIFO image size
 675          * for now, we support only ITU601 8 bit mode
 676          */
 677         cfg = (EXYNOS_CISRCFMT_ITU601_8BIT |
 678                 EXYNOS_CISRCFMT_SOURCEHSIZE(img_sz.hsize) |
 679                 EXYNOS_CISRCFMT_SOURCEVSIZE(img_sz.vsize));
 680         fimc_write(cfg, EXYNOS_CISRCFMT);
 681
 682         /* offset Y(RGB), Cb, Cr */
 683         cfg = (EXYNOS_CIIYOFF_HORIZONTAL(img_pos.x) |
 684                 EXYNOS_CIIYOFF_VERTICAL(img_pos.y));
 685         fimc_write(cfg, EXYNOS_CIIYOFF);
 686         cfg = (EXYNOS_CIICBOFF_HORIZONTAL(img_pos.x) |
 687                 EXYNOS_CIICBOFF_VERTICAL(img_pos.y));
 688         fimc_write(cfg, EXYNOS_CIICBOFF);
 689         cfg = (EXYNOS_CIICROFF_HORIZONTAL(img_pos.x) |
 690                 EXYNOS_CIICROFF_VERTICAL(img_pos.y));
 691         fimc_write(cfg, EXYNOS_CIICROFF);
 692
 693         return fimc_set_window(ctx, &img_pos, &img_sz);
 694 }
 695
 696 static int fimc_src_set_addr(struct device *dev,
 697                 struct drm_exynos_ipp_buf_info *buf_info, u32 buf_id,
 698                 enum drm_exynos_ipp_buf_type buf_type)
 699 {
 700         struct fimc_context *ctx = get_fimc_context(dev);
 701         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
 702         struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
 703         struct drm_exynos_ipp_property *property;
 704         struct drm_exynos_ipp_config *config;
 705
 706         if (!c_node) {
 707                 DRM_ERROR("failed to get c_node.\n");
 708                 return -EINVAL;
 709         }
 710
 711         property = &c_node->property;
 712
 713         DRM_DEBUG_KMS("prop_id[%d]buf_id[%d]buf_type[%d]\n",
 714                 property->prop_id, buf_id, buf_type);
 715
 716         if (buf_id > FIMC_MAX_SRC) {
 717                 dev_info(ippdrv->dev, "inavlid buf_id %d.\n", buf_id);
 718                 return -ENOMEM;
 719         }
 720
 721         /* address register set */
 722         switch (buf_type) {
 723         case IPP_BUF_ENQUEUE:
 724                 config = &property->config[EXYNOS_DRM_OPS_SRC];
 725                 fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_Y],
 726                         EXYNOS_CIIYSA(buf_id));
 727
 728                 if (config->fmt == DRM_FORMAT_YVU420) {
 729                         fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_CR],
 730                                 EXYNOS_CIICBSA(buf_id));
 731                         fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_CB],
 732                                 EXYNOS_CIICRSA(buf_id));
 733                 } else {
 734                         fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_CB],
 735                                 EXYNOS_CIICBSA(buf_id));
 736                         fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_CR],
 737                                 EXYNOS_CIICRSA(buf_id));
 738                 }
 739                 break;
 740         case IPP_BUF_DEQUEUE:
 741                 fimc_write(0x0, EXYNOS_CIIYSA(buf_id));
 742                 fimc_write(0x0, EXYNOS_CIICBSA(buf_id));
 743                 fimc_write(0x0, EXYNOS_CIICRSA(buf_id));
 744                 break;
 745         default:
 746                 /* bypass */
 747                 break;
 748         }
 749
 750         return 0;
 751 }
 752
 753 static struct exynos_drm_ipp_ops fimc_src_ops = {
 754         .set_fmt = fimc_src_set_fmt,
 755         .set_transf = fimc_src_set_transf,
 756         .set_size = fimc_src_set_size,
 757         .set_addr = fimc_src_set_addr,
 758 };
 759
 760 static int fimc_dst_set_fmt_order(struct fimc_context *ctx, u32 fmt)
 761 {
 762         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
 763         u32 cfg;
 764
 765         DRM_DEBUG_KMS("fmt[0x%x]\n", fmt);
 766
 767         /* RGB */
 768         cfg = fimc_read(EXYNOS_CISCCTRL);
 769         cfg &= ~EXYNOS_CISCCTRL_OUTRGB_FMT_RGB_MASK;
 770
 771         switch (fmt) {
 772         case DRM_FORMAT_RGB565:
 773                 cfg |= EXYNOS_CISCCTRL_OUTRGB_FMT_RGB565;
 774                 fimc_write(cfg, EXYNOS_CISCCTRL);
 775                 return 0;
 776         case DRM_FORMAT_RGB888:
 777                 cfg |= EXYNOS_CISCCTRL_OUTRGB_FMT_RGB888;
 778                 fimc_write(cfg, EXYNOS_CISCCTRL);
 779                 return 0;
 780         case DRM_FORMAT_XRGB8888:
 781                 cfg |= (EXYNOS_CISCCTRL_OUTRGB_FMT_RGB888 |
 782                         EXYNOS_CISCCTRL_EXTRGB_EXTENSION);
 783                 fimc_write(cfg, EXYNOS_CISCCTRL);
 784                 break;
 785         default:
 786                 /* bypass */
 787                 break;
 788         }
 789
 790         /* YUV */
 791         cfg = fimc_read(EXYNOS_CIOCTRL);
 792         cfg &= ~(EXYNOS_CIOCTRL_ORDER2P_MASK |
 793                 EXYNOS_CIOCTRL_ORDER422_MASK |
 794                 EXYNOS_CIOCTRL_YCBCR_PLANE_MASK);
 795
 796         switch (fmt) {
 797         case DRM_FORMAT_XRGB8888:
 798                 cfg |= EXYNOS_CIOCTRL_ALPHA_OUT;
 799                 break;
 800         case DRM_FORMAT_YUYV:
 801                 cfg |= EXYNOS_CIOCTRL_ORDER422_YCBYCR;
 802                 break;
 803         case DRM_FORMAT_YVYU:
 804                 cfg |= EXYNOS_CIOCTRL_ORDER422_YCRYCB;
 805                 break;
 806         case DRM_FORMAT_UYVY:
 807                 cfg |= EXYNOS_CIOCTRL_ORDER422_CBYCRY;
 808                 break;
 809         case DRM_FORMAT_VYUY:
 810                 cfg |= EXYNOS_CIOCTRL_ORDER422_CRYCBY;
 811                 break;
 812         case DRM_FORMAT_NV21:
 813         case DRM_FORMAT_NV61:
 814                 cfg |= EXYNOS_CIOCTRL_ORDER2P_LSB_CRCB;
 815                 cfg |= EXYNOS_CIOCTRL_YCBCR_2PLANE;
 816                 break;
 817         case DRM_FORMAT_YUV422:
 818         case DRM_FORMAT_YUV420:
 819         case DRM_FORMAT_YVU420:
 820                 cfg |= EXYNOS_CIOCTRL_YCBCR_3PLANE;
 821                 break;
 822         case DRM_FORMAT_NV12:
 823         case DRM_FORMAT_NV12MT:
 824         case DRM_FORMAT_NV16:
 825                 cfg |= EXYNOS_CIOCTRL_ORDER2P_LSB_CBCR;
 826                 cfg |= EXYNOS_CIOCTRL_YCBCR_2PLANE;
 827                 break;
 828         default:
 829                 dev_err(ippdrv->dev, "inavlid target yuv order 0x%x.\n", fmt);
 830                 return -EINVAL;
 831         }
 832
 833         fimc_write(cfg, EXYNOS_CIOCTRL);
 834
 835         return 0;
 836 }
 837
 838 static int fimc_dst_set_fmt(struct device *dev, u32 fmt)
 839 {
 840         struct fimc_context *ctx = get_fimc_context(dev);
 841         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
 842         u32 cfg;
 843
 844         DRM_DEBUG_KMS("fmt[0x%x]\n", fmt);
 845
 846         cfg = fimc_read(EXYNOS_CIEXTEN);
 847
 848         if (fmt == DRM_FORMAT_AYUV) {
 849                 cfg |= EXYNOS_CIEXTEN_YUV444_OUT;
 850                 fimc_write(cfg, EXYNOS_CIEXTEN);
 851         } else {
 852                 cfg &= ~EXYNOS_CIEXTEN_YUV444_OUT;
 853                 fimc_write(cfg, EXYNOS_CIEXTEN);
 854
 855                 cfg = fimc_read(EXYNOS_CITRGFMT);
 856                 cfg &= ~EXYNOS_CITRGFMT_OUTFORMAT_MASK;
 857
 858                 switch (fmt) {
 859                 case DRM_FORMAT_RGB565:
 860                 case DRM_FORMAT_RGB888:
 861                 case DRM_FORMAT_XRGB8888:
 862                         cfg |= EXYNOS_CITRGFMT_OUTFORMAT_RGB;
 863                         break;
 864                 case DRM_FORMAT_YUYV:
 865                 case DRM_FORMAT_YVYU:
 866                 case DRM_FORMAT_UYVY:
 867                 case DRM_FORMAT_VYUY:
 868                         cfg |= EXYNOS_CITRGFMT_OUTFORMAT_YCBCR422_1PLANE;
 869                         break;
 870                 case DRM_FORMAT_NV16:
 871                 case DRM_FORMAT_NV61:
 872                 case DRM_FORMAT_YUV422:
 873                         cfg |= EXYNOS_CITRGFMT_OUTFORMAT_YCBCR422;
 874                         break;
 875                 case DRM_FORMAT_YUV420:
 876                 case DRM_FORMAT_YVU420:
 877                 case DRM_FORMAT_NV12:
 878                 case DRM_FORMAT_NV12MT:
 879                 case DRM_FORMAT_NV21:
 880                         cfg |= EXYNOS_CITRGFMT_OUTFORMAT_YCBCR420;
 881                         break;
 882                 default:
 883                         dev_err(ippdrv->dev, "inavlid target format 0x%x.\n",
 884                                 fmt);
 885                         return -EINVAL;
 886                 }
 887
 888                 fimc_write(cfg, EXYNOS_CITRGFMT);
 889         }
 890
 891         cfg = fimc_read(EXYNOS_CIDMAPARAM);
 892         cfg &= ~EXYNOS_CIDMAPARAM_W_MODE_MASK;
 893
 894         if (fmt == DRM_FORMAT_NV12MT)
 895                 cfg |= EXYNOS_CIDMAPARAM_W_MODE_64X32;
 896         else
 897                 cfg |= EXYNOS_CIDMAPARAM_W_MODE_LINEAR;
 898
 899         fimc_write(cfg, EXYNOS_CIDMAPARAM);
 900
 901         return fimc_dst_set_fmt_order(ctx, fmt);
 902 }
 903
 904 static int fimc_dst_set_transf(struct device *dev,
 905                 enum drm_exynos_degree degree,
 906                 enum drm_exynos_flip flip, bool *swap)
 907 {
 908         struct fimc_context *ctx = get_fimc_context(dev);
 909         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
 910         u32 cfg;
 911
 912         DRM_DEBUG_KMS("degree[%d]flip[0x%x]\n", degree, flip);
 913
 914         cfg = fimc_read(EXYNOS_CITRGFMT);
 915         cfg &= ~EXYNOS_CITRGFMT_FLIP_MASK;
 916         cfg &= ~EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE;
 917
 918         switch (degree) {
 919         case EXYNOS_DRM_DEGREE_0:
 920                 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
 921                         cfg |= EXYNOS_CITRGFMT_FLIP_X_MIRROR;
 922                 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
 923                         cfg |= EXYNOS_CITRGFMT_FLIP_Y_MIRROR;
 924                 break;
 925         case EXYNOS_DRM_DEGREE_90:
 926                 cfg |= EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE;
 927                 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
 928                         cfg |= EXYNOS_CITRGFMT_FLIP_X_MIRROR;
 929                 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
 930                         cfg |= EXYNOS_CITRGFMT_FLIP_Y_MIRROR;
 931                 break;
 932         case EXYNOS_DRM_DEGREE_180:
 933                 cfg |= (EXYNOS_CITRGFMT_FLIP_X_MIRROR |
 934                         EXYNOS_CITRGFMT_FLIP_Y_MIRROR);
 935                 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
 936                         cfg &= ~EXYNOS_CITRGFMT_FLIP_X_MIRROR;
 937                 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
 938                         cfg &= ~EXYNOS_CITRGFMT_FLIP_Y_MIRROR;
 939                 break;
 940         case EXYNOS_DRM_DEGREE_270:
 941                 cfg |= (EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE |
 942                         EXYNOS_CITRGFMT_FLIP_X_MIRROR |
 943                         EXYNOS_CITRGFMT_FLIP_Y_MIRROR);
 944                 if (flip & EXYNOS_DRM_FLIP_VERTICAL)
 945                         cfg &= ~EXYNOS_CITRGFMT_FLIP_X_MIRROR;
 946                 if (flip & EXYNOS_DRM_FLIP_HORIZONTAL)
 947                         cfg &= ~EXYNOS_CITRGFMT_FLIP_Y_MIRROR;
 948                 break;
 949         default:
 950                 dev_err(ippdrv->dev, "inavlid degree value %d.\n", degree);
 951                 return -EINVAL;
 952         }
 953
 954         fimc_write(cfg, EXYNOS_CITRGFMT);
 955         *swap = (cfg & EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE) ? 1 : 0;
 956
 957         return 0;
 958 }
 959
 960 static int fimc_set_prescaler(struct fimc_context *ctx, struct fimc_scaler *sc,
 961                 struct drm_exynos_pos *src, struct drm_exynos_pos *dst)
 962 {
 963         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
 964         u32 cfg, cfg_ext, shfactor;
 965         u32 pre_dst_width, pre_dst_height;
 966         u32 hfactor, vfactor;
 967         int ret = 0;
 968         u32 src_w, src_h, dst_w, dst_h;
 969
 970         cfg_ext = fimc_read(EXYNOS_CITRGFMT);
 971         if (cfg_ext & EXYNOS_CITRGFMT_INROT90_CLOCKWISE) {
 972                 src_w = src->h;
 973                 src_h = src->w;
 974         } else {
 975                 src_w = src->w;
 976                 src_h = src->h;
 977         }
 978
 979         if (cfg_ext & EXYNOS_CITRGFMT_OUTROT90_CLOCKWISE) {
 980                 dst_w = dst->h;
 981                 dst_h = dst->w;
 982         } else {
 983                 dst_w = dst->w;
 984                 dst_h = dst->h;
 985         }
 986
 987         /* fimc_ippdrv_check_property assures that dividers are not null */
 988         hfactor = fls(src_w / dst_w / 2);
 989         if (hfactor > FIMC_SHFACTOR / 2) {
 990                 dev_err(ippdrv->dev, "failed to get ratio horizontal.\n");
 991                 return -EINVAL;
 992         }
 993
 994         vfactor = fls(src_h / dst_h / 2);
 995         if (vfactor > FIMC_SHFACTOR / 2) {
 996                 dev_err(ippdrv->dev, "failed to get ratio vertical.\n");
 997                 return -EINVAL;
 998         }
 999
1000         pre_dst_width = src_w >> hfactor;
1001         pre_dst_height = src_h >> vfactor;
1002         DRM_DEBUG_KMS("pre_dst_width[%d]pre_dst_height[%d]\n",
1003                 pre_dst_width, pre_dst_height);
1004         DRM_DEBUG_KMS("hfactor[%d]vfactor[%d]\n", hfactor, vfactor);
1005
1006         sc->hratio = (src_w << 14) / (dst_w << hfactor);
1007         sc->vratio = (src_h << 14) / (dst_h << vfactor);
1008         sc->up_h = (dst_w >= src_w) ? true : false;
1009         sc->up_v = (dst_h >= src_h) ? true : false;
1010         DRM_DEBUG_KMS("hratio[%d]vratio[%d]up_h[%d]up_v[%d]\n",
1011                 sc->hratio, sc->vratio, sc->up_h, sc->up_v);
1012
1013         shfactor = FIMC_SHFACTOR - (hfactor + vfactor);
1014         DRM_DEBUG_KMS("shfactor[%d]\n", shfactor);
1015
1016         cfg = (EXYNOS_CISCPRERATIO_SHFACTOR(shfactor) |
1017                 EXYNOS_CISCPRERATIO_PREHORRATIO(1 << hfactor) |
1018                 EXYNOS_CISCPRERATIO_PREVERRATIO(1 << vfactor));
1019         fimc_write(cfg, EXYNOS_CISCPRERATIO);
1020
1021         cfg = (EXYNOS_CISCPREDST_PREDSTWIDTH(pre_dst_width) |
1022                 EXYNOS_CISCPREDST_PREDSTHEIGHT(pre_dst_height));
1023         fimc_write(cfg, EXYNOS_CISCPREDST);
1024
1025         return ret;
1026 }
1027
1028 static void fimc_set_scaler(struct fimc_context *ctx, struct fimc_scaler *sc)
1029 {
1030         u32 cfg, cfg_ext;
1031
1032         DRM_DEBUG_KMS("range[%d]bypass[%d]up_h[%d]up_v[%d]\n",
1033                 sc->range, sc->bypass, sc->up_h, sc->up_v);
1034         DRM_DEBUG_KMS("hratio[%d]vratio[%d]\n",
1035                 sc->hratio, sc->vratio);
1036
1037         cfg = fimc_read(EXYNOS_CISCCTRL);
1038         cfg &= ~(EXYNOS_CISCCTRL_SCALERBYPASS |
1039                 EXYNOS_CISCCTRL_SCALEUP_H | EXYNOS_CISCCTRL_SCALEUP_V |
1040                 EXYNOS_CISCCTRL_MAIN_V_RATIO_MASK |
1041                 EXYNOS_CISCCTRL_MAIN_H_RATIO_MASK |
1042                 EXYNOS_CISCCTRL_CSCR2Y_WIDE |
1043                 EXYNOS_CISCCTRL_CSCY2R_WIDE);
1044
1045         if (sc->range)
1046                 cfg |= (EXYNOS_CISCCTRL_CSCR2Y_WIDE |
1047                         EXYNOS_CISCCTRL_CSCY2R_WIDE);
1048         if (sc->bypass)
1049                 cfg |= EXYNOS_CISCCTRL_SCALERBYPASS;
1050         if (sc->up_h)
1051                 cfg |= EXYNOS_CISCCTRL_SCALEUP_H;
1052         if (sc->up_v)
1053                 cfg |= EXYNOS_CISCCTRL_SCALEUP_V;
1054
1055         cfg |= (EXYNOS_CISCCTRL_MAINHORRATIO((sc->hratio >> 6)) |
1056                 EXYNOS_CISCCTRL_MAINVERRATIO((sc->vratio >> 6)));
1057         fimc_write(cfg, EXYNOS_CISCCTRL);
1058
1059         cfg_ext = fimc_read(EXYNOS_CIEXTEN);
1060         cfg_ext &= ~EXYNOS_CIEXTEN_MAINHORRATIO_EXT_MASK;
1061         cfg_ext &= ~EXYNOS_CIEXTEN_MAINVERRATIO_EXT_MASK;
1062         cfg_ext |= (EXYNOS_CIEXTEN_MAINHORRATIO_EXT(sc->hratio) |
1063                 EXYNOS_CIEXTEN_MAINVERRATIO_EXT(sc->vratio));
1064         fimc_write(cfg_ext, EXYNOS_CIEXTEN);
1065 }
1066
1067 static int fimc_dst_set_size(struct device *dev, int swap,
1068                 struct drm_exynos_pos *pos, struct drm_exynos_sz *sz)
1069 {
1070         struct fimc_context *ctx = get_fimc_context(dev);
1071         struct drm_exynos_pos img_pos = *pos;
1072         struct drm_exynos_sz img_sz = *sz;
1073         u32 cfg;
1074
1075         DRM_DEBUG_KMS("swap[%d]hsize[%d]vsize[%d]\n",
1076                 swap, sz->hsize, sz->vsize);
1077
1078         /* original size */
1079         cfg = (EXYNOS_ORGOSIZE_HORIZONTAL(img_sz.hsize) |
1080                 EXYNOS_ORGOSIZE_VERTICAL(img_sz.vsize));
1081
1082         fimc_write(cfg, EXYNOS_ORGOSIZE);
1083
1084         DRM_DEBUG_KMS("x[%d]y[%d]w[%d]h[%d]\n", pos->x, pos->y, pos->w, pos->h);
1085
1086         /* CSC ITU */
1087         cfg = fimc_read(EXYNOS_CIGCTRL);
1088         cfg &= ~EXYNOS_CIGCTRL_CSC_MASK;
1089
1090         if (sz->hsize >= FIMC_WIDTH_ITU_709)
1091                 cfg |= EXYNOS_CIGCTRL_CSC_ITU709;
1092         else
1093                 cfg |= EXYNOS_CIGCTRL_CSC_ITU601;
1094
1095         fimc_write(cfg, EXYNOS_CIGCTRL);
1096
1097         if (swap) {
1098                 img_pos.w = pos->h;
1099                 img_pos.h = pos->w;
1100                 img_sz.hsize = sz->vsize;
1101                 img_sz.vsize = sz->hsize;
1102         }
1103
1104         /* target image size */
1105         cfg = fimc_read(EXYNOS_CITRGFMT);
1106         cfg &= ~(EXYNOS_CITRGFMT_TARGETH_MASK |
1107                 EXYNOS_CITRGFMT_TARGETV_MASK);
1108         cfg |= (EXYNOS_CITRGFMT_TARGETHSIZE(img_pos.w) |
1109                 EXYNOS_CITRGFMT_TARGETVSIZE(img_pos.h));
1110         fimc_write(cfg, EXYNOS_CITRGFMT);
1111
1112         /* target area */
1113         cfg = EXYNOS_CITAREA_TARGET_AREA(img_pos.w * img_pos.h);
1114         fimc_write(cfg, EXYNOS_CITAREA);
1115
1116         /* offset Y(RGB), Cb, Cr */
1117         cfg = (EXYNOS_CIOYOFF_HORIZONTAL(img_pos.x) |
1118                 EXYNOS_CIOYOFF_VERTICAL(img_pos.y));
1119         fimc_write(cfg, EXYNOS_CIOYOFF);
1120         cfg = (EXYNOS_CIOCBOFF_HORIZONTAL(img_pos.x) |
1121                 EXYNOS_CIOCBOFF_VERTICAL(img_pos.y));
1122         fimc_write(cfg, EXYNOS_CIOCBOFF);
1123         cfg = (EXYNOS_CIOCROFF_HORIZONTAL(img_pos.x) |
1124                 EXYNOS_CIOCROFF_VERTICAL(img_pos.y));
1125         fimc_write(cfg, EXYNOS_CIOCROFF);
1126
1127         return 0;
1128 }
1129
1130 static int fimc_dst_get_buf_seq(struct fimc_context *ctx)
1131 {
1132         u32 cfg, i, buf_num = 0;
1133         u32 mask = 0x00000001;
1134
1135         cfg = fimc_read(EXYNOS_CIFCNTSEQ);
1136
1137         for (i = 0; i < FIMC_REG_SZ; i++)
1138                 if (cfg & (mask << i))
1139                         buf_num++;
1140
1141         DRM_DEBUG_KMS("buf_num[%d]\n", buf_num);
1142
1143         return buf_num;
1144 }
1145
1146 static int fimc_dst_set_buf_seq(struct fimc_context *ctx, u32 buf_id,
1147                 enum drm_exynos_ipp_buf_type buf_type)
1148 {
1149         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1150         bool enable;
1151         u32 cfg;
1152         u32 mask = 0x00000001 << buf_id;
1153         int ret = 0;
1154
1155         DRM_DEBUG_KMS("buf_id[%d]buf_type[%d]\n", buf_id, buf_type);
1156
1157         mutex_lock(&ctx->lock);
1158
1159         /* mask register set */
1160         cfg = fimc_read(EXYNOS_CIFCNTSEQ);
1161
1162         switch (buf_type) {
1163         case IPP_BUF_ENQUEUE:
1164                 enable = true;
1165                 break;
1166         case IPP_BUF_DEQUEUE:
1167                 enable = false;
1168                 break;
1169         default:
1170                 dev_err(ippdrv->dev, "invalid buf ctrl parameter.\n");
1171                 ret =  -EINVAL;
1172                 goto err_unlock;
1173         }
1174
1175         /* sequence id */
1176         cfg &= ~mask;
1177         cfg |= (enable << buf_id);
1178         fimc_write(cfg, EXYNOS_CIFCNTSEQ);
1179
1180         /* interrupt enable */
1181         if (buf_type == IPP_BUF_ENQUEUE &&
1182             fimc_dst_get_buf_seq(ctx) >= FIMC_BUF_START)
1183                 fimc_handle_irq(ctx, true, false, true);
1184
1185         /* interrupt disable */
1186         if (buf_type == IPP_BUF_DEQUEUE &&
1187             fimc_dst_get_buf_seq(ctx) <= FIMC_BUF_STOP)
1188                 fimc_handle_irq(ctx, false, false, true);
1189
1190 err_unlock:
1191         mutex_unlock(&ctx->lock);
1192         return ret;
1193 }
1194
1195 static int fimc_dst_set_addr(struct device *dev,
1196                 struct drm_exynos_ipp_buf_info *buf_info, u32 buf_id,
1197                 enum drm_exynos_ipp_buf_type buf_type)
1198 {
1199         struct fimc_context *ctx = get_fimc_context(dev);
1200         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1201         struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
1202         struct drm_exynos_ipp_property *property;
1203         struct drm_exynos_ipp_config *config;
1204
1205         if (!c_node) {
1206                 DRM_ERROR("failed to get c_node.\n");
1207                 return -EINVAL;
1208         }
1209
1210         property = &c_node->property;
1211
1212         DRM_DEBUG_KMS("prop_id[%d]buf_id[%d]buf_type[%d]\n",
1213                 property->prop_id, buf_id, buf_type);
1214
1215         if (buf_id > FIMC_MAX_DST) {
1216                 dev_info(ippdrv->dev, "inavlid buf_id %d.\n", buf_id);
1217                 return -ENOMEM;
1218         }
1219
1220         /* address register set */
1221         switch (buf_type) {
1222         case IPP_BUF_ENQUEUE:
1223                 config = &property->config[EXYNOS_DRM_OPS_DST];
1224
1225                 fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_Y],
1226                         EXYNOS_CIOYSA(buf_id));
1227
1228                 if (config->fmt == DRM_FORMAT_YVU420) {
1229                         fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_CR],
1230                                 EXYNOS_CIOCBSA(buf_id));
1231                         fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_CB],
1232                                 EXYNOS_CIOCRSA(buf_id));
1233                 } else {
1234                         fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_CB],
1235                                 EXYNOS_CIOCBSA(buf_id));
1236                         fimc_write(buf_info->base[EXYNOS_DRM_PLANAR_CR],
1237                                 EXYNOS_CIOCRSA(buf_id));
1238                 }
1239                 break;
1240         case IPP_BUF_DEQUEUE:
1241                 fimc_write(0x0, EXYNOS_CIOYSA(buf_id));
1242                 fimc_write(0x0, EXYNOS_CIOCBSA(buf_id));
1243                 fimc_write(0x0, EXYNOS_CIOCRSA(buf_id));
1244                 break;
1245         default:
1246                 /* bypass */
1247                 break;
1248         }
1249
1250         return fimc_dst_set_buf_seq(ctx, buf_id, buf_type);
1251 }
1252
1253 static struct exynos_drm_ipp_ops fimc_dst_ops = {
1254         .set_fmt = fimc_dst_set_fmt,
1255         .set_transf = fimc_dst_set_transf,
1256         .set_size = fimc_dst_set_size,
1257         .set_addr = fimc_dst_set_addr,
1258 };
1259
1260 static int fimc_clk_ctrl(struct fimc_context *ctx, bool enable)
1261 {
1262         DRM_DEBUG_KMS("enable[%d]\n", enable);
1263
1264         if (enable) {
1265                 clk_prepare_enable(ctx->clocks[FIMC_CLK_GATE]);
1266                 clk_prepare_enable(ctx->clocks[FIMC_CLK_WB_A]);
1267                 ctx->suspended = false;
1268         } else {
1269                 clk_disable_unprepare(ctx->clocks[FIMC_CLK_GATE]);
1270                 clk_disable_unprepare(ctx->clocks[FIMC_CLK_WB_A]);
1271                 ctx->suspended = true;
1272         }
1273
1274         return 0;
1275 }
1276
1277 static irqreturn_t fimc_irq_handler(int irq, void *dev_id)
1278 {
1279         struct fimc_context *ctx = dev_id;
1280         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1281         struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
1282         struct drm_exynos_ipp_event_work *event_work =
1283                 c_node->event_work;
1284         int buf_id;
1285
1286         DRM_DEBUG_KMS("fimc id[%d]\n", ctx->id);
1287
1288         fimc_clear_irq(ctx);
1289         if (fimc_check_ovf(ctx))
1290                 return IRQ_NONE;
1291
1292         if (!fimc_check_frame_end(ctx))
1293                 return IRQ_NONE;
1294
1295         buf_id = fimc_get_buf_id(ctx);
1296         if (buf_id < 0)
1297                 return IRQ_HANDLED;
1298
1299         DRM_DEBUG_KMS("buf_id[%d]\n", buf_id);
1300
1301         if (fimc_dst_set_buf_seq(ctx, buf_id, IPP_BUF_DEQUEUE) < 0) {
1302                 DRM_ERROR("failed to dequeue.\n");
1303                 return IRQ_HANDLED;
1304         }
1305
1306         event_work->ippdrv = ippdrv;
1307         event_work->buf_id[EXYNOS_DRM_OPS_DST] = buf_id;
1308         queue_work(ippdrv->event_workq, (struct work_struct *)event_work);
1309
1310         return IRQ_HANDLED;
1311 }
1312
1313 static int fimc_init_prop_list(struct exynos_drm_ippdrv *ippdrv)
1314 {
1315         struct drm_exynos_ipp_prop_list *prop_list = &ippdrv->prop_list;
1316
1317         prop_list->version = 1;
1318         prop_list->writeback = 1;
1319         prop_list->refresh_min = FIMC_REFRESH_MIN;
1320         prop_list->refresh_max = FIMC_REFRESH_MAX;
1321         prop_list->flip = (1 << EXYNOS_DRM_FLIP_NONE) |
1322                                 (1 << EXYNOS_DRM_FLIP_VERTICAL) |
1323                                 (1 << EXYNOS_DRM_FLIP_HORIZONTAL);
1324         prop_list->degree = (1 << EXYNOS_DRM_DEGREE_0) |
1325                                 (1 << EXYNOS_DRM_DEGREE_90) |
1326                                 (1 << EXYNOS_DRM_DEGREE_180) |
1327                                 (1 << EXYNOS_DRM_DEGREE_270);
1328         prop_list->csc = 1;
1329         prop_list->crop = 1;
1330         prop_list->crop_max.hsize = FIMC_CROP_MAX;
1331         prop_list->crop_max.vsize = FIMC_CROP_MAX;
1332         prop_list->crop_min.hsize = FIMC_CROP_MIN;
1333         prop_list->crop_min.vsize = FIMC_CROP_MIN;
1334         prop_list->scale = 1;
1335         prop_list->scale_max.hsize = FIMC_SCALE_MAX;
1336         prop_list->scale_max.vsize = FIMC_SCALE_MAX;
1337         prop_list->scale_min.hsize = FIMC_SCALE_MIN;
1338         prop_list->scale_min.vsize = FIMC_SCALE_MIN;
1339
1340         return 0;
1341 }
1342
1343 static inline bool fimc_check_drm_flip(enum drm_exynos_flip flip)
1344 {
1345         switch (flip) {
1346         case EXYNOS_DRM_FLIP_NONE:
1347         case EXYNOS_DRM_FLIP_VERTICAL:
1348         case EXYNOS_DRM_FLIP_HORIZONTAL:
1349         case EXYNOS_DRM_FLIP_BOTH:
1350                 return true;
1351         default:
1352                 DRM_DEBUG_KMS("invalid flip\n");
1353                 return false;
1354         }
1355 }
1356
1357 static int fimc_ippdrv_check_property(struct device *dev,
1358                 struct drm_exynos_ipp_property *property)
1359 {
1360         struct fimc_context *ctx = get_fimc_context(dev);
1361         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1362         struct drm_exynos_ipp_prop_list *pp = &ippdrv->prop_list;
1363         struct drm_exynos_ipp_config *config;
1364         struct drm_exynos_pos *pos;
1365         struct drm_exynos_sz *sz;
1366         bool swap;
1367         int i;
1368
1369         for_each_ipp_ops(i) {
1370                 if ((i == EXYNOS_DRM_OPS_SRC) &&
1371                         (property->cmd == IPP_CMD_WB))
1372                         continue;
1373
1374                 config = &property->config[i];
1375                 pos = &config->pos;
1376                 sz = &config->sz;
1377
1378                 /* check for flip */
1379                 if (!fimc_check_drm_flip(config->flip)) {
1380                         DRM_ERROR("invalid flip.\n");
1381                         goto err_property;
1382                 }
1383
1384                 /* check for degree */
1385                 switch (config->degree) {
1386                 case EXYNOS_DRM_DEGREE_90:
1387                 case EXYNOS_DRM_DEGREE_270:
1388                         swap = true;
1389                         break;
1390                 case EXYNOS_DRM_DEGREE_0:
1391                 case EXYNOS_DRM_DEGREE_180:
1392                         swap = false;
1393                         break;
1394                 default:
1395                         DRM_ERROR("invalid degree.\n");
1396                         goto err_property;
1397                 }
1398
1399                 /* check for buffer bound */
1400                 if ((pos->x + pos->w > sz->hsize) ||
1401                         (pos->y + pos->h > sz->vsize)) {
1402                         DRM_ERROR("out of buf bound.\n");
1403                         goto err_property;
1404                 }
1405
1406                 /* check for crop */
1407                 if ((i == EXYNOS_DRM_OPS_SRC) && (pp->crop)) {
1408                         if (swap) {
1409                                 if ((pos->h < pp->crop_min.hsize) ||
1410                                         (sz->vsize > pp->crop_max.hsize) ||
1411                                         (pos->w < pp->crop_min.vsize) ||
1412                                         (sz->hsize > pp->crop_max.vsize)) {
1413                                         DRM_ERROR("out of crop size.\n");
1414                                         goto err_property;
1415                                 }
1416                         } else {
1417                                 if ((pos->w < pp->crop_min.hsize) ||
1418                                         (sz->hsize > pp->crop_max.hsize) ||
1419                                         (pos->h < pp->crop_min.vsize) ||
1420                                         (sz->vsize > pp->crop_max.vsize)) {
1421                                         DRM_ERROR("out of crop size.\n");
1422                                         goto err_property;
1423                                 }
1424                         }
1425                 }
1426
1427                 /* check for scale */
1428                 if ((i == EXYNOS_DRM_OPS_DST) && (pp->scale)) {
1429                         if (swap) {
1430                                 if ((pos->h < pp->scale_min.hsize) ||
1431                                         (sz->vsize > pp->scale_max.hsize) ||
1432                                         (pos->w < pp->scale_min.vsize) ||
1433                                         (sz->hsize > pp->scale_max.vsize)) {
1434                                         DRM_ERROR("out of scale size.\n");
1435                                         goto err_property;
1436                                 }
1437                         } else {
1438                                 if ((pos->w < pp->scale_min.hsize) ||
1439                                         (sz->hsize > pp->scale_max.hsize) ||
1440                                         (pos->h < pp->scale_min.vsize) ||
1441                                         (sz->vsize > pp->scale_max.vsize)) {
1442                                         DRM_ERROR("out of scale size.\n");
1443                                         goto err_property;
1444                                 }
1445                         }
1446                 }
1447         }
1448
1449         return 0;
1450
1451 err_property:
1452         for_each_ipp_ops(i) {
1453                 if ((i == EXYNOS_DRM_OPS_SRC) &&
1454                         (property->cmd == IPP_CMD_WB))
1455                         continue;
1456
1457                 config = &property->config[i];
1458                 pos = &config->pos;
1459                 sz = &config->sz;
1460
1461                 DRM_ERROR("[%s]f[%d]r[%d]pos[%d %d %d %d]sz[%d %d]\n",
1462                         i ? "dst" : "src", config->flip, config->degree,
1463                         pos->x, pos->y, pos->w, pos->h,
1464                         sz->hsize, sz->vsize);
1465         }
1466
1467         return -EINVAL;
1468 }
1469
1470 static void fimc_clear_addr(struct fimc_context *ctx)
1471 {
1472         int i;
1473
1474         for (i = 0; i < FIMC_MAX_SRC; i++) {
1475                 fimc_write(0, EXYNOS_CIIYSA(i));
1476                 fimc_write(0, EXYNOS_CIICBSA(i));
1477                 fimc_write(0, EXYNOS_CIICRSA(i));
1478         }
1479
1480         for (i = 0; i < FIMC_MAX_DST; i++) {
1481                 fimc_write(0, EXYNOS_CIOYSA(i));
1482                 fimc_write(0, EXYNOS_CIOCBSA(i));
1483                 fimc_write(0, EXYNOS_CIOCRSA(i));
1484         }
1485 }
1486
1487 static int fimc_ippdrv_reset(struct device *dev)
1488 {
1489         struct fimc_context *ctx = get_fimc_context(dev);
1490
1491         /* reset h/w block */
1492         fimc_sw_reset(ctx);
1493
1494         /* reset scaler capability */
1495         memset(&ctx->sc, 0x0, sizeof(ctx->sc));
1496
1497         fimc_clear_addr(ctx);
1498
1499         return 0;
1500 }
1501
1502 static int fimc_ippdrv_start(struct device *dev, enum drm_exynos_ipp_cmd cmd)
1503 {
1504         struct fimc_context *ctx = get_fimc_context(dev);
1505         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1506         struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node;
1507         struct drm_exynos_ipp_property *property;
1508         struct drm_exynos_ipp_config *config;
1509         struct drm_exynos_pos   img_pos[EXYNOS_DRM_OPS_MAX];
1510         struct drm_exynos_ipp_set_wb set_wb;
1511         int ret, i;
1512         u32 cfg0, cfg1;
1513
1514         DRM_DEBUG_KMS("cmd[%d]\n", cmd);
1515
1516         if (!c_node) {
1517                 DRM_ERROR("failed to get c_node.\n");
1518                 return -EINVAL;
1519         }
1520
1521         property = &c_node->property;
1522
1523         fimc_handle_irq(ctx, true, false, true);
1524
1525         for_each_ipp_ops(i) {
1526                 config = &property->config[i];
1527                 img_pos[i] = config->pos;
1528         }
1529
1530         ret = fimc_set_prescaler(ctx, &ctx->sc,
1531                 &img_pos[EXYNOS_DRM_OPS_SRC],
1532                 &img_pos[EXYNOS_DRM_OPS_DST]);
1533         if (ret) {
1534                 dev_err(dev, "failed to set precalser.\n");
1535                 return ret;
1536         }
1537
1538         /* If set ture, we can save jpeg about screen */
1539         fimc_handle_jpeg(ctx, false);
1540         fimc_set_scaler(ctx, &ctx->sc);
1541         fimc_set_polarity(ctx, &ctx->pol);
1542
1543         switch (cmd) {
1544         case IPP_CMD_M2M:
1545                 fimc_set_type_ctrl(ctx, FIMC_WB_NONE);
1546                 fimc_handle_lastend(ctx, false);
1547
1548                 /* setup dma */
1549                 cfg0 = fimc_read(EXYNOS_MSCTRL);
1550                 cfg0 &= ~EXYNOS_MSCTRL_INPUT_MASK;
1551                 cfg0 |= EXYNOS_MSCTRL_INPUT_MEMORY;
1552                 fimc_write(cfg0, EXYNOS_MSCTRL);
1553                 break;
1554         case IPP_CMD_WB:
1555                 fimc_set_type_ctrl(ctx, FIMC_WB_A);
1556                 fimc_handle_lastend(ctx, true);
1557
1558                 /* setup FIMD */
1559                 ret = fimc_set_camblk_fimd0_wb(ctx);
1560                 if (ret < 0) {
1561                         dev_err(dev, "camblk setup failed.\n");
1562                         return ret;
1563                 }
1564
1565                 set_wb.enable = 1;
1566                 set_wb.refresh = property->refresh_rate;
1567                 exynos_drm_ippnb_send_event(IPP_SET_WRITEBACK, (void *)&set_wb);
1568                 break;
1569         case IPP_CMD_OUTPUT:
1570         default:
1571                 ret = -EINVAL;
1572                 dev_err(dev, "invalid operations.\n");
1573                 return ret;
1574         }
1575
1576         /* Reset status */
1577         fimc_write(0x0, EXYNOS_CISTATUS);
1578
1579         cfg0 = fimc_read(EXYNOS_CIIMGCPT);
1580         cfg0 &= ~EXYNOS_CIIMGCPT_IMGCPTEN_SC;
1581         cfg0 |= EXYNOS_CIIMGCPT_IMGCPTEN_SC;
1582
1583         /* Scaler */
1584         cfg1 = fimc_read(EXYNOS_CISCCTRL);
1585         cfg1 &= ~EXYNOS_CISCCTRL_SCAN_MASK;
1586         cfg1 |= (EXYNOS_CISCCTRL_PROGRESSIVE |
1587                 EXYNOS_CISCCTRL_SCALERSTART);
1588
1589         fimc_write(cfg1, EXYNOS_CISCCTRL);
1590
1591         /* Enable image capture*/
1592         cfg0 |= EXYNOS_CIIMGCPT_IMGCPTEN;
1593         fimc_write(cfg0, EXYNOS_CIIMGCPT);
1594
1595         /* Disable frame end irq */
1596         cfg0 = fimc_read(EXYNOS_CIGCTRL);
1597         cfg0 &= ~EXYNOS_CIGCTRL_IRQ_END_DISABLE;
1598         fimc_write(cfg0, EXYNOS_CIGCTRL);
1599
1600         cfg0 = fimc_read(EXYNOS_CIOCTRL);
1601         cfg0 &= ~EXYNOS_CIOCTRL_WEAVE_MASK;
1602         fimc_write(cfg0, EXYNOS_CIOCTRL);
1603
1604         if (cmd == IPP_CMD_M2M) {
1605                 cfg0 = fimc_read(EXYNOS_MSCTRL);
1606                 cfg0 |= EXYNOS_MSCTRL_ENVID;
1607                 fimc_write(cfg0, EXYNOS_MSCTRL);
1608
1609                 cfg0 = fimc_read(EXYNOS_MSCTRL);
1610                 cfg0 |= EXYNOS_MSCTRL_ENVID;
1611                 fimc_write(cfg0, EXYNOS_MSCTRL);
1612         }
1613
1614         return 0;
1615 }
1616
1617 static void fimc_ippdrv_stop(struct device *dev, enum drm_exynos_ipp_cmd cmd)
1618 {
1619         struct fimc_context *ctx = get_fimc_context(dev);
1620         struct drm_exynos_ipp_set_wb set_wb = {0, 0};
1621         u32 cfg;
1622
1623         DRM_DEBUG_KMS("cmd[%d]\n", cmd);
1624
1625         switch (cmd) {
1626         case IPP_CMD_M2M:
1627                 /* Source clear */
1628                 cfg = fimc_read(EXYNOS_MSCTRL);
1629                 cfg &= ~EXYNOS_MSCTRL_INPUT_MASK;
1630                 cfg &= ~EXYNOS_MSCTRL_ENVID;
1631                 fimc_write(cfg, EXYNOS_MSCTRL);
1632                 break;
1633         case IPP_CMD_WB:
1634                 exynos_drm_ippnb_send_event(IPP_SET_WRITEBACK, (void *)&set_wb);
1635                 break;
1636         case IPP_CMD_OUTPUT:
1637         default:
1638                 dev_err(dev, "invalid operations.\n");
1639                 break;
1640         }
1641
1642         fimc_handle_irq(ctx, false, false, true);
1643
1644         /* reset sequence */
1645         fimc_write(0x0, EXYNOS_CIFCNTSEQ);
1646
1647         /* Scaler disable */
1648         cfg = fimc_read(EXYNOS_CISCCTRL);
1649         cfg &= ~EXYNOS_CISCCTRL_SCALERSTART;
1650         fimc_write(cfg, EXYNOS_CISCCTRL);
1651
1652         /* Disable image capture */
1653         cfg = fimc_read(EXYNOS_CIIMGCPT);
1654         cfg &= ~(EXYNOS_CIIMGCPT_IMGCPTEN_SC | EXYNOS_CIIMGCPT_IMGCPTEN);
1655         fimc_write(cfg, EXYNOS_CIIMGCPT);
1656
1657         /* Enable frame end irq */
1658         cfg = fimc_read(EXYNOS_CIGCTRL);
1659         cfg |= EXYNOS_CIGCTRL_IRQ_END_DISABLE;
1660         fimc_write(cfg, EXYNOS_CIGCTRL);
1661 }
1662
1663 static void fimc_put_clocks(struct fimc_context *ctx)
1664 {
1665         int i;
1666
1667         for (i = 0; i < FIMC_CLKS_MAX; i++) {
1668                 if (IS_ERR(ctx->clocks[i]))
1669                         continue;
1670                 clk_put(ctx->clocks[i]);
1671                 ctx->clocks[i] = ERR_PTR(-EINVAL);
1672         }
1673 }
1674
1675 static int fimc_setup_clocks(struct fimc_context *ctx)
1676 {
1677         struct device *fimc_dev = ctx->ippdrv.dev;
1678         struct device *dev;
1679         int ret, i;
1680
1681         for (i = 0; i < FIMC_CLKS_MAX; i++)
1682                 ctx->clocks[i] = ERR_PTR(-EINVAL);
1683
1684         for (i = 0; i < FIMC_CLKS_MAX; i++) {
1685                 if (i == FIMC_CLK_WB_A || i == FIMC_CLK_WB_B)
1686                         dev = fimc_dev->parent;
1687                 else
1688                         dev = fimc_dev;
1689
1690                 ctx->clocks[i] = clk_get(dev, fimc_clock_names[i]);
1691                 if (IS_ERR(ctx->clocks[i])) {
1692                         if (i >= FIMC_CLK_MUX)
1693                                 break;
1694                         ret = PTR_ERR(ctx->clocks[i]);
1695                         dev_err(fimc_dev, "failed to get clock: %s\n",
1696                                                 fimc_clock_names[i]);
1697                         goto e_clk_free;
1698                 }
1699         }
1700
1701         /* Optional FIMC LCLK parent clock setting */
1702         if (!IS_ERR(ctx->clocks[FIMC_CLK_PARENT])) {
1703                 ret = clk_set_parent(ctx->clocks[FIMC_CLK_MUX],
1704                                      ctx->clocks[FIMC_CLK_PARENT]);
1705                 if (ret < 0) {
1706                         dev_err(fimc_dev, "failed to set parent.\n");
1707                         goto e_clk_free;
1708                 }
1709         }
1710
1711         ret = clk_set_rate(ctx->clocks[FIMC_CLK_LCLK], ctx->clk_frequency);
1712         if (ret < 0)
1713                 goto e_clk_free;
1714
1715         ret = clk_prepare_enable(ctx->clocks[FIMC_CLK_LCLK]);
1716         if (!ret)
1717                 return ret;
1718 e_clk_free:
1719         fimc_put_clocks(ctx);
1720         return ret;
1721 }
1722
1723 static int fimc_parse_dt(struct fimc_context *ctx)
1724 {
1725         struct device_node *node = ctx->ippdrv.dev->of_node;
1726
1727         /* Handle only devices that support the LCD Writeback data path */
1728         if (!of_property_read_bool(node, "samsung,lcd-wb"))
1729                 return -ENODEV;
1730
1731         if (of_property_read_u32(node, "clock-frequency",
1732                                         &ctx->clk_frequency))
1733                 ctx->clk_frequency = FIMC_DEFAULT_LCLK_FREQUENCY;
1734
1735         ctx->id = of_alias_get_id(node, "fimc");
1736
1737         if (ctx->id < 0) {
1738                 dev_err(ctx->ippdrv.dev, "failed to get node alias id.\n");
1739                 return -EINVAL;
1740         }
1741
1742         return 0;
1743 }
1744
1745 static int fimc_probe(struct platform_device *pdev)
1746 {
1747         struct device *dev = &pdev->dev;
1748         struct fimc_context *ctx;
1749         struct resource *res;
1750         struct exynos_drm_ippdrv *ippdrv;
1751         int ret;
1752
1753         if (!dev->of_node) {
1754                 dev_err(dev, "device tree node not found.\n");
1755                 return -ENODEV;
1756         }
1757
1758         ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1759         if (!ctx)
1760                 return -ENOMEM;
1761
1762         ctx->ippdrv.dev = dev;
1763
1764         ret = fimc_parse_dt(ctx);
1765         if (ret < 0)
1766                 return ret;
1767
1768         ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
1769                                                 "samsung,sysreg");
1770         if (IS_ERR(ctx->sysreg)) {
1771                 dev_err(dev, "syscon regmap lookup failed.\n");
1772                 return PTR_ERR(ctx->sysreg);
1773         }
1774
1775         /* resource memory */
1776         ctx->regs_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1777         ctx->regs = devm_ioremap_resource(dev, ctx->regs_res);
1778         if (IS_ERR(ctx->regs))
1779                 return PTR_ERR(ctx->regs);
1780
1781         /* resource irq */
1782         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1783         if (!res) {
1784                 dev_err(dev, "failed to request irq resource.\n");
1785                 return -ENOENT;
1786         }
1787
1788         ctx->irq = res->start;
1789         ret = devm_request_threaded_irq(dev, ctx->irq, NULL, fimc_irq_handler,
1790                 IRQF_ONESHOT, "drm_fimc", ctx);
1791         if (ret < 0) {
1792                 dev_err(dev, "failed to request irq.\n");
1793                 return ret;
1794         }
1795
1796         ret = fimc_setup_clocks(ctx);
1797         if (ret < 0)
1798                 return ret;
1799
1800         ippdrv = &ctx->ippdrv;
1801         ippdrv->ops[EXYNOS_DRM_OPS_SRC] = &fimc_src_ops;
1802         ippdrv->ops[EXYNOS_DRM_OPS_DST] = &fimc_dst_ops;
1803         ippdrv->check_property = fimc_ippdrv_check_property;
1804         ippdrv->reset = fimc_ippdrv_reset;
1805         ippdrv->start = fimc_ippdrv_start;
1806         ippdrv->stop = fimc_ippdrv_stop;
1807         ret = fimc_init_prop_list(ippdrv);
1808         if (ret < 0) {
1809                 dev_err(dev, "failed to init property list.\n");
1810                 goto err_put_clk;
1811         }
1812
1813         DRM_DEBUG_KMS("id[%d]ippdrv[0x%x]\n", ctx->id, (int)ippdrv);
1814
1815         mutex_init(&ctx->lock);
1816         platform_set_drvdata(pdev, ctx);
1817
1818         pm_runtime_set_active(dev);
1819         pm_runtime_enable(dev);
1820
1821         ret = exynos_drm_ippdrv_register(ippdrv);
1822         if (ret < 0) {
1823                 dev_err(dev, "failed to register drm fimc device.\n");
1824                 goto err_pm_dis;
1825         }
1826
1827         dev_info(dev, "drm fimc registered successfully.\n");
1828
1829         return 0;
1830
1831 err_pm_dis:
1832         pm_runtime_disable(dev);
1833 err_put_clk:
1834         fimc_put_clocks(ctx);
1835
1836         return ret;
1837 }
1838
1839 static int fimc_remove(struct platform_device *pdev)
1840 {
1841         struct device *dev = &pdev->dev;
1842         struct fimc_context *ctx = get_fimc_context(dev);
1843         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
1844
1845         exynos_drm_ippdrv_unregister(ippdrv);
1846         mutex_destroy(&ctx->lock);
1847
1848         fimc_put_clocks(ctx);
1849         pm_runtime_set_suspended(dev);
1850         pm_runtime_disable(dev);
1851
1852         return 0;
1853 }
1854
1855 #ifdef CONFIG_PM_SLEEP
1856 static int fimc_suspend(struct device *dev)
1857 {
1858         struct fimc_context *ctx = get_fimc_context(dev);
1859
1860         DRM_DEBUG_KMS("id[%d]\n", ctx->id);
1861
1862         if (pm_runtime_suspended(dev))
1863                 return 0;
1864
1865         return fimc_clk_ctrl(ctx, false);
1866 }
1867
1868 static int fimc_resume(struct device *dev)
1869 {
1870         struct fimc_context *ctx = get_fimc_context(dev);
1871
1872         DRM_DEBUG_KMS("id[%d]\n", ctx->id);
1873
1874         if (!pm_runtime_suspended(dev))
1875                 return fimc_clk_ctrl(ctx, true);
1876
1877         return 0;
1878 }
1879 #endif
1880
1881 #ifdef CONFIG_PM_RUNTIME
1882 static int fimc_runtime_suspend(struct device *dev)
1883 {
1884         struct fimc_context *ctx = get_fimc_context(dev);
1885
1886         DRM_DEBUG_KMS("id[%d]\n", ctx->id);
1887
1888         return  fimc_clk_ctrl(ctx, false);
1889 }
1890
1891 static int fimc_runtime_resume(struct device *dev)
1892 {
1893         struct fimc_context *ctx = get_fimc_context(dev);
1894
1895         DRM_DEBUG_KMS("id[%d]\n", ctx->id);
1896
1897         return  fimc_clk_ctrl(ctx, true);
1898 }
1899 #endif
1900
1901 static const struct dev_pm_ops fimc_pm_ops = {
1902         SET_SYSTEM_SLEEP_PM_OPS(fimc_suspend, fimc_resume)
1903         SET_RUNTIME_PM_OPS(fimc_runtime_suspend, fimc_runtime_resume, NULL)
1904 };
1905
1906 static const struct of_device_id fimc_of_match[] = {
1907         { .compatible = "samsung,exynos4210-fimc" },
1908         { .compatible = "samsung,exynos4212-fimc" },
1909         { },
1910 };
1911
1912 struct platform_driver fimc_driver = {
1913         .probe          = fimc_probe,
1914         .remove         = fimc_remove,
1915         .driver         = {
1916                 .of_match_table = fimc_of_match,
1917                 .name   = "exynos-drm-fimc",
1918                 .owner  = THIS_MODULE,
1919                 .pm     = &fimc_pm_ops,
1920         },
1921 };
1922