3 * Copyright (C) 2011 Samsung Electronics Co.Ltd
5 * Joonyoung Shim <jy0922.shim@samsung.com>
6 * Inki Dae <inki.dae@samsung.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
16 #include <linux/kernel.h>
17 #include <linux/platform_device.h>
18 #include <linux/clk.h>
20 #include <linux/of_device.h>
21 #include <linux/pm_runtime.h>
23 #include <video/of_display_timing.h>
24 #include <video/samsung_fimd.h>
25 #include <drm/exynos_drm.h>
27 #include "exynos_drm_drv.h"
28 #include "exynos_drm_fbdev.h"
29 #include "exynos_drm_crtc.h"
30 #include "exynos_drm_iommu.h"
33 * FIMD is stand for Fully Interactive Mobile Display and
34 * as a display controller, it transfers contents drawn on memory
35 * to a LCD Panel through Display Interfaces such as RGB or
39 /* position control register for hardware window 0, 2 ~ 4.*/
40 #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16)
41 #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16)
43 * size control register for hardware windows 0 and alpha control register
44 * for hardware windows 1 ~ 4
46 #define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16)
47 /* size control register for hardware windows 1 ~ 2. */
48 #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16)
50 #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8)
51 #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8)
52 #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4)
54 /* color key control register for hardware window 1 ~ 4. */
55 #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8))
56 /* color key value register for hardware window 1 ~ 4. */
57 #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8))
59 /* FIMD has totally five hardware windows. */
62 #define get_fimd_context(dev) platform_get_drvdata(to_platform_device(dev))
64 struct fimd_driver_data {
65 unsigned int timing_base;
67 unsigned int has_shadowcon:1;
68 unsigned int has_clksel:1;
71 static struct fimd_driver_data s3c64xx_fimd_driver_data = {
76 static struct fimd_driver_data exynos4_fimd_driver_data = {
81 static struct fimd_driver_data exynos5_fimd_driver_data = {
82 .timing_base = 0x20000,
86 struct fimd_win_data {
87 unsigned int offset_x;
88 unsigned int offset_y;
89 unsigned int ovl_width;
90 unsigned int ovl_height;
91 unsigned int fb_width;
92 unsigned int fb_height;
94 unsigned int pixel_format;
96 unsigned int buf_offsize;
97 unsigned int line_size; /* bytes */
102 struct fimd_context {
103 struct exynos_drm_subdrv subdrv;
105 struct drm_crtc *crtc;
109 struct fimd_win_data win_data[WINDOWS_NR];
111 unsigned int default_win;
112 unsigned long irq_flags;
117 wait_queue_head_t wait_vsync_queue;
118 atomic_t wait_vsync_event;
120 struct exynos_drm_panel_info *panel;
121 struct fimd_driver_data *driver_data;
125 static const struct of_device_id fimd_driver_dt_match[] = {
126 { .compatible = "samsung,s3c6400-fimd",
127 .data = &s3c64xx_fimd_driver_data },
128 { .compatible = "samsung,exynos4210-fimd",
129 .data = &exynos4_fimd_driver_data },
130 { .compatible = "samsung,exynos5250-fimd",
131 .data = &exynos5_fimd_driver_data },
136 static inline struct fimd_driver_data *drm_fimd_get_driver_data(
137 struct platform_device *pdev)
140 const struct of_device_id *of_id =
141 of_match_device(fimd_driver_dt_match, &pdev->dev);
144 return (struct fimd_driver_data *)of_id->data;
147 return (struct fimd_driver_data *)
148 platform_get_device_id(pdev)->driver_data;
151 static bool fimd_display_is_connected(struct device *dev)
158 static void *fimd_get_panel(struct device *dev)
160 struct fimd_context *ctx = get_fimd_context(dev);
165 static int fimd_check_mode(struct device *dev, struct drm_display_mode *mode)
172 static int fimd_display_power_on(struct device *dev, int mode)
179 static struct exynos_drm_display_ops fimd_display_ops = {
180 .type = EXYNOS_DISPLAY_TYPE_LCD,
181 .is_connected = fimd_display_is_connected,
182 .get_panel = fimd_get_panel,
183 .check_mode = fimd_check_mode,
184 .power_on = fimd_display_power_on,
187 static void fimd_dpms(struct device *subdrv_dev, int mode)
189 struct fimd_context *ctx = get_fimd_context(subdrv_dev);
191 DRM_DEBUG_KMS("%d\n", mode);
193 mutex_lock(&ctx->lock);
196 case DRM_MODE_DPMS_ON:
198 * enable fimd hardware only if suspended status.
200 * P.S. fimd_dpms function would be called at booting time so
201 * clk_enable could be called double time.
204 pm_runtime_get_sync(subdrv_dev);
206 case DRM_MODE_DPMS_STANDBY:
207 case DRM_MODE_DPMS_SUSPEND:
208 case DRM_MODE_DPMS_OFF:
210 pm_runtime_put_sync(subdrv_dev);
213 DRM_DEBUG_KMS("unspecified mode %d\n", mode);
217 mutex_unlock(&ctx->lock);
220 static void fimd_apply(struct device *subdrv_dev)
222 struct fimd_context *ctx = get_fimd_context(subdrv_dev);
223 struct exynos_drm_manager *mgr = ctx->subdrv.manager;
224 struct exynos_drm_manager_ops *mgr_ops = mgr->ops;
225 struct exynos_drm_overlay_ops *ovl_ops = mgr->overlay_ops;
226 struct fimd_win_data *win_data;
229 for (i = 0; i < WINDOWS_NR; i++) {
230 win_data = &ctx->win_data[i];
231 if (win_data->enabled && (ovl_ops && ovl_ops->commit))
232 ovl_ops->commit(subdrv_dev, i);
235 if (mgr_ops && mgr_ops->commit)
236 mgr_ops->commit(subdrv_dev);
239 static void fimd_commit(struct device *dev)
241 struct fimd_context *ctx = get_fimd_context(dev);
242 struct exynos_drm_panel_info *panel = ctx->panel;
243 struct fb_videomode *timing = &panel->timing;
244 struct fimd_driver_data *driver_data;
247 driver_data = ctx->driver_data;
251 /* setup polarity values from machine code. */
252 writel(ctx->vidcon1, ctx->regs + driver_data->timing_base + VIDCON1);
254 /* setup vertical timing values. */
255 val = VIDTCON0_VBPD(timing->upper_margin - 1) |
256 VIDTCON0_VFPD(timing->lower_margin - 1) |
257 VIDTCON0_VSPW(timing->vsync_len - 1);
258 writel(val, ctx->regs + driver_data->timing_base + VIDTCON0);
260 /* setup horizontal timing values. */
261 val = VIDTCON1_HBPD(timing->left_margin - 1) |
262 VIDTCON1_HFPD(timing->right_margin - 1) |
263 VIDTCON1_HSPW(timing->hsync_len - 1);
264 writel(val, ctx->regs + driver_data->timing_base + VIDTCON1);
266 /* setup horizontal and vertical display size. */
267 val = VIDTCON2_LINEVAL(timing->yres - 1) |
268 VIDTCON2_HOZVAL(timing->xres - 1) |
269 VIDTCON2_LINEVAL_E(timing->yres - 1) |
270 VIDTCON2_HOZVAL_E(timing->xres - 1);
271 writel(val, ctx->regs + driver_data->timing_base + VIDTCON2);
273 /* setup clock source, clock divider, enable dma. */
275 val &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR);
277 if (ctx->driver_data->has_clksel) {
278 val &= ~VIDCON0_CLKSEL_MASK;
279 val |= VIDCON0_CLKSEL_LCD;
283 val |= VIDCON0_CLKVAL_F(ctx->clkdiv - 1) | VIDCON0_CLKDIR;
285 val &= ~VIDCON0_CLKDIR; /* 1:1 clock */
288 * fields of register with prefix '_F' would be updated
289 * at vsync(same as dma start)
291 val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
292 writel(val, ctx->regs + VIDCON0);
295 static int fimd_enable_vblank(struct device *dev)
297 struct fimd_context *ctx = get_fimd_context(dev);
303 if (!test_and_set_bit(0, &ctx->irq_flags)) {
304 val = readl(ctx->regs + VIDINTCON0);
306 val |= VIDINTCON0_INT_ENABLE;
307 val |= VIDINTCON0_INT_FRAME;
309 val &= ~VIDINTCON0_FRAMESEL0_MASK;
310 val |= VIDINTCON0_FRAMESEL0_VSYNC;
311 val &= ~VIDINTCON0_FRAMESEL1_MASK;
312 val |= VIDINTCON0_FRAMESEL1_NONE;
314 writel(val, ctx->regs + VIDINTCON0);
320 static void fimd_disable_vblank(struct device *dev)
322 struct fimd_context *ctx = get_fimd_context(dev);
328 if (test_and_clear_bit(0, &ctx->irq_flags)) {
329 val = readl(ctx->regs + VIDINTCON0);
331 val &= ~VIDINTCON0_INT_FRAME;
332 val &= ~VIDINTCON0_INT_ENABLE;
334 writel(val, ctx->regs + VIDINTCON0);
338 static void fimd_wait_for_vblank(struct device *dev)
340 struct fimd_context *ctx = get_fimd_context(dev);
345 atomic_set(&ctx->wait_vsync_event, 1);
348 * wait for FIMD to signal VSYNC interrupt or return after
349 * timeout which is set to 50ms (refresh rate of 20).
351 if (!wait_event_timeout(ctx->wait_vsync_queue,
352 !atomic_read(&ctx->wait_vsync_event),
354 DRM_DEBUG_KMS("vblank wait timed out.\n");
357 static struct exynos_drm_manager_ops fimd_manager_ops = {
360 .commit = fimd_commit,
361 .enable_vblank = fimd_enable_vblank,
362 .disable_vblank = fimd_disable_vblank,
363 .wait_for_vblank = fimd_wait_for_vblank,
366 static void fimd_win_mode_set(struct device *dev,
367 struct exynos_drm_overlay *overlay)
369 struct fimd_context *ctx = get_fimd_context(dev);
370 struct fimd_win_data *win_data;
372 unsigned long offset;
375 dev_err(dev, "overlay is NULL\n");
380 if (win == DEFAULT_ZPOS)
381 win = ctx->default_win;
383 if (win < 0 || win >= WINDOWS_NR)
386 offset = overlay->fb_x * (overlay->bpp >> 3);
387 offset += overlay->fb_y * overlay->pitch;
389 DRM_DEBUG_KMS("offset = 0x%lx, pitch = %x\n", offset, overlay->pitch);
391 win_data = &ctx->win_data[win];
393 win_data->offset_x = overlay->crtc_x;
394 win_data->offset_y = overlay->crtc_y;
395 win_data->ovl_width = overlay->crtc_width;
396 win_data->ovl_height = overlay->crtc_height;
397 win_data->fb_width = overlay->fb_width;
398 win_data->fb_height = overlay->fb_height;
399 win_data->dma_addr = overlay->dma_addr[0] + offset;
400 win_data->bpp = overlay->bpp;
401 win_data->pixel_format = overlay->pixel_format;
402 win_data->buf_offsize = (overlay->fb_width - overlay->crtc_width) *
404 win_data->line_size = overlay->crtc_width * (overlay->bpp >> 3);
406 DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n",
407 win_data->offset_x, win_data->offset_y);
408 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
409 win_data->ovl_width, win_data->ovl_height);
410 DRM_DEBUG_KMS("paddr = 0x%lx\n", (unsigned long)win_data->dma_addr);
411 DRM_DEBUG_KMS("fb_width = %d, crtc_width = %d\n",
412 overlay->fb_width, overlay->crtc_width);
415 static void fimd_win_set_pixfmt(struct device *dev, unsigned int win)
417 struct fimd_context *ctx = get_fimd_context(dev);
418 struct fimd_win_data *win_data = &ctx->win_data[win];
423 switch (win_data->pixel_format) {
425 val |= WINCON0_BPPMODE_8BPP_PALETTE;
426 val |= WINCONx_BURSTLEN_8WORD;
427 val |= WINCONx_BYTSWP;
429 case DRM_FORMAT_XRGB1555:
430 val |= WINCON0_BPPMODE_16BPP_1555;
431 val |= WINCONx_HAWSWP;
432 val |= WINCONx_BURSTLEN_16WORD;
434 case DRM_FORMAT_RGB565:
435 val |= WINCON0_BPPMODE_16BPP_565;
436 val |= WINCONx_HAWSWP;
437 val |= WINCONx_BURSTLEN_16WORD;
439 case DRM_FORMAT_XRGB8888:
440 val |= WINCON0_BPPMODE_24BPP_888;
442 val |= WINCONx_BURSTLEN_16WORD;
444 case DRM_FORMAT_ARGB8888:
445 val |= WINCON1_BPPMODE_25BPP_A1888
446 | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
448 val |= WINCONx_BURSTLEN_16WORD;
451 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
453 val |= WINCON0_BPPMODE_24BPP_888;
455 val |= WINCONx_BURSTLEN_16WORD;
459 DRM_DEBUG_KMS("bpp = %d\n", win_data->bpp);
461 writel(val, ctx->regs + WINCON(win));
464 static void fimd_win_set_colkey(struct device *dev, unsigned int win)
466 struct fimd_context *ctx = get_fimd_context(dev);
467 unsigned int keycon0 = 0, keycon1 = 0;
469 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
470 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
472 keycon1 = WxKEYCON1_COLVAL(0xffffffff);
474 writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
475 writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
479 * shadow_protect_win() - disable updating values from shadow registers at vsync
481 * @win: window to protect registers for
482 * @protect: 1 to protect (disable updates)
484 static void fimd_shadow_protect_win(struct fimd_context *ctx,
485 int win, bool protect)
489 if (ctx->driver_data->has_shadowcon) {
491 bits = SHADOWCON_WINx_PROTECT(win);
494 bits = PRTCON_PROTECT;
497 val = readl(ctx->regs + reg);
502 writel(val, ctx->regs + reg);
505 static void fimd_win_commit(struct device *dev, int zpos)
507 struct fimd_context *ctx = get_fimd_context(dev);
508 struct fimd_win_data *win_data;
510 unsigned long val, alpha, size;
517 if (win == DEFAULT_ZPOS)
518 win = ctx->default_win;
520 if (win < 0 || win >= WINDOWS_NR)
523 win_data = &ctx->win_data[win];
526 * SHADOWCON/PRTCON register is used for enabling timing.
528 * for example, once only width value of a register is set,
529 * if the dma is started then fimd hardware could malfunction so
530 * with protect window setting, the register fields with prefix '_F'
531 * wouldn't be updated at vsync also but updated once unprotect window
535 /* protect windows */
536 fimd_shadow_protect_win(ctx, win, true);
538 /* buffer start address */
539 val = (unsigned long)win_data->dma_addr;
540 writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
542 /* buffer end address */
543 size = win_data->fb_width * win_data->ovl_height * (win_data->bpp >> 3);
544 val = (unsigned long)(win_data->dma_addr + size);
545 writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
547 DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
548 (unsigned long)win_data->dma_addr, val, size);
549 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
550 win_data->ovl_width, win_data->ovl_height);
553 val = VIDW_BUF_SIZE_OFFSET(win_data->buf_offsize) |
554 VIDW_BUF_SIZE_PAGEWIDTH(win_data->line_size) |
555 VIDW_BUF_SIZE_OFFSET_E(win_data->buf_offsize) |
556 VIDW_BUF_SIZE_PAGEWIDTH_E(win_data->line_size);
557 writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
560 val = VIDOSDxA_TOPLEFT_X(win_data->offset_x) |
561 VIDOSDxA_TOPLEFT_Y(win_data->offset_y) |
562 VIDOSDxA_TOPLEFT_X_E(win_data->offset_x) |
563 VIDOSDxA_TOPLEFT_Y_E(win_data->offset_y);
564 writel(val, ctx->regs + VIDOSD_A(win));
566 last_x = win_data->offset_x + win_data->ovl_width;
569 last_y = win_data->offset_y + win_data->ovl_height;
573 val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) |
574 VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y);
576 writel(val, ctx->regs + VIDOSD_B(win));
578 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
579 win_data->offset_x, win_data->offset_y, last_x, last_y);
581 /* hardware window 0 doesn't support alpha channel. */
584 alpha = VIDISD14C_ALPHA1_R(0xf) |
585 VIDISD14C_ALPHA1_G(0xf) |
586 VIDISD14C_ALPHA1_B(0xf);
588 writel(alpha, ctx->regs + VIDOSD_C(win));
592 if (win != 3 && win != 4) {
593 u32 offset = VIDOSD_D(win);
595 offset = VIDOSD_C(win);
596 val = win_data->ovl_width * win_data->ovl_height;
597 writel(val, ctx->regs + offset);
599 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val);
602 fimd_win_set_pixfmt(dev, win);
604 /* hardware window 0 doesn't support color key. */
606 fimd_win_set_colkey(dev, win);
609 val = readl(ctx->regs + WINCON(win));
610 val |= WINCONx_ENWIN;
611 writel(val, ctx->regs + WINCON(win));
613 /* Enable DMA channel and unprotect windows */
614 fimd_shadow_protect_win(ctx, win, false);
616 if (ctx->driver_data->has_shadowcon) {
617 val = readl(ctx->regs + SHADOWCON);
618 val |= SHADOWCON_CHx_ENABLE(win);
619 writel(val, ctx->regs + SHADOWCON);
622 win_data->enabled = true;
625 static void fimd_win_disable(struct device *dev, int zpos)
627 struct fimd_context *ctx = get_fimd_context(dev);
628 struct fimd_win_data *win_data;
632 if (win == DEFAULT_ZPOS)
633 win = ctx->default_win;
635 if (win < 0 || win >= WINDOWS_NR)
638 win_data = &ctx->win_data[win];
640 if (ctx->suspended) {
641 /* do not resume this window*/
642 win_data->resume = false;
646 /* protect windows */
647 fimd_shadow_protect_win(ctx, win, true);
650 val = readl(ctx->regs + WINCON(win));
651 val &= ~WINCONx_ENWIN;
652 writel(val, ctx->regs + WINCON(win));
654 /* unprotect windows */
655 if (ctx->driver_data->has_shadowcon) {
656 val = readl(ctx->regs + SHADOWCON);
657 val &= ~SHADOWCON_CHx_ENABLE(win);
658 writel(val, ctx->regs + SHADOWCON);
661 fimd_shadow_protect_win(ctx, win, false);
663 win_data->enabled = false;
666 static struct exynos_drm_overlay_ops fimd_overlay_ops = {
667 .mode_set = fimd_win_mode_set,
668 .commit = fimd_win_commit,
669 .disable = fimd_win_disable,
672 static struct exynos_drm_manager fimd_manager = {
674 .ops = &fimd_manager_ops,
675 .overlay_ops = &fimd_overlay_ops,
676 .display_ops = &fimd_display_ops,
679 static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
681 struct fimd_context *ctx = (struct fimd_context *)dev_id;
682 struct exynos_drm_subdrv *subdrv = &ctx->subdrv;
683 struct drm_device *drm_dev = subdrv->drm_dev;
684 struct exynos_drm_manager *manager = subdrv->manager;
687 val = readl(ctx->regs + VIDINTCON1);
689 if (val & VIDINTCON1_INT_FRAME)
690 /* VSYNC interrupt */
691 writel(VIDINTCON1_INT_FRAME, ctx->regs + VIDINTCON1);
693 /* check the crtc is detached already from encoder */
694 if (manager->pipe < 0)
697 drm_handle_vblank(drm_dev, manager->pipe);
698 exynos_drm_crtc_finish_pageflip(drm_dev, manager->pipe);
700 /* set wait vsync event to zero and wake up queue. */
701 if (atomic_read(&ctx->wait_vsync_event)) {
702 atomic_set(&ctx->wait_vsync_event, 0);
703 DRM_WAKEUP(&ctx->wait_vsync_queue);
709 static int fimd_subdrv_probe(struct drm_device *drm_dev, struct device *dev)
712 * enable drm irq mode.
713 * - with irq_enabled = 1, we can use the vblank feature.
715 * P.S. note that we wouldn't use drm irq handler but
716 * just specific driver own one instead because
717 * drm framework supports only one irq handler.
719 drm_dev->irq_enabled = 1;
722 * with vblank_disable_allowed = 1, vblank interrupt will be disabled
723 * by drm timer once a current process gives up ownership of
724 * vblank event.(after drm_vblank_put function is called)
726 drm_dev->vblank_disable_allowed = 1;
728 /* attach this sub driver to iommu mapping if supported. */
729 if (is_drm_iommu_supported(drm_dev))
730 drm_iommu_attach_device(drm_dev, dev);
735 static void fimd_subdrv_remove(struct drm_device *drm_dev, struct device *dev)
737 /* detach this sub driver from iommu mapping if supported. */
738 if (is_drm_iommu_supported(drm_dev))
739 drm_iommu_detach_device(drm_dev, dev);
742 static int fimd_calc_clkdiv(struct fimd_context *ctx,
743 struct fb_videomode *timing)
745 unsigned long clk = clk_get_rate(ctx->lcd_clk);
748 u32 best_framerate = 0;
751 retrace = timing->left_margin + timing->hsync_len +
752 timing->right_margin + timing->xres;
753 retrace *= timing->upper_margin + timing->vsync_len +
754 timing->lower_margin + timing->yres;
756 /* default framerate is 60Hz */
757 if (!timing->refresh)
758 timing->refresh = 60;
762 for (clkdiv = 1; clkdiv < 0x100; clkdiv++) {
765 /* get best framerate */
766 framerate = clk / clkdiv;
767 tmp = timing->refresh - framerate;
769 best_framerate = framerate;
773 best_framerate = framerate;
774 else if (tmp < (best_framerate - framerate))
775 best_framerate = framerate;
783 static void fimd_clear_win(struct fimd_context *ctx, int win)
785 writel(0, ctx->regs + WINCON(win));
786 writel(0, ctx->regs + VIDOSD_A(win));
787 writel(0, ctx->regs + VIDOSD_B(win));
788 writel(0, ctx->regs + VIDOSD_C(win));
790 if (win == 1 || win == 2)
791 writel(0, ctx->regs + VIDOSD_D(win));
793 fimd_shadow_protect_win(ctx, win, false);
796 static int fimd_clock(struct fimd_context *ctx, bool enable)
801 ret = clk_prepare_enable(ctx->bus_clk);
805 ret = clk_prepare_enable(ctx->lcd_clk);
807 clk_disable_unprepare(ctx->bus_clk);
811 clk_disable_unprepare(ctx->lcd_clk);
812 clk_disable_unprepare(ctx->bus_clk);
818 static void fimd_window_suspend(struct device *dev)
820 struct fimd_context *ctx = get_fimd_context(dev);
821 struct fimd_win_data *win_data;
824 for (i = 0; i < WINDOWS_NR; i++) {
825 win_data = &ctx->win_data[i];
826 win_data->resume = win_data->enabled;
827 fimd_win_disable(dev, i);
829 fimd_wait_for_vblank(dev);
832 static void fimd_window_resume(struct device *dev)
834 struct fimd_context *ctx = get_fimd_context(dev);
835 struct fimd_win_data *win_data;
838 for (i = 0; i < WINDOWS_NR; i++) {
839 win_data = &ctx->win_data[i];
840 win_data->enabled = win_data->resume;
841 win_data->resume = false;
845 static int fimd_activate(struct fimd_context *ctx, bool enable)
847 struct device *dev = ctx->subdrv.dev;
851 ret = fimd_clock(ctx, true);
855 ctx->suspended = false;
857 /* if vblank was enabled status, enable it again. */
858 if (test_and_clear_bit(0, &ctx->irq_flags))
859 fimd_enable_vblank(dev);
861 fimd_window_resume(dev);
863 fimd_window_suspend(dev);
865 fimd_clock(ctx, false);
866 ctx->suspended = true;
872 static int fimd_probe(struct platform_device *pdev)
874 struct device *dev = &pdev->dev;
875 struct fimd_context *ctx;
876 struct exynos_drm_subdrv *subdrv;
877 struct exynos_drm_fimd_pdata *pdata;
878 struct exynos_drm_panel_info *panel;
879 struct resource *res;
884 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
888 ret = of_get_fb_videomode(dev->of_node, &pdata->panel.timing,
891 DRM_ERROR("failed: of_get_fb_videomode() : %d\n", ret);
895 pdata = dev->platform_data;
897 DRM_ERROR("no platform data specified\n");
902 panel = &pdata->panel;
904 dev_err(dev, "panel is null.\n");
908 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
912 ctx->bus_clk = devm_clk_get(dev, "fimd");
913 if (IS_ERR(ctx->bus_clk)) {
914 dev_err(dev, "failed to get bus clock\n");
915 return PTR_ERR(ctx->bus_clk);
918 ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd");
919 if (IS_ERR(ctx->lcd_clk)) {
920 dev_err(dev, "failed to get lcd clock\n");
921 return PTR_ERR(ctx->lcd_clk);
924 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
926 ctx->regs = devm_ioremap_resource(dev, res);
927 if (IS_ERR(ctx->regs))
928 return PTR_ERR(ctx->regs);
930 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "vsync");
932 dev_err(dev, "irq request failed.\n");
936 ctx->irq = res->start;
938 ret = devm_request_irq(dev, ctx->irq, fimd_irq_handler,
941 dev_err(dev, "irq request failed.\n");
945 ctx->driver_data = drm_fimd_get_driver_data(pdev);
946 ctx->vidcon0 = pdata->vidcon0;
947 ctx->vidcon1 = pdata->vidcon1;
948 ctx->default_win = pdata->default_win;
950 DRM_INIT_WAITQUEUE(&ctx->wait_vsync_queue);
951 atomic_set(&ctx->wait_vsync_event, 0);
953 subdrv = &ctx->subdrv;
956 subdrv->manager = &fimd_manager;
957 subdrv->probe = fimd_subdrv_probe;
958 subdrv->remove = fimd_subdrv_remove;
960 mutex_init(&ctx->lock);
962 platform_set_drvdata(pdev, ctx);
964 pm_runtime_enable(dev);
965 pm_runtime_get_sync(dev);
967 ctx->clkdiv = fimd_calc_clkdiv(ctx, &panel->timing);
968 panel->timing.pixclock = clk_get_rate(ctx->lcd_clk) / ctx->clkdiv;
970 DRM_DEBUG_KMS("pixel clock = %d, clkdiv = %d\n",
971 panel->timing.pixclock, ctx->clkdiv);
973 for (win = 0; win < WINDOWS_NR; win++)
974 fimd_clear_win(ctx, win);
976 exynos_drm_subdrv_register(subdrv);
981 static int fimd_remove(struct platform_device *pdev)
983 struct device *dev = &pdev->dev;
984 struct fimd_context *ctx = platform_get_drvdata(pdev);
986 exynos_drm_subdrv_unregister(&ctx->subdrv);
991 pm_runtime_set_suspended(dev);
992 pm_runtime_put_sync(dev);
995 pm_runtime_disable(dev);
1000 #ifdef CONFIG_PM_SLEEP
1001 static int fimd_suspend(struct device *dev)
1003 struct fimd_context *ctx = get_fimd_context(dev);
1006 * do not use pm_runtime_suspend(). if pm_runtime_suspend() is
1007 * called here, an error would be returned by that interface
1008 * because the usage_count of pm runtime is more than 1.
1010 if (!pm_runtime_suspended(dev))
1011 return fimd_activate(ctx, false);
1016 static int fimd_resume(struct device *dev)
1018 struct fimd_context *ctx = get_fimd_context(dev);
1021 * if entered to sleep when lcd panel was on, the usage_count
1022 * of pm runtime would still be 1 so in this case, fimd driver
1023 * should be on directly not drawing on pm runtime interface.
1025 if (!pm_runtime_suspended(dev)) {
1028 ret = fimd_activate(ctx, true);
1033 * in case of dpms on(standby), fimd_apply function will
1034 * be called by encoder's dpms callback to update fimd's
1035 * registers but in case of sleep wakeup, it's not.
1036 * so fimd_apply function should be called at here.
1045 #ifdef CONFIG_PM_RUNTIME
1046 static int fimd_runtime_suspend(struct device *dev)
1048 struct fimd_context *ctx = get_fimd_context(dev);
1050 return fimd_activate(ctx, false);
1053 static int fimd_runtime_resume(struct device *dev)
1055 struct fimd_context *ctx = get_fimd_context(dev);
1057 return fimd_activate(ctx, true);
1061 static struct platform_device_id fimd_driver_ids[] = {
1063 .name = "s3c64xx-fb",
1064 .driver_data = (unsigned long)&s3c64xx_fimd_driver_data,
1066 .name = "exynos4-fb",
1067 .driver_data = (unsigned long)&exynos4_fimd_driver_data,
1069 .name = "exynos5-fb",
1070 .driver_data = (unsigned long)&exynos5_fimd_driver_data,
1075 static const struct dev_pm_ops fimd_pm_ops = {
1076 SET_SYSTEM_SLEEP_PM_OPS(fimd_suspend, fimd_resume)
1077 SET_RUNTIME_PM_OPS(fimd_runtime_suspend, fimd_runtime_resume, NULL)
1080 struct platform_driver fimd_driver = {
1081 .probe = fimd_probe,
1082 .remove = fimd_remove,
1083 .id_table = fimd_driver_ids,
1085 .name = "exynos4-fb",
1086 .owner = THIS_MODULE,
1088 .of_match_table = of_match_ptr(fimd_driver_dt_match),