drivers/gpu/drm/exynos/exynos_drm_fimd.c

   1 /* exynos_drm_fimd.c
   2  *
   3  * Copyright (C) 2011 Samsung Electronics Co.Ltd
   4  * Authors:
   5  *      Joonyoung Shim <jy0922.shim@samsung.com>
   6  *      Inki Dae <inki.dae@samsung.com>
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  *
  13  */
  14 #include <drm/drmP.h>
  15
  16 #include <linux/kernel.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/clk.h>
  19 #include <linux/of.h>
  20 #include <linux/of_device.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/component.h>
  23 #include <linux/mfd/syscon.h>
  24 #include <linux/regmap.h>
  25
  26 #include <video/of_display_timing.h>
  27 #include <video/of_videomode.h>
  28 #include <video/samsung_fimd.h>
  29 #include <drm/exynos_drm.h>
  30
  31 #include "exynos_drm_drv.h"
  32 #include "exynos_drm_fb.h"
  33 #include "exynos_drm_fbdev.h"
  34 #include "exynos_drm_crtc.h"
  35 #include "exynos_drm_plane.h"
  36 #include "exynos_drm_iommu.h"
  37
  38 /*
  39  * FIMD stands for Fully Interactive Mobile Display and
  40  * as a display controller, it transfers contents drawn on memory
  41  * to a LCD Panel through Display Interfaces such as RGB or
  42  * CPU Interface.
  43  */
  44
  45 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128
  46
  47 /* position control register for hardware window 0, 2 ~ 4.*/
  48 #define VIDOSD_A(win)           (VIDOSD_BASE + 0x00 + (win) * 16)
  49 #define VIDOSD_B(win)           (VIDOSD_BASE + 0x04 + (win) * 16)
  50 /*
  51  * size control register for hardware windows 0 and alpha control register
  52  * for hardware windows 1 ~ 4
  53  */
  54 #define VIDOSD_C(win)           (VIDOSD_BASE + 0x08 + (win) * 16)
  55 /* size control register for hardware windows 1 ~ 2. */
  56 #define VIDOSD_D(win)           (VIDOSD_BASE + 0x0C + (win) * 16)
  57
  58 #define VIDWnALPHA0(win)        (VIDW_ALPHA + 0x00 + (win) * 8)
  59 #define VIDWnALPHA1(win)        (VIDW_ALPHA + 0x04 + (win) * 8)
  60
  61 #define VIDWx_BUF_START(win, buf)       (VIDW_BUF_START(buf) + (win) * 8)
  62 #define VIDWx_BUF_START_S(win, buf)     (VIDW_BUF_START_S(buf) + (win) * 8)
  63 #define VIDWx_BUF_END(win, buf)         (VIDW_BUF_END(buf) + (win) * 8)
  64 #define VIDWx_BUF_SIZE(win, buf)        (VIDW_BUF_SIZE(buf) + (win) * 4)
  65
  66 /* color key control register for hardware window 1 ~ 4. */
  67 #define WKEYCON0_BASE(x)                ((WKEYCON0 + 0x140) + ((x - 1) * 8))
  68 /* color key value register for hardware window 1 ~ 4. */
  69 #define WKEYCON1_BASE(x)                ((WKEYCON1 + 0x140) + ((x - 1) * 8))
  70
  71 /* I80 / RGB trigger control register */
  72 #define TRIGCON                         0x1A4
  73 #define TRGMODE_I80_RGB_ENABLE_I80      (1 << 0)
  74 #define SWTRGCMD_I80_RGB_ENABLE         (1 << 1)
  75
  76 /* display mode change control register except exynos4 */
  77 #define VIDOUT_CON                      0x000
  78 #define VIDOUT_CON_F_I80_LDI0           (0x2 << 8)
  79
  80 /* I80 interface control for main LDI register */
  81 #define I80IFCONFAx(x)                  (0x1B0 + (x) * 4)
  82 #define I80IFCONFBx(x)                  (0x1B8 + (x) * 4)
  83 #define LCD_CS_SETUP(x)                 ((x) << 16)
  84 #define LCD_WR_SETUP(x)                 ((x) << 12)
  85 #define LCD_WR_ACTIVE(x)                ((x) << 8)
  86 #define LCD_WR_HOLD(x)                  ((x) << 4)
  87 #define I80IFEN_ENABLE                  (1 << 0)
  88
  89 /* FIMD has totally five hardware windows. */
  90 #define WINDOWS_NR      5
  91
  92 struct fimd_driver_data {
  93         unsigned int timing_base;
  94         unsigned int lcdblk_offset;
  95         unsigned int lcdblk_vt_shift;
  96         unsigned int lcdblk_bypass_shift;
  97         unsigned int lcdblk_mic_bypass_shift;
  98
  99         unsigned int has_shadowcon:1;
 100         unsigned int has_clksel:1;
 101         unsigned int has_limited_fmt:1;
 102         unsigned int has_vidoutcon:1;
 103         unsigned int has_vtsel:1;
 104         unsigned int has_mic_bypass:1;
 105         unsigned int has_dp_clk:1;
 106 };
 107
 108 static struct fimd_driver_data s3c64xx_fimd_driver_data = {
 109         .timing_base = 0x0,
 110         .has_clksel = 1,
 111         .has_limited_fmt = 1,
 112 };
 113
 114 static struct fimd_driver_data exynos3_fimd_driver_data = {
 115         .timing_base = 0x20000,
 116         .lcdblk_offset = 0x210,
 117         .lcdblk_bypass_shift = 1,
 118         .has_shadowcon = 1,
 119         .has_vidoutcon = 1,
 120 };
 121
 122 static struct fimd_driver_data exynos4_fimd_driver_data = {
 123         .timing_base = 0x0,
 124         .lcdblk_offset = 0x210,
 125         .lcdblk_vt_shift = 10,
 126         .lcdblk_bypass_shift = 1,
 127         .has_shadowcon = 1,
 128         .has_vtsel = 1,
 129 };
 130
 131 static struct fimd_driver_data exynos4415_fimd_driver_data = {
 132         .timing_base = 0x20000,
 133         .lcdblk_offset = 0x210,
 134         .lcdblk_vt_shift = 10,
 135         .lcdblk_bypass_shift = 1,
 136         .has_shadowcon = 1,
 137         .has_vidoutcon = 1,
 138         .has_vtsel = 1,
 139 };
 140
 141 static struct fimd_driver_data exynos5_fimd_driver_data = {
 142         .timing_base = 0x20000,
 143         .lcdblk_offset = 0x214,
 144         .lcdblk_vt_shift = 24,
 145         .lcdblk_bypass_shift = 15,
 146         .has_shadowcon = 1,
 147         .has_vidoutcon = 1,
 148         .has_vtsel = 1,
 149         .has_dp_clk = 1,
 150 };
 151
 152 static struct fimd_driver_data exynos5420_fimd_driver_data = {
 153         .timing_base = 0x20000,
 154         .lcdblk_offset = 0x214,
 155         .lcdblk_vt_shift = 24,
 156         .lcdblk_bypass_shift = 15,
 157         .lcdblk_mic_bypass_shift = 11,
 158         .has_shadowcon = 1,
 159         .has_vidoutcon = 1,
 160         .has_vtsel = 1,
 161         .has_mic_bypass = 1,
 162         .has_dp_clk = 1,
 163 };
 164
 165 struct fimd_context {
 166         struct device                   *dev;
 167         struct drm_device               *drm_dev;
 168         struct exynos_drm_crtc          *crtc;
 169         struct exynos_drm_plane         planes[WINDOWS_NR];
 170         struct exynos_drm_plane_config  configs[WINDOWS_NR];
 171         struct clk                      *bus_clk;
 172         struct clk                      *lcd_clk;
 173         void __iomem                    *regs;
 174         struct regmap                   *sysreg;
 175         unsigned long                   irq_flags;
 176         u32                             vidcon0;
 177         u32                             vidcon1;
 178         u32                             vidout_con;
 179         u32                             i80ifcon;
 180         bool                            i80_if;
 181         bool                            suspended;
 182         int                             pipe;
 183         wait_queue_head_t               wait_vsync_queue;
 184         atomic_t                        wait_vsync_event;
 185         atomic_t                        win_updated;
 186         atomic_t                        triggering;
 187
 188         const struct fimd_driver_data *driver_data;
 189         struct drm_encoder *encoder;
 190         struct exynos_drm_clk           dp_clk;
 191 };
 192
 193 static const struct of_device_id fimd_driver_dt_match[] = {
 194         { .compatible = "samsung,s3c6400-fimd",
 195           .data = &s3c64xx_fimd_driver_data },
 196         { .compatible = "samsung,exynos3250-fimd",
 197           .data = &exynos3_fimd_driver_data },
 198         { .compatible = "samsung,exynos4210-fimd",
 199           .data = &exynos4_fimd_driver_data },
 200         { .compatible = "samsung,exynos4415-fimd",
 201           .data = &exynos4415_fimd_driver_data },
 202         { .compatible = "samsung,exynos5250-fimd",
 203           .data = &exynos5_fimd_driver_data },
 204         { .compatible = "samsung,exynos5420-fimd",
 205           .data = &exynos5420_fimd_driver_data },
 206         {},
 207 };
 208 MODULE_DEVICE_TABLE(of, fimd_driver_dt_match);
 209
 210 static const enum drm_plane_type fimd_win_types[WINDOWS_NR] = {
 211         DRM_PLANE_TYPE_PRIMARY,
 212         DRM_PLANE_TYPE_OVERLAY,
 213         DRM_PLANE_TYPE_OVERLAY,
 214         DRM_PLANE_TYPE_OVERLAY,
 215         DRM_PLANE_TYPE_CURSOR,
 216 };
 217
 218 static const uint32_t fimd_formats[] = {
 219         DRM_FORMAT_C8,
 220         DRM_FORMAT_XRGB1555,
 221         DRM_FORMAT_RGB565,
 222         DRM_FORMAT_XRGB8888,
 223         DRM_FORMAT_ARGB8888,
 224 };
 225
 226 static int fimd_enable_vblank(struct exynos_drm_crtc *crtc)
 227 {
 228         struct fimd_context *ctx = crtc->ctx;
 229         u32 val;
 230
 231         if (ctx->suspended)
 232                 return -EPERM;
 233
 234         if (!test_and_set_bit(0, &ctx->irq_flags)) {
 235                 val = readl(ctx->regs + VIDINTCON0);
 236
 237                 val |= VIDINTCON0_INT_ENABLE;
 238
 239                 if (ctx->i80_if) {
 240                         val |= VIDINTCON0_INT_I80IFDONE;
 241                         val |= VIDINTCON0_INT_SYSMAINCON;
 242                         val &= ~VIDINTCON0_INT_SYSSUBCON;
 243                 } else {
 244                         val |= VIDINTCON0_INT_FRAME;
 245
 246                         val &= ~VIDINTCON0_FRAMESEL0_MASK;
 247                         val |= VIDINTCON0_FRAMESEL0_VSYNC;
 248                         val &= ~VIDINTCON0_FRAMESEL1_MASK;
 249                         val |= VIDINTCON0_FRAMESEL1_NONE;
 250                 }
 251
 252                 writel(val, ctx->regs + VIDINTCON0);
 253         }
 254
 255         return 0;
 256 }
 257
 258 static void fimd_disable_vblank(struct exynos_drm_crtc *crtc)
 259 {
 260         struct fimd_context *ctx = crtc->ctx;
 261         u32 val;
 262
 263         if (ctx->suspended)
 264                 return;
 265
 266         if (test_and_clear_bit(0, &ctx->irq_flags)) {
 267                 val = readl(ctx->regs + VIDINTCON0);
 268
 269                 val &= ~VIDINTCON0_INT_ENABLE;
 270
 271                 if (ctx->i80_if) {
 272                         val &= ~VIDINTCON0_INT_I80IFDONE;
 273                         val &= ~VIDINTCON0_INT_SYSMAINCON;
 274                         val &= ~VIDINTCON0_INT_SYSSUBCON;
 275                 } else
 276                         val &= ~VIDINTCON0_INT_FRAME;
 277
 278                 writel(val, ctx->regs + VIDINTCON0);
 279         }
 280 }
 281
 282 static void fimd_wait_for_vblank(struct exynos_drm_crtc *crtc)
 283 {
 284         struct fimd_context *ctx = crtc->ctx;
 285
 286         if (ctx->suspended)
 287                 return;
 288
 289         atomic_set(&ctx->wait_vsync_event, 1);
 290
 291         /*
 292          * wait for FIMD to signal VSYNC interrupt or return after
 293          * timeout which is set to 50ms (refresh rate of 20).
 294          */
 295         if (!wait_event_timeout(ctx->wait_vsync_queue,
 296                                 !atomic_read(&ctx->wait_vsync_event),
 297                                 HZ/20))
 298                 DRM_DEBUG_KMS("vblank wait timed out.\n");
 299 }
 300
 301 static void fimd_enable_video_output(struct fimd_context *ctx, unsigned int win,
 302                                         bool enable)
 303 {
 304         u32 val = readl(ctx->regs + WINCON(win));
 305
 306         if (enable)
 307                 val |= WINCONx_ENWIN;
 308         else
 309                 val &= ~WINCONx_ENWIN;
 310
 311         writel(val, ctx->regs + WINCON(win));
 312 }
 313
 314 static void fimd_enable_shadow_channel_path(struct fimd_context *ctx,
 315                                                 unsigned int win,
 316                                                 bool enable)
 317 {
 318         u32 val = readl(ctx->regs + SHADOWCON);
 319
 320         if (enable)
 321                 val |= SHADOWCON_CHx_ENABLE(win);
 322         else
 323                 val &= ~SHADOWCON_CHx_ENABLE(win);
 324
 325         writel(val, ctx->regs + SHADOWCON);
 326 }
 327
 328 static void fimd_clear_channels(struct exynos_drm_crtc *crtc)
 329 {
 330         struct fimd_context *ctx = crtc->ctx;
 331         unsigned int win, ch_enabled = 0;
 332
 333         DRM_DEBUG_KMS("%s\n", __FILE__);
 334
 335         /* Hardware is in unknown state, so ensure it gets enabled properly */
 336         pm_runtime_get_sync(ctx->dev);
 337
 338         clk_prepare_enable(ctx->bus_clk);
 339         clk_prepare_enable(ctx->lcd_clk);
 340
 341         /* Check if any channel is enabled. */
 342         for (win = 0; win < WINDOWS_NR; win++) {
 343                 u32 val = readl(ctx->regs + WINCON(win));
 344
 345                 if (val & WINCONx_ENWIN) {
 346                         fimd_enable_video_output(ctx, win, false);
 347
 348                         if (ctx->driver_data->has_shadowcon)
 349                                 fimd_enable_shadow_channel_path(ctx, win,
 350                                                                 false);
 351
 352                         ch_enabled = 1;
 353                 }
 354         }
 355
 356         /* Wait for vsync, as disable channel takes effect at next vsync */
 357         if (ch_enabled) {
 358                 int pipe = ctx->pipe;
 359
 360                 /* ensure that vblank interrupt won't be reported to core */
 361                 ctx->suspended = false;
 362                 ctx->pipe = -1;
 363
 364                 fimd_enable_vblank(ctx->crtc);
 365                 fimd_wait_for_vblank(ctx->crtc);
 366                 fimd_disable_vblank(ctx->crtc);
 367
 368                 ctx->suspended = true;
 369                 ctx->pipe = pipe;
 370         }
 371
 372         clk_disable_unprepare(ctx->lcd_clk);
 373         clk_disable_unprepare(ctx->bus_clk);
 374
 375         pm_runtime_put(ctx->dev);
 376 }
 377
 378 static u32 fimd_calc_clkdiv(struct fimd_context *ctx,
 379                 const struct drm_display_mode *mode)
 380 {
 381         unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh;
 382         u32 clkdiv;
 383
 384         if (ctx->i80_if) {
 385                 /*
 386                  * The frame done interrupt should be occurred prior to the
 387                  * next TE signal.
 388                  */
 389                 ideal_clk *= 2;
 390         }
 391
 392         /* Find the clock divider value that gets us closest to ideal_clk */
 393         clkdiv = DIV_ROUND_CLOSEST(clk_get_rate(ctx->lcd_clk), ideal_clk);
 394
 395         return (clkdiv < 0x100) ? clkdiv : 0xff;
 396 }
 397
 398 static void fimd_commit(struct exynos_drm_crtc *crtc)
 399 {
 400         struct fimd_context *ctx = crtc->ctx;
 401         struct drm_display_mode *mode = &crtc->base.state->adjusted_mode;
 402         const struct fimd_driver_data *driver_data = ctx->driver_data;
 403         void *timing_base = ctx->regs + driver_data->timing_base;
 404         u32 val, clkdiv;
 405
 406         if (ctx->suspended)
 407                 return;
 408
 409         /* nothing to do if we haven't set the mode yet */
 410         if (mode->htotal == 0 || mode->vtotal == 0)
 411                 return;
 412
 413         if (ctx->i80_if) {
 414                 val = ctx->i80ifcon | I80IFEN_ENABLE;
 415                 writel(val, timing_base + I80IFCONFAx(0));
 416
 417                 /* disable auto frame rate */
 418                 writel(0, timing_base + I80IFCONFBx(0));
 419
 420                 /* set video type selection to I80 interface */
 421                 if (driver_data->has_vtsel && ctx->sysreg &&
 422                                 regmap_update_bits(ctx->sysreg,
 423                                         driver_data->lcdblk_offset,
 424                                         0x3 << driver_data->lcdblk_vt_shift,
 425                                         0x1 << driver_data->lcdblk_vt_shift)) {
 426                         DRM_ERROR("Failed to update sysreg for I80 i/f.\n");
 427                         return;
 428                 }
 429         } else {
 430                 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd;
 431                 u32 vidcon1;
 432
 433                 /* setup polarity values */
 434                 vidcon1 = ctx->vidcon1;
 435                 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 436                         vidcon1 |= VIDCON1_INV_VSYNC;
 437                 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 438                         vidcon1 |= VIDCON1_INV_HSYNC;
 439                 writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1);
 440
 441                 /* setup vertical timing values. */
 442                 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
 443                 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end;
 444                 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay;
 445
 446                 val = VIDTCON0_VBPD(vbpd - 1) |
 447                         VIDTCON0_VFPD(vfpd - 1) |
 448                         VIDTCON0_VSPW(vsync_len - 1);
 449                 writel(val, ctx->regs + driver_data->timing_base + VIDTCON0);
 450
 451                 /* setup horizontal timing values.  */
 452                 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
 453                 hbpd = mode->crtc_htotal - mode->crtc_hsync_end;
 454                 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay;
 455
 456                 val = VIDTCON1_HBPD(hbpd - 1) |
 457                         VIDTCON1_HFPD(hfpd - 1) |
 458                         VIDTCON1_HSPW(hsync_len - 1);
 459                 writel(val, ctx->regs + driver_data->timing_base + VIDTCON1);
 460         }
 461
 462         if (driver_data->has_vidoutcon)
 463                 writel(ctx->vidout_con, timing_base + VIDOUT_CON);
 464
 465         /* set bypass selection */
 466         if (ctx->sysreg && regmap_update_bits(ctx->sysreg,
 467                                 driver_data->lcdblk_offset,
 468                                 0x1 << driver_data->lcdblk_bypass_shift,
 469                                 0x1 << driver_data->lcdblk_bypass_shift)) {
 470                 DRM_ERROR("Failed to update sysreg for bypass setting.\n");
 471                 return;
 472         }
 473
 474         /* TODO: When MIC is enabled for display path, the lcdblk_mic_bypass
 475          * bit should be cleared.
 476          */
 477         if (driver_data->has_mic_bypass && ctx->sysreg &&
 478             regmap_update_bits(ctx->sysreg,
 479                                 driver_data->lcdblk_offset,
 480                                 0x1 << driver_data->lcdblk_mic_bypass_shift,
 481                                 0x1 << driver_data->lcdblk_mic_bypass_shift)) {
 482                 DRM_ERROR("Failed to update sysreg for bypass mic.\n");
 483                 return;
 484         }
 485
 486         /* setup horizontal and vertical display size. */
 487         val = VIDTCON2_LINEVAL(mode->vdisplay - 1) |
 488                VIDTCON2_HOZVAL(mode->hdisplay - 1) |
 489                VIDTCON2_LINEVAL_E(mode->vdisplay - 1) |
 490                VIDTCON2_HOZVAL_E(mode->hdisplay - 1);
 491         writel(val, ctx->regs + driver_data->timing_base + VIDTCON2);
 492
 493         /*
 494          * fields of register with prefix '_F' would be updated
 495          * at vsync(same as dma start)
 496          */
 497         val = ctx->vidcon0;
 498         val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
 499
 500         if (ctx->driver_data->has_clksel)
 501                 val |= VIDCON0_CLKSEL_LCD;
 502
 503         clkdiv = fimd_calc_clkdiv(ctx, mode);
 504         if (clkdiv > 1)
 505                 val |= VIDCON0_CLKVAL_F(clkdiv - 1) | VIDCON0_CLKDIR;
 506
 507         writel(val, ctx->regs + VIDCON0);
 508 }
 509
 510
 511 static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win,
 512                                 uint32_t pixel_format, int width)
 513 {
 514         unsigned long val;
 515
 516         val = WINCONx_ENWIN;
 517
 518         /*
 519          * In case of s3c64xx, window 0 doesn't support alpha channel.
 520          * So the request format is ARGB8888 then change it to XRGB8888.
 521          */
 522         if (ctx->driver_data->has_limited_fmt && !win) {
 523                 if (pixel_format == DRM_FORMAT_ARGB8888)
 524                         pixel_format = DRM_FORMAT_XRGB8888;
 525         }
 526
 527         switch (pixel_format) {
 528         case DRM_FORMAT_C8:
 529                 val |= WINCON0_BPPMODE_8BPP_PALETTE;
 530                 val |= WINCONx_BURSTLEN_8WORD;
 531                 val |= WINCONx_BYTSWP;
 532                 break;
 533         case DRM_FORMAT_XRGB1555:
 534                 val |= WINCON0_BPPMODE_16BPP_1555;
 535                 val |= WINCONx_HAWSWP;
 536                 val |= WINCONx_BURSTLEN_16WORD;
 537                 break;
 538         case DRM_FORMAT_RGB565:
 539                 val |= WINCON0_BPPMODE_16BPP_565;
 540                 val |= WINCONx_HAWSWP;
 541                 val |= WINCONx_BURSTLEN_16WORD;
 542                 break;
 543         case DRM_FORMAT_XRGB8888:
 544                 val |= WINCON0_BPPMODE_24BPP_888;
 545                 val |= WINCONx_WSWP;
 546                 val |= WINCONx_BURSTLEN_16WORD;
 547                 break;
 548         case DRM_FORMAT_ARGB8888:
 549                 val |= WINCON1_BPPMODE_25BPP_A1888
 550                         | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
 551                 val |= WINCONx_WSWP;
 552                 val |= WINCONx_BURSTLEN_16WORD;
 553                 break;
 554         default:
 555                 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
 556
 557                 val |= WINCON0_BPPMODE_24BPP_888;
 558                 val |= WINCONx_WSWP;
 559                 val |= WINCONx_BURSTLEN_16WORD;
 560                 break;
 561         }
 562
 563         /*
 564          * Setting dma-burst to 16Word causes permanent tearing for very small
 565          * buffers, e.g. cursor buffer. Burst Mode switching which based on
 566          * plane size is not recommended as plane size varies alot towards the
 567          * end of the screen and rapid movement causes unstable DMA, but it is
 568          * still better to change dma-burst than displaying garbage.
 569          */
 570
 571         if (width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
 572                 val &= ~WINCONx_BURSTLEN_MASK;
 573                 val |= WINCONx_BURSTLEN_4WORD;
 574         }
 575
 576         writel(val, ctx->regs + WINCON(win));
 577
 578         /* hardware window 0 doesn't support alpha channel. */
 579         if (win != 0) {
 580                 /* OSD alpha */
 581                 val = VIDISD14C_ALPHA0_R(0xf) |
 582                         VIDISD14C_ALPHA0_G(0xf) |
 583                         VIDISD14C_ALPHA0_B(0xf) |
 584                         VIDISD14C_ALPHA1_R(0xf) |
 585                         VIDISD14C_ALPHA1_G(0xf) |
 586                         VIDISD14C_ALPHA1_B(0xf);
 587
 588                 writel(val, ctx->regs + VIDOSD_C(win));
 589
 590                 val = VIDW_ALPHA_R(0xf) | VIDW_ALPHA_G(0xf) |
 591                         VIDW_ALPHA_G(0xf);
 592                 writel(val, ctx->regs + VIDWnALPHA0(win));
 593                 writel(val, ctx->regs + VIDWnALPHA1(win));
 594         }
 595 }
 596
 597 static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win)
 598 {
 599         unsigned int keycon0 = 0, keycon1 = 0;
 600
 601         keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
 602                         WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
 603
 604         keycon1 = WxKEYCON1_COLVAL(0xffffffff);
 605
 606         writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
 607         writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
 608 }
 609
 610 /**
 611  * shadow_protect_win() - disable updating values from shadow registers at vsync
 612  *
 613  * @win: window to protect registers for
 614  * @protect: 1 to protect (disable updates)
 615  */
 616 static void fimd_shadow_protect_win(struct fimd_context *ctx,
 617                                     unsigned int win, bool protect)
 618 {
 619         u32 reg, bits, val;
 620
 621         /*
 622          * SHADOWCON/PRTCON register is used for enabling timing.
 623          *
 624          * for example, once only width value of a register is set,
 625          * if the dma is started then fimd hardware could malfunction so
 626          * with protect window setting, the register fields with prefix '_F'
 627          * wouldn't be updated at vsync also but updated once unprotect window
 628          * is set.
 629          */
 630
 631         if (ctx->driver_data->has_shadowcon) {
 632                 reg = SHADOWCON;
 633                 bits = SHADOWCON_WINx_PROTECT(win);
 634         } else {
 635                 reg = PRTCON;
 636                 bits = PRTCON_PROTECT;
 637         }
 638
 639         val = readl(ctx->regs + reg);
 640         if (protect)
 641                 val |= bits;
 642         else
 643                 val &= ~bits;
 644         writel(val, ctx->regs + reg);
 645 }
 646
 647 static void fimd_atomic_begin(struct exynos_drm_crtc *crtc)
 648 {
 649         struct fimd_context *ctx = crtc->ctx;
 650         int i;
 651
 652         if (ctx->suspended)
 653                 return;
 654
 655         for (i = 0; i < WINDOWS_NR; i++)
 656                 fimd_shadow_protect_win(ctx, i, true);
 657 }
 658
 659 static void fimd_atomic_flush(struct exynos_drm_crtc *crtc)
 660 {
 661         struct fimd_context *ctx = crtc->ctx;
 662         int i;
 663
 664         if (ctx->suspended)
 665                 return;
 666
 667         for (i = 0; i < WINDOWS_NR; i++)
 668                 fimd_shadow_protect_win(ctx, i, false);
 669 }
 670
 671 static void fimd_update_plane(struct exynos_drm_crtc *crtc,
 672                               struct exynos_drm_plane *plane)
 673 {
 674         struct exynos_drm_plane_state *state =
 675                                 to_exynos_plane_state(plane->base.state);
 676         struct fimd_context *ctx = crtc->ctx;
 677         struct drm_framebuffer *fb = state->base.fb;
 678         dma_addr_t dma_addr;
 679         unsigned long val, size, offset;
 680         unsigned int last_x, last_y, buf_offsize, line_size;
 681         unsigned int win = plane->index;
 682         unsigned int bpp = fb->bits_per_pixel >> 3;
 683         unsigned int pitch = fb->pitches[0];
 684
 685         if (ctx->suspended)
 686                 return;
 687
 688         offset = state->src.x * bpp;
 689         offset += state->src.y * pitch;
 690
 691         /* buffer start address */
 692         dma_addr = exynos_drm_fb_dma_addr(fb, 0) + offset;
 693         val = (unsigned long)dma_addr;
 694         writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
 695
 696         /* buffer end address */
 697         size = pitch * state->crtc.h;
 698         val = (unsigned long)(dma_addr + size);
 699         writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
 700
 701         DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
 702                         (unsigned long)dma_addr, val, size);
 703         DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
 704                         state->crtc.w, state->crtc.h);
 705
 706         /* buffer size */
 707         buf_offsize = pitch - (state->crtc.w * bpp);
 708         line_size = state->crtc.w * bpp;
 709         val = VIDW_BUF_SIZE_OFFSET(buf_offsize) |
 710                 VIDW_BUF_SIZE_PAGEWIDTH(line_size) |
 711                 VIDW_BUF_SIZE_OFFSET_E(buf_offsize) |
 712                 VIDW_BUF_SIZE_PAGEWIDTH_E(line_size);
 713         writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
 714
 715         /* OSD position */
 716         val = VIDOSDxA_TOPLEFT_X(state->crtc.x) |
 717                 VIDOSDxA_TOPLEFT_Y(state->crtc.y) |
 718                 VIDOSDxA_TOPLEFT_X_E(state->crtc.x) |
 719                 VIDOSDxA_TOPLEFT_Y_E(state->crtc.y);
 720         writel(val, ctx->regs + VIDOSD_A(win));
 721
 722         last_x = state->crtc.x + state->crtc.w;
 723         if (last_x)
 724                 last_x--;
 725         last_y = state->crtc.y + state->crtc.h;
 726         if (last_y)
 727                 last_y--;
 728
 729         val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) |
 730                 VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y);
 731
 732         writel(val, ctx->regs + VIDOSD_B(win));
 733
 734         DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
 735                         state->crtc.x, state->crtc.y, last_x, last_y);
 736
 737         /* OSD size */
 738         if (win != 3 && win != 4) {
 739                 u32 offset = VIDOSD_D(win);
 740                 if (win == 0)
 741                         offset = VIDOSD_C(win);
 742                 val = state->crtc.w * state->crtc.h;
 743                 writel(val, ctx->regs + offset);
 744
 745                 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val);
 746         }
 747
 748         fimd_win_set_pixfmt(ctx, win, fb->pixel_format, state->src.w);
 749
 750         /* hardware window 0 doesn't support color key. */
 751         if (win != 0)
 752                 fimd_win_set_colkey(ctx, win);
 753
 754         fimd_enable_video_output(ctx, win, true);
 755
 756         if (ctx->driver_data->has_shadowcon)
 757                 fimd_enable_shadow_channel_path(ctx, win, true);
 758
 759         if (ctx->i80_if)
 760                 atomic_set(&ctx->win_updated, 1);
 761 }
 762
 763 static void fimd_disable_plane(struct exynos_drm_crtc *crtc,
 764                                struct exynos_drm_plane *plane)
 765 {
 766         struct fimd_context *ctx = crtc->ctx;
 767         unsigned int win = plane->index;
 768
 769         if (ctx->suspended)
 770                 return;
 771
 772         fimd_enable_video_output(ctx, win, false);
 773
 774         if (ctx->driver_data->has_shadowcon)
 775                 fimd_enable_shadow_channel_path(ctx, win, false);
 776 }
 777
 778 static void fimd_enable(struct exynos_drm_crtc *crtc)
 779 {
 780         struct fimd_context *ctx = crtc->ctx;
 781
 782         if (!ctx->suspended)
 783                 return;
 784
 785         ctx->suspended = false;
 786
 787         pm_runtime_get_sync(ctx->dev);
 788
 789         /* if vblank was enabled status, enable it again. */
 790         if (test_and_clear_bit(0, &ctx->irq_flags))
 791                 fimd_enable_vblank(ctx->crtc);
 792
 793         fimd_commit(ctx->crtc);
 794 }
 795
 796 static void fimd_disable(struct exynos_drm_crtc *crtc)
 797 {
 798         struct fimd_context *ctx = crtc->ctx;
 799         int i;
 800
 801         if (ctx->suspended)
 802                 return;
 803
 804         /*
 805          * We need to make sure that all windows are disabled before we
 806          * suspend that connector. Otherwise we might try to scan from
 807          * a destroyed buffer later.
 808          */
 809         for (i = 0; i < WINDOWS_NR; i++)
 810                 fimd_disable_plane(crtc, &ctx->planes[i]);
 811
 812         fimd_enable_vblank(crtc);
 813         fimd_wait_for_vblank(crtc);
 814         fimd_disable_vblank(crtc);
 815
 816         writel(0, ctx->regs + VIDCON0);
 817
 818         pm_runtime_put_sync(ctx->dev);
 819         ctx->suspended = true;
 820 }
 821
 822 static void fimd_trigger(struct device *dev)
 823 {
 824         struct fimd_context *ctx = dev_get_drvdata(dev);
 825         const struct fimd_driver_data *driver_data = ctx->driver_data;
 826         void *timing_base = ctx->regs + driver_data->timing_base;
 827         u32 reg;
 828
 829          /*
 830           * Skips triggering if in triggering state, because multiple triggering
 831           * requests can cause panel reset.
 832           */
 833         if (atomic_read(&ctx->triggering))
 834                 return;
 835
 836         /* Enters triggering mode */
 837         atomic_set(&ctx->triggering, 1);
 838
 839         reg = readl(timing_base + TRIGCON);
 840         reg |= (TRGMODE_I80_RGB_ENABLE_I80 | SWTRGCMD_I80_RGB_ENABLE);
 841         writel(reg, timing_base + TRIGCON);
 842
 843         /*
 844          * Exits triggering mode if vblank is not enabled yet, because when the
 845          * VIDINTCON0 register is not set, it can not exit from triggering mode.
 846          */
 847         if (!test_bit(0, &ctx->irq_flags))
 848                 atomic_set(&ctx->triggering, 0);
 849 }
 850
 851 static void fimd_te_handler(struct exynos_drm_crtc *crtc)
 852 {
 853         struct fimd_context *ctx = crtc->ctx;
 854
 855         /* Checks the crtc is detached already from encoder */
 856         if (ctx->pipe < 0 || !ctx->drm_dev)
 857                 return;
 858
 859         /*
 860          * If there is a page flip request, triggers and handles the page flip
 861          * event so that current fb can be updated into panel GRAM.
 862          */
 863         if (atomic_add_unless(&ctx->win_updated, -1, 0))
 864                 fimd_trigger(ctx->dev);
 865
 866         /* Wakes up vsync event queue */
 867         if (atomic_read(&ctx->wait_vsync_event)) {
 868                 atomic_set(&ctx->wait_vsync_event, 0);
 869                 wake_up(&ctx->wait_vsync_queue);
 870         }
 871
 872         if (test_bit(0, &ctx->irq_flags))
 873                 drm_crtc_handle_vblank(&ctx->crtc->base);
 874 }
 875
 876 static void fimd_dp_clock_enable(struct exynos_drm_clk *clk, bool enable)
 877 {
 878         struct fimd_context *ctx = container_of(clk, struct fimd_context,
 879                                                 dp_clk);
 880         u32 val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE;
 881
 882         writel(val, ctx->regs + DP_MIE_CLKCON);
 883 }
 884
 885 static const struct exynos_drm_crtc_ops fimd_crtc_ops = {
 886         .enable = fimd_enable,
 887         .disable = fimd_disable,
 888         .commit = fimd_commit,
 889         .enable_vblank = fimd_enable_vblank,
 890         .disable_vblank = fimd_disable_vblank,
 891         .atomic_begin = fimd_atomic_begin,
 892         .update_plane = fimd_update_plane,
 893         .disable_plane = fimd_disable_plane,
 894         .atomic_flush = fimd_atomic_flush,
 895         .te_handler = fimd_te_handler,
 896 };
 897
 898 static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
 899 {
 900         struct fimd_context *ctx = (struct fimd_context *)dev_id;
 901         u32 val, clear_bit, start, start_s;
 902         int win;
 903
 904         val = readl(ctx->regs + VIDINTCON1);
 905
 906         clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME;
 907         if (val & clear_bit)
 908                 writel(clear_bit, ctx->regs + VIDINTCON1);
 909
 910         /* check the crtc is detached already from encoder */
 911         if (ctx->pipe < 0 || !ctx->drm_dev)
 912                 goto out;
 913
 914         if (!ctx->i80_if)
 915                 drm_crtc_handle_vblank(&ctx->crtc->base);
 916
 917         for (win = 0 ; win < WINDOWS_NR ; win++) {
 918                 struct exynos_drm_plane *plane = &ctx->planes[win];
 919
 920                 if (!plane->pending_fb)
 921                         continue;
 922
 923                 start = readl(ctx->regs + VIDWx_BUF_START(win, 0));
 924                 start_s = readl(ctx->regs + VIDWx_BUF_START_S(win, 0));
 925                 if (start == start_s)
 926                         exynos_drm_crtc_finish_update(ctx->crtc, plane);
 927         }
 928
 929         if (ctx->i80_if) {
 930                 /* Exits triggering mode */
 931                 atomic_set(&ctx->triggering, 0);
 932         } else {
 933                 /* set wait vsync event to zero and wake up queue. */
 934                 if (atomic_read(&ctx->wait_vsync_event)) {
 935                         atomic_set(&ctx->wait_vsync_event, 0);
 936                         wake_up(&ctx->wait_vsync_queue);
 937                 }
 938         }
 939
 940 out:
 941         return IRQ_HANDLED;
 942 }
 943
 944 static int fimd_bind(struct device *dev, struct device *master, void *data)
 945 {
 946         struct fimd_context *ctx = dev_get_drvdata(dev);
 947         struct drm_device *drm_dev = data;
 948         struct exynos_drm_private *priv = drm_dev->dev_private;
 949         struct exynos_drm_plane *exynos_plane;
 950         unsigned int i;
 951         int ret;
 952
 953         ctx->drm_dev = drm_dev;
 954         ctx->pipe = priv->pipe++;
 955
 956         for (i = 0; i < WINDOWS_NR; i++) {
 957                 ctx->configs[i].pixel_formats = fimd_formats;
 958                 ctx->configs[i].num_pixel_formats = ARRAY_SIZE(fimd_formats);
 959                 ctx->configs[i].zpos = i;
 960                 ctx->configs[i].type = fimd_win_types[i];
 961                 ret = exynos_plane_init(drm_dev, &ctx->planes[i], i,
 962                                         1 << ctx->pipe, &ctx->configs[i]);
 963                 if (ret)
 964                         return ret;
 965         }
 966
 967         exynos_plane = &ctx->planes[DEFAULT_WIN];
 968         ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
 969                                            ctx->pipe, EXYNOS_DISPLAY_TYPE_LCD,
 970                                            &fimd_crtc_ops, ctx);
 971         if (IS_ERR(ctx->crtc))
 972                 return PTR_ERR(ctx->crtc);
 973
 974         if (ctx->driver_data->has_dp_clk) {
 975                 ctx->dp_clk.enable = fimd_dp_clock_enable;
 976                 ctx->crtc->pipe_clk = &ctx->dp_clk;
 977         }
 978
 979         if (ctx->encoder)
 980                 exynos_dpi_bind(drm_dev, ctx->encoder);
 981
 982         if (is_drm_iommu_supported(drm_dev))
 983                 fimd_clear_channels(ctx->crtc);
 984
 985         ret = drm_iommu_attach_device(drm_dev, dev);
 986         if (ret)
 987                 priv->pipe--;
 988
 989         return ret;
 990 }
 991
 992 static void fimd_unbind(struct device *dev, struct device *master,
 993                         void *data)
 994 {
 995         struct fimd_context *ctx = dev_get_drvdata(dev);
 996
 997         fimd_disable(ctx->crtc);
 998
 999         drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
1000
1001         if (ctx->encoder)
1002                 exynos_dpi_remove(ctx->encoder);
1003 }
1004
1005 static const struct component_ops fimd_component_ops = {
1006         .bind   = fimd_bind,
1007         .unbind = fimd_unbind,
1008 };
1009
1010 static int fimd_probe(struct platform_device *pdev)
1011 {
1012         struct device *dev = &pdev->dev;
1013         struct fimd_context *ctx;
1014         struct device_node *i80_if_timings;
1015         struct resource *res;
1016         int ret;
1017
1018         if (!dev->of_node)
1019                 return -ENODEV;
1020
1021         ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1022         if (!ctx)
1023                 return -ENOMEM;
1024
1025         ctx->dev = dev;
1026         ctx->suspended = true;
1027         ctx->driver_data = of_device_get_match_data(dev);
1028
1029         if (of_property_read_bool(dev->of_node, "samsung,invert-vden"))
1030                 ctx->vidcon1 |= VIDCON1_INV_VDEN;
1031         if (of_property_read_bool(dev->of_node, "samsung,invert-vclk"))
1032                 ctx->vidcon1 |= VIDCON1_INV_VCLK;
1033
1034         i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings");
1035         if (i80_if_timings) {
1036                 u32 val;
1037
1038                 ctx->i80_if = true;
1039
1040                 if (ctx->driver_data->has_vidoutcon)
1041                         ctx->vidout_con |= VIDOUT_CON_F_I80_LDI0;
1042                 else
1043                         ctx->vidcon0 |= VIDCON0_VIDOUT_I80_LDI0;
1044                 /*
1045                  * The user manual describes that this "DSI_EN" bit is required
1046                  * to enable I80 24-bit data interface.
1047                  */
1048                 ctx->vidcon0 |= VIDCON0_DSI_EN;
1049
1050                 if (of_property_read_u32(i80_if_timings, "cs-setup", &val))
1051                         val = 0;
1052                 ctx->i80ifcon = LCD_CS_SETUP(val);
1053                 if (of_property_read_u32(i80_if_timings, "wr-setup", &val))
1054                         val = 0;
1055                 ctx->i80ifcon |= LCD_WR_SETUP(val);
1056                 if (of_property_read_u32(i80_if_timings, "wr-active", &val))
1057                         val = 1;
1058                 ctx->i80ifcon |= LCD_WR_ACTIVE(val);
1059                 if (of_property_read_u32(i80_if_timings, "wr-hold", &val))
1060                         val = 0;
1061                 ctx->i80ifcon |= LCD_WR_HOLD(val);
1062         }
1063         of_node_put(i80_if_timings);
1064
1065         ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
1066                                                         "samsung,sysreg");
1067         if (IS_ERR(ctx->sysreg)) {
1068                 dev_warn(dev, "failed to get system register.\n");
1069                 ctx->sysreg = NULL;
1070         }
1071
1072         ctx->bus_clk = devm_clk_get(dev, "fimd");
1073         if (IS_ERR(ctx->bus_clk)) {
1074                 dev_err(dev, "failed to get bus clock\n");
1075                 return PTR_ERR(ctx->bus_clk);
1076         }
1077
1078         ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd");
1079         if (IS_ERR(ctx->lcd_clk)) {
1080                 dev_err(dev, "failed to get lcd clock\n");
1081                 return PTR_ERR(ctx->lcd_clk);
1082         }
1083
1084         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1085
1086         ctx->regs = devm_ioremap_resource(dev, res);
1087         if (IS_ERR(ctx->regs))
1088                 return PTR_ERR(ctx->regs);
1089
1090         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1091                                            ctx->i80_if ? "lcd_sys" : "vsync");
1092         if (!res) {
1093                 dev_err(dev, "irq request failed.\n");
1094                 return -ENXIO;
1095         }
1096
1097         ret = devm_request_irq(dev, res->start, fimd_irq_handler,
1098                                                         0, "drm_fimd", ctx);
1099         if (ret) {
1100                 dev_err(dev, "irq request failed.\n");
1101                 return ret;
1102         }
1103
1104         init_waitqueue_head(&ctx->wait_vsync_queue);
1105         atomic_set(&ctx->wait_vsync_event, 0);
1106
1107         platform_set_drvdata(pdev, ctx);
1108
1109         ctx->encoder = exynos_dpi_probe(dev);
1110         if (IS_ERR(ctx->encoder))
1111                 return PTR_ERR(ctx->encoder);
1112
1113         pm_runtime_enable(dev);
1114
1115         ret = component_add(dev, &fimd_component_ops);
1116         if (ret)
1117                 goto err_disable_pm_runtime;
1118
1119         return ret;
1120
1121 err_disable_pm_runtime:
1122         pm_runtime_disable(dev);
1123
1124         return ret;
1125 }
1126
1127 static int fimd_remove(struct platform_device *pdev)
1128 {
1129         pm_runtime_disable(&pdev->dev);
1130
1131         component_del(&pdev->dev, &fimd_component_ops);
1132
1133         return 0;
1134 }
1135
1136 #ifdef CONFIG_PM
1137 static int exynos_fimd_suspend(struct device *dev)
1138 {
1139         struct fimd_context *ctx = dev_get_drvdata(dev);
1140
1141         clk_disable_unprepare(ctx->lcd_clk);
1142         clk_disable_unprepare(ctx->bus_clk);
1143
1144         return 0;
1145 }
1146
1147 static int exynos_fimd_resume(struct device *dev)
1148 {
1149         struct fimd_context *ctx = dev_get_drvdata(dev);
1150         int ret;
1151
1152         ret = clk_prepare_enable(ctx->bus_clk);
1153         if (ret < 0) {
1154                 DRM_ERROR("Failed to prepare_enable the bus clk [%d]\n", ret);
1155                 return ret;
1156         }
1157
1158         ret = clk_prepare_enable(ctx->lcd_clk);
1159         if  (ret < 0) {
1160                 DRM_ERROR("Failed to prepare_enable the lcd clk [%d]\n", ret);
1161                 return ret;
1162         }
1163
1164         return 0;
1165 }
1166 #endif
1167
1168 static const struct dev_pm_ops exynos_fimd_pm_ops = {
1169         SET_RUNTIME_PM_OPS(exynos_fimd_suspend, exynos_fimd_resume, NULL)
1170 };
1171
1172 struct platform_driver fimd_driver = {
1173         .probe          = fimd_probe,
1174         .remove         = fimd_remove,
1175         .driver         = {
1176                 .name   = "exynos4-fb",
1177                 .owner  = THIS_MODULE,
1178                 .pm     = &exynos_fimd_pm_ops,
1179                 .of_match_table = fimd_driver_dt_match,
1180         },
1181 };