drivers/gpu/drm/exynos/exynos_drm_fimd.c

   1 /* exynos_drm_fimd.c
   2  *
   3  * Copyright (C) 2011 Samsung Electronics Co.Ltd
   4  * Authors:
   5  *      Joonyoung Shim <jy0922.shim@samsung.com>
   6  *      Inki Dae <inki.dae@samsung.com>
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  *
  13  */
  14 #include <drm/drmP.h>
  15
  16 #include <linux/kernel.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/clk.h>
  19 #include <linux/of.h>
  20 #include <linux/of_device.h>
  21 #include <linux/pm_runtime.h>
  22
  23 #include <video/of_display_timing.h>
  24 #include <video/of_videomode.h>
  25 #include <video/samsung_fimd.h>
  26 #include <drm/exynos_drm.h>
  27
  28 #include "exynos_drm_drv.h"
  29 #include "exynos_drm_fbdev.h"
  30 #include "exynos_drm_crtc.h"
  31 #include "exynos_drm_iommu.h"
  32
  33 /*
  34  * FIMD is stand for Fully Interactive Mobile Display and
  35  * as a display controller, it transfers contents drawn on memory
  36  * to a LCD Panel through Display Interfaces such as RGB or
  37  * CPU Interface.
  38  */
  39
  40 #define FIMD_DEFAULT_FRAMERATE 60
  41
  42 /* position control register for hardware window 0, 2 ~ 4.*/
  43 #define VIDOSD_A(win)           (VIDOSD_BASE + 0x00 + (win) * 16)
  44 #define VIDOSD_B(win)           (VIDOSD_BASE + 0x04 + (win) * 16)
  45 /*
  46  * size control register for hardware windows 0 and alpha control register
  47  * for hardware windows 1 ~ 4
  48  */
  49 #define VIDOSD_C(win)           (VIDOSD_BASE + 0x08 + (win) * 16)
  50 /* size control register for hardware windows 1 ~ 2. */
  51 #define VIDOSD_D(win)           (VIDOSD_BASE + 0x0C + (win) * 16)
  52
  53 #define VIDWx_BUF_START(win, buf)       (VIDW_BUF_START(buf) + (win) * 8)
  54 #define VIDWx_BUF_END(win, buf)         (VIDW_BUF_END(buf) + (win) * 8)
  55 #define VIDWx_BUF_SIZE(win, buf)        (VIDW_BUF_SIZE(buf) + (win) * 4)
  56
  57 /* color key control register for hardware window 1 ~ 4. */
  58 #define WKEYCON0_BASE(x)                ((WKEYCON0 + 0x140) + ((x - 1) * 8))
  59 /* color key value register for hardware window 1 ~ 4. */
  60 #define WKEYCON1_BASE(x)                ((WKEYCON1 + 0x140) + ((x - 1) * 8))
  61
  62 /* FIMD has totally five hardware windows. */
  63 #define WINDOWS_NR      5
  64
  65 #define get_fimd_context(dev)   platform_get_drvdata(to_platform_device(dev))
  66
  67 struct fimd_driver_data {
  68         unsigned int timing_base;
  69
  70         unsigned int has_shadowcon:1;
  71         unsigned int has_clksel:1;
  72         unsigned int has_limited_fmt:1;
  73 };
  74
  75 static struct fimd_driver_data s3c64xx_fimd_driver_data = {
  76         .timing_base = 0x0,
  77         .has_clksel = 1,
  78         .has_limited_fmt = 1,
  79 };
  80
  81 static struct fimd_driver_data exynos4_fimd_driver_data = {
  82         .timing_base = 0x0,
  83         .has_shadowcon = 1,
  84 };
  85
  86 static struct fimd_driver_data exynos5_fimd_driver_data = {
  87         .timing_base = 0x20000,
  88         .has_shadowcon = 1,
  89 };
  90
  91 struct fimd_win_data {
  92         unsigned int            offset_x;
  93         unsigned int            offset_y;
  94         unsigned int            ovl_width;
  95         unsigned int            ovl_height;
  96         unsigned int            fb_width;
  97         unsigned int            fb_height;
  98         unsigned int            bpp;
  99         unsigned int            pixel_format;
 100         dma_addr_t              dma_addr;
 101         unsigned int            buf_offsize;
 102         unsigned int            line_size;      /* bytes */
 103         bool                    enabled;
 104         bool                    resume;
 105 };
 106
 107 struct fimd_context {
 108         struct exynos_drm_subdrv        subdrv;
 109         int                             irq;
 110         struct drm_crtc                 *crtc;
 111         struct clk                      *bus_clk;
 112         struct clk                      *lcd_clk;
 113         void __iomem                    *regs;
 114         struct fimd_win_data            win_data[WINDOWS_NR];
 115         unsigned int                    clkdiv;
 116         unsigned int                    default_win;
 117         unsigned long                   irq_flags;
 118         u32                             vidcon0;
 119         u32                             vidcon1;
 120         bool                            suspended;
 121         struct mutex                    lock;
 122         wait_queue_head_t               wait_vsync_queue;
 123         atomic_t                        wait_vsync_event;
 124
 125         struct exynos_drm_panel_info *panel;
 126         struct fimd_driver_data *driver_data;
 127 };
 128
 129 #ifdef CONFIG_OF
 130 static const struct of_device_id fimd_driver_dt_match[] = {
 131         { .compatible = "samsung,s3c6400-fimd",
 132           .data = &s3c64xx_fimd_driver_data },
 133         { .compatible = "samsung,exynos4210-fimd",
 134           .data = &exynos4_fimd_driver_data },
 135         { .compatible = "samsung,exynos5250-fimd",
 136           .data = &exynos5_fimd_driver_data },
 137         {},
 138 };
 139 #endif
 140
 141 static inline struct fimd_driver_data *drm_fimd_get_driver_data(
 142         struct platform_device *pdev)
 143 {
 144 #ifdef CONFIG_OF
 145         const struct of_device_id *of_id =
 146                         of_match_device(fimd_driver_dt_match, &pdev->dev);
 147
 148         if (of_id)
 149                 return (struct fimd_driver_data *)of_id->data;
 150 #endif
 151
 152         return (struct fimd_driver_data *)
 153                 platform_get_device_id(pdev)->driver_data;
 154 }
 155
 156 static bool fimd_display_is_connected(struct device *dev)
 157 {
 158         /* TODO. */
 159
 160         return true;
 161 }
 162
 163 static void *fimd_get_panel(struct device *dev)
 164 {
 165         struct fimd_context *ctx = get_fimd_context(dev);
 166
 167         return ctx->panel;
 168 }
 169
 170 static int fimd_check_mode(struct device *dev, struct drm_display_mode *mode)
 171 {
 172         /* TODO. */
 173
 174         return 0;
 175 }
 176
 177 static int fimd_display_power_on(struct device *dev, int mode)
 178 {
 179         /* TODO */
 180
 181         return 0;
 182 }
 183
 184 static struct exynos_drm_display_ops fimd_display_ops = {
 185         .type = EXYNOS_DISPLAY_TYPE_LCD,
 186         .is_connected = fimd_display_is_connected,
 187         .get_panel = fimd_get_panel,
 188         .check_mode = fimd_check_mode,
 189         .power_on = fimd_display_power_on,
 190 };
 191
 192 static void fimd_dpms(struct device *subdrv_dev, int mode)
 193 {
 194         struct fimd_context *ctx = get_fimd_context(subdrv_dev);
 195
 196         DRM_DEBUG_KMS("%d\n", mode);
 197
 198         mutex_lock(&ctx->lock);
 199
 200         switch (mode) {
 201         case DRM_MODE_DPMS_ON:
 202                 /*
 203                  * enable fimd hardware only if suspended status.
 204                  *
 205                  * P.S. fimd_dpms function would be called at booting time so
 206                  * clk_enable could be called double time.
 207                  */
 208                 if (ctx->suspended)
 209                         pm_runtime_get_sync(subdrv_dev);
 210                 break;
 211         case DRM_MODE_DPMS_STANDBY:
 212         case DRM_MODE_DPMS_SUSPEND:
 213         case DRM_MODE_DPMS_OFF:
 214                 if (!ctx->suspended)
 215                         pm_runtime_put_sync(subdrv_dev);
 216                 break;
 217         default:
 218                 DRM_DEBUG_KMS("unspecified mode %d\n", mode);
 219                 break;
 220         }
 221
 222         mutex_unlock(&ctx->lock);
 223 }
 224
 225 static void fimd_apply(struct device *subdrv_dev)
 226 {
 227         struct fimd_context *ctx = get_fimd_context(subdrv_dev);
 228         struct exynos_drm_manager *mgr = ctx->subdrv.manager;
 229         struct exynos_drm_manager_ops *mgr_ops = mgr->ops;
 230         struct exynos_drm_overlay_ops *ovl_ops = mgr->overlay_ops;
 231         struct fimd_win_data *win_data;
 232         int i;
 233
 234         for (i = 0; i < WINDOWS_NR; i++) {
 235                 win_data = &ctx->win_data[i];
 236                 if (win_data->enabled && (ovl_ops && ovl_ops->commit))
 237                         ovl_ops->commit(subdrv_dev, i);
 238         }
 239
 240         if (mgr_ops && mgr_ops->commit)
 241                 mgr_ops->commit(subdrv_dev);
 242 }
 243
 244 static void fimd_commit(struct device *dev)
 245 {
 246         struct fimd_context *ctx = get_fimd_context(dev);
 247         struct exynos_drm_panel_info *panel = ctx->panel;
 248         struct videomode *vm = &panel->vm;
 249         struct fimd_driver_data *driver_data;
 250         u32 val;
 251
 252         driver_data = ctx->driver_data;
 253         if (ctx->suspended)
 254                 return;
 255
 256         /* setup polarity values from machine code. */
 257         writel(ctx->vidcon1, ctx->regs + driver_data->timing_base + VIDCON1);
 258
 259         /* setup vertical timing values. */
 260         val = VIDTCON0_VBPD(vm->vback_porch - 1) |
 261                VIDTCON0_VFPD(vm->vfront_porch - 1) |
 262                VIDTCON0_VSPW(vm->vsync_len - 1);
 263         writel(val, ctx->regs + driver_data->timing_base + VIDTCON0);
 264
 265         /* setup horizontal timing values.  */
 266         val = VIDTCON1_HBPD(vm->hback_porch - 1) |
 267                VIDTCON1_HFPD(vm->hfront_porch - 1) |
 268                VIDTCON1_HSPW(vm->hsync_len - 1);
 269         writel(val, ctx->regs + driver_data->timing_base + VIDTCON1);
 270
 271         /* setup horizontal and vertical display size. */
 272         val = VIDTCON2_LINEVAL(vm->vactive - 1) |
 273                VIDTCON2_HOZVAL(vm->hactive - 1) |
 274                VIDTCON2_LINEVAL_E(vm->vactive - 1) |
 275                VIDTCON2_HOZVAL_E(vm->hactive - 1);
 276         writel(val, ctx->regs + driver_data->timing_base + VIDTCON2);
 277
 278         /* setup clock source, clock divider, enable dma. */
 279         val = ctx->vidcon0;
 280         val &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR);
 281
 282         if (ctx->driver_data->has_clksel) {
 283                 val &= ~VIDCON0_CLKSEL_MASK;
 284                 val |= VIDCON0_CLKSEL_LCD;
 285         }
 286
 287         if (ctx->clkdiv > 1)
 288                 val |= VIDCON0_CLKVAL_F(ctx->clkdiv - 1) | VIDCON0_CLKDIR;
 289         else
 290                 val &= ~VIDCON0_CLKDIR; /* 1:1 clock */
 291
 292         /*
 293          * fields of register with prefix '_F' would be updated
 294          * at vsync(same as dma start)
 295          */
 296         val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
 297         writel(val, ctx->regs + VIDCON0);
 298 }
 299
 300 static int fimd_enable_vblank(struct device *dev)
 301 {
 302         struct fimd_context *ctx = get_fimd_context(dev);
 303         u32 val;
 304
 305         if (ctx->suspended)
 306                 return -EPERM;
 307
 308         if (!test_and_set_bit(0, &ctx->irq_flags)) {
 309                 val = readl(ctx->regs + VIDINTCON0);
 310
 311                 val |= VIDINTCON0_INT_ENABLE;
 312                 val |= VIDINTCON0_INT_FRAME;
 313
 314                 val &= ~VIDINTCON0_FRAMESEL0_MASK;
 315                 val |= VIDINTCON0_FRAMESEL0_VSYNC;
 316                 val &= ~VIDINTCON0_FRAMESEL1_MASK;
 317                 val |= VIDINTCON0_FRAMESEL1_NONE;
 318
 319                 writel(val, ctx->regs + VIDINTCON0);
 320         }
 321
 322         return 0;
 323 }
 324
 325 static void fimd_disable_vblank(struct device *dev)
 326 {
 327         struct fimd_context *ctx = get_fimd_context(dev);
 328         u32 val;
 329
 330         if (ctx->suspended)
 331                 return;
 332
 333         if (test_and_clear_bit(0, &ctx->irq_flags)) {
 334                 val = readl(ctx->regs + VIDINTCON0);
 335
 336                 val &= ~VIDINTCON0_INT_FRAME;
 337                 val &= ~VIDINTCON0_INT_ENABLE;
 338
 339                 writel(val, ctx->regs + VIDINTCON0);
 340         }
 341 }
 342
 343 static void fimd_wait_for_vblank(struct device *dev)
 344 {
 345         struct fimd_context *ctx = get_fimd_context(dev);
 346
 347         if (ctx->suspended)
 348                 return;
 349
 350         atomic_set(&ctx->wait_vsync_event, 1);
 351
 352         /*
 353          * wait for FIMD to signal VSYNC interrupt or return after
 354          * timeout which is set to 50ms (refresh rate of 20).
 355          */
 356         if (!wait_event_timeout(ctx->wait_vsync_queue,
 357                                 !atomic_read(&ctx->wait_vsync_event),
 358                                 DRM_HZ/20))
 359                 DRM_DEBUG_KMS("vblank wait timed out.\n");
 360 }
 361
 362 static struct exynos_drm_manager_ops fimd_manager_ops = {
 363         .dpms = fimd_dpms,
 364         .apply = fimd_apply,
 365         .commit = fimd_commit,
 366         .enable_vblank = fimd_enable_vblank,
 367         .disable_vblank = fimd_disable_vblank,
 368         .wait_for_vblank = fimd_wait_for_vblank,
 369 };
 370
 371 static void fimd_win_mode_set(struct device *dev,
 372                               struct exynos_drm_overlay *overlay)
 373 {
 374         struct fimd_context *ctx = get_fimd_context(dev);
 375         struct fimd_win_data *win_data;
 376         int win;
 377         unsigned long offset;
 378
 379         if (!overlay) {
 380                 dev_err(dev, "overlay is NULL\n");
 381                 return;
 382         }
 383
 384         win = overlay->zpos;
 385         if (win == DEFAULT_ZPOS)
 386                 win = ctx->default_win;
 387
 388         if (win < 0 || win >= WINDOWS_NR)
 389                 return;
 390
 391         offset = overlay->fb_x * (overlay->bpp >> 3);
 392         offset += overlay->fb_y * overlay->pitch;
 393
 394         DRM_DEBUG_KMS("offset = 0x%lx, pitch = %x\n", offset, overlay->pitch);
 395
 396         win_data = &ctx->win_data[win];
 397
 398         win_data->offset_x = overlay->crtc_x;
 399         win_data->offset_y = overlay->crtc_y;
 400         win_data->ovl_width = overlay->crtc_width;
 401         win_data->ovl_height = overlay->crtc_height;
 402         win_data->fb_width = overlay->fb_width;
 403         win_data->fb_height = overlay->fb_height;
 404         win_data->dma_addr = overlay->dma_addr[0] + offset;
 405         win_data->bpp = overlay->bpp;
 406         win_data->pixel_format = overlay->pixel_format;
 407         win_data->buf_offsize = (overlay->fb_width - overlay->crtc_width) *
 408                                 (overlay->bpp >> 3);
 409         win_data->line_size = overlay->crtc_width * (overlay->bpp >> 3);
 410
 411         DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n",
 412                         win_data->offset_x, win_data->offset_y);
 413         DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
 414                         win_data->ovl_width, win_data->ovl_height);
 415         DRM_DEBUG_KMS("paddr = 0x%lx\n", (unsigned long)win_data->dma_addr);
 416         DRM_DEBUG_KMS("fb_width = %d, crtc_width = %d\n",
 417                         overlay->fb_width, overlay->crtc_width);
 418 }
 419
 420 static void fimd_win_set_pixfmt(struct device *dev, unsigned int win)
 421 {
 422         struct fimd_context *ctx = get_fimd_context(dev);
 423         struct fimd_win_data *win_data = &ctx->win_data[win];
 424         unsigned long val;
 425
 426         val = WINCONx_ENWIN;
 427
 428         /*
 429          * In case of s3c64xx, window 0 doesn't support alpha channel.
 430          * So the request format is ARGB8888 then change it to XRGB8888.
 431          */
 432         if (ctx->driver_data->has_limited_fmt && !win) {
 433                 if (win_data->pixel_format == DRM_FORMAT_ARGB8888)
 434                         win_data->pixel_format = DRM_FORMAT_XRGB8888;
 435         }
 436
 437         switch (win_data->pixel_format) {
 438         case DRM_FORMAT_C8:
 439                 val |= WINCON0_BPPMODE_8BPP_PALETTE;
 440                 val |= WINCONx_BURSTLEN_8WORD;
 441                 val |= WINCONx_BYTSWP;
 442                 break;
 443         case DRM_FORMAT_XRGB1555:
 444                 val |= WINCON0_BPPMODE_16BPP_1555;
 445                 val |= WINCONx_HAWSWP;
 446                 val |= WINCONx_BURSTLEN_16WORD;
 447                 break;
 448         case DRM_FORMAT_RGB565:
 449                 val |= WINCON0_BPPMODE_16BPP_565;
 450                 val |= WINCONx_HAWSWP;
 451                 val |= WINCONx_BURSTLEN_16WORD;
 452                 break;
 453         case DRM_FORMAT_XRGB8888:
 454                 val |= WINCON0_BPPMODE_24BPP_888;
 455                 val |= WINCONx_WSWP;
 456                 val |= WINCONx_BURSTLEN_16WORD;
 457                 break;
 458         case DRM_FORMAT_ARGB8888:
 459                 val |= WINCON1_BPPMODE_25BPP_A1888
 460                         | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
 461                 val |= WINCONx_WSWP;
 462                 val |= WINCONx_BURSTLEN_16WORD;
 463                 break;
 464         default:
 465                 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
 466
 467                 val |= WINCON0_BPPMODE_24BPP_888;
 468                 val |= WINCONx_WSWP;
 469                 val |= WINCONx_BURSTLEN_16WORD;
 470                 break;
 471         }
 472
 473         DRM_DEBUG_KMS("bpp = %d\n", win_data->bpp);
 474
 475         writel(val, ctx->regs + WINCON(win));
 476 }
 477
 478 static void fimd_win_set_colkey(struct device *dev, unsigned int win)
 479 {
 480         struct fimd_context *ctx = get_fimd_context(dev);
 481         unsigned int keycon0 = 0, keycon1 = 0;
 482
 483         keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
 484                         WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
 485
 486         keycon1 = WxKEYCON1_COLVAL(0xffffffff);
 487
 488         writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
 489         writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
 490 }
 491
 492 /**
 493  * shadow_protect_win() - disable updating values from shadow registers at vsync
 494  *
 495  * @win: window to protect registers for
 496  * @protect: 1 to protect (disable updates)
 497  */
 498 static void fimd_shadow_protect_win(struct fimd_context *ctx,
 499                                                         int win, bool protect)
 500 {
 501         u32 reg, bits, val;
 502
 503         if (ctx->driver_data->has_shadowcon) {
 504                 reg = SHADOWCON;
 505                 bits = SHADOWCON_WINx_PROTECT(win);
 506         } else {
 507                 reg = PRTCON;
 508                 bits = PRTCON_PROTECT;
 509         }
 510
 511         val = readl(ctx->regs + reg);
 512         if (protect)
 513                 val |= bits;
 514         else
 515                 val &= ~bits;
 516         writel(val, ctx->regs + reg);
 517 }
 518
 519 static void fimd_win_commit(struct device *dev, int zpos)
 520 {
 521         struct fimd_context *ctx = get_fimd_context(dev);
 522         struct fimd_win_data *win_data;
 523         int win = zpos;
 524         unsigned long val, alpha, size;
 525         unsigned int last_x;
 526         unsigned int last_y;
 527
 528         if (ctx->suspended)
 529                 return;
 530
 531         if (win == DEFAULT_ZPOS)
 532                 win = ctx->default_win;
 533
 534         if (win < 0 || win >= WINDOWS_NR)
 535                 return;
 536
 537         win_data = &ctx->win_data[win];
 538
 539         /*
 540          * SHADOWCON/PRTCON register is used for enabling timing.
 541          *
 542          * for example, once only width value of a register is set,
 543          * if the dma is started then fimd hardware could malfunction so
 544          * with protect window setting, the register fields with prefix '_F'
 545          * wouldn't be updated at vsync also but updated once unprotect window
 546          * is set.
 547          */
 548
 549         /* protect windows */
 550         fimd_shadow_protect_win(ctx, win, true);
 551
 552         /* buffer start address */
 553         val = (unsigned long)win_data->dma_addr;
 554         writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
 555
 556         /* buffer end address */
 557         size = win_data->fb_width * win_data->ovl_height * (win_data->bpp >> 3);
 558         val = (unsigned long)(win_data->dma_addr + size);
 559         writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
 560
 561         DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
 562                         (unsigned long)win_data->dma_addr, val, size);
 563         DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
 564                         win_data->ovl_width, win_data->ovl_height);
 565
 566         /* buffer size */
 567         val = VIDW_BUF_SIZE_OFFSET(win_data->buf_offsize) |
 568                 VIDW_BUF_SIZE_PAGEWIDTH(win_data->line_size) |
 569                 VIDW_BUF_SIZE_OFFSET_E(win_data->buf_offsize) |
 570                 VIDW_BUF_SIZE_PAGEWIDTH_E(win_data->line_size);
 571         writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
 572
 573         /* OSD position */
 574         val = VIDOSDxA_TOPLEFT_X(win_data->offset_x) |
 575                 VIDOSDxA_TOPLEFT_Y(win_data->offset_y) |
 576                 VIDOSDxA_TOPLEFT_X_E(win_data->offset_x) |
 577                 VIDOSDxA_TOPLEFT_Y_E(win_data->offset_y);
 578         writel(val, ctx->regs + VIDOSD_A(win));
 579
 580         last_x = win_data->offset_x + win_data->ovl_width;
 581         if (last_x)
 582                 last_x--;
 583         last_y = win_data->offset_y + win_data->ovl_height;
 584         if (last_y)
 585                 last_y--;
 586
 587         val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) |
 588                 VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y);
 589
 590         writel(val, ctx->regs + VIDOSD_B(win));
 591
 592         DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
 593                         win_data->offset_x, win_data->offset_y, last_x, last_y);
 594
 595         /* hardware window 0 doesn't support alpha channel. */
 596         if (win != 0) {
 597                 /* OSD alpha */
 598                 alpha = VIDISD14C_ALPHA1_R(0xf) |
 599                         VIDISD14C_ALPHA1_G(0xf) |
 600                         VIDISD14C_ALPHA1_B(0xf);
 601
 602                 writel(alpha, ctx->regs + VIDOSD_C(win));
 603         }
 604
 605         /* OSD size */
 606         if (win != 3 && win != 4) {
 607                 u32 offset = VIDOSD_D(win);
 608                 if (win == 0)
 609                         offset = VIDOSD_C(win);
 610                 val = win_data->ovl_width * win_data->ovl_height;
 611                 writel(val, ctx->regs + offset);
 612
 613                 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val);
 614         }
 615
 616         fimd_win_set_pixfmt(dev, win);
 617
 618         /* hardware window 0 doesn't support color key. */
 619         if (win != 0)
 620                 fimd_win_set_colkey(dev, win);
 621
 622         /* wincon */
 623         val = readl(ctx->regs + WINCON(win));
 624         val |= WINCONx_ENWIN;
 625         writel(val, ctx->regs + WINCON(win));
 626
 627         /* Enable DMA channel and unprotect windows */
 628         fimd_shadow_protect_win(ctx, win, false);
 629
 630         if (ctx->driver_data->has_shadowcon) {
 631                 val = readl(ctx->regs + SHADOWCON);
 632                 val |= SHADOWCON_CHx_ENABLE(win);
 633                 writel(val, ctx->regs + SHADOWCON);
 634         }
 635
 636         win_data->enabled = true;
 637 }
 638
 639 static void fimd_win_disable(struct device *dev, int zpos)
 640 {
 641         struct fimd_context *ctx = get_fimd_context(dev);
 642         struct fimd_win_data *win_data;
 643         int win = zpos;
 644         u32 val;
 645
 646         if (win == DEFAULT_ZPOS)
 647                 win = ctx->default_win;
 648
 649         if (win < 0 || win >= WINDOWS_NR)
 650                 return;
 651
 652         win_data = &ctx->win_data[win];
 653
 654         if (ctx->suspended) {
 655                 /* do not resume this window*/
 656                 win_data->resume = false;
 657                 return;
 658         }
 659
 660         /* protect windows */
 661         fimd_shadow_protect_win(ctx, win, true);
 662
 663         /* wincon */
 664         val = readl(ctx->regs + WINCON(win));
 665         val &= ~WINCONx_ENWIN;
 666         writel(val, ctx->regs + WINCON(win));
 667
 668         /* unprotect windows */
 669         if (ctx->driver_data->has_shadowcon) {
 670                 val = readl(ctx->regs + SHADOWCON);
 671                 val &= ~SHADOWCON_CHx_ENABLE(win);
 672                 writel(val, ctx->regs + SHADOWCON);
 673         }
 674
 675         fimd_shadow_protect_win(ctx, win, false);
 676
 677         win_data->enabled = false;
 678 }
 679
 680 static struct exynos_drm_overlay_ops fimd_overlay_ops = {
 681         .mode_set = fimd_win_mode_set,
 682         .commit = fimd_win_commit,
 683         .disable = fimd_win_disable,
 684 };
 685
 686 static struct exynos_drm_manager fimd_manager = {
 687         .pipe           = -1,
 688         .ops            = &fimd_manager_ops,
 689         .overlay_ops    = &fimd_overlay_ops,
 690         .display_ops    = &fimd_display_ops,
 691 };
 692
 693 static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
 694 {
 695         struct fimd_context *ctx = (struct fimd_context *)dev_id;
 696         struct exynos_drm_subdrv *subdrv = &ctx->subdrv;
 697         struct drm_device *drm_dev = subdrv->drm_dev;
 698         struct exynos_drm_manager *manager = subdrv->manager;
 699         u32 val;
 700
 701         val = readl(ctx->regs + VIDINTCON1);
 702
 703         if (val & VIDINTCON1_INT_FRAME)
 704                 /* VSYNC interrupt */
 705                 writel(VIDINTCON1_INT_FRAME, ctx->regs + VIDINTCON1);
 706
 707         /* check the crtc is detached already from encoder */
 708         if (manager->pipe < 0)
 709                 goto out;
 710
 711         drm_handle_vblank(drm_dev, manager->pipe);
 712         exynos_drm_crtc_finish_pageflip(drm_dev, manager->pipe);
 713
 714         /* set wait vsync event to zero and wake up queue. */
 715         if (atomic_read(&ctx->wait_vsync_event)) {
 716                 atomic_set(&ctx->wait_vsync_event, 0);
 717                 DRM_WAKEUP(&ctx->wait_vsync_queue);
 718         }
 719 out:
 720         return IRQ_HANDLED;
 721 }
 722
 723 static int fimd_subdrv_probe(struct drm_device *drm_dev, struct device *dev)
 724 {
 725         /*
 726          * enable drm irq mode.
 727          * - with irq_enabled = 1, we can use the vblank feature.
 728          *
 729          * P.S. note that we wouldn't use drm irq handler but
 730          *      just specific driver own one instead because
 731          *      drm framework supports only one irq handler.
 732          */
 733         drm_dev->irq_enabled = 1;
 734
 735         /*
 736          * with vblank_disable_allowed = 1, vblank interrupt will be disabled
 737          * by drm timer once a current process gives up ownership of
 738          * vblank event.(after drm_vblank_put function is called)
 739          */
 740         drm_dev->vblank_disable_allowed = 1;
 741
 742         /* attach this sub driver to iommu mapping if supported. */
 743         if (is_drm_iommu_supported(drm_dev))
 744                 drm_iommu_attach_device(drm_dev, dev);
 745
 746         return 0;
 747 }
 748
 749 static void fimd_subdrv_remove(struct drm_device *drm_dev, struct device *dev)
 750 {
 751         /* detach this sub driver from iommu mapping if supported. */
 752         if (is_drm_iommu_supported(drm_dev))
 753                 drm_iommu_detach_device(drm_dev, dev);
 754 }
 755
 756 static int fimd_configure_clocks(struct fimd_context *ctx, struct device *dev)
 757 {
 758         struct videomode *vm = &ctx->panel->vm;
 759         unsigned long clk;
 760
 761         ctx->bus_clk = devm_clk_get(dev, "fimd");
 762         if (IS_ERR(ctx->bus_clk)) {
 763                 dev_err(dev, "failed to get bus clock\n");
 764                 return PTR_ERR(ctx->bus_clk);
 765         }
 766
 767         ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd");
 768         if (IS_ERR(ctx->lcd_clk)) {
 769                 dev_err(dev, "failed to get lcd clock\n");
 770                 return PTR_ERR(ctx->lcd_clk);
 771         }
 772
 773         clk = clk_get_rate(ctx->lcd_clk);
 774         if (clk == 0) {
 775                 dev_err(dev, "error getting sclk_fimd clock rate\n");
 776                 return -EINVAL;
 777         }
 778
 779         if (vm->pixelclock == 0) {
 780                 unsigned long c;
 781                 c = vm->hactive + vm->hback_porch + vm->hfront_porch +
 782                     vm->hsync_len;
 783                 c *= vm->vactive + vm->vback_porch + vm->vfront_porch +
 784                      vm->vsync_len;
 785                 vm->pixelclock = c * FIMD_DEFAULT_FRAMERATE;
 786                 if (vm->pixelclock == 0) {
 787                         dev_err(dev, "incorrect display timings\n");
 788                         return -EINVAL;
 789                 }
 790                 dev_warn(dev, "pixel clock recalculated to %luHz (%dHz frame rate)\n",
 791                          vm->pixelclock, FIMD_DEFAULT_FRAMERATE);
 792         }
 793         ctx->clkdiv = DIV_ROUND_UP(clk, vm->pixelclock);
 794         if (ctx->clkdiv > 256) {
 795                 dev_warn(dev, "calculated pixel clock divider too high (%u), lowered to 256\n",
 796                          ctx->clkdiv);
 797                 ctx->clkdiv = 256;
 798         }
 799         vm->pixelclock = clk / ctx->clkdiv;
 800         DRM_DEBUG_KMS("pixel clock = %lu, clkdiv = %d\n", vm->pixelclock,
 801                       ctx->clkdiv);
 802
 803         return 0;
 804 }
 805
 806 static void fimd_clear_win(struct fimd_context *ctx, int win)
 807 {
 808         writel(0, ctx->regs + WINCON(win));
 809         writel(0, ctx->regs + VIDOSD_A(win));
 810         writel(0, ctx->regs + VIDOSD_B(win));
 811         writel(0, ctx->regs + VIDOSD_C(win));
 812
 813         if (win == 1 || win == 2)
 814                 writel(0, ctx->regs + VIDOSD_D(win));
 815
 816         fimd_shadow_protect_win(ctx, win, false);
 817 }
 818
 819 static int fimd_clock(struct fimd_context *ctx, bool enable)
 820 {
 821         if (enable) {
 822                 int ret;
 823
 824                 ret = clk_prepare_enable(ctx->bus_clk);
 825                 if (ret < 0)
 826                         return ret;
 827
 828                 ret = clk_prepare_enable(ctx->lcd_clk);
 829                 if  (ret < 0) {
 830                         clk_disable_unprepare(ctx->bus_clk);
 831                         return ret;
 832                 }
 833         } else {
 834                 clk_disable_unprepare(ctx->lcd_clk);
 835                 clk_disable_unprepare(ctx->bus_clk);
 836         }
 837
 838         return 0;
 839 }
 840
 841 static void fimd_window_suspend(struct device *dev)
 842 {
 843         struct fimd_context *ctx = get_fimd_context(dev);
 844         struct fimd_win_data *win_data;
 845         int i;
 846
 847         for (i = 0; i < WINDOWS_NR; i++) {
 848                 win_data = &ctx->win_data[i];
 849                 win_data->resume = win_data->enabled;
 850                 fimd_win_disable(dev, i);
 851         }
 852         fimd_wait_for_vblank(dev);
 853 }
 854
 855 static void fimd_window_resume(struct device *dev)
 856 {
 857         struct fimd_context *ctx = get_fimd_context(dev);
 858         struct fimd_win_data *win_data;
 859         int i;
 860
 861         for (i = 0; i < WINDOWS_NR; i++) {
 862                 win_data = &ctx->win_data[i];
 863                 win_data->enabled = win_data->resume;
 864                 win_data->resume = false;
 865         }
 866 }
 867
 868 static int fimd_activate(struct fimd_context *ctx, bool enable)
 869 {
 870         struct device *dev = ctx->subdrv.dev;
 871         if (enable) {
 872                 int ret;
 873
 874                 ret = fimd_clock(ctx, true);
 875                 if (ret < 0)
 876                         return ret;
 877
 878                 ctx->suspended = false;
 879
 880                 /* if vblank was enabled status, enable it again. */
 881                 if (test_and_clear_bit(0, &ctx->irq_flags))
 882                         fimd_enable_vblank(dev);
 883
 884                 fimd_window_resume(dev);
 885         } else {
 886                 fimd_window_suspend(dev);
 887
 888                 fimd_clock(ctx, false);
 889                 ctx->suspended = true;
 890         }
 891
 892         return 0;
 893 }
 894
 895 static int fimd_probe(struct platform_device *pdev)
 896 {
 897         struct device *dev = &pdev->dev;
 898         struct fimd_context *ctx;
 899         struct exynos_drm_subdrv *subdrv;
 900         struct exynos_drm_fimd_pdata *pdata;
 901         struct exynos_drm_panel_info *panel;
 902         struct resource *res;
 903         int win;
 904         int ret = -EINVAL;
 905
 906         if (dev->of_node) {
 907                 struct videomode *vm;
 908                 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
 909                 if (!pdata)
 910                         return -ENOMEM;
 911
 912                 vm = &pdata->panel.vm;
 913                 ret = of_get_videomode(dev->of_node, vm, OF_USE_NATIVE_MODE);
 914                 if (ret) {
 915                         DRM_ERROR("failed: of_get_videomode() : %d\n", ret);
 916                         return ret;
 917                 }
 918
 919                 if (vm->flags & DISPLAY_FLAGS_VSYNC_LOW)
 920                         pdata->vidcon1 |= VIDCON1_INV_VSYNC;
 921                 if (vm->flags & DISPLAY_FLAGS_HSYNC_LOW)
 922                         pdata->vidcon1 |= VIDCON1_INV_HSYNC;
 923                 if (vm->flags & DISPLAY_FLAGS_DE_LOW)
 924                         pdata->vidcon1 |= VIDCON1_INV_VDEN;
 925                 if (vm->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
 926                         pdata->vidcon1 |= VIDCON1_INV_VCLK;
 927         } else {
 928                 pdata = dev->platform_data;
 929                 if (!pdata) {
 930                         DRM_ERROR("no platform data specified\n");
 931                         return -EINVAL;
 932                 }
 933         }
 934
 935         panel = &pdata->panel;
 936         if (!panel) {
 937                 dev_err(dev, "panel is null.\n");
 938                 return -EINVAL;
 939         }
 940
 941         ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
 942         if (!ctx)
 943                 return -ENOMEM;
 944
 945         ret = fimd_configure_clocks(ctx, dev);
 946         if (ret)
 947                 return ret;
 948
 949         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 950
 951         ctx->regs = devm_ioremap_resource(dev, res);
 952         if (IS_ERR(ctx->regs))
 953                 return PTR_ERR(ctx->regs);
 954
 955         res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "vsync");
 956         if (!res) {
 957                 dev_err(dev, "irq request failed.\n");
 958                 return -ENXIO;
 959         }
 960
 961         ctx->irq = res->start;
 962
 963         ret = devm_request_irq(dev, ctx->irq, fimd_irq_handler,
 964                                                         0, "drm_fimd", ctx);
 965         if (ret) {
 966                 dev_err(dev, "irq request failed.\n");
 967                 return ret;
 968         }
 969
 970         ctx->driver_data = drm_fimd_get_driver_data(pdev);
 971         ctx->vidcon0 = pdata->vidcon0;
 972         ctx->vidcon1 = pdata->vidcon1;
 973         ctx->default_win = pdata->default_win;
 974         ctx->panel = panel;
 975         DRM_INIT_WAITQUEUE(&ctx->wait_vsync_queue);
 976         atomic_set(&ctx->wait_vsync_event, 0);
 977
 978         subdrv = &ctx->subdrv;
 979
 980         subdrv->dev = dev;
 981         subdrv->manager = &fimd_manager;
 982         subdrv->probe = fimd_subdrv_probe;
 983         subdrv->remove = fimd_subdrv_remove;
 984
 985         mutex_init(&ctx->lock);
 986
 987         platform_set_drvdata(pdev, ctx);
 988
 989         pm_runtime_enable(dev);
 990         pm_runtime_get_sync(dev);
 991
 992         for (win = 0; win < WINDOWS_NR; win++)
 993                 fimd_clear_win(ctx, win);
 994
 995         exynos_drm_subdrv_register(subdrv);
 996
 997         return 0;
 998 }
 999
1000 static int fimd_remove(struct platform_device *pdev)
1001 {
1002         struct device *dev = &pdev->dev;
1003         struct fimd_context *ctx = platform_get_drvdata(pdev);
1004
1005         exynos_drm_subdrv_unregister(&ctx->subdrv);
1006
1007         if (ctx->suspended)
1008                 goto out;
1009
1010         pm_runtime_set_suspended(dev);
1011         pm_runtime_put_sync(dev);
1012
1013 out:
1014         pm_runtime_disable(dev);
1015
1016         return 0;
1017 }
1018
1019 #ifdef CONFIG_PM_SLEEP
1020 static int fimd_suspend(struct device *dev)
1021 {
1022         struct fimd_context *ctx = get_fimd_context(dev);
1023
1024         /*
1025          * do not use pm_runtime_suspend(). if pm_runtime_suspend() is
1026          * called here, an error would be returned by that interface
1027          * because the usage_count of pm runtime is more than 1.
1028          */
1029         if (!pm_runtime_suspended(dev))
1030                 return fimd_activate(ctx, false);
1031
1032         return 0;
1033 }
1034
1035 static int fimd_resume(struct device *dev)
1036 {
1037         struct fimd_context *ctx = get_fimd_context(dev);
1038
1039         /*
1040          * if entered to sleep when lcd panel was on, the usage_count
1041          * of pm runtime would still be 1 so in this case, fimd driver
1042          * should be on directly not drawing on pm runtime interface.
1043          */
1044         if (!pm_runtime_suspended(dev)) {
1045                 int ret;
1046
1047                 ret = fimd_activate(ctx, true);
1048                 if (ret < 0)
1049                         return ret;
1050
1051                 /*
1052                  * in case of dpms on(standby), fimd_apply function will
1053                  * be called by encoder's dpms callback to update fimd's
1054                  * registers but in case of sleep wakeup, it's not.
1055                  * so fimd_apply function should be called at here.
1056                  */
1057                 fimd_apply(dev);
1058         }
1059
1060         return 0;
1061 }
1062 #endif
1063
1064 #ifdef CONFIG_PM_RUNTIME
1065 static int fimd_runtime_suspend(struct device *dev)
1066 {
1067         struct fimd_context *ctx = get_fimd_context(dev);
1068
1069         return fimd_activate(ctx, false);
1070 }
1071
1072 static int fimd_runtime_resume(struct device *dev)
1073 {
1074         struct fimd_context *ctx = get_fimd_context(dev);
1075
1076         return fimd_activate(ctx, true);
1077 }
1078 #endif
1079
1080 static struct platform_device_id fimd_driver_ids[] = {
1081         {
1082                 .name           = "s3c64xx-fb",
1083                 .driver_data    = (unsigned long)&s3c64xx_fimd_driver_data,
1084         }, {
1085                 .name           = "exynos4-fb",
1086                 .driver_data    = (unsigned long)&exynos4_fimd_driver_data,
1087         }, {
1088                 .name           = "exynos5-fb",
1089                 .driver_data    = (unsigned long)&exynos5_fimd_driver_data,
1090         },
1091         {},
1092 };
1093
1094 static const struct dev_pm_ops fimd_pm_ops = {
1095         SET_SYSTEM_SLEEP_PM_OPS(fimd_suspend, fimd_resume)
1096         SET_RUNTIME_PM_OPS(fimd_runtime_suspend, fimd_runtime_resume, NULL)
1097 };
1098
1099 struct platform_driver fimd_driver = {
1100         .probe          = fimd_probe,
1101         .remove         = fimd_remove,
1102         .id_table       = fimd_driver_ids,
1103         .driver         = {
1104                 .name   = "exynos4-fb",
1105                 .owner  = THIS_MODULE,
1106                 .pm     = &fimd_pm_ops,
1107                 .of_match_table = of_match_ptr(fimd_driver_dt_match),
1108         },
1109 };