3 * Copyright (C) 2011 Samsung Electronics Co.Ltd
5 * Joonyoung Shim <jy0922.shim@samsung.com>
6 * Inki Dae <inki.dae@samsung.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
16 #include <linux/kernel.h>
17 #include <linux/platform_device.h>
18 #include <linux/clk.h>
20 #include <linux/of_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/component.h>
24 #include <video/of_display_timing.h>
25 #include <video/of_videomode.h>
26 #include <video/samsung_fimd.h>
27 #include <drm/exynos_drm.h>
29 #include "exynos_drm_drv.h"
30 #include "exynos_drm_fbdev.h"
31 #include "exynos_drm_crtc.h"
32 #include "exynos_drm_iommu.h"
35 * FIMD stands for Fully Interactive Mobile Display and
36 * as a display controller, it transfers contents drawn on memory
37 * to a LCD Panel through Display Interfaces such as RGB or
41 #define FIMD_DEFAULT_FRAMERATE 60
42 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128
44 /* position control register for hardware window 0, 2 ~ 4.*/
45 #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16)
46 #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16)
48 * size control register for hardware windows 0 and alpha control register
49 * for hardware windows 1 ~ 4
51 #define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16)
52 /* size control register for hardware windows 1 ~ 2. */
53 #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16)
55 #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8)
56 #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8)
57 #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4)
59 /* color key control register for hardware window 1 ~ 4. */
60 #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8))
61 /* color key value register for hardware window 1 ~ 4. */
62 #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8))
64 /* FIMD has totally five hardware windows. */
67 #define get_fimd_manager(mgr) platform_get_drvdata(to_platform_device(dev))
69 struct fimd_driver_data {
70 unsigned int timing_base;
72 unsigned int has_shadowcon:1;
73 unsigned int has_clksel:1;
74 unsigned int has_limited_fmt:1;
77 static struct fimd_driver_data s3c64xx_fimd_driver_data = {
83 static struct fimd_driver_data exynos4_fimd_driver_data = {
88 static struct fimd_driver_data exynos5_fimd_driver_data = {
89 .timing_base = 0x20000,
93 struct fimd_win_data {
94 unsigned int offset_x;
95 unsigned int offset_y;
96 unsigned int ovl_width;
97 unsigned int ovl_height;
98 unsigned int fb_width;
99 unsigned int fb_height;
101 unsigned int pixel_format;
103 unsigned int buf_offsize;
104 unsigned int line_size; /* bytes */
109 struct fimd_context {
111 struct drm_device *drm_dev;
115 struct drm_display_mode mode;
116 struct fimd_win_data win_data[WINDOWS_NR];
117 unsigned int default_win;
118 unsigned long irq_flags;
122 wait_queue_head_t wait_vsync_queue;
123 atomic_t wait_vsync_event;
125 struct exynos_drm_panel_info panel;
126 struct fimd_driver_data *driver_data;
127 struct exynos_drm_display *display;
130 static const struct of_device_id fimd_driver_dt_match[] = {
131 { .compatible = "samsung,s3c6400-fimd",
132 .data = &s3c64xx_fimd_driver_data },
133 { .compatible = "samsung,exynos4210-fimd",
134 .data = &exynos4_fimd_driver_data },
135 { .compatible = "samsung,exynos5250-fimd",
136 .data = &exynos5_fimd_driver_data },
140 static inline struct fimd_driver_data *drm_fimd_get_driver_data(
141 struct platform_device *pdev)
143 const struct of_device_id *of_id =
144 of_match_device(fimd_driver_dt_match, &pdev->dev);
146 return (struct fimd_driver_data *)of_id->data;
149 static void fimd_wait_for_vblank(struct exynos_drm_manager *mgr)
151 struct fimd_context *ctx = mgr->ctx;
156 atomic_set(&ctx->wait_vsync_event, 1);
159 * wait for FIMD to signal VSYNC interrupt or return after
160 * timeout which is set to 50ms (refresh rate of 20).
162 if (!wait_event_timeout(ctx->wait_vsync_queue,
163 !atomic_read(&ctx->wait_vsync_event),
165 DRM_DEBUG_KMS("vblank wait timed out.\n");
169 static void fimd_clear_channel(struct exynos_drm_manager *mgr)
171 struct fimd_context *ctx = mgr->ctx;
172 int win, ch_enabled = 0;
174 DRM_DEBUG_KMS("%s\n", __FILE__);
176 /* Check if any channel is enabled. */
177 for (win = 0; win < WINDOWS_NR; win++) {
178 u32 val = readl(ctx->regs + SHADOWCON);
179 if (val & SHADOWCON_CHx_ENABLE(win)) {
180 val &= ~SHADOWCON_CHx_ENABLE(win);
181 writel(val, ctx->regs + SHADOWCON);
186 /* Wait for vsync, as disable channel takes effect at next vsync */
188 fimd_wait_for_vblank(mgr);
191 static int fimd_mgr_initialize(struct exynos_drm_manager *mgr,
192 struct drm_device *drm_dev)
194 struct fimd_context *ctx = mgr->ctx;
195 struct exynos_drm_private *priv;
196 priv = drm_dev->dev_private;
198 mgr->drm_dev = ctx->drm_dev = drm_dev;
199 mgr->pipe = ctx->pipe = priv->pipe++;
202 * enable drm irq mode.
203 * - with irq_enabled = true, we can use the vblank feature.
205 * P.S. note that we wouldn't use drm irq handler but
206 * just specific driver own one instead because
207 * drm framework supports only one irq handler.
209 drm_dev->irq_enabled = true;
212 * with vblank_disable_allowed = true, vblank interrupt will be disabled
213 * by drm timer once a current process gives up ownership of
214 * vblank event.(after drm_vblank_put function is called)
216 drm_dev->vblank_disable_allowed = true;
218 /* attach this sub driver to iommu mapping if supported. */
219 if (is_drm_iommu_supported(ctx->drm_dev)) {
221 * If any channel is already active, iommu will throw
222 * a PAGE FAULT when enabled. So clear any channel if enabled.
224 fimd_clear_channel(mgr);
225 drm_iommu_attach_device(ctx->drm_dev, ctx->dev);
231 static void fimd_mgr_remove(struct exynos_drm_manager *mgr)
233 struct fimd_context *ctx = mgr->ctx;
235 /* detach this sub driver from iommu mapping if supported. */
236 if (is_drm_iommu_supported(ctx->drm_dev))
237 drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
240 static u32 fimd_calc_clkdiv(struct fimd_context *ctx,
241 const struct drm_display_mode *mode)
243 unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh;
246 /* Find the clock divider value that gets us closest to ideal_clk */
247 clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->lcd_clk), ideal_clk);
249 return (clkdiv < 0x100) ? clkdiv : 0xff;
252 static bool fimd_mode_fixup(struct exynos_drm_manager *mgr,
253 const struct drm_display_mode *mode,
254 struct drm_display_mode *adjusted_mode)
256 if (adjusted_mode->vrefresh == 0)
257 adjusted_mode->vrefresh = FIMD_DEFAULT_FRAMERATE;
262 static void fimd_mode_set(struct exynos_drm_manager *mgr,
263 const struct drm_display_mode *in_mode)
265 struct fimd_context *ctx = mgr->ctx;
267 drm_mode_copy(&ctx->mode, in_mode);
270 static void fimd_commit(struct exynos_drm_manager *mgr)
272 struct fimd_context *ctx = mgr->ctx;
273 struct drm_display_mode *mode = &ctx->mode;
274 struct fimd_driver_data *driver_data;
275 u32 val, clkdiv, vidcon1;
276 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd;
278 driver_data = ctx->driver_data;
282 /* nothing to do if we haven't set the mode yet */
283 if (mode->htotal == 0 || mode->vtotal == 0)
286 /* setup polarity values */
287 vidcon1 = ctx->vidcon1;
288 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
289 vidcon1 |= VIDCON1_INV_VSYNC;
290 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
291 vidcon1 |= VIDCON1_INV_HSYNC;
292 writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1);
294 /* setup vertical timing values. */
295 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
296 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end;
297 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay;
299 val = VIDTCON0_VBPD(vbpd - 1) |
300 VIDTCON0_VFPD(vfpd - 1) |
301 VIDTCON0_VSPW(vsync_len - 1);
302 writel(val, ctx->regs + driver_data->timing_base + VIDTCON0);
304 /* setup horizontal timing values. */
305 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
306 hbpd = mode->crtc_htotal - mode->crtc_hsync_end;
307 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay;
309 val = VIDTCON1_HBPD(hbpd - 1) |
310 VIDTCON1_HFPD(hfpd - 1) |
311 VIDTCON1_HSPW(hsync_len - 1);
312 writel(val, ctx->regs + driver_data->timing_base + VIDTCON1);
314 /* setup horizontal and vertical display size. */
315 val = VIDTCON2_LINEVAL(mode->vdisplay - 1) |
316 VIDTCON2_HOZVAL(mode->hdisplay - 1) |
317 VIDTCON2_LINEVAL_E(mode->vdisplay - 1) |
318 VIDTCON2_HOZVAL_E(mode->hdisplay - 1);
319 writel(val, ctx->regs + driver_data->timing_base + VIDTCON2);
322 * fields of register with prefix '_F' would be updated
323 * at vsync(same as dma start)
325 val = VIDCON0_ENVID | VIDCON0_ENVID_F;
327 if (ctx->driver_data->has_clksel)
328 val |= VIDCON0_CLKSEL_LCD;
330 clkdiv = fimd_calc_clkdiv(ctx, mode);
332 val |= VIDCON0_CLKVAL_F(clkdiv - 1) | VIDCON0_CLKDIR;
334 writel(val, ctx->regs + VIDCON0);
337 static int fimd_enable_vblank(struct exynos_drm_manager *mgr)
339 struct fimd_context *ctx = mgr->ctx;
345 if (!test_and_set_bit(0, &ctx->irq_flags)) {
346 val = readl(ctx->regs + VIDINTCON0);
348 val |= VIDINTCON0_INT_ENABLE;
349 val |= VIDINTCON0_INT_FRAME;
351 val &= ~VIDINTCON0_FRAMESEL0_MASK;
352 val |= VIDINTCON0_FRAMESEL0_VSYNC;
353 val &= ~VIDINTCON0_FRAMESEL1_MASK;
354 val |= VIDINTCON0_FRAMESEL1_NONE;
356 writel(val, ctx->regs + VIDINTCON0);
362 static void fimd_disable_vblank(struct exynos_drm_manager *mgr)
364 struct fimd_context *ctx = mgr->ctx;
370 if (test_and_clear_bit(0, &ctx->irq_flags)) {
371 val = readl(ctx->regs + VIDINTCON0);
373 val &= ~VIDINTCON0_INT_FRAME;
374 val &= ~VIDINTCON0_INT_ENABLE;
376 writel(val, ctx->regs + VIDINTCON0);
380 static void fimd_win_mode_set(struct exynos_drm_manager *mgr,
381 struct exynos_drm_overlay *overlay)
383 struct fimd_context *ctx = mgr->ctx;
384 struct fimd_win_data *win_data;
386 unsigned long offset;
389 DRM_ERROR("overlay is NULL\n");
394 if (win == DEFAULT_ZPOS)
395 win = ctx->default_win;
397 if (win < 0 || win >= WINDOWS_NR)
400 offset = overlay->fb_x * (overlay->bpp >> 3);
401 offset += overlay->fb_y * overlay->pitch;
403 DRM_DEBUG_KMS("offset = 0x%lx, pitch = %x\n", offset, overlay->pitch);
405 win_data = &ctx->win_data[win];
407 win_data->offset_x = overlay->crtc_x;
408 win_data->offset_y = overlay->crtc_y;
409 win_data->ovl_width = overlay->crtc_width;
410 win_data->ovl_height = overlay->crtc_height;
411 win_data->fb_width = overlay->fb_width;
412 win_data->fb_height = overlay->fb_height;
413 win_data->dma_addr = overlay->dma_addr[0] + offset;
414 win_data->bpp = overlay->bpp;
415 win_data->pixel_format = overlay->pixel_format;
416 win_data->buf_offsize = (overlay->fb_width - overlay->crtc_width) *
418 win_data->line_size = overlay->crtc_width * (overlay->bpp >> 3);
420 DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n",
421 win_data->offset_x, win_data->offset_y);
422 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
423 win_data->ovl_width, win_data->ovl_height);
424 DRM_DEBUG_KMS("paddr = 0x%lx\n", (unsigned long)win_data->dma_addr);
425 DRM_DEBUG_KMS("fb_width = %d, crtc_width = %d\n",
426 overlay->fb_width, overlay->crtc_width);
429 static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win)
431 struct fimd_win_data *win_data = &ctx->win_data[win];
437 * In case of s3c64xx, window 0 doesn't support alpha channel.
438 * So the request format is ARGB8888 then change it to XRGB8888.
440 if (ctx->driver_data->has_limited_fmt && !win) {
441 if (win_data->pixel_format == DRM_FORMAT_ARGB8888)
442 win_data->pixel_format = DRM_FORMAT_XRGB8888;
445 switch (win_data->pixel_format) {
447 val |= WINCON0_BPPMODE_8BPP_PALETTE;
448 val |= WINCONx_BURSTLEN_8WORD;
449 val |= WINCONx_BYTSWP;
451 case DRM_FORMAT_XRGB1555:
452 val |= WINCON0_BPPMODE_16BPP_1555;
453 val |= WINCONx_HAWSWP;
454 val |= WINCONx_BURSTLEN_16WORD;
456 case DRM_FORMAT_RGB565:
457 val |= WINCON0_BPPMODE_16BPP_565;
458 val |= WINCONx_HAWSWP;
459 val |= WINCONx_BURSTLEN_16WORD;
461 case DRM_FORMAT_XRGB8888:
462 val |= WINCON0_BPPMODE_24BPP_888;
464 val |= WINCONx_BURSTLEN_16WORD;
466 case DRM_FORMAT_ARGB8888:
467 val |= WINCON1_BPPMODE_25BPP_A1888
468 | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
470 val |= WINCONx_BURSTLEN_16WORD;
473 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
475 val |= WINCON0_BPPMODE_24BPP_888;
477 val |= WINCONx_BURSTLEN_16WORD;
481 DRM_DEBUG_KMS("bpp = %d\n", win_data->bpp);
484 * In case of exynos, setting dma-burst to 16Word causes permanent
485 * tearing for very small buffers, e.g. cursor buffer. Burst Mode
486 * switching which is based on overlay size is not recommended as
487 * overlay size varies alot towards the end of the screen and rapid
488 * movement causes unstable DMA which results into iommu crash/tear.
491 if (win_data->fb_width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
492 val &= ~WINCONx_BURSTLEN_MASK;
493 val |= WINCONx_BURSTLEN_4WORD;
496 writel(val, ctx->regs + WINCON(win));
499 static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win)
501 unsigned int keycon0 = 0, keycon1 = 0;
503 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
504 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
506 keycon1 = WxKEYCON1_COLVAL(0xffffffff);
508 writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
509 writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
513 * shadow_protect_win() - disable updating values from shadow registers at vsync
515 * @win: window to protect registers for
516 * @protect: 1 to protect (disable updates)
518 static void fimd_shadow_protect_win(struct fimd_context *ctx,
519 int win, bool protect)
523 if (ctx->driver_data->has_shadowcon) {
525 bits = SHADOWCON_WINx_PROTECT(win);
528 bits = PRTCON_PROTECT;
531 val = readl(ctx->regs + reg);
536 writel(val, ctx->regs + reg);
539 static void fimd_win_commit(struct exynos_drm_manager *mgr, int zpos)
541 struct fimd_context *ctx = mgr->ctx;
542 struct fimd_win_data *win_data;
544 unsigned long val, alpha, size;
551 if (win == DEFAULT_ZPOS)
552 win = ctx->default_win;
554 if (win < 0 || win >= WINDOWS_NR)
557 win_data = &ctx->win_data[win];
559 /* If suspended, enable this on resume */
560 if (ctx->suspended) {
561 win_data->resume = true;
566 * SHADOWCON/PRTCON register is used for enabling timing.
568 * for example, once only width value of a register is set,
569 * if the dma is started then fimd hardware could malfunction so
570 * with protect window setting, the register fields with prefix '_F'
571 * wouldn't be updated at vsync also but updated once unprotect window
575 /* protect windows */
576 fimd_shadow_protect_win(ctx, win, true);
578 /* buffer start address */
579 val = (unsigned long)win_data->dma_addr;
580 writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
582 /* buffer end address */
583 size = win_data->fb_width * win_data->ovl_height * (win_data->bpp >> 3);
584 val = (unsigned long)(win_data->dma_addr + size);
585 writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
587 DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
588 (unsigned long)win_data->dma_addr, val, size);
589 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
590 win_data->ovl_width, win_data->ovl_height);
593 val = VIDW_BUF_SIZE_OFFSET(win_data->buf_offsize) |
594 VIDW_BUF_SIZE_PAGEWIDTH(win_data->line_size) |
595 VIDW_BUF_SIZE_OFFSET_E(win_data->buf_offsize) |
596 VIDW_BUF_SIZE_PAGEWIDTH_E(win_data->line_size);
597 writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
600 val = VIDOSDxA_TOPLEFT_X(win_data->offset_x) |
601 VIDOSDxA_TOPLEFT_Y(win_data->offset_y) |
602 VIDOSDxA_TOPLEFT_X_E(win_data->offset_x) |
603 VIDOSDxA_TOPLEFT_Y_E(win_data->offset_y);
604 writel(val, ctx->regs + VIDOSD_A(win));
606 last_x = win_data->offset_x + win_data->ovl_width;
609 last_y = win_data->offset_y + win_data->ovl_height;
613 val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) |
614 VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y);
616 writel(val, ctx->regs + VIDOSD_B(win));
618 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
619 win_data->offset_x, win_data->offset_y, last_x, last_y);
621 /* hardware window 0 doesn't support alpha channel. */
624 alpha = VIDISD14C_ALPHA1_R(0xf) |
625 VIDISD14C_ALPHA1_G(0xf) |
626 VIDISD14C_ALPHA1_B(0xf);
628 writel(alpha, ctx->regs + VIDOSD_C(win));
632 if (win != 3 && win != 4) {
633 u32 offset = VIDOSD_D(win);
635 offset = VIDOSD_C(win);
636 val = win_data->ovl_width * win_data->ovl_height;
637 writel(val, ctx->regs + offset);
639 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val);
642 fimd_win_set_pixfmt(ctx, win);
644 /* hardware window 0 doesn't support color key. */
646 fimd_win_set_colkey(ctx, win);
649 val = readl(ctx->regs + WINCON(win));
650 val |= WINCONx_ENWIN;
651 writel(val, ctx->regs + WINCON(win));
653 /* Enable DMA channel and unprotect windows */
654 fimd_shadow_protect_win(ctx, win, false);
656 if (ctx->driver_data->has_shadowcon) {
657 val = readl(ctx->regs + SHADOWCON);
658 val |= SHADOWCON_CHx_ENABLE(win);
659 writel(val, ctx->regs + SHADOWCON);
662 win_data->enabled = true;
665 static void fimd_win_disable(struct exynos_drm_manager *mgr, int zpos)
667 struct fimd_context *ctx = mgr->ctx;
668 struct fimd_win_data *win_data;
672 if (win == DEFAULT_ZPOS)
673 win = ctx->default_win;
675 if (win < 0 || win >= WINDOWS_NR)
678 win_data = &ctx->win_data[win];
680 if (ctx->suspended) {
681 /* do not resume this window*/
682 win_data->resume = false;
686 /* protect windows */
687 fimd_shadow_protect_win(ctx, win, true);
690 val = readl(ctx->regs + WINCON(win));
691 val &= ~WINCONx_ENWIN;
692 writel(val, ctx->regs + WINCON(win));
694 /* unprotect windows */
695 if (ctx->driver_data->has_shadowcon) {
696 val = readl(ctx->regs + SHADOWCON);
697 val &= ~SHADOWCON_CHx_ENABLE(win);
698 writel(val, ctx->regs + SHADOWCON);
701 fimd_shadow_protect_win(ctx, win, false);
703 win_data->enabled = false;
706 static void fimd_window_suspend(struct exynos_drm_manager *mgr)
708 struct fimd_context *ctx = mgr->ctx;
709 struct fimd_win_data *win_data;
712 for (i = 0; i < WINDOWS_NR; i++) {
713 win_data = &ctx->win_data[i];
714 win_data->resume = win_data->enabled;
715 if (win_data->enabled)
716 fimd_win_disable(mgr, i);
718 fimd_wait_for_vblank(mgr);
721 static void fimd_window_resume(struct exynos_drm_manager *mgr)
723 struct fimd_context *ctx = mgr->ctx;
724 struct fimd_win_data *win_data;
727 for (i = 0; i < WINDOWS_NR; i++) {
728 win_data = &ctx->win_data[i];
729 win_data->enabled = win_data->resume;
730 win_data->resume = false;
734 static void fimd_apply(struct exynos_drm_manager *mgr)
736 struct fimd_context *ctx = mgr->ctx;
737 struct fimd_win_data *win_data;
740 for (i = 0; i < WINDOWS_NR; i++) {
741 win_data = &ctx->win_data[i];
742 if (win_data->enabled)
743 fimd_win_commit(mgr, i);
749 static int fimd_poweron(struct exynos_drm_manager *mgr)
751 struct fimd_context *ctx = mgr->ctx;
757 ctx->suspended = false;
759 pm_runtime_get_sync(ctx->dev);
761 ret = clk_prepare_enable(ctx->bus_clk);
763 DRM_ERROR("Failed to prepare_enable the bus clk [%d]\n", ret);
767 ret = clk_prepare_enable(ctx->lcd_clk);
769 DRM_ERROR("Failed to prepare_enable the lcd clk [%d]\n", ret);
773 /* if vblank was enabled status, enable it again. */
774 if (test_and_clear_bit(0, &ctx->irq_flags)) {
775 ret = fimd_enable_vblank(mgr);
777 DRM_ERROR("Failed to re-enable vblank [%d]\n", ret);
778 goto enable_vblank_err;
782 fimd_window_resume(mgr);
789 clk_disable_unprepare(ctx->lcd_clk);
791 clk_disable_unprepare(ctx->bus_clk);
793 ctx->suspended = true;
797 static int fimd_poweroff(struct exynos_drm_manager *mgr)
799 struct fimd_context *ctx = mgr->ctx;
805 * We need to make sure that all windows are disabled before we
806 * suspend that connector. Otherwise we might try to scan from
807 * a destroyed buffer later.
809 fimd_window_suspend(mgr);
811 clk_disable_unprepare(ctx->lcd_clk);
812 clk_disable_unprepare(ctx->bus_clk);
814 pm_runtime_put_sync(ctx->dev);
816 ctx->suspended = true;
820 static void fimd_dpms(struct exynos_drm_manager *mgr, int mode)
822 DRM_DEBUG_KMS("%s, %d\n", __FILE__, mode);
825 case DRM_MODE_DPMS_ON:
828 case DRM_MODE_DPMS_STANDBY:
829 case DRM_MODE_DPMS_SUSPEND:
830 case DRM_MODE_DPMS_OFF:
834 DRM_DEBUG_KMS("unspecified mode %d\n", mode);
839 static struct exynos_drm_manager_ops fimd_manager_ops = {
841 .mode_fixup = fimd_mode_fixup,
842 .mode_set = fimd_mode_set,
843 .commit = fimd_commit,
844 .enable_vblank = fimd_enable_vblank,
845 .disable_vblank = fimd_disable_vblank,
846 .wait_for_vblank = fimd_wait_for_vblank,
847 .win_mode_set = fimd_win_mode_set,
848 .win_commit = fimd_win_commit,
849 .win_disable = fimd_win_disable,
852 static struct exynos_drm_manager fimd_manager = {
853 .type = EXYNOS_DISPLAY_TYPE_LCD,
854 .ops = &fimd_manager_ops,
857 static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
859 struct fimd_context *ctx = (struct fimd_context *)dev_id;
862 val = readl(ctx->regs + VIDINTCON1);
864 if (val & VIDINTCON1_INT_FRAME)
865 /* VSYNC interrupt */
866 writel(VIDINTCON1_INT_FRAME, ctx->regs + VIDINTCON1);
868 /* check the crtc is detached already from encoder */
869 if (ctx->pipe < 0 || !ctx->drm_dev)
872 drm_handle_vblank(ctx->drm_dev, ctx->pipe);
873 exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe);
875 /* set wait vsync event to zero and wake up queue. */
876 if (atomic_read(&ctx->wait_vsync_event)) {
877 atomic_set(&ctx->wait_vsync_event, 0);
878 wake_up(&ctx->wait_vsync_queue);
884 static int fimd_bind(struct device *dev, struct device *master, void *data)
886 struct fimd_context *ctx = fimd_manager.ctx;
887 struct drm_device *drm_dev = data;
889 fimd_mgr_initialize(&fimd_manager, drm_dev);
890 exynos_drm_crtc_create(&fimd_manager);
892 exynos_drm_create_enc_conn(drm_dev, ctx->display);
898 static void fimd_unbind(struct device *dev, struct device *master,
901 struct exynos_drm_manager *mgr = dev_get_drvdata(dev);
902 struct fimd_context *ctx = fimd_manager.ctx;
903 struct drm_crtc *crtc = mgr->crtc;
905 fimd_dpms(mgr, DRM_MODE_DPMS_OFF);
908 exynos_dpi_remove(dev);
910 fimd_mgr_remove(mgr);
912 crtc->funcs->destroy(crtc);
915 static const struct component_ops fimd_component_ops = {
917 .unbind = fimd_unbind,
920 static int fimd_probe(struct platform_device *pdev)
922 struct device *dev = &pdev->dev;
923 struct fimd_context *ctx;
924 struct resource *res;
927 ret = exynos_drm_component_add(&pdev->dev, EXYNOS_DEVICE_TYPE_CRTC,
934 goto err_del_component;
937 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
940 goto err_del_component;
944 ctx->suspended = true;
946 if (of_property_read_bool(dev->of_node, "samsung,invert-vden"))
947 ctx->vidcon1 |= VIDCON1_INV_VDEN;
948 if (of_property_read_bool(dev->of_node, "samsung,invert-vclk"))
949 ctx->vidcon1 |= VIDCON1_INV_VCLK;
951 ctx->bus_clk = devm_clk_get(dev, "fimd");
952 if (IS_ERR(ctx->bus_clk)) {
953 dev_err(dev, "failed to get bus clock\n");
954 ret = PTR_ERR(ctx->bus_clk);
955 goto err_del_component;
958 ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd");
959 if (IS_ERR(ctx->lcd_clk)) {
960 dev_err(dev, "failed to get lcd clock\n");
961 ret = PTR_ERR(ctx->lcd_clk);
962 goto err_del_component;
965 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
967 ctx->regs = devm_ioremap_resource(dev, res);
968 if (IS_ERR(ctx->regs)) {
969 ret = PTR_ERR(ctx->regs);
970 goto err_del_component;
973 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "vsync");
975 dev_err(dev, "irq request failed.\n");
977 goto err_del_component;
980 ret = devm_request_irq(dev, res->start, fimd_irq_handler,
983 dev_err(dev, "irq request failed.\n");
984 goto err_del_component;
987 ctx->driver_data = drm_fimd_get_driver_data(pdev);
988 init_waitqueue_head(&ctx->wait_vsync_queue);
989 atomic_set(&ctx->wait_vsync_event, 0);
991 platform_set_drvdata(pdev, &fimd_manager);
993 fimd_manager.ctx = ctx;
995 ctx->display = exynos_dpi_probe(dev);
996 if (IS_ERR(ctx->display))
997 return PTR_ERR(ctx->display);
999 pm_runtime_enable(&pdev->dev);
1001 ret = component_add(&pdev->dev, &fimd_component_ops);
1003 goto err_disable_pm_runtime;
1007 err_disable_pm_runtime:
1008 pm_runtime_disable(&pdev->dev);
1011 exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CRTC);
1015 static int fimd_remove(struct platform_device *pdev)
1017 pm_runtime_disable(&pdev->dev);
1019 component_del(&pdev->dev, &fimd_component_ops);
1020 exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CRTC);
1025 struct platform_driver fimd_driver = {
1026 .probe = fimd_probe,
1027 .remove = fimd_remove,
1029 .name = "exynos4-fb",
1030 .owner = THIS_MODULE,
1031 .of_match_table = fimd_driver_dt_match,