3 * Copyright (C) 2011 Samsung Electronics Co.Ltd
5 * Joonyoung Shim <jy0922.shim@samsung.com>
6 * Inki Dae <inki.dae@samsung.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
16 #include <linux/kernel.h>
17 #include <linux/platform_device.h>
18 #include <linux/clk.h>
20 #include <linux/of_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/component.h>
23 #include <linux/mfd/syscon.h>
24 #include <linux/regmap.h>
26 #include <video/of_display_timing.h>
27 #include <video/of_videomode.h>
28 #include <video/samsung_fimd.h>
29 #include <drm/exynos_drm.h>
31 #include "exynos_drm_drv.h"
32 #include "exynos_drm_fbdev.h"
33 #include "exynos_drm_crtc.h"
34 #include "exynos_drm_iommu.h"
37 * FIMD stands for Fully Interactive Mobile Display and
38 * as a display controller, it transfers contents drawn on memory
39 * to a LCD Panel through Display Interfaces such as RGB or
43 #define FIMD_DEFAULT_FRAMERATE 60
44 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128
46 /* position control register for hardware window 0, 2 ~ 4.*/
47 #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16)
48 #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16)
50 * size control register for hardware windows 0 and alpha control register
51 * for hardware windows 1 ~ 4
53 #define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16)
54 /* size control register for hardware windows 1 ~ 2. */
55 #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16)
57 #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8)
58 #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8)
59 #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4)
61 /* color key control register for hardware window 1 ~ 4. */
62 #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8))
63 /* color key value register for hardware window 1 ~ 4. */
64 #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8))
66 /* I80 / RGB trigger control register */
68 #define TRGMODE_I80_RGB_ENABLE_I80 (1 << 0)
69 #define SWTRGCMD_I80_RGB_ENABLE (1 << 1)
71 /* display mode change control register except exynos4 */
72 #define VIDOUT_CON 0x000
73 #define VIDOUT_CON_F_I80_LDI0 (0x2 << 8)
75 /* I80 interface control for main LDI register */
76 #define I80IFCONFAx(x) (0x1B0 + (x) * 4)
77 #define I80IFCONFBx(x) (0x1B8 + (x) * 4)
78 #define LCD_CS_SETUP(x) ((x) << 16)
79 #define LCD_WR_SETUP(x) ((x) << 12)
80 #define LCD_WR_ACTIVE(x) ((x) << 8)
81 #define LCD_WR_HOLD(x) ((x) << 4)
82 #define I80IFEN_ENABLE (1 << 0)
84 /* FIMD has totally five hardware windows. */
87 #define get_fimd_manager(mgr) platform_get_drvdata(to_platform_device(dev))
89 struct fimd_driver_data {
90 unsigned int timing_base;
91 unsigned int lcdblk_offset;
92 unsigned int lcdblk_vt_shift;
93 unsigned int lcdblk_bypass_shift;
95 unsigned int has_shadowcon:1;
96 unsigned int has_clksel:1;
97 unsigned int has_limited_fmt:1;
98 unsigned int has_vidoutcon:1;
99 unsigned int has_vtsel:1;
102 static struct fimd_driver_data s3c64xx_fimd_driver_data = {
105 .has_limited_fmt = 1,
108 static struct fimd_driver_data exynos3_fimd_driver_data = {
109 .timing_base = 0x20000,
110 .lcdblk_offset = 0x210,
111 .lcdblk_bypass_shift = 1,
116 static struct fimd_driver_data exynos4_fimd_driver_data = {
118 .lcdblk_offset = 0x210,
119 .lcdblk_vt_shift = 10,
120 .lcdblk_bypass_shift = 1,
125 static struct fimd_driver_data exynos4415_fimd_driver_data = {
126 .timing_base = 0x20000,
127 .lcdblk_offset = 0x210,
128 .lcdblk_vt_shift = 10,
129 .lcdblk_bypass_shift = 1,
135 static struct fimd_driver_data exynos5_fimd_driver_data = {
136 .timing_base = 0x20000,
137 .lcdblk_offset = 0x214,
138 .lcdblk_vt_shift = 24,
139 .lcdblk_bypass_shift = 15,
145 struct fimd_win_data {
146 unsigned int offset_x;
147 unsigned int offset_y;
148 unsigned int ovl_width;
149 unsigned int ovl_height;
150 unsigned int fb_width;
151 unsigned int fb_height;
153 unsigned int pixel_format;
155 unsigned int buf_offsize;
156 unsigned int line_size; /* bytes */
161 struct fimd_context {
163 struct drm_device *drm_dev;
167 struct regmap *sysreg;
168 struct drm_display_mode mode;
169 struct fimd_win_data win_data[WINDOWS_NR];
170 unsigned int default_win;
171 unsigned long irq_flags;
179 wait_queue_head_t wait_vsync_queue;
180 atomic_t wait_vsync_event;
181 atomic_t win_updated;
184 struct exynos_drm_panel_info panel;
185 struct fimd_driver_data *driver_data;
186 struct exynos_drm_display *display;
189 static const struct of_device_id fimd_driver_dt_match[] = {
190 { .compatible = "samsung,s3c6400-fimd",
191 .data = &s3c64xx_fimd_driver_data },
192 { .compatible = "samsung,exynos3250-fimd",
193 .data = &exynos3_fimd_driver_data },
194 { .compatible = "samsung,exynos4210-fimd",
195 .data = &exynos4_fimd_driver_data },
196 { .compatible = "samsung,exynos4415-fimd",
197 .data = &exynos4415_fimd_driver_data },
198 { .compatible = "samsung,exynos5250-fimd",
199 .data = &exynos5_fimd_driver_data },
202 MODULE_DEVICE_TABLE(of, fimd_driver_dt_match);
204 static inline struct fimd_driver_data *drm_fimd_get_driver_data(
205 struct platform_device *pdev)
207 const struct of_device_id *of_id =
208 of_match_device(fimd_driver_dt_match, &pdev->dev);
210 return (struct fimd_driver_data *)of_id->data;
213 static void fimd_wait_for_vblank(struct exynos_drm_manager *mgr)
215 struct fimd_context *ctx = mgr->ctx;
220 atomic_set(&ctx->wait_vsync_event, 1);
223 * wait for FIMD to signal VSYNC interrupt or return after
224 * timeout which is set to 50ms (refresh rate of 20).
226 if (!wait_event_timeout(ctx->wait_vsync_queue,
227 !atomic_read(&ctx->wait_vsync_event),
229 DRM_DEBUG_KMS("vblank wait timed out.\n");
232 static void fimd_clear_channel(struct exynos_drm_manager *mgr)
234 struct fimd_context *ctx = mgr->ctx;
235 int win, ch_enabled = 0;
237 DRM_DEBUG_KMS("%s\n", __FILE__);
239 /* Check if any channel is enabled. */
240 for (win = 0; win < WINDOWS_NR; win++) {
241 u32 val = readl(ctx->regs + WINCON(win));
243 if (val & WINCONx_ENWIN) {
245 val &= ~WINCONx_ENWIN;
246 writel(val, ctx->regs + WINCON(win));
248 /* unprotect windows */
249 if (ctx->driver_data->has_shadowcon) {
250 val = readl(ctx->regs + SHADOWCON);
251 val &= ~SHADOWCON_CHx_ENABLE(win);
252 writel(val, ctx->regs + SHADOWCON);
258 /* Wait for vsync, as disable channel takes effect at next vsync */
260 unsigned int state = ctx->suspended;
263 fimd_wait_for_vblank(mgr);
264 ctx->suspended = state;
268 static int fimd_mgr_initialize(struct exynos_drm_manager *mgr,
269 struct drm_device *drm_dev)
271 struct fimd_context *ctx = mgr->ctx;
272 struct exynos_drm_private *priv;
273 priv = drm_dev->dev_private;
275 mgr->drm_dev = ctx->drm_dev = drm_dev;
276 mgr->pipe = ctx->pipe = priv->pipe++;
278 /* attach this sub driver to iommu mapping if supported. */
279 if (is_drm_iommu_supported(ctx->drm_dev)) {
281 * If any channel is already active, iommu will throw
282 * a PAGE FAULT when enabled. So clear any channel if enabled.
284 fimd_clear_channel(mgr);
285 drm_iommu_attach_device(ctx->drm_dev, ctx->dev);
291 static void fimd_mgr_remove(struct exynos_drm_manager *mgr)
293 struct fimd_context *ctx = mgr->ctx;
295 /* detach this sub driver from iommu mapping if supported. */
296 if (is_drm_iommu_supported(ctx->drm_dev))
297 drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
300 static u32 fimd_calc_clkdiv(struct fimd_context *ctx,
301 const struct drm_display_mode *mode)
303 unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh;
308 * The frame done interrupt should be occurred prior to the
314 /* Find the clock divider value that gets us closest to ideal_clk */
315 clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->lcd_clk), ideal_clk);
317 return (clkdiv < 0x100) ? clkdiv : 0xff;
320 static bool fimd_mode_fixup(struct exynos_drm_manager *mgr,
321 const struct drm_display_mode *mode,
322 struct drm_display_mode *adjusted_mode)
324 if (adjusted_mode->vrefresh == 0)
325 adjusted_mode->vrefresh = FIMD_DEFAULT_FRAMERATE;
330 static void fimd_mode_set(struct exynos_drm_manager *mgr,
331 const struct drm_display_mode *in_mode)
333 struct fimd_context *ctx = mgr->ctx;
335 drm_mode_copy(&ctx->mode, in_mode);
338 static void fimd_commit(struct exynos_drm_manager *mgr)
340 struct fimd_context *ctx = mgr->ctx;
341 struct drm_display_mode *mode = &ctx->mode;
342 struct fimd_driver_data *driver_data = ctx->driver_data;
343 void *timing_base = ctx->regs + driver_data->timing_base;
349 /* nothing to do if we haven't set the mode yet */
350 if (mode->htotal == 0 || mode->vtotal == 0)
354 val = ctx->i80ifcon | I80IFEN_ENABLE;
355 writel(val, timing_base + I80IFCONFAx(0));
357 /* disable auto frame rate */
358 writel(0, timing_base + I80IFCONFBx(0));
360 /* set video type selection to I80 interface */
361 if (driver_data->has_vtsel && ctx->sysreg &&
362 regmap_update_bits(ctx->sysreg,
363 driver_data->lcdblk_offset,
364 0x3 << driver_data->lcdblk_vt_shift,
365 0x1 << driver_data->lcdblk_vt_shift)) {
366 DRM_ERROR("Failed to update sysreg for I80 i/f.\n");
370 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd;
373 /* setup polarity values */
374 vidcon1 = ctx->vidcon1;
375 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
376 vidcon1 |= VIDCON1_INV_VSYNC;
377 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
378 vidcon1 |= VIDCON1_INV_HSYNC;
379 writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1);
381 /* setup vertical timing values. */
382 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
383 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end;
384 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay;
386 val = VIDTCON0_VBPD(vbpd - 1) |
387 VIDTCON0_VFPD(vfpd - 1) |
388 VIDTCON0_VSPW(vsync_len - 1);
389 writel(val, ctx->regs + driver_data->timing_base + VIDTCON0);
391 /* setup horizontal timing values. */
392 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
393 hbpd = mode->crtc_htotal - mode->crtc_hsync_end;
394 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay;
396 val = VIDTCON1_HBPD(hbpd - 1) |
397 VIDTCON1_HFPD(hfpd - 1) |
398 VIDTCON1_HSPW(hsync_len - 1);
399 writel(val, ctx->regs + driver_data->timing_base + VIDTCON1);
402 if (driver_data->has_vidoutcon)
403 writel(ctx->vidout_con, timing_base + VIDOUT_CON);
405 /* set bypass selection */
406 if (ctx->sysreg && regmap_update_bits(ctx->sysreg,
407 driver_data->lcdblk_offset,
408 0x1 << driver_data->lcdblk_bypass_shift,
409 0x1 << driver_data->lcdblk_bypass_shift)) {
410 DRM_ERROR("Failed to update sysreg for bypass setting.\n");
414 /* setup horizontal and vertical display size. */
415 val = VIDTCON2_LINEVAL(mode->vdisplay - 1) |
416 VIDTCON2_HOZVAL(mode->hdisplay - 1) |
417 VIDTCON2_LINEVAL_E(mode->vdisplay - 1) |
418 VIDTCON2_HOZVAL_E(mode->hdisplay - 1);
419 writel(val, ctx->regs + driver_data->timing_base + VIDTCON2);
422 * fields of register with prefix '_F' would be updated
423 * at vsync(same as dma start)
426 val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
428 if (ctx->driver_data->has_clksel)
429 val |= VIDCON0_CLKSEL_LCD;
431 clkdiv = fimd_calc_clkdiv(ctx, mode);
433 val |= VIDCON0_CLKVAL_F(clkdiv - 1) | VIDCON0_CLKDIR;
435 writel(val, ctx->regs + VIDCON0);
438 static int fimd_enable_vblank(struct exynos_drm_manager *mgr)
440 struct fimd_context *ctx = mgr->ctx;
446 if (!test_and_set_bit(0, &ctx->irq_flags)) {
447 val = readl(ctx->regs + VIDINTCON0);
449 val |= VIDINTCON0_INT_ENABLE;
450 val |= VIDINTCON0_INT_FRAME;
452 val &= ~VIDINTCON0_FRAMESEL0_MASK;
453 val |= VIDINTCON0_FRAMESEL0_VSYNC;
454 val &= ~VIDINTCON0_FRAMESEL1_MASK;
455 val |= VIDINTCON0_FRAMESEL1_NONE;
457 writel(val, ctx->regs + VIDINTCON0);
463 static void fimd_disable_vblank(struct exynos_drm_manager *mgr)
465 struct fimd_context *ctx = mgr->ctx;
471 if (test_and_clear_bit(0, &ctx->irq_flags)) {
472 val = readl(ctx->regs + VIDINTCON0);
474 val &= ~VIDINTCON0_INT_FRAME;
475 val &= ~VIDINTCON0_INT_ENABLE;
477 writel(val, ctx->regs + VIDINTCON0);
481 static void fimd_win_mode_set(struct exynos_drm_manager *mgr,
482 struct exynos_drm_overlay *overlay)
484 struct fimd_context *ctx = mgr->ctx;
485 struct fimd_win_data *win_data;
487 unsigned long offset;
490 DRM_ERROR("overlay is NULL\n");
495 if (win == DEFAULT_ZPOS)
496 win = ctx->default_win;
498 if (win < 0 || win >= WINDOWS_NR)
501 offset = overlay->fb_x * (overlay->bpp >> 3);
502 offset += overlay->fb_y * overlay->pitch;
504 DRM_DEBUG_KMS("offset = 0x%lx, pitch = %x\n", offset, overlay->pitch);
506 win_data = &ctx->win_data[win];
508 win_data->offset_x = overlay->crtc_x;
509 win_data->offset_y = overlay->crtc_y;
510 win_data->ovl_width = overlay->crtc_width;
511 win_data->ovl_height = overlay->crtc_height;
512 win_data->fb_width = overlay->fb_width;
513 win_data->fb_height = overlay->fb_height;
514 win_data->dma_addr = overlay->dma_addr[0] + offset;
515 win_data->bpp = overlay->bpp;
516 win_data->pixel_format = overlay->pixel_format;
517 win_data->buf_offsize = (overlay->fb_width - overlay->crtc_width) *
519 win_data->line_size = overlay->crtc_width * (overlay->bpp >> 3);
521 DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n",
522 win_data->offset_x, win_data->offset_y);
523 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
524 win_data->ovl_width, win_data->ovl_height);
525 DRM_DEBUG_KMS("paddr = 0x%lx\n", (unsigned long)win_data->dma_addr);
526 DRM_DEBUG_KMS("fb_width = %d, crtc_width = %d\n",
527 overlay->fb_width, overlay->crtc_width);
530 static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win)
532 struct fimd_win_data *win_data = &ctx->win_data[win];
538 * In case of s3c64xx, window 0 doesn't support alpha channel.
539 * So the request format is ARGB8888 then change it to XRGB8888.
541 if (ctx->driver_data->has_limited_fmt && !win) {
542 if (win_data->pixel_format == DRM_FORMAT_ARGB8888)
543 win_data->pixel_format = DRM_FORMAT_XRGB8888;
546 switch (win_data->pixel_format) {
548 val |= WINCON0_BPPMODE_8BPP_PALETTE;
549 val |= WINCONx_BURSTLEN_8WORD;
550 val |= WINCONx_BYTSWP;
552 case DRM_FORMAT_XRGB1555:
553 val |= WINCON0_BPPMODE_16BPP_1555;
554 val |= WINCONx_HAWSWP;
555 val |= WINCONx_BURSTLEN_16WORD;
557 case DRM_FORMAT_RGB565:
558 val |= WINCON0_BPPMODE_16BPP_565;
559 val |= WINCONx_HAWSWP;
560 val |= WINCONx_BURSTLEN_16WORD;
562 case DRM_FORMAT_XRGB8888:
563 val |= WINCON0_BPPMODE_24BPP_888;
565 val |= WINCONx_BURSTLEN_16WORD;
567 case DRM_FORMAT_ARGB8888:
568 val |= WINCON1_BPPMODE_25BPP_A1888
569 | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
571 val |= WINCONx_BURSTLEN_16WORD;
574 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
576 val |= WINCON0_BPPMODE_24BPP_888;
578 val |= WINCONx_BURSTLEN_16WORD;
582 DRM_DEBUG_KMS("bpp = %d\n", win_data->bpp);
585 * In case of exynos, setting dma-burst to 16Word causes permanent
586 * tearing for very small buffers, e.g. cursor buffer. Burst Mode
587 * switching which is based on overlay size is not recommended as
588 * overlay size varies alot towards the end of the screen and rapid
589 * movement causes unstable DMA which results into iommu crash/tear.
592 if (win_data->fb_width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
593 val &= ~WINCONx_BURSTLEN_MASK;
594 val |= WINCONx_BURSTLEN_4WORD;
597 writel(val, ctx->regs + WINCON(win));
600 static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win)
602 unsigned int keycon0 = 0, keycon1 = 0;
604 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
605 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
607 keycon1 = WxKEYCON1_COLVAL(0xffffffff);
609 writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
610 writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
614 * shadow_protect_win() - disable updating values from shadow registers at vsync
616 * @win: window to protect registers for
617 * @protect: 1 to protect (disable updates)
619 static void fimd_shadow_protect_win(struct fimd_context *ctx,
620 int win, bool protect)
624 if (ctx->driver_data->has_shadowcon) {
626 bits = SHADOWCON_WINx_PROTECT(win);
629 bits = PRTCON_PROTECT;
632 val = readl(ctx->regs + reg);
637 writel(val, ctx->regs + reg);
640 static void fimd_win_commit(struct exynos_drm_manager *mgr, int zpos)
642 struct fimd_context *ctx = mgr->ctx;
643 struct fimd_win_data *win_data;
645 unsigned long val, alpha, size;
652 if (win == DEFAULT_ZPOS)
653 win = ctx->default_win;
655 if (win < 0 || win >= WINDOWS_NR)
658 win_data = &ctx->win_data[win];
660 /* If suspended, enable this on resume */
661 if (ctx->suspended) {
662 win_data->resume = true;
667 * SHADOWCON/PRTCON register is used for enabling timing.
669 * for example, once only width value of a register is set,
670 * if the dma is started then fimd hardware could malfunction so
671 * with protect window setting, the register fields with prefix '_F'
672 * wouldn't be updated at vsync also but updated once unprotect window
676 /* protect windows */
677 fimd_shadow_protect_win(ctx, win, true);
679 /* buffer start address */
680 val = (unsigned long)win_data->dma_addr;
681 writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
683 /* buffer end address */
684 size = win_data->fb_width * win_data->ovl_height * (win_data->bpp >> 3);
685 val = (unsigned long)(win_data->dma_addr + size);
686 writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
688 DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
689 (unsigned long)win_data->dma_addr, val, size);
690 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
691 win_data->ovl_width, win_data->ovl_height);
694 val = VIDW_BUF_SIZE_OFFSET(win_data->buf_offsize) |
695 VIDW_BUF_SIZE_PAGEWIDTH(win_data->line_size) |
696 VIDW_BUF_SIZE_OFFSET_E(win_data->buf_offsize) |
697 VIDW_BUF_SIZE_PAGEWIDTH_E(win_data->line_size);
698 writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
701 val = VIDOSDxA_TOPLEFT_X(win_data->offset_x) |
702 VIDOSDxA_TOPLEFT_Y(win_data->offset_y) |
703 VIDOSDxA_TOPLEFT_X_E(win_data->offset_x) |
704 VIDOSDxA_TOPLEFT_Y_E(win_data->offset_y);
705 writel(val, ctx->regs + VIDOSD_A(win));
707 last_x = win_data->offset_x + win_data->ovl_width;
710 last_y = win_data->offset_y + win_data->ovl_height;
714 val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) |
715 VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y);
717 writel(val, ctx->regs + VIDOSD_B(win));
719 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
720 win_data->offset_x, win_data->offset_y, last_x, last_y);
722 /* hardware window 0 doesn't support alpha channel. */
725 alpha = VIDISD14C_ALPHA1_R(0xf) |
726 VIDISD14C_ALPHA1_G(0xf) |
727 VIDISD14C_ALPHA1_B(0xf);
729 writel(alpha, ctx->regs + VIDOSD_C(win));
733 if (win != 3 && win != 4) {
734 u32 offset = VIDOSD_D(win);
736 offset = VIDOSD_C(win);
737 val = win_data->ovl_width * win_data->ovl_height;
738 writel(val, ctx->regs + offset);
740 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val);
743 fimd_win_set_pixfmt(ctx, win);
745 /* hardware window 0 doesn't support color key. */
747 fimd_win_set_colkey(ctx, win);
750 val = readl(ctx->regs + WINCON(win));
751 val |= WINCONx_ENWIN;
752 writel(val, ctx->regs + WINCON(win));
754 /* Enable DMA channel and unprotect windows */
755 fimd_shadow_protect_win(ctx, win, false);
757 if (ctx->driver_data->has_shadowcon) {
758 val = readl(ctx->regs + SHADOWCON);
759 val |= SHADOWCON_CHx_ENABLE(win);
760 writel(val, ctx->regs + SHADOWCON);
763 win_data->enabled = true;
766 atomic_set(&ctx->win_updated, 1);
769 static void fimd_win_disable(struct exynos_drm_manager *mgr, int zpos)
771 struct fimd_context *ctx = mgr->ctx;
772 struct fimd_win_data *win_data;
776 if (win == DEFAULT_ZPOS)
777 win = ctx->default_win;
779 if (win < 0 || win >= WINDOWS_NR)
782 win_data = &ctx->win_data[win];
784 if (ctx->suspended) {
785 /* do not resume this window*/
786 win_data->resume = false;
790 /* protect windows */
791 fimd_shadow_protect_win(ctx, win, true);
794 val = readl(ctx->regs + WINCON(win));
795 val &= ~WINCONx_ENWIN;
796 writel(val, ctx->regs + WINCON(win));
798 /* unprotect windows */
799 if (ctx->driver_data->has_shadowcon) {
800 val = readl(ctx->regs + SHADOWCON);
801 val &= ~SHADOWCON_CHx_ENABLE(win);
802 writel(val, ctx->regs + SHADOWCON);
805 fimd_shadow_protect_win(ctx, win, false);
807 win_data->enabled = false;
810 static void fimd_window_suspend(struct exynos_drm_manager *mgr)
812 struct fimd_context *ctx = mgr->ctx;
813 struct fimd_win_data *win_data;
816 for (i = 0; i < WINDOWS_NR; i++) {
817 win_data = &ctx->win_data[i];
818 win_data->resume = win_data->enabled;
819 if (win_data->enabled)
820 fimd_win_disable(mgr, i);
824 static void fimd_window_resume(struct exynos_drm_manager *mgr)
826 struct fimd_context *ctx = mgr->ctx;
827 struct fimd_win_data *win_data;
830 for (i = 0; i < WINDOWS_NR; i++) {
831 win_data = &ctx->win_data[i];
832 win_data->enabled = win_data->resume;
833 win_data->resume = false;
837 static void fimd_apply(struct exynos_drm_manager *mgr)
839 struct fimd_context *ctx = mgr->ctx;
840 struct fimd_win_data *win_data;
843 for (i = 0; i < WINDOWS_NR; i++) {
844 win_data = &ctx->win_data[i];
845 if (win_data->enabled)
846 fimd_win_commit(mgr, i);
848 fimd_win_disable(mgr, i);
854 static int fimd_poweron(struct exynos_drm_manager *mgr)
856 struct fimd_context *ctx = mgr->ctx;
862 ctx->suspended = false;
864 pm_runtime_get_sync(ctx->dev);
866 ret = clk_prepare_enable(ctx->bus_clk);
868 DRM_ERROR("Failed to prepare_enable the bus clk [%d]\n", ret);
872 ret = clk_prepare_enable(ctx->lcd_clk);
874 DRM_ERROR("Failed to prepare_enable the lcd clk [%d]\n", ret);
878 /* if vblank was enabled status, enable it again. */
879 if (test_and_clear_bit(0, &ctx->irq_flags)) {
880 ret = fimd_enable_vblank(mgr);
882 DRM_ERROR("Failed to re-enable vblank [%d]\n", ret);
883 goto enable_vblank_err;
887 fimd_window_resume(mgr);
894 clk_disable_unprepare(ctx->lcd_clk);
896 clk_disable_unprepare(ctx->bus_clk);
898 ctx->suspended = true;
902 static int fimd_poweroff(struct exynos_drm_manager *mgr)
904 struct fimd_context *ctx = mgr->ctx;
910 * We need to make sure that all windows are disabled before we
911 * suspend that connector. Otherwise we might try to scan from
912 * a destroyed buffer later.
914 fimd_window_suspend(mgr);
916 clk_disable_unprepare(ctx->lcd_clk);
917 clk_disable_unprepare(ctx->bus_clk);
919 pm_runtime_put_sync(ctx->dev);
921 ctx->suspended = true;
925 static void fimd_dpms(struct exynos_drm_manager *mgr, int mode)
927 DRM_DEBUG_KMS("%s, %d\n", __FILE__, mode);
930 case DRM_MODE_DPMS_ON:
933 case DRM_MODE_DPMS_STANDBY:
934 case DRM_MODE_DPMS_SUSPEND:
935 case DRM_MODE_DPMS_OFF:
939 DRM_DEBUG_KMS("unspecified mode %d\n", mode);
944 static void fimd_trigger(struct device *dev)
946 struct exynos_drm_manager *mgr = get_fimd_manager(dev);
947 struct fimd_context *ctx = mgr->ctx;
948 struct fimd_driver_data *driver_data = ctx->driver_data;
949 void *timing_base = ctx->regs + driver_data->timing_base;
953 * Skips to trigger if in triggering state, because multiple triggering
954 * requests can cause panel reset.
956 if (atomic_read(&ctx->triggering))
959 atomic_set(&ctx->triggering, 1);
961 reg = readl(ctx->regs + VIDINTCON0);
962 reg |= (VIDINTCON0_INT_ENABLE | VIDINTCON0_INT_I80IFDONE |
963 VIDINTCON0_INT_SYSMAINCON);
964 writel(reg, ctx->regs + VIDINTCON0);
966 reg = readl(timing_base + TRIGCON);
967 reg |= (TRGMODE_I80_RGB_ENABLE_I80 | SWTRGCMD_I80_RGB_ENABLE);
968 writel(reg, timing_base + TRIGCON);
971 static void fimd_te_handler(struct exynos_drm_manager *mgr)
973 struct fimd_context *ctx = mgr->ctx;
975 /* Checks the crtc is detached already from encoder */
976 if (ctx->pipe < 0 || !ctx->drm_dev)
980 * If there is a page flip request, triggers and handles the page flip
981 * event so that current fb can be updated into panel GRAM.
983 if (atomic_add_unless(&ctx->win_updated, -1, 0))
984 fimd_trigger(ctx->dev);
986 /* Wakes up vsync event queue */
987 if (atomic_read(&ctx->wait_vsync_event)) {
988 atomic_set(&ctx->wait_vsync_event, 0);
989 wake_up(&ctx->wait_vsync_queue);
992 if (!atomic_read(&ctx->triggering))
993 drm_handle_vblank(ctx->drm_dev, ctx->pipe);
996 static struct exynos_drm_manager_ops fimd_manager_ops = {
998 .mode_fixup = fimd_mode_fixup,
999 .mode_set = fimd_mode_set,
1000 .commit = fimd_commit,
1001 .enable_vblank = fimd_enable_vblank,
1002 .disable_vblank = fimd_disable_vblank,
1003 .wait_for_vblank = fimd_wait_for_vblank,
1004 .win_mode_set = fimd_win_mode_set,
1005 .win_commit = fimd_win_commit,
1006 .win_disable = fimd_win_disable,
1007 .te_handler = fimd_te_handler,
1010 static struct exynos_drm_manager fimd_manager = {
1011 .type = EXYNOS_DISPLAY_TYPE_LCD,
1012 .ops = &fimd_manager_ops,
1015 static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
1017 struct fimd_context *ctx = (struct fimd_context *)dev_id;
1020 val = readl(ctx->regs + VIDINTCON1);
1022 clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME;
1023 if (val & clear_bit)
1024 writel(clear_bit, ctx->regs + VIDINTCON1);
1026 /* check the crtc is detached already from encoder */
1027 if (ctx->pipe < 0 || !ctx->drm_dev)
1031 /* unset I80 frame done interrupt */
1032 val = readl(ctx->regs + VIDINTCON0);
1033 val &= ~(VIDINTCON0_INT_I80IFDONE | VIDINTCON0_INT_SYSMAINCON);
1034 writel(val, ctx->regs + VIDINTCON0);
1036 /* exit triggering mode */
1037 atomic_set(&ctx->triggering, 0);
1039 drm_handle_vblank(ctx->drm_dev, ctx->pipe);
1040 exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe);
1042 drm_handle_vblank(ctx->drm_dev, ctx->pipe);
1043 exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe);
1045 /* set wait vsync event to zero and wake up queue. */
1046 if (atomic_read(&ctx->wait_vsync_event)) {
1047 atomic_set(&ctx->wait_vsync_event, 0);
1048 wake_up(&ctx->wait_vsync_queue);
1056 static int fimd_bind(struct device *dev, struct device *master, void *data)
1058 struct fimd_context *ctx = fimd_manager.ctx;
1059 struct drm_device *drm_dev = data;
1061 fimd_mgr_initialize(&fimd_manager, drm_dev);
1062 exynos_drm_crtc_create(&fimd_manager);
1064 exynos_drm_create_enc_conn(drm_dev, ctx->display);
1070 static void fimd_unbind(struct device *dev, struct device *master,
1073 struct exynos_drm_manager *mgr = dev_get_drvdata(dev);
1074 struct fimd_context *ctx = fimd_manager.ctx;
1076 fimd_dpms(mgr, DRM_MODE_DPMS_OFF);
1079 exynos_dpi_remove(dev);
1081 fimd_mgr_remove(mgr);
1084 static const struct component_ops fimd_component_ops = {
1086 .unbind = fimd_unbind,
1089 static int fimd_probe(struct platform_device *pdev)
1091 struct device *dev = &pdev->dev;
1092 struct fimd_context *ctx;
1093 struct device_node *i80_if_timings;
1094 struct resource *res;
1097 ret = exynos_drm_component_add(&pdev->dev, EXYNOS_DEVICE_TYPE_CRTC,
1102 if (!dev->of_node) {
1104 goto err_del_component;
1107 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1110 goto err_del_component;
1114 ctx->suspended = true;
1115 ctx->driver_data = drm_fimd_get_driver_data(pdev);
1117 if (of_property_read_bool(dev->of_node, "samsung,invert-vden"))
1118 ctx->vidcon1 |= VIDCON1_INV_VDEN;
1119 if (of_property_read_bool(dev->of_node, "samsung,invert-vclk"))
1120 ctx->vidcon1 |= VIDCON1_INV_VCLK;
1122 i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings");
1123 if (i80_if_timings) {
1128 if (ctx->driver_data->has_vidoutcon)
1129 ctx->vidout_con |= VIDOUT_CON_F_I80_LDI0;
1131 ctx->vidcon0 |= VIDCON0_VIDOUT_I80_LDI0;
1133 * The user manual describes that this "DSI_EN" bit is required
1134 * to enable I80 24-bit data interface.
1136 ctx->vidcon0 |= VIDCON0_DSI_EN;
1138 if (of_property_read_u32(i80_if_timings, "cs-setup", &val))
1140 ctx->i80ifcon = LCD_CS_SETUP(val);
1141 if (of_property_read_u32(i80_if_timings, "wr-setup", &val))
1143 ctx->i80ifcon |= LCD_WR_SETUP(val);
1144 if (of_property_read_u32(i80_if_timings, "wr-active", &val))
1146 ctx->i80ifcon |= LCD_WR_ACTIVE(val);
1147 if (of_property_read_u32(i80_if_timings, "wr-hold", &val))
1149 ctx->i80ifcon |= LCD_WR_HOLD(val);
1151 of_node_put(i80_if_timings);
1153 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
1155 if (IS_ERR(ctx->sysreg)) {
1156 dev_warn(dev, "failed to get system register.\n");
1160 ctx->bus_clk = devm_clk_get(dev, "fimd");
1161 if (IS_ERR(ctx->bus_clk)) {
1162 dev_err(dev, "failed to get bus clock\n");
1163 ret = PTR_ERR(ctx->bus_clk);
1164 goto err_del_component;
1167 ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd");
1168 if (IS_ERR(ctx->lcd_clk)) {
1169 dev_err(dev, "failed to get lcd clock\n");
1170 ret = PTR_ERR(ctx->lcd_clk);
1171 goto err_del_component;
1174 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1176 ctx->regs = devm_ioremap_resource(dev, res);
1177 if (IS_ERR(ctx->regs)) {
1178 ret = PTR_ERR(ctx->regs);
1179 goto err_del_component;
1182 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1183 ctx->i80_if ? "lcd_sys" : "vsync");
1185 dev_err(dev, "irq request failed.\n");
1187 goto err_del_component;
1190 ret = devm_request_irq(dev, res->start, fimd_irq_handler,
1191 0, "drm_fimd", ctx);
1193 dev_err(dev, "irq request failed.\n");
1194 goto err_del_component;
1197 init_waitqueue_head(&ctx->wait_vsync_queue);
1198 atomic_set(&ctx->wait_vsync_event, 0);
1200 platform_set_drvdata(pdev, &fimd_manager);
1202 fimd_manager.ctx = ctx;
1204 ctx->display = exynos_dpi_probe(dev);
1205 if (IS_ERR(ctx->display))
1206 return PTR_ERR(ctx->display);
1208 pm_runtime_enable(&pdev->dev);
1210 ret = component_add(&pdev->dev, &fimd_component_ops);
1212 goto err_disable_pm_runtime;
1216 err_disable_pm_runtime:
1217 pm_runtime_disable(&pdev->dev);
1220 exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CRTC);
1224 static int fimd_remove(struct platform_device *pdev)
1226 pm_runtime_disable(&pdev->dev);
1228 component_del(&pdev->dev, &fimd_component_ops);
1229 exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CRTC);
1234 struct platform_driver fimd_driver = {
1235 .probe = fimd_probe,
1236 .remove = fimd_remove,
1238 .name = "exynos4-fb",
1239 .owner = THIS_MODULE,
1240 .of_match_table = fimd_driver_dt_match,