3 * Copyright (C) 2011 Samsung Electronics Co.Ltd
5 * Joonyoung Shim <jy0922.shim@samsung.com>
6 * Inki Dae <inki.dae@samsung.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
16 #include <linux/kernel.h>
17 #include <linux/platform_device.h>
18 #include <linux/clk.h>
20 #include <linux/of_device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/component.h>
23 #include <linux/mfd/syscon.h>
24 #include <linux/regmap.h>
26 #include <video/of_display_timing.h>
27 #include <video/of_videomode.h>
28 #include <video/samsung_fimd.h>
29 #include <drm/exynos_drm.h>
31 #include "exynos_drm_drv.h"
32 #include "exynos_drm_fbdev.h"
33 #include "exynos_drm_crtc.h"
34 #include "exynos_drm_iommu.h"
37 * FIMD stands for Fully Interactive Mobile Display and
38 * as a display controller, it transfers contents drawn on memory
39 * to a LCD Panel through Display Interfaces such as RGB or
43 #define FIMD_DEFAULT_FRAMERATE 60
44 #define MIN_FB_WIDTH_FOR_16WORD_BURST 128
46 /* position control register for hardware window 0, 2 ~ 4.*/
47 #define VIDOSD_A(win) (VIDOSD_BASE + 0x00 + (win) * 16)
48 #define VIDOSD_B(win) (VIDOSD_BASE + 0x04 + (win) * 16)
50 * size control register for hardware windows 0 and alpha control register
51 * for hardware windows 1 ~ 4
53 #define VIDOSD_C(win) (VIDOSD_BASE + 0x08 + (win) * 16)
54 /* size control register for hardware windows 1 ~ 2. */
55 #define VIDOSD_D(win) (VIDOSD_BASE + 0x0C + (win) * 16)
57 #define VIDWx_BUF_START(win, buf) (VIDW_BUF_START(buf) + (win) * 8)
58 #define VIDWx_BUF_END(win, buf) (VIDW_BUF_END(buf) + (win) * 8)
59 #define VIDWx_BUF_SIZE(win, buf) (VIDW_BUF_SIZE(buf) + (win) * 4)
61 /* color key control register for hardware window 1 ~ 4. */
62 #define WKEYCON0_BASE(x) ((WKEYCON0 + 0x140) + ((x - 1) * 8))
63 /* color key value register for hardware window 1 ~ 4. */
64 #define WKEYCON1_BASE(x) ((WKEYCON1 + 0x140) + ((x - 1) * 8))
66 /* I80 / RGB trigger control register */
68 #define TRGMODE_I80_RGB_ENABLE_I80 (1 << 0)
69 #define SWTRGCMD_I80_RGB_ENABLE (1 << 1)
71 /* display mode change control register except exynos4 */
72 #define VIDOUT_CON 0x000
73 #define VIDOUT_CON_F_I80_LDI0 (0x2 << 8)
75 /* I80 interface control for main LDI register */
76 #define I80IFCONFAx(x) (0x1B0 + (x) * 4)
77 #define I80IFCONFBx(x) (0x1B8 + (x) * 4)
78 #define LCD_CS_SETUP(x) ((x) << 16)
79 #define LCD_WR_SETUP(x) ((x) << 12)
80 #define LCD_WR_ACTIVE(x) ((x) << 8)
81 #define LCD_WR_HOLD(x) ((x) << 4)
82 #define I80IFEN_ENABLE (1 << 0)
84 /* FIMD has totally five hardware windows. */
87 #define get_fimd_manager(mgr) platform_get_drvdata(to_platform_device(dev))
89 struct fimd_driver_data {
90 unsigned int timing_base;
91 unsigned int lcdblk_offset;
92 unsigned int lcdblk_vt_shift;
93 unsigned int lcdblk_bypass_shift;
95 unsigned int has_shadowcon:1;
96 unsigned int has_clksel:1;
97 unsigned int has_limited_fmt:1;
98 unsigned int has_vidoutcon:1;
101 static struct fimd_driver_data s3c64xx_fimd_driver_data = {
104 .has_limited_fmt = 1,
107 static struct fimd_driver_data exynos4_fimd_driver_data = {
109 .lcdblk_offset = 0x210,
110 .lcdblk_vt_shift = 10,
111 .lcdblk_bypass_shift = 1,
115 static struct fimd_driver_data exynos5_fimd_driver_data = {
116 .timing_base = 0x20000,
117 .lcdblk_offset = 0x214,
118 .lcdblk_vt_shift = 24,
119 .lcdblk_bypass_shift = 15,
124 struct fimd_win_data {
125 unsigned int offset_x;
126 unsigned int offset_y;
127 unsigned int ovl_width;
128 unsigned int ovl_height;
129 unsigned int fb_width;
130 unsigned int fb_height;
132 unsigned int pixel_format;
134 unsigned int buf_offsize;
135 unsigned int line_size; /* bytes */
140 struct fimd_context {
142 struct drm_device *drm_dev;
146 struct regmap *sysreg;
147 struct drm_display_mode mode;
148 struct fimd_win_data win_data[WINDOWS_NR];
149 unsigned int default_win;
150 unsigned long irq_flags;
158 wait_queue_head_t wait_vsync_queue;
159 atomic_t wait_vsync_event;
160 atomic_t win_updated;
163 struct exynos_drm_panel_info panel;
164 struct fimd_driver_data *driver_data;
165 struct exynos_drm_display *display;
168 static const struct of_device_id fimd_driver_dt_match[] = {
169 { .compatible = "samsung,s3c6400-fimd",
170 .data = &s3c64xx_fimd_driver_data },
171 { .compatible = "samsung,exynos4210-fimd",
172 .data = &exynos4_fimd_driver_data },
173 { .compatible = "samsung,exynos5250-fimd",
174 .data = &exynos5_fimd_driver_data },
177 MODULE_DEVICE_TABLE(of, fimd_driver_dt_match);
179 static inline struct fimd_driver_data *drm_fimd_get_driver_data(
180 struct platform_device *pdev)
182 const struct of_device_id *of_id =
183 of_match_device(fimd_driver_dt_match, &pdev->dev);
185 return (struct fimd_driver_data *)of_id->data;
188 static void fimd_wait_for_vblank(struct exynos_drm_manager *mgr)
190 struct fimd_context *ctx = mgr->ctx;
195 atomic_set(&ctx->wait_vsync_event, 1);
198 * wait for FIMD to signal VSYNC interrupt or return after
199 * timeout which is set to 50ms (refresh rate of 20).
201 if (!wait_event_timeout(ctx->wait_vsync_queue,
202 !atomic_read(&ctx->wait_vsync_event),
204 DRM_DEBUG_KMS("vblank wait timed out.\n");
208 static void fimd_clear_channel(struct exynos_drm_manager *mgr)
210 struct fimd_context *ctx = mgr->ctx;
211 int win, ch_enabled = 0;
213 DRM_DEBUG_KMS("%s\n", __FILE__);
215 /* Check if any channel is enabled. */
216 for (win = 0; win < WINDOWS_NR; win++) {
217 u32 val = readl(ctx->regs + SHADOWCON);
218 if (val & SHADOWCON_CHx_ENABLE(win)) {
219 val &= ~SHADOWCON_CHx_ENABLE(win);
220 writel(val, ctx->regs + SHADOWCON);
225 /* Wait for vsync, as disable channel takes effect at next vsync */
227 fimd_wait_for_vblank(mgr);
230 static int fimd_mgr_initialize(struct exynos_drm_manager *mgr,
231 struct drm_device *drm_dev)
233 struct fimd_context *ctx = mgr->ctx;
234 struct exynos_drm_private *priv;
235 priv = drm_dev->dev_private;
237 mgr->drm_dev = ctx->drm_dev = drm_dev;
238 mgr->pipe = ctx->pipe = priv->pipe++;
241 * enable drm irq mode.
242 * - with irq_enabled = true, we can use the vblank feature.
244 * P.S. note that we wouldn't use drm irq handler but
245 * just specific driver own one instead because
246 * drm framework supports only one irq handler.
248 drm_dev->irq_enabled = true;
251 * with vblank_disable_allowed = true, vblank interrupt will be disabled
252 * by drm timer once a current process gives up ownership of
253 * vblank event.(after drm_vblank_put function is called)
255 drm_dev->vblank_disable_allowed = true;
257 /* attach this sub driver to iommu mapping if supported. */
258 if (is_drm_iommu_supported(ctx->drm_dev)) {
260 * If any channel is already active, iommu will throw
261 * a PAGE FAULT when enabled. So clear any channel if enabled.
263 fimd_clear_channel(mgr);
264 drm_iommu_attach_device(ctx->drm_dev, ctx->dev);
270 static void fimd_mgr_remove(struct exynos_drm_manager *mgr)
272 struct fimd_context *ctx = mgr->ctx;
274 /* detach this sub driver from iommu mapping if supported. */
275 if (is_drm_iommu_supported(ctx->drm_dev))
276 drm_iommu_detach_device(ctx->drm_dev, ctx->dev);
279 static u32 fimd_calc_clkdiv(struct fimd_context *ctx,
280 const struct drm_display_mode *mode)
282 unsigned long ideal_clk = mode->htotal * mode->vtotal * mode->vrefresh;
287 * The frame done interrupt should be occurred prior to the
293 /* Find the clock divider value that gets us closest to ideal_clk */
294 clkdiv = DIV_ROUND_UP(clk_get_rate(ctx->lcd_clk), ideal_clk);
296 return (clkdiv < 0x100) ? clkdiv : 0xff;
299 static bool fimd_mode_fixup(struct exynos_drm_manager *mgr,
300 const struct drm_display_mode *mode,
301 struct drm_display_mode *adjusted_mode)
303 if (adjusted_mode->vrefresh == 0)
304 adjusted_mode->vrefresh = FIMD_DEFAULT_FRAMERATE;
309 static void fimd_mode_set(struct exynos_drm_manager *mgr,
310 const struct drm_display_mode *in_mode)
312 struct fimd_context *ctx = mgr->ctx;
314 drm_mode_copy(&ctx->mode, in_mode);
317 static void fimd_commit(struct exynos_drm_manager *mgr)
319 struct fimd_context *ctx = mgr->ctx;
320 struct drm_display_mode *mode = &ctx->mode;
321 struct fimd_driver_data *driver_data = ctx->driver_data;
322 void *timing_base = ctx->regs + driver_data->timing_base;
328 /* nothing to do if we haven't set the mode yet */
329 if (mode->htotal == 0 || mode->vtotal == 0)
333 val = ctx->i80ifcon | I80IFEN_ENABLE;
334 writel(val, timing_base + I80IFCONFAx(0));
336 /* disable auto frame rate */
337 writel(0, timing_base + I80IFCONFBx(0));
339 /* set video type selection to I80 interface */
340 if (ctx->sysreg && regmap_update_bits(ctx->sysreg,
341 driver_data->lcdblk_offset,
342 0x3 << driver_data->lcdblk_vt_shift,
343 0x1 << driver_data->lcdblk_vt_shift)) {
344 DRM_ERROR("Failed to update sysreg for I80 i/f.\n");
348 int vsync_len, vbpd, vfpd, hsync_len, hbpd, hfpd;
351 /* setup polarity values */
352 vidcon1 = ctx->vidcon1;
353 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
354 vidcon1 |= VIDCON1_INV_VSYNC;
355 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
356 vidcon1 |= VIDCON1_INV_HSYNC;
357 writel(vidcon1, ctx->regs + driver_data->timing_base + VIDCON1);
359 /* setup vertical timing values. */
360 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
361 vbpd = mode->crtc_vtotal - mode->crtc_vsync_end;
362 vfpd = mode->crtc_vsync_start - mode->crtc_vdisplay;
364 val = VIDTCON0_VBPD(vbpd - 1) |
365 VIDTCON0_VFPD(vfpd - 1) |
366 VIDTCON0_VSPW(vsync_len - 1);
367 writel(val, ctx->regs + driver_data->timing_base + VIDTCON0);
369 /* setup horizontal timing values. */
370 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
371 hbpd = mode->crtc_htotal - mode->crtc_hsync_end;
372 hfpd = mode->crtc_hsync_start - mode->crtc_hdisplay;
374 val = VIDTCON1_HBPD(hbpd - 1) |
375 VIDTCON1_HFPD(hfpd - 1) |
376 VIDTCON1_HSPW(hsync_len - 1);
377 writel(val, ctx->regs + driver_data->timing_base + VIDTCON1);
380 if (driver_data->has_vidoutcon)
381 writel(ctx->vidout_con, timing_base + VIDOUT_CON);
383 /* set bypass selection */
384 if (ctx->sysreg && regmap_update_bits(ctx->sysreg,
385 driver_data->lcdblk_offset,
386 0x1 << driver_data->lcdblk_bypass_shift,
387 0x1 << driver_data->lcdblk_bypass_shift)) {
388 DRM_ERROR("Failed to update sysreg for bypass setting.\n");
392 /* setup horizontal and vertical display size. */
393 val = VIDTCON2_LINEVAL(mode->vdisplay - 1) |
394 VIDTCON2_HOZVAL(mode->hdisplay - 1) |
395 VIDTCON2_LINEVAL_E(mode->vdisplay - 1) |
396 VIDTCON2_HOZVAL_E(mode->hdisplay - 1);
397 writel(val, ctx->regs + driver_data->timing_base + VIDTCON2);
400 * fields of register with prefix '_F' would be updated
401 * at vsync(same as dma start)
404 val |= VIDCON0_ENVID | VIDCON0_ENVID_F;
406 if (ctx->driver_data->has_clksel)
407 val |= VIDCON0_CLKSEL_LCD;
409 clkdiv = fimd_calc_clkdiv(ctx, mode);
411 val |= VIDCON0_CLKVAL_F(clkdiv - 1) | VIDCON0_CLKDIR;
413 writel(val, ctx->regs + VIDCON0);
416 static int fimd_enable_vblank(struct exynos_drm_manager *mgr)
418 struct fimd_context *ctx = mgr->ctx;
424 if (!test_and_set_bit(0, &ctx->irq_flags)) {
425 val = readl(ctx->regs + VIDINTCON0);
427 val |= VIDINTCON0_INT_ENABLE;
428 val |= VIDINTCON0_INT_FRAME;
430 val &= ~VIDINTCON0_FRAMESEL0_MASK;
431 val |= VIDINTCON0_FRAMESEL0_VSYNC;
432 val &= ~VIDINTCON0_FRAMESEL1_MASK;
433 val |= VIDINTCON0_FRAMESEL1_NONE;
435 writel(val, ctx->regs + VIDINTCON0);
441 static void fimd_disable_vblank(struct exynos_drm_manager *mgr)
443 struct fimd_context *ctx = mgr->ctx;
449 if (test_and_clear_bit(0, &ctx->irq_flags)) {
450 val = readl(ctx->regs + VIDINTCON0);
452 val &= ~VIDINTCON0_INT_FRAME;
453 val &= ~VIDINTCON0_INT_ENABLE;
455 writel(val, ctx->regs + VIDINTCON0);
459 static void fimd_win_mode_set(struct exynos_drm_manager *mgr,
460 struct exynos_drm_overlay *overlay)
462 struct fimd_context *ctx = mgr->ctx;
463 struct fimd_win_data *win_data;
465 unsigned long offset;
468 DRM_ERROR("overlay is NULL\n");
473 if (win == DEFAULT_ZPOS)
474 win = ctx->default_win;
476 if (win < 0 || win >= WINDOWS_NR)
479 offset = overlay->fb_x * (overlay->bpp >> 3);
480 offset += overlay->fb_y * overlay->pitch;
482 DRM_DEBUG_KMS("offset = 0x%lx, pitch = %x\n", offset, overlay->pitch);
484 win_data = &ctx->win_data[win];
486 win_data->offset_x = overlay->crtc_x;
487 win_data->offset_y = overlay->crtc_y;
488 win_data->ovl_width = overlay->crtc_width;
489 win_data->ovl_height = overlay->crtc_height;
490 win_data->fb_width = overlay->fb_width;
491 win_data->fb_height = overlay->fb_height;
492 win_data->dma_addr = overlay->dma_addr[0] + offset;
493 win_data->bpp = overlay->bpp;
494 win_data->pixel_format = overlay->pixel_format;
495 win_data->buf_offsize = (overlay->fb_width - overlay->crtc_width) *
497 win_data->line_size = overlay->crtc_width * (overlay->bpp >> 3);
499 DRM_DEBUG_KMS("offset_x = %d, offset_y = %d\n",
500 win_data->offset_x, win_data->offset_y);
501 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
502 win_data->ovl_width, win_data->ovl_height);
503 DRM_DEBUG_KMS("paddr = 0x%lx\n", (unsigned long)win_data->dma_addr);
504 DRM_DEBUG_KMS("fb_width = %d, crtc_width = %d\n",
505 overlay->fb_width, overlay->crtc_width);
508 static void fimd_win_set_pixfmt(struct fimd_context *ctx, unsigned int win)
510 struct fimd_win_data *win_data = &ctx->win_data[win];
516 * In case of s3c64xx, window 0 doesn't support alpha channel.
517 * So the request format is ARGB8888 then change it to XRGB8888.
519 if (ctx->driver_data->has_limited_fmt && !win) {
520 if (win_data->pixel_format == DRM_FORMAT_ARGB8888)
521 win_data->pixel_format = DRM_FORMAT_XRGB8888;
524 switch (win_data->pixel_format) {
526 val |= WINCON0_BPPMODE_8BPP_PALETTE;
527 val |= WINCONx_BURSTLEN_8WORD;
528 val |= WINCONx_BYTSWP;
530 case DRM_FORMAT_XRGB1555:
531 val |= WINCON0_BPPMODE_16BPP_1555;
532 val |= WINCONx_HAWSWP;
533 val |= WINCONx_BURSTLEN_16WORD;
535 case DRM_FORMAT_RGB565:
536 val |= WINCON0_BPPMODE_16BPP_565;
537 val |= WINCONx_HAWSWP;
538 val |= WINCONx_BURSTLEN_16WORD;
540 case DRM_FORMAT_XRGB8888:
541 val |= WINCON0_BPPMODE_24BPP_888;
543 val |= WINCONx_BURSTLEN_16WORD;
545 case DRM_FORMAT_ARGB8888:
546 val |= WINCON1_BPPMODE_25BPP_A1888
547 | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
549 val |= WINCONx_BURSTLEN_16WORD;
552 DRM_DEBUG_KMS("invalid pixel size so using unpacked 24bpp.\n");
554 val |= WINCON0_BPPMODE_24BPP_888;
556 val |= WINCONx_BURSTLEN_16WORD;
560 DRM_DEBUG_KMS("bpp = %d\n", win_data->bpp);
563 * In case of exynos, setting dma-burst to 16Word causes permanent
564 * tearing for very small buffers, e.g. cursor buffer. Burst Mode
565 * switching which is based on overlay size is not recommended as
566 * overlay size varies alot towards the end of the screen and rapid
567 * movement causes unstable DMA which results into iommu crash/tear.
570 if (win_data->fb_width < MIN_FB_WIDTH_FOR_16WORD_BURST) {
571 val &= ~WINCONx_BURSTLEN_MASK;
572 val |= WINCONx_BURSTLEN_4WORD;
575 writel(val, ctx->regs + WINCON(win));
578 static void fimd_win_set_colkey(struct fimd_context *ctx, unsigned int win)
580 unsigned int keycon0 = 0, keycon1 = 0;
582 keycon0 = ~(WxKEYCON0_KEYBL_EN | WxKEYCON0_KEYEN_F |
583 WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
585 keycon1 = WxKEYCON1_COLVAL(0xffffffff);
587 writel(keycon0, ctx->regs + WKEYCON0_BASE(win));
588 writel(keycon1, ctx->regs + WKEYCON1_BASE(win));
592 * shadow_protect_win() - disable updating values from shadow registers at vsync
594 * @win: window to protect registers for
595 * @protect: 1 to protect (disable updates)
597 static void fimd_shadow_protect_win(struct fimd_context *ctx,
598 int win, bool protect)
602 if (ctx->driver_data->has_shadowcon) {
604 bits = SHADOWCON_WINx_PROTECT(win);
607 bits = PRTCON_PROTECT;
610 val = readl(ctx->regs + reg);
615 writel(val, ctx->regs + reg);
618 static void fimd_win_commit(struct exynos_drm_manager *mgr, int zpos)
620 struct fimd_context *ctx = mgr->ctx;
621 struct fimd_win_data *win_data;
623 unsigned long val, alpha, size;
630 if (win == DEFAULT_ZPOS)
631 win = ctx->default_win;
633 if (win < 0 || win >= WINDOWS_NR)
636 win_data = &ctx->win_data[win];
638 /* If suspended, enable this on resume */
639 if (ctx->suspended) {
640 win_data->resume = true;
645 * SHADOWCON/PRTCON register is used for enabling timing.
647 * for example, once only width value of a register is set,
648 * if the dma is started then fimd hardware could malfunction so
649 * with protect window setting, the register fields with prefix '_F'
650 * wouldn't be updated at vsync also but updated once unprotect window
654 /* protect windows */
655 fimd_shadow_protect_win(ctx, win, true);
657 /* buffer start address */
658 val = (unsigned long)win_data->dma_addr;
659 writel(val, ctx->regs + VIDWx_BUF_START(win, 0));
661 /* buffer end address */
662 size = win_data->fb_width * win_data->ovl_height * (win_data->bpp >> 3);
663 val = (unsigned long)(win_data->dma_addr + size);
664 writel(val, ctx->regs + VIDWx_BUF_END(win, 0));
666 DRM_DEBUG_KMS("start addr = 0x%lx, end addr = 0x%lx, size = 0x%lx\n",
667 (unsigned long)win_data->dma_addr, val, size);
668 DRM_DEBUG_KMS("ovl_width = %d, ovl_height = %d\n",
669 win_data->ovl_width, win_data->ovl_height);
672 val = VIDW_BUF_SIZE_OFFSET(win_data->buf_offsize) |
673 VIDW_BUF_SIZE_PAGEWIDTH(win_data->line_size) |
674 VIDW_BUF_SIZE_OFFSET_E(win_data->buf_offsize) |
675 VIDW_BUF_SIZE_PAGEWIDTH_E(win_data->line_size);
676 writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0));
679 val = VIDOSDxA_TOPLEFT_X(win_data->offset_x) |
680 VIDOSDxA_TOPLEFT_Y(win_data->offset_y) |
681 VIDOSDxA_TOPLEFT_X_E(win_data->offset_x) |
682 VIDOSDxA_TOPLEFT_Y_E(win_data->offset_y);
683 writel(val, ctx->regs + VIDOSD_A(win));
685 last_x = win_data->offset_x + win_data->ovl_width;
688 last_y = win_data->offset_y + win_data->ovl_height;
692 val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) |
693 VIDOSDxB_BOTRIGHT_X_E(last_x) | VIDOSDxB_BOTRIGHT_Y_E(last_y);
695 writel(val, ctx->regs + VIDOSD_B(win));
697 DRM_DEBUG_KMS("osd pos: tx = %d, ty = %d, bx = %d, by = %d\n",
698 win_data->offset_x, win_data->offset_y, last_x, last_y);
700 /* hardware window 0 doesn't support alpha channel. */
703 alpha = VIDISD14C_ALPHA1_R(0xf) |
704 VIDISD14C_ALPHA1_G(0xf) |
705 VIDISD14C_ALPHA1_B(0xf);
707 writel(alpha, ctx->regs + VIDOSD_C(win));
711 if (win != 3 && win != 4) {
712 u32 offset = VIDOSD_D(win);
714 offset = VIDOSD_C(win);
715 val = win_data->ovl_width * win_data->ovl_height;
716 writel(val, ctx->regs + offset);
718 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val);
721 fimd_win_set_pixfmt(ctx, win);
723 /* hardware window 0 doesn't support color key. */
725 fimd_win_set_colkey(ctx, win);
728 val = readl(ctx->regs + WINCON(win));
729 val |= WINCONx_ENWIN;
730 writel(val, ctx->regs + WINCON(win));
732 /* Enable DMA channel and unprotect windows */
733 fimd_shadow_protect_win(ctx, win, false);
735 if (ctx->driver_data->has_shadowcon) {
736 val = readl(ctx->regs + SHADOWCON);
737 val |= SHADOWCON_CHx_ENABLE(win);
738 writel(val, ctx->regs + SHADOWCON);
741 win_data->enabled = true;
744 atomic_set(&ctx->win_updated, 1);
747 static void fimd_win_disable(struct exynos_drm_manager *mgr, int zpos)
749 struct fimd_context *ctx = mgr->ctx;
750 struct fimd_win_data *win_data;
754 if (win == DEFAULT_ZPOS)
755 win = ctx->default_win;
757 if (win < 0 || win >= WINDOWS_NR)
760 win_data = &ctx->win_data[win];
762 if (ctx->suspended) {
763 /* do not resume this window*/
764 win_data->resume = false;
768 /* protect windows */
769 fimd_shadow_protect_win(ctx, win, true);
772 val = readl(ctx->regs + WINCON(win));
773 val &= ~WINCONx_ENWIN;
774 writel(val, ctx->regs + WINCON(win));
776 /* unprotect windows */
777 if (ctx->driver_data->has_shadowcon) {
778 val = readl(ctx->regs + SHADOWCON);
779 val &= ~SHADOWCON_CHx_ENABLE(win);
780 writel(val, ctx->regs + SHADOWCON);
783 fimd_shadow_protect_win(ctx, win, false);
785 win_data->enabled = false;
788 static void fimd_window_suspend(struct exynos_drm_manager *mgr)
790 struct fimd_context *ctx = mgr->ctx;
791 struct fimd_win_data *win_data;
794 for (i = 0; i < WINDOWS_NR; i++) {
795 win_data = &ctx->win_data[i];
796 win_data->resume = win_data->enabled;
797 if (win_data->enabled)
798 fimd_win_disable(mgr, i);
800 fimd_wait_for_vblank(mgr);
803 static void fimd_window_resume(struct exynos_drm_manager *mgr)
805 struct fimd_context *ctx = mgr->ctx;
806 struct fimd_win_data *win_data;
809 for (i = 0; i < WINDOWS_NR; i++) {
810 win_data = &ctx->win_data[i];
811 win_data->enabled = win_data->resume;
812 win_data->resume = false;
816 static void fimd_apply(struct exynos_drm_manager *mgr)
818 struct fimd_context *ctx = mgr->ctx;
819 struct fimd_win_data *win_data;
822 for (i = 0; i < WINDOWS_NR; i++) {
823 win_data = &ctx->win_data[i];
824 if (win_data->enabled)
825 fimd_win_commit(mgr, i);
827 fimd_win_disable(mgr, i);
833 static int fimd_poweron(struct exynos_drm_manager *mgr)
835 struct fimd_context *ctx = mgr->ctx;
841 ctx->suspended = false;
843 pm_runtime_get_sync(ctx->dev);
845 ret = clk_prepare_enable(ctx->bus_clk);
847 DRM_ERROR("Failed to prepare_enable the bus clk [%d]\n", ret);
851 ret = clk_prepare_enable(ctx->lcd_clk);
853 DRM_ERROR("Failed to prepare_enable the lcd clk [%d]\n", ret);
857 /* if vblank was enabled status, enable it again. */
858 if (test_and_clear_bit(0, &ctx->irq_flags)) {
859 ret = fimd_enable_vblank(mgr);
861 DRM_ERROR("Failed to re-enable vblank [%d]\n", ret);
862 goto enable_vblank_err;
866 fimd_window_resume(mgr);
873 clk_disable_unprepare(ctx->lcd_clk);
875 clk_disable_unprepare(ctx->bus_clk);
877 ctx->suspended = true;
881 static int fimd_poweroff(struct exynos_drm_manager *mgr)
883 struct fimd_context *ctx = mgr->ctx;
889 * We need to make sure that all windows are disabled before we
890 * suspend that connector. Otherwise we might try to scan from
891 * a destroyed buffer later.
893 fimd_window_suspend(mgr);
895 clk_disable_unprepare(ctx->lcd_clk);
896 clk_disable_unprepare(ctx->bus_clk);
898 pm_runtime_put_sync(ctx->dev);
900 ctx->suspended = true;
904 static void fimd_dpms(struct exynos_drm_manager *mgr, int mode)
906 DRM_DEBUG_KMS("%s, %d\n", __FILE__, mode);
909 case DRM_MODE_DPMS_ON:
912 case DRM_MODE_DPMS_STANDBY:
913 case DRM_MODE_DPMS_SUSPEND:
914 case DRM_MODE_DPMS_OFF:
918 DRM_DEBUG_KMS("unspecified mode %d\n", mode);
923 static void fimd_trigger(struct device *dev)
925 struct exynos_drm_manager *mgr = get_fimd_manager(dev);
926 struct fimd_context *ctx = mgr->ctx;
927 struct fimd_driver_data *driver_data = ctx->driver_data;
928 void *timing_base = ctx->regs + driver_data->timing_base;
931 atomic_set(&ctx->triggering, 1);
933 reg = readl(ctx->regs + VIDINTCON0);
934 reg |= (VIDINTCON0_INT_ENABLE | VIDINTCON0_INT_I80IFDONE |
935 VIDINTCON0_INT_SYSMAINCON);
936 writel(reg, ctx->regs + VIDINTCON0);
938 reg = readl(timing_base + TRIGCON);
939 reg |= (TRGMODE_I80_RGB_ENABLE_I80 | SWTRGCMD_I80_RGB_ENABLE);
940 writel(reg, timing_base + TRIGCON);
943 static void fimd_te_handler(struct exynos_drm_manager *mgr)
945 struct fimd_context *ctx = mgr->ctx;
947 /* Checks the crtc is detached already from encoder */
948 if (ctx->pipe < 0 || !ctx->drm_dev)
952 * Skips to trigger if in triggering state, because multiple triggering
953 * requests can cause panel reset.
955 if (atomic_read(&ctx->triggering))
959 * If there is a page flip request, triggers and handles the page flip
960 * event so that current fb can be updated into panel GRAM.
962 if (atomic_add_unless(&ctx->win_updated, -1, 0))
963 fimd_trigger(ctx->dev);
965 /* Wakes up vsync event queue */
966 if (atomic_read(&ctx->wait_vsync_event)) {
967 atomic_set(&ctx->wait_vsync_event, 0);
968 wake_up(&ctx->wait_vsync_queue);
970 if (!atomic_read(&ctx->triggering))
971 drm_handle_vblank(ctx->drm_dev, ctx->pipe);
975 static struct exynos_drm_manager_ops fimd_manager_ops = {
977 .mode_fixup = fimd_mode_fixup,
978 .mode_set = fimd_mode_set,
979 .commit = fimd_commit,
980 .enable_vblank = fimd_enable_vblank,
981 .disable_vblank = fimd_disable_vblank,
982 .wait_for_vblank = fimd_wait_for_vblank,
983 .win_mode_set = fimd_win_mode_set,
984 .win_commit = fimd_win_commit,
985 .win_disable = fimd_win_disable,
986 .te_handler = fimd_te_handler,
989 static struct exynos_drm_manager fimd_manager = {
990 .type = EXYNOS_DISPLAY_TYPE_LCD,
991 .ops = &fimd_manager_ops,
994 static irqreturn_t fimd_irq_handler(int irq, void *dev_id)
996 struct fimd_context *ctx = (struct fimd_context *)dev_id;
999 val = readl(ctx->regs + VIDINTCON1);
1001 clear_bit = ctx->i80_if ? VIDINTCON1_INT_I80 : VIDINTCON1_INT_FRAME;
1002 if (val & clear_bit)
1003 writel(clear_bit, ctx->regs + VIDINTCON1);
1005 /* check the crtc is detached already from encoder */
1006 if (ctx->pipe < 0 || !ctx->drm_dev)
1010 /* unset I80 frame done interrupt */
1011 val = readl(ctx->regs + VIDINTCON0);
1012 val &= ~(VIDINTCON0_INT_I80IFDONE | VIDINTCON0_INT_SYSMAINCON);
1013 writel(val, ctx->regs + VIDINTCON0);
1015 /* exit triggering mode */
1016 atomic_set(&ctx->triggering, 0);
1018 drm_handle_vblank(ctx->drm_dev, ctx->pipe);
1019 exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe);
1021 drm_handle_vblank(ctx->drm_dev, ctx->pipe);
1022 exynos_drm_crtc_finish_pageflip(ctx->drm_dev, ctx->pipe);
1024 /* set wait vsync event to zero and wake up queue. */
1025 if (atomic_read(&ctx->wait_vsync_event)) {
1026 atomic_set(&ctx->wait_vsync_event, 0);
1027 wake_up(&ctx->wait_vsync_queue);
1035 static int fimd_bind(struct device *dev, struct device *master, void *data)
1037 struct fimd_context *ctx = fimd_manager.ctx;
1038 struct drm_device *drm_dev = data;
1040 fimd_mgr_initialize(&fimd_manager, drm_dev);
1041 exynos_drm_crtc_create(&fimd_manager);
1043 exynos_drm_create_enc_conn(drm_dev, ctx->display);
1049 static void fimd_unbind(struct device *dev, struct device *master,
1052 struct exynos_drm_manager *mgr = dev_get_drvdata(dev);
1053 struct fimd_context *ctx = fimd_manager.ctx;
1054 struct drm_crtc *crtc = mgr->crtc;
1056 fimd_dpms(mgr, DRM_MODE_DPMS_OFF);
1059 exynos_dpi_remove(dev);
1061 fimd_mgr_remove(mgr);
1063 crtc->funcs->destroy(crtc);
1066 static const struct component_ops fimd_component_ops = {
1068 .unbind = fimd_unbind,
1071 static int fimd_probe(struct platform_device *pdev)
1073 struct device *dev = &pdev->dev;
1074 struct fimd_context *ctx;
1075 struct device_node *i80_if_timings;
1076 struct resource *res;
1079 ret = exynos_drm_component_add(&pdev->dev, EXYNOS_DEVICE_TYPE_CRTC,
1084 if (!dev->of_node) {
1086 goto err_del_component;
1089 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
1092 goto err_del_component;
1096 ctx->suspended = true;
1097 ctx->driver_data = drm_fimd_get_driver_data(pdev);
1099 if (of_property_read_bool(dev->of_node, "samsung,invert-vden"))
1100 ctx->vidcon1 |= VIDCON1_INV_VDEN;
1101 if (of_property_read_bool(dev->of_node, "samsung,invert-vclk"))
1102 ctx->vidcon1 |= VIDCON1_INV_VCLK;
1104 i80_if_timings = of_get_child_by_name(dev->of_node, "i80-if-timings");
1105 if (i80_if_timings) {
1110 if (ctx->driver_data->has_vidoutcon)
1111 ctx->vidout_con |= VIDOUT_CON_F_I80_LDI0;
1113 ctx->vidcon0 |= VIDCON0_VIDOUT_I80_LDI0;
1115 * The user manual describes that this "DSI_EN" bit is required
1116 * to enable I80 24-bit data interface.
1118 ctx->vidcon0 |= VIDCON0_DSI_EN;
1120 if (of_property_read_u32(i80_if_timings, "cs-setup", &val))
1122 ctx->i80ifcon = LCD_CS_SETUP(val);
1123 if (of_property_read_u32(i80_if_timings, "wr-setup", &val))
1125 ctx->i80ifcon |= LCD_WR_SETUP(val);
1126 if (of_property_read_u32(i80_if_timings, "wr-active", &val))
1128 ctx->i80ifcon |= LCD_WR_ACTIVE(val);
1129 if (of_property_read_u32(i80_if_timings, "wr-hold", &val))
1131 ctx->i80ifcon |= LCD_WR_HOLD(val);
1133 of_node_put(i80_if_timings);
1135 ctx->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
1137 if (IS_ERR(ctx->sysreg)) {
1138 dev_warn(dev, "failed to get system register.\n");
1142 ctx->bus_clk = devm_clk_get(dev, "fimd");
1143 if (IS_ERR(ctx->bus_clk)) {
1144 dev_err(dev, "failed to get bus clock\n");
1145 ret = PTR_ERR(ctx->bus_clk);
1146 goto err_del_component;
1149 ctx->lcd_clk = devm_clk_get(dev, "sclk_fimd");
1150 if (IS_ERR(ctx->lcd_clk)) {
1151 dev_err(dev, "failed to get lcd clock\n");
1152 ret = PTR_ERR(ctx->lcd_clk);
1153 goto err_del_component;
1156 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1158 ctx->regs = devm_ioremap_resource(dev, res);
1159 if (IS_ERR(ctx->regs)) {
1160 ret = PTR_ERR(ctx->regs);
1161 goto err_del_component;
1164 res = platform_get_resource_byname(pdev, IORESOURCE_IRQ,
1165 ctx->i80_if ? "lcd_sys" : "vsync");
1167 dev_err(dev, "irq request failed.\n");
1169 goto err_del_component;
1172 ret = devm_request_irq(dev, res->start, fimd_irq_handler,
1173 0, "drm_fimd", ctx);
1175 dev_err(dev, "irq request failed.\n");
1176 goto err_del_component;
1179 init_waitqueue_head(&ctx->wait_vsync_queue);
1180 atomic_set(&ctx->wait_vsync_event, 0);
1182 platform_set_drvdata(pdev, &fimd_manager);
1184 fimd_manager.ctx = ctx;
1186 ctx->display = exynos_dpi_probe(dev);
1187 if (IS_ERR(ctx->display))
1188 return PTR_ERR(ctx->display);
1190 pm_runtime_enable(&pdev->dev);
1192 ret = component_add(&pdev->dev, &fimd_component_ops);
1194 goto err_disable_pm_runtime;
1198 err_disable_pm_runtime:
1199 pm_runtime_disable(&pdev->dev);
1202 exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CRTC);
1206 static int fimd_remove(struct platform_device *pdev)
1208 pm_runtime_disable(&pdev->dev);
1210 component_del(&pdev->dev, &fimd_component_ops);
1211 exynos_drm_component_del(&pdev->dev, EXYNOS_DEVICE_TYPE_CRTC);
1216 struct platform_driver fimd_driver = {
1217 .probe = fimd_probe,
1218 .remove = fimd_remove,
1220 .name = "exynos4-fb",
1221 .owner = THIS_MODULE,
1222 .of_match_table = fimd_driver_dt_match,