drivers/gpu/drm/exynos/exynos_hdmi.c

   1 /*
   2  * Copyright (C) 2011 Samsung Electronics Co.Ltd
   3  * Authors:
   4  * Seung-Woo Kim <sw0312.kim@samsung.com>
   5  *      Inki Dae <inki.dae@samsung.com>
   6  *      Joonyoung Shim <jy0922.shim@samsung.com>
   7  *
   8  * Based on drivers/media/video/s5p-tv/hdmi_drv.c
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License as published by the
  12  * Free Software Foundation; either version 2 of the License, or (at your
  13  * option) any later version.
  14  *
  15  */
  16
  17 #include <drm/drmP.h>
  18 #include <drm/drm_edid.h>
  19 #include <drm/drm_crtc_helper.h>
  20 #include <drm/drm_atomic_helper.h>
  21
  22 #include "regs-hdmi.h"
  23
  24 #include <linux/kernel.h>
  25 #include <linux/wait.h>
  26 #include <linux/i2c.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/irq.h>
  30 #include <linux/delay.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/clk.h>
  33 #include <linux/gpio/consumer.h>
  34 #include <linux/regulator/consumer.h>
  35 #include <linux/io.h>
  36 #include <linux/of_address.h>
  37 #include <linux/of_device.h>
  38 #include <linux/hdmi.h>
  39 #include <linux/component.h>
  40 #include <linux/mfd/syscon.h>
  41 #include <linux/regmap.h>
  42
  43 #include <drm/exynos_drm.h>
  44
  45 #include "exynos_drm_drv.h"
  46 #include "exynos_drm_crtc.h"
  47
  48 #define HOTPLUG_DEBOUNCE_MS             1100
  49
  50 /* AVI header and aspect ratio */
  51 #define HDMI_AVI_VERSION                0x02
  52 #define HDMI_AVI_LENGTH                 0x0d
  53
  54 /* AUI header info */
  55 #define HDMI_AUI_VERSION                0x01
  56 #define HDMI_AUI_LENGTH                 0x0a
  57
  58 /* AVI active format aspect ratio */
  59 #define AVI_SAME_AS_PIC_ASPECT_RATIO    0x08
  60 #define AVI_4_3_CENTER_RATIO            0x09
  61 #define AVI_16_9_CENTER_RATIO           0x0a
  62
  63 enum hdmi_type {
  64         HDMI_TYPE13,
  65         HDMI_TYPE14,
  66         HDMI_TYPE_COUNT
  67 };
  68
  69 #define HDMI_MAPPED_BASE 0xffff0000
  70
  71 enum hdmi_mapped_regs {
  72         HDMI_PHY_STATUS = HDMI_MAPPED_BASE,
  73         HDMI_PHY_RSTOUT,
  74         HDMI_ACR_CON,
  75         HDMI_ACR_MCTS0,
  76         HDMI_ACR_CTS0,
  77         HDMI_ACR_N0
  78 };
  79
  80 static const u32 hdmi_reg_map[][HDMI_TYPE_COUNT] = {
  81         { HDMI_V13_PHY_STATUS, HDMI_PHY_STATUS_0 },
  82         { HDMI_V13_PHY_RSTOUT, HDMI_V14_PHY_RSTOUT },
  83         { HDMI_V13_ACR_CON, HDMI_V14_ACR_CON },
  84         { HDMI_V13_ACR_MCTS0, HDMI_V14_ACR_MCTS0 },
  85         { HDMI_V13_ACR_CTS0, HDMI_V14_ACR_CTS0 },
  86         { HDMI_V13_ACR_N0, HDMI_V14_ACR_N0 },
  87 };
  88
  89 static const char * const supply[] = {
  90         "vdd",
  91         "vdd_osc",
  92         "vdd_pll",
  93 };
  94
  95 struct hdmiphy_config {
  96         int pixel_clock;
  97         u8 conf[32];
  98 };
  99
 100 struct hdmiphy_configs {
 101         int count;
 102         const struct hdmiphy_config *data;
 103 };
 104
 105 struct string_array_spec {
 106         int count;
 107         const char * const *data;
 108 };
 109
 110 #define INIT_ARRAY_SPEC(a) { .count = ARRAY_SIZE(a), .data = a }
 111
 112 struct hdmi_driver_data {
 113         unsigned int type;
 114         unsigned int is_apb_phy:1;
 115         unsigned int has_sysreg:1;
 116         struct hdmiphy_configs phy_confs;
 117         struct string_array_spec clk_gates;
 118         /*
 119          * Array of triplets (p_off, p_on, clock), where p_off and p_on are
 120          * required parents of clock when HDMI-PHY is respectively off or on.
 121          */
 122         struct string_array_spec clk_muxes;
 123 };
 124
 125 struct hdmi_context {
 126         struct drm_encoder              encoder;
 127         struct device                   *dev;
 128         struct drm_device               *drm_dev;
 129         struct drm_connector            connector;
 130         bool                            powered;
 131         bool                            dvi_mode;
 132         struct delayed_work             hotplug_work;
 133         struct drm_display_mode         current_mode;
 134         u8                              cea_video_id;
 135         const struct hdmi_driver_data   *drv_data;
 136
 137         void __iomem                    *regs;
 138         void __iomem                    *regs_hdmiphy;
 139         struct i2c_client               *hdmiphy_port;
 140         struct i2c_adapter              *ddc_adpt;
 141         struct gpio_desc                *hpd_gpio;
 142         int                             irq;
 143         struct regmap                   *pmureg;
 144         struct regmap                   *sysreg;
 145         struct clk                      **clk_gates;
 146         struct clk                      **clk_muxes;
 147         struct regulator_bulk_data      regul_bulk[ARRAY_SIZE(supply)];
 148         struct regulator                *reg_hdmi_en;
 149 };
 150
 151 static inline struct hdmi_context *encoder_to_hdmi(struct drm_encoder *e)
 152 {
 153         return container_of(e, struct hdmi_context, encoder);
 154 }
 155
 156 static inline struct hdmi_context *connector_to_hdmi(struct drm_connector *c)
 157 {
 158         return container_of(c, struct hdmi_context, connector);
 159 }
 160
 161 static const struct hdmiphy_config hdmiphy_v13_configs[] = {
 162         {
 163                 .pixel_clock = 27000000,
 164                 .conf = {
 165                         0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40,
 166                         0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
 167                         0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
 168                         0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x80,
 169                 },
 170         },
 171         {
 172                 .pixel_clock = 27027000,
 173                 .conf = {
 174                         0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C, 0x09, 0x64,
 175                         0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
 176                         0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
 177                         0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x80,
 178                 },
 179         },
 180         {
 181                 .pixel_clock = 74176000,
 182                 .conf = {
 183                         0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xef, 0x5B,
 184                         0x6D, 0x10, 0x01, 0x51, 0xef, 0xF3, 0x54, 0xb9,
 185                         0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
 186                         0x22, 0x40, 0xa5, 0x26, 0x01, 0x00, 0x00, 0x80,
 187                 },
 188         },
 189         {
 190                 .pixel_clock = 74250000,
 191                 .conf = {
 192                         0x01, 0x05, 0x00, 0xd8, 0x10, 0x9c, 0xf8, 0x40,
 193                         0x6a, 0x10, 0x01, 0x51, 0xff, 0xf1, 0x54, 0xba,
 194                         0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xe0,
 195                         0x22, 0x40, 0xa4, 0x26, 0x01, 0x00, 0x00, 0x80,
 196                 },
 197         },
 198         {
 199                 .pixel_clock = 148500000,
 200                 .conf = {
 201                         0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xf8, 0x40,
 202                         0x6A, 0x18, 0x00, 0x51, 0xff, 0xF1, 0x54, 0xba,
 203                         0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xE0,
 204                         0x22, 0x40, 0xa4, 0x26, 0x02, 0x00, 0x00, 0x80,
 205                 },
 206         },
 207 };
 208
 209 static const struct hdmiphy_config hdmiphy_v14_configs[] = {
 210         {
 211                 .pixel_clock = 25200000,
 212                 .conf = {
 213                         0x01, 0x51, 0x2A, 0x75, 0x40, 0x01, 0x00, 0x08,
 214                         0x82, 0x80, 0xfc, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 215                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 216                         0x54, 0xf4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 217                 },
 218         },
 219         {
 220                 .pixel_clock = 27000000,
 221                 .conf = {
 222                         0x01, 0xd1, 0x22, 0x51, 0x40, 0x08, 0xfc, 0x20,
 223                         0x98, 0xa0, 0xcb, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 224                         0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 225                         0x54, 0xe4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 226                 },
 227         },
 228         {
 229                 .pixel_clock = 27027000,
 230                 .conf = {
 231                         0x01, 0xd1, 0x2d, 0x72, 0x40, 0x64, 0x12, 0x08,
 232                         0x43, 0xa0, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 233                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 234                         0x54, 0xe3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 235                 },
 236         },
 237         {
 238                 .pixel_clock = 36000000,
 239                 .conf = {
 240                         0x01, 0x51, 0x2d, 0x55, 0x40, 0x01, 0x00, 0x08,
 241                         0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 242                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 243                         0x54, 0xab, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 244                 },
 245         },
 246         {
 247                 .pixel_clock = 40000000,
 248                 .conf = {
 249                         0x01, 0x51, 0x32, 0x55, 0x40, 0x01, 0x00, 0x08,
 250                         0x82, 0x80, 0x2c, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 251                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 252                         0x54, 0x9a, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 253                 },
 254         },
 255         {
 256                 .pixel_clock = 65000000,
 257                 .conf = {
 258                         0x01, 0xd1, 0x36, 0x34, 0x40, 0x1e, 0x0a, 0x08,
 259                         0x82, 0xa0, 0x45, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 260                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 261                         0x54, 0xbd, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 262                 },
 263         },
 264         {
 265                 .pixel_clock = 71000000,
 266                 .conf = {
 267                         0x01, 0xd1, 0x3b, 0x35, 0x40, 0x0c, 0x04, 0x08,
 268                         0x85, 0xa0, 0x63, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 269                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 270                         0x54, 0xad, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 271                 },
 272         },
 273         {
 274                 .pixel_clock = 73250000,
 275                 .conf = {
 276                         0x01, 0xd1, 0x3d, 0x35, 0x40, 0x18, 0x02, 0x08,
 277                         0x83, 0xa0, 0x6e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 278                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 279                         0x54, 0xa8, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 280                 },
 281         },
 282         {
 283                 .pixel_clock = 74176000,
 284                 .conf = {
 285                         0x01, 0xd1, 0x3e, 0x35, 0x40, 0x5b, 0xde, 0x08,
 286                         0x82, 0xa0, 0x73, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 287                         0x56, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 288                         0x54, 0xa6, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 289                 },
 290         },
 291         {
 292                 .pixel_clock = 74250000,
 293                 .conf = {
 294                         0x01, 0xd1, 0x1f, 0x10, 0x40, 0x40, 0xf8, 0x08,
 295                         0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 296                         0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 297                         0x54, 0xa5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 298                 },
 299         },
 300         {
 301                 .pixel_clock = 83500000,
 302                 .conf = {
 303                         0x01, 0xd1, 0x23, 0x11, 0x40, 0x0c, 0xfb, 0x08,
 304                         0x85, 0xa0, 0xd1, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 305                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 306                         0x54, 0x93, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 307                 },
 308         },
 309         {
 310                 .pixel_clock = 106500000,
 311                 .conf = {
 312                         0x01, 0xd1, 0x2c, 0x12, 0x40, 0x0c, 0x09, 0x08,
 313                         0x84, 0xa0, 0x0a, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 314                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 315                         0x54, 0x73, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 316                 },
 317         },
 318         {
 319                 .pixel_clock = 108000000,
 320                 .conf = {
 321                         0x01, 0x51, 0x2d, 0x15, 0x40, 0x01, 0x00, 0x08,
 322                         0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 323                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 324                         0x54, 0xc7, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
 325                 },
 326         },
 327         {
 328                 .pixel_clock = 115500000,
 329                 .conf = {
 330                         0x01, 0xd1, 0x30, 0x12, 0x40, 0x40, 0x10, 0x08,
 331                         0x80, 0x80, 0x21, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 332                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 333                         0x54, 0xaa, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
 334                 },
 335         },
 336         {
 337                 .pixel_clock = 119000000,
 338                 .conf = {
 339                         0x01, 0xd1, 0x32, 0x1a, 0x40, 0x30, 0xd8, 0x08,
 340                         0x04, 0xa0, 0x2a, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 341                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 342                         0x54, 0x9d, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
 343                 },
 344         },
 345         {
 346                 .pixel_clock = 146250000,
 347                 .conf = {
 348                         0x01, 0xd1, 0x3d, 0x15, 0x40, 0x18, 0xfd, 0x08,
 349                         0x83, 0xa0, 0x6e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
 350                         0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 351                         0x54, 0x50, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
 352                 },
 353         },
 354         {
 355                 .pixel_clock = 148500000,
 356                 .conf = {
 357                         0x01, 0xd1, 0x1f, 0x00, 0x40, 0x40, 0xf8, 0x08,
 358                         0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,
 359                         0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
 360                         0x54, 0x4b, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
 361                 },
 362         },
 363 };
 364
 365 static const struct hdmiphy_config hdmiphy_5420_configs[] = {
 366         {
 367                 .pixel_clock = 25200000,
 368                 .conf = {
 369                         0x01, 0x52, 0x3F, 0x55, 0x40, 0x01, 0x00, 0xC8,
 370                         0x82, 0xC8, 0xBD, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
 371                         0x06, 0x80, 0x01, 0x84, 0x05, 0x02, 0x24, 0x66,
 372                         0x54, 0xF4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 373                 },
 374         },
 375         {
 376                 .pixel_clock = 27000000,
 377                 .conf = {
 378                         0x01, 0xD1, 0x22, 0x51, 0x40, 0x08, 0xFC, 0xE0,
 379                         0x98, 0xE8, 0xCB, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
 380                         0x06, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
 381                         0x54, 0xE4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 382                 },
 383         },
 384         {
 385                 .pixel_clock = 27027000,
 386                 .conf = {
 387                         0x01, 0xD1, 0x2D, 0x72, 0x40, 0x64, 0x12, 0xC8,
 388                         0x43, 0xE8, 0x0E, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
 389                         0x26, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
 390                         0x54, 0xE3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 391                 },
 392         },
 393         {
 394                 .pixel_clock = 36000000,
 395                 .conf = {
 396                         0x01, 0x51, 0x2D, 0x55, 0x40, 0x40, 0x00, 0xC8,
 397                         0x02, 0xC8, 0x0E, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
 398                         0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
 399                         0x54, 0xAB, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 400                 },
 401         },
 402         {
 403                 .pixel_clock = 40000000,
 404                 .conf = {
 405                         0x01, 0xD1, 0x21, 0x31, 0x40, 0x3C, 0x28, 0xC8,
 406                         0x87, 0xE8, 0xC8, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
 407                         0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
 408                         0x54, 0x9A, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 409                 },
 410         },
 411         {
 412                 .pixel_clock = 65000000,
 413                 .conf = {
 414                         0x01, 0xD1, 0x36, 0x34, 0x40, 0x0C, 0x04, 0xC8,
 415                         0x82, 0xE8, 0x45, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
 416                         0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
 417                         0x54, 0xBD, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 418                 },
 419         },
 420         {
 421                 .pixel_clock = 71000000,
 422                 .conf = {
 423                         0x01, 0xD1, 0x3B, 0x35, 0x40, 0x0C, 0x04, 0xC8,
 424                         0x85, 0xE8, 0x63, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
 425                         0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
 426                         0x54, 0x57, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 427                 },
 428         },
 429         {
 430                 .pixel_clock = 73250000,
 431                 .conf = {
 432                         0x01, 0xD1, 0x1F, 0x10, 0x40, 0x78, 0x8D, 0xC8,
 433                         0x81, 0xE8, 0xB7, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
 434                         0x56, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
 435                         0x54, 0xA8, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 436                 },
 437         },
 438         {
 439                 .pixel_clock = 74176000,
 440                 .conf = {
 441                         0x01, 0xD1, 0x1F, 0x10, 0x40, 0x5B, 0xEF, 0xC8,
 442                         0x81, 0xE8, 0xB9, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
 443                         0x56, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
 444                         0x54, 0xA6, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 445                 },
 446         },
 447         {
 448                 .pixel_clock = 74250000,
 449                 .conf = {
 450                         0x01, 0xD1, 0x1F, 0x10, 0x40, 0x40, 0xF8, 0x08,
 451                         0x81, 0xE8, 0xBA, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
 452                         0x26, 0x80, 0x09, 0x84, 0x05, 0x22, 0x24, 0x66,
 453                         0x54, 0xA5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 454                 },
 455         },
 456         {
 457                 .pixel_clock = 83500000,
 458                 .conf = {
 459                         0x01, 0xD1, 0x23, 0x11, 0x40, 0x0C, 0xFB, 0xC8,
 460                         0x85, 0xE8, 0xD1, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
 461                         0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
 462                         0x54, 0x4A, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 463                 },
 464         },
 465         {
 466                 .pixel_clock = 88750000,
 467                 .conf = {
 468                         0x01, 0xD1, 0x25, 0x11, 0x40, 0x18, 0xFF, 0xC8,
 469                         0x83, 0xE8, 0xDE, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
 470                         0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
 471                         0x54, 0x45, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
 472                 },
 473         },
 474         {
 475                 .pixel_clock = 106500000,
 476                 .conf = {
 477                         0x01, 0xD1, 0x2C, 0x12, 0x40, 0x0C, 0x09, 0xC8,
 478                         0x84, 0xE8, 0x0A, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
 479                         0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
 480                         0x54, 0x73, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 481                 },
 482         },
 483         {
 484                 .pixel_clock = 108000000,
 485                 .conf = {
 486                         0x01, 0x51, 0x2D, 0x15, 0x40, 0x01, 0x00, 0xC8,
 487                         0x82, 0xC8, 0x0E, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
 488                         0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
 489                         0x54, 0xC7, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
 490                 },
 491         },
 492         {
 493                 .pixel_clock = 115500000,
 494                 .conf = {
 495                         0x01, 0xD1, 0x30, 0x14, 0x40, 0x0C, 0x03, 0xC8,
 496                         0x88, 0xE8, 0x21, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
 497                         0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
 498                         0x54, 0x6A, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 499                 },
 500         },
 501         {
 502                 .pixel_clock = 146250000,
 503                 .conf = {
 504                         0x01, 0xD1, 0x3D, 0x15, 0x40, 0x18, 0xFD, 0xC8,
 505                         0x83, 0xE8, 0x6E, 0xD9, 0x45, 0xA0, 0xAC, 0x80,
 506                         0x08, 0x80, 0x09, 0x84, 0x05, 0x02, 0x24, 0x66,
 507                         0x54, 0x54, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
 508                 },
 509         },
 510         {
 511                 .pixel_clock = 148500000,
 512                 .conf = {
 513                         0x01, 0xD1, 0x1F, 0x00, 0x40, 0x40, 0xF8, 0x08,
 514                         0x81, 0xE8, 0xBA, 0xD8, 0x45, 0xA0, 0xAC, 0x80,
 515                         0x26, 0x80, 0x09, 0x84, 0x05, 0x22, 0x24, 0x66,
 516                         0x54, 0x4B, 0x25, 0x03, 0x00, 0x80, 0x01, 0x80,
 517                 },
 518         },
 519 };
 520
 521 static const struct hdmiphy_config hdmiphy_5433_configs[] = {
 522         {
 523                 .pixel_clock = 27000000,
 524                 .conf = {
 525                         0x01, 0x51, 0x22, 0x51, 0x08, 0xfc, 0x88, 0x46,
 526                         0x72, 0x50, 0x24, 0x0c, 0x24, 0x0f, 0x7c, 0xa5,
 527                         0xd4, 0x2b, 0x87, 0x00, 0x00, 0x04, 0x00, 0x30,
 528                         0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
 529                 },
 530         },
 531         {
 532                 .pixel_clock = 27027000,
 533                 .conf = {
 534                         0x01, 0x51, 0x2d, 0x72, 0x64, 0x09, 0x88, 0xc3,
 535                         0x71, 0x50, 0x24, 0x14, 0x24, 0x0f, 0x7c, 0xa5,
 536                         0xd4, 0x2b, 0x87, 0x00, 0x00, 0x04, 0x00, 0x30,
 537                         0x28, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
 538                 },
 539         },
 540         {
 541                 .pixel_clock = 40000000,
 542                 .conf = {
 543                         0x01, 0x51, 0x32, 0x55, 0x01, 0x00, 0x88, 0x02,
 544                         0x4d, 0x50, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC,
 545                         0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
 546                         0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
 547                 },
 548         },
 549         {
 550                 .pixel_clock = 50000000,
 551                 .conf = {
 552                         0x01, 0x51, 0x34, 0x40, 0x64, 0x09, 0x88, 0xc3,
 553                         0x3d, 0x50, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC,
 554                         0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
 555                         0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
 556                 },
 557         },
 558         {
 559                 .pixel_clock = 65000000,
 560                 .conf = {
 561                         0x01, 0x51, 0x36, 0x31, 0x40, 0x10, 0x04, 0xc6,
 562                         0x2e, 0xe8, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC,
 563                         0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
 564                         0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
 565                 },
 566         },
 567         {
 568                 .pixel_clock = 74176000,
 569                 .conf = {
 570                         0x01, 0x51, 0x3E, 0x35, 0x5B, 0xDE, 0x88, 0x42,
 571                         0x53, 0x51, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC,
 572                         0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
 573                         0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
 574                 },
 575         },
 576         {
 577                 .pixel_clock = 74250000,
 578                 .conf = {
 579                         0x01, 0x51, 0x3E, 0x35, 0x40, 0xF0, 0x88, 0xC2,
 580                         0x52, 0x51, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC,
 581                         0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
 582                         0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
 583                 },
 584         },
 585         {
 586                 .pixel_clock = 108000000,
 587                 .conf = {
 588                         0x01, 0x51, 0x2d, 0x15, 0x01, 0x00, 0x88, 0x02,
 589                         0x72, 0x52, 0x44, 0x8C, 0x27, 0x00, 0x7C, 0xAC,
 590                         0xD6, 0x2B, 0x67, 0x00, 0x00, 0x04, 0x00, 0x30,
 591                         0x08, 0x10, 0x01, 0x01, 0x48, 0x40, 0x00, 0x40,
 592                 },
 593         },
 594         {
 595                 .pixel_clock = 148500000,
 596                 .conf = {
 597                         0x01, 0x51, 0x1f, 0x00, 0x40, 0xf8, 0x88, 0xc1,
 598                         0x52, 0x52, 0x24, 0x0c, 0x24, 0x0f, 0x7c, 0xa5,
 599                         0xd4, 0x2b, 0x87, 0x00, 0x00, 0x04, 0x00, 0x30,
 600                         0x08, 0x10, 0x01, 0x01, 0x48, 0x4a, 0x00, 0x40,
 601                 },
 602         },
 603 };
 604
 605 static const char * const hdmi_clk_gates4[] = {
 606         "hdmi", "sclk_hdmi"
 607 };
 608
 609 static const char * const hdmi_clk_muxes4[] = {
 610         "sclk_pixel", "sclk_hdmiphy", "mout_hdmi"
 611 };
 612
 613 static const char * const hdmi_clk_gates5433[] = {
 614         "hdmi_pclk", "hdmi_i_pclk", "i_tmds_clk", "i_pixel_clk", "i_spdif_clk"
 615 };
 616
 617 static const char * const hdmi_clk_muxes5433[] = {
 618         "oscclk", "tmds_clko", "tmds_clko_user",
 619         "oscclk", "pixel_clko", "pixel_clko_user"
 620 };
 621
 622 static const struct hdmi_driver_data exynos4210_hdmi_driver_data = {
 623         .type           = HDMI_TYPE13,
 624         .phy_confs      = INIT_ARRAY_SPEC(hdmiphy_v13_configs),
 625         .clk_gates      = INIT_ARRAY_SPEC(hdmi_clk_gates4),
 626         .clk_muxes      = INIT_ARRAY_SPEC(hdmi_clk_muxes4),
 627 };
 628
 629 static const struct hdmi_driver_data exynos4212_hdmi_driver_data = {
 630         .type           = HDMI_TYPE14,
 631         .phy_confs      = INIT_ARRAY_SPEC(hdmiphy_v14_configs),
 632         .clk_gates      = INIT_ARRAY_SPEC(hdmi_clk_gates4),
 633         .clk_muxes      = INIT_ARRAY_SPEC(hdmi_clk_muxes4),
 634 };
 635
 636 static const struct hdmi_driver_data exynos5420_hdmi_driver_data = {
 637         .type           = HDMI_TYPE14,
 638         .is_apb_phy     = 1,
 639         .phy_confs      = INIT_ARRAY_SPEC(hdmiphy_5420_configs),
 640         .clk_gates      = INIT_ARRAY_SPEC(hdmi_clk_gates4),
 641         .clk_muxes      = INIT_ARRAY_SPEC(hdmi_clk_muxes4),
 642 };
 643
 644 static const struct hdmi_driver_data exynos5433_hdmi_driver_data = {
 645         .type           = HDMI_TYPE14,
 646         .is_apb_phy     = 1,
 647         .has_sysreg     = 1,
 648         .phy_confs      = INIT_ARRAY_SPEC(hdmiphy_5433_configs),
 649         .clk_gates      = INIT_ARRAY_SPEC(hdmi_clk_gates5433),
 650         .clk_muxes      = INIT_ARRAY_SPEC(hdmi_clk_muxes5433),
 651 };
 652
 653 static inline u32 hdmi_map_reg(struct hdmi_context *hdata, u32 reg_id)
 654 {
 655         if ((reg_id & 0xffff0000) == HDMI_MAPPED_BASE)
 656                 return hdmi_reg_map[reg_id & 0xffff][hdata->drv_data->type];
 657         return reg_id;
 658 }
 659
 660 static inline u32 hdmi_reg_read(struct hdmi_context *hdata, u32 reg_id)
 661 {
 662         return readl(hdata->regs + hdmi_map_reg(hdata, reg_id));
 663 }
 664
 665 static inline void hdmi_reg_writeb(struct hdmi_context *hdata,
 666                                  u32 reg_id, u8 value)
 667 {
 668         writel(value, hdata->regs + hdmi_map_reg(hdata, reg_id));
 669 }
 670
 671 static inline void hdmi_reg_writev(struct hdmi_context *hdata, u32 reg_id,
 672                                    int bytes, u32 val)
 673 {
 674         reg_id = hdmi_map_reg(hdata, reg_id);
 675
 676         while (--bytes >= 0) {
 677                 writel(val & 0xff, hdata->regs + reg_id);
 678                 val >>= 8;
 679                 reg_id += 4;
 680         }
 681 }
 682
 683 static inline void hdmi_reg_writemask(struct hdmi_context *hdata,
 684                                  u32 reg_id, u32 value, u32 mask)
 685 {
 686         u32 old;
 687
 688         reg_id = hdmi_map_reg(hdata, reg_id);
 689         old = readl(hdata->regs + reg_id);
 690         value = (value & mask) | (old & ~mask);
 691         writel(value, hdata->regs + reg_id);
 692 }
 693
 694 static int hdmiphy_reg_write_buf(struct hdmi_context *hdata,
 695                         u32 reg_offset, const u8 *buf, u32 len)
 696 {
 697         if ((reg_offset + len) > 32)
 698                 return -EINVAL;
 699
 700         if (hdata->hdmiphy_port) {
 701                 int ret;
 702
 703                 ret = i2c_master_send(hdata->hdmiphy_port, buf, len);
 704                 if (ret == len)
 705                         return 0;
 706                 return ret;
 707         } else {
 708                 int i;
 709                 for (i = 0; i < len; i++)
 710                         writel(buf[i], hdata->regs_hdmiphy +
 711                                 ((reg_offset + i)<<2));
 712                 return 0;
 713         }
 714 }
 715
 716 static void hdmi_v13_regs_dump(struct hdmi_context *hdata, char *prefix)
 717 {
 718 #define DUMPREG(reg_id) \
 719         DRM_DEBUG_KMS("%s:" #reg_id " = %08x\n", prefix, \
 720         readl(hdata->regs + reg_id))
 721         DRM_DEBUG_KMS("%s: ---- CONTROL REGISTERS ----\n", prefix);
 722         DUMPREG(HDMI_INTC_FLAG);
 723         DUMPREG(HDMI_INTC_CON);
 724         DUMPREG(HDMI_HPD_STATUS);
 725         DUMPREG(HDMI_V13_PHY_RSTOUT);
 726         DUMPREG(HDMI_V13_PHY_VPLL);
 727         DUMPREG(HDMI_V13_PHY_CMU);
 728         DUMPREG(HDMI_V13_CORE_RSTOUT);
 729
 730         DRM_DEBUG_KMS("%s: ---- CORE REGISTERS ----\n", prefix);
 731         DUMPREG(HDMI_CON_0);
 732         DUMPREG(HDMI_CON_1);
 733         DUMPREG(HDMI_CON_2);
 734         DUMPREG(HDMI_SYS_STATUS);
 735         DUMPREG(HDMI_V13_PHY_STATUS);
 736         DUMPREG(HDMI_STATUS_EN);
 737         DUMPREG(HDMI_HPD);
 738         DUMPREG(HDMI_MODE_SEL);
 739         DUMPREG(HDMI_V13_HPD_GEN);
 740         DUMPREG(HDMI_V13_DC_CONTROL);
 741         DUMPREG(HDMI_V13_VIDEO_PATTERN_GEN);
 742
 743         DRM_DEBUG_KMS("%s: ---- CORE SYNC REGISTERS ----\n", prefix);
 744         DUMPREG(HDMI_H_BLANK_0);
 745         DUMPREG(HDMI_H_BLANK_1);
 746         DUMPREG(HDMI_V13_V_BLANK_0);
 747         DUMPREG(HDMI_V13_V_BLANK_1);
 748         DUMPREG(HDMI_V13_V_BLANK_2);
 749         DUMPREG(HDMI_V13_H_V_LINE_0);
 750         DUMPREG(HDMI_V13_H_V_LINE_1);
 751         DUMPREG(HDMI_V13_H_V_LINE_2);
 752         DUMPREG(HDMI_VSYNC_POL);
 753         DUMPREG(HDMI_INT_PRO_MODE);
 754         DUMPREG(HDMI_V13_V_BLANK_F_0);
 755         DUMPREG(HDMI_V13_V_BLANK_F_1);
 756         DUMPREG(HDMI_V13_V_BLANK_F_2);
 757         DUMPREG(HDMI_V13_H_SYNC_GEN_0);
 758         DUMPREG(HDMI_V13_H_SYNC_GEN_1);
 759         DUMPREG(HDMI_V13_H_SYNC_GEN_2);
 760         DUMPREG(HDMI_V13_V_SYNC_GEN_1_0);
 761         DUMPREG(HDMI_V13_V_SYNC_GEN_1_1);
 762         DUMPREG(HDMI_V13_V_SYNC_GEN_1_2);
 763         DUMPREG(HDMI_V13_V_SYNC_GEN_2_0);
 764         DUMPREG(HDMI_V13_V_SYNC_GEN_2_1);
 765         DUMPREG(HDMI_V13_V_SYNC_GEN_2_2);
 766         DUMPREG(HDMI_V13_V_SYNC_GEN_3_0);
 767         DUMPREG(HDMI_V13_V_SYNC_GEN_3_1);
 768         DUMPREG(HDMI_V13_V_SYNC_GEN_3_2);
 769
 770         DRM_DEBUG_KMS("%s: ---- TG REGISTERS ----\n", prefix);
 771         DUMPREG(HDMI_TG_CMD);
 772         DUMPREG(HDMI_TG_H_FSZ_L);
 773         DUMPREG(HDMI_TG_H_FSZ_H);
 774         DUMPREG(HDMI_TG_HACT_ST_L);
 775         DUMPREG(HDMI_TG_HACT_ST_H);
 776         DUMPREG(HDMI_TG_HACT_SZ_L);
 777         DUMPREG(HDMI_TG_HACT_SZ_H);
 778         DUMPREG(HDMI_TG_V_FSZ_L);
 779         DUMPREG(HDMI_TG_V_FSZ_H);
 780         DUMPREG(HDMI_TG_VSYNC_L);
 781         DUMPREG(HDMI_TG_VSYNC_H);
 782         DUMPREG(HDMI_TG_VSYNC2_L);
 783         DUMPREG(HDMI_TG_VSYNC2_H);
 784         DUMPREG(HDMI_TG_VACT_ST_L);
 785         DUMPREG(HDMI_TG_VACT_ST_H);
 786         DUMPREG(HDMI_TG_VACT_SZ_L);
 787         DUMPREG(HDMI_TG_VACT_SZ_H);
 788         DUMPREG(HDMI_TG_FIELD_CHG_L);
 789         DUMPREG(HDMI_TG_FIELD_CHG_H);
 790         DUMPREG(HDMI_TG_VACT_ST2_L);
 791         DUMPREG(HDMI_TG_VACT_ST2_H);
 792         DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_L);
 793         DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_H);
 794         DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_L);
 795         DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_H);
 796         DUMPREG(HDMI_TG_FIELD_TOP_HDMI_L);
 797         DUMPREG(HDMI_TG_FIELD_TOP_HDMI_H);
 798         DUMPREG(HDMI_TG_FIELD_BOT_HDMI_L);
 799         DUMPREG(HDMI_TG_FIELD_BOT_HDMI_H);
 800 #undef DUMPREG
 801 }
 802
 803 static void hdmi_v14_regs_dump(struct hdmi_context *hdata, char *prefix)
 804 {
 805         int i;
 806
 807 #define DUMPREG(reg_id) \
 808         DRM_DEBUG_KMS("%s:" #reg_id " = %08x\n", prefix, \
 809         readl(hdata->regs + reg_id))
 810
 811         DRM_DEBUG_KMS("%s: ---- CONTROL REGISTERS ----\n", prefix);
 812         DUMPREG(HDMI_INTC_CON);
 813         DUMPREG(HDMI_INTC_FLAG);
 814         DUMPREG(HDMI_HPD_STATUS);
 815         DUMPREG(HDMI_INTC_CON_1);
 816         DUMPREG(HDMI_INTC_FLAG_1);
 817         DUMPREG(HDMI_PHY_STATUS_0);
 818         DUMPREG(HDMI_PHY_STATUS_PLL);
 819         DUMPREG(HDMI_PHY_CON_0);
 820         DUMPREG(HDMI_V14_PHY_RSTOUT);
 821         DUMPREG(HDMI_PHY_VPLL);
 822         DUMPREG(HDMI_PHY_CMU);
 823         DUMPREG(HDMI_CORE_RSTOUT);
 824
 825         DRM_DEBUG_KMS("%s: ---- CORE REGISTERS ----\n", prefix);
 826         DUMPREG(HDMI_CON_0);
 827         DUMPREG(HDMI_CON_1);
 828         DUMPREG(HDMI_CON_2);
 829         DUMPREG(HDMI_SYS_STATUS);
 830         DUMPREG(HDMI_PHY_STATUS_0);
 831         DUMPREG(HDMI_STATUS_EN);
 832         DUMPREG(HDMI_HPD);
 833         DUMPREG(HDMI_MODE_SEL);
 834         DUMPREG(HDMI_ENC_EN);
 835         DUMPREG(HDMI_DC_CONTROL);
 836         DUMPREG(HDMI_VIDEO_PATTERN_GEN);
 837
 838         DRM_DEBUG_KMS("%s: ---- CORE SYNC REGISTERS ----\n", prefix);
 839         DUMPREG(HDMI_H_BLANK_0);
 840         DUMPREG(HDMI_H_BLANK_1);
 841         DUMPREG(HDMI_V2_BLANK_0);
 842         DUMPREG(HDMI_V2_BLANK_1);
 843         DUMPREG(HDMI_V1_BLANK_0);
 844         DUMPREG(HDMI_V1_BLANK_1);
 845         DUMPREG(HDMI_V_LINE_0);
 846         DUMPREG(HDMI_V_LINE_1);
 847         DUMPREG(HDMI_H_LINE_0);
 848         DUMPREG(HDMI_H_LINE_1);
 849         DUMPREG(HDMI_HSYNC_POL);
 850
 851         DUMPREG(HDMI_VSYNC_POL);
 852         DUMPREG(HDMI_INT_PRO_MODE);
 853         DUMPREG(HDMI_V_BLANK_F0_0);
 854         DUMPREG(HDMI_V_BLANK_F0_1);
 855         DUMPREG(HDMI_V_BLANK_F1_0);
 856         DUMPREG(HDMI_V_BLANK_F1_1);
 857
 858         DUMPREG(HDMI_H_SYNC_START_0);
 859         DUMPREG(HDMI_H_SYNC_START_1);
 860         DUMPREG(HDMI_H_SYNC_END_0);
 861         DUMPREG(HDMI_H_SYNC_END_1);
 862
 863         DUMPREG(HDMI_V_SYNC_LINE_BEF_2_0);
 864         DUMPREG(HDMI_V_SYNC_LINE_BEF_2_1);
 865         DUMPREG(HDMI_V_SYNC_LINE_BEF_1_0);
 866         DUMPREG(HDMI_V_SYNC_LINE_BEF_1_1);
 867
 868         DUMPREG(HDMI_V_SYNC_LINE_AFT_2_0);
 869         DUMPREG(HDMI_V_SYNC_LINE_AFT_2_1);
 870         DUMPREG(HDMI_V_SYNC_LINE_AFT_1_0);
 871         DUMPREG(HDMI_V_SYNC_LINE_AFT_1_1);
 872
 873         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_2_0);
 874         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_2_1);
 875         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_1_0);
 876         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_1_1);
 877
 878         DUMPREG(HDMI_V_BLANK_F2_0);
 879         DUMPREG(HDMI_V_BLANK_F2_1);
 880         DUMPREG(HDMI_V_BLANK_F3_0);
 881         DUMPREG(HDMI_V_BLANK_F3_1);
 882         DUMPREG(HDMI_V_BLANK_F4_0);
 883         DUMPREG(HDMI_V_BLANK_F4_1);
 884         DUMPREG(HDMI_V_BLANK_F5_0);
 885         DUMPREG(HDMI_V_BLANK_F5_1);
 886
 887         DUMPREG(HDMI_V_SYNC_LINE_AFT_3_0);
 888         DUMPREG(HDMI_V_SYNC_LINE_AFT_3_1);
 889         DUMPREG(HDMI_V_SYNC_LINE_AFT_4_0);
 890         DUMPREG(HDMI_V_SYNC_LINE_AFT_4_1);
 891         DUMPREG(HDMI_V_SYNC_LINE_AFT_5_0);
 892         DUMPREG(HDMI_V_SYNC_LINE_AFT_5_1);
 893         DUMPREG(HDMI_V_SYNC_LINE_AFT_6_0);
 894         DUMPREG(HDMI_V_SYNC_LINE_AFT_6_1);
 895
 896         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_3_0);
 897         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_3_1);
 898         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_4_0);
 899         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_4_1);
 900         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_5_0);
 901         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_5_1);
 902         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_6_0);
 903         DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_6_1);
 904
 905         DUMPREG(HDMI_VACT_SPACE_1_0);
 906         DUMPREG(HDMI_VACT_SPACE_1_1);
 907         DUMPREG(HDMI_VACT_SPACE_2_0);
 908         DUMPREG(HDMI_VACT_SPACE_2_1);
 909         DUMPREG(HDMI_VACT_SPACE_3_0);
 910         DUMPREG(HDMI_VACT_SPACE_3_1);
 911         DUMPREG(HDMI_VACT_SPACE_4_0);
 912         DUMPREG(HDMI_VACT_SPACE_4_1);
 913         DUMPREG(HDMI_VACT_SPACE_5_0);
 914         DUMPREG(HDMI_VACT_SPACE_5_1);
 915         DUMPREG(HDMI_VACT_SPACE_6_0);
 916         DUMPREG(HDMI_VACT_SPACE_6_1);
 917
 918         DRM_DEBUG_KMS("%s: ---- TG REGISTERS ----\n", prefix);
 919         DUMPREG(HDMI_TG_CMD);
 920         DUMPREG(HDMI_TG_H_FSZ_L);
 921         DUMPREG(HDMI_TG_H_FSZ_H);
 922         DUMPREG(HDMI_TG_HACT_ST_L);
 923         DUMPREG(HDMI_TG_HACT_ST_H);
 924         DUMPREG(HDMI_TG_HACT_SZ_L);
 925         DUMPREG(HDMI_TG_HACT_SZ_H);
 926         DUMPREG(HDMI_TG_V_FSZ_L);
 927         DUMPREG(HDMI_TG_V_FSZ_H);
 928         DUMPREG(HDMI_TG_VSYNC_L);
 929         DUMPREG(HDMI_TG_VSYNC_H);
 930         DUMPREG(HDMI_TG_VSYNC2_L);
 931         DUMPREG(HDMI_TG_VSYNC2_H);
 932         DUMPREG(HDMI_TG_VACT_ST_L);
 933         DUMPREG(HDMI_TG_VACT_ST_H);
 934         DUMPREG(HDMI_TG_VACT_SZ_L);
 935         DUMPREG(HDMI_TG_VACT_SZ_H);
 936         DUMPREG(HDMI_TG_FIELD_CHG_L);
 937         DUMPREG(HDMI_TG_FIELD_CHG_H);
 938         DUMPREG(HDMI_TG_VACT_ST2_L);
 939         DUMPREG(HDMI_TG_VACT_ST2_H);
 940         DUMPREG(HDMI_TG_VACT_ST3_L);
 941         DUMPREG(HDMI_TG_VACT_ST3_H);
 942         DUMPREG(HDMI_TG_VACT_ST4_L);
 943         DUMPREG(HDMI_TG_VACT_ST4_H);
 944         DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_L);
 945         DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_H);
 946         DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_L);
 947         DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_H);
 948         DUMPREG(HDMI_TG_FIELD_TOP_HDMI_L);
 949         DUMPREG(HDMI_TG_FIELD_TOP_HDMI_H);
 950         DUMPREG(HDMI_TG_FIELD_BOT_HDMI_L);
 951         DUMPREG(HDMI_TG_FIELD_BOT_HDMI_H);
 952         DUMPREG(HDMI_TG_3D);
 953
 954         DRM_DEBUG_KMS("%s: ---- PACKET REGISTERS ----\n", prefix);
 955         DUMPREG(HDMI_AVI_CON);
 956         DUMPREG(HDMI_AVI_HEADER0);
 957         DUMPREG(HDMI_AVI_HEADER1);
 958         DUMPREG(HDMI_AVI_HEADER2);
 959         DUMPREG(HDMI_AVI_CHECK_SUM);
 960         DUMPREG(HDMI_VSI_CON);
 961         DUMPREG(HDMI_VSI_HEADER0);
 962         DUMPREG(HDMI_VSI_HEADER1);
 963         DUMPREG(HDMI_VSI_HEADER2);
 964         for (i = 0; i < 7; ++i)
 965                 DUMPREG(HDMI_VSI_DATA(i));
 966
 967 #undef DUMPREG
 968 }
 969
 970 static void hdmi_regs_dump(struct hdmi_context *hdata, char *prefix)
 971 {
 972         if (hdata->drv_data->type == HDMI_TYPE13)
 973                 hdmi_v13_regs_dump(hdata, prefix);
 974         else
 975                 hdmi_v14_regs_dump(hdata, prefix);
 976 }
 977
 978 static int hdmi_clk_enable_gates(struct hdmi_context *hdata)
 979 {
 980         int i, ret;
 981
 982         for (i = 0; i < hdata->drv_data->clk_gates.count; ++i) {
 983                 ret = clk_prepare_enable(hdata->clk_gates[i]);
 984                 if (!ret)
 985                         continue;
 986
 987                 dev_err(hdata->dev, "Cannot enable clock '%s', %d\n",
 988                         hdata->drv_data->clk_gates.data[i], ret);
 989                 while (i--)
 990                         clk_disable_unprepare(hdata->clk_gates[i]);
 991                 return ret;
 992         }
 993
 994         return 0;
 995 }
 996
 997 static void hdmi_clk_disable_gates(struct hdmi_context *hdata)
 998 {
 999         int i = hdata->drv_data->clk_gates.count;
1000
1001         while (i--)
1002                 clk_disable_unprepare(hdata->clk_gates[i]);
1003 }
1004
1005 static int hdmi_clk_set_parents(struct hdmi_context *hdata, bool to_phy)
1006 {
1007         struct device *dev = hdata->dev;
1008         int ret = 0;
1009         int i;
1010
1011         for (i = 0; i < hdata->drv_data->clk_muxes.count; i += 3) {
1012                 struct clk **c = &hdata->clk_muxes[i];
1013
1014                 ret = clk_set_parent(c[2], c[to_phy]);
1015                 if (!ret)
1016                         continue;
1017
1018                 dev_err(dev, "Cannot set clock parent of '%s' to '%s', %d\n",
1019                         hdata->drv_data->clk_muxes.data[i + 2],
1020                         hdata->drv_data->clk_muxes.data[i + to_phy], ret);
1021         }
1022
1023         return ret;
1024 }
1025
1026 static u8 hdmi_chksum(struct hdmi_context *hdata,
1027                         u32 start, u8 len, u32 hdr_sum)
1028 {
1029         int i;
1030
1031         /* hdr_sum : header0 + header1 + header2
1032         * start : start address of packet byte1
1033         * len : packet bytes - 1 */
1034         for (i = 0; i < len; ++i)
1035                 hdr_sum += 0xff & hdmi_reg_read(hdata, start + i * 4);
1036
1037         /* return 2's complement of 8 bit hdr_sum */
1038         return (u8)(~(hdr_sum & 0xff) + 1);
1039 }
1040
1041 static void hdmi_reg_infoframe(struct hdmi_context *hdata,
1042                         union hdmi_infoframe *infoframe)
1043 {
1044         u32 hdr_sum;
1045         u8 chksum;
1046         u8 ar;
1047
1048         if (hdata->dvi_mode) {
1049                 hdmi_reg_writeb(hdata, HDMI_VSI_CON,
1050                                 HDMI_VSI_CON_DO_NOT_TRANSMIT);
1051                 hdmi_reg_writeb(hdata, HDMI_AVI_CON,
1052                                 HDMI_AVI_CON_DO_NOT_TRANSMIT);
1053                 hdmi_reg_writeb(hdata, HDMI_AUI_CON, HDMI_AUI_CON_NO_TRAN);
1054                 return;
1055         }
1056
1057         switch (infoframe->any.type) {
1058         case HDMI_INFOFRAME_TYPE_AVI:
1059                 hdmi_reg_writeb(hdata, HDMI_AVI_CON, HDMI_AVI_CON_EVERY_VSYNC);
1060                 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER0, infoframe->any.type);
1061                 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER1,
1062                                 infoframe->any.version);
1063                 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER2, infoframe->any.length);
1064                 hdr_sum = infoframe->any.type + infoframe->any.version +
1065                           infoframe->any.length;
1066
1067                 /* Output format zero hardcoded ,RGB YBCR selection */
1068                 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(1), 0 << 5 |
1069                         AVI_ACTIVE_FORMAT_VALID |
1070                         AVI_UNDERSCANNED_DISPLAY_VALID);
1071
1072                 /*
1073                  * Set the aspect ratio as per the mode, mentioned in
1074                  * Table 9 AVI InfoFrame Data Byte 2 of CEA-861-D Standard
1075                  */
1076                 ar = hdata->current_mode.picture_aspect_ratio;
1077                 switch (ar) {
1078                 case HDMI_PICTURE_ASPECT_4_3:
1079                         ar |= AVI_4_3_CENTER_RATIO;
1080                         break;
1081                 case HDMI_PICTURE_ASPECT_16_9:
1082                         ar |= AVI_16_9_CENTER_RATIO;
1083                         break;
1084                 case HDMI_PICTURE_ASPECT_NONE:
1085                 default:
1086                         ar |= AVI_SAME_AS_PIC_ASPECT_RATIO;
1087                         break;
1088                 }
1089                 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2), ar);
1090
1091                 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(4), hdata->cea_video_id);
1092
1093                 chksum = hdmi_chksum(hdata, HDMI_AVI_BYTE(1),
1094                                         infoframe->any.length, hdr_sum);
1095                 DRM_DEBUG_KMS("AVI checksum = 0x%x\n", chksum);
1096                 hdmi_reg_writeb(hdata, HDMI_AVI_CHECK_SUM, chksum);
1097                 break;
1098         case HDMI_INFOFRAME_TYPE_AUDIO:
1099                 hdmi_reg_writeb(hdata, HDMI_AUI_CON, 0x02);
1100                 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER0, infoframe->any.type);
1101                 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER1,
1102                                 infoframe->any.version);
1103                 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER2, infoframe->any.length);
1104                 hdr_sum = infoframe->any.type + infoframe->any.version +
1105                           infoframe->any.length;
1106                 chksum = hdmi_chksum(hdata, HDMI_AUI_BYTE(1),
1107                                         infoframe->any.length, hdr_sum);
1108                 DRM_DEBUG_KMS("AUI checksum = 0x%x\n", chksum);
1109                 hdmi_reg_writeb(hdata, HDMI_AUI_CHECK_SUM, chksum);
1110                 break;
1111         default:
1112                 break;
1113         }
1114 }
1115
1116 static enum drm_connector_status hdmi_detect(struct drm_connector *connector,
1117                                 bool force)
1118 {
1119         struct hdmi_context *hdata = connector_to_hdmi(connector);
1120
1121         if (gpiod_get_value(hdata->hpd_gpio))
1122                 return connector_status_connected;
1123
1124         return connector_status_disconnected;
1125 }
1126
1127 static void hdmi_connector_destroy(struct drm_connector *connector)
1128 {
1129         drm_connector_unregister(connector);
1130         drm_connector_cleanup(connector);
1131 }
1132
1133 static const struct drm_connector_funcs hdmi_connector_funcs = {
1134         .dpms = drm_atomic_helper_connector_dpms,
1135         .fill_modes = drm_helper_probe_single_connector_modes,
1136         .detect = hdmi_detect,
1137         .destroy = hdmi_connector_destroy,
1138         .reset = drm_atomic_helper_connector_reset,
1139         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1140         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1141 };
1142
1143 static int hdmi_get_modes(struct drm_connector *connector)
1144 {
1145         struct hdmi_context *hdata = connector_to_hdmi(connector);
1146         struct edid *edid;
1147         int ret;
1148
1149         if (!hdata->ddc_adpt)
1150                 return -ENODEV;
1151
1152         edid = drm_get_edid(connector, hdata->ddc_adpt);
1153         if (!edid)
1154                 return -ENODEV;
1155
1156         hdata->dvi_mode = !drm_detect_hdmi_monitor(edid);
1157         DRM_DEBUG_KMS("%s : width[%d] x height[%d]\n",
1158                 (hdata->dvi_mode ? "dvi monitor" : "hdmi monitor"),
1159                 edid->width_cm, edid->height_cm);
1160
1161         drm_mode_connector_update_edid_property(connector, edid);
1162
1163         ret = drm_add_edid_modes(connector, edid);
1164
1165         kfree(edid);
1166
1167         return ret;
1168 }
1169
1170 static int hdmi_find_phy_conf(struct hdmi_context *hdata, u32 pixel_clock)
1171 {
1172         const struct hdmiphy_configs *confs = &hdata->drv_data->phy_confs;
1173         int i;
1174
1175         for (i = 0; i < confs->count; i++)
1176                 if (confs->data[i].pixel_clock == pixel_clock)
1177                         return i;
1178
1179         DRM_DEBUG_KMS("Could not find phy config for %d\n", pixel_clock);
1180         return -EINVAL;
1181 }
1182
1183 static int hdmi_mode_valid(struct drm_connector *connector,
1184                         struct drm_display_mode *mode)
1185 {
1186         struct hdmi_context *hdata = connector_to_hdmi(connector);
1187         int ret;
1188
1189         DRM_DEBUG_KMS("xres=%d, yres=%d, refresh=%d, intl=%d clock=%d\n",
1190                 mode->hdisplay, mode->vdisplay, mode->vrefresh,
1191                 (mode->flags & DRM_MODE_FLAG_INTERLACE) ? true :
1192                 false, mode->clock * 1000);
1193
1194         ret = hdmi_find_phy_conf(hdata, mode->clock * 1000);
1195         if (ret < 0)
1196                 return MODE_BAD;
1197
1198         return MODE_OK;
1199 }
1200
1201 static struct drm_encoder *hdmi_best_encoder(struct drm_connector *connector)
1202 {
1203         struct hdmi_context *hdata = connector_to_hdmi(connector);
1204
1205         return &hdata->encoder;
1206 }
1207
1208 static const struct drm_connector_helper_funcs hdmi_connector_helper_funcs = {
1209         .get_modes = hdmi_get_modes,
1210         .mode_valid = hdmi_mode_valid,
1211         .best_encoder = hdmi_best_encoder,
1212 };
1213
1214 static int hdmi_create_connector(struct drm_encoder *encoder)
1215 {
1216         struct hdmi_context *hdata = encoder_to_hdmi(encoder);
1217         struct drm_connector *connector = &hdata->connector;
1218         int ret;
1219
1220         connector->interlace_allowed = true;
1221         connector->polled = DRM_CONNECTOR_POLL_HPD;
1222
1223         ret = drm_connector_init(hdata->drm_dev, connector,
1224                         &hdmi_connector_funcs, DRM_MODE_CONNECTOR_HDMIA);
1225         if (ret) {
1226                 DRM_ERROR("Failed to initialize connector with drm\n");
1227                 return ret;
1228         }
1229
1230         drm_connector_helper_add(connector, &hdmi_connector_helper_funcs);
1231         drm_connector_register(connector);
1232         drm_mode_connector_attach_encoder(connector, encoder);
1233
1234         return 0;
1235 }
1236
1237 static bool hdmi_mode_fixup(struct drm_encoder *encoder,
1238                             const struct drm_display_mode *mode,
1239                             struct drm_display_mode *adjusted_mode)
1240 {
1241         struct drm_device *dev = encoder->dev;
1242         struct drm_connector *connector;
1243         struct drm_display_mode *m;
1244         int mode_ok;
1245
1246         drm_mode_set_crtcinfo(adjusted_mode, 0);
1247
1248         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1249                 if (connector->encoder == encoder)
1250                         break;
1251         }
1252
1253         if (connector->encoder != encoder)
1254                 return true;
1255
1256         mode_ok = hdmi_mode_valid(connector, adjusted_mode);
1257
1258         if (mode_ok == MODE_OK)
1259                 return true;
1260
1261         /*
1262          * Find the most suitable mode and copy it to adjusted_mode.
1263          */
1264         list_for_each_entry(m, &connector->modes, head) {
1265                 mode_ok = hdmi_mode_valid(connector, m);
1266
1267                 if (mode_ok == MODE_OK) {
1268                         DRM_INFO("desired mode doesn't exist so\n");
1269                         DRM_INFO("use the most suitable mode among modes.\n");
1270
1271                         DRM_DEBUG_KMS("Adjusted Mode: [%d]x[%d] [%d]Hz\n",
1272                                 m->hdisplay, m->vdisplay, m->vrefresh);
1273
1274                         drm_mode_copy(adjusted_mode, m);
1275                         break;
1276                 }
1277         }
1278
1279         return true;
1280 }
1281
1282 static void hdmi_reg_acr(struct hdmi_context *hdata, u32 freq)
1283 {
1284         u32 n, cts;
1285
1286         cts = (freq % 9) ? 27000 : 30000;
1287         n = 128 * freq / (27000000 / cts);
1288
1289         hdmi_reg_writev(hdata, HDMI_ACR_N0, 3, n);
1290         hdmi_reg_writev(hdata, HDMI_ACR_MCTS0, 3, cts);
1291         hdmi_reg_writev(hdata, HDMI_ACR_CTS0, 3, cts);
1292         hdmi_reg_writeb(hdata, HDMI_ACR_CON, 4);
1293 }
1294
1295 static void hdmi_audio_init(struct hdmi_context *hdata)
1296 {
1297         u32 sample_rate, bits_per_sample;
1298         u32 data_num, bit_ch, sample_frq;
1299         u32 val;
1300
1301         sample_rate = 44100;
1302         bits_per_sample = 16;
1303
1304         switch (bits_per_sample) {
1305         case 20:
1306                 data_num = 2;
1307                 bit_ch = 1;
1308                 break;
1309         case 24:
1310                 data_num = 3;
1311                 bit_ch = 1;
1312                 break;
1313         default:
1314                 data_num = 1;
1315                 bit_ch = 0;
1316                 break;
1317         }
1318
1319         hdmi_reg_acr(hdata, sample_rate);
1320
1321         hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CON, HDMI_I2S_IN_DISABLE
1322                                 | HDMI_I2S_AUD_I2S | HDMI_I2S_CUV_I2S_ENABLE
1323                                 | HDMI_I2S_MUX_ENABLE);
1324
1325         hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CH, HDMI_I2S_CH0_EN
1326                         | HDMI_I2S_CH1_EN | HDMI_I2S_CH2_EN);
1327
1328         hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CUV, HDMI_I2S_CUV_RL_EN);
1329
1330         sample_frq = (sample_rate == 44100) ? 0 :
1331                         (sample_rate == 48000) ? 2 :
1332                         (sample_rate == 32000) ? 3 :
1333                         (sample_rate == 96000) ? 0xa : 0x0;
1334
1335         hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_DIS);
1336         hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_EN);
1337
1338         val = hdmi_reg_read(hdata, HDMI_I2S_DSD_CON) | 0x01;
1339         hdmi_reg_writeb(hdata, HDMI_I2S_DSD_CON, val);
1340
1341         /* Configuration I2S input ports. Configure I2S_PIN_SEL_0~4 */
1342         hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_0, HDMI_I2S_SEL_SCLK(5)
1343                         | HDMI_I2S_SEL_LRCK(6));
1344         hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_1, HDMI_I2S_SEL_SDATA1(1)
1345                         | HDMI_I2S_SEL_SDATA2(4));
1346         hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_2, HDMI_I2S_SEL_SDATA3(1)
1347                         | HDMI_I2S_SEL_SDATA2(2));
1348         hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_3, HDMI_I2S_SEL_DSD(0));
1349
1350         /* I2S_CON_1 & 2 */
1351         hdmi_reg_writeb(hdata, HDMI_I2S_CON_1, HDMI_I2S_SCLK_FALLING_EDGE
1352                         | HDMI_I2S_L_CH_LOW_POL);
1353         hdmi_reg_writeb(hdata, HDMI_I2S_CON_2, HDMI_I2S_MSB_FIRST_MODE
1354                         | HDMI_I2S_SET_BIT_CH(bit_ch)
1355                         | HDMI_I2S_SET_SDATA_BIT(data_num)
1356                         | HDMI_I2S_BASIC_FORMAT);
1357
1358         /* Configure register related to CUV information */
1359         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_0, HDMI_I2S_CH_STATUS_MODE_0
1360                         | HDMI_I2S_2AUD_CH_WITHOUT_PREEMPH
1361                         | HDMI_I2S_COPYRIGHT
1362                         | HDMI_I2S_LINEAR_PCM
1363                         | HDMI_I2S_CONSUMER_FORMAT);
1364         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_1, HDMI_I2S_CD_PLAYER);
1365         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_2, HDMI_I2S_SET_SOURCE_NUM(0));
1366         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_3, HDMI_I2S_CLK_ACCUR_LEVEL_2
1367                         | HDMI_I2S_SET_SMP_FREQ(sample_frq));
1368         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_4,
1369                         HDMI_I2S_ORG_SMP_FREQ_44_1
1370                         | HDMI_I2S_WORD_LEN_MAX24_24BITS
1371                         | HDMI_I2S_WORD_LEN_MAX_24BITS);
1372
1373         hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_CON, HDMI_I2S_CH_STATUS_RELOAD);
1374 }
1375
1376 static void hdmi_audio_control(struct hdmi_context *hdata, bool onoff)
1377 {
1378         if (hdata->dvi_mode)
1379                 return;
1380
1381         hdmi_reg_writeb(hdata, HDMI_AUI_CON, onoff ? 2 : 0);
1382         hdmi_reg_writemask(hdata, HDMI_CON_0, onoff ?
1383                         HDMI_ASP_EN : HDMI_ASP_DIS, HDMI_ASP_MASK);
1384 }
1385
1386 static void hdmi_start(struct hdmi_context *hdata, bool start)
1387 {
1388         u32 val = start ? HDMI_TG_EN : 0;
1389
1390         if (hdata->current_mode.flags & DRM_MODE_FLAG_INTERLACE)
1391                 val |= HDMI_FIELD_EN;
1392
1393         hdmi_reg_writemask(hdata, HDMI_CON_0, val, HDMI_EN);
1394         hdmi_reg_writemask(hdata, HDMI_TG_CMD, val, HDMI_TG_EN | HDMI_FIELD_EN);
1395 }
1396
1397 static void hdmi_conf_init(struct hdmi_context *hdata)
1398 {
1399         union hdmi_infoframe infoframe;
1400
1401         /* disable HPD interrupts from HDMI IP block, use GPIO instead */
1402         hdmi_reg_writemask(hdata, HDMI_INTC_CON, 0, HDMI_INTC_EN_GLOBAL |
1403                 HDMI_INTC_EN_HPD_PLUG | HDMI_INTC_EN_HPD_UNPLUG);
1404
1405         /* choose HDMI mode */
1406         hdmi_reg_writemask(hdata, HDMI_MODE_SEL,
1407                 HDMI_MODE_HDMI_EN, HDMI_MODE_MASK);
1408         /* apply video pre-amble and guard band in HDMI mode only */
1409         hdmi_reg_writeb(hdata, HDMI_CON_2, 0);
1410         /* disable bluescreen */
1411         hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_BLUE_SCR_EN);
1412
1413         if (hdata->dvi_mode) {
1414                 hdmi_reg_writemask(hdata, HDMI_MODE_SEL,
1415                                 HDMI_MODE_DVI_EN, HDMI_MODE_MASK);
1416                 hdmi_reg_writeb(hdata, HDMI_CON_2,
1417                                 HDMI_VID_PREAMBLE_DIS | HDMI_GUARD_BAND_DIS);
1418         }
1419
1420         if (hdata->drv_data->type == HDMI_TYPE13) {
1421                 /* choose bluescreen (fecal) color */
1422                 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_0, 0x12);
1423                 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_1, 0x34);
1424                 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_2, 0x56);
1425
1426                 /* enable AVI packet every vsync, fixes purple line problem */
1427                 hdmi_reg_writeb(hdata, HDMI_V13_AVI_CON, 0x02);
1428                 /* force RGB, look to CEA-861-D, table 7 for more detail */
1429                 hdmi_reg_writeb(hdata, HDMI_V13_AVI_BYTE(0), 0 << 5);
1430                 hdmi_reg_writemask(hdata, HDMI_CON_1, 0x10 << 5, 0x11 << 5);
1431
1432                 hdmi_reg_writeb(hdata, HDMI_V13_SPD_CON, 0x02);
1433                 hdmi_reg_writeb(hdata, HDMI_V13_AUI_CON, 0x02);
1434                 hdmi_reg_writeb(hdata, HDMI_V13_ACR_CON, 0x04);
1435         } else {
1436                 infoframe.any.type = HDMI_INFOFRAME_TYPE_AVI;
1437                 infoframe.any.version = HDMI_AVI_VERSION;
1438                 infoframe.any.length = HDMI_AVI_LENGTH;
1439                 hdmi_reg_infoframe(hdata, &infoframe);
1440
1441                 infoframe.any.type = HDMI_INFOFRAME_TYPE_AUDIO;
1442                 infoframe.any.version = HDMI_AUI_VERSION;
1443                 infoframe.any.length = HDMI_AUI_LENGTH;
1444                 hdmi_reg_infoframe(hdata, &infoframe);
1445
1446                 /* enable AVI packet every vsync, fixes purple line problem */
1447                 hdmi_reg_writemask(hdata, HDMI_CON_1, 2, 3 << 5);
1448         }
1449 }
1450
1451 static void hdmiphy_wait_for_pll(struct hdmi_context *hdata)
1452 {
1453         int tries;
1454
1455         for (tries = 0; tries < 10; ++tries) {
1456                 u32 val = hdmi_reg_read(hdata, HDMI_PHY_STATUS);
1457
1458                 if (val & HDMI_PHY_STATUS_READY) {
1459                         DRM_DEBUG_KMS("PLL stabilized after %d tries\n", tries);
1460                         return;
1461                 }
1462                 usleep_range(10, 20);
1463         }
1464
1465         DRM_ERROR("PLL could not reach steady state\n");
1466 }
1467
1468 static void hdmi_v13_mode_apply(struct hdmi_context *hdata)
1469 {
1470         struct drm_display_mode *m = &hdata->current_mode;
1471         unsigned int val;
1472
1473         hdmi_reg_writev(hdata, HDMI_H_BLANK_0, 2, m->htotal - m->hdisplay);
1474         hdmi_reg_writev(hdata, HDMI_V13_H_V_LINE_0, 3,
1475                         (m->htotal << 12) | m->vtotal);
1476
1477         val = (m->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0;
1478         hdmi_reg_writev(hdata, HDMI_VSYNC_POL, 1, val);
1479
1480         val = (m->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0;
1481         hdmi_reg_writev(hdata, HDMI_INT_PRO_MODE, 1, val);
1482
1483         val = (m->hsync_start - m->hdisplay - 2);
1484         val |= ((m->hsync_end - m->hdisplay - 2) << 10);
1485         val |= ((m->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0)<<20;
1486         hdmi_reg_writev(hdata, HDMI_V13_H_SYNC_GEN_0, 3, val);
1487
1488         /*
1489          * Quirk requirement for exynos HDMI IP design,
1490          * 2 pixels less than the actual calculation for hsync_start
1491          * and end.
1492          */
1493
1494         /* Following values & calculations differ for different type of modes */
1495         if (m->flags & DRM_MODE_FLAG_INTERLACE) {
1496                 val = ((m->vsync_end - m->vdisplay) / 2);
1497                 val |= ((m->vsync_start - m->vdisplay) / 2) << 12;
1498                 hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_1_0, 3, val);
1499
1500                 val = m->vtotal / 2;
1501                 val |= ((m->vtotal - m->vdisplay) / 2) << 11;
1502                 hdmi_reg_writev(hdata, HDMI_V13_V_BLANK_0, 3, val);
1503
1504                 val = (m->vtotal +
1505                         ((m->vsync_end - m->vsync_start) * 4) + 5) / 2;
1506                 val |= m->vtotal << 11;
1507                 hdmi_reg_writev(hdata, HDMI_V13_V_BLANK_F_0, 3, val);
1508
1509                 val = ((m->vtotal / 2) + 7);
1510                 val |= ((m->vtotal / 2) + 2) << 12;
1511                 hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_2_0, 3, val);
1512
1513                 val = ((m->htotal / 2) + (m->hsync_start - m->hdisplay));
1514                 val |= ((m->htotal / 2) +
1515                         (m->hsync_start - m->hdisplay)) << 12;
1516                 hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_3_0, 3, val);
1517
1518                 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST_L, 2,
1519                                 (m->vtotal - m->vdisplay) / 2);
1520                 hdmi_reg_writev(hdata, HDMI_TG_VACT_SZ_L, 2, m->vdisplay / 2);
1521
1522                 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST2_L, 2, 0x249);
1523         } else {
1524                 val = m->vtotal;
1525                 val |= (m->vtotal - m->vdisplay) << 11;
1526                 hdmi_reg_writev(hdata, HDMI_V13_V_BLANK_0, 3, val);
1527
1528                 hdmi_reg_writev(hdata, HDMI_V13_V_BLANK_F_0, 3, 0);
1529
1530                 val = (m->vsync_end - m->vdisplay);
1531                 val |= ((m->vsync_start - m->vdisplay) << 12);
1532                 hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_1_0, 3, val);
1533
1534                 hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_2_0, 3, 0x1001);
1535                 hdmi_reg_writev(hdata, HDMI_V13_V_SYNC_GEN_3_0, 3, 0x1001);
1536                 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST_L, 2,
1537                                 m->vtotal - m->vdisplay);
1538                 hdmi_reg_writev(hdata, HDMI_TG_VACT_SZ_L, 2, m->vdisplay);
1539         }
1540
1541         hdmi_reg_writev(hdata, HDMI_TG_H_FSZ_L, 2, m->htotal);
1542         hdmi_reg_writev(hdata, HDMI_TG_HACT_ST_L, 2, m->htotal - m->hdisplay);
1543         hdmi_reg_writev(hdata, HDMI_TG_HACT_SZ_L, 2, m->hdisplay);
1544         hdmi_reg_writev(hdata, HDMI_TG_V_FSZ_L, 2, m->vtotal);
1545 }
1546
1547 static void hdmi_v14_mode_apply(struct hdmi_context *hdata)
1548 {
1549         struct drm_display_mode *m = &hdata->current_mode;
1550
1551         hdmi_reg_writev(hdata, HDMI_H_BLANK_0, 2, m->htotal - m->hdisplay);
1552         hdmi_reg_writev(hdata, HDMI_V_LINE_0, 2, m->vtotal);
1553         hdmi_reg_writev(hdata, HDMI_H_LINE_0, 2, m->htotal);
1554         hdmi_reg_writev(hdata, HDMI_HSYNC_POL, 1,
1555                         (m->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0);
1556         hdmi_reg_writev(hdata, HDMI_VSYNC_POL, 1,
1557                         (m->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0);
1558         hdmi_reg_writev(hdata, HDMI_INT_PRO_MODE, 1,
1559                         (m->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0);
1560
1561         /*
1562          * Quirk requirement for exynos 5 HDMI IP design,
1563          * 2 pixels less than the actual calculation for hsync_start
1564          * and end.
1565          */
1566
1567         /* Following values & calculations differ for different type of modes */
1568         if (m->flags & DRM_MODE_FLAG_INTERLACE) {
1569                 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_BEF_2_0, 2,
1570                         (m->vsync_end - m->vdisplay) / 2);
1571                 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_BEF_1_0, 2,
1572                         (m->vsync_start - m->vdisplay) / 2);
1573                 hdmi_reg_writev(hdata, HDMI_V2_BLANK_0, 2, m->vtotal / 2);
1574                 hdmi_reg_writev(hdata, HDMI_V1_BLANK_0, 2,
1575                                 (m->vtotal - m->vdisplay) / 2);
1576                 hdmi_reg_writev(hdata, HDMI_V_BLANK_F0_0, 2,
1577                                 m->vtotal - m->vdisplay / 2);
1578                 hdmi_reg_writev(hdata, HDMI_V_BLANK_F1_0, 2, m->vtotal);
1579                 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_2_0, 2,
1580                                 (m->vtotal / 2) + 7);
1581                 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_1_0, 2,
1582                                 (m->vtotal / 2) + 2);
1583                 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_0, 2,
1584                         (m->htotal / 2) + (m->hsync_start - m->hdisplay));
1585                 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_0, 2,
1586                         (m->htotal / 2) + (m->hsync_start - m->hdisplay));
1587                 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST_L, 2,
1588                                 (m->vtotal - m->vdisplay) / 2);
1589                 hdmi_reg_writev(hdata, HDMI_TG_VACT_SZ_L, 2, m->vdisplay / 2);
1590                 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST2_L, 2,
1591                                 m->vtotal - m->vdisplay / 2);
1592                 hdmi_reg_writev(hdata, HDMI_TG_VSYNC2_L, 2,
1593                                 (m->vtotal / 2) + 1);
1594                 hdmi_reg_writev(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, 2,
1595                                 (m->vtotal / 2) + 1);
1596                 hdmi_reg_writev(hdata, HDMI_TG_FIELD_BOT_HDMI_L, 2,
1597                                 (m->vtotal / 2) + 1);
1598                 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST3_L, 2, 0x0);
1599                 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST4_L, 2, 0x0);
1600         } else {
1601                 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_BEF_2_0, 2,
1602                         m->vsync_end - m->vdisplay);
1603                 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_BEF_1_0, 2,
1604                         m->vsync_start - m->vdisplay);
1605                 hdmi_reg_writev(hdata, HDMI_V2_BLANK_0, 2, m->vtotal);
1606                 hdmi_reg_writev(hdata, HDMI_V1_BLANK_0, 2,
1607                                 m->vtotal - m->vdisplay);
1608                 hdmi_reg_writev(hdata, HDMI_V_BLANK_F0_0, 2, 0xffff);
1609                 hdmi_reg_writev(hdata, HDMI_V_BLANK_F1_0, 2, 0xffff);
1610                 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_2_0, 2, 0xffff);
1611                 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_1_0, 2, 0xffff);
1612                 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_0, 2, 0xffff);
1613                 hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_0, 2, 0xffff);
1614                 hdmi_reg_writev(hdata, HDMI_TG_VACT_ST_L, 2,
1615                                 m->vtotal - m->vdisplay);
1616                 hdmi_reg_writev(hdata, HDMI_TG_VACT_SZ_L, 2, m->vdisplay);
1617         }
1618
1619         hdmi_reg_writev(hdata, HDMI_H_SYNC_START_0, 2,
1620                         m->hsync_start - m->hdisplay - 2);
1621         hdmi_reg_writev(hdata, HDMI_H_SYNC_END_0, 2,
1622                         m->hsync_end - m->hdisplay - 2);
1623         hdmi_reg_writev(hdata, HDMI_VACT_SPACE_1_0, 2, 0xffff);
1624         hdmi_reg_writev(hdata, HDMI_VACT_SPACE_2_0, 2, 0xffff);
1625         hdmi_reg_writev(hdata, HDMI_VACT_SPACE_3_0, 2, 0xffff);
1626         hdmi_reg_writev(hdata, HDMI_VACT_SPACE_4_0, 2, 0xffff);
1627         hdmi_reg_writev(hdata, HDMI_VACT_SPACE_5_0, 2, 0xffff);
1628         hdmi_reg_writev(hdata, HDMI_VACT_SPACE_6_0, 2, 0xffff);
1629         hdmi_reg_writev(hdata, HDMI_V_BLANK_F2_0, 2, 0xffff);
1630         hdmi_reg_writev(hdata, HDMI_V_BLANK_F3_0, 2, 0xffff);
1631         hdmi_reg_writev(hdata, HDMI_V_BLANK_F4_0, 2, 0xffff);
1632         hdmi_reg_writev(hdata, HDMI_V_BLANK_F5_0, 2, 0xffff);
1633         hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_3_0, 2, 0xffff);
1634         hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_4_0, 2, 0xffff);
1635         hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_5_0, 2, 0xffff);
1636         hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_6_0, 2, 0xffff);
1637         hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_3_0, 2, 0xffff);
1638         hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_4_0, 2, 0xffff);
1639         hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_5_0, 2, 0xffff);
1640         hdmi_reg_writev(hdata, HDMI_V_SYNC_LINE_AFT_PXL_6_0, 2, 0xffff);
1641
1642         hdmi_reg_writev(hdata, HDMI_TG_H_FSZ_L, 2, m->htotal);
1643         hdmi_reg_writev(hdata, HDMI_TG_HACT_ST_L, 2, m->htotal - m->hdisplay);
1644         hdmi_reg_writev(hdata, HDMI_TG_HACT_SZ_L, 2, m->hdisplay);
1645         hdmi_reg_writev(hdata, HDMI_TG_V_FSZ_L, 2, m->vtotal);
1646         if (hdata->drv_data == &exynos5433_hdmi_driver_data)
1647                 hdmi_reg_writeb(hdata, HDMI_TG_DECON_EN, 1);
1648 }
1649
1650 static void hdmi_mode_apply(struct hdmi_context *hdata)
1651 {
1652         if (hdata->drv_data->type == HDMI_TYPE13)
1653                 hdmi_v13_mode_apply(hdata);
1654         else
1655                 hdmi_v14_mode_apply(hdata);
1656
1657         hdmiphy_wait_for_pll(hdata);
1658         hdmi_clk_set_parents(hdata, true);
1659         hdmi_start(hdata, true);
1660 }
1661
1662 static void hdmiphy_conf_reset(struct hdmi_context *hdata)
1663 {
1664         hdmi_clk_set_parents(hdata, false);
1665
1666         hdmi_reg_writemask(hdata, HDMI_PHY_RSTOUT, ~0, HDMI_PHY_SW_RSTOUT);
1667         usleep_range(10000, 12000);
1668         hdmi_reg_writemask(hdata, HDMI_PHY_RSTOUT, 0, HDMI_PHY_SW_RSTOUT);
1669         usleep_range(10000, 12000);
1670 }
1671
1672 static void hdmiphy_enable_mode_set(struct hdmi_context *hdata, bool enable)
1673 {
1674         u8 v = enable ? HDMI_PHY_ENABLE_MODE_SET : HDMI_PHY_DISABLE_MODE_SET;
1675
1676         if (hdata->drv_data == &exynos5433_hdmi_driver_data)
1677                 writel(v, hdata->regs_hdmiphy + HDMIPHY5433_MODE_SET_DONE);
1678 }
1679
1680 static void hdmiphy_conf_apply(struct hdmi_context *hdata)
1681 {
1682         int ret;
1683         int i;
1684
1685         i = hdmi_find_phy_conf(hdata, hdata->current_mode.clock * 1000);
1686         if (i < 0) {
1687                 DRM_ERROR("failed to find hdmiphy conf\n");
1688                 return;
1689         }
1690
1691         hdmiphy_enable_mode_set(hdata, true);
1692         ret = hdmiphy_reg_write_buf(hdata, 0,
1693                         hdata->drv_data->phy_confs.data[i].conf, 32);
1694         if (ret) {
1695                 DRM_ERROR("failed to configure hdmiphy\n");
1696                 return;
1697         }
1698         hdmiphy_enable_mode_set(hdata, false);
1699
1700         usleep_range(10000, 12000);
1701 }
1702
1703 static void hdmi_conf_apply(struct hdmi_context *hdata)
1704 {
1705         hdmiphy_conf_reset(hdata);
1706         hdmiphy_conf_apply(hdata);
1707         hdmi_start(hdata, false);
1708         hdmi_conf_init(hdata);
1709         hdmi_audio_init(hdata);
1710         hdmi_mode_apply(hdata);
1711         hdmi_audio_control(hdata, true);
1712         hdmi_regs_dump(hdata, "start");
1713 }
1714
1715 static void hdmi_mode_set(struct drm_encoder *encoder,
1716                           struct drm_display_mode *mode,
1717                           struct drm_display_mode *adjusted_mode)
1718 {
1719         struct hdmi_context *hdata = encoder_to_hdmi(encoder);
1720         struct drm_display_mode *m = adjusted_mode;
1721
1722         DRM_DEBUG_KMS("xres=%d, yres=%d, refresh=%d, intl=%s\n",
1723                 m->hdisplay, m->vdisplay,
1724                 m->vrefresh, (m->flags & DRM_MODE_FLAG_INTERLACE) ?
1725                 "INTERLACED" : "PROGRESSIVE");
1726
1727         drm_mode_copy(&hdata->current_mode, m);
1728         hdata->cea_video_id = drm_match_cea_mode(mode);
1729 }
1730
1731 static void hdmi_set_refclk(struct hdmi_context *hdata, bool on)
1732 {
1733         if (!hdata->sysreg)
1734                 return;
1735
1736         regmap_update_bits(hdata->sysreg, EXYNOS5433_SYSREG_DISP_HDMI_PHY,
1737                            SYSREG_HDMI_REFCLK_INT_CLK, on ? ~0 : 0);
1738 }
1739
1740 static void hdmi_enable(struct drm_encoder *encoder)
1741 {
1742         struct hdmi_context *hdata = encoder_to_hdmi(encoder);
1743
1744         if (hdata->powered)
1745                 return;
1746
1747         pm_runtime_get_sync(hdata->dev);
1748
1749         if (regulator_bulk_enable(ARRAY_SIZE(supply), hdata->regul_bulk))
1750                 DRM_DEBUG_KMS("failed to enable regulator bulk\n");
1751
1752         regmap_update_bits(hdata->pmureg, PMU_HDMI_PHY_CONTROL,
1753                         PMU_HDMI_PHY_ENABLE_BIT, 1);
1754
1755         hdmi_set_refclk(hdata, true);
1756
1757         hdmi_conf_apply(hdata);
1758
1759         hdata->powered = true;
1760 }
1761
1762 static void hdmi_disable(struct drm_encoder *encoder)
1763 {
1764         struct hdmi_context *hdata = encoder_to_hdmi(encoder);
1765         struct drm_crtc *crtc = encoder->crtc;
1766         const struct drm_crtc_helper_funcs *funcs = NULL;
1767
1768         if (!hdata->powered)
1769                 return;
1770
1771         /*
1772          * The SFRs of VP and Mixer are updated by Vertical Sync of
1773          * Timing generator which is a part of HDMI so the sequence
1774          * to disable TV Subsystem should be as following,
1775          *      VP -> Mixer -> HDMI
1776          *
1777          * Below codes will try to disable Mixer and VP(if used)
1778          * prior to disabling HDMI.
1779          */
1780         if (crtc)
1781                 funcs = crtc->helper_private;
1782         if (funcs && funcs->disable)
1783                 (*funcs->disable)(crtc);
1784
1785         hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_EN);
1786
1787         cancel_delayed_work(&hdata->hotplug_work);
1788
1789         hdmi_set_refclk(hdata, false);
1790
1791         regmap_update_bits(hdata->pmureg, PMU_HDMI_PHY_CONTROL,
1792                         PMU_HDMI_PHY_ENABLE_BIT, 0);
1793
1794         regulator_bulk_disable(ARRAY_SIZE(supply), hdata->regul_bulk);
1795
1796         pm_runtime_put_sync(hdata->dev);
1797
1798         hdata->powered = false;
1799 }
1800
1801 static const struct drm_encoder_helper_funcs exynos_hdmi_encoder_helper_funcs = {
1802         .mode_fixup     = hdmi_mode_fixup,
1803         .mode_set       = hdmi_mode_set,
1804         .enable         = hdmi_enable,
1805         .disable        = hdmi_disable,
1806 };
1807
1808 static const struct drm_encoder_funcs exynos_hdmi_encoder_funcs = {
1809         .destroy = drm_encoder_cleanup,
1810 };
1811
1812 static void hdmi_hotplug_work_func(struct work_struct *work)
1813 {
1814         struct hdmi_context *hdata;
1815
1816         hdata = container_of(work, struct hdmi_context, hotplug_work.work);
1817
1818         if (hdata->drm_dev)
1819                 drm_helper_hpd_irq_event(hdata->drm_dev);
1820 }
1821
1822 static irqreturn_t hdmi_irq_thread(int irq, void *arg)
1823 {
1824         struct hdmi_context *hdata = arg;
1825
1826         mod_delayed_work(system_wq, &hdata->hotplug_work,
1827                         msecs_to_jiffies(HOTPLUG_DEBOUNCE_MS));
1828
1829         return IRQ_HANDLED;
1830 }
1831
1832 static int hdmi_clks_get(struct hdmi_context *hdata,
1833                          const struct string_array_spec *names,
1834                          struct clk **clks)
1835 {
1836         struct device *dev = hdata->dev;
1837         int i;
1838
1839         for (i = 0; i < names->count; ++i) {
1840                 struct clk *clk = devm_clk_get(dev, names->data[i]);
1841
1842                 if (IS_ERR(clk)) {
1843                         int ret = PTR_ERR(clk);
1844
1845                         dev_err(dev, "Cannot get clock %s, %d\n",
1846                                 names->data[i], ret);
1847
1848                         return ret;
1849                 }
1850
1851                 clks[i] = clk;
1852         }
1853
1854         return 0;
1855 }
1856
1857 static int hdmi_clk_init(struct hdmi_context *hdata)
1858 {
1859         const struct hdmi_driver_data *drv_data = hdata->drv_data;
1860         int count = drv_data->clk_gates.count + drv_data->clk_muxes.count;
1861         struct device *dev = hdata->dev;
1862         struct clk **clks;
1863         int ret;
1864
1865         if (!count)
1866                 return 0;
1867
1868         clks = devm_kzalloc(dev, sizeof(*clks) * count, GFP_KERNEL);
1869         if (!clks)
1870         return -ENOMEM;
1871
1872         hdata->clk_gates = clks;
1873         hdata->clk_muxes = clks + drv_data->clk_gates.count;
1874
1875         ret = hdmi_clks_get(hdata, &drv_data->clk_gates, hdata->clk_gates);
1876         if (ret)
1877                 return ret;
1878
1879         return hdmi_clks_get(hdata, &drv_data->clk_muxes, hdata->clk_muxes);
1880 }
1881
1882
1883 static int hdmi_resources_init(struct hdmi_context *hdata)
1884 {
1885         struct device *dev = hdata->dev;
1886         int i, ret;
1887
1888         DRM_DEBUG_KMS("HDMI resource init\n");
1889
1890         hdata->hpd_gpio = devm_gpiod_get(dev, "hpd", GPIOD_IN);
1891         if (IS_ERR(hdata->hpd_gpio)) {
1892                 DRM_ERROR("cannot get hpd gpio property\n");
1893                 return PTR_ERR(hdata->hpd_gpio);
1894         }
1895
1896         hdata->irq = gpiod_to_irq(hdata->hpd_gpio);
1897         if (hdata->irq < 0) {
1898                 DRM_ERROR("failed to get GPIO irq\n");
1899                 return  hdata->irq;
1900         }
1901
1902         ret = hdmi_clk_init(hdata);
1903         if (ret)
1904                 return ret;
1905
1906         ret = hdmi_clk_set_parents(hdata, false);
1907         if (ret)
1908                 return ret;
1909
1910         for (i = 0; i < ARRAY_SIZE(supply); ++i) {
1911                 hdata->regul_bulk[i].supply = supply[i];
1912                 hdata->regul_bulk[i].consumer = NULL;
1913         }
1914         ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(supply), hdata->regul_bulk);
1915         if (ret) {
1916                 DRM_ERROR("failed to get regulators\n");
1917                 return ret;
1918         }
1919
1920         hdata->reg_hdmi_en = devm_regulator_get_optional(dev, "hdmi-en");
1921
1922         if (PTR_ERR(hdata->reg_hdmi_en) == -ENODEV)
1923                 return 0;
1924
1925         if (IS_ERR(hdata->reg_hdmi_en))
1926                 return PTR_ERR(hdata->reg_hdmi_en);
1927
1928         ret = regulator_enable(hdata->reg_hdmi_en);
1929         if (ret)
1930                 DRM_ERROR("failed to enable hdmi-en regulator\n");
1931
1932         return ret;
1933 }
1934
1935 static struct of_device_id hdmi_match_types[] = {
1936         {
1937                 .compatible = "samsung,exynos4210-hdmi",
1938                 .data = &exynos4210_hdmi_driver_data,
1939         }, {
1940                 .compatible = "samsung,exynos4212-hdmi",
1941                 .data = &exynos4212_hdmi_driver_data,
1942         }, {
1943                 .compatible = "samsung,exynos5420-hdmi",
1944                 .data = &exynos5420_hdmi_driver_data,
1945         }, {
1946                 .compatible = "samsung,exynos5433-hdmi",
1947                 .data = &exynos5433_hdmi_driver_data,
1948         }, {
1949                 /* end node */
1950         }
1951 };
1952 MODULE_DEVICE_TABLE (of, hdmi_match_types);
1953
1954 static int hdmi_bind(struct device *dev, struct device *master, void *data)
1955 {
1956         struct drm_device *drm_dev = data;
1957         struct hdmi_context *hdata = dev_get_drvdata(dev);
1958         struct drm_encoder *encoder = &hdata->encoder;
1959         int ret, pipe;
1960
1961         hdata->drm_dev = drm_dev;
1962
1963         pipe = exynos_drm_crtc_get_pipe_from_type(drm_dev,
1964                                                   EXYNOS_DISPLAY_TYPE_HDMI);
1965         if (pipe < 0)
1966                 return pipe;
1967
1968         encoder->possible_crtcs = 1 << pipe;
1969
1970         DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
1971
1972         drm_encoder_init(drm_dev, encoder, &exynos_hdmi_encoder_funcs,
1973                          DRM_MODE_ENCODER_TMDS, NULL);
1974
1975         drm_encoder_helper_add(encoder, &exynos_hdmi_encoder_helper_funcs);
1976
1977         ret = hdmi_create_connector(encoder);
1978         if (ret) {
1979                 DRM_ERROR("failed to create connector ret = %d\n", ret);
1980                 drm_encoder_cleanup(encoder);
1981                 return ret;
1982         }
1983
1984         return 0;
1985 }
1986
1987 static void hdmi_unbind(struct device *dev, struct device *master, void *data)
1988 {
1989 }
1990
1991 static const struct component_ops hdmi_component_ops = {
1992         .bind   = hdmi_bind,
1993         .unbind = hdmi_unbind,
1994 };
1995
1996 static struct device_node *hdmi_legacy_ddc_dt_binding(struct device *dev)
1997 {
1998         const char *compatible_str = "samsung,exynos4210-hdmiddc";
1999         struct device_node *np;
2000
2001         np = of_find_compatible_node(NULL, NULL, compatible_str);
2002         if (np)
2003                 return of_get_next_parent(np);
2004
2005         return NULL;
2006 }
2007
2008 static struct device_node *hdmi_legacy_phy_dt_binding(struct device *dev)
2009 {
2010         const char *compatible_str = "samsung,exynos4212-hdmiphy";
2011
2012         return of_find_compatible_node(NULL, NULL, compatible_str);
2013 }
2014
2015 static int hdmi_probe(struct platform_device *pdev)
2016 {
2017         struct device_node *ddc_node, *phy_node;
2018         const struct of_device_id *match;
2019         struct device *dev = &pdev->dev;
2020         struct hdmi_context *hdata;
2021         struct resource *res;
2022         int ret;
2023
2024         hdata = devm_kzalloc(dev, sizeof(struct hdmi_context), GFP_KERNEL);
2025         if (!hdata)
2026                 return -ENOMEM;
2027
2028         match = of_match_device(hdmi_match_types, dev);
2029         if (!match)
2030                 return -ENODEV;
2031
2032         hdata->drv_data = match->data;
2033
2034         platform_set_drvdata(pdev, hdata);
2035
2036         hdata->dev = dev;
2037
2038         ret = hdmi_resources_init(hdata);
2039         if (ret) {
2040                 DRM_ERROR("hdmi_resources_init failed\n");
2041                 return ret;
2042         }
2043
2044         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2045         hdata->regs = devm_ioremap_resource(dev, res);
2046         if (IS_ERR(hdata->regs)) {
2047                 ret = PTR_ERR(hdata->regs);
2048                 return ret;
2049         }
2050
2051         ddc_node = hdmi_legacy_ddc_dt_binding(dev);
2052         if (ddc_node)
2053                 goto out_get_ddc_adpt;
2054
2055         ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
2056         if (!ddc_node) {
2057                 DRM_ERROR("Failed to find ddc node in device tree\n");
2058                 return -ENODEV;
2059         }
2060
2061 out_get_ddc_adpt:
2062         hdata->ddc_adpt = of_find_i2c_adapter_by_node(ddc_node);
2063         if (!hdata->ddc_adpt) {
2064                 DRM_ERROR("Failed to get ddc i2c adapter by node\n");
2065                 return -EPROBE_DEFER;
2066         }
2067
2068         phy_node = hdmi_legacy_phy_dt_binding(dev);
2069         if (phy_node)
2070                 goto out_get_phy_port;
2071
2072         phy_node = of_parse_phandle(dev->of_node, "phy", 0);
2073         if (!phy_node) {
2074                 DRM_ERROR("Failed to find hdmiphy node in device tree\n");
2075                 ret = -ENODEV;
2076                 goto err_ddc;
2077         }
2078
2079 out_get_phy_port:
2080         if (hdata->drv_data->is_apb_phy) {
2081                 hdata->regs_hdmiphy = of_iomap(phy_node, 0);
2082                 if (!hdata->regs_hdmiphy) {
2083                         DRM_ERROR("failed to ioremap hdmi phy\n");
2084                         ret = -ENOMEM;
2085                         goto err_ddc;
2086                 }
2087         } else {
2088                 hdata->hdmiphy_port = of_find_i2c_device_by_node(phy_node);
2089                 if (!hdata->hdmiphy_port) {
2090                         DRM_ERROR("Failed to get hdmi phy i2c client\n");
2091                         ret = -EPROBE_DEFER;
2092                         goto err_ddc;
2093                 }
2094         }
2095
2096         INIT_DELAYED_WORK(&hdata->hotplug_work, hdmi_hotplug_work_func);
2097
2098         ret = devm_request_threaded_irq(dev, hdata->irq, NULL,
2099                         hdmi_irq_thread, IRQF_TRIGGER_RISING |
2100                         IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
2101                         "hdmi", hdata);
2102         if (ret) {
2103                 DRM_ERROR("failed to register hdmi interrupt\n");
2104                 goto err_hdmiphy;
2105         }
2106
2107         hdata->pmureg = syscon_regmap_lookup_by_phandle(dev->of_node,
2108                         "samsung,syscon-phandle");
2109         if (IS_ERR(hdata->pmureg)) {
2110                 DRM_ERROR("syscon regmap lookup failed.\n");
2111                 ret = -EPROBE_DEFER;
2112                 goto err_hdmiphy;
2113         }
2114
2115         if (hdata->drv_data->has_sysreg) {
2116                 hdata->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
2117                                 "samsung,sysreg-phandle");
2118                 if (IS_ERR(hdata->sysreg)) {
2119                         DRM_ERROR("sysreg regmap lookup failed.\n");
2120                         ret = -EPROBE_DEFER;
2121                         goto err_hdmiphy;
2122                 }
2123         }
2124
2125         pm_runtime_enable(dev);
2126
2127         ret = component_add(&pdev->dev, &hdmi_component_ops);
2128         if (ret)
2129                 goto err_disable_pm_runtime;
2130
2131         return ret;
2132
2133 err_disable_pm_runtime:
2134         pm_runtime_disable(dev);
2135
2136 err_hdmiphy:
2137         if (hdata->hdmiphy_port)
2138                 put_device(&hdata->hdmiphy_port->dev);
2139 err_ddc:
2140         put_device(&hdata->ddc_adpt->dev);
2141
2142         return ret;
2143 }
2144
2145 static int hdmi_remove(struct platform_device *pdev)
2146 {
2147         struct hdmi_context *hdata = platform_get_drvdata(pdev);
2148
2149         cancel_delayed_work_sync(&hdata->hotplug_work);
2150
2151         component_del(&pdev->dev, &hdmi_component_ops);
2152
2153         pm_runtime_disable(&pdev->dev);
2154
2155         if (!IS_ERR(hdata->reg_hdmi_en))
2156                 regulator_disable(hdata->reg_hdmi_en);
2157
2158         if (hdata->hdmiphy_port)
2159                 put_device(&hdata->hdmiphy_port->dev);
2160
2161         put_device(&hdata->ddc_adpt->dev);
2162
2163         return 0;
2164 }
2165
2166 #ifdef CONFIG_PM
2167 static int exynos_hdmi_suspend(struct device *dev)
2168 {
2169         struct hdmi_context *hdata = dev_get_drvdata(dev);
2170
2171         hdmi_clk_disable_gates(hdata);
2172
2173         return 0;
2174 }
2175
2176 static int exynos_hdmi_resume(struct device *dev)
2177 {
2178         struct hdmi_context *hdata = dev_get_drvdata(dev);
2179         int ret;
2180
2181         ret = hdmi_clk_enable_gates(hdata);
2182         if (ret < 0)
2183                 return ret;
2184
2185         return 0;
2186 }
2187 #endif
2188
2189 static const struct dev_pm_ops exynos_hdmi_pm_ops = {
2190         SET_RUNTIME_PM_OPS(exynos_hdmi_suspend, exynos_hdmi_resume, NULL)
2191 };
2192
2193 struct platform_driver hdmi_driver = {
2194         .probe          = hdmi_probe,
2195         .remove         = hdmi_remove,
2196         .driver         = {
2197                 .name   = "exynos-hdmi",
2198                 .owner  = THIS_MODULE,
2199                 .pm     = &exynos_hdmi_pm_ops,
2200                 .of_match_table = hdmi_match_types,
2201         },
2202 };