2 * Copyright (C) 2011 Samsung Electronics Co.Ltd
4 * Seung-Woo Kim <sw0312.kim@samsung.com>
5 * Inki Dae <inki.dae@samsung.com>
6 * Joonyoung Shim <jy0922.shim@samsung.com>
8 * Based on drivers/media/video/s5p-tv/hdmi_drv.c
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
18 #include <drm/drm_edid.h>
19 #include <drm/drm_crtc_helper.h>
21 #include "regs-hdmi.h"
23 #include <linux/kernel.h>
24 #include <linux/spinlock.h>
25 #include <linux/wait.h>
26 #include <linux/i2c.h>
27 #include <linux/platform_device.h>
28 #include <linux/interrupt.h>
29 #include <linux/irq.h>
30 #include <linux/delay.h>
31 #include <linux/pm_runtime.h>
32 #include <linux/clk.h>
33 #include <linux/regulator/consumer.h>
36 #include <linux/i2c.h>
37 #include <linux/of_gpio.h>
38 #include <linux/hdmi.h>
40 #include <drm/exynos_drm.h>
42 #include "exynos_drm_drv.h"
43 #include "exynos_mixer.h"
45 #include <linux/gpio.h>
46 #include <media/s5p_hdmi.h>
48 #define get_hdmi_display(dev) platform_get_drvdata(to_platform_device(dev))
49 #define ctx_from_connector(c) container_of(c, struct hdmi_context, connector)
51 /* AVI header and aspect ratio */
52 #define HDMI_AVI_VERSION 0x02
53 #define HDMI_AVI_LENGTH 0x0D
56 #define HDMI_AUI_VERSION 0x01
57 #define HDMI_AUI_LENGTH 0x0A
58 #define AVI_SAME_AS_PIC_ASPECT_RATIO 0x8
59 #define AVI_4_3_CENTER_RATIO 0x9
60 #define AVI_16_9_CENTER_RATIO 0xa
67 struct hdmi_driver_data {
69 unsigned int is_apb_phy:1;
72 struct hdmi_resources {
74 struct clk *sclk_hdmi;
75 struct clk *sclk_pixel;
76 struct clk *sclk_hdmiphy;
78 struct clk *mout_hdmi;
79 struct regulator_bulk_data *regul_bulk;
100 u8 field_bot_hdmi[2];
104 struct hdmi_v13_core_regs {
117 struct hdmi_v14_core_regs {
130 u8 v_sync_line_bef_2[2];
131 u8 v_sync_line_bef_1[2];
132 u8 v_sync_line_aft_2[2];
133 u8 v_sync_line_aft_1[2];
134 u8 v_sync_line_aft_pxl_2[2];
135 u8 v_sync_line_aft_pxl_1[2];
136 u8 v_blank_f2[2]; /* for 3D mode */
137 u8 v_blank_f3[2]; /* for 3D mode */
138 u8 v_blank_f4[2]; /* for 3D mode */
139 u8 v_blank_f5[2]; /* for 3D mode */
140 u8 v_sync_line_aft_3[2];
141 u8 v_sync_line_aft_4[2];
142 u8 v_sync_line_aft_5[2];
143 u8 v_sync_line_aft_6[2];
144 u8 v_sync_line_aft_pxl_3[2];
145 u8 v_sync_line_aft_pxl_4[2];
146 u8 v_sync_line_aft_pxl_5[2];
147 u8 v_sync_line_aft_pxl_6[2];
156 struct hdmi_v13_conf {
157 struct hdmi_v13_core_regs core;
158 struct hdmi_tg_regs tg;
161 struct hdmi_v14_conf {
162 struct hdmi_v14_core_regs core;
163 struct hdmi_tg_regs tg;
166 struct hdmi_conf_regs {
169 enum hdmi_picture_aspect aspect_ratio;
171 struct hdmi_v13_conf v13_conf;
172 struct hdmi_v14_conf v14_conf;
176 struct hdmi_context {
178 struct drm_device *drm_dev;
179 struct drm_connector connector;
180 struct drm_encoder *encoder;
184 struct mutex hdmi_mutex;
189 struct i2c_adapter *ddc_adpt;
190 struct i2c_client *hdmiphy_port;
192 /* current hdmiphy conf regs */
193 struct hdmi_conf_regs mode_conf;
195 struct hdmi_resources res;
202 struct hdmiphy_config {
207 struct hdmi_driver_data exynos4212_hdmi_driver_data = {
211 struct hdmi_driver_data exynos5_hdmi_driver_data = {
215 /* list of phy config settings */
216 static const struct hdmiphy_config hdmiphy_v13_configs[] = {
218 .pixel_clock = 27000000,
220 0x01, 0x05, 0x00, 0xD8, 0x10, 0x1C, 0x30, 0x40,
221 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
222 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
223 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00,
227 .pixel_clock = 27027000,
229 0x01, 0x05, 0x00, 0xD4, 0x10, 0x9C, 0x09, 0x64,
230 0x6B, 0x10, 0x02, 0x51, 0xDF, 0xF2, 0x54, 0x87,
231 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
232 0x22, 0x40, 0xE3, 0x26, 0x00, 0x00, 0x00, 0x00,
236 .pixel_clock = 74176000,
238 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xef, 0x5B,
239 0x6D, 0x10, 0x01, 0x51, 0xef, 0xF3, 0x54, 0xb9,
240 0x84, 0x00, 0x30, 0x38, 0x00, 0x08, 0x10, 0xE0,
241 0x22, 0x40, 0xa5, 0x26, 0x01, 0x00, 0x00, 0x00,
245 .pixel_clock = 74250000,
247 0x01, 0x05, 0x00, 0xd8, 0x10, 0x9c, 0xf8, 0x40,
248 0x6a, 0x10, 0x01, 0x51, 0xff, 0xf1, 0x54, 0xba,
249 0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xe0,
250 0x22, 0x40, 0xa4, 0x26, 0x01, 0x00, 0x00, 0x00,
254 .pixel_clock = 148500000,
256 0x01, 0x05, 0x00, 0xD8, 0x10, 0x9C, 0xf8, 0x40,
257 0x6A, 0x18, 0x00, 0x51, 0xff, 0xF1, 0x54, 0xba,
258 0x84, 0x00, 0x10, 0x38, 0x00, 0x08, 0x10, 0xE0,
259 0x22, 0x40, 0xa4, 0x26, 0x02, 0x00, 0x00, 0x00,
264 static const struct hdmiphy_config hdmiphy_v14_configs[] = {
266 .pixel_clock = 25200000,
268 0x01, 0x51, 0x2A, 0x75, 0x40, 0x01, 0x00, 0x08,
269 0x82, 0x80, 0xfc, 0xd8, 0x45, 0xa0, 0xac, 0x80,
270 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
271 0x54, 0xf4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
275 .pixel_clock = 27000000,
277 0x01, 0xd1, 0x22, 0x51, 0x40, 0x08, 0xfc, 0x20,
278 0x98, 0xa0, 0xcb, 0xd8, 0x45, 0xa0, 0xac, 0x80,
279 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
280 0x54, 0xe4, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
284 .pixel_clock = 27027000,
286 0x01, 0xd1, 0x2d, 0x72, 0x40, 0x64, 0x12, 0x08,
287 0x43, 0xa0, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
288 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
289 0x54, 0xe3, 0x24, 0x00, 0x00, 0x00, 0x01, 0x00,
293 .pixel_clock = 36000000,
295 0x01, 0x51, 0x2d, 0x55, 0x40, 0x01, 0x00, 0x08,
296 0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
297 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
298 0x54, 0xab, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
302 .pixel_clock = 40000000,
304 0x01, 0x51, 0x32, 0x55, 0x40, 0x01, 0x00, 0x08,
305 0x82, 0x80, 0x2c, 0xd9, 0x45, 0xa0, 0xac, 0x80,
306 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
307 0x54, 0x9a, 0x24, 0x00, 0x00, 0x00, 0x01, 0x80,
311 .pixel_clock = 65000000,
313 0x01, 0xd1, 0x36, 0x34, 0x40, 0x1e, 0x0a, 0x08,
314 0x82, 0xa0, 0x45, 0xd9, 0x45, 0xa0, 0xac, 0x80,
315 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
316 0x54, 0xbd, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
320 .pixel_clock = 71000000,
322 0x01, 0x91, 0x1e, 0x15, 0x40, 0x3c, 0xce, 0x08,
323 0x04, 0x20, 0xb2, 0xd8, 0x45, 0xa0, 0xac, 0x80,
324 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
325 0x54, 0xad, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
329 .pixel_clock = 73250000,
331 0x01, 0xd1, 0x1f, 0x15, 0x40, 0x18, 0xe9, 0x08,
332 0x02, 0xa0, 0xb7, 0xd8, 0x45, 0xa0, 0xac, 0x80,
333 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
334 0x54, 0xa8, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
338 .pixel_clock = 74176000,
340 0x01, 0xd1, 0x3e, 0x35, 0x40, 0x5b, 0xde, 0x08,
341 0x82, 0xa0, 0x73, 0xd9, 0x45, 0xa0, 0xac, 0x80,
342 0x56, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
343 0x54, 0xa6, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
347 .pixel_clock = 74250000,
349 0x01, 0xd1, 0x1f, 0x10, 0x40, 0x40, 0xf8, 0x08,
350 0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,
351 0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
352 0x54, 0xa5, 0x24, 0x01, 0x00, 0x00, 0x01, 0x00,
356 .pixel_clock = 83500000,
358 0x01, 0xd1, 0x23, 0x11, 0x40, 0x0c, 0xfb, 0x08,
359 0x85, 0xa0, 0xd1, 0xd8, 0x45, 0xa0, 0xac, 0x80,
360 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
361 0x54, 0x93, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
365 .pixel_clock = 88750000,
367 0x01, 0x91, 0x25, 0x17, 0x40, 0x30, 0xfe, 0x08,
368 0x06, 0x20, 0xde, 0xd8, 0x45, 0xa0, 0xac, 0x80,
369 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
370 0x54, 0x8a, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
374 .pixel_clock = 106500000,
376 0x01, 0xd1, 0x2c, 0x12, 0x40, 0x0c, 0x09, 0x08,
377 0x84, 0xa0, 0x0a, 0xd9, 0x45, 0xa0, 0xac, 0x80,
378 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
379 0x54, 0x73, 0x24, 0x01, 0x00, 0x00, 0x01, 0x80,
383 .pixel_clock = 108000000,
385 0x01, 0x51, 0x2d, 0x15, 0x40, 0x01, 0x00, 0x08,
386 0x82, 0x80, 0x0e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
387 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
388 0x54, 0xc7, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
392 .pixel_clock = 115500000,
394 0x01, 0xd1, 0x30, 0x1a, 0x40, 0x40, 0x10, 0x04,
395 0x04, 0xa0, 0x21, 0xd9, 0x45, 0xa0, 0xac, 0x80,
396 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
397 0x54, 0xaa, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
401 .pixel_clock = 119000000,
403 0x01, 0x91, 0x32, 0x14, 0x40, 0x60, 0xd8, 0x08,
404 0x06, 0x20, 0x2a, 0xd9, 0x45, 0xa0, 0xac, 0x80,
405 0x06, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
406 0x54, 0x9d, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
410 .pixel_clock = 146250000,
412 0x01, 0xd1, 0x3d, 0x15, 0x40, 0x18, 0xfd, 0x08,
413 0x83, 0xa0, 0x6e, 0xd9, 0x45, 0xa0, 0xac, 0x80,
414 0x08, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
415 0x54, 0x50, 0x25, 0x03, 0x00, 0x00, 0x01, 0x80,
419 .pixel_clock = 148500000,
421 0x01, 0xd1, 0x1f, 0x00, 0x40, 0x40, 0xf8, 0x08,
422 0x81, 0xa0, 0xba, 0xd8, 0x45, 0xa0, 0xac, 0x80,
423 0x3c, 0x80, 0x11, 0x04, 0x02, 0x22, 0x44, 0x86,
424 0x54, 0x4b, 0x25, 0x03, 0x00, 0x00, 0x01, 0x00,
429 static inline u32 hdmi_reg_read(struct hdmi_context *hdata, u32 reg_id)
431 return readl(hdata->regs + reg_id);
434 static inline void hdmi_reg_writeb(struct hdmi_context *hdata,
435 u32 reg_id, u8 value)
437 writeb(value, hdata->regs + reg_id);
440 static inline void hdmi_reg_writemask(struct hdmi_context *hdata,
441 u32 reg_id, u32 value, u32 mask)
443 u32 old = readl(hdata->regs + reg_id);
444 value = (value & mask) | (old & ~mask);
445 writel(value, hdata->regs + reg_id);
448 static void hdmi_v13_regs_dump(struct hdmi_context *hdata, char *prefix)
450 #define DUMPREG(reg_id) \
451 DRM_DEBUG_KMS("%s:" #reg_id " = %08x\n", prefix, \
452 readl(hdata->regs + reg_id))
453 DRM_DEBUG_KMS("%s: ---- CONTROL REGISTERS ----\n", prefix);
454 DUMPREG(HDMI_INTC_FLAG);
455 DUMPREG(HDMI_INTC_CON);
456 DUMPREG(HDMI_HPD_STATUS);
457 DUMPREG(HDMI_V13_PHY_RSTOUT);
458 DUMPREG(HDMI_V13_PHY_VPLL);
459 DUMPREG(HDMI_V13_PHY_CMU);
460 DUMPREG(HDMI_V13_CORE_RSTOUT);
462 DRM_DEBUG_KMS("%s: ---- CORE REGISTERS ----\n", prefix);
466 DUMPREG(HDMI_SYS_STATUS);
467 DUMPREG(HDMI_V13_PHY_STATUS);
468 DUMPREG(HDMI_STATUS_EN);
470 DUMPREG(HDMI_MODE_SEL);
471 DUMPREG(HDMI_V13_HPD_GEN);
472 DUMPREG(HDMI_V13_DC_CONTROL);
473 DUMPREG(HDMI_V13_VIDEO_PATTERN_GEN);
475 DRM_DEBUG_KMS("%s: ---- CORE SYNC REGISTERS ----\n", prefix);
476 DUMPREG(HDMI_H_BLANK_0);
477 DUMPREG(HDMI_H_BLANK_1);
478 DUMPREG(HDMI_V13_V_BLANK_0);
479 DUMPREG(HDMI_V13_V_BLANK_1);
480 DUMPREG(HDMI_V13_V_BLANK_2);
481 DUMPREG(HDMI_V13_H_V_LINE_0);
482 DUMPREG(HDMI_V13_H_V_LINE_1);
483 DUMPREG(HDMI_V13_H_V_LINE_2);
484 DUMPREG(HDMI_VSYNC_POL);
485 DUMPREG(HDMI_INT_PRO_MODE);
486 DUMPREG(HDMI_V13_V_BLANK_F_0);
487 DUMPREG(HDMI_V13_V_BLANK_F_1);
488 DUMPREG(HDMI_V13_V_BLANK_F_2);
489 DUMPREG(HDMI_V13_H_SYNC_GEN_0);
490 DUMPREG(HDMI_V13_H_SYNC_GEN_1);
491 DUMPREG(HDMI_V13_H_SYNC_GEN_2);
492 DUMPREG(HDMI_V13_V_SYNC_GEN_1_0);
493 DUMPREG(HDMI_V13_V_SYNC_GEN_1_1);
494 DUMPREG(HDMI_V13_V_SYNC_GEN_1_2);
495 DUMPREG(HDMI_V13_V_SYNC_GEN_2_0);
496 DUMPREG(HDMI_V13_V_SYNC_GEN_2_1);
497 DUMPREG(HDMI_V13_V_SYNC_GEN_2_2);
498 DUMPREG(HDMI_V13_V_SYNC_GEN_3_0);
499 DUMPREG(HDMI_V13_V_SYNC_GEN_3_1);
500 DUMPREG(HDMI_V13_V_SYNC_GEN_3_2);
502 DRM_DEBUG_KMS("%s: ---- TG REGISTERS ----\n", prefix);
503 DUMPREG(HDMI_TG_CMD);
504 DUMPREG(HDMI_TG_H_FSZ_L);
505 DUMPREG(HDMI_TG_H_FSZ_H);
506 DUMPREG(HDMI_TG_HACT_ST_L);
507 DUMPREG(HDMI_TG_HACT_ST_H);
508 DUMPREG(HDMI_TG_HACT_SZ_L);
509 DUMPREG(HDMI_TG_HACT_SZ_H);
510 DUMPREG(HDMI_TG_V_FSZ_L);
511 DUMPREG(HDMI_TG_V_FSZ_H);
512 DUMPREG(HDMI_TG_VSYNC_L);
513 DUMPREG(HDMI_TG_VSYNC_H);
514 DUMPREG(HDMI_TG_VSYNC2_L);
515 DUMPREG(HDMI_TG_VSYNC2_H);
516 DUMPREG(HDMI_TG_VACT_ST_L);
517 DUMPREG(HDMI_TG_VACT_ST_H);
518 DUMPREG(HDMI_TG_VACT_SZ_L);
519 DUMPREG(HDMI_TG_VACT_SZ_H);
520 DUMPREG(HDMI_TG_FIELD_CHG_L);
521 DUMPREG(HDMI_TG_FIELD_CHG_H);
522 DUMPREG(HDMI_TG_VACT_ST2_L);
523 DUMPREG(HDMI_TG_VACT_ST2_H);
524 DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_L);
525 DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_H);
526 DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_L);
527 DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_H);
528 DUMPREG(HDMI_TG_FIELD_TOP_HDMI_L);
529 DUMPREG(HDMI_TG_FIELD_TOP_HDMI_H);
530 DUMPREG(HDMI_TG_FIELD_BOT_HDMI_L);
531 DUMPREG(HDMI_TG_FIELD_BOT_HDMI_H);
535 static void hdmi_v14_regs_dump(struct hdmi_context *hdata, char *prefix)
539 #define DUMPREG(reg_id) \
540 DRM_DEBUG_KMS("%s:" #reg_id " = %08x\n", prefix, \
541 readl(hdata->regs + reg_id))
543 DRM_DEBUG_KMS("%s: ---- CONTROL REGISTERS ----\n", prefix);
544 DUMPREG(HDMI_INTC_CON);
545 DUMPREG(HDMI_INTC_FLAG);
546 DUMPREG(HDMI_HPD_STATUS);
547 DUMPREG(HDMI_INTC_CON_1);
548 DUMPREG(HDMI_INTC_FLAG_1);
549 DUMPREG(HDMI_PHY_STATUS_0);
550 DUMPREG(HDMI_PHY_STATUS_PLL);
551 DUMPREG(HDMI_PHY_CON_0);
552 DUMPREG(HDMI_PHY_RSTOUT);
553 DUMPREG(HDMI_PHY_VPLL);
554 DUMPREG(HDMI_PHY_CMU);
555 DUMPREG(HDMI_CORE_RSTOUT);
557 DRM_DEBUG_KMS("%s: ---- CORE REGISTERS ----\n", prefix);
561 DUMPREG(HDMI_SYS_STATUS);
562 DUMPREG(HDMI_PHY_STATUS_0);
563 DUMPREG(HDMI_STATUS_EN);
565 DUMPREG(HDMI_MODE_SEL);
566 DUMPREG(HDMI_ENC_EN);
567 DUMPREG(HDMI_DC_CONTROL);
568 DUMPREG(HDMI_VIDEO_PATTERN_GEN);
570 DRM_DEBUG_KMS("%s: ---- CORE SYNC REGISTERS ----\n", prefix);
571 DUMPREG(HDMI_H_BLANK_0);
572 DUMPREG(HDMI_H_BLANK_1);
573 DUMPREG(HDMI_V2_BLANK_0);
574 DUMPREG(HDMI_V2_BLANK_1);
575 DUMPREG(HDMI_V1_BLANK_0);
576 DUMPREG(HDMI_V1_BLANK_1);
577 DUMPREG(HDMI_V_LINE_0);
578 DUMPREG(HDMI_V_LINE_1);
579 DUMPREG(HDMI_H_LINE_0);
580 DUMPREG(HDMI_H_LINE_1);
581 DUMPREG(HDMI_HSYNC_POL);
583 DUMPREG(HDMI_VSYNC_POL);
584 DUMPREG(HDMI_INT_PRO_MODE);
585 DUMPREG(HDMI_V_BLANK_F0_0);
586 DUMPREG(HDMI_V_BLANK_F0_1);
587 DUMPREG(HDMI_V_BLANK_F1_0);
588 DUMPREG(HDMI_V_BLANK_F1_1);
590 DUMPREG(HDMI_H_SYNC_START_0);
591 DUMPREG(HDMI_H_SYNC_START_1);
592 DUMPREG(HDMI_H_SYNC_END_0);
593 DUMPREG(HDMI_H_SYNC_END_1);
595 DUMPREG(HDMI_V_SYNC_LINE_BEF_2_0);
596 DUMPREG(HDMI_V_SYNC_LINE_BEF_2_1);
597 DUMPREG(HDMI_V_SYNC_LINE_BEF_1_0);
598 DUMPREG(HDMI_V_SYNC_LINE_BEF_1_1);
600 DUMPREG(HDMI_V_SYNC_LINE_AFT_2_0);
601 DUMPREG(HDMI_V_SYNC_LINE_AFT_2_1);
602 DUMPREG(HDMI_V_SYNC_LINE_AFT_1_0);
603 DUMPREG(HDMI_V_SYNC_LINE_AFT_1_1);
605 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_2_0);
606 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_2_1);
607 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_1_0);
608 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_1_1);
610 DUMPREG(HDMI_V_BLANK_F2_0);
611 DUMPREG(HDMI_V_BLANK_F2_1);
612 DUMPREG(HDMI_V_BLANK_F3_0);
613 DUMPREG(HDMI_V_BLANK_F3_1);
614 DUMPREG(HDMI_V_BLANK_F4_0);
615 DUMPREG(HDMI_V_BLANK_F4_1);
616 DUMPREG(HDMI_V_BLANK_F5_0);
617 DUMPREG(HDMI_V_BLANK_F5_1);
619 DUMPREG(HDMI_V_SYNC_LINE_AFT_3_0);
620 DUMPREG(HDMI_V_SYNC_LINE_AFT_3_1);
621 DUMPREG(HDMI_V_SYNC_LINE_AFT_4_0);
622 DUMPREG(HDMI_V_SYNC_LINE_AFT_4_1);
623 DUMPREG(HDMI_V_SYNC_LINE_AFT_5_0);
624 DUMPREG(HDMI_V_SYNC_LINE_AFT_5_1);
625 DUMPREG(HDMI_V_SYNC_LINE_AFT_6_0);
626 DUMPREG(HDMI_V_SYNC_LINE_AFT_6_1);
628 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_3_0);
629 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_3_1);
630 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_4_0);
631 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_4_1);
632 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_5_0);
633 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_5_1);
634 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_6_0);
635 DUMPREG(HDMI_V_SYNC_LINE_AFT_PXL_6_1);
637 DUMPREG(HDMI_VACT_SPACE_1_0);
638 DUMPREG(HDMI_VACT_SPACE_1_1);
639 DUMPREG(HDMI_VACT_SPACE_2_0);
640 DUMPREG(HDMI_VACT_SPACE_2_1);
641 DUMPREG(HDMI_VACT_SPACE_3_0);
642 DUMPREG(HDMI_VACT_SPACE_3_1);
643 DUMPREG(HDMI_VACT_SPACE_4_0);
644 DUMPREG(HDMI_VACT_SPACE_4_1);
645 DUMPREG(HDMI_VACT_SPACE_5_0);
646 DUMPREG(HDMI_VACT_SPACE_5_1);
647 DUMPREG(HDMI_VACT_SPACE_6_0);
648 DUMPREG(HDMI_VACT_SPACE_6_1);
650 DRM_DEBUG_KMS("%s: ---- TG REGISTERS ----\n", prefix);
651 DUMPREG(HDMI_TG_CMD);
652 DUMPREG(HDMI_TG_H_FSZ_L);
653 DUMPREG(HDMI_TG_H_FSZ_H);
654 DUMPREG(HDMI_TG_HACT_ST_L);
655 DUMPREG(HDMI_TG_HACT_ST_H);
656 DUMPREG(HDMI_TG_HACT_SZ_L);
657 DUMPREG(HDMI_TG_HACT_SZ_H);
658 DUMPREG(HDMI_TG_V_FSZ_L);
659 DUMPREG(HDMI_TG_V_FSZ_H);
660 DUMPREG(HDMI_TG_VSYNC_L);
661 DUMPREG(HDMI_TG_VSYNC_H);
662 DUMPREG(HDMI_TG_VSYNC2_L);
663 DUMPREG(HDMI_TG_VSYNC2_H);
664 DUMPREG(HDMI_TG_VACT_ST_L);
665 DUMPREG(HDMI_TG_VACT_ST_H);
666 DUMPREG(HDMI_TG_VACT_SZ_L);
667 DUMPREG(HDMI_TG_VACT_SZ_H);
668 DUMPREG(HDMI_TG_FIELD_CHG_L);
669 DUMPREG(HDMI_TG_FIELD_CHG_H);
670 DUMPREG(HDMI_TG_VACT_ST2_L);
671 DUMPREG(HDMI_TG_VACT_ST2_H);
672 DUMPREG(HDMI_TG_VACT_ST3_L);
673 DUMPREG(HDMI_TG_VACT_ST3_H);
674 DUMPREG(HDMI_TG_VACT_ST4_L);
675 DUMPREG(HDMI_TG_VACT_ST4_H);
676 DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_L);
677 DUMPREG(HDMI_TG_VSYNC_TOP_HDMI_H);
678 DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_L);
679 DUMPREG(HDMI_TG_VSYNC_BOT_HDMI_H);
680 DUMPREG(HDMI_TG_FIELD_TOP_HDMI_L);
681 DUMPREG(HDMI_TG_FIELD_TOP_HDMI_H);
682 DUMPREG(HDMI_TG_FIELD_BOT_HDMI_L);
683 DUMPREG(HDMI_TG_FIELD_BOT_HDMI_H);
686 DRM_DEBUG_KMS("%s: ---- PACKET REGISTERS ----\n", prefix);
687 DUMPREG(HDMI_AVI_CON);
688 DUMPREG(HDMI_AVI_HEADER0);
689 DUMPREG(HDMI_AVI_HEADER1);
690 DUMPREG(HDMI_AVI_HEADER2);
691 DUMPREG(HDMI_AVI_CHECK_SUM);
692 DUMPREG(HDMI_VSI_CON);
693 DUMPREG(HDMI_VSI_HEADER0);
694 DUMPREG(HDMI_VSI_HEADER1);
695 DUMPREG(HDMI_VSI_HEADER2);
696 for (i = 0; i < 7; ++i)
697 DUMPREG(HDMI_VSI_DATA(i));
702 static void hdmi_regs_dump(struct hdmi_context *hdata, char *prefix)
704 if (hdata->type == HDMI_TYPE13)
705 hdmi_v13_regs_dump(hdata, prefix);
707 hdmi_v14_regs_dump(hdata, prefix);
710 static u8 hdmi_chksum(struct hdmi_context *hdata,
711 u32 start, u8 len, u32 hdr_sum)
715 /* hdr_sum : header0 + header1 + header2
716 * start : start address of packet byte1
717 * len : packet bytes - 1 */
718 for (i = 0; i < len; ++i)
719 hdr_sum += 0xff & hdmi_reg_read(hdata, start + i * 4);
721 /* return 2's complement of 8 bit hdr_sum */
722 return (u8)(~(hdr_sum & 0xff) + 1);
725 static void hdmi_reg_infoframe(struct hdmi_context *hdata,
726 union hdmi_infoframe *infoframe)
733 mod = hdmi_reg_read(hdata, HDMI_MODE_SEL);
734 if (hdata->dvi_mode) {
735 hdmi_reg_writeb(hdata, HDMI_VSI_CON,
736 HDMI_VSI_CON_DO_NOT_TRANSMIT);
737 hdmi_reg_writeb(hdata, HDMI_AVI_CON,
738 HDMI_AVI_CON_DO_NOT_TRANSMIT);
739 hdmi_reg_writeb(hdata, HDMI_AUI_CON, HDMI_AUI_CON_NO_TRAN);
743 switch (infoframe->any.type) {
744 case HDMI_INFOFRAME_TYPE_AVI:
745 hdmi_reg_writeb(hdata, HDMI_AVI_CON, HDMI_AVI_CON_EVERY_VSYNC);
746 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER0, infoframe->any.type);
747 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER1,
748 infoframe->any.version);
749 hdmi_reg_writeb(hdata, HDMI_AVI_HEADER2, infoframe->any.length);
750 hdr_sum = infoframe->any.type + infoframe->any.version +
751 infoframe->any.length;
753 /* Output format zero hardcoded ,RGB YBCR selection */
754 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(1), 0 << 5 |
755 AVI_ACTIVE_FORMAT_VALID |
756 AVI_UNDERSCANNED_DISPLAY_VALID);
759 * Set the aspect ratio as per the mode, mentioned in
760 * Table 9 AVI InfoFrame Data Byte 2 of CEA-861-D Standard
762 switch (hdata->mode_conf.aspect_ratio) {
763 case HDMI_PICTURE_ASPECT_4_3:
764 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2),
765 hdata->mode_conf.aspect_ratio |
766 AVI_4_3_CENTER_RATIO);
768 case HDMI_PICTURE_ASPECT_16_9:
769 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2),
770 hdata->mode_conf.aspect_ratio |
771 AVI_16_9_CENTER_RATIO);
773 case HDMI_PICTURE_ASPECT_NONE:
775 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2),
776 hdata->mode_conf.aspect_ratio |
777 AVI_SAME_AS_PIC_ASPECT_RATIO);
781 vic = hdata->mode_conf.cea_video_id;
782 hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(4), vic);
784 chksum = hdmi_chksum(hdata, HDMI_AVI_BYTE(1),
785 infoframe->any.length, hdr_sum);
786 DRM_DEBUG_KMS("AVI checksum = 0x%x\n", chksum);
787 hdmi_reg_writeb(hdata, HDMI_AVI_CHECK_SUM, chksum);
789 case HDMI_INFOFRAME_TYPE_AUDIO:
790 hdmi_reg_writeb(hdata, HDMI_AUI_CON, 0x02);
791 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER0, infoframe->any.type);
792 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER1,
793 infoframe->any.version);
794 hdmi_reg_writeb(hdata, HDMI_AUI_HEADER2, infoframe->any.length);
795 hdr_sum = infoframe->any.type + infoframe->any.version +
796 infoframe->any.length;
797 chksum = hdmi_chksum(hdata, HDMI_AUI_BYTE(1),
798 infoframe->any.length, hdr_sum);
799 DRM_DEBUG_KMS("AUI checksum = 0x%x\n", chksum);
800 hdmi_reg_writeb(hdata, HDMI_AUI_CHECK_SUM, chksum);
807 static enum drm_connector_status hdmi_detect(struct drm_connector *connector,
810 struct hdmi_context *hdata = ctx_from_connector(connector);
812 return hdata->hpd ? connector_status_connected :
813 connector_status_disconnected;
816 static void hdmi_connector_destroy(struct drm_connector *connector)
820 static struct drm_connector_funcs hdmi_connector_funcs = {
821 .dpms = drm_helper_connector_dpms,
822 .fill_modes = drm_helper_probe_single_connector_modes,
823 .detect = hdmi_detect,
824 .destroy = hdmi_connector_destroy,
827 static int hdmi_get_modes(struct drm_connector *connector)
829 struct hdmi_context *hdata = ctx_from_connector(connector);
832 if (!hdata->ddc_adpt)
835 edid = drm_get_edid(connector, hdata->ddc_adpt);
839 hdata->dvi_mode = !drm_detect_hdmi_monitor(edid);
840 DRM_DEBUG_KMS("%s : width[%d] x height[%d]\n",
841 (hdata->dvi_mode ? "dvi monitor" : "hdmi monitor"),
842 edid->width_cm, edid->height_cm);
844 drm_mode_connector_update_edid_property(connector, edid);
846 return drm_add_edid_modes(connector, edid);
849 static int hdmi_find_phy_conf(struct hdmi_context *hdata, u32 pixel_clock)
851 const struct hdmiphy_config *confs;
854 if (hdata->type == HDMI_TYPE13) {
855 confs = hdmiphy_v13_configs;
856 count = ARRAY_SIZE(hdmiphy_v13_configs);
857 } else if (hdata->type == HDMI_TYPE14) {
858 confs = hdmiphy_v14_configs;
859 count = ARRAY_SIZE(hdmiphy_v14_configs);
863 for (i = 0; i < count; i++)
864 if (confs[i].pixel_clock == pixel_clock)
867 DRM_DEBUG_KMS("Could not find phy config for %d\n", pixel_clock);
871 static int hdmi_mode_valid(struct drm_connector *connector,
872 struct drm_display_mode *mode)
874 struct hdmi_context *hdata = ctx_from_connector(connector);
877 DRM_DEBUG_KMS("xres=%d, yres=%d, refresh=%d, intl=%d clock=%d\n",
878 mode->hdisplay, mode->vdisplay, mode->vrefresh,
879 (mode->flags & DRM_MODE_FLAG_INTERLACE) ? true :
880 false, mode->clock * 1000);
882 ret = mixer_check_mode(mode);
886 ret = hdmi_find_phy_conf(hdata, mode->clock * 1000);
893 static struct drm_encoder *hdmi_best_encoder(struct drm_connector *connector)
895 struct hdmi_context *hdata = ctx_from_connector(connector);
897 return hdata->encoder;
900 static struct drm_connector_helper_funcs hdmi_connector_helper_funcs = {
901 .get_modes = hdmi_get_modes,
902 .mode_valid = hdmi_mode_valid,
903 .best_encoder = hdmi_best_encoder,
906 static int hdmi_create_connector(struct exynos_drm_display *display,
907 struct drm_encoder *encoder)
909 struct hdmi_context *hdata = display->ctx;
910 struct drm_connector *connector = &hdata->connector;
913 hdata->encoder = encoder;
914 connector->interlace_allowed = true;
915 connector->polled = DRM_CONNECTOR_POLL_HPD;
917 ret = drm_connector_init(hdata->drm_dev, connector,
918 &hdmi_connector_funcs, DRM_MODE_CONNECTOR_HDMIA);
920 DRM_ERROR("Failed to initialize connector with drm\n");
924 drm_connector_helper_add(connector, &hdmi_connector_helper_funcs);
925 drm_sysfs_connector_add(connector);
926 drm_mode_connector_attach_encoder(connector, encoder);
931 static int hdmi_initialize(struct exynos_drm_display *display,
932 struct drm_device *drm_dev)
934 struct hdmi_context *hdata = display->ctx;
936 hdata->drm_dev = drm_dev;
941 static void hdmi_mode_fixup(struct exynos_drm_display *display,
942 struct drm_connector *connector,
943 const struct drm_display_mode *mode,
944 struct drm_display_mode *adjusted_mode)
946 struct drm_display_mode *m;
949 DRM_DEBUG_KMS("%s\n", __FILE__);
951 drm_mode_set_crtcinfo(adjusted_mode, 0);
953 mode_ok = hdmi_mode_valid(connector, adjusted_mode);
955 /* just return if user desired mode exists. */
956 if (mode_ok == MODE_OK)
960 * otherwise, find the most suitable mode among modes and change it
963 list_for_each_entry(m, &connector->modes, head) {
964 mode_ok = hdmi_mode_valid(connector, m);
966 if (mode_ok == MODE_OK) {
967 DRM_INFO("desired mode doesn't exist so\n");
968 DRM_INFO("use the most suitable mode among modes.\n");
970 DRM_DEBUG_KMS("Adjusted Mode: [%d]x[%d] [%d]Hz\n",
971 m->hdisplay, m->vdisplay, m->vrefresh);
973 drm_mode_copy(adjusted_mode, m);
979 static void hdmi_set_acr(u32 freq, u8 *acr)
1019 acr[2] = cts >> 8 & 0xff;
1020 acr[3] = cts & 0xff;
1023 acr[5] = n >> 8 & 0xff;
1027 static void hdmi_reg_acr(struct hdmi_context *hdata, u8 *acr)
1029 hdmi_reg_writeb(hdata, HDMI_ACR_N0, acr[6]);
1030 hdmi_reg_writeb(hdata, HDMI_ACR_N1, acr[5]);
1031 hdmi_reg_writeb(hdata, HDMI_ACR_N2, acr[4]);
1032 hdmi_reg_writeb(hdata, HDMI_ACR_MCTS0, acr[3]);
1033 hdmi_reg_writeb(hdata, HDMI_ACR_MCTS1, acr[2]);
1034 hdmi_reg_writeb(hdata, HDMI_ACR_MCTS2, acr[1]);
1035 hdmi_reg_writeb(hdata, HDMI_ACR_CTS0, acr[3]);
1036 hdmi_reg_writeb(hdata, HDMI_ACR_CTS1, acr[2]);
1037 hdmi_reg_writeb(hdata, HDMI_ACR_CTS2, acr[1]);
1039 if (hdata->type == HDMI_TYPE13)
1040 hdmi_reg_writeb(hdata, HDMI_V13_ACR_CON, 4);
1042 hdmi_reg_writeb(hdata, HDMI_ACR_CON, 4);
1045 static void hdmi_audio_init(struct hdmi_context *hdata)
1047 u32 sample_rate, bits_per_sample, frame_size_code;
1048 u32 data_num, bit_ch, sample_frq;
1052 sample_rate = 44100;
1053 bits_per_sample = 16;
1054 frame_size_code = 0;
1056 switch (bits_per_sample) {
1071 hdmi_set_acr(sample_rate, acr);
1072 hdmi_reg_acr(hdata, acr);
1074 hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CON, HDMI_I2S_IN_DISABLE
1075 | HDMI_I2S_AUD_I2S | HDMI_I2S_CUV_I2S_ENABLE
1076 | HDMI_I2S_MUX_ENABLE);
1078 hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CH, HDMI_I2S_CH0_EN
1079 | HDMI_I2S_CH1_EN | HDMI_I2S_CH2_EN);
1081 hdmi_reg_writeb(hdata, HDMI_I2S_MUX_CUV, HDMI_I2S_CUV_RL_EN);
1083 sample_frq = (sample_rate == 44100) ? 0 :
1084 (sample_rate == 48000) ? 2 :
1085 (sample_rate == 32000) ? 3 :
1086 (sample_rate == 96000) ? 0xa : 0x0;
1088 hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_DIS);
1089 hdmi_reg_writeb(hdata, HDMI_I2S_CLK_CON, HDMI_I2S_CLK_EN);
1091 val = hdmi_reg_read(hdata, HDMI_I2S_DSD_CON) | 0x01;
1092 hdmi_reg_writeb(hdata, HDMI_I2S_DSD_CON, val);
1094 /* Configuration I2S input ports. Configure I2S_PIN_SEL_0~4 */
1095 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_0, HDMI_I2S_SEL_SCLK(5)
1096 | HDMI_I2S_SEL_LRCK(6));
1097 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_1, HDMI_I2S_SEL_SDATA1(1)
1098 | HDMI_I2S_SEL_SDATA2(4));
1099 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_2, HDMI_I2S_SEL_SDATA3(1)
1100 | HDMI_I2S_SEL_SDATA2(2));
1101 hdmi_reg_writeb(hdata, HDMI_I2S_PIN_SEL_3, HDMI_I2S_SEL_DSD(0));
1104 hdmi_reg_writeb(hdata, HDMI_I2S_CON_1, HDMI_I2S_SCLK_FALLING_EDGE
1105 | HDMI_I2S_L_CH_LOW_POL);
1106 hdmi_reg_writeb(hdata, HDMI_I2S_CON_2, HDMI_I2S_MSB_FIRST_MODE
1107 | HDMI_I2S_SET_BIT_CH(bit_ch)
1108 | HDMI_I2S_SET_SDATA_BIT(data_num)
1109 | HDMI_I2S_BASIC_FORMAT);
1111 /* Configure register related to CUV information */
1112 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_0, HDMI_I2S_CH_STATUS_MODE_0
1113 | HDMI_I2S_2AUD_CH_WITHOUT_PREEMPH
1114 | HDMI_I2S_COPYRIGHT
1115 | HDMI_I2S_LINEAR_PCM
1116 | HDMI_I2S_CONSUMER_FORMAT);
1117 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_1, HDMI_I2S_CD_PLAYER);
1118 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_2, HDMI_I2S_SET_SOURCE_NUM(0));
1119 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_3, HDMI_I2S_CLK_ACCUR_LEVEL_2
1120 | HDMI_I2S_SET_SMP_FREQ(sample_frq));
1121 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_4,
1122 HDMI_I2S_ORG_SMP_FREQ_44_1
1123 | HDMI_I2S_WORD_LEN_MAX24_24BITS
1124 | HDMI_I2S_WORD_LEN_MAX_24BITS);
1126 hdmi_reg_writeb(hdata, HDMI_I2S_CH_ST_CON, HDMI_I2S_CH_STATUS_RELOAD);
1129 static void hdmi_audio_control(struct hdmi_context *hdata, bool onoff)
1131 if (hdata->dvi_mode)
1134 hdmi_reg_writeb(hdata, HDMI_AUI_CON, onoff ? 2 : 0);
1135 hdmi_reg_writemask(hdata, HDMI_CON_0, onoff ?
1136 HDMI_ASP_EN : HDMI_ASP_DIS, HDMI_ASP_MASK);
1139 static void hdmi_conf_reset(struct hdmi_context *hdata)
1143 if (hdata->type == HDMI_TYPE13)
1144 reg = HDMI_V13_CORE_RSTOUT;
1146 reg = HDMI_CORE_RSTOUT;
1148 /* resetting HDMI core */
1149 hdmi_reg_writemask(hdata, reg, 0, HDMI_CORE_SW_RSTOUT);
1150 usleep_range(10000, 12000);
1151 hdmi_reg_writemask(hdata, reg, ~0, HDMI_CORE_SW_RSTOUT);
1152 usleep_range(10000, 12000);
1155 static void hdmi_conf_init(struct hdmi_context *hdata)
1157 union hdmi_infoframe infoframe;
1159 /* disable HPD interrupts from HDMI IP block, use GPIO instead */
1160 hdmi_reg_writemask(hdata, HDMI_INTC_CON, 0, HDMI_INTC_EN_GLOBAL |
1161 HDMI_INTC_EN_HPD_PLUG | HDMI_INTC_EN_HPD_UNPLUG);
1163 /* choose HDMI mode */
1164 hdmi_reg_writemask(hdata, HDMI_MODE_SEL,
1165 HDMI_MODE_HDMI_EN, HDMI_MODE_MASK);
1166 /* disable bluescreen */
1167 hdmi_reg_writemask(hdata, HDMI_CON_0, 0, HDMI_BLUE_SCR_EN);
1169 if (hdata->dvi_mode) {
1170 /* choose DVI mode */
1171 hdmi_reg_writemask(hdata, HDMI_MODE_SEL,
1172 HDMI_MODE_DVI_EN, HDMI_MODE_MASK);
1173 hdmi_reg_writeb(hdata, HDMI_CON_2,
1174 HDMI_VID_PREAMBLE_DIS | HDMI_GUARD_BAND_DIS);
1177 if (hdata->type == HDMI_TYPE13) {
1178 /* choose bluescreen (fecal) color */
1179 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_0, 0x12);
1180 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_1, 0x34);
1181 hdmi_reg_writeb(hdata, HDMI_V13_BLUE_SCREEN_2, 0x56);
1183 /* enable AVI packet every vsync, fixes purple line problem */
1184 hdmi_reg_writeb(hdata, HDMI_V13_AVI_CON, 0x02);
1185 /* force RGB, look to CEA-861-D, table 7 for more detail */
1186 hdmi_reg_writeb(hdata, HDMI_V13_AVI_BYTE(0), 0 << 5);
1187 hdmi_reg_writemask(hdata, HDMI_CON_1, 0x10 << 5, 0x11 << 5);
1189 hdmi_reg_writeb(hdata, HDMI_V13_SPD_CON, 0x02);
1190 hdmi_reg_writeb(hdata, HDMI_V13_AUI_CON, 0x02);
1191 hdmi_reg_writeb(hdata, HDMI_V13_ACR_CON, 0x04);
1193 infoframe.any.type = HDMI_INFOFRAME_TYPE_AVI;
1194 infoframe.any.version = HDMI_AVI_VERSION;
1195 infoframe.any.length = HDMI_AVI_LENGTH;
1196 hdmi_reg_infoframe(hdata, &infoframe);
1198 infoframe.any.type = HDMI_INFOFRAME_TYPE_AUDIO;
1199 infoframe.any.version = HDMI_AUI_VERSION;
1200 infoframe.any.length = HDMI_AUI_LENGTH;
1201 hdmi_reg_infoframe(hdata, &infoframe);
1203 /* enable AVI packet every vsync, fixes purple line problem */
1204 hdmi_reg_writemask(hdata, HDMI_CON_1, 2, 3 << 5);
1208 static void hdmi_v13_mode_apply(struct hdmi_context *hdata)
1210 const struct hdmi_tg_regs *tg = &hdata->mode_conf.conf.v13_conf.tg;
1211 const struct hdmi_v13_core_regs *core =
1212 &hdata->mode_conf.conf.v13_conf.core;
1215 /* setting core registers */
1216 hdmi_reg_writeb(hdata, HDMI_H_BLANK_0, core->h_blank[0]);
1217 hdmi_reg_writeb(hdata, HDMI_H_BLANK_1, core->h_blank[1]);
1218 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_0, core->v_blank[0]);
1219 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_1, core->v_blank[1]);
1220 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_2, core->v_blank[2]);
1221 hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_0, core->h_v_line[0]);
1222 hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_1, core->h_v_line[1]);
1223 hdmi_reg_writeb(hdata, HDMI_V13_H_V_LINE_2, core->h_v_line[2]);
1224 hdmi_reg_writeb(hdata, HDMI_VSYNC_POL, core->vsync_pol[0]);
1225 hdmi_reg_writeb(hdata, HDMI_INT_PRO_MODE, core->int_pro_mode[0]);
1226 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_0, core->v_blank_f[0]);
1227 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_1, core->v_blank_f[1]);
1228 hdmi_reg_writeb(hdata, HDMI_V13_V_BLANK_F_2, core->v_blank_f[2]);
1229 hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_0, core->h_sync_gen[0]);
1230 hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_1, core->h_sync_gen[1]);
1231 hdmi_reg_writeb(hdata, HDMI_V13_H_SYNC_GEN_2, core->h_sync_gen[2]);
1232 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_0, core->v_sync_gen1[0]);
1233 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_1, core->v_sync_gen1[1]);
1234 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_1_2, core->v_sync_gen1[2]);
1235 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_0, core->v_sync_gen2[0]);
1236 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_1, core->v_sync_gen2[1]);
1237 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_2_2, core->v_sync_gen2[2]);
1238 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_0, core->v_sync_gen3[0]);
1239 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_1, core->v_sync_gen3[1]);
1240 hdmi_reg_writeb(hdata, HDMI_V13_V_SYNC_GEN_3_2, core->v_sync_gen3[2]);
1241 /* Timing generator registers */
1242 hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_L, tg->h_fsz[0]);
1243 hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_H, tg->h_fsz[1]);
1244 hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_L, tg->hact_st[0]);
1245 hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_H, tg->hact_st[1]);
1246 hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_L, tg->hact_sz[0]);
1247 hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_H, tg->hact_sz[1]);
1248 hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_L, tg->v_fsz[0]);
1249 hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_H, tg->v_fsz[1]);
1250 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_L, tg->vsync[0]);
1251 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_H, tg->vsync[1]);
1252 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_L, tg->vsync2[0]);
1253 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_H, tg->vsync2[1]);
1254 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_L, tg->vact_st[0]);
1255 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_H, tg->vact_st[1]);
1256 hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_L, tg->vact_sz[0]);
1257 hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_H, tg->vact_sz[1]);
1258 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_L, tg->field_chg[0]);
1259 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_H, tg->field_chg[1]);
1260 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_L, tg->vact_st2[0]);
1261 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_H, tg->vact_st2[1]);
1262 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_L, tg->vsync_top_hdmi[0]);
1263 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_H, tg->vsync_top_hdmi[1]);
1264 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, tg->vsync_bot_hdmi[0]);
1265 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_H, tg->vsync_bot_hdmi[1]);
1266 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_L, tg->field_top_hdmi[0]);
1267 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_H, tg->field_top_hdmi[1]);
1268 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_L, tg->field_bot_hdmi[0]);
1269 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_H, tg->field_bot_hdmi[1]);
1271 /* waiting for HDMIPHY's PLL to get to steady state */
1272 for (tries = 100; tries; --tries) {
1273 u32 val = hdmi_reg_read(hdata, HDMI_V13_PHY_STATUS);
1274 if (val & HDMI_PHY_STATUS_READY)
1276 usleep_range(1000, 2000);
1278 /* steady state not achieved */
1280 DRM_ERROR("hdmiphy's pll could not reach steady state.\n");
1281 hdmi_regs_dump(hdata, "timing apply");
1284 clk_disable_unprepare(hdata->res.sclk_hdmi);
1285 clk_set_parent(hdata->res.mout_hdmi, hdata->res.sclk_hdmiphy);
1286 clk_prepare_enable(hdata->res.sclk_hdmi);
1288 /* enable HDMI and timing generator */
1289 hdmi_reg_writemask(hdata, HDMI_CON_0, ~0, HDMI_EN);
1290 if (core->int_pro_mode[0])
1291 hdmi_reg_writemask(hdata, HDMI_TG_CMD, ~0, HDMI_TG_EN |
1294 hdmi_reg_writemask(hdata, HDMI_TG_CMD, ~0, HDMI_TG_EN);
1297 static void hdmi_v14_mode_apply(struct hdmi_context *hdata)
1299 const struct hdmi_tg_regs *tg = &hdata->mode_conf.conf.v14_conf.tg;
1300 const struct hdmi_v14_core_regs *core =
1301 &hdata->mode_conf.conf.v14_conf.core;
1304 /* setting core registers */
1305 hdmi_reg_writeb(hdata, HDMI_H_BLANK_0, core->h_blank[0]);
1306 hdmi_reg_writeb(hdata, HDMI_H_BLANK_1, core->h_blank[1]);
1307 hdmi_reg_writeb(hdata, HDMI_V2_BLANK_0, core->v2_blank[0]);
1308 hdmi_reg_writeb(hdata, HDMI_V2_BLANK_1, core->v2_blank[1]);
1309 hdmi_reg_writeb(hdata, HDMI_V1_BLANK_0, core->v1_blank[0]);
1310 hdmi_reg_writeb(hdata, HDMI_V1_BLANK_1, core->v1_blank[1]);
1311 hdmi_reg_writeb(hdata, HDMI_V_LINE_0, core->v_line[0]);
1312 hdmi_reg_writeb(hdata, HDMI_V_LINE_1, core->v_line[1]);
1313 hdmi_reg_writeb(hdata, HDMI_H_LINE_0, core->h_line[0]);
1314 hdmi_reg_writeb(hdata, HDMI_H_LINE_1, core->h_line[1]);
1315 hdmi_reg_writeb(hdata, HDMI_HSYNC_POL, core->hsync_pol[0]);
1316 hdmi_reg_writeb(hdata, HDMI_VSYNC_POL, core->vsync_pol[0]);
1317 hdmi_reg_writeb(hdata, HDMI_INT_PRO_MODE, core->int_pro_mode[0]);
1318 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F0_0, core->v_blank_f0[0]);
1319 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F0_1, core->v_blank_f0[1]);
1320 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F1_0, core->v_blank_f1[0]);
1321 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F1_1, core->v_blank_f1[1]);
1322 hdmi_reg_writeb(hdata, HDMI_H_SYNC_START_0, core->h_sync_start[0]);
1323 hdmi_reg_writeb(hdata, HDMI_H_SYNC_START_1, core->h_sync_start[1]);
1324 hdmi_reg_writeb(hdata, HDMI_H_SYNC_END_0, core->h_sync_end[0]);
1325 hdmi_reg_writeb(hdata, HDMI_H_SYNC_END_1, core->h_sync_end[1]);
1326 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_2_0,
1327 core->v_sync_line_bef_2[0]);
1328 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_2_1,
1329 core->v_sync_line_bef_2[1]);
1330 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_1_0,
1331 core->v_sync_line_bef_1[0]);
1332 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_BEF_1_1,
1333 core->v_sync_line_bef_1[1]);
1334 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_2_0,
1335 core->v_sync_line_aft_2[0]);
1336 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_2_1,
1337 core->v_sync_line_aft_2[1]);
1338 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_1_0,
1339 core->v_sync_line_aft_1[0]);
1340 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_1_1,
1341 core->v_sync_line_aft_1[1]);
1342 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_0,
1343 core->v_sync_line_aft_pxl_2[0]);
1344 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_2_1,
1345 core->v_sync_line_aft_pxl_2[1]);
1346 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_0,
1347 core->v_sync_line_aft_pxl_1[0]);
1348 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_1_1,
1349 core->v_sync_line_aft_pxl_1[1]);
1350 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F2_0, core->v_blank_f2[0]);
1351 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F2_1, core->v_blank_f2[1]);
1352 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F3_0, core->v_blank_f3[0]);
1353 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F3_1, core->v_blank_f3[1]);
1354 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F4_0, core->v_blank_f4[0]);
1355 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F4_1, core->v_blank_f4[1]);
1356 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F5_0, core->v_blank_f5[0]);
1357 hdmi_reg_writeb(hdata, HDMI_V_BLANK_F5_1, core->v_blank_f5[1]);
1358 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_3_0,
1359 core->v_sync_line_aft_3[0]);
1360 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_3_1,
1361 core->v_sync_line_aft_3[1]);
1362 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_4_0,
1363 core->v_sync_line_aft_4[0]);
1364 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_4_1,
1365 core->v_sync_line_aft_4[1]);
1366 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_5_0,
1367 core->v_sync_line_aft_5[0]);
1368 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_5_1,
1369 core->v_sync_line_aft_5[1]);
1370 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_6_0,
1371 core->v_sync_line_aft_6[0]);
1372 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_6_1,
1373 core->v_sync_line_aft_6[1]);
1374 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_3_0,
1375 core->v_sync_line_aft_pxl_3[0]);
1376 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_3_1,
1377 core->v_sync_line_aft_pxl_3[1]);
1378 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_4_0,
1379 core->v_sync_line_aft_pxl_4[0]);
1380 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_4_1,
1381 core->v_sync_line_aft_pxl_4[1]);
1382 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_5_0,
1383 core->v_sync_line_aft_pxl_5[0]);
1384 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_5_1,
1385 core->v_sync_line_aft_pxl_5[1]);
1386 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_6_0,
1387 core->v_sync_line_aft_pxl_6[0]);
1388 hdmi_reg_writeb(hdata, HDMI_V_SYNC_LINE_AFT_PXL_6_1,
1389 core->v_sync_line_aft_pxl_6[1]);
1390 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_1_0, core->vact_space_1[0]);
1391 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_1_1, core->vact_space_1[1]);
1392 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_2_0, core->vact_space_2[0]);
1393 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_2_1, core->vact_space_2[1]);
1394 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_3_0, core->vact_space_3[0]);
1395 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_3_1, core->vact_space_3[1]);
1396 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_4_0, core->vact_space_4[0]);
1397 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_4_1, core->vact_space_4[1]);
1398 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_5_0, core->vact_space_5[0]);
1399 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_5_1, core->vact_space_5[1]);
1400 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_6_0, core->vact_space_6[0]);
1401 hdmi_reg_writeb(hdata, HDMI_VACT_SPACE_6_1, core->vact_space_6[1]);
1403 /* Timing generator registers */
1404 hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_L, tg->h_fsz[0]);
1405 hdmi_reg_writeb(hdata, HDMI_TG_H_FSZ_H, tg->h_fsz[1]);
1406 hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_L, tg->hact_st[0]);
1407 hdmi_reg_writeb(hdata, HDMI_TG_HACT_ST_H, tg->hact_st[1]);
1408 hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_L, tg->hact_sz[0]);
1409 hdmi_reg_writeb(hdata, HDMI_TG_HACT_SZ_H, tg->hact_sz[1]);
1410 hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_L, tg->v_fsz[0]);
1411 hdmi_reg_writeb(hdata, HDMI_TG_V_FSZ_H, tg->v_fsz[1]);
1412 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_L, tg->vsync[0]);
1413 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_H, tg->vsync[1]);
1414 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_L, tg->vsync2[0]);
1415 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC2_H, tg->vsync2[1]);
1416 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_L, tg->vact_st[0]);
1417 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST_H, tg->vact_st[1]);
1418 hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_L, tg->vact_sz[0]);
1419 hdmi_reg_writeb(hdata, HDMI_TG_VACT_SZ_H, tg->vact_sz[1]);
1420 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_L, tg->field_chg[0]);
1421 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_CHG_H, tg->field_chg[1]);
1422 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_L, tg->vact_st2[0]);
1423 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST2_H, tg->vact_st2[1]);
1424 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST3_L, tg->vact_st3[0]);
1425 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST3_H, tg->vact_st3[1]);
1426 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST4_L, tg->vact_st4[0]);
1427 hdmi_reg_writeb(hdata, HDMI_TG_VACT_ST4_H, tg->vact_st4[1]);
1428 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_L, tg->vsync_top_hdmi[0]);
1429 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_TOP_HDMI_H, tg->vsync_top_hdmi[1]);
1430 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_L, tg->vsync_bot_hdmi[0]);
1431 hdmi_reg_writeb(hdata, HDMI_TG_VSYNC_BOT_HDMI_H, tg->vsync_bot_hdmi[1]);
1432 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_L, tg->field_top_hdmi[0]);
1433 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_TOP_HDMI_H, tg->field_top_hdmi[1]);
1434 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_L, tg->field_bot_hdmi[0]);
1435 hdmi_reg_writeb(hdata, HDMI_TG_FIELD_BOT_HDMI_H, tg->field_bot_hdmi[1]);
1436 hdmi_reg_writeb(hdata, HDMI_TG_3D, tg->tg_3d[0]);
1438 /* waiting for HDMIPHY's PLL to get to steady state */
1439 for (tries = 100; tries; --tries) {
1440 u32 val = hdmi_reg_read(hdata, HDMI_PHY_STATUS_0);
1441 if (val & HDMI_PHY_STATUS_READY)
1443 usleep_range(1000, 2000);
1445 /* steady state not achieved */
1447 DRM_ERROR("hdmiphy's pll could not reach steady state.\n");
1448 hdmi_regs_dump(hdata, "timing apply");
1451 clk_disable_unprepare(hdata->res.sclk_hdmi);
1452 clk_set_parent(hdata->res.mout_hdmi, hdata->res.sclk_hdmiphy);
1453 clk_prepare_enable(hdata->res.sclk_hdmi);
1455 /* enable HDMI and timing generator */
1456 hdmi_reg_writemask(hdata, HDMI_CON_0, ~0, HDMI_EN);
1457 if (core->int_pro_mode[0])
1458 hdmi_reg_writemask(hdata, HDMI_TG_CMD, ~0, HDMI_TG_EN |
1461 hdmi_reg_writemask(hdata, HDMI_TG_CMD, ~0, HDMI_TG_EN);
1464 static void hdmi_mode_apply(struct hdmi_context *hdata)
1466 if (hdata->type == HDMI_TYPE13)
1467 hdmi_v13_mode_apply(hdata);
1469 hdmi_v14_mode_apply(hdata);
1472 static void hdmiphy_conf_reset(struct hdmi_context *hdata)
1477 clk_disable_unprepare(hdata->res.sclk_hdmi);
1478 clk_set_parent(hdata->res.mout_hdmi, hdata->res.sclk_pixel);
1479 clk_prepare_enable(hdata->res.sclk_hdmi);
1481 /* operation mode */
1485 if (hdata->hdmiphy_port)
1486 i2c_master_send(hdata->hdmiphy_port, buffer, 2);
1488 if (hdata->type == HDMI_TYPE13)
1489 reg = HDMI_V13_PHY_RSTOUT;
1491 reg = HDMI_PHY_RSTOUT;
1494 hdmi_reg_writemask(hdata, reg, ~0, HDMI_PHY_SW_RSTOUT);
1495 usleep_range(10000, 12000);
1496 hdmi_reg_writemask(hdata, reg, 0, HDMI_PHY_SW_RSTOUT);
1497 usleep_range(10000, 12000);
1500 static void hdmiphy_poweron(struct hdmi_context *hdata)
1502 if (hdata->type == HDMI_TYPE14)
1503 hdmi_reg_writemask(hdata, HDMI_PHY_CON_0, 0,
1504 HDMI_PHY_POWER_OFF_EN);
1507 static void hdmiphy_poweroff(struct hdmi_context *hdata)
1509 if (hdata->type == HDMI_TYPE14)
1510 hdmi_reg_writemask(hdata, HDMI_PHY_CON_0, ~0,
1511 HDMI_PHY_POWER_OFF_EN);
1514 static void hdmiphy_conf_apply(struct hdmi_context *hdata)
1516 const u8 *hdmiphy_data;
1519 u8 read_buffer[32] = {0, };
1523 if (!hdata->hdmiphy_port) {
1524 DRM_ERROR("hdmiphy is not attached\n");
1529 i = hdmi_find_phy_conf(hdata, hdata->mode_conf.pixel_clock);
1531 DRM_ERROR("failed to find hdmiphy conf\n");
1535 if (hdata->type == HDMI_TYPE13)
1536 hdmiphy_data = hdmiphy_v13_configs[i].conf;
1538 hdmiphy_data = hdmiphy_v14_configs[i].conf;
1540 memcpy(buffer, hdmiphy_data, 32);
1541 ret = i2c_master_send(hdata->hdmiphy_port, buffer, 32);
1543 DRM_ERROR("failed to configure HDMIPHY via I2C\n");
1547 usleep_range(10000, 12000);
1549 /* operation mode */
1550 operation[0] = 0x1f;
1551 operation[1] = 0x80;
1553 ret = i2c_master_send(hdata->hdmiphy_port, operation, 2);
1555 DRM_ERROR("failed to enable hdmiphy\n");
1559 ret = i2c_master_recv(hdata->hdmiphy_port, read_buffer, 32);
1561 DRM_ERROR("failed to read hdmiphy config\n");
1565 for (i = 0; i < ret; i++)
1566 DRM_DEBUG_KMS("hdmiphy[0x%02x] write[0x%02x] - "
1567 "recv [0x%02x]\n", i, buffer[i], read_buffer[i]);
1570 static void hdmi_conf_apply(struct hdmi_context *hdata)
1572 hdmiphy_conf_reset(hdata);
1573 hdmiphy_conf_apply(hdata);
1575 mutex_lock(&hdata->hdmi_mutex);
1576 hdmi_conf_reset(hdata);
1577 hdmi_conf_init(hdata);
1578 mutex_unlock(&hdata->hdmi_mutex);
1580 hdmi_audio_init(hdata);
1582 /* setting core registers */
1583 hdmi_mode_apply(hdata);
1584 hdmi_audio_control(hdata, true);
1586 hdmi_regs_dump(hdata, "start");
1589 static void hdmi_set_reg(u8 *reg_pair, int num_bytes, u32 value)
1592 BUG_ON(num_bytes > 4);
1593 for (i = 0; i < num_bytes; i++)
1594 reg_pair[i] = (value >> (8 * i)) & 0xff;
1597 static void hdmi_v13_mode_set(struct hdmi_context *hdata,
1598 struct drm_display_mode *m)
1600 struct hdmi_v13_core_regs *core = &hdata->mode_conf.conf.v13_conf.core;
1601 struct hdmi_tg_regs *tg = &hdata->mode_conf.conf.v13_conf.tg;
1604 hdata->mode_conf.cea_video_id =
1605 drm_match_cea_mode((struct drm_display_mode *)m);
1606 hdata->mode_conf.pixel_clock = m->clock * 1000;
1607 hdata->mode_conf.aspect_ratio = m->picture_aspect_ratio;
1609 hdmi_set_reg(core->h_blank, 2, m->htotal - m->hdisplay);
1610 hdmi_set_reg(core->h_v_line, 3, (m->htotal << 12) | m->vtotal);
1612 val = (m->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0;
1613 hdmi_set_reg(core->vsync_pol, 1, val);
1615 val = (m->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0;
1616 hdmi_set_reg(core->int_pro_mode, 1, val);
1618 val = (m->hsync_start - m->hdisplay - 2);
1619 val |= ((m->hsync_end - m->hdisplay - 2) << 10);
1620 val |= ((m->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0)<<20;
1621 hdmi_set_reg(core->h_sync_gen, 3, val);
1624 * Quirk requirement for exynos HDMI IP design,
1625 * 2 pixels less than the actual calculation for hsync_start
1629 /* Following values & calculations differ for different type of modes */
1630 if (m->flags & DRM_MODE_FLAG_INTERLACE) {
1631 /* Interlaced Mode */
1632 val = ((m->vsync_end - m->vdisplay) / 2);
1633 val |= ((m->vsync_start - m->vdisplay) / 2) << 12;
1634 hdmi_set_reg(core->v_sync_gen1, 3, val);
1636 val = m->vtotal / 2;
1637 val |= ((m->vtotal - m->vdisplay) / 2) << 11;
1638 hdmi_set_reg(core->v_blank, 3, val);
1641 ((m->vsync_end - m->vsync_start) * 4) + 5) / 2;
1642 val |= m->vtotal << 11;
1643 hdmi_set_reg(core->v_blank_f, 3, val);
1645 val = ((m->vtotal / 2) + 7);
1646 val |= ((m->vtotal / 2) + 2) << 12;
1647 hdmi_set_reg(core->v_sync_gen2, 3, val);
1649 val = ((m->htotal / 2) + (m->hsync_start - m->hdisplay));
1650 val |= ((m->htotal / 2) +
1651 (m->hsync_start - m->hdisplay)) << 12;
1652 hdmi_set_reg(core->v_sync_gen3, 3, val);
1654 hdmi_set_reg(tg->vact_st, 2, (m->vtotal - m->vdisplay) / 2);
1655 hdmi_set_reg(tg->vact_sz, 2, m->vdisplay / 2);
1657 hdmi_set_reg(tg->vact_st2, 2, 0x249);/* Reset value + 1*/
1659 /* Progressive Mode */
1662 val |= (m->vtotal - m->vdisplay) << 11;
1663 hdmi_set_reg(core->v_blank, 3, val);
1665 hdmi_set_reg(core->v_blank_f, 3, 0);
1667 val = (m->vsync_end - m->vdisplay);
1668 val |= ((m->vsync_start - m->vdisplay) << 12);
1669 hdmi_set_reg(core->v_sync_gen1, 3, val);
1671 hdmi_set_reg(core->v_sync_gen2, 3, 0x1001);/* Reset value */
1672 hdmi_set_reg(core->v_sync_gen3, 3, 0x1001);/* Reset value */
1673 hdmi_set_reg(tg->vact_st, 2, m->vtotal - m->vdisplay);
1674 hdmi_set_reg(tg->vact_sz, 2, m->vdisplay);
1675 hdmi_set_reg(tg->vact_st2, 2, 0x248); /* Reset value */
1678 /* Timing generator registers */
1679 hdmi_set_reg(tg->cmd, 1, 0x0);
1680 hdmi_set_reg(tg->h_fsz, 2, m->htotal);
1681 hdmi_set_reg(tg->hact_st, 2, m->htotal - m->hdisplay);
1682 hdmi_set_reg(tg->hact_sz, 2, m->hdisplay);
1683 hdmi_set_reg(tg->v_fsz, 2, m->vtotal);
1684 hdmi_set_reg(tg->vsync, 2, 0x1);
1685 hdmi_set_reg(tg->vsync2, 2, 0x233); /* Reset value */
1686 hdmi_set_reg(tg->field_chg, 2, 0x233); /* Reset value */
1687 hdmi_set_reg(tg->vsync_top_hdmi, 2, 0x1); /* Reset value */
1688 hdmi_set_reg(tg->vsync_bot_hdmi, 2, 0x233); /* Reset value */
1689 hdmi_set_reg(tg->field_top_hdmi, 2, 0x1); /* Reset value */
1690 hdmi_set_reg(tg->field_bot_hdmi, 2, 0x233); /* Reset value */
1691 hdmi_set_reg(tg->tg_3d, 1, 0x0); /* Not used */
1694 static void hdmi_v14_mode_set(struct hdmi_context *hdata,
1695 struct drm_display_mode *m)
1697 struct hdmi_tg_regs *tg = &hdata->mode_conf.conf.v14_conf.tg;
1698 struct hdmi_v14_core_regs *core =
1699 &hdata->mode_conf.conf.v14_conf.core;
1701 hdata->mode_conf.cea_video_id =
1702 drm_match_cea_mode((struct drm_display_mode *)m);
1703 hdata->mode_conf.pixel_clock = m->clock * 1000;
1704 hdata->mode_conf.aspect_ratio = m->picture_aspect_ratio;
1706 hdmi_set_reg(core->h_blank, 2, m->htotal - m->hdisplay);
1707 hdmi_set_reg(core->v_line, 2, m->vtotal);
1708 hdmi_set_reg(core->h_line, 2, m->htotal);
1709 hdmi_set_reg(core->hsync_pol, 1,
1710 (m->flags & DRM_MODE_FLAG_NHSYNC) ? 1 : 0);
1711 hdmi_set_reg(core->vsync_pol, 1,
1712 (m->flags & DRM_MODE_FLAG_NVSYNC) ? 1 : 0);
1713 hdmi_set_reg(core->int_pro_mode, 1,
1714 (m->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0);
1717 * Quirk requirement for exynos 5 HDMI IP design,
1718 * 2 pixels less than the actual calculation for hsync_start
1722 /* Following values & calculations differ for different type of modes */
1723 if (m->flags & DRM_MODE_FLAG_INTERLACE) {
1724 /* Interlaced Mode */
1725 hdmi_set_reg(core->v_sync_line_bef_2, 2,
1726 (m->vsync_end - m->vdisplay) / 2);
1727 hdmi_set_reg(core->v_sync_line_bef_1, 2,
1728 (m->vsync_start - m->vdisplay) / 2);
1729 hdmi_set_reg(core->v2_blank, 2, m->vtotal / 2);
1730 hdmi_set_reg(core->v1_blank, 2, (m->vtotal - m->vdisplay) / 2);
1731 hdmi_set_reg(core->v_blank_f0, 2, m->vtotal - m->vdisplay / 2);
1732 hdmi_set_reg(core->v_blank_f1, 2, m->vtotal);
1733 hdmi_set_reg(core->v_sync_line_aft_2, 2, (m->vtotal / 2) + 7);
1734 hdmi_set_reg(core->v_sync_line_aft_1, 2, (m->vtotal / 2) + 2);
1735 hdmi_set_reg(core->v_sync_line_aft_pxl_2, 2,
1736 (m->htotal / 2) + (m->hsync_start - m->hdisplay));
1737 hdmi_set_reg(core->v_sync_line_aft_pxl_1, 2,
1738 (m->htotal / 2) + (m->hsync_start - m->hdisplay));
1739 hdmi_set_reg(tg->vact_st, 2, (m->vtotal - m->vdisplay) / 2);
1740 hdmi_set_reg(tg->vact_sz, 2, m->vdisplay / 2);
1741 hdmi_set_reg(tg->vact_st2, 2, m->vtotal - m->vdisplay / 2);
1742 hdmi_set_reg(tg->vsync2, 2, (m->vtotal / 2) + 1);
1743 hdmi_set_reg(tg->vsync_bot_hdmi, 2, (m->vtotal / 2) + 1);
1744 hdmi_set_reg(tg->field_bot_hdmi, 2, (m->vtotal / 2) + 1);
1745 hdmi_set_reg(tg->vact_st3, 2, 0x0);
1746 hdmi_set_reg(tg->vact_st4, 2, 0x0);
1748 /* Progressive Mode */
1749 hdmi_set_reg(core->v_sync_line_bef_2, 2,
1750 m->vsync_end - m->vdisplay);
1751 hdmi_set_reg(core->v_sync_line_bef_1, 2,
1752 m->vsync_start - m->vdisplay);
1753 hdmi_set_reg(core->v2_blank, 2, m->vtotal);
1754 hdmi_set_reg(core->v1_blank, 2, m->vtotal - m->vdisplay);
1755 hdmi_set_reg(core->v_blank_f0, 2, 0xffff);
1756 hdmi_set_reg(core->v_blank_f1, 2, 0xffff);
1757 hdmi_set_reg(core->v_sync_line_aft_2, 2, 0xffff);
1758 hdmi_set_reg(core->v_sync_line_aft_1, 2, 0xffff);
1759 hdmi_set_reg(core->v_sync_line_aft_pxl_2, 2, 0xffff);
1760 hdmi_set_reg(core->v_sync_line_aft_pxl_1, 2, 0xffff);
1761 hdmi_set_reg(tg->vact_st, 2, m->vtotal - m->vdisplay);
1762 hdmi_set_reg(tg->vact_sz, 2, m->vdisplay);
1763 hdmi_set_reg(tg->vact_st2, 2, 0x248); /* Reset value */
1764 hdmi_set_reg(tg->vact_st3, 2, 0x47b); /* Reset value */
1765 hdmi_set_reg(tg->vact_st4, 2, 0x6ae); /* Reset value */
1766 hdmi_set_reg(tg->vsync2, 2, 0x233); /* Reset value */
1767 hdmi_set_reg(tg->vsync_bot_hdmi, 2, 0x233); /* Reset value */
1768 hdmi_set_reg(tg->field_bot_hdmi, 2, 0x233); /* Reset value */
1771 /* Following values & calculations are same irrespective of mode type */
1772 hdmi_set_reg(core->h_sync_start, 2, m->hsync_start - m->hdisplay - 2);
1773 hdmi_set_reg(core->h_sync_end, 2, m->hsync_end - m->hdisplay - 2);
1774 hdmi_set_reg(core->vact_space_1, 2, 0xffff);
1775 hdmi_set_reg(core->vact_space_2, 2, 0xffff);
1776 hdmi_set_reg(core->vact_space_3, 2, 0xffff);
1777 hdmi_set_reg(core->vact_space_4, 2, 0xffff);
1778 hdmi_set_reg(core->vact_space_5, 2, 0xffff);
1779 hdmi_set_reg(core->vact_space_6, 2, 0xffff);
1780 hdmi_set_reg(core->v_blank_f2, 2, 0xffff);
1781 hdmi_set_reg(core->v_blank_f3, 2, 0xffff);
1782 hdmi_set_reg(core->v_blank_f4, 2, 0xffff);
1783 hdmi_set_reg(core->v_blank_f5, 2, 0xffff);
1784 hdmi_set_reg(core->v_sync_line_aft_3, 2, 0xffff);
1785 hdmi_set_reg(core->v_sync_line_aft_4, 2, 0xffff);
1786 hdmi_set_reg(core->v_sync_line_aft_5, 2, 0xffff);
1787 hdmi_set_reg(core->v_sync_line_aft_6, 2, 0xffff);
1788 hdmi_set_reg(core->v_sync_line_aft_pxl_3, 2, 0xffff);
1789 hdmi_set_reg(core->v_sync_line_aft_pxl_4, 2, 0xffff);
1790 hdmi_set_reg(core->v_sync_line_aft_pxl_5, 2, 0xffff);
1791 hdmi_set_reg(core->v_sync_line_aft_pxl_6, 2, 0xffff);
1793 /* Timing generator registers */
1794 hdmi_set_reg(tg->cmd, 1, 0x0);
1795 hdmi_set_reg(tg->h_fsz, 2, m->htotal);
1796 hdmi_set_reg(tg->hact_st, 2, m->htotal - m->hdisplay);
1797 hdmi_set_reg(tg->hact_sz, 2, m->hdisplay);
1798 hdmi_set_reg(tg->v_fsz, 2, m->vtotal);
1799 hdmi_set_reg(tg->vsync, 2, 0x1);
1800 hdmi_set_reg(tg->field_chg, 2, 0x233); /* Reset value */
1801 hdmi_set_reg(tg->vsync_top_hdmi, 2, 0x1); /* Reset value */
1802 hdmi_set_reg(tg->field_top_hdmi, 2, 0x1); /* Reset value */
1803 hdmi_set_reg(tg->tg_3d, 1, 0x0);
1806 static void hdmi_mode_set(struct exynos_drm_display *display,
1807 struct drm_display_mode *mode)
1809 struct hdmi_context *hdata = display->ctx;
1810 struct drm_display_mode *m = mode;
1812 DRM_DEBUG_KMS("xres=%d, yres=%d, refresh=%d, intl=%s\n",
1813 m->hdisplay, m->vdisplay,
1814 m->vrefresh, (m->flags & DRM_MODE_FLAG_INTERLACE) ?
1815 "INTERLACED" : "PROGERESSIVE");
1817 if (hdata->type == HDMI_TYPE13)
1818 hdmi_v13_mode_set(hdata, mode);
1820 hdmi_v14_mode_set(hdata, mode);
1823 static void hdmi_commit(struct exynos_drm_display *display)
1825 struct hdmi_context *hdata = display->ctx;
1827 mutex_lock(&hdata->hdmi_mutex);
1828 if (!hdata->powered) {
1829 mutex_unlock(&hdata->hdmi_mutex);
1832 mutex_unlock(&hdata->hdmi_mutex);
1834 hdmi_conf_apply(hdata);
1837 static void hdmi_poweron(struct exynos_drm_display *display)
1839 struct hdmi_context *hdata = display->ctx;
1840 struct hdmi_resources *res = &hdata->res;
1842 mutex_lock(&hdata->hdmi_mutex);
1843 if (hdata->powered) {
1844 mutex_unlock(&hdata->hdmi_mutex);
1848 hdata->powered = true;
1850 mutex_unlock(&hdata->hdmi_mutex);
1852 pm_runtime_get_sync(hdata->dev);
1854 if (regulator_bulk_enable(res->regul_count, res->regul_bulk))
1855 DRM_DEBUG_KMS("failed to enable regulator bulk\n");
1857 clk_prepare_enable(res->hdmiphy);
1858 clk_prepare_enable(res->hdmi);
1859 clk_prepare_enable(res->sclk_hdmi);
1861 hdmiphy_poweron(hdata);
1862 hdmi_commit(display);
1865 static void hdmi_poweroff(struct exynos_drm_display *display)
1867 struct hdmi_context *hdata = display->ctx;
1868 struct hdmi_resources *res = &hdata->res;
1870 mutex_lock(&hdata->hdmi_mutex);
1871 if (!hdata->powered)
1873 mutex_unlock(&hdata->hdmi_mutex);
1876 * The TV power domain needs any condition of hdmiphy to turn off and
1877 * its reset state seems to meet the condition.
1879 hdmiphy_conf_reset(hdata);
1880 hdmiphy_poweroff(hdata);
1882 clk_disable_unprepare(res->sclk_hdmi);
1883 clk_disable_unprepare(res->hdmi);
1884 clk_disable_unprepare(res->hdmiphy);
1885 regulator_bulk_disable(res->regul_count, res->regul_bulk);
1887 pm_runtime_put_sync(hdata->dev);
1889 mutex_lock(&hdata->hdmi_mutex);
1890 hdata->powered = false;
1893 mutex_unlock(&hdata->hdmi_mutex);
1896 static void hdmi_dpms(struct exynos_drm_display *display, int mode)
1898 DRM_DEBUG_KMS("mode %d\n", mode);
1901 case DRM_MODE_DPMS_ON:
1902 hdmi_poweron(display);
1904 case DRM_MODE_DPMS_STANDBY:
1905 case DRM_MODE_DPMS_SUSPEND:
1906 case DRM_MODE_DPMS_OFF:
1907 hdmi_poweroff(display);
1910 DRM_DEBUG_KMS("unknown dpms mode: %d\n", mode);
1915 static struct exynos_drm_display_ops hdmi_display_ops = {
1916 .initialize = hdmi_initialize,
1917 .create_connector = hdmi_create_connector,
1918 .mode_fixup = hdmi_mode_fixup,
1919 .mode_set = hdmi_mode_set,
1921 .commit = hdmi_commit,
1924 static struct exynos_drm_display hdmi_display = {
1925 .type = EXYNOS_DISPLAY_TYPE_HDMI,
1926 .ops = &hdmi_display_ops,
1929 static irqreturn_t hdmi_irq_thread(int irq, void *arg)
1931 struct hdmi_context *hdata = arg;
1933 mutex_lock(&hdata->hdmi_mutex);
1934 hdata->hpd = gpio_get_value(hdata->hpd_gpio);
1935 mutex_unlock(&hdata->hdmi_mutex);
1938 drm_helper_hpd_irq_event(hdata->drm_dev);
1943 static int hdmi_resources_init(struct hdmi_context *hdata)
1945 struct device *dev = hdata->dev;
1946 struct hdmi_resources *res = &hdata->res;
1947 static char *supply[] = {
1955 DRM_DEBUG_KMS("HDMI resource init\n");
1957 memset(res, 0, sizeof(*res));
1959 /* get clocks, power */
1960 res->hdmi = devm_clk_get(dev, "hdmi");
1961 if (IS_ERR(res->hdmi)) {
1962 DRM_ERROR("failed to get clock 'hdmi'\n");
1965 res->sclk_hdmi = devm_clk_get(dev, "sclk_hdmi");
1966 if (IS_ERR(res->sclk_hdmi)) {
1967 DRM_ERROR("failed to get clock 'sclk_hdmi'\n");
1970 res->sclk_pixel = devm_clk_get(dev, "sclk_pixel");
1971 if (IS_ERR(res->sclk_pixel)) {
1972 DRM_ERROR("failed to get clock 'sclk_pixel'\n");
1975 res->sclk_hdmiphy = devm_clk_get(dev, "sclk_hdmiphy");
1976 if (IS_ERR(res->sclk_hdmiphy)) {
1977 DRM_ERROR("failed to get clock 'sclk_hdmiphy'\n");
1980 res->hdmiphy = devm_clk_get(dev, "hdmiphy");
1981 if (IS_ERR(res->hdmiphy)) {
1982 DRM_ERROR("failed to get clock 'hdmiphy'\n");
1985 res->mout_hdmi = devm_clk_get(dev, "mout_hdmi");
1986 if (IS_ERR(res->mout_hdmi)) {
1987 DRM_ERROR("failed to get clock 'mout_hdmi'\n");
1991 clk_set_parent(res->mout_hdmi, res->sclk_pixel);
1993 res->regul_bulk = devm_kzalloc(dev, ARRAY_SIZE(supply) *
1994 sizeof(res->regul_bulk[0]), GFP_KERNEL);
1995 if (!res->regul_bulk)
1997 for (i = 0; i < ARRAY_SIZE(supply); ++i) {
1998 res->regul_bulk[i].supply = supply[i];
1999 res->regul_bulk[i].consumer = NULL;
2001 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(supply), res->regul_bulk);
2003 DRM_ERROR("failed to get regulators\n");
2006 res->regul_count = ARRAY_SIZE(supply);
2010 DRM_ERROR("HDMI resource init - failed\n");
2014 static struct s5p_hdmi_platform_data *drm_hdmi_dt_parse_pdata
2015 (struct device *dev)
2017 struct device_node *np = dev->of_node;
2018 struct s5p_hdmi_platform_data *pd;
2021 pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
2025 if (!of_find_property(np, "hpd-gpio", &value)) {
2026 DRM_ERROR("no hpd gpio property found\n");
2030 pd->hpd_gpio = of_get_named_gpio(np, "hpd-gpio", 0);
2038 static struct of_device_id hdmi_match_types[] = {
2040 .compatible = "samsung,exynos5-hdmi",
2041 .data = &exynos5_hdmi_driver_data,
2043 .compatible = "samsung,exynos4212-hdmi",
2044 .data = &exynos4212_hdmi_driver_data,
2050 static int hdmi_probe(struct platform_device *pdev)
2052 struct device *dev = &pdev->dev;
2053 struct hdmi_context *hdata;
2054 struct s5p_hdmi_platform_data *pdata;
2055 struct resource *res;
2056 const struct of_device_id *match;
2057 struct device_node *ddc_node, *phy_node;
2058 struct hdmi_driver_data *drv_data;
2064 pdata = drm_hdmi_dt_parse_pdata(dev);
2068 hdata = devm_kzalloc(dev, sizeof(struct hdmi_context), GFP_KERNEL);
2072 mutex_init(&hdata->hdmi_mutex);
2074 platform_set_drvdata(pdev, &hdmi_display);
2076 match = of_match_node(hdmi_match_types, dev->of_node);
2080 drv_data = (struct hdmi_driver_data *)match->data;
2081 hdata->type = drv_data->type;
2083 hdata->hpd_gpio = pdata->hpd_gpio;
2086 ret = hdmi_resources_init(hdata);
2088 DRM_ERROR("hdmi_resources_init failed\n");
2092 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2093 hdata->regs = devm_ioremap_resource(dev, res);
2094 if (IS_ERR(hdata->regs))
2095 return PTR_ERR(hdata->regs);
2097 ret = devm_gpio_request(dev, hdata->hpd_gpio, "HPD");
2099 DRM_ERROR("failed to request HPD gpio\n");
2103 /* DDC i2c driver */
2104 ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
2106 DRM_ERROR("Failed to find ddc node in device tree\n");
2109 hdata->ddc_adpt = of_find_i2c_adapter_by_node(ddc_node);
2110 if (!hdata->ddc_adpt) {
2111 DRM_ERROR("Failed to get ddc i2c adapter by node\n");
2115 /* Not support APB PHY yet. */
2116 if (drv_data->is_apb_phy)
2119 /* hdmiphy i2c driver */
2120 phy_node = of_parse_phandle(dev->of_node, "phy", 0);
2122 DRM_ERROR("Failed to find hdmiphy node in device tree\n");
2126 hdata->hdmiphy_port = of_find_i2c_device_by_node(phy_node);
2127 if (!hdata->hdmiphy_port) {
2128 DRM_ERROR("Failed to get hdmi phy i2c client from node\n");
2133 hdata->irq = gpio_to_irq(hdata->hpd_gpio);
2134 if (hdata->irq < 0) {
2135 DRM_ERROR("failed to get GPIO irq\n");
2140 hdata->hpd = gpio_get_value(hdata->hpd_gpio);
2142 ret = devm_request_threaded_irq(dev, hdata->irq, NULL,
2143 hdmi_irq_thread, IRQF_TRIGGER_RISING |
2144 IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
2147 DRM_ERROR("failed to register hdmi interrupt\n");
2151 pm_runtime_enable(dev);
2153 hdmi_display.ctx = hdata;
2154 exynos_drm_display_register(&hdmi_display);
2159 put_device(&hdata->hdmiphy_port->dev);
2161 put_device(&hdata->ddc_adpt->dev);
2165 static int hdmi_remove(struct platform_device *pdev)
2167 struct device *dev = &pdev->dev;
2168 struct exynos_drm_display *display = get_hdmi_display(dev);
2169 struct hdmi_context *hdata = display->ctx;
2171 put_device(&hdata->hdmiphy_port->dev);
2172 put_device(&hdata->ddc_adpt->dev);
2173 pm_runtime_disable(&pdev->dev);
2178 struct platform_driver hdmi_driver = {
2179 .probe = hdmi_probe,
2180 .remove = hdmi_remove,
2182 .name = "exynos-hdmi",
2183 .owner = THIS_MODULE,
2184 .of_match_table = hdmi_match_types,