1 /**************************************************************************
2 * Copyright (c) 2011, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 **************************************************************************/
20 #include <linux/backlight.h>
23 #include <drm/gma_drm.h>
26 #include "psb_intel_reg.h"
27 #include "intel_bios.h"
28 #include "cdv_device.h"
29 #include "gma_device.h"
31 #define VGA_SR_INDEX 0x3c4
32 #define VGA_SR_DATA 0x3c5
34 static void cdv_disable_vga(struct drm_device *dev)
41 outb(1, VGA_SR_INDEX);
42 sr1 = inb(VGA_SR_DATA);
43 outb(sr1 | 1<<5, VGA_SR_DATA);
46 REG_WRITE(vga_reg, VGA_DISP_DISABLE);
50 static int cdv_output_init(struct drm_device *dev)
52 struct drm_psb_private *dev_priv = dev->dev_private;
54 drm_mode_create_scaling_mode_property(dev);
58 cdv_intel_crt_init(dev, &dev_priv->mode_dev);
59 cdv_intel_lvds_init(dev, &dev_priv->mode_dev);
61 /* These bits indicate HDMI not SDVO on CDV */
62 if (REG_READ(SDVOB) & SDVO_DETECTED) {
63 cdv_hdmi_init(dev, &dev_priv->mode_dev, SDVOB);
64 if (REG_READ(DP_B) & DP_DETECTED)
65 cdv_intel_dp_init(dev, &dev_priv->mode_dev, DP_B);
68 if (REG_READ(SDVOC) & SDVO_DETECTED) {
69 cdv_hdmi_init(dev, &dev_priv->mode_dev, SDVOC);
70 if (REG_READ(DP_C) & DP_DETECTED)
71 cdv_intel_dp_init(dev, &dev_priv->mode_dev, DP_C);
76 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
79 * Cedartrail Backlght Interfaces
82 static struct backlight_device *cdv_backlight_device;
84 static int cdv_backlight_combination_mode(struct drm_device *dev)
86 return REG_READ(BLC_PWM_CTL2) & PWM_LEGACY_MODE;
89 static u32 cdv_get_max_backlight(struct drm_device *dev)
91 u32 max = REG_READ(BLC_PWM_CTL);
94 DRM_DEBUG_KMS("LVDS Panel PWM value is 0!\n");
95 /* i915 does this, I believe which means that we should not
96 * smash PWM control as firmware will take control of it. */
101 if (cdv_backlight_combination_mode(dev))
106 static int cdv_get_brightness(struct backlight_device *bd)
108 struct drm_device *dev = bl_get_data(bd);
109 u32 val = REG_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
111 if (cdv_backlight_combination_mode(dev)) {
115 pci_read_config_byte(dev->pdev, 0xF4, &lbpc);
118 return (val * 100)/cdv_get_max_backlight(dev);
122 static int cdv_set_brightness(struct backlight_device *bd)
124 struct drm_device *dev = bl_get_data(bd);
125 int level = bd->props.brightness;
128 /* Percentage 1-100% being valid */
132 level *= cdv_get_max_backlight(dev);
135 if (cdv_backlight_combination_mode(dev)) {
136 u32 max = cdv_get_max_backlight(dev);
139 lbpc = level * 0xfe / max + 1;
142 pci_write_config_byte(dev->pdev, 0xF4, lbpc);
145 blc_pwm_ctl = REG_READ(BLC_PWM_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;
146 REG_WRITE(BLC_PWM_CTL, (blc_pwm_ctl |
147 (level << BACKLIGHT_DUTY_CYCLE_SHIFT)));
151 static const struct backlight_ops cdv_ops = {
152 .get_brightness = cdv_get_brightness,
153 .update_status = cdv_set_brightness,
156 static int cdv_backlight_init(struct drm_device *dev)
158 struct drm_psb_private *dev_priv = dev->dev_private;
159 struct backlight_properties props;
161 memset(&props, 0, sizeof(struct backlight_properties));
162 props.max_brightness = 100;
163 props.type = BACKLIGHT_PLATFORM;
165 cdv_backlight_device = backlight_device_register("psb-bl",
166 NULL, (void *)dev, &cdv_ops, &props);
167 if (IS_ERR(cdv_backlight_device))
168 return PTR_ERR(cdv_backlight_device);
170 cdv_backlight_device->props.brightness =
171 cdv_get_brightness(cdv_backlight_device);
172 backlight_update_status(cdv_backlight_device);
173 dev_priv->backlight_device = cdv_backlight_device;
174 dev_priv->backlight_enabled = true;
181 * Provide the Cedarview specific chip logic and low level methods
182 * for power management
184 * FIXME: we need to implement the apm/ospm base management bits
185 * for this and the MID devices.
188 static inline u32 CDV_MSG_READ32(uint port, uint offset)
190 int mcr = (0x10<<24) | (port << 16) | (offset << 8);
191 uint32_t ret_val = 0;
192 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
193 pci_write_config_dword(pci_root, 0xD0, mcr);
194 pci_read_config_dword(pci_root, 0xD4, &ret_val);
195 pci_dev_put(pci_root);
199 static inline void CDV_MSG_WRITE32(uint port, uint offset, u32 value)
201 int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0;
202 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
203 pci_write_config_dword(pci_root, 0xD4, value);
204 pci_write_config_dword(pci_root, 0xD0, mcr);
205 pci_dev_put(pci_root);
208 #define PSB_PM_SSC 0x20
209 #define PSB_PM_SSS 0x30
210 #define PSB_PWRGT_GFX_ON 0x02
211 #define PSB_PWRGT_GFX_OFF 0x01
212 #define PSB_PWRGT_GFX_D0 0x00
213 #define PSB_PWRGT_GFX_D3 0x03
215 static void cdv_init_pm(struct drm_device *dev)
217 struct drm_psb_private *dev_priv = dev->dev_private;
221 dev_priv->apm_base = CDV_MSG_READ32(PSB_PUNIT_PORT,
223 dev_priv->ospm_base = CDV_MSG_READ32(PSB_PUNIT_PORT,
224 PSB_OSPMBA) & 0xFFFF;
227 pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD);
230 pwr_cnt &= ~PSB_PWRGT_GFX_MASK;
231 pwr_cnt |= PSB_PWRGT_GFX_ON;
232 outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD);
234 /* Wait for the GPU power */
235 for (i = 0; i < 5; i++) {
236 u32 pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS);
237 if ((pwr_sts & PSB_PWRGT_GFX_MASK) == 0)
241 dev_err(dev->dev, "GPU: power management timed out.\n");
244 static void cdv_errata(struct drm_device *dev)
246 /* Disable bonus launch.
247 * CPU and GPU competes for memory and display misses updates and
248 * flickers. Worst with dual core, dual displays.
250 * Fixes were done to Win 7 gfx driver to disable a feature called
251 * Bonus Launch to work around the issue, by degrading
254 CDV_MSG_WRITE32(3, 0x30, 0x08027108);
258 * cdv_save_display_registers - save registers lost on suspend
259 * @dev: our DRM device
261 * Save the state we need in order to be able to restore the interface
262 * upon resume from suspend
264 static int cdv_save_display_registers(struct drm_device *dev)
266 struct drm_psb_private *dev_priv = dev->dev_private;
267 struct psb_save_area *regs = &dev_priv->regs;
268 struct drm_connector *connector;
270 dev_dbg(dev->dev, "Saving GPU registers.\n");
272 pci_read_config_byte(dev->pdev, 0xF4, ®s->cdv.saveLBB);
274 regs->cdv.saveDSPCLK_GATE_D = REG_READ(DSPCLK_GATE_D);
275 regs->cdv.saveRAMCLK_GATE_D = REG_READ(RAMCLK_GATE_D);
277 regs->cdv.saveDSPARB = REG_READ(DSPARB);
278 regs->cdv.saveDSPFW[0] = REG_READ(DSPFW1);
279 regs->cdv.saveDSPFW[1] = REG_READ(DSPFW2);
280 regs->cdv.saveDSPFW[2] = REG_READ(DSPFW3);
281 regs->cdv.saveDSPFW[3] = REG_READ(DSPFW4);
282 regs->cdv.saveDSPFW[4] = REG_READ(DSPFW5);
283 regs->cdv.saveDSPFW[5] = REG_READ(DSPFW6);
285 regs->cdv.saveADPA = REG_READ(ADPA);
287 regs->cdv.savePP_CONTROL = REG_READ(PP_CONTROL);
288 regs->cdv.savePFIT_PGM_RATIOS = REG_READ(PFIT_PGM_RATIOS);
289 regs->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL);
290 regs->saveBLC_PWM_CTL2 = REG_READ(BLC_PWM_CTL2);
291 regs->cdv.saveLVDS = REG_READ(LVDS);
293 regs->cdv.savePFIT_CONTROL = REG_READ(PFIT_CONTROL);
295 regs->cdv.savePP_ON_DELAYS = REG_READ(PP_ON_DELAYS);
296 regs->cdv.savePP_OFF_DELAYS = REG_READ(PP_OFF_DELAYS);
297 regs->cdv.savePP_CYCLE = REG_READ(PP_CYCLE);
299 regs->cdv.saveVGACNTRL = REG_READ(VGACNTRL);
301 regs->cdv.saveIER = REG_READ(PSB_INT_ENABLE_R);
302 regs->cdv.saveIMR = REG_READ(PSB_INT_MASK_R);
304 list_for_each_entry(connector, &dev->mode_config.connector_list, head)
305 connector->funcs->dpms(connector, DRM_MODE_DPMS_OFF);
311 * cdv_restore_display_registers - restore lost register state
312 * @dev: our DRM device
314 * Restore register state that was lost during suspend and resume.
318 static int cdv_restore_display_registers(struct drm_device *dev)
320 struct drm_psb_private *dev_priv = dev->dev_private;
321 struct psb_save_area *regs = &dev_priv->regs;
322 struct drm_connector *connector;
325 pci_write_config_byte(dev->pdev, 0xF4, regs->cdv.saveLBB);
327 REG_WRITE(DSPCLK_GATE_D, regs->cdv.saveDSPCLK_GATE_D);
328 REG_WRITE(RAMCLK_GATE_D, regs->cdv.saveRAMCLK_GATE_D);
330 /* BIOS does below anyway */
331 REG_WRITE(DPIO_CFG, 0);
332 REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 | DPIO_CMN_RESET_N);
334 temp = REG_READ(DPLL_A);
335 if ((temp & DPLL_SYNCLOCK_ENABLE) == 0) {
336 REG_WRITE(DPLL_A, temp | DPLL_SYNCLOCK_ENABLE);
340 temp = REG_READ(DPLL_B);
341 if ((temp & DPLL_SYNCLOCK_ENABLE) == 0) {
342 REG_WRITE(DPLL_B, temp | DPLL_SYNCLOCK_ENABLE);
348 REG_WRITE(DSPFW1, regs->cdv.saveDSPFW[0]);
349 REG_WRITE(DSPFW2, regs->cdv.saveDSPFW[1]);
350 REG_WRITE(DSPFW3, regs->cdv.saveDSPFW[2]);
351 REG_WRITE(DSPFW4, regs->cdv.saveDSPFW[3]);
352 REG_WRITE(DSPFW5, regs->cdv.saveDSPFW[4]);
353 REG_WRITE(DSPFW6, regs->cdv.saveDSPFW[5]);
355 REG_WRITE(DSPARB, regs->cdv.saveDSPARB);
356 REG_WRITE(ADPA, regs->cdv.saveADPA);
358 REG_WRITE(BLC_PWM_CTL2, regs->saveBLC_PWM_CTL2);
359 REG_WRITE(LVDS, regs->cdv.saveLVDS);
360 REG_WRITE(PFIT_CONTROL, regs->cdv.savePFIT_CONTROL);
361 REG_WRITE(PFIT_PGM_RATIOS, regs->cdv.savePFIT_PGM_RATIOS);
362 REG_WRITE(BLC_PWM_CTL, regs->saveBLC_PWM_CTL);
363 REG_WRITE(PP_ON_DELAYS, regs->cdv.savePP_ON_DELAYS);
364 REG_WRITE(PP_OFF_DELAYS, regs->cdv.savePP_OFF_DELAYS);
365 REG_WRITE(PP_CYCLE, regs->cdv.savePP_CYCLE);
366 REG_WRITE(PP_CONTROL, regs->cdv.savePP_CONTROL);
368 REG_WRITE(VGACNTRL, regs->cdv.saveVGACNTRL);
370 REG_WRITE(PSB_INT_ENABLE_R, regs->cdv.saveIER);
371 REG_WRITE(PSB_INT_MASK_R, regs->cdv.saveIMR);
373 /* Fix arbitration bug */
376 drm_mode_config_reset(dev);
378 list_for_each_entry(connector, &dev->mode_config.connector_list, head)
379 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
381 /* Resume the modeset for every activated CRTC */
382 drm_helper_resume_force_mode(dev);
386 static int cdv_power_down(struct drm_device *dev)
388 struct drm_psb_private *dev_priv = dev->dev_private;
389 u32 pwr_cnt, pwr_mask, pwr_sts;
392 pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD);
393 pwr_cnt &= ~PSB_PWRGT_GFX_MASK;
394 pwr_cnt |= PSB_PWRGT_GFX_OFF;
395 pwr_mask = PSB_PWRGT_GFX_MASK;
397 outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD);
400 pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS);
401 if ((pwr_sts & pwr_mask) == PSB_PWRGT_GFX_D3)
408 static int cdv_power_up(struct drm_device *dev)
410 struct drm_psb_private *dev_priv = dev->dev_private;
411 u32 pwr_cnt, pwr_mask, pwr_sts;
414 pwr_cnt = inl(dev_priv->apm_base + PSB_APM_CMD);
415 pwr_cnt &= ~PSB_PWRGT_GFX_MASK;
416 pwr_cnt |= PSB_PWRGT_GFX_ON;
417 pwr_mask = PSB_PWRGT_GFX_MASK;
419 outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD);
422 pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS);
423 if ((pwr_sts & pwr_mask) == PSB_PWRGT_GFX_D0)
430 static void cdv_hotplug_work_func(struct work_struct *work)
432 struct drm_psb_private *dev_priv = container_of(work, struct drm_psb_private,
434 struct drm_device *dev = dev_priv->dev;
436 /* Just fire off a uevent and let userspace tell us what to do */
437 drm_helper_hpd_irq_event(dev);
440 /* The core driver has received a hotplug IRQ. We are in IRQ context
441 so extract the needed information and kick off queued processing */
443 static int cdv_hotplug_event(struct drm_device *dev)
445 struct drm_psb_private *dev_priv = dev->dev_private;
446 schedule_work(&dev_priv->hotplug_work);
447 REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT));
451 static void cdv_hotplug_enable(struct drm_device *dev, bool on)
454 u32 hotplug = REG_READ(PORT_HOTPLUG_EN);
455 hotplug |= HDMIB_HOTPLUG_INT_EN | HDMIC_HOTPLUG_INT_EN |
456 HDMID_HOTPLUG_INT_EN | CRT_HOTPLUG_INT_EN;
457 REG_WRITE(PORT_HOTPLUG_EN, hotplug);
459 REG_WRITE(PORT_HOTPLUG_EN, 0);
460 REG_WRITE(PORT_HOTPLUG_STAT, REG_READ(PORT_HOTPLUG_STAT));
464 static const char *force_audio_names[] = {
470 void cdv_intel_attach_force_audio_property(struct drm_connector *connector)
472 struct drm_device *dev = connector->dev;
473 struct drm_psb_private *dev_priv = dev->dev_private;
474 struct drm_property *prop;
477 prop = dev_priv->force_audio_property;
479 prop = drm_property_create(dev, DRM_MODE_PROP_ENUM,
481 ARRAY_SIZE(force_audio_names));
485 for (i = 0; i < ARRAY_SIZE(force_audio_names); i++)
486 drm_property_add_enum(prop, i, i-1, force_audio_names[i]);
488 dev_priv->force_audio_property = prop;
490 drm_object_attach_property(&connector->base, prop, 0);
494 static const char *broadcast_rgb_names[] = {
499 void cdv_intel_attach_broadcast_rgb_property(struct drm_connector *connector)
501 struct drm_device *dev = connector->dev;
502 struct drm_psb_private *dev_priv = dev->dev_private;
503 struct drm_property *prop;
506 prop = dev_priv->broadcast_rgb_property;
508 prop = drm_property_create(dev, DRM_MODE_PROP_ENUM,
510 ARRAY_SIZE(broadcast_rgb_names));
514 for (i = 0; i < ARRAY_SIZE(broadcast_rgb_names); i++)
515 drm_property_add_enum(prop, i, i, broadcast_rgb_names[i]);
517 dev_priv->broadcast_rgb_property = prop;
520 drm_object_attach_property(&connector->base, prop, 0);
524 static const struct psb_offset cdv_regmap[2] = {
532 .dpll_md = DPLL_A_MD,
539 .stride = DSPASTRIDE,
546 .linoff = DSPALINOFF,
547 .tileoff = DSPATILEOFF,
548 .palette = PALETTE_A,
557 .dpll_md = DPLL_B_MD,
564 .stride = DSPBSTRIDE,
571 .linoff = DSPBLINOFF,
572 .tileoff = DSPBTILEOFF,
573 .palette = PALETTE_B,
577 static int cdv_chip_setup(struct drm_device *dev)
579 struct drm_psb_private *dev_priv = dev->dev_private;
580 INIT_WORK(&dev_priv->hotplug_work, cdv_hotplug_work_func);
582 if (pci_enable_msi(dev->pdev))
583 dev_warn(dev->dev, "Enabling MSI failed!\n");
584 dev_priv->regmap = cdv_regmap;
585 gma_get_core_freq(dev);
586 psb_intel_opregion_init(dev);
587 psb_intel_init_bios(dev);
588 cdv_hotplug_enable(dev, false);
592 /* CDV is much like Poulsbo but has MID like SGX offsets and PM */
594 const struct psb_ops cdv_chip_ops = {
595 .name = "GMA3600/3650",
599 .hdmi_mask = (1 << 0) | (1 << 1),
600 .lvds_mask = (1 << 1),
601 .sdvo_mask = (1 << 0),
602 .cursor_needs_phys = 0,
603 .sgx_offset = MRST_SGX_OFFSET,
604 .chip_setup = cdv_chip_setup,
605 .errata = cdv_errata,
607 .crtc_helper = &cdv_intel_helper_funcs,
608 .crtc_funcs = &cdv_intel_crtc_funcs,
609 .clock_funcs = &cdv_clock_funcs,
611 .output_init = cdv_output_init,
612 .hotplug = cdv_hotplug_event,
613 .hotplug_enable = cdv_hotplug_enable,
615 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
616 .backlight_init = cdv_backlight_init,
619 .init_pm = cdv_init_pm,
620 .save_regs = cdv_save_display_registers,
621 .restore_regs = cdv_restore_display_registers,
622 .save_crtc = gma_crtc_save,
623 .restore_crtc = gma_crtc_restore,
624 .power_down = cdv_power_down,
625 .power_up = cdv_power_up,
626 .update_wm = cdv_update_wm,
627 .disable_sr = cdv_disable_sr,