drivers/gpu/drm/gma500/cdv_intel_display.c

   1 /*
   2  * Copyright © 2006-2011 Intel Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program; if not, write to the Free Software Foundation, Inc.,
  15  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  16  *
  17  * Authors:
  18  *      Eric Anholt <eric@anholt.net>
  19  */
  20
  21 #include <linux/i2c.h>
  22 #include <linux/pm_runtime.h>
  23
  24 #include <drm/drmP.h>
  25 #include "framebuffer.h"
  26 #include "psb_drv.h"
  27 #include "psb_intel_drv.h"
  28 #include "psb_intel_reg.h"
  29 #include "psb_intel_display.h"
  30 #include "power.h"
  31 #include "cdv_device.h"
  32
  33
  34 struct cdv_intel_range_t {
  35         int min, max;
  36 };
  37
  38 struct cdv_intel_p2_t {
  39         int dot_limit;
  40         int p2_slow, p2_fast;
  41 };
  42
  43 struct cdv_intel_clock_t {
  44         /* given values */
  45         int n;
  46         int m1, m2;
  47         int p1, p2;
  48         /* derived values */
  49         int dot;
  50         int vco;
  51         int m;
  52         int p;
  53 };
  54
  55 #define INTEL_P2_NUM                  2
  56
  57 struct cdv_intel_limit_t {
  58         struct cdv_intel_range_t dot, vco, n, m, m1, m2, p, p1;
  59         struct cdv_intel_p2_t p2;
  60 };
  61
  62 #define CDV_LIMIT_SINGLE_LVDS_96        0
  63 #define CDV_LIMIT_SINGLE_LVDS_100       1
  64 #define CDV_LIMIT_DAC_HDMI_27           2
  65 #define CDV_LIMIT_DAC_HDMI_96           3
  66
  67 static const struct cdv_intel_limit_t cdv_intel_limits[] = {
  68         {                       /* CDV_SIGNLE_LVDS_96MHz */
  69          .dot = {.min = 20000, .max = 115500},
  70          .vco = {.min = 1800000, .max = 3600000},
  71          .n = {.min = 2, .max = 6},
  72          .m = {.min = 60, .max = 160},
  73          .m1 = {.min = 0, .max = 0},
  74          .m2 = {.min = 58, .max = 158},
  75          .p = {.min = 28, .max = 140},
  76          .p1 = {.min = 2, .max = 10},
  77          .p2 = {.dot_limit = 200000,
  78                 .p2_slow = 14, .p2_fast = 14},
  79          },
  80         {                       /* CDV_SINGLE_LVDS_100MHz */
  81          .dot = {.min = 20000, .max = 115500},
  82          .vco = {.min = 1800000, .max = 3600000},
  83          .n = {.min = 2, .max = 6},
  84          .m = {.min = 60, .max = 160},
  85          .m1 = {.min = 0, .max = 0},
  86          .m2 = {.min = 58, .max = 158},
  87          .p = {.min = 28, .max = 140},
  88          .p1 = {.min = 2, .max = 10},
  89          /* The single-channel range is 25-112Mhz, and dual-channel
  90           * is 80-224Mhz.  Prefer single channel as much as possible.
  91           */
  92          .p2 = {.dot_limit = 200000, .p2_slow = 14, .p2_fast = 14},
  93          },
  94         {                       /* CDV_DAC_HDMI_27MHz */
  95          .dot = {.min = 20000, .max = 400000},
  96          .vco = {.min = 1809000, .max = 3564000},
  97          .n = {.min = 1, .max = 1},
  98          .m = {.min = 67, .max = 132},
  99          .m1 = {.min = 0, .max = 0},
 100          .m2 = {.min = 65, .max = 130},
 101          .p = {.min = 5, .max = 90},
 102          .p1 = {.min = 1, .max = 9},
 103          .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 5},
 104          },
 105         {                       /* CDV_DAC_HDMI_96MHz */
 106          .dot = {.min = 20000, .max = 400000},
 107          .vco = {.min = 1800000, .max = 3600000},
 108          .n = {.min = 2, .max = 6},
 109          .m = {.min = 60, .max = 160},
 110          .m1 = {.min = 0, .max = 0},
 111          .m2 = {.min = 58, .max = 158},
 112          .p = {.min = 5, .max = 100},
 113          .p1 = {.min = 1, .max = 10},
 114          .p2 = {.dot_limit = 225000, .p2_slow = 10, .p2_fast = 5},
 115          },
 116 };
 117
 118 #define _wait_for(COND, MS, W) ({ \
 119         unsigned long timeout__ = jiffies + msecs_to_jiffies(MS);       \
 120         int ret__ = 0;                                                  \
 121         while (!(COND)) {                                               \
 122                 if (time_after(jiffies, timeout__)) {                   \
 123                         ret__ = -ETIMEDOUT;                             \
 124                         break;                                          \
 125                 }                                                       \
 126                 if (W && !in_dbg_master())                              \
 127                         msleep(W);                                      \
 128         }                                                               \
 129         ret__;                                                          \
 130 })
 131
 132 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
 133
 134
 135 static int cdv_sb_read(struct drm_device *dev, u32 reg, u32 *val)
 136 {
 137         int ret;
 138
 139         ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
 140         if (ret) {
 141                 DRM_ERROR("timeout waiting for SB to idle before read\n");
 142                 return ret;
 143         }
 144
 145         REG_WRITE(SB_ADDR, reg);
 146         REG_WRITE(SB_PCKT,
 147                    SET_FIELD(SB_OPCODE_READ, SB_OPCODE) |
 148                    SET_FIELD(SB_DEST_DPLL, SB_DEST) |
 149                    SET_FIELD(0xf, SB_BYTE_ENABLE));
 150
 151         ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
 152         if (ret) {
 153                 DRM_ERROR("timeout waiting for SB to idle after read\n");
 154                 return ret;
 155         }
 156
 157         *val = REG_READ(SB_DATA);
 158
 159         return 0;
 160 }
 161
 162 static int cdv_sb_write(struct drm_device *dev, u32 reg, u32 val)
 163 {
 164         int ret;
 165         static bool dpio_debug = true;
 166         u32 temp;
 167
 168         if (dpio_debug) {
 169                 if (cdv_sb_read(dev, reg, &temp) == 0)
 170                         DRM_DEBUG_KMS("0x%08x: 0x%08x (before)\n", reg, temp);
 171                 DRM_DEBUG_KMS("0x%08x: 0x%08x\n", reg, val);
 172         }
 173
 174         ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
 175         if (ret) {
 176                 DRM_ERROR("timeout waiting for SB to idle before write\n");
 177                 return ret;
 178         }
 179
 180         REG_WRITE(SB_ADDR, reg);
 181         REG_WRITE(SB_DATA, val);
 182         REG_WRITE(SB_PCKT,
 183                    SET_FIELD(SB_OPCODE_WRITE, SB_OPCODE) |
 184                    SET_FIELD(SB_DEST_DPLL, SB_DEST) |
 185                    SET_FIELD(0xf, SB_BYTE_ENABLE));
 186
 187         ret = wait_for((REG_READ(SB_PCKT) & SB_BUSY) == 0, 1000);
 188         if (ret) {
 189                 DRM_ERROR("timeout waiting for SB to idle after write\n");
 190                 return ret;
 191         }
 192
 193         if (dpio_debug) {
 194                 if (cdv_sb_read(dev, reg, &temp) == 0)
 195                         DRM_DEBUG_KMS("0x%08x: 0x%08x (after)\n", reg, temp);
 196         }
 197
 198         return 0;
 199 }
 200
 201 /* Reset the DPIO configuration register.  The BIOS does this at every
 202  * mode set.
 203  */
 204 static void cdv_sb_reset(struct drm_device *dev)
 205 {
 206
 207         REG_WRITE(DPIO_CFG, 0);
 208         REG_READ(DPIO_CFG);
 209         REG_WRITE(DPIO_CFG, DPIO_MODE_SELECT_0 | DPIO_CMN_RESET_N);
 210 }
 211
 212 /* Unlike most Intel display engines, on Cedarview the DPLL registers
 213  * are behind this sideband bus.  They must be programmed while the
 214  * DPLL reference clock is on in the DPLL control register, but before
 215  * the DPLL is enabled in the DPLL control register.
 216  */
 217 static int
 218 cdv_dpll_set_clock_cdv(struct drm_device *dev, struct drm_crtc *crtc,
 219                                struct cdv_intel_clock_t *clock, bool is_lvds)
 220 {
 221         struct psb_intel_crtc *psb_crtc = to_psb_intel_crtc(crtc);
 222         int pipe = psb_crtc->pipe;
 223         u32 m, n_vco, p;
 224         int ret = 0;
 225         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
 226         int ref_sfr = (pipe == 0) ? SB_REF_DPLLA : SB_REF_DPLLB;
 227         u32 ref_value;
 228         u32 lane_reg, lane_value;
 229
 230         cdv_sb_reset(dev);
 231
 232         REG_WRITE(dpll_reg, DPLL_SYNCLOCK_ENABLE | DPLL_VGA_MODE_DIS);
 233
 234         udelay(100);
 235
 236         /* Follow the BIOS and write the REF/SFR Register. Hardcoded value */
 237         ref_value = 0x68A701;
 238
 239         cdv_sb_write(dev, SB_REF_SFR(pipe), ref_value);
 240
 241         /* We don't know what the other fields of these regs are, so
 242          * leave them in place.
 243          */
 244         /*
 245          * The BIT 14:13 of 0x8010/0x8030 is used to select the ref clk
 246          * for the pipe A/B. Display spec 1.06 has wrong definition.
 247          * Correct definition is like below:
 248          *
 249          * refclka mean use clock from same PLL
 250          *
 251          * if DPLLA sets 01 and DPLLB sets 01, they use clock from their pll
 252          *
 253          * if DPLLA sets 01 and DPLLB sets 02, both use clk from DPLLA
 254          *
 255          */
 256         ret = cdv_sb_read(dev, ref_sfr, &ref_value);
 257         if (ret)
 258                 return ret;
 259         ref_value &= ~(REF_CLK_MASK);
 260
 261         /* use DPLL_A for pipeB on CRT/HDMI */
 262         if (pipe == 1 && !is_lvds) {
 263                 DRM_DEBUG_KMS("use DPLLA for pipe B\n");
 264                 ref_value |= REF_CLK_DPLLA;
 265         } else {
 266                 DRM_DEBUG_KMS("use their DPLL for pipe A/B\n");
 267                 ref_value |= REF_CLK_DPLL;
 268         }
 269         ret = cdv_sb_write(dev, ref_sfr, ref_value);
 270         if (ret)
 271                 return ret;
 272
 273         ret = cdv_sb_read(dev, SB_M(pipe), &m);
 274         if (ret)
 275                 return ret;
 276         m &= ~SB_M_DIVIDER_MASK;
 277         m |= ((clock->m2) << SB_M_DIVIDER_SHIFT);
 278         ret = cdv_sb_write(dev, SB_M(pipe), m);
 279         if (ret)
 280                 return ret;
 281
 282         ret = cdv_sb_read(dev, SB_N_VCO(pipe), &n_vco);
 283         if (ret)
 284                 return ret;
 285
 286         /* Follow the BIOS to program the N_DIVIDER REG */
 287         n_vco &= 0xFFFF;
 288         n_vco |= 0x107;
 289         n_vco &= ~(SB_N_VCO_SEL_MASK |
 290                    SB_N_DIVIDER_MASK |
 291                    SB_N_CB_TUNE_MASK);
 292
 293         n_vco |= ((clock->n) << SB_N_DIVIDER_SHIFT);
 294
 295         if (clock->vco < 2250000) {
 296                 n_vco |= (2 << SB_N_CB_TUNE_SHIFT);
 297                 n_vco |= (0 << SB_N_VCO_SEL_SHIFT);
 298         } else if (clock->vco < 2750000) {
 299                 n_vco |= (1 << SB_N_CB_TUNE_SHIFT);
 300                 n_vco |= (1 << SB_N_VCO_SEL_SHIFT);
 301         } else if (clock->vco < 3300000) {
 302                 n_vco |= (0 << SB_N_CB_TUNE_SHIFT);
 303                 n_vco |= (2 << SB_N_VCO_SEL_SHIFT);
 304         } else {
 305                 n_vco |= (0 << SB_N_CB_TUNE_SHIFT);
 306                 n_vco |= (3 << SB_N_VCO_SEL_SHIFT);
 307         }
 308
 309         ret = cdv_sb_write(dev, SB_N_VCO(pipe), n_vco);
 310         if (ret)
 311                 return ret;
 312
 313         ret = cdv_sb_read(dev, SB_P(pipe), &p);
 314         if (ret)
 315                 return ret;
 316         p &= ~(SB_P2_DIVIDER_MASK | SB_P1_DIVIDER_MASK);
 317         p |= SET_FIELD(clock->p1, SB_P1_DIVIDER);
 318         switch (clock->p2) {
 319         case 5:
 320                 p |= SET_FIELD(SB_P2_5, SB_P2_DIVIDER);
 321                 break;
 322         case 10:
 323                 p |= SET_FIELD(SB_P2_10, SB_P2_DIVIDER);
 324                 break;
 325         case 14:
 326                 p |= SET_FIELD(SB_P2_14, SB_P2_DIVIDER);
 327                 break;
 328         case 7:
 329                 p |= SET_FIELD(SB_P2_7, SB_P2_DIVIDER);
 330                 break;
 331         default:
 332                 DRM_ERROR("Bad P2 clock: %d\n", clock->p2);
 333                 return -EINVAL;
 334         }
 335         ret = cdv_sb_write(dev, SB_P(pipe), p);
 336         if (ret)
 337                 return ret;
 338
 339         lane_reg = PSB_LANE0;
 340         cdv_sb_read(dev, lane_reg, &lane_value);
 341         lane_value &= ~(LANE_PLL_MASK);
 342         lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
 343         cdv_sb_write(dev, lane_reg, lane_value);
 344
 345         lane_reg = PSB_LANE1;
 346         cdv_sb_read(dev, lane_reg, &lane_value);
 347         lane_value &= ~(LANE_PLL_MASK);
 348         lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
 349         cdv_sb_write(dev, lane_reg, lane_value);
 350
 351         lane_reg = PSB_LANE2;
 352         cdv_sb_read(dev, lane_reg, &lane_value);
 353         lane_value &= ~(LANE_PLL_MASK);
 354         lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
 355         cdv_sb_write(dev, lane_reg, lane_value);
 356
 357         lane_reg = PSB_LANE3;
 358         cdv_sb_read(dev, lane_reg, &lane_value);
 359         lane_value &= ~(LANE_PLL_MASK);
 360         lane_value |= LANE_PLL_ENABLE | LANE_PLL_PIPE(pipe);
 361         cdv_sb_write(dev, lane_reg, lane_value);
 362
 363         return 0;
 364 }
 365
 366 /*
 367  * Returns whether any encoder on the specified pipe is of the specified type
 368  */
 369 static bool cdv_intel_pipe_has_type(struct drm_crtc *crtc, int type)
 370 {
 371         struct drm_device *dev = crtc->dev;
 372         struct drm_mode_config *mode_config = &dev->mode_config;
 373         struct drm_connector *l_entry;
 374
 375         list_for_each_entry(l_entry, &mode_config->connector_list, head) {
 376                 if (l_entry->encoder && l_entry->encoder->crtc == crtc) {
 377                         struct psb_intel_encoder *psb_intel_encoder =
 378                                         psb_intel_attached_encoder(l_entry);
 379                         if (psb_intel_encoder->type == type)
 380                                 return true;
 381                 }
 382         }
 383         return false;
 384 }
 385
 386 static const struct cdv_intel_limit_t *cdv_intel_limit(struct drm_crtc *crtc,
 387                                                         int refclk)
 388 {
 389         const struct cdv_intel_limit_t *limit;
 390         if (cdv_intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 391                 /*
 392                  * Now only single-channel LVDS is supported on CDV. If it is
 393                  * incorrect, please add the dual-channel LVDS.
 394                  */
 395                 if (refclk == 96000)
 396                         limit = &cdv_intel_limits[CDV_LIMIT_SINGLE_LVDS_96];
 397                 else
 398                         limit = &cdv_intel_limits[CDV_LIMIT_SINGLE_LVDS_100];
 399         } else {
 400                 if (refclk == 27000)
 401                         limit = &cdv_intel_limits[CDV_LIMIT_DAC_HDMI_27];
 402                 else
 403                         limit = &cdv_intel_limits[CDV_LIMIT_DAC_HDMI_96];
 404         }
 405         return limit;
 406 }
 407
 408 /* m1 is reserved as 0 in CDV, n is a ring counter */
 409 static void cdv_intel_clock(struct drm_device *dev,
 410                         int refclk, struct cdv_intel_clock_t *clock)
 411 {
 412         clock->m = clock->m2 + 2;
 413         clock->p = clock->p1 * clock->p2;
 414         clock->vco = (refclk * clock->m) / clock->n;
 415         clock->dot = clock->vco / clock->p;
 416 }
 417
 418
 419 #define INTELPllInvalid(s)   { /* ErrorF (s) */; return false; }
 420 static bool cdv_intel_PLL_is_valid(struct drm_crtc *crtc,
 421                                 const struct cdv_intel_limit_t *limit,
 422                                struct cdv_intel_clock_t *clock)
 423 {
 424         if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
 425                 INTELPllInvalid("p1 out of range\n");
 426         if (clock->p < limit->p.min || limit->p.max < clock->p)
 427                 INTELPllInvalid("p out of range\n");
 428         /* unnecessary to check the range of m(m1/M2)/n again */
 429         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 430                 INTELPllInvalid("vco out of range\n");
 431         /* XXX: We may need to be checking "Dot clock"
 432          * depending on the multiplier, connector, etc.,
 433          * rather than just a single range.
 434          */
 435         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 436                 INTELPllInvalid("dot out of range\n");
 437
 438         return true;
 439 }
 440
 441 static bool cdv_intel_find_best_PLL(struct drm_crtc *crtc, int target,
 442                                 int refclk,
 443                                 struct cdv_intel_clock_t *best_clock)
 444 {
 445         struct drm_device *dev = crtc->dev;
 446         struct cdv_intel_clock_t clock;
 447         const struct cdv_intel_limit_t *limit = cdv_intel_limit(crtc, refclk);
 448         int err = target;
 449
 450
 451         if (cdv_intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 452             (REG_READ(LVDS) & LVDS_PORT_EN) != 0) {
 453                 /*
 454                  * For LVDS, if the panel is on, just rely on its current
 455                  * settings for dual-channel.  We haven't figured out how to
 456                  * reliably set up different single/dual channel state, if we
 457                  * even can.
 458                  */
 459                 if ((REG_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 460                     LVDS_CLKB_POWER_UP)
 461                         clock.p2 = limit->p2.p2_fast;
 462                 else
 463                         clock.p2 = limit->p2.p2_slow;
 464         } else {
 465                 if (target < limit->p2.dot_limit)
 466                         clock.p2 = limit->p2.p2_slow;
 467                 else
 468                         clock.p2 = limit->p2.p2_fast;
 469         }
 470
 471         memset(best_clock, 0, sizeof(*best_clock));
 472         clock.m1 = 0;
 473         /* m1 is reserved as 0 in CDV, n is a ring counter.
 474            So skip the m1 loop */
 475         for (clock.n = limit->n.min; clock.n <= limit->n.max; clock.n++) {
 476                 for (clock.m2 = limit->m2.min; clock.m2 <= limit->m2.max;
 477                                              clock.m2++) {
 478                         for (clock.p1 = limit->p1.min;
 479                                         clock.p1 <= limit->p1.max;
 480                                         clock.p1++) {
 481                                 int this_err;
 482
 483                                 cdv_intel_clock(dev, refclk, &clock);
 484
 485                                 if (!cdv_intel_PLL_is_valid(crtc,
 486                                                                 limit, &clock))
 487                                                 continue;
 488
 489                                 this_err = abs(clock.dot - target);
 490                                 if (this_err < err) {
 491                                         *best_clock = clock;
 492                                         err = this_err;
 493                                 }
 494                         }
 495                 }
 496         }
 497
 498         return err != target;
 499 }
 500
 501 static int cdv_intel_pipe_set_base(struct drm_crtc *crtc,
 502                             int x, int y, struct drm_framebuffer *old_fb)
 503 {
 504         struct drm_device *dev = crtc->dev;
 505         struct drm_psb_private *dev_priv = dev->dev_private;
 506         struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
 507         struct psb_framebuffer *psbfb = to_psb_fb(crtc->fb);
 508         int pipe = psb_intel_crtc->pipe;
 509         const struct psb_offset *map = &dev_priv->regmap[pipe];
 510         unsigned long start, offset;
 511         u32 dspcntr;
 512         int ret = 0;
 513
 514         if (!gma_power_begin(dev, true))
 515                 return 0;
 516
 517         /* no fb bound */
 518         if (!crtc->fb) {
 519                 dev_err(dev->dev, "No FB bound\n");
 520                 goto psb_intel_pipe_cleaner;
 521         }
 522
 523
 524         /* We are displaying this buffer, make sure it is actually loaded
 525            into the GTT */
 526         ret = psb_gtt_pin(psbfb->gtt);
 527         if (ret < 0)
 528                 goto psb_intel_pipe_set_base_exit;
 529         start = psbfb->gtt->offset;
 530         offset = y * crtc->fb->pitches[0] + x * (crtc->fb->bits_per_pixel / 8);
 531
 532         REG_WRITE(map->stride, crtc->fb->pitches[0]);
 533
 534         dspcntr = REG_READ(map->cntr);
 535         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
 536
 537         switch (crtc->fb->bits_per_pixel) {
 538         case 8:
 539                 dspcntr |= DISPPLANE_8BPP;
 540                 break;
 541         case 16:
 542                 if (crtc->fb->depth == 15)
 543                         dspcntr |= DISPPLANE_15_16BPP;
 544                 else
 545                         dspcntr |= DISPPLANE_16BPP;
 546                 break;
 547         case 24:
 548         case 32:
 549                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
 550                 break;
 551         default:
 552                 dev_err(dev->dev, "Unknown color depth\n");
 553                 ret = -EINVAL;
 554                 goto psb_intel_pipe_set_base_exit;
 555         }
 556         REG_WRITE(map->cntr, dspcntr);
 557
 558         dev_dbg(dev->dev,
 559                 "Writing base %08lX %08lX %d %d\n", start, offset, x, y);
 560
 561         REG_WRITE(map->base, offset);
 562         REG_READ(map->base);
 563         REG_WRITE(map->surf, start);
 564         REG_READ(map->surf);
 565
 566 psb_intel_pipe_cleaner:
 567         /* If there was a previous display we can now unpin it */
 568         if (old_fb)
 569                 psb_gtt_unpin(to_psb_fb(old_fb)->gtt);
 570
 571 psb_intel_pipe_set_base_exit:
 572         gma_power_end(dev);
 573         return ret;
 574 }
 575
 576 #define         FIFO_PIPEA              (1 << 0)
 577 #define         FIFO_PIPEB              (1 << 1)
 578
 579 static bool cdv_intel_pipe_enabled(struct drm_device *dev, int pipe)
 580 {
 581         struct drm_crtc *crtc;
 582         struct drm_psb_private *dev_priv = dev->dev_private;
 583         struct psb_intel_crtc *psb_intel_crtc = NULL;
 584
 585         crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 586         psb_intel_crtc = to_psb_intel_crtc(crtc);
 587
 588         if (crtc->fb == NULL || !psb_intel_crtc->active)
 589                 return false;
 590         return true;
 591 }
 592
 593 static bool cdv_intel_single_pipe_active (struct drm_device *dev)
 594 {
 595         uint32_t pipe_enabled = 0;
 596
 597         if (cdv_intel_pipe_enabled(dev, 0))
 598                 pipe_enabled |= FIFO_PIPEA;
 599
 600         if (cdv_intel_pipe_enabled(dev, 1))
 601                 pipe_enabled |= FIFO_PIPEB;
 602
 603
 604         DRM_DEBUG_KMS("pipe enabled %x\n", pipe_enabled);
 605
 606         if (pipe_enabled == FIFO_PIPEA || pipe_enabled == FIFO_PIPEB)
 607                 return true;
 608         else
 609                 return false;
 610 }
 611
 612 static bool is_pipeb_lvds(struct drm_device *dev, struct drm_crtc *crtc)
 613 {
 614         struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
 615         struct drm_mode_config *mode_config = &dev->mode_config;
 616         struct drm_connector *connector;
 617
 618         if (psb_intel_crtc->pipe != 1)
 619                 return false;
 620
 621         list_for_each_entry(connector, &mode_config->connector_list, head) {
 622                 struct psb_intel_encoder *psb_intel_encoder =
 623                                         psb_intel_attached_encoder(connector);
 624
 625                 if (!connector->encoder
 626                     || connector->encoder->crtc != crtc)
 627                         continue;
 628
 629                 if (psb_intel_encoder->type == INTEL_OUTPUT_LVDS)
 630                         return true;
 631         }
 632
 633         return false;
 634 }
 635
 636 static void cdv_intel_disable_self_refresh (struct drm_device *dev)
 637 {
 638         if (REG_READ(FW_BLC_SELF) & FW_BLC_SELF_EN) {
 639
 640                 /* Disable self-refresh before adjust WM */
 641                 REG_WRITE(FW_BLC_SELF, (REG_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN));
 642                 REG_READ(FW_BLC_SELF);
 643
 644                 cdv_intel_wait_for_vblank(dev);
 645
 646                 /* Cedarview workaround to write ovelay plane, which force to leave
 647                  * MAX_FIFO state.
 648                  */
 649                 REG_WRITE(OV_OVADD, 0/*dev_priv->ovl_offset*/);
 650                 REG_READ(OV_OVADD);
 651
 652                 cdv_intel_wait_for_vblank(dev);
 653         }
 654
 655 }
 656
 657 static void cdv_intel_update_watermark (struct drm_device *dev, struct drm_crtc *crtc)
 658 {
 659
 660         if (cdv_intel_single_pipe_active(dev)) {
 661                 u32 fw;
 662
 663                 fw = REG_READ(DSPFW1);
 664                 fw &= ~DSP_FIFO_SR_WM_MASK;
 665                 fw |= (0x7e << DSP_FIFO_SR_WM_SHIFT);
 666                 fw &= ~CURSOR_B_FIFO_WM_MASK;
 667                 fw |= (0x4 << CURSOR_B_FIFO_WM_SHIFT);
 668                 REG_WRITE(DSPFW1, fw);
 669
 670                 fw = REG_READ(DSPFW2);
 671                 fw &= ~CURSOR_A_FIFO_WM_MASK;
 672                 fw |= (0x6 << CURSOR_A_FIFO_WM_SHIFT);
 673                 fw &= ~DSP_PLANE_C_FIFO_WM_MASK;
 674                 fw |= (0x8 << DSP_PLANE_C_FIFO_WM_SHIFT);
 675                 REG_WRITE(DSPFW2, fw);
 676
 677                 REG_WRITE(DSPFW3, 0x36000000);
 678
 679                 /* ignore FW4 */
 680
 681                 if (is_pipeb_lvds(dev, crtc)) {
 682                         REG_WRITE(DSPFW5, 0x00040330);
 683                 } else {
 684                         fw = (3 << DSP_PLANE_B_FIFO_WM1_SHIFT) |
 685                              (4 << DSP_PLANE_A_FIFO_WM1_SHIFT) |
 686                              (3 << CURSOR_B_FIFO_WM1_SHIFT) |
 687                              (4 << CURSOR_FIFO_SR_WM1_SHIFT);
 688                         REG_WRITE(DSPFW5, fw);
 689                 }
 690
 691                 REG_WRITE(DSPFW6, 0x10);
 692
 693                 cdv_intel_wait_for_vblank(dev);
 694
 695                 /* enable self-refresh for single pipe active */
 696                 REG_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
 697                 REG_READ(FW_BLC_SELF);
 698                 cdv_intel_wait_for_vblank(dev);
 699
 700         } else {
 701
 702                 /* HW team suggested values... */
 703                 REG_WRITE(DSPFW1, 0x3f880808);
 704                 REG_WRITE(DSPFW2, 0x0b020202);
 705                 REG_WRITE(DSPFW3, 0x24000000);
 706                 REG_WRITE(DSPFW4, 0x08030202);
 707                 REG_WRITE(DSPFW5, 0x01010101);
 708                 REG_WRITE(DSPFW6, 0x1d0);
 709
 710                 cdv_intel_wait_for_vblank(dev);
 711
 712                 cdv_intel_disable_self_refresh(dev);
 713
 714         }
 715 }
 716
 717 /** Loads the palette/gamma unit for the CRTC with the prepared values */
 718 static void cdv_intel_crtc_load_lut(struct drm_crtc *crtc)
 719 {
 720         struct drm_device *dev = crtc->dev;
 721         struct drm_psb_private *dev_priv = dev->dev_private;
 722         struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
 723         int palreg = PALETTE_A;
 724         int i;
 725
 726         /* The clocks have to be on to load the palette. */
 727         if (!crtc->enabled)
 728                 return;
 729
 730         switch (psb_intel_crtc->pipe) {
 731         case 0:
 732                 break;
 733         case 1:
 734                 palreg = PALETTE_B;
 735                 break;
 736         case 2:
 737                 palreg = PALETTE_C;
 738                 break;
 739         default:
 740                 dev_err(dev->dev, "Illegal Pipe Number.\n");
 741                 return;
 742         }
 743
 744         if (gma_power_begin(dev, false)) {
 745                 for (i = 0; i < 256; i++) {
 746                         REG_WRITE(palreg + 4 * i,
 747                                   ((psb_intel_crtc->lut_r[i] +
 748                                   psb_intel_crtc->lut_adj[i]) << 16) |
 749                                   ((psb_intel_crtc->lut_g[i] +
 750                                   psb_intel_crtc->lut_adj[i]) << 8) |
 751                                   (psb_intel_crtc->lut_b[i] +
 752                                   psb_intel_crtc->lut_adj[i]));
 753                 }
 754                 gma_power_end(dev);
 755         } else {
 756                 for (i = 0; i < 256; i++) {
 757                         dev_priv->regs.pipe[0].palette[i] =
 758                                   ((psb_intel_crtc->lut_r[i] +
 759                                   psb_intel_crtc->lut_adj[i]) << 16) |
 760                                   ((psb_intel_crtc->lut_g[i] +
 761                                   psb_intel_crtc->lut_adj[i]) << 8) |
 762                                   (psb_intel_crtc->lut_b[i] +
 763                                   psb_intel_crtc->lut_adj[i]);
 764                 }
 765
 766         }
 767 }
 768
 769 /**
 770  * Sets the power management mode of the pipe and plane.
 771  *
 772  * This code should probably grow support for turning the cursor off and back
 773  * on appropriately at the same time as we're turning the pipe off/on.
 774  */
 775 static void cdv_intel_crtc_dpms(struct drm_crtc *crtc, int mode)
 776 {
 777         struct drm_device *dev = crtc->dev;
 778         struct drm_psb_private *dev_priv = dev->dev_private;
 779         struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
 780         int pipe = psb_intel_crtc->pipe;
 781         const struct psb_offset *map = &dev_priv->regmap[pipe];
 782         u32 temp;
 783
 784         /* XXX: When our outputs are all unaware of DPMS modes other than off
 785          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
 786          */
 787         cdv_intel_disable_self_refresh(dev);
 788
 789         switch (mode) {
 790         case DRM_MODE_DPMS_ON:
 791         case DRM_MODE_DPMS_STANDBY:
 792         case DRM_MODE_DPMS_SUSPEND:
 793                 if (psb_intel_crtc->active)
 794                         return;
 795
 796                 psb_intel_crtc->active = true;
 797
 798                 /* Enable the DPLL */
 799                 temp = REG_READ(map->dpll);
 800                 if ((temp & DPLL_VCO_ENABLE) == 0) {
 801                         REG_WRITE(map->dpll, temp);
 802                         REG_READ(map->dpll);
 803                         /* Wait for the clocks to stabilize. */
 804                         udelay(150);
 805                         REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);
 806                         REG_READ(map->dpll);
 807                         /* Wait for the clocks to stabilize. */
 808                         udelay(150);
 809                         REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);
 810                         REG_READ(map->dpll);
 811                         /* Wait for the clocks to stabilize. */
 812                         udelay(150);
 813                 }
 814
 815                 /* Jim Bish - switch plan and pipe per scott */
 816                 /* Enable the plane */
 817                 temp = REG_READ(map->cntr);
 818                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
 819                         REG_WRITE(map->cntr,
 820                                   temp | DISPLAY_PLANE_ENABLE);
 821                         /* Flush the plane changes */
 822                         REG_WRITE(map->base, REG_READ(map->base));
 823                 }
 824
 825                 udelay(150);
 826
 827                 /* Enable the pipe */
 828                 temp = REG_READ(map->conf);
 829                 if ((temp & PIPEACONF_ENABLE) == 0)
 830                         REG_WRITE(map->conf, temp | PIPEACONF_ENABLE);
 831
 832                 temp = REG_READ(map->status);
 833                 temp &= ~(0xFFFF);
 834                 temp |= PIPE_FIFO_UNDERRUN;
 835                 REG_WRITE(map->status, temp);
 836                 REG_READ(map->status);
 837
 838                 cdv_intel_update_watermark(dev, crtc);
 839                 cdv_intel_crtc_load_lut(crtc);
 840
 841                 /* Give the overlay scaler a chance to enable
 842                  * if it's on this pipe */
 843                 /* psb_intel_crtc_dpms_video(crtc, true); TODO */
 844                 psb_intel_crtc->crtc_enable = true;
 845                 break;
 846         case DRM_MODE_DPMS_OFF:
 847                 if (!psb_intel_crtc->active)
 848                         return;
 849
 850                 psb_intel_crtc->active = false;
 851
 852                 /* Give the overlay scaler a chance to disable
 853                  * if it's on this pipe */
 854                 /* psb_intel_crtc_dpms_video(crtc, FALSE); TODO */
 855
 856                 /* Disable the VGA plane that we never use */
 857                 REG_WRITE(VGACNTRL, VGA_DISP_DISABLE);
 858
 859                 /* Jim Bish - changed pipe/plane here as well. */
 860
 861                 drm_vblank_off(dev, pipe);
 862                 /* Wait for vblank for the disable to take effect */
 863                 cdv_intel_wait_for_vblank(dev);
 864
 865                 /* Next, disable display pipes */
 866                 temp = REG_READ(map->conf);
 867                 if ((temp & PIPEACONF_ENABLE) != 0) {
 868                         REG_WRITE(map->conf, temp & ~PIPEACONF_ENABLE);
 869                         REG_READ(map->conf);
 870                 }
 871
 872                 /* Wait for vblank for the disable to take effect. */
 873                 cdv_intel_wait_for_vblank(dev);
 874
 875                 udelay(150);
 876
 877                 /* Disable display plane */
 878                 temp = REG_READ(map->cntr);
 879                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
 880                         REG_WRITE(map->cntr,
 881                                   temp & ~DISPLAY_PLANE_ENABLE);
 882                         /* Flush the plane changes */
 883                         REG_WRITE(map->base, REG_READ(map->base));
 884                         REG_READ(map->base);
 885                 }
 886
 887                 temp = REG_READ(map->dpll);
 888                 if ((temp & DPLL_VCO_ENABLE) != 0) {
 889                         REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE);
 890                         REG_READ(map->dpll);
 891                 }
 892
 893                 /* Wait for the clocks to turn off. */
 894                 udelay(150);
 895                 cdv_intel_update_watermark(dev, crtc);
 896                 psb_intel_crtc->crtc_enable = false;
 897                 break;
 898         }
 899         /*Set FIFO Watermarks*/
 900         REG_WRITE(DSPARB, 0x3F3E);
 901 }
 902
 903 static void cdv_intel_crtc_prepare(struct drm_crtc *crtc)
 904 {
 905         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
 906         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
 907 }
 908
 909 static void cdv_intel_crtc_commit(struct drm_crtc *crtc)
 910 {
 911         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
 912         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
 913 }
 914
 915 static bool cdv_intel_crtc_mode_fixup(struct drm_crtc *crtc,
 916                                   const struct drm_display_mode *mode,
 917                                   struct drm_display_mode *adjusted_mode)
 918 {
 919         return true;
 920 }
 921
 922
 923 /**
 924  * Return the pipe currently connected to the panel fitter,
 925  * or -1 if the panel fitter is not present or not in use
 926  */
 927 static int cdv_intel_panel_fitter_pipe(struct drm_device *dev)
 928 {
 929         u32 pfit_control;
 930
 931         pfit_control = REG_READ(PFIT_CONTROL);
 932
 933         /* See if the panel fitter is in use */
 934         if ((pfit_control & PFIT_ENABLE) == 0)
 935                 return -1;
 936         return (pfit_control >> 29) & 0x3;
 937 }
 938
 939 static int cdv_intel_crtc_mode_set(struct drm_crtc *crtc,
 940                                struct drm_display_mode *mode,
 941                                struct drm_display_mode *adjusted_mode,
 942                                int x, int y,
 943                                struct drm_framebuffer *old_fb)
 944 {
 945         struct drm_device *dev = crtc->dev;
 946         struct drm_psb_private *dev_priv = dev->dev_private;
 947         struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
 948         int pipe = psb_intel_crtc->pipe;
 949         const struct psb_offset *map = &dev_priv->regmap[pipe];
 950         int refclk;
 951         struct cdv_intel_clock_t clock;
 952         u32 dpll = 0, dspcntr, pipeconf;
 953         bool ok;
 954         bool is_crt = false, is_lvds = false, is_tv = false;
 955         bool is_hdmi = false;
 956         struct drm_mode_config *mode_config = &dev->mode_config;
 957         struct drm_connector *connector;
 958
 959         list_for_each_entry(connector, &mode_config->connector_list, head) {
 960                 struct psb_intel_encoder *psb_intel_encoder =
 961                                         psb_intel_attached_encoder(connector);
 962
 963                 if (!connector->encoder
 964                     || connector->encoder->crtc != crtc)
 965                         continue;
 966
 967                 switch (psb_intel_encoder->type) {
 968                 case INTEL_OUTPUT_LVDS:
 969                         is_lvds = true;
 970                         break;
 971                 case INTEL_OUTPUT_TVOUT:
 972                         is_tv = true;
 973                         break;
 974                 case INTEL_OUTPUT_ANALOG:
 975                         is_crt = true;
 976                         break;
 977                 case INTEL_OUTPUT_HDMI:
 978                         is_hdmi = true;
 979                         break;
 980                 }
 981         }
 982
 983         if (dev_priv->dplla_96mhz)
 984                 /* low-end sku, 96/100 mhz */
 985                 refclk = 96000;
 986         else
 987                 /* high-end sku, 27/100 mhz */
 988                 refclk = 27000;
 989
 990         if (is_lvds && dev_priv->lvds_use_ssc) {
 991                 refclk = dev_priv->lvds_ssc_freq * 1000;
 992                 DRM_DEBUG_KMS("Use SSC reference clock %d Mhz\n", dev_priv->lvds_ssc_freq);
 993         }
 994
 995         drm_mode_debug_printmodeline(adjusted_mode);
 996
 997         ok = cdv_intel_find_best_PLL(crtc, adjusted_mode->clock, refclk,
 998                                  &clock);
 999         if (!ok) {
1000                 dev_err(dev->dev, "Couldn't find PLL settings for mode!\n");
1001                 return 0;
1002         }
1003
1004         dpll = DPLL_VGA_MODE_DIS;
1005         if (is_tv) {
1006                 /* XXX: just matching BIOS for now */
1007 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
1008                 dpll |= 3;
1009         }
1010 /*              dpll |= PLL_REF_INPUT_DREFCLK; */
1011
1012         dpll |= DPLL_SYNCLOCK_ENABLE;
1013 /*      if (is_lvds)
1014                 dpll |= DPLLB_MODE_LVDS;
1015         else
1016                 dpll |= DPLLB_MODE_DAC_SERIAL; */
1017         /* dpll |= (2 << 11); */
1018
1019         /* setup pipeconf */
1020         pipeconf = REG_READ(map->conf);
1021
1022         /* Set up the display plane register */
1023         dspcntr = DISPPLANE_GAMMA_ENABLE;
1024
1025         if (pipe == 0)
1026                 dspcntr |= DISPPLANE_SEL_PIPE_A;
1027         else
1028                 dspcntr |= DISPPLANE_SEL_PIPE_B;
1029
1030         dspcntr |= DISPLAY_PLANE_ENABLE;
1031         pipeconf |= PIPEACONF_ENABLE;
1032
1033         REG_WRITE(map->dpll, dpll | DPLL_VGA_MODE_DIS | DPLL_SYNCLOCK_ENABLE);
1034         REG_READ(map->dpll);
1035
1036         cdv_dpll_set_clock_cdv(dev, crtc, &clock, is_lvds);
1037
1038         udelay(150);
1039
1040
1041         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
1042          * This is an exception to the general rule that mode_set doesn't turn
1043          * things on.
1044          */
1045         if (is_lvds) {
1046                 u32 lvds = REG_READ(LVDS);
1047
1048                 lvds |=
1049                     LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP |
1050                     LVDS_PIPEB_SELECT;
1051                 /* Set the B0-B3 data pairs corresponding to
1052                  * whether we're going to
1053                  * set the DPLLs for dual-channel mode or not.
1054                  */
1055                 if (clock.p2 == 7)
1056                         lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
1057                 else
1058                         lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
1059
1060                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
1061                  * appropriately here, but we need to look more
1062                  * thoroughly into how panels behave in the two modes.
1063                  */
1064
1065                 REG_WRITE(LVDS, lvds);
1066                 REG_READ(LVDS);
1067         }
1068
1069         dpll |= DPLL_VCO_ENABLE;
1070
1071         /* Disable the panel fitter if it was on our pipe */
1072         if (cdv_intel_panel_fitter_pipe(dev) == pipe)
1073                 REG_WRITE(PFIT_CONTROL, 0);
1074
1075         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
1076         drm_mode_debug_printmodeline(mode);
1077
1078         REG_WRITE(map->dpll,
1079                 (REG_READ(map->dpll) & ~DPLL_LOCK) | DPLL_VCO_ENABLE);
1080         REG_READ(map->dpll);
1081         /* Wait for the clocks to stabilize. */
1082         udelay(150); /* 42 usec w/o calibration, 110 with.  rounded up. */
1083
1084         if (!(REG_READ(map->dpll) & DPLL_LOCK)) {
1085                 dev_err(dev->dev, "Failed to get DPLL lock\n");
1086                 return -EBUSY;
1087         }
1088
1089         {
1090                 int sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
1091                 REG_WRITE(map->dpll_md, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) | ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
1092         }
1093
1094         REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) |
1095                   ((adjusted_mode->crtc_htotal - 1) << 16));
1096         REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) |
1097                   ((adjusted_mode->crtc_hblank_end - 1) << 16));
1098         REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) |
1099                   ((adjusted_mode->crtc_hsync_end - 1) << 16));
1100         REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) |
1101                   ((adjusted_mode->crtc_vtotal - 1) << 16));
1102         REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) |
1103                   ((adjusted_mode->crtc_vblank_end - 1) << 16));
1104         REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) |
1105                   ((adjusted_mode->crtc_vsync_end - 1) << 16));
1106         /* pipesrc and dspsize control the size that is scaled from,
1107          * which should always be the user's requested size.
1108          */
1109         REG_WRITE(map->size,
1110                   ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1));
1111         REG_WRITE(map->pos, 0);
1112         REG_WRITE(map->src,
1113                   ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
1114         REG_WRITE(map->conf, pipeconf);
1115         REG_READ(map->conf);
1116
1117         cdv_intel_wait_for_vblank(dev);
1118
1119         REG_WRITE(map->cntr, dspcntr);
1120
1121         /* Flush the plane changes */
1122         {
1123                 struct drm_crtc_helper_funcs *crtc_funcs =
1124                     crtc->helper_private;
1125                 crtc_funcs->mode_set_base(crtc, x, y, old_fb);
1126         }
1127
1128         cdv_intel_wait_for_vblank(dev);
1129
1130         return 0;
1131 }
1132
1133
1134 /**
1135  * Save HW states of giving crtc
1136  */
1137 static void cdv_intel_crtc_save(struct drm_crtc *crtc)
1138 {
1139         struct drm_device *dev = crtc->dev;
1140         struct drm_psb_private *dev_priv = dev->dev_private;
1141         struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1142         struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state;
1143         const struct psb_offset *map = &dev_priv->regmap[psb_intel_crtc->pipe];
1144         uint32_t paletteReg;
1145         int i;
1146
1147         if (!crtc_state) {
1148                 dev_dbg(dev->dev, "No CRTC state found\n");
1149                 return;
1150         }
1151
1152         crtc_state->saveDSPCNTR = REG_READ(map->cntr);
1153         crtc_state->savePIPECONF = REG_READ(map->conf);
1154         crtc_state->savePIPESRC = REG_READ(map->src);
1155         crtc_state->saveFP0 = REG_READ(map->fp0);
1156         crtc_state->saveFP1 = REG_READ(map->fp1);
1157         crtc_state->saveDPLL = REG_READ(map->dpll);
1158         crtc_state->saveHTOTAL = REG_READ(map->htotal);
1159         crtc_state->saveHBLANK = REG_READ(map->hblank);
1160         crtc_state->saveHSYNC = REG_READ(map->hsync);
1161         crtc_state->saveVTOTAL = REG_READ(map->vtotal);
1162         crtc_state->saveVBLANK = REG_READ(map->vblank);
1163         crtc_state->saveVSYNC = REG_READ(map->vsync);
1164         crtc_state->saveDSPSTRIDE = REG_READ(map->stride);
1165
1166         /*NOTE: DSPSIZE DSPPOS only for psb*/
1167         crtc_state->saveDSPSIZE = REG_READ(map->size);
1168         crtc_state->saveDSPPOS = REG_READ(map->pos);
1169
1170         crtc_state->saveDSPBASE = REG_READ(map->base);
1171
1172         DRM_DEBUG("(%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n",
1173                         crtc_state->saveDSPCNTR,
1174                         crtc_state->savePIPECONF,
1175                         crtc_state->savePIPESRC,
1176                         crtc_state->saveFP0,
1177                         crtc_state->saveFP1,
1178                         crtc_state->saveDPLL,
1179                         crtc_state->saveHTOTAL,
1180                         crtc_state->saveHBLANK,
1181                         crtc_state->saveHSYNC,
1182                         crtc_state->saveVTOTAL,
1183                         crtc_state->saveVBLANK,
1184                         crtc_state->saveVSYNC,
1185                         crtc_state->saveDSPSTRIDE,
1186                         crtc_state->saveDSPSIZE,
1187                         crtc_state->saveDSPPOS,
1188                         crtc_state->saveDSPBASE
1189                 );
1190
1191         paletteReg = map->palette;
1192         for (i = 0; i < 256; ++i)
1193                 crtc_state->savePalette[i] = REG_READ(paletteReg + (i << 2));
1194 }
1195
1196 /**
1197  * Restore HW states of giving crtc
1198  */
1199 static void cdv_intel_crtc_restore(struct drm_crtc *crtc)
1200 {
1201         struct drm_device *dev = crtc->dev;
1202         struct drm_psb_private *dev_priv = dev->dev_private;
1203         struct psb_intel_crtc *psb_intel_crtc =  to_psb_intel_crtc(crtc);
1204         struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state;
1205         const struct psb_offset *map = &dev_priv->regmap[psb_intel_crtc->pipe];
1206         uint32_t paletteReg;
1207         int i;
1208
1209         if (!crtc_state) {
1210                 dev_dbg(dev->dev, "No crtc state\n");
1211                 return;
1212         }
1213
1214         DRM_DEBUG(
1215                 "current:(%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n",
1216                 REG_READ(map->cntr),
1217                 REG_READ(map->conf),
1218                 REG_READ(map->src),
1219                 REG_READ(map->fp0),
1220                 REG_READ(map->fp1),
1221                 REG_READ(map->dpll),
1222                 REG_READ(map->htotal),
1223                 REG_READ(map->hblank),
1224                 REG_READ(map->hsync),
1225                 REG_READ(map->vtotal),
1226                 REG_READ(map->vblank),
1227                 REG_READ(map->vsync),
1228                 REG_READ(map->stride),
1229                 REG_READ(map->size),
1230                 REG_READ(map->pos),
1231                 REG_READ(map->base)
1232         );
1233
1234         DRM_DEBUG(
1235                 "saved: (%x %x %x %x %x %x %x %x %x %x %x %x %x %x %x %x)\n",
1236                 crtc_state->saveDSPCNTR,
1237                 crtc_state->savePIPECONF,
1238                 crtc_state->savePIPESRC,
1239                 crtc_state->saveFP0,
1240                 crtc_state->saveFP1,
1241                 crtc_state->saveDPLL,
1242                 crtc_state->saveHTOTAL,
1243                 crtc_state->saveHBLANK,
1244                 crtc_state->saveHSYNC,
1245                 crtc_state->saveVTOTAL,
1246                 crtc_state->saveVBLANK,
1247                 crtc_state->saveVSYNC,
1248                 crtc_state->saveDSPSTRIDE,
1249                 crtc_state->saveDSPSIZE,
1250                 crtc_state->saveDSPPOS,
1251                 crtc_state->saveDSPBASE
1252         );
1253
1254
1255         if (crtc_state->saveDPLL & DPLL_VCO_ENABLE) {
1256                 REG_WRITE(map->dpll,
1257                                 crtc_state->saveDPLL & ~DPLL_VCO_ENABLE);
1258                 REG_READ(map->dpll);
1259                 DRM_DEBUG("write dpll: %x\n",
1260                                 REG_READ(map->dpll));
1261                 udelay(150);
1262         }
1263
1264         REG_WRITE(map->fp0, crtc_state->saveFP0);
1265         REG_READ(map->fp0);
1266
1267         REG_WRITE(map->fp1, crtc_state->saveFP1);
1268         REG_READ(map->fp1);
1269
1270         REG_WRITE(map->dpll, crtc_state->saveDPLL);
1271         REG_READ(map->dpll);
1272         udelay(150);
1273
1274         REG_WRITE(map->htotal, crtc_state->saveHTOTAL);
1275         REG_WRITE(map->hblank, crtc_state->saveHBLANK);
1276         REG_WRITE(map->hsync, crtc_state->saveHSYNC);
1277         REG_WRITE(map->vtotal, crtc_state->saveVTOTAL);
1278         REG_WRITE(map->vblank, crtc_state->saveVBLANK);
1279         REG_WRITE(map->vsync, crtc_state->saveVSYNC);
1280         REG_WRITE(map->stride, crtc_state->saveDSPSTRIDE);
1281
1282         REG_WRITE(map->size, crtc_state->saveDSPSIZE);
1283         REG_WRITE(map->pos, crtc_state->saveDSPPOS);
1284
1285         REG_WRITE(map->src, crtc_state->savePIPESRC);
1286         REG_WRITE(map->base, crtc_state->saveDSPBASE);
1287         REG_WRITE(map->conf, crtc_state->savePIPECONF);
1288
1289         cdv_intel_wait_for_vblank(dev);
1290
1291         REG_WRITE(map->cntr, crtc_state->saveDSPCNTR);
1292         REG_WRITE(map->base, crtc_state->saveDSPBASE);
1293
1294         cdv_intel_wait_for_vblank(dev);
1295
1296         paletteReg = map->palette;
1297         for (i = 0; i < 256; ++i)
1298                 REG_WRITE(paletteReg + (i << 2), crtc_state->savePalette[i]);
1299 }
1300
1301 static int cdv_intel_crtc_cursor_set(struct drm_crtc *crtc,
1302                                  struct drm_file *file_priv,
1303                                  uint32_t handle,
1304                                  uint32_t width, uint32_t height)
1305 {
1306         struct drm_device *dev = crtc->dev;
1307         struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1308         int pipe = psb_intel_crtc->pipe;
1309         uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
1310         uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
1311         uint32_t temp;
1312         size_t addr = 0;
1313         struct gtt_range *gt;
1314         struct drm_gem_object *obj;
1315         int ret;
1316
1317         /* if we want to turn of the cursor ignore width and height */
1318         if (!handle) {
1319                 /* turn off the cursor */
1320                 temp = CURSOR_MODE_DISABLE;
1321
1322                 if (gma_power_begin(dev, false)) {
1323                         REG_WRITE(control, temp);
1324                         REG_WRITE(base, 0);
1325                         gma_power_end(dev);
1326                 }
1327
1328                 /* unpin the old GEM object */
1329                 if (psb_intel_crtc->cursor_obj) {
1330                         gt = container_of(psb_intel_crtc->cursor_obj,
1331                                                         struct gtt_range, gem);
1332                         psb_gtt_unpin(gt);
1333                         drm_gem_object_unreference(psb_intel_crtc->cursor_obj);
1334                         psb_intel_crtc->cursor_obj = NULL;
1335                 }
1336
1337                 return 0;
1338         }
1339
1340         /* Currently we only support 64x64 cursors */
1341         if (width != 64 || height != 64) {
1342                 dev_dbg(dev->dev, "we currently only support 64x64 cursors\n");
1343                 return -EINVAL;
1344         }
1345
1346         obj = drm_gem_object_lookup(dev, file_priv, handle);
1347         if (!obj)
1348                 return -ENOENT;
1349
1350         if (obj->size < width * height * 4) {
1351                 dev_dbg(dev->dev, "buffer is to small\n");
1352                 return -ENOMEM;
1353         }
1354
1355         gt = container_of(obj, struct gtt_range, gem);
1356
1357         /* Pin the memory into the GTT */
1358         ret = psb_gtt_pin(gt);
1359         if (ret) {
1360                 dev_err(dev->dev, "Can not pin down handle 0x%x\n", handle);
1361                 return ret;
1362         }
1363
1364         addr = gt->offset;      /* Or resource.start ??? */
1365
1366         psb_intel_crtc->cursor_addr = addr;
1367
1368         temp = 0;
1369         /* set the pipe for the cursor */
1370         temp |= (pipe << 28);
1371         temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
1372
1373         if (gma_power_begin(dev, false)) {
1374                 REG_WRITE(control, temp);
1375                 REG_WRITE(base, addr);
1376                 gma_power_end(dev);
1377         }
1378
1379         /* unpin the old GEM object */
1380         if (psb_intel_crtc->cursor_obj) {
1381                 gt = container_of(psb_intel_crtc->cursor_obj,
1382                                                         struct gtt_range, gem);
1383                 psb_gtt_unpin(gt);
1384                 drm_gem_object_unreference(psb_intel_crtc->cursor_obj);
1385                 psb_intel_crtc->cursor_obj = obj;
1386         }
1387         return 0;
1388 }
1389
1390 static int cdv_intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
1391 {
1392         struct drm_device *dev = crtc->dev;
1393         struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1394         int pipe = psb_intel_crtc->pipe;
1395         uint32_t temp = 0;
1396         uint32_t adder;
1397
1398
1399         if (x < 0) {
1400                 temp |= (CURSOR_POS_SIGN << CURSOR_X_SHIFT);
1401                 x = -x;
1402         }
1403         if (y < 0) {
1404                 temp |= (CURSOR_POS_SIGN << CURSOR_Y_SHIFT);
1405                 y = -y;
1406         }
1407
1408         temp |= ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT);
1409         temp |= ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
1410
1411         adder = psb_intel_crtc->cursor_addr;
1412
1413         if (gma_power_begin(dev, false)) {
1414                 REG_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
1415                 REG_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
1416                 gma_power_end(dev);
1417         }
1418         return 0;
1419 }
1420
1421 static void cdv_intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red,
1422                          u16 *green, u16 *blue, uint32_t start, uint32_t size)
1423 {
1424         struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1425         int i;
1426         int end = (start + size > 256) ? 256 : start + size;
1427
1428         for (i = start; i < end; i++) {
1429                 psb_intel_crtc->lut_r[i] = red[i] >> 8;
1430                 psb_intel_crtc->lut_g[i] = green[i] >> 8;
1431                 psb_intel_crtc->lut_b[i] = blue[i] >> 8;
1432         }
1433
1434         cdv_intel_crtc_load_lut(crtc);
1435 }
1436
1437 static int cdv_crtc_set_config(struct drm_mode_set *set)
1438 {
1439         int ret = 0;
1440         struct drm_device *dev = set->crtc->dev;
1441         struct drm_psb_private *dev_priv = dev->dev_private;
1442
1443         if (!dev_priv->rpm_enabled)
1444                 return drm_crtc_helper_set_config(set);
1445
1446         pm_runtime_forbid(&dev->pdev->dev);
1447
1448         ret = drm_crtc_helper_set_config(set);
1449
1450         pm_runtime_allow(&dev->pdev->dev);
1451
1452         return ret;
1453 }
1454
1455 /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
1456
1457 /* FIXME: why are we using this, should it be cdv_ in this tree ? */
1458
1459 static void i8xx_clock(int refclk, struct cdv_intel_clock_t *clock)
1460 {
1461         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
1462         clock->p = clock->p1 * clock->p2;
1463         clock->vco = refclk * clock->m / (clock->n + 2);
1464         clock->dot = clock->vco / clock->p;
1465 }
1466
1467 /* Returns the clock of the currently programmed mode of the given pipe. */
1468 static int cdv_intel_crtc_clock_get(struct drm_device *dev,
1469                                 struct drm_crtc *crtc)
1470 {
1471         struct drm_psb_private *dev_priv = dev->dev_private;
1472         struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1473         int pipe = psb_intel_crtc->pipe;
1474         const struct psb_offset *map = &dev_priv->regmap[pipe];
1475         u32 dpll;
1476         u32 fp;
1477         struct cdv_intel_clock_t clock;
1478         bool is_lvds;
1479         struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
1480
1481         if (gma_power_begin(dev, false)) {
1482                 dpll = REG_READ(map->dpll);
1483                 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
1484                         fp = REG_READ(map->fp0);
1485                 else
1486                         fp = REG_READ(map->fp1);
1487                 is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN);
1488                 gma_power_end(dev);
1489         } else {
1490                 dpll = p->dpll;
1491                 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
1492                         fp = p->fp0;
1493                 else
1494                         fp = p->fp1;
1495
1496                 is_lvds = (pipe == 1) &&
1497                                 (dev_priv->regs.psb.saveLVDS & LVDS_PORT_EN);
1498         }
1499
1500         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
1501         clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
1502         clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
1503
1504         if (is_lvds) {
1505                 clock.p1 =
1506                     ffs((dpll &
1507                          DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
1508                         DPLL_FPA01_P1_POST_DIV_SHIFT);
1509                 if (clock.p1 == 0) {
1510                         clock.p1 = 4;
1511                         dev_err(dev->dev, "PLL %d\n", dpll);
1512                 }
1513                 clock.p2 = 14;
1514
1515                 if ((dpll & PLL_REF_INPUT_MASK) ==
1516                     PLLB_REF_INPUT_SPREADSPECTRUMIN) {
1517                         /* XXX: might not be 66MHz */
1518                         i8xx_clock(66000, &clock);
1519                 } else
1520                         i8xx_clock(48000, &clock);
1521         } else {
1522                 if (dpll & PLL_P1_DIVIDE_BY_TWO)
1523                         clock.p1 = 2;
1524                 else {
1525                         clock.p1 =
1526                             ((dpll &
1527                               DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
1528                              DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
1529                 }
1530                 if (dpll & PLL_P2_DIVIDE_BY_4)
1531                         clock.p2 = 4;
1532                 else
1533                         clock.p2 = 2;
1534
1535                 i8xx_clock(48000, &clock);
1536         }
1537
1538         /* XXX: It would be nice to validate the clocks, but we can't reuse
1539          * i830PllIsValid() because it relies on the xf86_config connector
1540          * configuration being accurate, which it isn't necessarily.
1541          */
1542
1543         return clock.dot;
1544 }
1545
1546 /** Returns the currently programmed mode of the given pipe. */
1547 struct drm_display_mode *cdv_intel_crtc_mode_get(struct drm_device *dev,
1548                                              struct drm_crtc *crtc)
1549 {
1550         struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1551         int pipe = psb_intel_crtc->pipe;
1552         struct drm_psb_private *dev_priv = dev->dev_private;
1553         struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
1554         const struct psb_offset *map = &dev_priv->regmap[pipe];
1555         struct drm_display_mode *mode;
1556         int htot;
1557         int hsync;
1558         int vtot;
1559         int vsync;
1560
1561         if (gma_power_begin(dev, false)) {
1562                 htot = REG_READ(map->htotal);
1563                 hsync = REG_READ(map->hsync);
1564                 vtot = REG_READ(map->vtotal);
1565                 vsync = REG_READ(map->vsync);
1566                 gma_power_end(dev);
1567         } else {
1568                 htot = p->htotal;
1569                 hsync = p->hsync;
1570                 vtot = p->vtotal;
1571                 vsync = p->vsync;
1572         }
1573
1574         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
1575         if (!mode)
1576                 return NULL;
1577
1578         mode->clock = cdv_intel_crtc_clock_get(dev, crtc);
1579         mode->hdisplay = (htot & 0xffff) + 1;
1580         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
1581         mode->hsync_start = (hsync & 0xffff) + 1;
1582         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
1583         mode->vdisplay = (vtot & 0xffff) + 1;
1584         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
1585         mode->vsync_start = (vsync & 0xffff) + 1;
1586         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
1587
1588         drm_mode_set_name(mode);
1589         drm_mode_set_crtcinfo(mode, 0);
1590
1591         return mode;
1592 }
1593
1594 static void cdv_intel_crtc_destroy(struct drm_crtc *crtc)
1595 {
1596         struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1597
1598         kfree(psb_intel_crtc->crtc_state);
1599         drm_crtc_cleanup(crtc);
1600         kfree(psb_intel_crtc);
1601 }
1602
1603 const struct drm_crtc_helper_funcs cdv_intel_helper_funcs = {
1604         .dpms = cdv_intel_crtc_dpms,
1605         .mode_fixup = cdv_intel_crtc_mode_fixup,
1606         .mode_set = cdv_intel_crtc_mode_set,
1607         .mode_set_base = cdv_intel_pipe_set_base,
1608         .prepare = cdv_intel_crtc_prepare,
1609         .commit = cdv_intel_crtc_commit,
1610 };
1611
1612 const struct drm_crtc_funcs cdv_intel_crtc_funcs = {
1613         .save = cdv_intel_crtc_save,
1614         .restore = cdv_intel_crtc_restore,
1615         .cursor_set = cdv_intel_crtc_cursor_set,
1616         .cursor_move = cdv_intel_crtc_cursor_move,
1617         .gamma_set = cdv_intel_crtc_gamma_set,
1618         .set_config = cdv_crtc_set_config,
1619         .destroy = cdv_intel_crtc_destroy,
1620 };