2 * Copyright © 2006-2011 Intel Corporation
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc.,
15 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 * Eric Anholt <eric@anholt.net>
19 * Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
23 #include "gma_display.h"
24 #include "psb_intel_drv.h"
25 #include "psb_intel_reg.h"
27 #include "framebuffer.h"
30 * Returns whether any output on the specified pipe is of the specified type
32 bool gma_pipe_has_type(struct drm_crtc *crtc, int type)
34 struct drm_device *dev = crtc->dev;
35 struct drm_mode_config *mode_config = &dev->mode_config;
36 struct drm_connector *l_entry;
38 list_for_each_entry(l_entry, &mode_config->connector_list, head) {
39 if (l_entry->encoder && l_entry->encoder->crtc == crtc) {
40 struct gma_encoder *gma_encoder =
41 gma_attached_encoder(l_entry);
42 if (gma_encoder->type == type)
50 void gma_wait_for_vblank(struct drm_device *dev)
52 /* Wait for 20ms, i.e. one cycle at 50hz. */
56 int gma_pipe_set_base(struct drm_crtc *crtc, int x, int y,
57 struct drm_framebuffer *old_fb)
59 struct drm_device *dev = crtc->dev;
60 struct drm_psb_private *dev_priv = dev->dev_private;
61 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
62 struct psb_framebuffer *psbfb = to_psb_fb(crtc->primary->fb);
63 int pipe = gma_crtc->pipe;
64 const struct psb_offset *map = &dev_priv->regmap[pipe];
65 unsigned long start, offset;
69 if (!gma_power_begin(dev, true))
73 if (!crtc->primary->fb) {
74 dev_err(dev->dev, "No FB bound\n");
75 goto gma_pipe_cleaner;
78 /* We are displaying this buffer, make sure it is actually loaded
80 ret = psb_gtt_pin(psbfb->gtt);
82 goto gma_pipe_set_base_exit;
83 start = psbfb->gtt->offset;
84 offset = y * crtc->primary->fb->pitches[0] + x * (crtc->primary->fb->bits_per_pixel / 8);
86 REG_WRITE(map->stride, crtc->primary->fb->pitches[0]);
88 dspcntr = REG_READ(map->cntr);
89 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
91 switch (crtc->primary->fb->bits_per_pixel) {
93 dspcntr |= DISPPLANE_8BPP;
96 if (crtc->primary->fb->depth == 15)
97 dspcntr |= DISPPLANE_15_16BPP;
99 dspcntr |= DISPPLANE_16BPP;
103 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
106 dev_err(dev->dev, "Unknown color depth\n");
108 goto gma_pipe_set_base_exit;
110 REG_WRITE(map->cntr, dspcntr);
113 "Writing base %08lX %08lX %d %d\n", start, offset, x, y);
115 /* FIXME: Investigate whether this really is the base for psb and why
116 the linear offset is named base for the other chips. map->surf
117 should be the base and map->linoff the offset for all chips */
119 REG_WRITE(map->base, offset + start);
122 REG_WRITE(map->base, offset);
124 REG_WRITE(map->surf, start);
129 /* If there was a previous display we can now unpin it */
131 psb_gtt_unpin(to_psb_fb(old_fb)->gtt);
133 gma_pipe_set_base_exit:
138 /* Loads the palette/gamma unit for the CRTC with the prepared values */
139 void gma_crtc_load_lut(struct drm_crtc *crtc)
141 struct drm_device *dev = crtc->dev;
142 struct drm_psb_private *dev_priv = dev->dev_private;
143 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
144 const struct psb_offset *map = &dev_priv->regmap[gma_crtc->pipe];
145 int palreg = map->palette;
148 /* The clocks have to be on to load the palette. */
152 if (gma_power_begin(dev, false)) {
153 for (i = 0; i < 256; i++) {
154 REG_WRITE(palreg + 4 * i,
155 ((gma_crtc->lut_r[i] +
156 gma_crtc->lut_adj[i]) << 16) |
157 ((gma_crtc->lut_g[i] +
158 gma_crtc->lut_adj[i]) << 8) |
159 (gma_crtc->lut_b[i] +
160 gma_crtc->lut_adj[i]));
164 for (i = 0; i < 256; i++) {
165 /* FIXME: Why pipe[0] and not pipe[..._crtc->pipe]? */
166 dev_priv->regs.pipe[0].palette[i] =
167 ((gma_crtc->lut_r[i] +
168 gma_crtc->lut_adj[i]) << 16) |
169 ((gma_crtc->lut_g[i] +
170 gma_crtc->lut_adj[i]) << 8) |
171 (gma_crtc->lut_b[i] +
172 gma_crtc->lut_adj[i]);
178 void gma_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, u16 *blue,
181 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
183 int end = (start + size > 256) ? 256 : start + size;
185 for (i = start; i < end; i++) {
186 gma_crtc->lut_r[i] = red[i] >> 8;
187 gma_crtc->lut_g[i] = green[i] >> 8;
188 gma_crtc->lut_b[i] = blue[i] >> 8;
191 gma_crtc_load_lut(crtc);
195 * Sets the power management mode of the pipe and plane.
197 * This code should probably grow support for turning the cursor off and back
198 * on appropriately at the same time as we're turning the pipe off/on.
200 void gma_crtc_dpms(struct drm_crtc *crtc, int mode)
202 struct drm_device *dev = crtc->dev;
203 struct drm_psb_private *dev_priv = dev->dev_private;
204 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
205 int pipe = gma_crtc->pipe;
206 const struct psb_offset *map = &dev_priv->regmap[pipe];
209 /* XXX: When our outputs are all unaware of DPMS modes other than off
210 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
214 dev_priv->ops->disable_sr(dev);
217 case DRM_MODE_DPMS_ON:
218 case DRM_MODE_DPMS_STANDBY:
219 case DRM_MODE_DPMS_SUSPEND:
220 if (gma_crtc->active)
223 gma_crtc->active = true;
225 /* Enable the DPLL */
226 temp = REG_READ(map->dpll);
227 if ((temp & DPLL_VCO_ENABLE) == 0) {
228 REG_WRITE(map->dpll, temp);
230 /* Wait for the clocks to stabilize. */
232 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);
234 /* Wait for the clocks to stabilize. */
236 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);
238 /* Wait for the clocks to stabilize. */
242 /* Enable the plane */
243 temp = REG_READ(map->cntr);
244 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
246 temp | DISPLAY_PLANE_ENABLE);
247 /* Flush the plane changes */
248 REG_WRITE(map->base, REG_READ(map->base));
253 /* Enable the pipe */
254 temp = REG_READ(map->conf);
255 if ((temp & PIPEACONF_ENABLE) == 0)
256 REG_WRITE(map->conf, temp | PIPEACONF_ENABLE);
258 temp = REG_READ(map->status);
260 temp |= PIPE_FIFO_UNDERRUN;
261 REG_WRITE(map->status, temp);
262 REG_READ(map->status);
264 gma_crtc_load_lut(crtc);
266 /* Give the overlay scaler a chance to enable
267 * if it's on this pipe */
268 /* psb_intel_crtc_dpms_video(crtc, true); TODO */
270 case DRM_MODE_DPMS_OFF:
271 if (!gma_crtc->active)
274 gma_crtc->active = false;
276 /* Give the overlay scaler a chance to disable
277 * if it's on this pipe */
278 /* psb_intel_crtc_dpms_video(crtc, FALSE); TODO */
280 /* Disable the VGA plane that we never use */
281 REG_WRITE(VGACNTRL, VGA_DISP_DISABLE);
283 /* Turn off vblank interrupts */
284 drm_vblank_off(dev, pipe);
286 /* Wait for vblank for the disable to take effect */
287 gma_wait_for_vblank(dev);
290 temp = REG_READ(map->cntr);
291 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
293 temp & ~DISPLAY_PLANE_ENABLE);
294 /* Flush the plane changes */
295 REG_WRITE(map->base, REG_READ(map->base));
300 temp = REG_READ(map->conf);
301 if ((temp & PIPEACONF_ENABLE) != 0) {
302 REG_WRITE(map->conf, temp & ~PIPEACONF_ENABLE);
306 /* Wait for vblank for the disable to take effect. */
307 gma_wait_for_vblank(dev);
312 temp = REG_READ(map->dpll);
313 if ((temp & DPLL_VCO_ENABLE) != 0) {
314 REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE);
318 /* Wait for the clocks to turn off. */
324 dev_priv->ops->update_wm(dev, crtc);
326 /* Set FIFO watermarks */
327 REG_WRITE(DSPARB, 0x3F3E);
330 int gma_crtc_cursor_set(struct drm_crtc *crtc,
331 struct drm_file *file_priv,
333 uint32_t width, uint32_t height)
335 struct drm_device *dev = crtc->dev;
336 struct drm_psb_private *dev_priv = dev->dev_private;
337 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
338 int pipe = gma_crtc->pipe;
339 uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
340 uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
343 struct gtt_range *gt;
344 struct gtt_range *cursor_gt = gma_crtc->cursor_gt;
345 struct drm_gem_object *obj;
346 void *tmp_dst, *tmp_src;
347 int ret = 0, i, cursor_pages;
349 /* If we didn't get a handle then turn the cursor off */
351 temp = CURSOR_MODE_DISABLE;
352 if (gma_power_begin(dev, false)) {
353 REG_WRITE(control, temp);
358 /* Unpin the old GEM object */
359 if (gma_crtc->cursor_obj) {
360 gt = container_of(gma_crtc->cursor_obj,
361 struct gtt_range, gem);
363 drm_gem_object_unreference_unlocked(gma_crtc->cursor_obj);
364 gma_crtc->cursor_obj = NULL;
369 /* Currently we only support 64x64 cursors */
370 if (width != 64 || height != 64) {
371 dev_dbg(dev->dev, "We currently only support 64x64 cursors\n");
375 obj = drm_gem_object_lookup(file_priv, handle);
381 if (obj->size < width * height * 4) {
382 dev_dbg(dev->dev, "Buffer is too small\n");
387 gt = container_of(obj, struct gtt_range, gem);
389 /* Pin the memory into the GTT */
390 ret = psb_gtt_pin(gt);
392 dev_err(dev->dev, "Can not pin down handle 0x%x\n", handle);
396 if (dev_priv->ops->cursor_needs_phys) {
397 if (cursor_gt == NULL) {
398 dev_err(dev->dev, "No hardware cursor mem available");
403 /* Prevent overflow */
407 cursor_pages = gt->npage;
409 /* Copy the cursor to cursor mem */
410 tmp_dst = dev_priv->vram_addr + cursor_gt->offset;
411 for (i = 0; i < cursor_pages; i++) {
412 tmp_src = kmap(gt->pages[i]);
413 memcpy(tmp_dst, tmp_src, PAGE_SIZE);
414 kunmap(gt->pages[i]);
415 tmp_dst += PAGE_SIZE;
418 addr = gma_crtc->cursor_addr;
421 gma_crtc->cursor_addr = addr;
425 /* set the pipe for the cursor */
426 temp |= (pipe << 28);
427 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
429 if (gma_power_begin(dev, false)) {
430 REG_WRITE(control, temp);
431 REG_WRITE(base, addr);
435 /* unpin the old bo */
436 if (gma_crtc->cursor_obj) {
437 gt = container_of(gma_crtc->cursor_obj, struct gtt_range, gem);
439 drm_gem_object_unreference_unlocked(gma_crtc->cursor_obj);
442 gma_crtc->cursor_obj = obj;
447 drm_gem_object_unreference_unlocked(obj);
451 int gma_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
453 struct drm_device *dev = crtc->dev;
454 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
455 int pipe = gma_crtc->pipe;
460 temp |= (CURSOR_POS_SIGN << CURSOR_X_SHIFT);
464 temp |= (CURSOR_POS_SIGN << CURSOR_Y_SHIFT);
468 temp |= ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT);
469 temp |= ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
471 addr = gma_crtc->cursor_addr;
473 if (gma_power_begin(dev, false)) {
474 REG_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
475 REG_WRITE((pipe == 0) ? CURABASE : CURBBASE, addr);
481 void gma_crtc_prepare(struct drm_crtc *crtc)
483 const struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
484 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
487 void gma_crtc_commit(struct drm_crtc *crtc)
489 const struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
490 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
493 void gma_crtc_disable(struct drm_crtc *crtc)
495 struct gtt_range *gt;
496 const struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
498 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
500 if (crtc->primary->fb) {
501 gt = to_psb_fb(crtc->primary->fb)->gtt;
506 void gma_crtc_destroy(struct drm_crtc *crtc)
508 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
510 kfree(gma_crtc->crtc_state);
511 drm_crtc_cleanup(crtc);
515 int gma_crtc_set_config(struct drm_mode_set *set)
517 struct drm_device *dev = set->crtc->dev;
518 struct drm_psb_private *dev_priv = dev->dev_private;
521 if (!dev_priv->rpm_enabled)
522 return drm_crtc_helper_set_config(set);
524 pm_runtime_forbid(&dev->pdev->dev);
525 ret = drm_crtc_helper_set_config(set);
526 pm_runtime_allow(&dev->pdev->dev);
532 * Save HW states of given crtc
534 void gma_crtc_save(struct drm_crtc *crtc)
536 struct drm_device *dev = crtc->dev;
537 struct drm_psb_private *dev_priv = dev->dev_private;
538 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
539 struct psb_intel_crtc_state *crtc_state = gma_crtc->crtc_state;
540 const struct psb_offset *map = &dev_priv->regmap[gma_crtc->pipe];
541 uint32_t palette_reg;
545 dev_err(dev->dev, "No CRTC state found\n");
549 crtc_state->saveDSPCNTR = REG_READ(map->cntr);
550 crtc_state->savePIPECONF = REG_READ(map->conf);
551 crtc_state->savePIPESRC = REG_READ(map->src);
552 crtc_state->saveFP0 = REG_READ(map->fp0);
553 crtc_state->saveFP1 = REG_READ(map->fp1);
554 crtc_state->saveDPLL = REG_READ(map->dpll);
555 crtc_state->saveHTOTAL = REG_READ(map->htotal);
556 crtc_state->saveHBLANK = REG_READ(map->hblank);
557 crtc_state->saveHSYNC = REG_READ(map->hsync);
558 crtc_state->saveVTOTAL = REG_READ(map->vtotal);
559 crtc_state->saveVBLANK = REG_READ(map->vblank);
560 crtc_state->saveVSYNC = REG_READ(map->vsync);
561 crtc_state->saveDSPSTRIDE = REG_READ(map->stride);
563 /* NOTE: DSPSIZE DSPPOS only for psb */
564 crtc_state->saveDSPSIZE = REG_READ(map->size);
565 crtc_state->saveDSPPOS = REG_READ(map->pos);
567 crtc_state->saveDSPBASE = REG_READ(map->base);
569 palette_reg = map->palette;
570 for (i = 0; i < 256; ++i)
571 crtc_state->savePalette[i] = REG_READ(palette_reg + (i << 2));
575 * Restore HW states of given crtc
577 void gma_crtc_restore(struct drm_crtc *crtc)
579 struct drm_device *dev = crtc->dev;
580 struct drm_psb_private *dev_priv = dev->dev_private;
581 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
582 struct psb_intel_crtc_state *crtc_state = gma_crtc->crtc_state;
583 const struct psb_offset *map = &dev_priv->regmap[gma_crtc->pipe];
584 uint32_t palette_reg;
588 dev_err(dev->dev, "No crtc state\n");
592 if (crtc_state->saveDPLL & DPLL_VCO_ENABLE) {
594 crtc_state->saveDPLL & ~DPLL_VCO_ENABLE);
599 REG_WRITE(map->fp0, crtc_state->saveFP0);
602 REG_WRITE(map->fp1, crtc_state->saveFP1);
605 REG_WRITE(map->dpll, crtc_state->saveDPLL);
609 REG_WRITE(map->htotal, crtc_state->saveHTOTAL);
610 REG_WRITE(map->hblank, crtc_state->saveHBLANK);
611 REG_WRITE(map->hsync, crtc_state->saveHSYNC);
612 REG_WRITE(map->vtotal, crtc_state->saveVTOTAL);
613 REG_WRITE(map->vblank, crtc_state->saveVBLANK);
614 REG_WRITE(map->vsync, crtc_state->saveVSYNC);
615 REG_WRITE(map->stride, crtc_state->saveDSPSTRIDE);
617 REG_WRITE(map->size, crtc_state->saveDSPSIZE);
618 REG_WRITE(map->pos, crtc_state->saveDSPPOS);
620 REG_WRITE(map->src, crtc_state->savePIPESRC);
621 REG_WRITE(map->base, crtc_state->saveDSPBASE);
622 REG_WRITE(map->conf, crtc_state->savePIPECONF);
624 gma_wait_for_vblank(dev);
626 REG_WRITE(map->cntr, crtc_state->saveDSPCNTR);
627 REG_WRITE(map->base, crtc_state->saveDSPBASE);
629 gma_wait_for_vblank(dev);
631 palette_reg = map->palette;
632 for (i = 0; i < 256; ++i)
633 REG_WRITE(palette_reg + (i << 2), crtc_state->savePalette[i]);
636 void gma_encoder_prepare(struct drm_encoder *encoder)
638 const struct drm_encoder_helper_funcs *encoder_funcs =
639 encoder->helper_private;
640 /* lvds has its own version of prepare see psb_intel_lvds_prepare */
641 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
644 void gma_encoder_commit(struct drm_encoder *encoder)
646 const struct drm_encoder_helper_funcs *encoder_funcs =
647 encoder->helper_private;
648 /* lvds has its own version of commit see psb_intel_lvds_commit */
649 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
652 void gma_encoder_destroy(struct drm_encoder *encoder)
654 struct gma_encoder *intel_encoder = to_gma_encoder(encoder);
656 drm_encoder_cleanup(encoder);
657 kfree(intel_encoder);
660 /* Currently there is only a 1:1 mapping of encoders and connectors */
661 struct drm_encoder *gma_best_encoder(struct drm_connector *connector)
663 struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
665 return &gma_encoder->base;
668 void gma_connector_attach_encoder(struct gma_connector *connector,
669 struct gma_encoder *encoder)
671 connector->encoder = encoder;
672 drm_mode_connector_attach_encoder(&connector->base,
676 #define GMA_PLL_INVALID(s) { /* DRM_ERROR(s); */ return false; }
678 bool gma_pll_is_valid(struct drm_crtc *crtc,
679 const struct gma_limit_t *limit,
680 struct gma_clock_t *clock)
682 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
683 GMA_PLL_INVALID("p1 out of range");
684 if (clock->p < limit->p.min || limit->p.max < clock->p)
685 GMA_PLL_INVALID("p out of range");
686 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
687 GMA_PLL_INVALID("m2 out of range");
688 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
689 GMA_PLL_INVALID("m1 out of range");
690 /* On CDV m1 is always 0 */
691 if (clock->m1 <= clock->m2 && clock->m1 != 0)
692 GMA_PLL_INVALID("m1 <= m2 && m1 != 0");
693 if (clock->m < limit->m.min || limit->m.max < clock->m)
694 GMA_PLL_INVALID("m out of range");
695 if (clock->n < limit->n.min || limit->n.max < clock->n)
696 GMA_PLL_INVALID("n out of range");
697 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
698 GMA_PLL_INVALID("vco out of range");
699 /* XXX: We may need to be checking "Dot clock"
700 * depending on the multiplier, connector, etc.,
701 * rather than just a single range.
703 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
704 GMA_PLL_INVALID("dot out of range");
709 bool gma_find_best_pll(const struct gma_limit_t *limit,
710 struct drm_crtc *crtc, int target, int refclk,
711 struct gma_clock_t *best_clock)
713 struct drm_device *dev = crtc->dev;
714 const struct gma_clock_funcs *clock_funcs =
715 to_gma_crtc(crtc)->clock_funcs;
716 struct gma_clock_t clock;
719 if (gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
720 (REG_READ(LVDS) & LVDS_PORT_EN) != 0) {
722 * For LVDS, if the panel is on, just rely on its current
723 * settings for dual-channel. We haven't figured out how to
724 * reliably set up different single/dual channel state, if we
727 if ((REG_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
729 clock.p2 = limit->p2.p2_fast;
731 clock.p2 = limit->p2.p2_slow;
733 if (target < limit->p2.dot_limit)
734 clock.p2 = limit->p2.p2_slow;
736 clock.p2 = limit->p2.p2_fast;
739 memset(best_clock, 0, sizeof(*best_clock));
741 /* m1 is always 0 on CDV so the outmost loop will run just once */
742 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
743 for (clock.m2 = limit->m2.min;
744 (clock.m2 < clock.m1 || clock.m1 == 0) &&
745 clock.m2 <= limit->m2.max; clock.m2++) {
746 for (clock.n = limit->n.min;
747 clock.n <= limit->n.max; clock.n++) {
748 for (clock.p1 = limit->p1.min;
749 clock.p1 <= limit->p1.max;
753 clock_funcs->clock(refclk, &clock);
755 if (!clock_funcs->pll_is_valid(crtc,
759 this_err = abs(clock.dot - target);
760 if (this_err < err) {
769 return err != target;