drivers/gpu/drm/gma500/gma_display.c

   1 /*
   2  * Copyright © 2006-2011 Intel Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program; if not, write to the Free Software Foundation, Inc.,
  15  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  16  *
  17  * Authors:
  18  *      Eric Anholt <eric@anholt.net>
  19  *      Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
  20  */
  21
  22 #include <drm/drmP.h>
  23 #include "gma_display.h"
  24 #include "psb_intel_drv.h"
  25 #include "psb_intel_reg.h"
  26 #include "psb_drv.h"
  27 #include "framebuffer.h"
  28
  29 /**
  30  * Returns whether any output on the specified pipe is of the specified type
  31  */
  32 bool gma_pipe_has_type(struct drm_crtc *crtc, int type)
  33 {
  34         struct drm_device *dev = crtc->dev;
  35         struct drm_mode_config *mode_config = &dev->mode_config;
  36         struct drm_connector *l_entry;
  37
  38         list_for_each_entry(l_entry, &mode_config->connector_list, head) {
  39                 if (l_entry->encoder && l_entry->encoder->crtc == crtc) {
  40                         struct gma_encoder *gma_encoder =
  41                                                 gma_attached_encoder(l_entry);
  42                         if (gma_encoder->type == type)
  43                                 return true;
  44                 }
  45         }
  46
  47         return false;
  48 }
  49
  50 void gma_wait_for_vblank(struct drm_device *dev)
  51 {
  52         /* Wait for 20ms, i.e. one cycle at 50hz. */
  53         mdelay(20);
  54 }
  55
  56 int gma_pipe_set_base(struct drm_crtc *crtc, int x, int y,
  57                       struct drm_framebuffer *old_fb)
  58 {
  59         struct drm_device *dev = crtc->dev;
  60         struct drm_psb_private *dev_priv = dev->dev_private;
  61         struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
  62         struct drm_framebuffer *fb = crtc->primary->fb;
  63         struct psb_framebuffer *psbfb = to_psb_fb(fb);
  64         int pipe = gma_crtc->pipe;
  65         const struct psb_offset *map = &dev_priv->regmap[pipe];
  66         unsigned long start, offset;
  67         u32 dspcntr;
  68         int ret = 0;
  69
  70         if (!gma_power_begin(dev, true))
  71                 return 0;
  72
  73         /* no fb bound */
  74         if (!fb) {
  75                 dev_err(dev->dev, "No FB bound\n");
  76                 goto gma_pipe_cleaner;
  77         }
  78
  79         /* We are displaying this buffer, make sure it is actually loaded
  80            into the GTT */
  81         ret = psb_gtt_pin(psbfb->gtt);
  82         if (ret < 0)
  83                 goto gma_pipe_set_base_exit;
  84         start = psbfb->gtt->offset;
  85         offset = y * fb->pitches[0] + x * fb->format->cpp[0];
  86
  87         REG_WRITE(map->stride, fb->pitches[0]);
  88
  89         dspcntr = REG_READ(map->cntr);
  90         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
  91
  92         switch (fb->format->cpp[0] * 8) {
  93         case 8:
  94                 dspcntr |= DISPPLANE_8BPP;
  95                 break;
  96         case 16:
  97                 if (fb->format->depth == 15)
  98                         dspcntr |= DISPPLANE_15_16BPP;
  99                 else
 100                         dspcntr |= DISPPLANE_16BPP;
 101                 break;
 102         case 24:
 103         case 32:
 104                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
 105                 break;
 106         default:
 107                 dev_err(dev->dev, "Unknown color depth\n");
 108                 ret = -EINVAL;
 109                 goto gma_pipe_set_base_exit;
 110         }
 111         REG_WRITE(map->cntr, dspcntr);
 112
 113         dev_dbg(dev->dev,
 114                 "Writing base %08lX %08lX %d %d\n", start, offset, x, y);
 115
 116         /* FIXME: Investigate whether this really is the base for psb and why
 117                   the linear offset is named base for the other chips. map->surf
 118                   should be the base and map->linoff the offset for all chips */
 119         if (IS_PSB(dev)) {
 120                 REG_WRITE(map->base, offset + start);
 121                 REG_READ(map->base);
 122         } else {
 123                 REG_WRITE(map->base, offset);
 124                 REG_READ(map->base);
 125                 REG_WRITE(map->surf, start);
 126                 REG_READ(map->surf);
 127         }
 128
 129 gma_pipe_cleaner:
 130         /* If there was a previous display we can now unpin it */
 131         if (old_fb)
 132                 psb_gtt_unpin(to_psb_fb(old_fb)->gtt);
 133
 134 gma_pipe_set_base_exit:
 135         gma_power_end(dev);
 136         return ret;
 137 }
 138
 139 /* Loads the palette/gamma unit for the CRTC with the prepared values */
 140 void gma_crtc_load_lut(struct drm_crtc *crtc)
 141 {
 142         struct drm_device *dev = crtc->dev;
 143         struct drm_psb_private *dev_priv = dev->dev_private;
 144         struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
 145         const struct psb_offset *map = &dev_priv->regmap[gma_crtc->pipe];
 146         int palreg = map->palette;
 147         int i;
 148
 149         /* The clocks have to be on to load the palette. */
 150         if (!crtc->enabled)
 151                 return;
 152
 153         if (gma_power_begin(dev, false)) {
 154                 for (i = 0; i < 256; i++) {
 155                         REG_WRITE(palreg + 4 * i,
 156                                   ((gma_crtc->lut_r[i] +
 157                                   gma_crtc->lut_adj[i]) << 16) |
 158                                   ((gma_crtc->lut_g[i] +
 159                                   gma_crtc->lut_adj[i]) << 8) |
 160                                   (gma_crtc->lut_b[i] +
 161                                   gma_crtc->lut_adj[i]));
 162                 }
 163                 gma_power_end(dev);
 164         } else {
 165                 for (i = 0; i < 256; i++) {
 166                         /* FIXME: Why pipe[0] and not pipe[..._crtc->pipe]? */
 167                         dev_priv->regs.pipe[0].palette[i] =
 168                                   ((gma_crtc->lut_r[i] +
 169                                   gma_crtc->lut_adj[i]) << 16) |
 170                                   ((gma_crtc->lut_g[i] +
 171                                   gma_crtc->lut_adj[i]) << 8) |
 172                                   (gma_crtc->lut_b[i] +
 173                                   gma_crtc->lut_adj[i]);
 174                 }
 175
 176         }
 177 }
 178
 179 int gma_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, u16 *blue,
 180                        u32 size,
 181                        struct drm_modeset_acquire_ctx *ctx)
 182 {
 183         struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
 184         int i;
 185
 186         for (i = 0; i < size; i++) {
 187                 gma_crtc->lut_r[i] = red[i] >> 8;
 188                 gma_crtc->lut_g[i] = green[i] >> 8;
 189                 gma_crtc->lut_b[i] = blue[i] >> 8;
 190         }
 191
 192         gma_crtc_load_lut(crtc);
 193
 194         return 0;
 195 }
 196
 197 /**
 198  * Sets the power management mode of the pipe and plane.
 199  *
 200  * This code should probably grow support for turning the cursor off and back
 201  * on appropriately at the same time as we're turning the pipe off/on.
 202  */
 203 void gma_crtc_dpms(struct drm_crtc *crtc, int mode)
 204 {
 205         struct drm_device *dev = crtc->dev;
 206         struct drm_psb_private *dev_priv = dev->dev_private;
 207         struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
 208         int pipe = gma_crtc->pipe;
 209         const struct psb_offset *map = &dev_priv->regmap[pipe];
 210         u32 temp;
 211
 212         /* XXX: When our outputs are all unaware of DPMS modes other than off
 213          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
 214          */
 215
 216         if (IS_CDV(dev))
 217                 dev_priv->ops->disable_sr(dev);
 218
 219         switch (mode) {
 220         case DRM_MODE_DPMS_ON:
 221         case DRM_MODE_DPMS_STANDBY:
 222         case DRM_MODE_DPMS_SUSPEND:
 223                 if (gma_crtc->active)
 224                         break;
 225
 226                 gma_crtc->active = true;
 227
 228                 /* Enable the DPLL */
 229                 temp = REG_READ(map->dpll);
 230                 if ((temp & DPLL_VCO_ENABLE) == 0) {
 231                         REG_WRITE(map->dpll, temp);
 232                         REG_READ(map->dpll);
 233                         /* Wait for the clocks to stabilize. */
 234                         udelay(150);
 235                         REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);
 236                         REG_READ(map->dpll);
 237                         /* Wait for the clocks to stabilize. */
 238                         udelay(150);
 239                         REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);
 240                         REG_READ(map->dpll);
 241                         /* Wait for the clocks to stabilize. */
 242                         udelay(150);
 243                 }
 244
 245                 /* Enable the plane */
 246                 temp = REG_READ(map->cntr);
 247                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
 248                         REG_WRITE(map->cntr,
 249                                   temp | DISPLAY_PLANE_ENABLE);
 250                         /* Flush the plane changes */
 251                         REG_WRITE(map->base, REG_READ(map->base));
 252                 }
 253
 254                 udelay(150);
 255
 256                 /* Enable the pipe */
 257                 temp = REG_READ(map->conf);
 258                 if ((temp & PIPEACONF_ENABLE) == 0)
 259                         REG_WRITE(map->conf, temp | PIPEACONF_ENABLE);
 260
 261                 temp = REG_READ(map->status);
 262                 temp &= ~(0xFFFF);
 263                 temp |= PIPE_FIFO_UNDERRUN;
 264                 REG_WRITE(map->status, temp);
 265                 REG_READ(map->status);
 266
 267                 gma_crtc_load_lut(crtc);
 268
 269                 /* Give the overlay scaler a chance to enable
 270                  * if it's on this pipe */
 271                 /* psb_intel_crtc_dpms_video(crtc, true); TODO */
 272                 break;
 273         case DRM_MODE_DPMS_OFF:
 274                 if (!gma_crtc->active)
 275                         break;
 276
 277                 gma_crtc->active = false;
 278
 279                 /* Give the overlay scaler a chance to disable
 280                  * if it's on this pipe */
 281                 /* psb_intel_crtc_dpms_video(crtc, FALSE); TODO */
 282
 283                 /* Disable the VGA plane that we never use */
 284                 REG_WRITE(VGACNTRL, VGA_DISP_DISABLE);
 285
 286                 /* Turn off vblank interrupts */
 287                 drm_crtc_vblank_off(crtc);
 288
 289                 /* Wait for vblank for the disable to take effect */
 290                 gma_wait_for_vblank(dev);
 291
 292                 /* Disable plane */
 293                 temp = REG_READ(map->cntr);
 294                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
 295                         REG_WRITE(map->cntr,
 296                                   temp & ~DISPLAY_PLANE_ENABLE);
 297                         /* Flush the plane changes */
 298                         REG_WRITE(map->base, REG_READ(map->base));
 299                         REG_READ(map->base);
 300                 }
 301
 302                 /* Disable pipe */
 303                 temp = REG_READ(map->conf);
 304                 if ((temp & PIPEACONF_ENABLE) != 0) {
 305                         REG_WRITE(map->conf, temp & ~PIPEACONF_ENABLE);
 306                         REG_READ(map->conf);
 307                 }
 308
 309                 /* Wait for vblank for the disable to take effect. */
 310                 gma_wait_for_vblank(dev);
 311
 312                 udelay(150);
 313
 314                 /* Disable DPLL */
 315                 temp = REG_READ(map->dpll);
 316                 if ((temp & DPLL_VCO_ENABLE) != 0) {
 317                         REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE);
 318                         REG_READ(map->dpll);
 319                 }
 320
 321                 /* Wait for the clocks to turn off. */
 322                 udelay(150);
 323                 break;
 324         }
 325
 326         if (IS_CDV(dev))
 327                 dev_priv->ops->update_wm(dev, crtc);
 328
 329         /* Set FIFO watermarks */
 330         REG_WRITE(DSPARB, 0x3F3E);
 331 }
 332
 333 int gma_crtc_cursor_set(struct drm_crtc *crtc,
 334                         struct drm_file *file_priv,
 335                         uint32_t handle,
 336                         uint32_t width, uint32_t height)
 337 {
 338         struct drm_device *dev = crtc->dev;
 339         struct drm_psb_private *dev_priv = dev->dev_private;
 340         struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
 341         int pipe = gma_crtc->pipe;
 342         uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
 343         uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
 344         uint32_t temp;
 345         size_t addr = 0;
 346         struct gtt_range *gt;
 347         struct gtt_range *cursor_gt = gma_crtc->cursor_gt;
 348         struct drm_gem_object *obj;
 349         void *tmp_dst, *tmp_src;
 350         int ret = 0, i, cursor_pages;
 351
 352         /* If we didn't get a handle then turn the cursor off */
 353         if (!handle) {
 354                 temp = CURSOR_MODE_DISABLE;
 355                 if (gma_power_begin(dev, false)) {
 356                         REG_WRITE(control, temp);
 357                         REG_WRITE(base, 0);
 358                         gma_power_end(dev);
 359                 }
 360
 361                 /* Unpin the old GEM object */
 362                 if (gma_crtc->cursor_obj) {
 363                         gt = container_of(gma_crtc->cursor_obj,
 364                                           struct gtt_range, gem);
 365                         psb_gtt_unpin(gt);
 366                         drm_gem_object_unreference_unlocked(gma_crtc->cursor_obj);
 367                         gma_crtc->cursor_obj = NULL;
 368                 }
 369                 return 0;
 370         }
 371
 372         /* Currently we only support 64x64 cursors */
 373         if (width != 64 || height != 64) {
 374                 dev_dbg(dev->dev, "We currently only support 64x64 cursors\n");
 375                 return -EINVAL;
 376         }
 377
 378         obj = drm_gem_object_lookup(file_priv, handle);
 379         if (!obj) {
 380                 ret = -ENOENT;
 381                 goto unlock;
 382         }
 383
 384         if (obj->size < width * height * 4) {
 385                 dev_dbg(dev->dev, "Buffer is too small\n");
 386                 ret = -ENOMEM;
 387                 goto unref_cursor;
 388         }
 389
 390         gt = container_of(obj, struct gtt_range, gem);
 391
 392         /* Pin the memory into the GTT */
 393         ret = psb_gtt_pin(gt);
 394         if (ret) {
 395                 dev_err(dev->dev, "Can not pin down handle 0x%x\n", handle);
 396                 goto unref_cursor;
 397         }
 398
 399         if (dev_priv->ops->cursor_needs_phys) {
 400                 if (cursor_gt == NULL) {
 401                         dev_err(dev->dev, "No hardware cursor mem available");
 402                         ret = -ENOMEM;
 403                         goto unref_cursor;
 404                 }
 405
 406                 /* Prevent overflow */
 407                 if (gt->npage > 4)
 408                         cursor_pages = 4;
 409                 else
 410                         cursor_pages = gt->npage;
 411
 412                 /* Copy the cursor to cursor mem */
 413                 tmp_dst = dev_priv->vram_addr + cursor_gt->offset;
 414                 for (i = 0; i < cursor_pages; i++) {
 415                         tmp_src = kmap(gt->pages[i]);
 416                         memcpy(tmp_dst, tmp_src, PAGE_SIZE);
 417                         kunmap(gt->pages[i]);
 418                         tmp_dst += PAGE_SIZE;
 419                 }
 420
 421                 addr = gma_crtc->cursor_addr;
 422         } else {
 423                 addr = gt->offset;
 424                 gma_crtc->cursor_addr = addr;
 425         }
 426
 427         temp = 0;
 428         /* set the pipe for the cursor */
 429         temp |= (pipe << 28);
 430         temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
 431
 432         if (gma_power_begin(dev, false)) {
 433                 REG_WRITE(control, temp);
 434                 REG_WRITE(base, addr);
 435                 gma_power_end(dev);
 436         }
 437
 438         /* unpin the old bo */
 439         if (gma_crtc->cursor_obj) {
 440                 gt = container_of(gma_crtc->cursor_obj, struct gtt_range, gem);
 441                 psb_gtt_unpin(gt);
 442                 drm_gem_object_unreference_unlocked(gma_crtc->cursor_obj);
 443         }
 444
 445         gma_crtc->cursor_obj = obj;
 446 unlock:
 447         return ret;
 448
 449 unref_cursor:
 450         drm_gem_object_unreference_unlocked(obj);
 451         return ret;
 452 }
 453
 454 int gma_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
 455 {
 456         struct drm_device *dev = crtc->dev;
 457         struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
 458         int pipe = gma_crtc->pipe;
 459         uint32_t temp = 0;
 460         uint32_t addr;
 461
 462         if (x < 0) {
 463                 temp |= (CURSOR_POS_SIGN << CURSOR_X_SHIFT);
 464                 x = -x;
 465         }
 466         if (y < 0) {
 467                 temp |= (CURSOR_POS_SIGN << CURSOR_Y_SHIFT);
 468                 y = -y;
 469         }
 470
 471         temp |= ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT);
 472         temp |= ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
 473
 474         addr = gma_crtc->cursor_addr;
 475
 476         if (gma_power_begin(dev, false)) {
 477                 REG_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
 478                 REG_WRITE((pipe == 0) ? CURABASE : CURBBASE, addr);
 479                 gma_power_end(dev);
 480         }
 481         return 0;
 482 }
 483
 484 void gma_crtc_prepare(struct drm_crtc *crtc)
 485 {
 486         const struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
 487         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
 488 }
 489
 490 void gma_crtc_commit(struct drm_crtc *crtc)
 491 {
 492         const struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
 493         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
 494 }
 495
 496 void gma_crtc_disable(struct drm_crtc *crtc)
 497 {
 498         struct gtt_range *gt;
 499         const struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
 500
 501         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
 502
 503         if (crtc->primary->fb) {
 504                 gt = to_psb_fb(crtc->primary->fb)->gtt;
 505                 psb_gtt_unpin(gt);
 506         }
 507 }
 508
 509 void gma_crtc_destroy(struct drm_crtc *crtc)
 510 {
 511         struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
 512
 513         kfree(gma_crtc->crtc_state);
 514         drm_crtc_cleanup(crtc);
 515         kfree(gma_crtc);
 516 }
 517
 518 int gma_crtc_set_config(struct drm_mode_set *set,
 519                         struct drm_modeset_acquire_ctx *ctx)
 520 {
 521         struct drm_device *dev = set->crtc->dev;
 522         struct drm_psb_private *dev_priv = dev->dev_private;
 523         int ret;
 524
 525         if (!dev_priv->rpm_enabled)
 526                 return drm_crtc_helper_set_config(set, ctx);
 527
 528         pm_runtime_forbid(&dev->pdev->dev);
 529         ret = drm_crtc_helper_set_config(set, ctx);
 530         pm_runtime_allow(&dev->pdev->dev);
 531
 532         return ret;
 533 }
 534
 535 /**
 536  * Save HW states of given crtc
 537  */
 538 void gma_crtc_save(struct drm_crtc *crtc)
 539 {
 540         struct drm_device *dev = crtc->dev;
 541         struct drm_psb_private *dev_priv = dev->dev_private;
 542         struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
 543         struct psb_intel_crtc_state *crtc_state = gma_crtc->crtc_state;
 544         const struct psb_offset *map = &dev_priv->regmap[gma_crtc->pipe];
 545         uint32_t palette_reg;
 546         int i;
 547
 548         if (!crtc_state) {
 549                 dev_err(dev->dev, "No CRTC state found\n");
 550                 return;
 551         }
 552
 553         crtc_state->saveDSPCNTR = REG_READ(map->cntr);
 554         crtc_state->savePIPECONF = REG_READ(map->conf);
 555         crtc_state->savePIPESRC = REG_READ(map->src);
 556         crtc_state->saveFP0 = REG_READ(map->fp0);
 557         crtc_state->saveFP1 = REG_READ(map->fp1);
 558         crtc_state->saveDPLL = REG_READ(map->dpll);
 559         crtc_state->saveHTOTAL = REG_READ(map->htotal);
 560         crtc_state->saveHBLANK = REG_READ(map->hblank);
 561         crtc_state->saveHSYNC = REG_READ(map->hsync);
 562         crtc_state->saveVTOTAL = REG_READ(map->vtotal);
 563         crtc_state->saveVBLANK = REG_READ(map->vblank);
 564         crtc_state->saveVSYNC = REG_READ(map->vsync);
 565         crtc_state->saveDSPSTRIDE = REG_READ(map->stride);
 566
 567         /* NOTE: DSPSIZE DSPPOS only for psb */
 568         crtc_state->saveDSPSIZE = REG_READ(map->size);
 569         crtc_state->saveDSPPOS = REG_READ(map->pos);
 570
 571         crtc_state->saveDSPBASE = REG_READ(map->base);
 572
 573         palette_reg = map->palette;
 574         for (i = 0; i < 256; ++i)
 575                 crtc_state->savePalette[i] = REG_READ(palette_reg + (i << 2));
 576 }
 577
 578 /**
 579  * Restore HW states of given crtc
 580  */
 581 void gma_crtc_restore(struct drm_crtc *crtc)
 582 {
 583         struct drm_device *dev = crtc->dev;
 584         struct drm_psb_private *dev_priv = dev->dev_private;
 585         struct gma_crtc *gma_crtc =  to_gma_crtc(crtc);
 586         struct psb_intel_crtc_state *crtc_state = gma_crtc->crtc_state;
 587         const struct psb_offset *map = &dev_priv->regmap[gma_crtc->pipe];
 588         uint32_t palette_reg;
 589         int i;
 590
 591         if (!crtc_state) {
 592                 dev_err(dev->dev, "No crtc state\n");
 593                 return;
 594         }
 595
 596         if (crtc_state->saveDPLL & DPLL_VCO_ENABLE) {
 597                 REG_WRITE(map->dpll,
 598                         crtc_state->saveDPLL & ~DPLL_VCO_ENABLE);
 599                 REG_READ(map->dpll);
 600                 udelay(150);
 601         }
 602
 603         REG_WRITE(map->fp0, crtc_state->saveFP0);
 604         REG_READ(map->fp0);
 605
 606         REG_WRITE(map->fp1, crtc_state->saveFP1);
 607         REG_READ(map->fp1);
 608
 609         REG_WRITE(map->dpll, crtc_state->saveDPLL);
 610         REG_READ(map->dpll);
 611         udelay(150);
 612
 613         REG_WRITE(map->htotal, crtc_state->saveHTOTAL);
 614         REG_WRITE(map->hblank, crtc_state->saveHBLANK);
 615         REG_WRITE(map->hsync, crtc_state->saveHSYNC);
 616         REG_WRITE(map->vtotal, crtc_state->saveVTOTAL);
 617         REG_WRITE(map->vblank, crtc_state->saveVBLANK);
 618         REG_WRITE(map->vsync, crtc_state->saveVSYNC);
 619         REG_WRITE(map->stride, crtc_state->saveDSPSTRIDE);
 620
 621         REG_WRITE(map->size, crtc_state->saveDSPSIZE);
 622         REG_WRITE(map->pos, crtc_state->saveDSPPOS);
 623
 624         REG_WRITE(map->src, crtc_state->savePIPESRC);
 625         REG_WRITE(map->base, crtc_state->saveDSPBASE);
 626         REG_WRITE(map->conf, crtc_state->savePIPECONF);
 627
 628         gma_wait_for_vblank(dev);
 629
 630         REG_WRITE(map->cntr, crtc_state->saveDSPCNTR);
 631         REG_WRITE(map->base, crtc_state->saveDSPBASE);
 632
 633         gma_wait_for_vblank(dev);
 634
 635         palette_reg = map->palette;
 636         for (i = 0; i < 256; ++i)
 637                 REG_WRITE(palette_reg + (i << 2), crtc_state->savePalette[i]);
 638 }
 639
 640 void gma_encoder_prepare(struct drm_encoder *encoder)
 641 {
 642         const struct drm_encoder_helper_funcs *encoder_funcs =
 643             encoder->helper_private;
 644         /* lvds has its own version of prepare see psb_intel_lvds_prepare */
 645         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
 646 }
 647
 648 void gma_encoder_commit(struct drm_encoder *encoder)
 649 {
 650         const struct drm_encoder_helper_funcs *encoder_funcs =
 651             encoder->helper_private;
 652         /* lvds has its own version of commit see psb_intel_lvds_commit */
 653         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
 654 }
 655
 656 void gma_encoder_destroy(struct drm_encoder *encoder)
 657 {
 658         struct gma_encoder *intel_encoder = to_gma_encoder(encoder);
 659
 660         drm_encoder_cleanup(encoder);
 661         kfree(intel_encoder);
 662 }
 663
 664 /* Currently there is only a 1:1 mapping of encoders and connectors */
 665 struct drm_encoder *gma_best_encoder(struct drm_connector *connector)
 666 {
 667         struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
 668
 669         return &gma_encoder->base;
 670 }
 671
 672 void gma_connector_attach_encoder(struct gma_connector *connector,
 673                                   struct gma_encoder *encoder)
 674 {
 675         connector->encoder = encoder;
 676         drm_mode_connector_attach_encoder(&connector->base,
 677                                           &encoder->base);
 678 }
 679
 680 #define GMA_PLL_INVALID(s) { /* DRM_ERROR(s); */ return false; }
 681
 682 bool gma_pll_is_valid(struct drm_crtc *crtc,
 683                       const struct gma_limit_t *limit,
 684                       struct gma_clock_t *clock)
 685 {
 686         if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
 687                 GMA_PLL_INVALID("p1 out of range");
 688         if (clock->p < limit->p.min || limit->p.max < clock->p)
 689                 GMA_PLL_INVALID("p out of range");
 690         if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
 691                 GMA_PLL_INVALID("m2 out of range");
 692         if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
 693                 GMA_PLL_INVALID("m1 out of range");
 694         /* On CDV m1 is always 0 */
 695         if (clock->m1 <= clock->m2 && clock->m1 != 0)
 696                 GMA_PLL_INVALID("m1 <= m2 && m1 != 0");
 697         if (clock->m < limit->m.min || limit->m.max < clock->m)
 698                 GMA_PLL_INVALID("m out of range");
 699         if (clock->n < limit->n.min || limit->n.max < clock->n)
 700                 GMA_PLL_INVALID("n out of range");
 701         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 702                 GMA_PLL_INVALID("vco out of range");
 703         /* XXX: We may need to be checking "Dot clock"
 704          * depending on the multiplier, connector, etc.,
 705          * rather than just a single range.
 706          */
 707         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 708                 GMA_PLL_INVALID("dot out of range");
 709
 710         return true;
 711 }
 712
 713 bool gma_find_best_pll(const struct gma_limit_t *limit,
 714                        struct drm_crtc *crtc, int target, int refclk,
 715                        struct gma_clock_t *best_clock)
 716 {
 717         struct drm_device *dev = crtc->dev;
 718         const struct gma_clock_funcs *clock_funcs =
 719                                                 to_gma_crtc(crtc)->clock_funcs;
 720         struct gma_clock_t clock;
 721         int err = target;
 722
 723         if (gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 724             (REG_READ(LVDS) & LVDS_PORT_EN) != 0) {
 725                 /*
 726                  * For LVDS, if the panel is on, just rely on its current
 727                  * settings for dual-channel.  We haven't figured out how to
 728                  * reliably set up different single/dual channel state, if we
 729                  * even can.
 730                  */
 731                 if ((REG_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 732                     LVDS_CLKB_POWER_UP)
 733                         clock.p2 = limit->p2.p2_fast;
 734                 else
 735                         clock.p2 = limit->p2.p2_slow;
 736         } else {
 737                 if (target < limit->p2.dot_limit)
 738                         clock.p2 = limit->p2.p2_slow;
 739                 else
 740                         clock.p2 = limit->p2.p2_fast;
 741         }
 742
 743         memset(best_clock, 0, sizeof(*best_clock));
 744
 745         /* m1 is always 0 on CDV so the outmost loop will run just once */
 746         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
 747                 for (clock.m2 = limit->m2.min;
 748                      (clock.m2 < clock.m1 || clock.m1 == 0) &&
 749                       clock.m2 <= limit->m2.max; clock.m2++) {
 750                         for (clock.n = limit->n.min;
 751                              clock.n <= limit->n.max; clock.n++) {
 752                                 for (clock.p1 = limit->p1.min;
 753                                      clock.p1 <= limit->p1.max;
 754                                      clock.p1++) {
 755                                         int this_err;
 756
 757                                         clock_funcs->clock(refclk, &clock);
 758
 759                                         if (!clock_funcs->pll_is_valid(crtc,
 760                                                                 limit, &clock))
 761                                                 continue;
 762
 763                                         this_err = abs(clock.dot - target);
 764                                         if (this_err < err) {
 765                                                 *best_clock = clock;
 766                                                 err = this_err;
 767                                         }
 768                                 }
 769                         }
 770                 }
 771         }
 772
 773         return err != target;
 774 }