2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2008,2010 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
26 * Eric Anholt <eric@anholt.net>
27 * Chris Wilson <chris@chris-wilson.co.uk>
29 #include <linux/module.h>
30 #include <linux/i2c.h>
31 #include <linux/i2c-algo-bit.h>
34 #include "psb_intel_drv.h"
37 #include "psb_intel_reg.h"
39 #define _wait_for(COND, MS, W) ({ \
40 unsigned long timeout__ = jiffies + msecs_to_jiffies(MS); \
43 if (time_after(jiffies, timeout__)) { \
47 if (W && !(in_atomic() || in_dbg_master())) msleep(W); \
52 #define wait_for(COND, MS) _wait_for(COND, MS, 1)
53 #define wait_for_atomic(COND, MS) _wait_for(COND, MS, 0)
55 /* Intel GPIO access functions */
57 #define I2C_RISEFALL_TIME 20
59 static inline struct intel_gmbus *
60 to_intel_gmbus(struct i2c_adapter *i2c)
62 return container_of(i2c, struct intel_gmbus, adapter);
66 struct i2c_adapter adapter;
67 struct i2c_algo_bit_data algo;
68 struct drm_psb_private *dev_priv;
73 gma_intel_i2c_reset(struct drm_device *dev)
78 static void intel_i2c_quirk_set(struct drm_psb_private *dev_priv, bool enable)
80 /* When using bit bashing for I2C, this bit needs to be set to 1 */
81 /* FIXME: We are never Pineview, right?
85 if (!IS_PINEVIEW(dev_priv->dev))
88 val = REG_READ(DSPCLK_GATE_D);
90 val |= DPCUNIT_CLOCK_GATE_DISABLE;
92 val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
93 REG_WRITE(DSPCLK_GATE_D, val);
99 static u32 get_reserved(struct intel_gpio *gpio)
101 struct drm_psb_private *dev_priv = gpio->dev_priv;
102 struct drm_device *dev = dev_priv->dev;
105 /* On most chips, these bits must be preserved in software. */
106 reserved = REG_READ(gpio->reg) &
107 (GPIO_DATA_PULLUP_DISABLE |
108 GPIO_CLOCK_PULLUP_DISABLE);
113 static int get_clock(void *data)
115 struct intel_gpio *gpio = data;
116 struct drm_psb_private *dev_priv = gpio->dev_priv;
117 struct drm_device *dev = dev_priv->dev;
118 u32 reserved = get_reserved(gpio);
119 REG_WRITE(gpio->reg, reserved | GPIO_CLOCK_DIR_MASK);
120 REG_WRITE(gpio->reg, reserved);
121 return (REG_READ(gpio->reg) & GPIO_CLOCK_VAL_IN) != 0;
124 static int get_data(void *data)
126 struct intel_gpio *gpio = data;
127 struct drm_psb_private *dev_priv = gpio->dev_priv;
128 struct drm_device *dev = dev_priv->dev;
129 u32 reserved = get_reserved(gpio);
130 REG_WRITE(gpio->reg, reserved | GPIO_DATA_DIR_MASK);
131 REG_WRITE(gpio->reg, reserved);
132 return (REG_READ(gpio->reg) & GPIO_DATA_VAL_IN) != 0;
135 static void set_clock(void *data, int state_high)
137 struct intel_gpio *gpio = data;
138 struct drm_psb_private *dev_priv = gpio->dev_priv;
139 struct drm_device *dev = dev_priv->dev;
140 u32 reserved = get_reserved(gpio);
144 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
146 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
149 REG_WRITE(gpio->reg, reserved | clock_bits);
150 REG_READ(gpio->reg); /* Posting */
153 static void set_data(void *data, int state_high)
155 struct intel_gpio *gpio = data;
156 struct drm_psb_private *dev_priv = gpio->dev_priv;
157 struct drm_device *dev = dev_priv->dev;
158 u32 reserved = get_reserved(gpio);
162 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
164 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
167 REG_WRITE(gpio->reg, reserved | data_bits);
171 static struct i2c_adapter *
172 intel_gpio_create(struct drm_psb_private *dev_priv, u32 pin)
174 static const int map_pin_to_reg[] = {
184 struct intel_gpio *gpio;
186 if (pin >= ARRAY_SIZE(map_pin_to_reg) || !map_pin_to_reg[pin])
189 gpio = kzalloc(sizeof(struct intel_gpio), GFP_KERNEL);
193 gpio->reg = map_pin_to_reg[pin];
194 gpio->dev_priv = dev_priv;
196 snprintf(gpio->adapter.name, sizeof(gpio->adapter.name),
197 "gma500 GPIO%c", "?BACDE?F"[pin]);
198 gpio->adapter.owner = THIS_MODULE;
199 gpio->adapter.algo_data = &gpio->algo;
200 gpio->adapter.dev.parent = &dev_priv->dev->pdev->dev;
201 gpio->algo.setsda = set_data;
202 gpio->algo.setscl = set_clock;
203 gpio->algo.getsda = get_data;
204 gpio->algo.getscl = get_clock;
205 gpio->algo.udelay = I2C_RISEFALL_TIME;
206 gpio->algo.timeout = usecs_to_jiffies(2200);
207 gpio->algo.data = gpio;
209 if (i2c_bit_add_bus(&gpio->adapter))
212 return &gpio->adapter;
220 intel_i2c_quirk_xfer(struct drm_psb_private *dev_priv,
221 struct i2c_adapter *adapter,
222 struct i2c_msg *msgs,
225 struct intel_gpio *gpio = container_of(adapter,
230 gma_intel_i2c_reset(dev_priv->dev);
232 intel_i2c_quirk_set(dev_priv, true);
235 udelay(I2C_RISEFALL_TIME);
237 ret = adapter->algo->master_xfer(adapter, msgs, num);
241 intel_i2c_quirk_set(dev_priv, false);
247 gmbus_xfer(struct i2c_adapter *adapter,
248 struct i2c_msg *msgs,
251 struct intel_gmbus *bus = container_of(adapter,
254 struct drm_psb_private *dev_priv = adapter->algo_data;
255 struct drm_device *dev = dev_priv->dev;
259 return intel_i2c_quirk_xfer(dev_priv,
260 bus->force_bit, msgs, num);
264 REG_WRITE(GMBUS0 + reg_offset, bus->reg0);
266 for (i = 0; i < num; i++) {
267 u16 len = msgs[i].len;
268 u8 *buf = msgs[i].buf;
270 if (msgs[i].flags & I2C_M_RD) {
271 REG_WRITE(GMBUS1 + reg_offset,
272 GMBUS_CYCLE_WAIT | (i + 1 == num ? GMBUS_CYCLE_STOP : 0) |
273 (len << GMBUS_BYTE_COUNT_SHIFT) |
274 (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
275 GMBUS_SLAVE_READ | GMBUS_SW_RDY);
276 REG_READ(GMBUS2+reg_offset);
280 if (wait_for(REG_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50))
282 if (REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
285 val = REG_READ(GMBUS3 + reg_offset);
289 } while (--len && ++loop < 4);
296 val |= *buf++ << (8 * loop);
297 } while (--len && ++loop < 4);
299 REG_WRITE(GMBUS3 + reg_offset, val);
300 REG_WRITE(GMBUS1 + reg_offset,
301 (i + 1 == num ? GMBUS_CYCLE_STOP : GMBUS_CYCLE_WAIT) |
302 (msgs[i].len << GMBUS_BYTE_COUNT_SHIFT) |
303 (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
304 GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
305 REG_READ(GMBUS2+reg_offset);
308 if (wait_for(REG_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50))
310 if (REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
315 val |= *buf++ << (8 * loop);
316 } while (--len && ++loop < 4);
318 REG_WRITE(GMBUS3 + reg_offset, val);
319 REG_READ(GMBUS2+reg_offset);
323 if (i + 1 < num && wait_for(REG_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE), 50))
325 if (REG_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
332 /* Toggle the Software Clear Interrupt bit. This has the effect
333 * of resetting the GMBUS controller and so clearing the
334 * BUS_ERROR raised by the slave's NAK.
336 REG_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
337 REG_WRITE(GMBUS1 + reg_offset, 0);
340 /* Mark the GMBUS interface as disabled. We will re-enable it at the
341 * start of the next xfer, till then let it sleep.
343 REG_WRITE(GMBUS0 + reg_offset, 0);
347 DRM_INFO("GMBUS timed out, falling back to bit banging on pin %d [%s]\n",
348 bus->reg0 & 0xff, bus->adapter.name);
349 REG_WRITE(GMBUS0 + reg_offset, 0);
351 /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
352 bus->force_bit = intel_gpio_create(dev_priv, bus->reg0 & 0xff);
356 return intel_i2c_quirk_xfer(dev_priv, bus->force_bit, msgs, num);
359 static u32 gmbus_func(struct i2c_adapter *adapter)
361 struct intel_gmbus *bus = container_of(adapter,
366 bus->force_bit->algo->functionality(bus->force_bit);
368 return (I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
369 /* I2C_FUNC_10BIT_ADDR | */
370 I2C_FUNC_SMBUS_READ_BLOCK_DATA |
371 I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
374 static const struct i2c_algorithm gmbus_algorithm = {
375 .master_xfer = gmbus_xfer,
376 .functionality = gmbus_func
380 * intel_gmbus_setup - instantiate all Intel i2c GMBuses
383 int gma_intel_setup_gmbus(struct drm_device *dev)
385 static const char *names[GMBUS_NUM_PORTS] = {
395 struct drm_psb_private *dev_priv = dev->dev_private;
398 dev_priv->gmbus = kcalloc(GMBUS_NUM_PORTS, sizeof(struct intel_gmbus),
400 if (dev_priv->gmbus == NULL)
403 for (i = 0; i < GMBUS_NUM_PORTS; i++) {
404 struct intel_gmbus *bus = &dev_priv->gmbus[i];
406 bus->adapter.owner = THIS_MODULE;
407 bus->adapter.class = I2C_CLASS_DDC;
408 snprintf(bus->adapter.name,
409 sizeof(bus->adapter.name),
413 bus->adapter.dev.parent = &dev->pdev->dev;
414 bus->adapter.algo_data = dev_priv;
416 bus->adapter.algo = &gmbus_algorithm;
417 ret = i2c_add_adapter(&bus->adapter);
421 /* By default use a conservative clock rate */
422 bus->reg0 = i | GMBUS_RATE_100KHZ;
424 /* XXX force bit banging until GMBUS is fully debugged */
425 bus->force_bit = intel_gpio_create(dev_priv, i);
428 gma_intel_i2c_reset(dev_priv->dev);
434 struct intel_gmbus *bus = &dev_priv->gmbus[i];
435 i2c_del_adapter(&bus->adapter);
437 kfree(dev_priv->gmbus);
438 dev_priv->gmbus = NULL;
442 void gma_intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
444 struct intel_gmbus *bus = to_intel_gmbus(adapter);
452 bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | (speed << 8);
455 void gma_intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
457 struct intel_gmbus *bus = to_intel_gmbus(adapter);
460 if (bus->force_bit == NULL) {
461 struct drm_psb_private *dev_priv = adapter->algo_data;
462 bus->force_bit = intel_gpio_create(dev_priv,
466 if (bus->force_bit) {
467 i2c_del_adapter(bus->force_bit);
468 kfree(bus->force_bit);
469 bus->force_bit = NULL;
474 void gma_intel_teardown_gmbus(struct drm_device *dev)
476 struct drm_psb_private *dev_priv = dev->dev_private;
479 if (dev_priv->gmbus == NULL)
482 for (i = 0; i < GMBUS_NUM_PORTS; i++) {
483 struct intel_gmbus *bus = &dev_priv->gmbus[i];
484 if (bus->force_bit) {
485 i2c_del_adapter(bus->force_bit);
486 kfree(bus->force_bit);
488 i2c_del_adapter(&bus->adapter);
491 kfree(dev_priv->gmbus);
492 dev_priv->gmbus = NULL;