1 /**************************************************************************
2 * Copyright (c) 2011, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 **************************************************************************/
21 * - Split functions by vbt type
22 * - Make them all take drm_device
23 * - Check ioremap failures
28 #include <drm/gma_drm.h>
32 static void mid_get_fuse_settings(struct drm_device *dev)
34 struct drm_psb_private *dev_priv = dev->dev_private;
35 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
36 uint32_t fuse_value = 0;
37 uint32_t fuse_value_tmp = 0;
39 #define FB_REG06 0xD0810600
40 #define FB_MIPI_DISABLE (1 << 11)
41 #define FB_REG09 0xD0810900
42 #define FB_REG09 0xD0810900
43 #define FB_SKU_MASK 0x7000
44 #define FB_SKU_SHIFT 12
48 if (pci_root == NULL) {
54 pci_write_config_dword(pci_root, 0xD0, FB_REG06);
55 pci_read_config_dword(pci_root, 0xD4, &fuse_value);
57 /* FB_MIPI_DISABLE doesn't mean LVDS on with Medfield */
59 dev_priv->iLVDS_enable = fuse_value & FB_MIPI_DISABLE;
61 DRM_INFO("internal display is %s\n",
62 dev_priv->iLVDS_enable ? "LVDS display" : "MIPI display");
64 /* Prevent runtime suspend at start*/
65 if (dev_priv->iLVDS_enable) {
66 dev_priv->is_lvds_on = true;
67 dev_priv->is_mipi_on = false;
69 dev_priv->is_mipi_on = true;
70 dev_priv->is_lvds_on = false;
73 dev_priv->video_device_fuse = fuse_value;
75 pci_write_config_dword(pci_root, 0xD0, FB_REG09);
76 pci_read_config_dword(pci_root, 0xD4, &fuse_value);
78 dev_dbg(dev->dev, "SKU values is 0x%x.\n", fuse_value);
79 fuse_value_tmp = (fuse_value & FB_SKU_MASK) >> FB_SKU_SHIFT;
81 dev_priv->fuse_reg_value = fuse_value;
83 switch (fuse_value_tmp) {
85 dev_priv->core_freq = 200;
88 dev_priv->core_freq = 100;
91 dev_priv->core_freq = 166;
94 dev_warn(dev->dev, "Invalid SKU values, SKU value = 0x%08x\n",
96 dev_priv->core_freq = 0;
98 dev_dbg(dev->dev, "LNC core clk is %dMHz.\n", dev_priv->core_freq);
99 pci_dev_put(pci_root);
103 * Get the revison ID, B0:D2:F0;0x08
105 static void mid_get_pci_revID(struct drm_psb_private *dev_priv)
107 uint32_t platform_rev_id = 0;
108 struct pci_dev *pci_gfx_root = pci_get_bus_and_slot(0, PCI_DEVFN(2, 0));
110 if (pci_gfx_root == NULL) {
114 pci_read_config_dword(pci_gfx_root, 0x08, &platform_rev_id);
115 dev_priv->platform_rev_id = (uint8_t) platform_rev_id;
116 pci_dev_put(pci_gfx_root);
117 dev_dbg(dev_priv->dev->dev, "platform_rev_id is %x\n",
118 dev_priv->platform_rev_id);
121 struct mid_vbt_header {
126 /* The same for r0 and r1 */
128 struct mid_vbt_header vbt_header;
134 struct mid_vbt_header vbt_header;
138 u8 primary_panel_idx;
139 u8 secondary_panel_idx;
143 static int read_vbt_r0(u32 addr, struct vbt_r0 *vbt)
145 void __iomem *vbt_virtual;
147 vbt_virtual = ioremap(addr, sizeof(*vbt));
148 if (vbt_virtual == NULL)
151 memcpy_fromio(vbt, vbt_virtual, sizeof(*vbt));
152 iounmap(vbt_virtual);
157 static int read_vbt_r10(u32 addr, struct vbt_r10 *vbt)
159 void __iomem *vbt_virtual;
161 vbt_virtual = ioremap(addr, sizeof(*vbt));
165 memcpy_fromio(vbt, vbt_virtual, sizeof(*vbt));
166 iounmap(vbt_virtual);
171 static int mid_get_vbt_data_r0(struct drm_psb_private *dev_priv, u32 addr)
174 void __iomem *gct_virtual;
178 if (read_vbt_r0(addr, &vbt))
181 gct_virtual = ioremap(addr + sizeof(vbt), vbt.size - sizeof(vbt));
184 memcpy_fromio(&gct, gct_virtual, sizeof(gct));
185 iounmap(gct_virtual);
187 bpi = gct.PD.BootPanelIndex;
188 dev_priv->gct_data.bpi = bpi;
189 dev_priv->gct_data.pt = gct.PD.PanelType;
190 dev_priv->gct_data.DTD = gct.panel[bpi].DTD;
191 dev_priv->gct_data.Panel_Port_Control =
192 gct.panel[bpi].Panel_Port_Control;
193 dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
194 gct.panel[bpi].Panel_MIPI_Display_Descriptor;
199 static int mid_get_vbt_data_r1(struct drm_psb_private *dev_priv, u32 addr)
202 void __iomem *gct_virtual;
206 if (read_vbt_r0(addr, &vbt))
209 gct_virtual = ioremap(addr + sizeof(vbt), vbt.size - sizeof(vbt));
212 memcpy_fromio(&gct, gct_virtual, sizeof(gct));
213 iounmap(gct_virtual);
215 bpi = gct.PD.BootPanelIndex;
216 dev_priv->gct_data.bpi = bpi;
217 dev_priv->gct_data.pt = gct.PD.PanelType;
218 dev_priv->gct_data.DTD = gct.panel[bpi].DTD;
219 dev_priv->gct_data.Panel_Port_Control =
220 gct.panel[bpi].Panel_Port_Control;
221 dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
222 gct.panel[bpi].Panel_MIPI_Display_Descriptor;
227 static int mid_get_vbt_data_r10(struct drm_psb_private *dev_priv, u32 addr)
230 void __iomem *gct_virtual;
232 struct oaktrail_timing_info *dp_ti = &dev_priv->gct_data.DTD;
233 struct gct_r10_timing_info *ti;
236 if (read_vbt_r10(addr, &vbt))
239 gct = kmalloc(sizeof(*gct) * vbt.panel_count, GFP_KERNEL);
243 gct_virtual = ioremap(addr + sizeof(vbt),
244 sizeof(*gct) * vbt.panel_count);
247 memcpy_fromio(gct, gct_virtual, sizeof(*gct));
248 iounmap(gct_virtual);
250 dev_priv->gct_data.bpi = vbt.primary_panel_idx;
251 dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
252 gct[vbt.primary_panel_idx].Panel_MIPI_Display_Descriptor;
254 ti = &gct[vbt.primary_panel_idx].DTD;
255 dp_ti->pixel_clock = ti->pixel_clock;
256 dp_ti->hactive_hi = ti->hactive_hi;
257 dp_ti->hactive_lo = ti->hactive_lo;
258 dp_ti->hblank_hi = ti->hblank_hi;
259 dp_ti->hblank_lo = ti->hblank_lo;
260 dp_ti->hsync_offset_hi = ti->hsync_offset_hi;
261 dp_ti->hsync_offset_lo = ti->hsync_offset_lo;
262 dp_ti->hsync_pulse_width_hi = ti->hsync_pulse_width_hi;
263 dp_ti->hsync_pulse_width_lo = ti->hsync_pulse_width_lo;
264 dp_ti->vactive_hi = ti->vactive_hi;
265 dp_ti->vactive_lo = ti->vactive_lo;
266 dp_ti->vblank_hi = ti->vblank_hi;
267 dp_ti->vblank_lo = ti->vblank_lo;
268 dp_ti->vsync_offset_hi = ti->vsync_offset_hi;
269 dp_ti->vsync_offset_lo = ti->vsync_offset_lo;
270 dp_ti->vsync_pulse_width_hi = ti->vsync_pulse_width_hi;
271 dp_ti->vsync_pulse_width_lo = ti->vsync_pulse_width_lo;
279 static void mid_get_vbt_data(struct drm_psb_private *dev_priv)
281 struct drm_device *dev = dev_priv->dev;
283 u8 __iomem *vbt_virtual;
284 struct mid_vbt_header vbt_header;
285 struct pci_dev *pci_gfx_root = pci_get_bus_and_slot(0, PCI_DEVFN(2, 0));
288 /* Get the address of the platform config vbt */
289 pci_read_config_dword(pci_gfx_root, 0xFC, &addr);
290 pci_dev_put(pci_gfx_root);
292 dev_dbg(dev->dev, "drm platform config address is %x\n", addr);
297 /* get the virtual address of the vbt */
298 vbt_virtual = ioremap(addr, sizeof(vbt_header));
302 memcpy_fromio(&vbt_header, vbt_virtual, sizeof(vbt_header));
303 iounmap(vbt_virtual);
305 if (memcmp(&vbt_header.signature, "$GCT", 4))
308 dev_dbg(dev->dev, "GCT revision is %02x\n", vbt_header.revision);
310 switch (vbt_header.revision) {
312 ret = mid_get_vbt_data_r0(dev_priv, addr);
315 ret = mid_get_vbt_data_r1(dev_priv, addr);
318 ret = mid_get_vbt_data_r10(dev_priv, addr);
321 dev_err(dev->dev, "Unknown revision of GCT!\n");
326 dev_err(dev->dev, "Unable to read GCT!");
328 dev_priv->has_gct = true;
331 int mid_chip_setup(struct drm_device *dev)
333 struct drm_psb_private *dev_priv = dev->dev_private;
334 mid_get_fuse_settings(dev);
335 mid_get_vbt_data(dev_priv);
336 mid_get_pci_revID(dev_priv);