2 * Copyright © 2009 Intel Corporation
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc.,
15 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 #include <linux/i2c.h>
19 #include <linux/pm_runtime.h>
22 #include "framebuffer.h"
24 #include "psb_intel_drv.h"
25 #include "psb_intel_reg.h"
26 #include "gma_display.h"
29 struct psb_intel_range_t {
33 struct oaktrail_limit_t {
34 struct psb_intel_range_t dot, m, p1;
37 struct oaktrail_clock_t {
44 #define MRST_LIMIT_LVDS_100L 0
45 #define MRST_LIMIT_LVDS_83 1
46 #define MRST_LIMIT_LVDS_100 2
48 #define MRST_DOT_MIN 19750
49 #define MRST_DOT_MAX 120000
50 #define MRST_M_MIN_100L 20
51 #define MRST_M_MIN_100 10
52 #define MRST_M_MIN_83 12
53 #define MRST_M_MAX_100L 34
54 #define MRST_M_MAX_100 17
55 #define MRST_M_MAX_83 20
57 #define MRST_P1_MAX_0 7
58 #define MRST_P1_MAX_1 8
60 static const struct oaktrail_limit_t oaktrail_limits[] = {
61 { /* MRST_LIMIT_LVDS_100L */
62 .dot = {.min = MRST_DOT_MIN, .max = MRST_DOT_MAX},
63 .m = {.min = MRST_M_MIN_100L, .max = MRST_M_MAX_100L},
64 .p1 = {.min = MRST_P1_MIN, .max = MRST_P1_MAX_1},
66 { /* MRST_LIMIT_LVDS_83L */
67 .dot = {.min = MRST_DOT_MIN, .max = MRST_DOT_MAX},
68 .m = {.min = MRST_M_MIN_83, .max = MRST_M_MAX_83},
69 .p1 = {.min = MRST_P1_MIN, .max = MRST_P1_MAX_0},
71 { /* MRST_LIMIT_LVDS_100 */
72 .dot = {.min = MRST_DOT_MIN, .max = MRST_DOT_MAX},
73 .m = {.min = MRST_M_MIN_100, .max = MRST_M_MAX_100},
74 .p1 = {.min = MRST_P1_MIN, .max = MRST_P1_MAX_1},
79 static const u32 oaktrail_m_converts[] = {
80 0x2B, 0x15, 0x2A, 0x35, 0x1A, 0x0D, 0x26, 0x33, 0x19, 0x2C,
81 0x36, 0x3B, 0x1D, 0x2E, 0x37, 0x1B, 0x2D, 0x16, 0x0B, 0x25,
82 0x12, 0x09, 0x24, 0x32, 0x39, 0x1c,
85 static const struct oaktrail_limit_t *oaktrail_limit(struct drm_crtc *crtc)
87 const struct oaktrail_limit_t *limit = NULL;
88 struct drm_device *dev = crtc->dev;
89 struct drm_psb_private *dev_priv = dev->dev_private;
91 if (gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
92 || gma_pipe_has_type(crtc, INTEL_OUTPUT_MIPI)) {
93 switch (dev_priv->core_freq) {
95 limit = &oaktrail_limits[MRST_LIMIT_LVDS_100L];
98 limit = &oaktrail_limits[MRST_LIMIT_LVDS_83];
101 limit = &oaktrail_limits[MRST_LIMIT_LVDS_100];
106 dev_err(dev->dev, "oaktrail_limit Wrong display type.\n");
112 /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
113 static void oaktrail_clock(int refclk, struct oaktrail_clock_t *clock)
115 clock->dot = (refclk * clock->m) / (14 * clock->p1);
118 static void mrstPrintPll(char *prefix, struct oaktrail_clock_t *clock)
120 pr_debug("%s: dotclock = %d, m = %d, p1 = %d.\n",
121 prefix, clock->dot, clock->m, clock->p1);
125 * Returns a set of divisors for the desired target clock with the given refclk,
126 * or FALSE. Divisor values are the actual divisors for
129 mrstFindBestPLL(struct drm_crtc *crtc, int target, int refclk,
130 struct oaktrail_clock_t *best_clock)
132 struct oaktrail_clock_t clock;
133 const struct oaktrail_limit_t *limit = oaktrail_limit(crtc);
136 memset(best_clock, 0, sizeof(*best_clock));
138 for (clock.m = limit->m.min; clock.m <= limit->m.max; clock.m++) {
139 for (clock.p1 = limit->p1.min; clock.p1 <= limit->p1.max;
143 oaktrail_clock(refclk, &clock);
145 this_err = abs(clock.dot - target);
146 if (this_err < err) {
152 dev_dbg(crtc->dev->dev, "mrstFindBestPLL err = %d.\n", err);
153 return err != target;
157 * Sets the power management mode of the pipe and plane.
159 * This code should probably grow support for turning the cursor off and back
160 * on appropriately at the same time as we're turning the pipe off/on.
162 static void oaktrail_crtc_dpms(struct drm_crtc *crtc, int mode)
164 struct drm_device *dev = crtc->dev;
165 struct drm_psb_private *dev_priv = dev->dev_private;
166 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
167 int pipe = gma_crtc->pipe;
168 const struct psb_offset *map = &dev_priv->regmap[pipe];
172 oaktrail_crtc_hdmi_dpms(crtc, mode);
176 if (!gma_power_begin(dev, true))
179 /* XXX: When our outputs are all unaware of DPMS modes other than off
180 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
183 case DRM_MODE_DPMS_ON:
184 case DRM_MODE_DPMS_STANDBY:
185 case DRM_MODE_DPMS_SUSPEND:
186 /* Enable the DPLL */
187 temp = REG_READ(map->dpll);
188 if ((temp & DPLL_VCO_ENABLE) == 0) {
189 REG_WRITE(map->dpll, temp);
191 /* Wait for the clocks to stabilize. */
193 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);
195 /* Wait for the clocks to stabilize. */
197 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);
199 /* Wait for the clocks to stabilize. */
202 /* Enable the pipe */
203 temp = REG_READ(map->conf);
204 if ((temp & PIPEACONF_ENABLE) == 0)
205 REG_WRITE(map->conf, temp | PIPEACONF_ENABLE);
206 /* Enable the plane */
207 temp = REG_READ(map->cntr);
208 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
210 temp | DISPLAY_PLANE_ENABLE);
211 /* Flush the plane changes */
212 REG_WRITE(map->base, REG_READ(map->base));
215 gma_crtc_load_lut(crtc);
217 /* Give the overlay scaler a chance to enable
218 if it's on this pipe */
219 /* psb_intel_crtc_dpms_video(crtc, true); TODO */
221 case DRM_MODE_DPMS_OFF:
222 /* Give the overlay scaler a chance to disable
223 * if it's on this pipe */
224 /* psb_intel_crtc_dpms_video(crtc, FALSE); TODO */
226 /* Disable the VGA plane that we never use */
227 REG_WRITE(VGACNTRL, VGA_DISP_DISABLE);
228 /* Disable display plane */
229 temp = REG_READ(map->cntr);
230 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
232 temp & ~DISPLAY_PLANE_ENABLE);
233 /* Flush the plane changes */
234 REG_WRITE(map->base, REG_READ(map->base));
238 /* Next, disable display pipes */
239 temp = REG_READ(map->conf);
240 if ((temp & PIPEACONF_ENABLE) != 0) {
241 REG_WRITE(map->conf, temp & ~PIPEACONF_ENABLE);
244 /* Wait for for the pipe disable to take effect. */
245 gma_wait_for_vblank(dev);
247 temp = REG_READ(map->dpll);
248 if ((temp & DPLL_VCO_ENABLE) != 0) {
249 REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE);
253 /* Wait for the clocks to turn off. */
258 /*Set FIFO Watermarks*/
259 REG_WRITE(DSPARB, 0x3FFF);
260 REG_WRITE(DSPFW1, 0x3F88080A);
261 REG_WRITE(DSPFW2, 0x0b060808);
262 REG_WRITE(DSPFW3, 0x0);
263 REG_WRITE(DSPFW4, 0x08030404);
264 REG_WRITE(DSPFW5, 0x04040404);
265 REG_WRITE(DSPFW6, 0x78);
266 REG_WRITE(0x70400, REG_READ(0x70400) | 0x4000);
267 /* Must write Bit 14 of the Chicken Bit Register */
273 * Return the pipe currently connected to the panel fitter,
274 * or -1 if the panel fitter is not present or not in use
276 static int oaktrail_panel_fitter_pipe(struct drm_device *dev)
280 pfit_control = REG_READ(PFIT_CONTROL);
282 /* See if the panel fitter is in use */
283 if ((pfit_control & PFIT_ENABLE) == 0)
285 return (pfit_control >> 29) & 3;
288 static int oaktrail_crtc_mode_set(struct drm_crtc *crtc,
289 struct drm_display_mode *mode,
290 struct drm_display_mode *adjusted_mode,
292 struct drm_framebuffer *old_fb)
294 struct drm_device *dev = crtc->dev;
295 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
296 struct drm_psb_private *dev_priv = dev->dev_private;
297 int pipe = gma_crtc->pipe;
298 const struct psb_offset *map = &dev_priv->regmap[pipe];
300 struct oaktrail_clock_t clock;
301 u32 dpll = 0, fp = 0, dspcntr, pipeconf;
302 bool ok, is_sdvo = false;
303 bool is_lvds = false;
304 bool is_mipi = false;
305 struct drm_mode_config *mode_config = &dev->mode_config;
306 struct gma_encoder *gma_encoder = NULL;
307 uint64_t scalingType = DRM_MODE_SCALE_FULLSCREEN;
308 struct drm_connector *connector;
311 return oaktrail_crtc_hdmi_mode_set(crtc, mode, adjusted_mode, x, y, old_fb);
313 if (!gma_power_begin(dev, true))
316 memcpy(&gma_crtc->saved_mode,
318 sizeof(struct drm_display_mode));
319 memcpy(&gma_crtc->saved_adjusted_mode,
321 sizeof(struct drm_display_mode));
323 list_for_each_entry(connector, &mode_config->connector_list, head) {
324 if (!connector->encoder || connector->encoder->crtc != crtc)
327 gma_encoder = gma_attached_encoder(connector);
329 switch (gma_encoder->type) {
330 case INTEL_OUTPUT_LVDS:
333 case INTEL_OUTPUT_SDVO:
336 case INTEL_OUTPUT_MIPI:
342 /* Disable the VGA plane that we never use */
343 REG_WRITE(VGACNTRL, VGA_DISP_DISABLE);
345 /* Disable the panel fitter if it was on our pipe */
346 if (oaktrail_panel_fitter_pipe(dev) == pipe)
347 REG_WRITE(PFIT_CONTROL, 0);
350 ((mode->crtc_hdisplay - 1) << 16) |
351 (mode->crtc_vdisplay - 1));
354 drm_object_property_get_value(&connector->base,
355 dev->mode_config.scaling_mode_property, &scalingType);
357 if (scalingType == DRM_MODE_SCALE_NO_SCALE) {
358 /* Moorestown doesn't have register support for centering so
359 * we need to mess with the h/vblank and h/vsync start and
360 * ends to get centering */
361 int offsetX = 0, offsetY = 0;
363 offsetX = (adjusted_mode->crtc_hdisplay -
364 mode->crtc_hdisplay) / 2;
365 offsetY = (adjusted_mode->crtc_vdisplay -
366 mode->crtc_vdisplay) / 2;
368 REG_WRITE(map->htotal, (mode->crtc_hdisplay - 1) |
369 ((adjusted_mode->crtc_htotal - 1) << 16));
370 REG_WRITE(map->vtotal, (mode->crtc_vdisplay - 1) |
371 ((adjusted_mode->crtc_vtotal - 1) << 16));
372 REG_WRITE(map->hblank,
373 (adjusted_mode->crtc_hblank_start - offsetX - 1) |
374 ((adjusted_mode->crtc_hblank_end - offsetX - 1) << 16));
375 REG_WRITE(map->hsync,
376 (adjusted_mode->crtc_hsync_start - offsetX - 1) |
377 ((adjusted_mode->crtc_hsync_end - offsetX - 1) << 16));
378 REG_WRITE(map->vblank,
379 (adjusted_mode->crtc_vblank_start - offsetY - 1) |
380 ((adjusted_mode->crtc_vblank_end - offsetY - 1) << 16));
381 REG_WRITE(map->vsync,
382 (adjusted_mode->crtc_vsync_start - offsetY - 1) |
383 ((adjusted_mode->crtc_vsync_end - offsetY - 1) << 16));
385 REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) |
386 ((adjusted_mode->crtc_htotal - 1) << 16));
387 REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) |
388 ((adjusted_mode->crtc_vtotal - 1) << 16));
389 REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) |
390 ((adjusted_mode->crtc_hblank_end - 1) << 16));
391 REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) |
392 ((adjusted_mode->crtc_hsync_end - 1) << 16));
393 REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) |
394 ((adjusted_mode->crtc_vblank_end - 1) << 16));
395 REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) |
396 ((adjusted_mode->crtc_vsync_end - 1) << 16));
399 /* Flush the plane changes */
401 struct drm_crtc_helper_funcs *crtc_funcs =
402 crtc->helper_private;
403 crtc_funcs->mode_set_base(crtc, x, y, old_fb);
407 pipeconf = REG_READ(map->conf);
409 /* Set up the display plane register */
410 dspcntr = REG_READ(map->cntr);
411 dspcntr |= DISPPLANE_GAMMA_ENABLE;
414 dspcntr |= DISPPLANE_SEL_PIPE_A;
416 dspcntr |= DISPPLANE_SEL_PIPE_B;
419 goto oaktrail_crtc_mode_set_exit;
421 refclk = dev_priv->core_freq * 1000;
423 dpll = 0; /*BIT16 = 0 for 100MHz reference */
425 ok = mrstFindBestPLL(crtc, adjusted_mode->clock, refclk, &clock);
428 dev_dbg(dev->dev, "mrstFindBestPLL fail in oaktrail_crtc_mode_set.\n");
430 dev_dbg(dev->dev, "oaktrail_crtc_mode_set pixel clock = %d,"
431 "m = %x, p1 = %x.\n", clock.dot, clock.m,
435 fp = oaktrail_m_converts[(clock.m - MRST_M_MIN)] << 8;
437 dpll |= DPLL_VGA_MODE_DIS;
440 dpll |= DPLL_VCO_ENABLE;
443 dpll |= DPLLA_MODE_LVDS;
445 dpll |= DPLLB_MODE_DAC_SERIAL;
448 int sdvo_pixel_multiply =
449 adjusted_mode->clock / mode->clock;
451 dpll |= DPLL_DVO_HIGH_SPEED;
453 (sdvo_pixel_multiply -
454 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
458 /* compute bitmask from p1 value */
459 dpll |= (1 << (clock.p1 - 2)) << 17;
461 dpll |= DPLL_VCO_ENABLE;
463 mrstPrintPll("chosen", &clock);
465 if (dpll & DPLL_VCO_ENABLE) {
466 REG_WRITE(map->fp0, fp);
467 REG_WRITE(map->dpll, dpll & ~DPLL_VCO_ENABLE);
469 /* Check the DPLLA lock bit PIPEACONF[29] */
473 REG_WRITE(map->fp0, fp);
474 REG_WRITE(map->dpll, dpll);
476 /* Wait for the clocks to stabilize. */
479 /* write it again -- the BIOS does, after all */
480 REG_WRITE(map->dpll, dpll);
482 /* Wait for the clocks to stabilize. */
485 REG_WRITE(map->conf, pipeconf);
487 gma_wait_for_vblank(dev);
489 REG_WRITE(map->cntr, dspcntr);
490 gma_wait_for_vblank(dev);
492 oaktrail_crtc_mode_set_exit:
497 static int oaktrail_pipe_set_base(struct drm_crtc *crtc,
498 int x, int y, struct drm_framebuffer *old_fb)
500 struct drm_device *dev = crtc->dev;
501 struct drm_psb_private *dev_priv = dev->dev_private;
502 struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
503 struct psb_framebuffer *psbfb = to_psb_fb(crtc->fb);
504 int pipe = gma_crtc->pipe;
505 const struct psb_offset *map = &dev_priv->regmap[pipe];
506 unsigned long start, offset;
513 dev_dbg(dev->dev, "No FB bound\n");
517 if (!gma_power_begin(dev, true))
520 start = psbfb->gtt->offset;
521 offset = y * crtc->fb->pitches[0] + x * (crtc->fb->bits_per_pixel / 8);
523 REG_WRITE(map->stride, crtc->fb->pitches[0]);
525 dspcntr = REG_READ(map->cntr);
526 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
528 switch (crtc->fb->bits_per_pixel) {
530 dspcntr |= DISPPLANE_8BPP;
533 if (crtc->fb->depth == 15)
534 dspcntr |= DISPPLANE_15_16BPP;
536 dspcntr |= DISPPLANE_16BPP;
540 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
543 dev_err(dev->dev, "Unknown color depth\n");
545 goto pipe_set_base_exit;
547 REG_WRITE(map->cntr, dspcntr);
549 REG_WRITE(map->base, offset);
551 REG_WRITE(map->surf, start);
559 const struct drm_crtc_helper_funcs oaktrail_helper_funcs = {
560 .dpms = oaktrail_crtc_dpms,
561 .mode_fixup = gma_crtc_mode_fixup,
562 .mode_set = oaktrail_crtc_mode_set,
563 .mode_set_base = oaktrail_pipe_set_base,
564 .prepare = gma_crtc_prepare,
565 .commit = gma_crtc_commit,