2 * Copyright © 2006-2011 Intel Corporation
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc.,
15 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 * Eric Anholt <eric@anholt.net>
21 #include <linux/i2c.h>
22 #include <linux/pm_runtime.h>
25 #include "framebuffer.h"
27 #include "psb_intel_drv.h"
28 #include "psb_intel_reg.h"
29 #include "psb_intel_display.h"
32 struct psb_intel_clock_t {
44 struct psb_intel_range_t {
48 struct psb_intel_p2_t {
53 #define INTEL_P2_NUM 2
55 struct psb_intel_limit_t {
56 struct psb_intel_range_t dot, vco, n, m, m1, m2, p, p1;
57 struct psb_intel_p2_t p2;
60 #define I8XX_DOT_MIN 25000
61 #define I8XX_DOT_MAX 350000
62 #define I8XX_VCO_MIN 930000
63 #define I8XX_VCO_MAX 1400000
67 #define I8XX_M_MAX 140
68 #define I8XX_M1_MIN 18
69 #define I8XX_M1_MAX 26
71 #define I8XX_M2_MAX 16
73 #define I8XX_P_MAX 128
75 #define I8XX_P1_MAX 33
76 #define I8XX_P1_LVDS_MIN 1
77 #define I8XX_P1_LVDS_MAX 6
78 #define I8XX_P2_SLOW 4
79 #define I8XX_P2_FAST 2
80 #define I8XX_P2_LVDS_SLOW 14
81 #define I8XX_P2_LVDS_FAST 14 /* No fast option */
82 #define I8XX_P2_SLOW_LIMIT 165000
84 #define I9XX_DOT_MIN 20000
85 #define I9XX_DOT_MAX 400000
86 #define I9XX_VCO_MIN 1400000
87 #define I9XX_VCO_MAX 2800000
91 #define I9XX_M_MAX 120
92 #define I9XX_M1_MIN 10
93 #define I9XX_M1_MAX 20
96 #define I9XX_P_SDVO_DAC_MIN 5
97 #define I9XX_P_SDVO_DAC_MAX 80
98 #define I9XX_P_LVDS_MIN 7
99 #define I9XX_P_LVDS_MAX 98
100 #define I9XX_P1_MIN 1
101 #define I9XX_P1_MAX 8
102 #define I9XX_P2_SDVO_DAC_SLOW 10
103 #define I9XX_P2_SDVO_DAC_FAST 5
104 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
105 #define I9XX_P2_LVDS_SLOW 14
106 #define I9XX_P2_LVDS_FAST 7
107 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
109 #define INTEL_LIMIT_I8XX_DVO_DAC 0
110 #define INTEL_LIMIT_I8XX_LVDS 1
111 #define INTEL_LIMIT_I9XX_SDVO_DAC 2
112 #define INTEL_LIMIT_I9XX_LVDS 3
114 static const struct psb_intel_limit_t psb_intel_limits[] = {
115 { /* INTEL_LIMIT_I8XX_DVO_DAC */
116 .dot = {.min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX},
117 .vco = {.min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX},
118 .n = {.min = I8XX_N_MIN, .max = I8XX_N_MAX},
119 .m = {.min = I8XX_M_MIN, .max = I8XX_M_MAX},
120 .m1 = {.min = I8XX_M1_MIN, .max = I8XX_M1_MAX},
121 .m2 = {.min = I8XX_M2_MIN, .max = I8XX_M2_MAX},
122 .p = {.min = I8XX_P_MIN, .max = I8XX_P_MAX},
123 .p1 = {.min = I8XX_P1_MIN, .max = I8XX_P1_MAX},
124 .p2 = {.dot_limit = I8XX_P2_SLOW_LIMIT,
125 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST},
127 { /* INTEL_LIMIT_I8XX_LVDS */
128 .dot = {.min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX},
129 .vco = {.min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX},
130 .n = {.min = I8XX_N_MIN, .max = I8XX_N_MAX},
131 .m = {.min = I8XX_M_MIN, .max = I8XX_M_MAX},
132 .m1 = {.min = I8XX_M1_MIN, .max = I8XX_M1_MAX},
133 .m2 = {.min = I8XX_M2_MIN, .max = I8XX_M2_MAX},
134 .p = {.min = I8XX_P_MIN, .max = I8XX_P_MAX},
135 .p1 = {.min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX},
136 .p2 = {.dot_limit = I8XX_P2_SLOW_LIMIT,
137 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST},
139 { /* INTEL_LIMIT_I9XX_SDVO_DAC */
140 .dot = {.min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
141 .vco = {.min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX},
142 .n = {.min = I9XX_N_MIN, .max = I9XX_N_MAX},
143 .m = {.min = I9XX_M_MIN, .max = I9XX_M_MAX},
144 .m1 = {.min = I9XX_M1_MIN, .max = I9XX_M1_MAX},
145 .m2 = {.min = I9XX_M2_MIN, .max = I9XX_M2_MAX},
146 .p = {.min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX},
147 .p1 = {.min = I9XX_P1_MIN, .max = I9XX_P1_MAX},
148 .p2 = {.dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
149 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast =
150 I9XX_P2_SDVO_DAC_FAST},
152 { /* INTEL_LIMIT_I9XX_LVDS */
153 .dot = {.min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
154 .vco = {.min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX},
155 .n = {.min = I9XX_N_MIN, .max = I9XX_N_MAX},
156 .m = {.min = I9XX_M_MIN, .max = I9XX_M_MAX},
157 .m1 = {.min = I9XX_M1_MIN, .max = I9XX_M1_MAX},
158 .m2 = {.min = I9XX_M2_MIN, .max = I9XX_M2_MAX},
159 .p = {.min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX},
160 .p1 = {.min = I9XX_P1_MIN, .max = I9XX_P1_MAX},
161 /* The single-channel range is 25-112Mhz, and dual-channel
162 * is 80-224Mhz. Prefer single channel as much as possible.
164 .p2 = {.dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
165 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST},
169 static const struct psb_intel_limit_t *psb_intel_limit(struct drm_crtc *crtc)
171 const struct psb_intel_limit_t *limit;
173 if (psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
174 limit = &psb_intel_limits[INTEL_LIMIT_I9XX_LVDS];
176 limit = &psb_intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC];
180 /** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
182 static void i8xx_clock(int refclk, struct psb_intel_clock_t *clock)
184 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
185 clock->p = clock->p1 * clock->p2;
186 clock->vco = refclk * clock->m / (clock->n + 2);
187 clock->dot = clock->vco / clock->p;
190 /** Derive the pixel clock for the given refclk and divisors for 9xx chips. */
192 static void i9xx_clock(int refclk, struct psb_intel_clock_t *clock)
194 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
195 clock->p = clock->p1 * clock->p2;
196 clock->vco = refclk * clock->m / (clock->n + 2);
197 clock->dot = clock->vco / clock->p;
200 static void psb_intel_clock(struct drm_device *dev, int refclk,
201 struct psb_intel_clock_t *clock)
203 return i9xx_clock(refclk, clock);
207 * Returns whether any output on the specified pipe is of the specified type
209 bool psb_intel_pipe_has_type(struct drm_crtc *crtc, int type)
211 struct drm_device *dev = crtc->dev;
212 struct drm_mode_config *mode_config = &dev->mode_config;
213 struct drm_connector *l_entry;
215 list_for_each_entry(l_entry, &mode_config->connector_list, head) {
216 if (l_entry->encoder && l_entry->encoder->crtc == crtc) {
217 struct psb_intel_encoder *psb_intel_encoder =
218 psb_intel_attached_encoder(l_entry);
219 if (psb_intel_encoder->type == type)
226 #define INTELPllInvalid(s) { /* ErrorF (s) */; return false; }
228 * Returns whether the given set of divisors are valid for a given refclk with
229 * the given connectors.
232 static bool psb_intel_PLL_is_valid(struct drm_crtc *crtc,
233 struct psb_intel_clock_t *clock)
235 const struct psb_intel_limit_t *limit = psb_intel_limit(crtc);
237 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
238 INTELPllInvalid("p1 out of range\n");
239 if (clock->p < limit->p.min || limit->p.max < clock->p)
240 INTELPllInvalid("p out of range\n");
241 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
242 INTELPllInvalid("m2 out of range\n");
243 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
244 INTELPllInvalid("m1 out of range\n");
245 if (clock->m1 <= clock->m2)
246 INTELPllInvalid("m1 <= m2\n");
247 if (clock->m < limit->m.min || limit->m.max < clock->m)
248 INTELPllInvalid("m out of range\n");
249 if (clock->n < limit->n.min || limit->n.max < clock->n)
250 INTELPllInvalid("n out of range\n");
251 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
252 INTELPllInvalid("vco out of range\n");
253 /* XXX: We may need to be checking "Dot clock"
254 * depending on the multiplier, connector, etc.,
255 * rather than just a single range.
257 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
258 INTELPllInvalid("dot out of range\n");
264 * Returns a set of divisors for the desired target clock with the given
265 * refclk, or FALSE. The returned values represent the clock equation:
266 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
268 static bool psb_intel_find_best_PLL(struct drm_crtc *crtc, int target,
270 struct psb_intel_clock_t *best_clock)
272 struct drm_device *dev = crtc->dev;
273 struct psb_intel_clock_t clock;
274 const struct psb_intel_limit_t *limit = psb_intel_limit(crtc);
277 if (psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
278 (REG_READ(LVDS) & LVDS_PORT_EN) != 0) {
280 * For LVDS, if the panel is on, just rely on its current
281 * settings for dual-channel. We haven't figured out how to
282 * reliably set up different single/dual channel state, if we
285 if ((REG_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
287 clock.p2 = limit->p2.p2_fast;
289 clock.p2 = limit->p2.p2_slow;
291 if (target < limit->p2.dot_limit)
292 clock.p2 = limit->p2.p2_slow;
294 clock.p2 = limit->p2.p2_fast;
297 memset(best_clock, 0, sizeof(*best_clock));
299 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
301 for (clock.m2 = limit->m2.min;
302 clock.m2 < clock.m1 && clock.m2 <= limit->m2.max;
304 for (clock.n = limit->n.min;
305 clock.n <= limit->n.max; clock.n++) {
306 for (clock.p1 = limit->p1.min;
307 clock.p1 <= limit->p1.max;
311 psb_intel_clock(dev, refclk, &clock);
313 if (!psb_intel_PLL_is_valid
317 this_err = abs(clock.dot - target);
318 if (this_err < err) {
327 return err != target;
330 void psb_intel_wait_for_vblank(struct drm_device *dev)
332 /* Wait for 20ms, i.e. one cycle at 50hz. */
336 int psb_intel_pipe_set_base(struct drm_crtc *crtc,
337 int x, int y, struct drm_framebuffer *old_fb)
339 struct drm_device *dev = crtc->dev;
340 /* struct drm_i915_master_private *master_priv; */
341 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
342 struct psb_framebuffer *psbfb = to_psb_fb(crtc->fb);
343 int pipe = psb_intel_crtc->pipe;
344 unsigned long start, offset;
345 int dspbase = (pipe == 0 ? DSPABASE : DSPBBASE);
346 int dspsurf = (pipe == 0 ? DSPASURF : DSPBSURF);
347 int dspstride = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE;
348 int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
352 if (!gma_power_begin(dev, true))
357 dev_dbg(dev->dev, "No FB bound\n");
358 goto psb_intel_pipe_cleaner;
361 /* We are displaying this buffer, make sure it is actually loaded
363 ret = psb_gtt_pin(psbfb->gtt);
365 goto psb_intel_pipe_set_base_exit;
366 start = psbfb->gtt->offset;
368 offset = y * crtc->fb->pitches[0] + x * (crtc->fb->bits_per_pixel / 8);
370 REG_WRITE(dspstride, crtc->fb->pitches[0]);
372 dspcntr = REG_READ(dspcntr_reg);
373 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
375 switch (crtc->fb->bits_per_pixel) {
377 dspcntr |= DISPPLANE_8BPP;
380 if (crtc->fb->depth == 15)
381 dspcntr |= DISPPLANE_15_16BPP;
383 dspcntr |= DISPPLANE_16BPP;
387 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
390 dev_err(dev->dev, "Unknown color depth\n");
392 psb_gtt_unpin(psbfb->gtt);
393 goto psb_intel_pipe_set_base_exit;
395 REG_WRITE(dspcntr_reg, dspcntr);
398 if (0 /* FIXMEAC - check what PSB needs */) {
399 REG_WRITE(dspbase, offset);
401 REG_WRITE(dspsurf, start);
404 REG_WRITE(dspbase, start + offset);
408 psb_intel_pipe_cleaner:
409 /* If there was a previous display we can now unpin it */
411 psb_gtt_unpin(to_psb_fb(old_fb)->gtt);
413 psb_intel_pipe_set_base_exit:
419 * Sets the power management mode of the pipe and plane.
421 * This code should probably grow support for turning the cursor off and back
422 * on appropriately at the same time as we're turning the pipe off/on.
424 static void psb_intel_crtc_dpms(struct drm_crtc *crtc, int mode)
426 struct drm_device *dev = crtc->dev;
427 /* struct drm_i915_master_private *master_priv; */
428 /* struct drm_i915_private *dev_priv = dev->dev_private; */
429 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
430 int pipe = psb_intel_crtc->pipe;
431 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
432 int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
433 int dspbase_reg = (pipe == 0) ? DSPABASE : DSPBBASE;
434 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
438 /* XXX: When our outputs are all unaware of DPMS modes other than off
439 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
442 case DRM_MODE_DPMS_ON:
443 case DRM_MODE_DPMS_STANDBY:
444 case DRM_MODE_DPMS_SUSPEND:
445 /* Enable the DPLL */
446 temp = REG_READ(dpll_reg);
447 if ((temp & DPLL_VCO_ENABLE) == 0) {
448 REG_WRITE(dpll_reg, temp);
450 /* Wait for the clocks to stabilize. */
452 REG_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
454 /* Wait for the clocks to stabilize. */
456 REG_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
458 /* Wait for the clocks to stabilize. */
462 /* Enable the pipe */
463 temp = REG_READ(pipeconf_reg);
464 if ((temp & PIPEACONF_ENABLE) == 0)
465 REG_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
467 /* Enable the plane */
468 temp = REG_READ(dspcntr_reg);
469 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
470 REG_WRITE(dspcntr_reg,
471 temp | DISPLAY_PLANE_ENABLE);
472 /* Flush the plane changes */
473 REG_WRITE(dspbase_reg, REG_READ(dspbase_reg));
476 psb_intel_crtc_load_lut(crtc);
478 /* Give the overlay scaler a chance to enable
479 * if it's on this pipe */
480 /* psb_intel_crtc_dpms_video(crtc, true); TODO */
482 case DRM_MODE_DPMS_OFF:
483 /* Give the overlay scaler a chance to disable
484 * if it's on this pipe */
485 /* psb_intel_crtc_dpms_video(crtc, FALSE); TODO */
487 /* Disable the VGA plane that we never use */
488 REG_WRITE(VGACNTRL, VGA_DISP_DISABLE);
490 /* Disable display plane */
491 temp = REG_READ(dspcntr_reg);
492 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
493 REG_WRITE(dspcntr_reg,
494 temp & ~DISPLAY_PLANE_ENABLE);
495 /* Flush the plane changes */
496 REG_WRITE(dspbase_reg, REG_READ(dspbase_reg));
497 REG_READ(dspbase_reg);
500 /* Next, disable display pipes */
501 temp = REG_READ(pipeconf_reg);
502 if ((temp & PIPEACONF_ENABLE) != 0) {
503 REG_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
504 REG_READ(pipeconf_reg);
507 /* Wait for vblank for the disable to take effect. */
508 psb_intel_wait_for_vblank(dev);
510 temp = REG_READ(dpll_reg);
511 if ((temp & DPLL_VCO_ENABLE) != 0) {
512 REG_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
516 /* Wait for the clocks to turn off. */
521 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
523 /*Set FIFO Watermarks*/
524 REG_WRITE(DSPARB, 0x3F3E);
527 static void psb_intel_crtc_prepare(struct drm_crtc *crtc)
529 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
530 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
533 static void psb_intel_crtc_commit(struct drm_crtc *crtc)
535 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
536 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
539 void psb_intel_encoder_prepare(struct drm_encoder *encoder)
541 struct drm_encoder_helper_funcs *encoder_funcs =
542 encoder->helper_private;
543 /* lvds has its own version of prepare see psb_intel_lvds_prepare */
544 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
547 void psb_intel_encoder_commit(struct drm_encoder *encoder)
549 struct drm_encoder_helper_funcs *encoder_funcs =
550 encoder->helper_private;
551 /* lvds has its own version of commit see psb_intel_lvds_commit */
552 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
555 void psb_intel_encoder_destroy(struct drm_encoder *encoder)
557 struct psb_intel_encoder *intel_encoder = to_psb_intel_encoder(encoder);
559 drm_encoder_cleanup(encoder);
560 kfree(intel_encoder);
563 static bool psb_intel_crtc_mode_fixup(struct drm_crtc *crtc,
564 struct drm_display_mode *mode,
565 struct drm_display_mode *adjusted_mode)
572 * Return the pipe currently connected to the panel fitter,
573 * or -1 if the panel fitter is not present or not in use
575 static int psb_intel_panel_fitter_pipe(struct drm_device *dev)
579 pfit_control = REG_READ(PFIT_CONTROL);
581 /* See if the panel fitter is in use */
582 if ((pfit_control & PFIT_ENABLE) == 0)
584 /* Must be on PIPE 1 for PSB */
588 static int psb_intel_crtc_mode_set(struct drm_crtc *crtc,
589 struct drm_display_mode *mode,
590 struct drm_display_mode *adjusted_mode,
592 struct drm_framebuffer *old_fb)
594 struct drm_device *dev = crtc->dev;
595 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
596 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
597 int pipe = psb_intel_crtc->pipe;
598 int fp_reg = (pipe == 0) ? FPA0 : FPB0;
599 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
600 int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
601 int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
602 int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
603 int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
604 int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
605 int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
606 int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
607 int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
608 int dspsize_reg = (pipe == 0) ? DSPASIZE : DSPBSIZE;
609 int dsppos_reg = (pipe == 0) ? DSPAPOS : DSPBPOS;
610 int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
612 struct psb_intel_clock_t clock;
613 u32 dpll = 0, fp = 0, dspcntr, pipeconf;
614 bool ok, is_sdvo = false, is_dvo = false;
615 bool is_crt = false, is_lvds = false, is_tv = false;
616 struct drm_mode_config *mode_config = &dev->mode_config;
617 struct drm_connector *connector;
619 /* No scan out no play */
620 if (crtc->fb == NULL) {
621 crtc_funcs->mode_set_base(crtc, x, y, old_fb);
625 list_for_each_entry(connector, &mode_config->connector_list, head) {
626 struct psb_intel_encoder *psb_intel_encoder =
627 psb_intel_attached_encoder(connector);
629 if (!connector->encoder
630 || connector->encoder->crtc != crtc)
633 switch (psb_intel_encoder->type) {
634 case INTEL_OUTPUT_LVDS:
637 case INTEL_OUTPUT_SDVO:
640 case INTEL_OUTPUT_DVO:
643 case INTEL_OUTPUT_TVOUT:
646 case INTEL_OUTPUT_ANALOG:
654 ok = psb_intel_find_best_PLL(crtc, adjusted_mode->clock, refclk,
657 dev_err(dev->dev, "Couldn't find PLL settings for mode!\n");
661 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
663 dpll = DPLL_VGA_MODE_DIS;
665 dpll |= DPLLB_MODE_LVDS;
666 dpll |= DPLL_DVO_HIGH_SPEED;
668 dpll |= DPLLB_MODE_DAC_SERIAL;
670 int sdvo_pixel_multiply =
671 adjusted_mode->clock / mode->clock;
672 dpll |= DPLL_DVO_HIGH_SPEED;
674 (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
677 /* compute bitmask from p1 value */
678 dpll |= (1 << (clock.p1 - 1)) << 16;
681 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
684 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
687 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
690 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
695 /* XXX: just matching BIOS for now */
696 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
699 dpll |= PLL_REF_INPUT_DREFCLK;
702 pipeconf = REG_READ(pipeconf_reg);
704 /* Set up the display plane register */
705 dspcntr = DISPPLANE_GAMMA_ENABLE;
708 dspcntr |= DISPPLANE_SEL_PIPE_A;
710 dspcntr |= DISPPLANE_SEL_PIPE_B;
712 dspcntr |= DISPLAY_PLANE_ENABLE;
713 pipeconf |= PIPEACONF_ENABLE;
714 dpll |= DPLL_VCO_ENABLE;
717 /* Disable the panel fitter if it was on our pipe */
718 if (psb_intel_panel_fitter_pipe(dev) == pipe)
719 REG_WRITE(PFIT_CONTROL, 0);
721 drm_mode_debug_printmodeline(mode);
723 if (dpll & DPLL_VCO_ENABLE) {
724 REG_WRITE(fp_reg, fp);
725 REG_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
730 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
731 * This is an exception to the general rule that mode_set doesn't turn
735 u32 lvds = REG_READ(LVDS);
737 lvds &= ~LVDS_PIPEB_SELECT;
739 lvds |= LVDS_PIPEB_SELECT;
741 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
742 /* Set the B0-B3 data pairs corresponding to
743 * whether we're going to
744 * set the DPLLs for dual-channel mode or not.
746 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
748 lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
750 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
751 * appropriately here, but we need to look more
752 * thoroughly into how panels behave in the two modes.
755 REG_WRITE(LVDS, lvds);
759 REG_WRITE(fp_reg, fp);
760 REG_WRITE(dpll_reg, dpll);
762 /* Wait for the clocks to stabilize. */
765 /* write it again -- the BIOS does, after all */
766 REG_WRITE(dpll_reg, dpll);
769 /* Wait for the clocks to stabilize. */
772 REG_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
773 ((adjusted_mode->crtc_htotal - 1) << 16));
774 REG_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
775 ((adjusted_mode->crtc_hblank_end - 1) << 16));
776 REG_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
777 ((adjusted_mode->crtc_hsync_end - 1) << 16));
778 REG_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
779 ((adjusted_mode->crtc_vtotal - 1) << 16));
780 REG_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
781 ((adjusted_mode->crtc_vblank_end - 1) << 16));
782 REG_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
783 ((adjusted_mode->crtc_vsync_end - 1) << 16));
784 /* pipesrc and dspsize control the size that is scaled from,
785 * which should always be the user's requested size.
787 REG_WRITE(dspsize_reg,
788 ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1));
789 REG_WRITE(dsppos_reg, 0);
790 REG_WRITE(pipesrc_reg,
791 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
792 REG_WRITE(pipeconf_reg, pipeconf);
793 REG_READ(pipeconf_reg);
795 psb_intel_wait_for_vblank(dev);
797 REG_WRITE(dspcntr_reg, dspcntr);
799 /* Flush the plane changes */
800 crtc_funcs->mode_set_base(crtc, x, y, old_fb);
802 psb_intel_wait_for_vblank(dev);
807 /** Loads the palette/gamma unit for the CRTC with the prepared values */
808 void psb_intel_crtc_load_lut(struct drm_crtc *crtc)
810 struct drm_device *dev = crtc->dev;
811 struct drm_psb_private *dev_priv =
812 (struct drm_psb_private *)dev->dev_private;
813 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
814 int palreg = PALETTE_A;
817 /* The clocks have to be on to load the palette. */
821 switch (psb_intel_crtc->pipe) {
831 dev_err(dev->dev, "Illegal Pipe Number.\n");
835 if (gma_power_begin(dev, false)) {
836 for (i = 0; i < 256; i++) {
837 REG_WRITE(palreg + 4 * i,
838 ((psb_intel_crtc->lut_r[i] +
839 psb_intel_crtc->lut_adj[i]) << 16) |
840 ((psb_intel_crtc->lut_g[i] +
841 psb_intel_crtc->lut_adj[i]) << 8) |
842 (psb_intel_crtc->lut_b[i] +
843 psb_intel_crtc->lut_adj[i]));
847 for (i = 0; i < 256; i++) {
848 dev_priv->regs.save_palette_a[i] =
849 ((psb_intel_crtc->lut_r[i] +
850 psb_intel_crtc->lut_adj[i]) << 16) |
851 ((psb_intel_crtc->lut_g[i] +
852 psb_intel_crtc->lut_adj[i]) << 8) |
853 (psb_intel_crtc->lut_b[i] +
854 psb_intel_crtc->lut_adj[i]);
861 * Save HW states of giving crtc
863 static void psb_intel_crtc_save(struct drm_crtc *crtc)
865 struct drm_device *dev = crtc->dev;
866 /* struct drm_psb_private *dev_priv =
867 (struct drm_psb_private *)dev->dev_private; */
868 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
869 struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state;
870 int pipeA = (psb_intel_crtc->pipe == 0);
875 dev_err(dev->dev, "No CRTC state found\n");
879 crtc_state->saveDSPCNTR = REG_READ(pipeA ? DSPACNTR : DSPBCNTR);
880 crtc_state->savePIPECONF = REG_READ(pipeA ? PIPEACONF : PIPEBCONF);
881 crtc_state->savePIPESRC = REG_READ(pipeA ? PIPEASRC : PIPEBSRC);
882 crtc_state->saveFP0 = REG_READ(pipeA ? FPA0 : FPB0);
883 crtc_state->saveFP1 = REG_READ(pipeA ? FPA1 : FPB1);
884 crtc_state->saveDPLL = REG_READ(pipeA ? DPLL_A : DPLL_B);
885 crtc_state->saveHTOTAL = REG_READ(pipeA ? HTOTAL_A : HTOTAL_B);
886 crtc_state->saveHBLANK = REG_READ(pipeA ? HBLANK_A : HBLANK_B);
887 crtc_state->saveHSYNC = REG_READ(pipeA ? HSYNC_A : HSYNC_B);
888 crtc_state->saveVTOTAL = REG_READ(pipeA ? VTOTAL_A : VTOTAL_B);
889 crtc_state->saveVBLANK = REG_READ(pipeA ? VBLANK_A : VBLANK_B);
890 crtc_state->saveVSYNC = REG_READ(pipeA ? VSYNC_A : VSYNC_B);
891 crtc_state->saveDSPSTRIDE = REG_READ(pipeA ? DSPASTRIDE : DSPBSTRIDE);
893 /*NOTE: DSPSIZE DSPPOS only for psb*/
894 crtc_state->saveDSPSIZE = REG_READ(pipeA ? DSPASIZE : DSPBSIZE);
895 crtc_state->saveDSPPOS = REG_READ(pipeA ? DSPAPOS : DSPBPOS);
897 crtc_state->saveDSPBASE = REG_READ(pipeA ? DSPABASE : DSPBBASE);
899 paletteReg = pipeA ? PALETTE_A : PALETTE_B;
900 for (i = 0; i < 256; ++i)
901 crtc_state->savePalette[i] = REG_READ(paletteReg + (i << 2));
905 * Restore HW states of giving crtc
907 static void psb_intel_crtc_restore(struct drm_crtc *crtc)
909 struct drm_device *dev = crtc->dev;
910 /* struct drm_psb_private * dev_priv =
911 (struct drm_psb_private *)dev->dev_private; */
912 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
913 struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state;
914 /* struct drm_crtc_helper_funcs * crtc_funcs = crtc->helper_private; */
915 int pipeA = (psb_intel_crtc->pipe == 0);
920 dev_err(dev->dev, "No crtc state\n");
924 if (crtc_state->saveDPLL & DPLL_VCO_ENABLE) {
925 REG_WRITE(pipeA ? DPLL_A : DPLL_B,
926 crtc_state->saveDPLL & ~DPLL_VCO_ENABLE);
927 REG_READ(pipeA ? DPLL_A : DPLL_B);
931 REG_WRITE(pipeA ? FPA0 : FPB0, crtc_state->saveFP0);
932 REG_READ(pipeA ? FPA0 : FPB0);
934 REG_WRITE(pipeA ? FPA1 : FPB1, crtc_state->saveFP1);
935 REG_READ(pipeA ? FPA1 : FPB1);
937 REG_WRITE(pipeA ? DPLL_A : DPLL_B, crtc_state->saveDPLL);
938 REG_READ(pipeA ? DPLL_A : DPLL_B);
941 REG_WRITE(pipeA ? HTOTAL_A : HTOTAL_B, crtc_state->saveHTOTAL);
942 REG_WRITE(pipeA ? HBLANK_A : HBLANK_B, crtc_state->saveHBLANK);
943 REG_WRITE(pipeA ? HSYNC_A : HSYNC_B, crtc_state->saveHSYNC);
944 REG_WRITE(pipeA ? VTOTAL_A : VTOTAL_B, crtc_state->saveVTOTAL);
945 REG_WRITE(pipeA ? VBLANK_A : VBLANK_B, crtc_state->saveVBLANK);
946 REG_WRITE(pipeA ? VSYNC_A : VSYNC_B, crtc_state->saveVSYNC);
947 REG_WRITE(pipeA ? DSPASTRIDE : DSPBSTRIDE, crtc_state->saveDSPSTRIDE);
949 REG_WRITE(pipeA ? DSPASIZE : DSPBSIZE, crtc_state->saveDSPSIZE);
950 REG_WRITE(pipeA ? DSPAPOS : DSPBPOS, crtc_state->saveDSPPOS);
952 REG_WRITE(pipeA ? PIPEASRC : PIPEBSRC, crtc_state->savePIPESRC);
953 REG_WRITE(pipeA ? DSPABASE : DSPBBASE, crtc_state->saveDSPBASE);
954 REG_WRITE(pipeA ? PIPEACONF : PIPEBCONF, crtc_state->savePIPECONF);
956 psb_intel_wait_for_vblank(dev);
958 REG_WRITE(pipeA ? DSPACNTR : DSPBCNTR, crtc_state->saveDSPCNTR);
959 REG_WRITE(pipeA ? DSPABASE : DSPBBASE, crtc_state->saveDSPBASE);
961 psb_intel_wait_for_vblank(dev);
963 paletteReg = pipeA ? PALETTE_A : PALETTE_B;
964 for (i = 0; i < 256; ++i)
965 REG_WRITE(paletteReg + (i << 2), crtc_state->savePalette[i]);
968 static int psb_intel_crtc_cursor_set(struct drm_crtc *crtc,
969 struct drm_file *file_priv,
971 uint32_t width, uint32_t height)
973 struct drm_device *dev = crtc->dev;
974 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
975 int pipe = psb_intel_crtc->pipe;
976 uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
977 uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
980 struct gtt_range *gt;
981 struct drm_gem_object *obj;
984 /* if we want to turn of the cursor ignore width and height */
986 /* turn off the cursor */
987 temp = CURSOR_MODE_DISABLE;
989 if (gma_power_begin(dev, false)) {
990 REG_WRITE(control, temp);
995 /* Unpin the old GEM object */
996 if (psb_intel_crtc->cursor_obj) {
997 gt = container_of(psb_intel_crtc->cursor_obj,
998 struct gtt_range, gem);
1000 drm_gem_object_unreference(psb_intel_crtc->cursor_obj);
1001 psb_intel_crtc->cursor_obj = NULL;
1007 /* Currently we only support 64x64 cursors */
1008 if (width != 64 || height != 64) {
1009 dev_dbg(dev->dev, "we currently only support 64x64 cursors\n");
1013 obj = drm_gem_object_lookup(dev, file_priv, handle);
1017 if (obj->size < width * height * 4) {
1018 dev_dbg(dev->dev, "buffer is to small\n");
1022 gt = container_of(obj, struct gtt_range, gem);
1024 /* Pin the memory into the GTT */
1025 ret = psb_gtt_pin(gt);
1027 dev_err(dev->dev, "Can not pin down handle 0x%x\n", handle);
1032 addr = gt->offset; /* Or resource.start ??? */
1034 psb_intel_crtc->cursor_addr = addr;
1037 /* set the pipe for the cursor */
1038 temp |= (pipe << 28);
1039 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
1041 if (gma_power_begin(dev, false)) {
1042 REG_WRITE(control, temp);
1043 REG_WRITE(base, addr);
1047 /* unpin the old bo */
1048 if (psb_intel_crtc->cursor_obj) {
1049 gt = container_of(psb_intel_crtc->cursor_obj,
1050 struct gtt_range, gem);
1052 drm_gem_object_unreference(psb_intel_crtc->cursor_obj);
1053 psb_intel_crtc->cursor_obj = obj;
1058 static int psb_intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
1060 struct drm_device *dev = crtc->dev;
1061 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1062 int pipe = psb_intel_crtc->pipe;
1068 temp |= (CURSOR_POS_SIGN << CURSOR_X_SHIFT);
1072 temp |= (CURSOR_POS_SIGN << CURSOR_Y_SHIFT);
1076 temp |= ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT);
1077 temp |= ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
1079 addr = psb_intel_crtc->cursor_addr;
1081 if (gma_power_begin(dev, false)) {
1082 REG_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
1083 REG_WRITE((pipe == 0) ? CURABASE : CURBBASE, addr);
1089 void psb_intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red,
1090 u16 *green, u16 *blue, uint32_t type, uint32_t size)
1092 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1098 for (i = 0; i < 256; i++) {
1099 psb_intel_crtc->lut_r[i] = red[i] >> 8;
1100 psb_intel_crtc->lut_g[i] = green[i] >> 8;
1101 psb_intel_crtc->lut_b[i] = blue[i] >> 8;
1104 psb_intel_crtc_load_lut(crtc);
1107 static int psb_crtc_set_config(struct drm_mode_set *set)
1110 struct drm_device *dev = set->crtc->dev;
1111 struct drm_psb_private *dev_priv = dev->dev_private;
1113 if (!dev_priv->rpm_enabled)
1114 return drm_crtc_helper_set_config(set);
1116 pm_runtime_forbid(&dev->pdev->dev);
1117 ret = drm_crtc_helper_set_config(set);
1118 pm_runtime_allow(&dev->pdev->dev);
1122 /* Returns the clock of the currently programmed mode of the given pipe. */
1123 static int psb_intel_crtc_clock_get(struct drm_device *dev,
1124 struct drm_crtc *crtc)
1126 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1127 int pipe = psb_intel_crtc->pipe;
1130 struct psb_intel_clock_t clock;
1132 struct drm_psb_private *dev_priv = dev->dev_private;
1134 if (gma_power_begin(dev, false)) {
1135 dpll = REG_READ((pipe == 0) ? DPLL_A : DPLL_B);
1136 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
1137 fp = REG_READ((pipe == 0) ? FPA0 : FPB0);
1139 fp = REG_READ((pipe == 0) ? FPA1 : FPB1);
1140 is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN);
1143 dpll = (pipe == 0) ?
1144 dev_priv->regs.saveDPLL_A : dev_priv->regs.saveDPLL_B;
1146 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
1148 dev_priv->regs.saveFPA0 :
1149 dev_priv->regs.saveFPB0;
1152 dev_priv->regs.saveFPA1 :
1153 dev_priv->regs.saveFPB1;
1155 is_lvds = (pipe == 1) && (dev_priv->regs.saveLVDS &
1159 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
1160 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
1161 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
1166 DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
1167 DPLL_FPA01_P1_POST_DIV_SHIFT);
1170 if ((dpll & PLL_REF_INPUT_MASK) ==
1171 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
1172 /* XXX: might not be 66MHz */
1173 i8xx_clock(66000, &clock);
1175 i8xx_clock(48000, &clock);
1177 if (dpll & PLL_P1_DIVIDE_BY_TWO)
1182 DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
1183 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
1185 if (dpll & PLL_P2_DIVIDE_BY_4)
1190 i8xx_clock(48000, &clock);
1193 /* XXX: It would be nice to validate the clocks, but we can't reuse
1194 * i830PllIsValid() because it relies on the xf86_config connector
1195 * configuration being accurate, which it isn't necessarily.
1201 /** Returns the currently programmed mode of the given pipe. */
1202 struct drm_display_mode *psb_intel_crtc_mode_get(struct drm_device *dev,
1203 struct drm_crtc *crtc)
1205 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1206 int pipe = psb_intel_crtc->pipe;
1207 struct drm_display_mode *mode;
1212 struct drm_psb_private *dev_priv = dev->dev_private;
1214 if (gma_power_begin(dev, false)) {
1215 htot = REG_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
1216 hsync = REG_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
1217 vtot = REG_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
1218 vsync = REG_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
1221 htot = (pipe == 0) ?
1222 dev_priv->regs.saveHTOTAL_A :
1223 dev_priv->regs.saveHTOTAL_B;
1224 hsync = (pipe == 0) ?
1225 dev_priv->regs.saveHSYNC_A :
1226 dev_priv->regs.saveHSYNC_B;
1227 vtot = (pipe == 0) ?
1228 dev_priv->regs.saveVTOTAL_A :
1229 dev_priv->regs.saveVTOTAL_B;
1230 vsync = (pipe == 0) ?
1231 dev_priv->regs.saveVSYNC_A :
1232 dev_priv->regs.saveVSYNC_B;
1235 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
1239 mode->clock = psb_intel_crtc_clock_get(dev, crtc);
1240 mode->hdisplay = (htot & 0xffff) + 1;
1241 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
1242 mode->hsync_start = (hsync & 0xffff) + 1;
1243 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
1244 mode->vdisplay = (vtot & 0xffff) + 1;
1245 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
1246 mode->vsync_start = (vsync & 0xffff) + 1;
1247 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
1249 drm_mode_set_name(mode);
1250 drm_mode_set_crtcinfo(mode, 0);
1255 void psb_intel_crtc_destroy(struct drm_crtc *crtc)
1257 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1258 struct gtt_range *gt;
1260 /* Unpin the old GEM object */
1261 if (psb_intel_crtc->cursor_obj) {
1262 gt = container_of(psb_intel_crtc->cursor_obj,
1263 struct gtt_range, gem);
1265 drm_gem_object_unreference(psb_intel_crtc->cursor_obj);
1266 psb_intel_crtc->cursor_obj = NULL;
1268 kfree(psb_intel_crtc->crtc_state);
1269 drm_crtc_cleanup(crtc);
1270 kfree(psb_intel_crtc);
1273 const struct drm_crtc_helper_funcs psb_intel_helper_funcs = {
1274 .dpms = psb_intel_crtc_dpms,
1275 .mode_fixup = psb_intel_crtc_mode_fixup,
1276 .mode_set = psb_intel_crtc_mode_set,
1277 .mode_set_base = psb_intel_pipe_set_base,
1278 .prepare = psb_intel_crtc_prepare,
1279 .commit = psb_intel_crtc_commit,
1282 const struct drm_crtc_funcs psb_intel_crtc_funcs = {
1283 .save = psb_intel_crtc_save,
1284 .restore = psb_intel_crtc_restore,
1285 .cursor_set = psb_intel_crtc_cursor_set,
1286 .cursor_move = psb_intel_crtc_cursor_move,
1287 .gamma_set = psb_intel_crtc_gamma_set,
1288 .set_config = psb_crtc_set_config,
1289 .destroy = psb_intel_crtc_destroy,
1293 * Set the default value of cursor control and base register
1294 * to zero. This is a workaround for h/w defect on Oaktrail
1296 static void psb_intel_cursor_init(struct drm_device *dev, int pipe)
1298 u32 control[3] = { CURACNTR, CURBCNTR, CURCCNTR };
1299 u32 base[3] = { CURABASE, CURBBASE, CURCBASE };
1301 REG_WRITE(control[pipe], 0);
1302 REG_WRITE(base[pipe], 0);
1305 void psb_intel_crtc_init(struct drm_device *dev, int pipe,
1306 struct psb_intel_mode_device *mode_dev)
1308 struct drm_psb_private *dev_priv = dev->dev_private;
1309 struct psb_intel_crtc *psb_intel_crtc;
1311 uint16_t *r_base, *g_base, *b_base;
1313 /* We allocate a extra array of drm_connector pointers
1314 * for fbdev after the crtc */
1316 kzalloc(sizeof(struct psb_intel_crtc) +
1317 (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)),
1319 if (psb_intel_crtc == NULL)
1322 psb_intel_crtc->crtc_state =
1323 kzalloc(sizeof(struct psb_intel_crtc_state), GFP_KERNEL);
1324 if (!psb_intel_crtc->crtc_state) {
1325 dev_err(dev->dev, "Crtc state error: No memory\n");
1326 kfree(psb_intel_crtc);
1330 /* Set the CRTC operations from the chip specific data */
1331 drm_crtc_init(dev, &psb_intel_crtc->base, dev_priv->ops->crtc_funcs);
1333 drm_mode_crtc_set_gamma_size(&psb_intel_crtc->base, 256);
1334 psb_intel_crtc->pipe = pipe;
1335 psb_intel_crtc->plane = pipe;
1337 r_base = psb_intel_crtc->base.gamma_store;
1338 g_base = r_base + 256;
1339 b_base = g_base + 256;
1340 for (i = 0; i < 256; i++) {
1341 psb_intel_crtc->lut_r[i] = i;
1342 psb_intel_crtc->lut_g[i] = i;
1343 psb_intel_crtc->lut_b[i] = i;
1348 psb_intel_crtc->lut_adj[i] = 0;
1351 psb_intel_crtc->mode_dev = mode_dev;
1352 psb_intel_crtc->cursor_addr = 0;
1354 drm_crtc_helper_add(&psb_intel_crtc->base,
1355 dev_priv->ops->crtc_helper);
1357 /* Setup the array of drm_connector pointer array */
1358 psb_intel_crtc->mode_set.crtc = &psb_intel_crtc->base;
1359 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
1360 dev_priv->plane_to_crtc_mapping[psb_intel_crtc->plane] != NULL);
1361 dev_priv->plane_to_crtc_mapping[psb_intel_crtc->plane] =
1362 &psb_intel_crtc->base;
1363 dev_priv->pipe_to_crtc_mapping[psb_intel_crtc->pipe] =
1364 &psb_intel_crtc->base;
1365 psb_intel_crtc->mode_set.connectors =
1366 (struct drm_connector **) (psb_intel_crtc + 1);
1367 psb_intel_crtc->mode_set.num_connectors = 0;
1368 psb_intel_cursor_init(dev, pipe);
1371 int psb_intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1372 struct drm_file *file_priv)
1374 struct drm_psb_private *dev_priv = dev->dev_private;
1375 struct drm_psb_get_pipe_from_crtc_id_arg *pipe_from_crtc_id = data;
1376 struct drm_mode_object *drmmode_obj;
1377 struct psb_intel_crtc *crtc;
1380 dev_err(dev->dev, "called with no initialization\n");
1384 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
1385 DRM_MODE_OBJECT_CRTC);
1388 dev_err(dev->dev, "no such CRTC id\n");
1392 crtc = to_psb_intel_crtc(obj_to_crtc(drmmode_obj));
1393 pipe_from_crtc_id->pipe = crtc->pipe;
1398 struct drm_crtc *psb_intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
1400 struct drm_crtc *crtc = NULL;
1402 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1403 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1404 if (psb_intel_crtc->pipe == pipe)
1410 int psb_intel_connector_clones(struct drm_device *dev, int type_mask)
1413 struct drm_connector *connector;
1416 list_for_each_entry(connector, &dev->mode_config.connector_list,
1418 struct psb_intel_encoder *psb_intel_encoder =
1419 psb_intel_attached_encoder(connector);
1420 if (type_mask & (1 << psb_intel_encoder->type))
1421 index_mask |= (1 << entry);
1428 void psb_intel_modeset_cleanup(struct drm_device *dev)
1430 drm_mode_config_cleanup(dev);
1434 /* current intel driver doesn't take advantage of encoders
1435 always give back the encoder for the connector
1437 struct drm_encoder *psb_intel_best_encoder(struct drm_connector *connector)
1439 struct psb_intel_encoder *psb_intel_encoder =
1440 psb_intel_attached_encoder(connector);
1442 return &psb_intel_encoder->base;
1445 void psb_intel_connector_attach_encoder(struct psb_intel_connector *connector,
1446 struct psb_intel_encoder *encoder)
1448 connector->encoder = encoder;
1449 drm_mode_connector_attach_encoder(&connector->base,