drivers/gpu/drm/gma500/psb_intel_display.c

   1 /*
   2  * Copyright Â© 2006-2011 Intel Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along with
  14  * this program; if not, write to the Free Software Foundation, Inc.,
  15  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  16  *
  17  * Authors:
  18  *      Eric Anholt <eric@anholt.net>
  19  */
  20
  21 #include <linux/i2c.h>
  22 #include <linux/pm_runtime.h>
  23
  24 #include <drm/drmP.h>
  25 #include "framebuffer.h"
  26 #include "psb_drv.h"
  27 #include "psb_intel_drv.h"
  28 #include "psb_intel_reg.h"
  29 #include "gma_display.h"
  30 #include "power.h"
  31
  32 #define INTEL_LIMIT_I9XX_SDVO_DAC   0
  33 #define INTEL_LIMIT_I9XX_LVDS       1
  34
  35 static const struct gma_limit_t psb_intel_limits[] = {
  36         {                       /* INTEL_LIMIT_I9XX_SDVO_DAC */
  37          .dot = {.min = 20000, .max = 400000},
  38          .vco = {.min = 1400000, .max = 2800000},
  39          .n = {.min = 1, .max = 6},
  40          .m = {.min = 70, .max = 120},
  41          .m1 = {.min = 8, .max = 18},
  42          .m2 = {.min = 3, .max = 7},
  43          .p = {.min = 5, .max = 80},
  44          .p1 = {.min = 1, .max = 8},
  45          .p2 = {.dot_limit = 200000, .p2_slow = 10, .p2_fast = 5},
  46          .find_pll = gma_find_best_pll,
  47          },
  48         {                       /* INTEL_LIMIT_I9XX_LVDS */
  49          .dot = {.min = 20000, .max = 400000},
  50          .vco = {.min = 1400000, .max = 2800000},
  51          .n = {.min = 1, .max = 6},
  52          .m = {.min = 70, .max = 120},
  53          .m1 = {.min = 8, .max = 18},
  54          .m2 = {.min = 3, .max = 7},
  55          .p = {.min = 7, .max = 98},
  56          .p1 = {.min = 1, .max = 8},
  57          /* The single-channel range is 25-112Mhz, and dual-channel
  58           * is 80-224Mhz.  Prefer single channel as much as possible.
  59           */
  60          .p2 = {.dot_limit = 112000, .p2_slow = 14, .p2_fast = 7},
  61          .find_pll = gma_find_best_pll,
  62          },
  63 };
  64
  65 static const struct gma_limit_t *psb_intel_limit(struct drm_crtc *crtc,
  66                                                  int refclk)
  67 {
  68         const struct gma_limit_t *limit;
  69
  70         if (gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
  71                 limit = &psb_intel_limits[INTEL_LIMIT_I9XX_LVDS];
  72         else
  73                 limit = &psb_intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC];
  74         return limit;
  75 }
  76
  77 static void psb_intel_clock(int refclk, struct gma_clock_t *clock)
  78 {
  79         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
  80         clock->p = clock->p1 * clock->p2;
  81         clock->vco = refclk * clock->m / (clock->n + 2);
  82         clock->dot = clock->vco / clock->p;
  83 }
  84
  85 static int psb_intel_pipe_set_base(struct drm_crtc *crtc,
  86                             int x, int y, struct drm_framebuffer *old_fb)
  87 {
  88         struct drm_device *dev = crtc->dev;
  89         struct drm_psb_private *dev_priv = dev->dev_private;
  90         struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
  91         struct psb_framebuffer *psbfb = to_psb_fb(crtc->fb);
  92         int pipe = psb_intel_crtc->pipe;
  93         const struct psb_offset *map = &dev_priv->regmap[pipe];
  94         unsigned long start, offset;
  95         u32 dspcntr;
  96         int ret = 0;
  97
  98         if (!gma_power_begin(dev, true))
  99                 return 0;
 100
 101         /* no fb bound */
 102         if (!crtc->fb) {
 103                 dev_dbg(dev->dev, "No FB bound\n");
 104                 goto psb_intel_pipe_cleaner;
 105         }
 106
 107         /* We are displaying this buffer, make sure it is actually loaded
 108            into the GTT */
 109         ret = psb_gtt_pin(psbfb->gtt);
 110         if (ret < 0)
 111                 goto psb_intel_pipe_set_base_exit;
 112         start = psbfb->gtt->offset;
 113
 114         offset = y * crtc->fb->pitches[0] + x * (crtc->fb->bits_per_pixel / 8);
 115
 116         REG_WRITE(map->stride, crtc->fb->pitches[0]);
 117
 118         dspcntr = REG_READ(map->cntr);
 119         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
 120
 121         switch (crtc->fb->bits_per_pixel) {
 122         case 8:
 123                 dspcntr |= DISPPLANE_8BPP;
 124                 break;
 125         case 16:
 126                 if (crtc->fb->depth == 15)
 127                         dspcntr |= DISPPLANE_15_16BPP;
 128                 else
 129                         dspcntr |= DISPPLANE_16BPP;
 130                 break;
 131         case 24:
 132         case 32:
 133                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
 134                 break;
 135         default:
 136                 dev_err(dev->dev, "Unknown color depth\n");
 137                 ret = -EINVAL;
 138                 psb_gtt_unpin(psbfb->gtt);
 139                 goto psb_intel_pipe_set_base_exit;
 140         }
 141         REG_WRITE(map->cntr, dspcntr);
 142
 143         REG_WRITE(map->base, start + offset);
 144         REG_READ(map->base);
 145
 146 psb_intel_pipe_cleaner:
 147         /* If there was a previous display we can now unpin it */
 148         if (old_fb)
 149                 psb_gtt_unpin(to_psb_fb(old_fb)->gtt);
 150
 151 psb_intel_pipe_set_base_exit:
 152         gma_power_end(dev);
 153         return ret;
 154 }
 155
 156 /**
 157  * Sets the power management mode of the pipe and plane.
 158  *
 159  * This code should probably grow support for turning the cursor off and back
 160  * on appropriately at the same time as we're turning the pipe off/on.
 161  */
 162 static void psb_intel_crtc_dpms(struct drm_crtc *crtc, int mode)
 163 {
 164         struct drm_device *dev = crtc->dev;
 165         struct drm_psb_private *dev_priv = dev->dev_private;
 166         struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
 167         int pipe = psb_intel_crtc->pipe;
 168         const struct psb_offset *map = &dev_priv->regmap[pipe];
 169         u32 temp;
 170
 171         /* XXX: When our outputs are all unaware of DPMS modes other than off
 172          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
 173          */
 174         switch (mode) {
 175         case DRM_MODE_DPMS_ON:
 176         case DRM_MODE_DPMS_STANDBY:
 177         case DRM_MODE_DPMS_SUSPEND:
 178                 /* Enable the DPLL */
 179                 temp = REG_READ(map->dpll);
 180                 if ((temp & DPLL_VCO_ENABLE) == 0) {
 181                         REG_WRITE(map->dpll, temp);
 182                         REG_READ(map->dpll);
 183                         /* Wait for the clocks to stabilize. */
 184                         udelay(150);
 185                         REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);
 186                         REG_READ(map->dpll);
 187                         /* Wait for the clocks to stabilize. */
 188                         udelay(150);
 189                         REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);
 190                         REG_READ(map->dpll);
 191                         /* Wait for the clocks to stabilize. */
 192                         udelay(150);
 193                 }
 194
 195                 /* Enable the pipe */
 196                 temp = REG_READ(map->conf);
 197                 if ((temp & PIPEACONF_ENABLE) == 0)
 198                         REG_WRITE(map->conf, temp | PIPEACONF_ENABLE);
 199
 200                 /* Enable the plane */
 201                 temp = REG_READ(map->cntr);
 202                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
 203                         REG_WRITE(map->cntr,
 204                                   temp | DISPLAY_PLANE_ENABLE);
 205                         /* Flush the plane changes */
 206                         REG_WRITE(map->base, REG_READ(map->base));
 207                 }
 208
 209                 psb_intel_crtc_load_lut(crtc);
 210
 211                 /* Give the overlay scaler a chance to enable
 212                  * if it's on this pipe */
 213                 /* psb_intel_crtc_dpms_video(crtc, true); TODO */
 214                 break;
 215         case DRM_MODE_DPMS_OFF:
 216                 /* Give the overlay scaler a chance to disable
 217                  * if it's on this pipe */
 218                 /* psb_intel_crtc_dpms_video(crtc, FALSE); TODO */
 219
 220                 /* Disable the VGA plane that we never use */
 221                 REG_WRITE(VGACNTRL, VGA_DISP_DISABLE);
 222
 223                 /* Disable display plane */
 224                 temp = REG_READ(map->cntr);
 225                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
 226                         REG_WRITE(map->cntr,
 227                                   temp & ~DISPLAY_PLANE_ENABLE);
 228                         /* Flush the plane changes */
 229                         REG_WRITE(map->base, REG_READ(map->base));
 230                         REG_READ(map->base);
 231                 }
 232
 233                 /* Next, disable display pipes */
 234                 temp = REG_READ(map->conf);
 235                 if ((temp & PIPEACONF_ENABLE) != 0) {
 236                         REG_WRITE(map->conf, temp & ~PIPEACONF_ENABLE);
 237                         REG_READ(map->conf);
 238                 }
 239
 240                 /* Wait for vblank for the disable to take effect. */
 241                 gma_wait_for_vblank(dev);
 242
 243                 temp = REG_READ(map->dpll);
 244                 if ((temp & DPLL_VCO_ENABLE) != 0) {
 245                         REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE);
 246                         REG_READ(map->dpll);
 247                 }
 248
 249                 /* Wait for the clocks to turn off. */
 250                 udelay(150);
 251                 break;
 252         }
 253
 254         /*Set FIFO Watermarks*/
 255         REG_WRITE(DSPARB, 0x3F3E);
 256 }
 257
 258 static void psb_intel_crtc_prepare(struct drm_crtc *crtc)
 259 {
 260         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
 261         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
 262 }
 263
 264 static void psb_intel_crtc_commit(struct drm_crtc *crtc)
 265 {
 266         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
 267         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
 268 }
 269
 270 void psb_intel_encoder_prepare(struct drm_encoder *encoder)
 271 {
 272         struct drm_encoder_helper_funcs *encoder_funcs =
 273             encoder->helper_private;
 274         /* lvds has its own version of prepare see psb_intel_lvds_prepare */
 275         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
 276 }
 277
 278 void psb_intel_encoder_commit(struct drm_encoder *encoder)
 279 {
 280         struct drm_encoder_helper_funcs *encoder_funcs =
 281             encoder->helper_private;
 282         /* lvds has its own version of commit see psb_intel_lvds_commit */
 283         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
 284 }
 285
 286 void psb_intel_encoder_destroy(struct drm_encoder *encoder)
 287 {
 288         struct psb_intel_encoder *intel_encoder = to_psb_intel_encoder(encoder);
 289
 290         drm_encoder_cleanup(encoder);
 291         kfree(intel_encoder);
 292 }
 293
 294 static bool psb_intel_crtc_mode_fixup(struct drm_crtc *crtc,
 295                                   const struct drm_display_mode *mode,
 296                                   struct drm_display_mode *adjusted_mode)
 297 {
 298         return true;
 299 }
 300
 301
 302 /**
 303  * Return the pipe currently connected to the panel fitter,
 304  * or -1 if the panel fitter is not present or not in use
 305  */
 306 static int psb_intel_panel_fitter_pipe(struct drm_device *dev)
 307 {
 308         u32 pfit_control;
 309
 310         pfit_control = REG_READ(PFIT_CONTROL);
 311
 312         /* See if the panel fitter is in use */
 313         if ((pfit_control & PFIT_ENABLE) == 0)
 314                 return -1;
 315         /* Must be on PIPE 1 for PSB */
 316         return 1;
 317 }
 318
 319 static int psb_intel_crtc_mode_set(struct drm_crtc *crtc,
 320                                struct drm_display_mode *mode,
 321                                struct drm_display_mode *adjusted_mode,
 322                                int x, int y,
 323                                struct drm_framebuffer *old_fb)
 324 {
 325         struct drm_device *dev = crtc->dev;
 326         struct drm_psb_private *dev_priv = dev->dev_private;
 327         struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
 328         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
 329         int pipe = psb_intel_crtc->pipe;
 330         const struct psb_offset *map = &dev_priv->regmap[pipe];
 331         int refclk;
 332         struct gma_clock_t clock;
 333         u32 dpll = 0, fp = 0, dspcntr, pipeconf;
 334         bool ok, is_sdvo = false;
 335         bool is_lvds = false, is_tv = false;
 336         struct drm_mode_config *mode_config = &dev->mode_config;
 337         struct drm_connector *connector;
 338         const struct gma_limit_t *limit;
 339
 340         /* No scan out no play */
 341         if (crtc->fb == NULL) {
 342                 crtc_funcs->mode_set_base(crtc, x, y, old_fb);
 343                 return 0;
 344         }
 345
 346         list_for_each_entry(connector, &mode_config->connector_list, head) {
 347                 struct psb_intel_encoder *psb_intel_encoder =
 348                                         psb_intel_attached_encoder(connector);
 349
 350                 if (!connector->encoder
 351                     || connector->encoder->crtc != crtc)
 352                         continue;
 353
 354                 switch (psb_intel_encoder->type) {
 355                 case INTEL_OUTPUT_LVDS:
 356                         is_lvds = true;
 357                         break;
 358                 case INTEL_OUTPUT_SDVO:
 359                         is_sdvo = true;
 360                         break;
 361                 case INTEL_OUTPUT_TVOUT:
 362                         is_tv = true;
 363                         break;
 364                 }
 365         }
 366
 367         refclk = 96000;
 368
 369         limit = psb_intel_crtc->clock_funcs->limit(crtc, refclk);
 370
 371         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk,
 372                                  &clock);
 373         if (!ok) {
 374                 DRM_ERROR("Couldn't find PLL settings for mode! target: %d, actual: %d",
 375                           adjusted_mode->clock, clock.dot);
 376                 return 0;
 377         }
 378
 379         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
 380
 381         dpll = DPLL_VGA_MODE_DIS;
 382         if (is_lvds) {
 383                 dpll |= DPLLB_MODE_LVDS;
 384                 dpll |= DPLL_DVO_HIGH_SPEED;
 385         } else
 386                 dpll |= DPLLB_MODE_DAC_SERIAL;
 387         if (is_sdvo) {
 388                 int sdvo_pixel_multiply =
 389                             adjusted_mode->clock / mode->clock;
 390                 dpll |= DPLL_DVO_HIGH_SPEED;
 391                 dpll |=
 392                     (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
 393         }
 394
 395         /* compute bitmask from p1 value */
 396         dpll |= (1 << (clock.p1 - 1)) << 16;
 397         switch (clock.p2) {
 398         case 5:
 399                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
 400                 break;
 401         case 7:
 402                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
 403                 break;
 404         case 10:
 405                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
 406                 break;
 407         case 14:
 408                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
 409                 break;
 410         }
 411
 412         if (is_tv) {
 413                 /* XXX: just matching BIOS for now */
 414 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
 415                 dpll |= 3;
 416         }
 417         dpll |= PLL_REF_INPUT_DREFCLK;
 418
 419         /* setup pipeconf */
 420         pipeconf = REG_READ(map->conf);
 421
 422         /* Set up the display plane register */
 423         dspcntr = DISPPLANE_GAMMA_ENABLE;
 424
 425         if (pipe == 0)
 426                 dspcntr |= DISPPLANE_SEL_PIPE_A;
 427         else
 428                 dspcntr |= DISPPLANE_SEL_PIPE_B;
 429
 430         dspcntr |= DISPLAY_PLANE_ENABLE;
 431         pipeconf |= PIPEACONF_ENABLE;
 432         dpll |= DPLL_VCO_ENABLE;
 433
 434
 435         /* Disable the panel fitter if it was on our pipe */
 436         if (psb_intel_panel_fitter_pipe(dev) == pipe)
 437                 REG_WRITE(PFIT_CONTROL, 0);
 438
 439         drm_mode_debug_printmodeline(mode);
 440
 441         if (dpll & DPLL_VCO_ENABLE) {
 442                 REG_WRITE(map->fp0, fp);
 443                 REG_WRITE(map->dpll, dpll & ~DPLL_VCO_ENABLE);
 444                 REG_READ(map->dpll);
 445                 udelay(150);
 446         }
 447
 448         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
 449          * This is an exception to the general rule that mode_set doesn't turn
 450          * things on.
 451          */
 452         if (is_lvds) {
 453                 u32 lvds = REG_READ(LVDS);
 454
 455                 lvds &= ~LVDS_PIPEB_SELECT;
 456                 if (pipe == 1)
 457                         lvds |= LVDS_PIPEB_SELECT;
 458
 459                 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
 460                 /* Set the B0-B3 data pairs corresponding to
 461                  * whether we're going to
 462                  * set the DPLLs for dual-channel mode or not.
 463                  */
 464                 lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
 465                 if (clock.p2 == 7)
 466                         lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
 467
 468                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
 469                  * appropriately here, but we need to look more
 470                  * thoroughly into how panels behave in the two modes.
 471                  */
 472
 473                 REG_WRITE(LVDS, lvds);
 474                 REG_READ(LVDS);
 475         }
 476
 477         REG_WRITE(map->fp0, fp);
 478         REG_WRITE(map->dpll, dpll);
 479         REG_READ(map->dpll);
 480         /* Wait for the clocks to stabilize. */
 481         udelay(150);
 482
 483         /* write it again -- the BIOS does, after all */
 484         REG_WRITE(map->dpll, dpll);
 485
 486         REG_READ(map->dpll);
 487         /* Wait for the clocks to stabilize. */
 488         udelay(150);
 489
 490         REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) |
 491                   ((adjusted_mode->crtc_htotal - 1) << 16));
 492         REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) |
 493                   ((adjusted_mode->crtc_hblank_end - 1) << 16));
 494         REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) |
 495                   ((adjusted_mode->crtc_hsync_end - 1) << 16));
 496         REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) |
 497                   ((adjusted_mode->crtc_vtotal - 1) << 16));
 498         REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) |
 499                   ((adjusted_mode->crtc_vblank_end - 1) << 16));
 500         REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) |
 501                   ((adjusted_mode->crtc_vsync_end - 1) << 16));
 502         /* pipesrc and dspsize control the size that is scaled from,
 503          * which should always be the user's requested size.
 504          */
 505         REG_WRITE(map->size,
 506                   ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1));
 507         REG_WRITE(map->pos, 0);
 508         REG_WRITE(map->src,
 509                   ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
 510         REG_WRITE(map->conf, pipeconf);
 511         REG_READ(map->conf);
 512
 513         gma_wait_for_vblank(dev);
 514
 515         REG_WRITE(map->cntr, dspcntr);
 516
 517         /* Flush the plane changes */
 518         crtc_funcs->mode_set_base(crtc, x, y, old_fb);
 519
 520         gma_wait_for_vblank(dev);
 521
 522         return 0;
 523 }
 524
 525 /** Loads the palette/gamma unit for the CRTC with the prepared values */
 526 void psb_intel_crtc_load_lut(struct drm_crtc *crtc)
 527 {
 528         struct drm_device *dev = crtc->dev;
 529         struct drm_psb_private *dev_priv = dev->dev_private;
 530         struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
 531         const struct psb_offset *map = &dev_priv->regmap[psb_intel_crtc->pipe];
 532         int palreg = map->palette;
 533         int i;
 534
 535         /* The clocks have to be on to load the palette. */
 536         if (!crtc->enabled)
 537                 return;
 538
 539         switch (psb_intel_crtc->pipe) {
 540         case 0:
 541         case 1:
 542                 break;
 543         default:
 544                 dev_err(dev->dev, "Illegal Pipe Number.\n");
 545                 return;
 546         }
 547
 548         if (gma_power_begin(dev, false)) {
 549                 for (i = 0; i < 256; i++) {
 550                         REG_WRITE(palreg + 4 * i,
 551                                   ((psb_intel_crtc->lut_r[i] +
 552                                   psb_intel_crtc->lut_adj[i]) << 16) |
 553                                   ((psb_intel_crtc->lut_g[i] +
 554                                   psb_intel_crtc->lut_adj[i]) << 8) |
 555                                   (psb_intel_crtc->lut_b[i] +
 556                                   psb_intel_crtc->lut_adj[i]));
 557                 }
 558                 gma_power_end(dev);
 559         } else {
 560                 for (i = 0; i < 256; i++) {
 561                         dev_priv->regs.pipe[0].palette[i] =
 562                                   ((psb_intel_crtc->lut_r[i] +
 563                                   psb_intel_crtc->lut_adj[i]) << 16) |
 564                                   ((psb_intel_crtc->lut_g[i] +
 565                                   psb_intel_crtc->lut_adj[i]) << 8) |
 566                                   (psb_intel_crtc->lut_b[i] +
 567                                   psb_intel_crtc->lut_adj[i]);
 568                 }
 569
 570         }
 571 }
 572
 573 /**
 574  * Save HW states of giving crtc
 575  */
 576 static void psb_intel_crtc_save(struct drm_crtc *crtc)
 577 {
 578         struct drm_device *dev = crtc->dev;
 579         struct drm_psb_private *dev_priv = dev->dev_private;
 580         struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
 581         struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state;
 582         const struct psb_offset *map = &dev_priv->regmap[psb_intel_crtc->pipe];
 583         uint32_t paletteReg;
 584         int i;
 585
 586         if (!crtc_state) {
 587                 dev_err(dev->dev, "No CRTC state found\n");
 588                 return;
 589         }
 590
 591         crtc_state->saveDSPCNTR = REG_READ(map->cntr);
 592         crtc_state->savePIPECONF = REG_READ(map->conf);
 593         crtc_state->savePIPESRC = REG_READ(map->src);
 594         crtc_state->saveFP0 = REG_READ(map->fp0);
 595         crtc_state->saveFP1 = REG_READ(map->fp1);
 596         crtc_state->saveDPLL = REG_READ(map->dpll);
 597         crtc_state->saveHTOTAL = REG_READ(map->htotal);
 598         crtc_state->saveHBLANK = REG_READ(map->hblank);
 599         crtc_state->saveHSYNC = REG_READ(map->hsync);
 600         crtc_state->saveVTOTAL = REG_READ(map->vtotal);
 601         crtc_state->saveVBLANK = REG_READ(map->vblank);
 602         crtc_state->saveVSYNC = REG_READ(map->vsync);
 603         crtc_state->saveDSPSTRIDE = REG_READ(map->stride);
 604
 605         /*NOTE: DSPSIZE DSPPOS only for psb*/
 606         crtc_state->saveDSPSIZE = REG_READ(map->size);
 607         crtc_state->saveDSPPOS = REG_READ(map->pos);
 608
 609         crtc_state->saveDSPBASE = REG_READ(map->base);
 610
 611         paletteReg = map->palette;
 612         for (i = 0; i < 256; ++i)
 613                 crtc_state->savePalette[i] = REG_READ(paletteReg + (i << 2));
 614 }
 615
 616 /**
 617  * Restore HW states of giving crtc
 618  */
 619 static void psb_intel_crtc_restore(struct drm_crtc *crtc)
 620 {
 621         struct drm_device *dev = crtc->dev;
 622         struct drm_psb_private *dev_priv = dev->dev_private;
 623         struct psb_intel_crtc *psb_intel_crtc =  to_psb_intel_crtc(crtc);
 624         struct psb_intel_crtc_state *crtc_state = psb_intel_crtc->crtc_state;
 625         const struct psb_offset *map = &dev_priv->regmap[psb_intel_crtc->pipe];
 626         uint32_t paletteReg;
 627         int i;
 628
 629         if (!crtc_state) {
 630                 dev_err(dev->dev, "No crtc state\n");
 631                 return;
 632         }
 633
 634         if (crtc_state->saveDPLL & DPLL_VCO_ENABLE) {
 635                 REG_WRITE(map->dpll,
 636                         crtc_state->saveDPLL & ~DPLL_VCO_ENABLE);
 637                 REG_READ(map->dpll);
 638                 udelay(150);
 639         }
 640
 641         REG_WRITE(map->fp0, crtc_state->saveFP0);
 642         REG_READ(map->fp0);
 643
 644         REG_WRITE(map->fp1, crtc_state->saveFP1);
 645         REG_READ(map->fp1);
 646
 647         REG_WRITE(map->dpll, crtc_state->saveDPLL);
 648         REG_READ(map->dpll);
 649         udelay(150);
 650
 651         REG_WRITE(map->htotal, crtc_state->saveHTOTAL);
 652         REG_WRITE(map->hblank, crtc_state->saveHBLANK);
 653         REG_WRITE(map->hsync, crtc_state->saveHSYNC);
 654         REG_WRITE(map->vtotal, crtc_state->saveVTOTAL);
 655         REG_WRITE(map->vblank, crtc_state->saveVBLANK);
 656         REG_WRITE(map->vsync, crtc_state->saveVSYNC);
 657         REG_WRITE(map->stride, crtc_state->saveDSPSTRIDE);
 658
 659         REG_WRITE(map->size, crtc_state->saveDSPSIZE);
 660         REG_WRITE(map->pos, crtc_state->saveDSPPOS);
 661
 662         REG_WRITE(map->src, crtc_state->savePIPESRC);
 663         REG_WRITE(map->base, crtc_state->saveDSPBASE);
 664         REG_WRITE(map->conf, crtc_state->savePIPECONF);
 665
 666         gma_wait_for_vblank(dev);
 667
 668         REG_WRITE(map->cntr, crtc_state->saveDSPCNTR);
 669         REG_WRITE(map->base, crtc_state->saveDSPBASE);
 670
 671         gma_wait_for_vblank(dev);
 672
 673         paletteReg = map->palette;
 674         for (i = 0; i < 256; ++i)
 675                 REG_WRITE(paletteReg + (i << 2), crtc_state->savePalette[i]);
 676 }
 677
 678 static int psb_intel_crtc_cursor_set(struct drm_crtc *crtc,
 679                                  struct drm_file *file_priv,
 680                                  uint32_t handle,
 681                                  uint32_t width, uint32_t height)
 682 {
 683         struct drm_device *dev = crtc->dev;
 684         struct drm_psb_private *dev_priv = dev->dev_private;
 685         struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
 686         int pipe = psb_intel_crtc->pipe;
 687         uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
 688         uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
 689         uint32_t temp;
 690         size_t addr = 0;
 691         struct gtt_range *gt;
 692         struct gtt_range *cursor_gt = psb_intel_crtc->cursor_gt;
 693         struct drm_gem_object *obj;
 694         void *tmp_dst, *tmp_src;
 695         int ret = 0, i, cursor_pages;
 696
 697         /* if we want to turn of the cursor ignore width and height */
 698         if (!handle) {
 699                 /* turn off the cursor */
 700                 temp = CURSOR_MODE_DISABLE;
 701
 702                 if (gma_power_begin(dev, false)) {
 703                         REG_WRITE(control, temp);
 704                         REG_WRITE(base, 0);
 705                         gma_power_end(dev);
 706                 }
 707
 708                 /* Unpin the old GEM object */
 709                 if (psb_intel_crtc->cursor_obj) {
 710                         gt = container_of(psb_intel_crtc->cursor_obj,
 711                                                         struct gtt_range, gem);
 712                         psb_gtt_unpin(gt);
 713                         drm_gem_object_unreference(psb_intel_crtc->cursor_obj);
 714                         psb_intel_crtc->cursor_obj = NULL;
 715                 }
 716
 717                 return 0;
 718         }
 719
 720         /* Currently we only support 64x64 cursors */
 721         if (width != 64 || height != 64) {
 722                 dev_dbg(dev->dev, "we currently only support 64x64 cursors\n");
 723                 return -EINVAL;
 724         }
 725
 726         obj = drm_gem_object_lookup(dev, file_priv, handle);
 727         if (!obj)
 728                 return -ENOENT;
 729
 730         if (obj->size < width * height * 4) {
 731                 dev_dbg(dev->dev, "buffer is to small\n");
 732                 ret = -ENOMEM;
 733                 goto unref_cursor;
 734         }
 735
 736         gt = container_of(obj, struct gtt_range, gem);
 737
 738         /* Pin the memory into the GTT */
 739         ret = psb_gtt_pin(gt);
 740         if (ret) {
 741                 dev_err(dev->dev, "Can not pin down handle 0x%x\n", handle);
 742                 goto unref_cursor;
 743         }
 744
 745         if (dev_priv->ops->cursor_needs_phys) {
 746                 if (cursor_gt == NULL) {
 747                         dev_err(dev->dev, "No hardware cursor mem available");
 748                         ret = -ENOMEM;
 749                         goto unref_cursor;
 750                 }
 751
 752                 /* Prevent overflow */
 753                 if (gt->npage > 4)
 754                         cursor_pages = 4;
 755                 else
 756                         cursor_pages = gt->npage;
 757
 758                 /* Copy the cursor to cursor mem */
 759                 tmp_dst = dev_priv->vram_addr + cursor_gt->offset;
 760                 for (i = 0; i < cursor_pages; i++) {
 761                         tmp_src = kmap(gt->pages[i]);
 762                         memcpy(tmp_dst, tmp_src, PAGE_SIZE);
 763                         kunmap(gt->pages[i]);
 764                         tmp_dst += PAGE_SIZE;
 765                 }
 766
 767                 addr = psb_intel_crtc->cursor_addr;
 768         } else {
 769                 addr = gt->offset;      /* Or resource.start ??? */
 770                 psb_intel_crtc->cursor_addr = addr;
 771         }
 772
 773         temp = 0;
 774         /* set the pipe for the cursor */
 775         temp |= (pipe << 28);
 776         temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
 777
 778         if (gma_power_begin(dev, false)) {
 779                 REG_WRITE(control, temp);
 780                 REG_WRITE(base, addr);
 781                 gma_power_end(dev);
 782         }
 783
 784         /* unpin the old bo */
 785         if (psb_intel_crtc->cursor_obj) {
 786                 gt = container_of(psb_intel_crtc->cursor_obj,
 787                                                         struct gtt_range, gem);
 788                 psb_gtt_unpin(gt);
 789                 drm_gem_object_unreference(psb_intel_crtc->cursor_obj);
 790         }
 791
 792         psb_intel_crtc->cursor_obj = obj;
 793         return ret;
 794
 795 unref_cursor:
 796         drm_gem_object_unreference(obj);
 797         return ret;
 798 }
 799
 800 static int psb_intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
 801 {
 802         struct drm_device *dev = crtc->dev;
 803         struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
 804         int pipe = psb_intel_crtc->pipe;
 805         uint32_t temp = 0;
 806         uint32_t addr;
 807
 808
 809         if (x < 0) {
 810                 temp |= (CURSOR_POS_SIGN << CURSOR_X_SHIFT);
 811                 x = -x;
 812         }
 813         if (y < 0) {
 814                 temp |= (CURSOR_POS_SIGN << CURSOR_Y_SHIFT);
 815                 y = -y;
 816         }
 817
 818         temp |= ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT);
 819         temp |= ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
 820
 821         addr = psb_intel_crtc->cursor_addr;
 822
 823         if (gma_power_begin(dev, false)) {
 824                 REG_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
 825                 REG_WRITE((pipe == 0) ? CURABASE : CURBBASE, addr);
 826                 gma_power_end(dev);
 827         }
 828         return 0;
 829 }
 830
 831 static void psb_intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red,
 832                          u16 *green, u16 *blue, uint32_t type, uint32_t size)
 833 {
 834         struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
 835         int i;
 836
 837         if (size != 256)
 838                 return;
 839
 840         for (i = 0; i < 256; i++) {
 841                 psb_intel_crtc->lut_r[i] = red[i] >> 8;
 842                 psb_intel_crtc->lut_g[i] = green[i] >> 8;
 843                 psb_intel_crtc->lut_b[i] = blue[i] >> 8;
 844         }
 845
 846         psb_intel_crtc_load_lut(crtc);
 847 }
 848
 849 static int psb_crtc_set_config(struct drm_mode_set *set)
 850 {
 851         int ret;
 852         struct drm_device *dev = set->crtc->dev;
 853         struct drm_psb_private *dev_priv = dev->dev_private;
 854
 855         if (!dev_priv->rpm_enabled)
 856                 return drm_crtc_helper_set_config(set);
 857
 858         pm_runtime_forbid(&dev->pdev->dev);
 859         ret = drm_crtc_helper_set_config(set);
 860         pm_runtime_allow(&dev->pdev->dev);
 861         return ret;
 862 }
 863
 864 /* Returns the clock of the currently programmed mode of the given pipe. */
 865 static int psb_intel_crtc_clock_get(struct drm_device *dev,
 866                                 struct drm_crtc *crtc)
 867 {
 868         struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
 869         struct drm_psb_private *dev_priv = dev->dev_private;
 870         int pipe = psb_intel_crtc->pipe;
 871         const struct psb_offset *map = &dev_priv->regmap[pipe];
 872         u32 dpll;
 873         u32 fp;
 874         struct gma_clock_t clock;
 875         bool is_lvds;
 876         struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
 877
 878         if (gma_power_begin(dev, false)) {
 879                 dpll = REG_READ(map->dpll);
 880                 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
 881                         fp = REG_READ(map->fp0);
 882                 else
 883                         fp = REG_READ(map->fp1);
 884                 is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN);
 885                 gma_power_end(dev);
 886         } else {
 887                 dpll = p->dpll;
 888
 889                 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
 890                         fp = p->fp0;
 891                 else
 892                         fp = p->fp1;
 893
 894                 is_lvds = (pipe == 1) && (dev_priv->regs.psb.saveLVDS &
 895                                                                 LVDS_PORT_EN);
 896         }
 897
 898         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
 899         clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
 900         clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
 901
 902         if (is_lvds) {
 903                 clock.p1 =
 904                     ffs((dpll &
 905                          DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
 906                         DPLL_FPA01_P1_POST_DIV_SHIFT);
 907                 clock.p2 = 14;
 908
 909                 if ((dpll & PLL_REF_INPUT_MASK) ==
 910                     PLLB_REF_INPUT_SPREADSPECTRUMIN) {
 911                         /* XXX: might not be 66MHz */
 912                         psb_intel_clock(66000, &clock);
 913                 } else
 914                         psb_intel_clock(48000, &clock);
 915         } else {
 916                 if (dpll & PLL_P1_DIVIDE_BY_TWO)
 917                         clock.p1 = 2;
 918                 else {
 919                         clock.p1 =
 920                             ((dpll &
 921                               DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
 922                              DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
 923                 }
 924                 if (dpll & PLL_P2_DIVIDE_BY_4)
 925                         clock.p2 = 4;
 926                 else
 927                         clock.p2 = 2;
 928
 929                 psb_intel_clock(48000, &clock);
 930         }
 931
 932         /* XXX: It would be nice to validate the clocks, but we can't reuse
 933          * i830PllIsValid() because it relies on the xf86_config connector
 934          * configuration being accurate, which it isn't necessarily.
 935          */
 936
 937         return clock.dot;
 938 }
 939
 940 /** Returns the currently programmed mode of the given pipe. */
 941 struct drm_display_mode *psb_intel_crtc_mode_get(struct drm_device *dev,
 942                                              struct drm_crtc *crtc)
 943 {
 944         struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
 945         int pipe = psb_intel_crtc->pipe;
 946         struct drm_display_mode *mode;
 947         int htot;
 948         int hsync;
 949         int vtot;
 950         int vsync;
 951         struct drm_psb_private *dev_priv = dev->dev_private;
 952         struct psb_pipe *p = &dev_priv->regs.pipe[pipe];
 953         const struct psb_offset *map = &dev_priv->regmap[pipe];
 954
 955         if (gma_power_begin(dev, false)) {
 956                 htot = REG_READ(map->htotal);
 957                 hsync = REG_READ(map->hsync);
 958                 vtot = REG_READ(map->vtotal);
 959                 vsync = REG_READ(map->vsync);
 960                 gma_power_end(dev);
 961         } else {
 962                 htot = p->htotal;
 963                 hsync = p->hsync;
 964                 vtot = p->vtotal;
 965                 vsync = p->vsync;
 966         }
 967
 968         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
 969         if (!mode)
 970                 return NULL;
 971
 972         mode->clock = psb_intel_crtc_clock_get(dev, crtc);
 973         mode->hdisplay = (htot & 0xffff) + 1;
 974         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
 975         mode->hsync_start = (hsync & 0xffff) + 1;
 976         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
 977         mode->vdisplay = (vtot & 0xffff) + 1;
 978         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
 979         mode->vsync_start = (vsync & 0xffff) + 1;
 980         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
 981
 982         drm_mode_set_name(mode);
 983         drm_mode_set_crtcinfo(mode, 0);
 984
 985         return mode;
 986 }
 987
 988 static void psb_intel_crtc_destroy(struct drm_crtc *crtc)
 989 {
 990         struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
 991         struct gtt_range *gt;
 992
 993         /* Unpin the old GEM object */
 994         if (psb_intel_crtc->cursor_obj) {
 995                 gt = container_of(psb_intel_crtc->cursor_obj,
 996                                                 struct gtt_range, gem);
 997                 psb_gtt_unpin(gt);
 998                 drm_gem_object_unreference(psb_intel_crtc->cursor_obj);
 999                 psb_intel_crtc->cursor_obj = NULL;
1000         }
1001
1002         if (psb_intel_crtc->cursor_gt != NULL)
1003                 psb_gtt_free_range(crtc->dev, psb_intel_crtc->cursor_gt);
1004         kfree(psb_intel_crtc->crtc_state);
1005         drm_crtc_cleanup(crtc);
1006         kfree(psb_intel_crtc);
1007 }
1008
1009 static void psb_intel_crtc_disable(struct drm_crtc *crtc)
1010 {
1011         struct gtt_range *gt;
1012         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
1013
1014         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
1015
1016         if (crtc->fb) {
1017                 gt = to_psb_fb(crtc->fb)->gtt;
1018                 psb_gtt_unpin(gt);
1019         }
1020 }
1021
1022 const struct drm_crtc_helper_funcs psb_intel_helper_funcs = {
1023         .dpms = psb_intel_crtc_dpms,
1024         .mode_fixup = psb_intel_crtc_mode_fixup,
1025         .mode_set = psb_intel_crtc_mode_set,
1026         .mode_set_base = psb_intel_pipe_set_base,
1027         .prepare = psb_intel_crtc_prepare,
1028         .commit = psb_intel_crtc_commit,
1029         .disable = psb_intel_crtc_disable,
1030 };
1031
1032 const struct drm_crtc_funcs psb_intel_crtc_funcs = {
1033         .save = psb_intel_crtc_save,
1034         .restore = psb_intel_crtc_restore,
1035         .cursor_set = psb_intel_crtc_cursor_set,
1036         .cursor_move = psb_intel_crtc_cursor_move,
1037         .gamma_set = psb_intel_crtc_gamma_set,
1038         .set_config = psb_crtc_set_config,
1039         .destroy = psb_intel_crtc_destroy,
1040 };
1041
1042 const struct gma_clock_funcs psb_clock_funcs = {
1043         .clock = psb_intel_clock,
1044         .limit = psb_intel_limit,
1045         .pll_is_valid = gma_pll_is_valid,
1046 };
1047
1048 /*
1049  * Set the default value of cursor control and base register
1050  * to zero. This is a workaround for h/w defect on Oaktrail
1051  */
1052 static void psb_intel_cursor_init(struct drm_device *dev,
1053                                   struct psb_intel_crtc *psb_intel_crtc)
1054 {
1055         struct drm_psb_private *dev_priv = dev->dev_private;
1056         u32 control[3] = { CURACNTR, CURBCNTR, CURCCNTR };
1057         u32 base[3] = { CURABASE, CURBBASE, CURCBASE };
1058         struct gtt_range *cursor_gt;
1059
1060         if (dev_priv->ops->cursor_needs_phys) {
1061                 /* Allocate 4 pages of stolen mem for a hardware cursor. That
1062                  * is enough for the 64 x 64 ARGB cursors we support.
1063                  */
1064                 cursor_gt = psb_gtt_alloc_range(dev, 4 * PAGE_SIZE, "cursor", 1);
1065                 if (!cursor_gt) {
1066                         psb_intel_crtc->cursor_gt = NULL;
1067                         goto out;
1068                 }
1069                 psb_intel_crtc->cursor_gt = cursor_gt;
1070                 psb_intel_crtc->cursor_addr = dev_priv->stolen_base +
1071                                                         cursor_gt->offset;
1072         } else {
1073                 psb_intel_crtc->cursor_gt = NULL;
1074         }
1075
1076 out:
1077         REG_WRITE(control[psb_intel_crtc->pipe], 0);
1078         REG_WRITE(base[psb_intel_crtc->pipe], 0);
1079 }
1080
1081 void psb_intel_crtc_init(struct drm_device *dev, int pipe,
1082                      struct psb_intel_mode_device *mode_dev)
1083 {
1084         struct drm_psb_private *dev_priv = dev->dev_private;
1085         struct psb_intel_crtc *psb_intel_crtc;
1086         int i;
1087         uint16_t *r_base, *g_base, *b_base;
1088
1089         /* We allocate a extra array of drm_connector pointers
1090          * for fbdev after the crtc */
1091         psb_intel_crtc =
1092             kzalloc(sizeof(struct psb_intel_crtc) +
1093                     (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)),
1094                     GFP_KERNEL);
1095         if (psb_intel_crtc == NULL)
1096                 return;
1097
1098         psb_intel_crtc->crtc_state =
1099                 kzalloc(sizeof(struct psb_intel_crtc_state), GFP_KERNEL);
1100         if (!psb_intel_crtc->crtc_state) {
1101                 dev_err(dev->dev, "Crtc state error: No memory\n");
1102                 kfree(psb_intel_crtc);
1103                 return;
1104         }
1105
1106         /* Set the CRTC operations from the chip specific data */
1107         drm_crtc_init(dev, &psb_intel_crtc->base, dev_priv->ops->crtc_funcs);
1108
1109         /* Set the CRTC clock functions from chip specific data */
1110         psb_intel_crtc->clock_funcs = dev_priv->ops->clock_funcs;
1111
1112         drm_mode_crtc_set_gamma_size(&psb_intel_crtc->base, 256);
1113         psb_intel_crtc->pipe = pipe;
1114         psb_intel_crtc->plane = pipe;
1115
1116         r_base = psb_intel_crtc->base.gamma_store;
1117         g_base = r_base + 256;
1118         b_base = g_base + 256;
1119         for (i = 0; i < 256; i++) {
1120                 psb_intel_crtc->lut_r[i] = i;
1121                 psb_intel_crtc->lut_g[i] = i;
1122                 psb_intel_crtc->lut_b[i] = i;
1123                 r_base[i] = i << 8;
1124                 g_base[i] = i << 8;
1125                 b_base[i] = i << 8;
1126
1127                 psb_intel_crtc->lut_adj[i] = 0;
1128         }
1129
1130         psb_intel_crtc->mode_dev = mode_dev;
1131         psb_intel_crtc->cursor_addr = 0;
1132
1133         drm_crtc_helper_add(&psb_intel_crtc->base,
1134                                                 dev_priv->ops->crtc_helper);
1135
1136         /* Setup the array of drm_connector pointer array */
1137         psb_intel_crtc->mode_set.crtc = &psb_intel_crtc->base;
1138         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
1139                dev_priv->plane_to_crtc_mapping[psb_intel_crtc->plane] != NULL);
1140         dev_priv->plane_to_crtc_mapping[psb_intel_crtc->plane] =
1141                                                         &psb_intel_crtc->base;
1142         dev_priv->pipe_to_crtc_mapping[psb_intel_crtc->pipe] =
1143                                                         &psb_intel_crtc->base;
1144         psb_intel_crtc->mode_set.connectors =
1145             (struct drm_connector **) (psb_intel_crtc + 1);
1146         psb_intel_crtc->mode_set.num_connectors = 0;
1147         psb_intel_cursor_init(dev, psb_intel_crtc);
1148
1149         /* Set to true so that the pipe is forced off on initial config. */
1150         psb_intel_crtc->active = true;
1151 }
1152
1153 int psb_intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
1154                                 struct drm_file *file_priv)
1155 {
1156         struct drm_psb_private *dev_priv = dev->dev_private;
1157         struct drm_psb_get_pipe_from_crtc_id_arg *pipe_from_crtc_id = data;
1158         struct drm_mode_object *drmmode_obj;
1159         struct psb_intel_crtc *crtc;
1160
1161         if (!dev_priv) {
1162                 dev_err(dev->dev, "called with no initialization\n");
1163                 return -EINVAL;
1164         }
1165
1166         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
1167                         DRM_MODE_OBJECT_CRTC);
1168
1169         if (!drmmode_obj) {
1170                 dev_err(dev->dev, "no such CRTC id\n");
1171                 return -EINVAL;
1172         }
1173
1174         crtc = to_psb_intel_crtc(obj_to_crtc(drmmode_obj));
1175         pipe_from_crtc_id->pipe = crtc->pipe;
1176
1177         return 0;
1178 }
1179
1180 struct drm_crtc *psb_intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
1181 {
1182         struct drm_crtc *crtc = NULL;
1183
1184         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1185                 struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
1186                 if (psb_intel_crtc->pipe == pipe)
1187                         break;
1188         }
1189         return crtc;
1190 }
1191
1192 int psb_intel_connector_clones(struct drm_device *dev, int type_mask)
1193 {
1194         int index_mask = 0;
1195         struct drm_connector *connector;
1196         int entry = 0;
1197
1198         list_for_each_entry(connector, &dev->mode_config.connector_list,
1199                             head) {
1200                 struct psb_intel_encoder *psb_intel_encoder =
1201                                         psb_intel_attached_encoder(connector);
1202                 if (type_mask & (1 << psb_intel_encoder->type))
1203                         index_mask |= (1 << entry);
1204                 entry++;
1205         }
1206         return index_mask;
1207 }
1208
1209 /* current intel driver doesn't take advantage of encoders
1210    always give back the encoder for the connector
1211 */
1212 struct drm_encoder *psb_intel_best_encoder(struct drm_connector *connector)
1213 {
1214         struct psb_intel_encoder *psb_intel_encoder =
1215                                         psb_intel_attached_encoder(connector);
1216
1217         return &psb_intel_encoder->base;
1218 }
1219
1220 void psb_intel_connector_attach_encoder(struct psb_intel_connector *connector,
1221                                         struct psb_intel_encoder *encoder)
1222 {
1223         connector->encoder = encoder;
1224         drm_mode_connector_attach_encoder(&connector->base,
1225                                           &encoder->base);
1226 }