2 * Copyright (c) 2009, Intel Corporation.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, write to the Free Software Foundation, Inc.,
15 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 #ifndef __PSB_INTEL_REG_H__
18 #define __PSB_INTEL_REG_H__
31 # define GPIO_CLOCK_DIR_MASK (1 << 0)
32 # define GPIO_CLOCK_DIR_IN (0 << 1)
33 # define GPIO_CLOCK_DIR_OUT (1 << 1)
34 # define GPIO_CLOCK_VAL_MASK (1 << 2)
35 # define GPIO_CLOCK_VAL_OUT (1 << 3)
36 # define GPIO_CLOCK_VAL_IN (1 << 4)
37 # define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
38 # define GPIO_DATA_DIR_MASK (1 << 8)
39 # define GPIO_DATA_DIR_IN (0 << 9)
40 # define GPIO_DATA_DIR_OUT (1 << 9)
41 # define GPIO_DATA_VAL_MASK (1 << 10)
42 # define GPIO_DATA_VAL_OUT (1 << 11)
43 # define GPIO_DATA_VAL_IN (1 << 12)
44 # define GPIO_DATA_PULLUP_DISABLE (1 << 13)
46 #define GMBUS0 0x5100 /* clock/port select */
47 #define GMBUS_RATE_100KHZ (0<<8)
48 #define GMBUS_RATE_50KHZ (1<<8)
49 #define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */
50 #define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */
51 #define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */
52 #define GMBUS_PORT_DISABLED 0
53 #define GMBUS_PORT_SSC 1
54 #define GMBUS_PORT_VGADDC 2
55 #define GMBUS_PORT_PANEL 3
56 #define GMBUS_PORT_DPC 4 /* HDMIC */
57 #define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */
59 #define GMBUS_PORT_DPD 7 /* HDMID */
60 #define GMBUS_NUM_PORTS 8
61 #define GMBUS1 0x5104 /* command/status */
62 #define GMBUS_SW_CLR_INT (1<<31)
63 #define GMBUS_SW_RDY (1<<30)
64 #define GMBUS_ENT (1<<29) /* enable timeout */
65 #define GMBUS_CYCLE_NONE (0<<25)
66 #define GMBUS_CYCLE_WAIT (1<<25)
67 #define GMBUS_CYCLE_INDEX (2<<25)
68 #define GMBUS_CYCLE_STOP (4<<25)
69 #define GMBUS_BYTE_COUNT_SHIFT 16
70 #define GMBUS_SLAVE_INDEX_SHIFT 8
71 #define GMBUS_SLAVE_ADDR_SHIFT 1
72 #define GMBUS_SLAVE_READ (1<<0)
73 #define GMBUS_SLAVE_WRITE (0<<0)
74 #define GMBUS2 0x5108 /* status */
75 #define GMBUS_INUSE (1<<15)
76 #define GMBUS_HW_WAIT_PHASE (1<<14)
77 #define GMBUS_STALL_TIMEOUT (1<<13)
78 #define GMBUS_INT (1<<12)
79 #define GMBUS_HW_RDY (1<<11)
80 #define GMBUS_SATOER (1<<10)
81 #define GMBUS_ACTIVE (1<<9)
82 #define GMBUS3 0x510c /* data buffer bytes 3-0 */
83 #define GMBUS4 0x5110 /* interrupt mask (Pineview+) */
84 #define GMBUS_SLAVE_TIMEOUT_EN (1<<4)
85 #define GMBUS_NAK_EN (1<<3)
86 #define GMBUS_IDLE_EN (1<<2)
87 #define GMBUS_HW_WAIT_EN (1<<1)
88 #define GMBUS_HW_RDY_EN (1<<0)
89 #define GMBUS5 0x5120 /* byte index */
90 #define GMBUS_2BYTE_INDEX_EN (1<<31)
92 #define BLC_PWM_CTL 0x61254
93 #define BLC_PWM_CTL2 0x61250
94 #define BLC_PWM_CTL_C 0x62254
95 #define BLC_PWM_CTL2_C 0x62250
96 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
98 * This is the most significant 15 bits of the number of backlight cycles in a
99 * complete cycle of the modulated backlight control.
101 * The actual value is this field multiplied by two.
103 #define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
104 #define BLM_LEGACY_MODE (1 << 16)
106 * This is the number of cycles out of the backlight modulation cycle for which
107 * the backlight is on.
109 * This field must be no greater than the number of cycles in the complete
110 * backlight modulation cycle.
112 #define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
113 #define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
115 #define I915_GCFGC 0xf0
116 #define I915_LOW_FREQUENCY_ENABLE (1 << 7)
117 #define I915_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
118 #define I915_DISPLAY_CLOCK_333_MHZ (4 << 4)
119 #define I915_DISPLAY_CLOCK_MASK (7 << 4)
121 #define I855_HPLLCC 0xc0
122 #define I855_CLOCK_CONTROL_MASK (3 << 0)
123 #define I855_CLOCK_133_200 (0 << 0)
124 #define I855_CLOCK_100_200 (1 << 0)
125 #define I855_CLOCK_100_133 (2 << 0)
126 #define I855_CLOCK_166_250 (3 << 0)
128 /* I830 CRTC registers */
129 #define HTOTAL_A 0x60000
130 #define HBLANK_A 0x60004
131 #define HSYNC_A 0x60008
132 #define VTOTAL_A 0x6000c
133 #define VBLANK_A 0x60010
134 #define VSYNC_A 0x60014
135 #define PIPEASRC 0x6001c
136 #define BCLRPAT_A 0x60020
137 #define VSYNCSHIFT_A 0x60028
139 #define HTOTAL_B 0x61000
140 #define HBLANK_B 0x61004
141 #define HSYNC_B 0x61008
142 #define VTOTAL_B 0x6100c
143 #define VBLANK_B 0x61010
144 #define VSYNC_B 0x61014
145 #define PIPEBSRC 0x6101c
146 #define BCLRPAT_B 0x61020
147 #define VSYNCSHIFT_B 0x61028
149 #define HTOTAL_C 0x62000
150 #define HBLANK_C 0x62004
151 #define HSYNC_C 0x62008
152 #define VTOTAL_C 0x6200c
153 #define VBLANK_C 0x62010
154 #define VSYNC_C 0x62014
155 #define PIPECSRC 0x6201c
156 #define BCLRPAT_C 0x62020
157 #define VSYNCSHIFT_C 0x62028
159 #define PP_STATUS 0x61200
160 # define PP_ON (1 << 31)
162 * Indicates that all dependencies of the panel are on:
166 * - LVDS/DVOB/DVOC on
168 #define PP_READY (1 << 30)
169 #define PP_SEQUENCE_NONE (0 << 28)
170 #define PP_SEQUENCE_ON (1 << 28)
171 #define PP_SEQUENCE_OFF (2 << 28)
172 #define PP_SEQUENCE_MASK 0x30000000
173 #define PP_CONTROL 0x61204
174 #define POWER_TARGET_ON (1 << 0)
176 #define LVDSPP_ON 0x61208
177 #define LVDSPP_OFF 0x6120c
178 #define PP_CYCLE 0x61210
180 #define PFIT_CONTROL 0x61230
181 #define PFIT_ENABLE (1 << 31)
182 #define PFIT_PIPE_MASK (3 << 29)
183 #define PFIT_PIPE_SHIFT 29
184 #define PFIT_SCALING_MODE_PILLARBOX (1 << 27)
185 #define PFIT_SCALING_MODE_LETTERBOX (3 << 26)
186 #define VERT_INTERP_DISABLE (0 << 10)
187 #define VERT_INTERP_BILINEAR (1 << 10)
188 #define VERT_INTERP_MASK (3 << 10)
189 #define VERT_AUTO_SCALE (1 << 9)
190 #define HORIZ_INTERP_DISABLE (0 << 6)
191 #define HORIZ_INTERP_BILINEAR (1 << 6)
192 #define HORIZ_INTERP_MASK (3 << 6)
193 #define HORIZ_AUTO_SCALE (1 << 5)
194 #define PANEL_8TO6_DITHER_ENABLE (1 << 3)
196 #define PFIT_PGM_RATIOS 0x61234
197 #define PFIT_VERT_SCALE_MASK 0xfff00000
198 #define PFIT_HORIZ_SCALE_MASK 0x0000fff0
200 #define PFIT_AUTO_RATIOS 0x61238
202 #define DPLL_A 0x06014
203 #define DPLL_B 0x06018
204 #define DPLL_VCO_ENABLE (1 << 31)
205 #define DPLL_DVO_HIGH_SPEED (1 << 30)
206 #define DPLL_SYNCLOCK_ENABLE (1 << 29)
207 #define DPLL_VGA_MODE_DIS (1 << 28)
208 #define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
209 #define DPLLB_MODE_LVDS (2 << 26) /* i915 */
210 #define DPLL_MODE_MASK (3 << 26)
211 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
212 #define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
213 #define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
214 #define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
215 #define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
216 #define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
217 #define DPLL_LOCK (1 << 15) /* CDV */
220 * The i830 generation, in DAC/serial mode, defines p1 as two plus this
221 * bitfield, or just 2 if PLL_P1_DIVIDE_BY_TWO is set.
223 # define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
225 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
226 * this field (only one bit may be set).
228 #define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
229 #define DPLL_FPA01_P1_POST_DIV_SHIFT 16
230 #define PLL_P2_DIVIDE_BY_4 (1 << 23) /* i830, required
232 # define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
233 #define PLL_REF_INPUT_DREFCLK (0 << 13)
234 #define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
235 #define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO
237 #define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
238 #define PLL_REF_INPUT_MASK (3 << 13)
239 #define PLL_LOAD_PULSE_PHASE_SHIFT 9
241 * Parallel to Serial Load Pulse phase selection.
242 * Selects the phase for the 10X DPLL clock for the PCIe
243 * digital display port. The range is 4 to 13; 10 or more
244 * is just a flip delay. The default is 6
246 #define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
247 #define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
250 * SDVO multiplier for 945G/GM. Not used on 965.
252 * DPLL_MD_UDI_MULTIPLIER_MASK
254 #define SDVO_MULTIPLIER_MASK 0x000000ff
255 #define SDVO_MULTIPLIER_SHIFT_HIRES 4
256 #define SDVO_MULTIPLIER_SHIFT_VGA 0
261 /* Pipe A SDVO/UDI clock multiplier/divider register for G965. */
262 #define DPLL_A_MD 0x0601c
263 /* Pipe B SDVO/UDI clock multiplier/divider register for G965. */
264 #define DPLL_B_MD 0x06020
266 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
268 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
270 #define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
271 #define DPLL_MD_UDI_DIVIDER_SHIFT 24
272 /* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
273 #define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
274 #define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
276 * SDVO/UDI pixel multiplier.
278 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
279 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
280 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
281 * dummy bytes in the datastream at an increased clock rate, with both sides of
282 * the link knowing how many bytes are fill.
284 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
285 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
286 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
287 * through an SDVO command.
289 * This register field has values of multiplication factor minus 1, with
290 * a maximum multiplier of 5 for SDVO.
292 #define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
293 #define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
295 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
296 * This best be set to the default value (3) or the CRT won't work. No,
297 * I don't entirely understand what this does...
299 #define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
300 #define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
302 #define DPLL_TEST 0x606c
303 #define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
304 #define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
305 #define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
306 #define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
307 #define DPLLB_TEST_N_BYPASS (1 << 19)
308 #define DPLLB_TEST_M_BYPASS (1 << 18)
309 #define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
310 #define DPLLA_TEST_N_BYPASS (1 << 3)
311 #define DPLLA_TEST_M_BYPASS (1 << 2)
312 #define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
315 #define ADPA_DAC_ENABLE (1 << 31)
316 #define ADPA_DAC_DISABLE 0
317 #define ADPA_PIPE_SELECT_MASK (1 << 30)
318 #define ADPA_PIPE_A_SELECT 0
319 #define ADPA_PIPE_B_SELECT (1 << 30)
320 #define ADPA_USE_VGA_HVPOLARITY (1 << 15)
321 #define ADPA_SETS_HVPOLARITY 0
322 #define ADPA_VSYNC_CNTL_DISABLE (1 << 11)
323 #define ADPA_VSYNC_CNTL_ENABLE 0
324 #define ADPA_HSYNC_CNTL_DISABLE (1 << 10)
325 #define ADPA_HSYNC_CNTL_ENABLE 0
326 #define ADPA_VSYNC_ACTIVE_HIGH (1 << 4)
327 #define ADPA_VSYNC_ACTIVE_LOW 0
328 #define ADPA_HSYNC_ACTIVE_HIGH (1 << 3)
329 #define ADPA_HSYNC_ACTIVE_LOW 0
335 #define FP_N_DIV_MASK 0x003f0000
336 #define FP_N_DIV_SHIFT 16
337 #define FP_M1_DIV_MASK 0x00003f00
338 #define FP_M1_DIV_SHIFT 8
339 #define FP_M2_DIV_MASK 0x0000003f
340 #define FP_M2_DIV_SHIFT 0
342 #define PORT_HOTPLUG_EN 0x61110
343 #define SDVOB_HOTPLUG_INT_EN (1 << 26)
344 #define SDVOC_HOTPLUG_INT_EN (1 << 25)
345 #define TV_HOTPLUG_INT_EN (1 << 18)
346 #define CRT_HOTPLUG_INT_EN (1 << 9)
347 #define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
349 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
350 #define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
351 #define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
352 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
353 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
354 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
355 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
356 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
357 #define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
358 #define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
359 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
360 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
361 #define CRT_HOTPLUG_DETECT_MASK 0x000000F8
363 #define PORT_HOTPLUG_STAT 0x61114
364 #define CRT_HOTPLUG_INT_STATUS (1 << 11)
365 #define TV_HOTPLUG_INT_STATUS (1 << 10)
366 #define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
367 #define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
368 #define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
369 #define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
370 #define SDVOC_HOTPLUG_INT_STATUS (1 << 7)
371 #define SDVOB_HOTPLUG_INT_STATUS (1 << 6)
373 #define SDVOB 0x61140
374 #define SDVOC 0x61160
375 #define SDVO_ENABLE (1 << 31)
376 #define SDVO_PIPE_B_SELECT (1 << 30)
377 #define SDVO_STALL_SELECT (1 << 29)
378 #define SDVO_INTERRUPT_ENABLE (1 << 26)
379 #define SDVO_COLOR_RANGE_16_235 (1 << 8)
380 #define SDVO_AUDIO_ENABLE (1 << 6)
383 * 915G/GM SDVO pixel multiplier.
385 * Programmed value is multiplier - 1, up to 5x.
387 * DPLL_MD_UDI_MULTIPLIER_MASK
389 #define SDVO_PORT_MULTIPLY_MASK (7 << 23)
390 #define SDVO_PORT_MULTIPLY_SHIFT 23
391 #define SDVO_PHASE_SELECT_MASK (15 << 19)
392 #define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
393 #define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
394 #define SDVOC_GANG_MODE (1 << 16)
395 #define SDVO_BORDER_ENABLE (1 << 7)
396 #define SDVOB_PCIE_CONCURRENCY (1 << 3)
397 #define SDVO_DETECTED (1 << 2)
398 /* Bits to be preserved when writing */
399 #define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14))
400 #define SDVOC_PRESERVE_MASK (1 << 17)
403 * This register controls the LVDS output enable, pipe selection, and data
406 * All of the clock/data pairs are force powered down by power sequencing.
410 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
411 * the DPLL semantics change when the LVDS is assigned to that pipe.
413 #define LVDS_PORT_EN (1 << 31)
414 /* Selects pipe B for LVDS data. Must be set on pre-965. */
415 #define LVDS_PIPEB_SELECT (1 << 30)
417 /* Turns on border drawing to allow centered display. */
418 #define LVDS_BORDER_EN (1 << 15)
421 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
424 #define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
425 #define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
426 #define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
428 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
429 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
432 #define LVDS_A3_POWER_MASK (3 << 6)
433 #define LVDS_A3_POWER_DOWN (0 << 6)
434 #define LVDS_A3_POWER_UP (3 << 6)
436 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
439 #define LVDS_CLKB_POWER_MASK (3 << 4)
440 #define LVDS_CLKB_POWER_DOWN (0 << 4)
441 #define LVDS_CLKB_POWER_UP (3 << 4)
443 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
444 * setting for whether we are in dual-channel mode. The B3 pair will
445 * additionally only be powered up when LVDS_A3_POWER_UP is set.
447 #define LVDS_B0B3_POWER_MASK (3 << 2)
448 #define LVDS_B0B3_POWER_DOWN (0 << 2)
449 #define LVDS_B0B3_POWER_UP (3 << 2)
451 #define PIPEACONF 0x70008
452 #define PIPEACONF_ENABLE (1 << 31)
453 #define PIPEACONF_DISABLE 0
454 #define PIPEACONF_DOUBLE_WIDE (1 << 30)
455 #define PIPECONF_ACTIVE (1 << 30)
456 #define I965_PIPECONF_ACTIVE (1 << 30)
457 #define PIPECONF_DSIPLL_LOCK (1 << 29)
458 #define PIPEACONF_SINGLE_WIDE 0
459 #define PIPEACONF_PIPE_UNLOCKED 0
460 #define PIPEACONF_DSR (1 << 26)
461 #define PIPEACONF_PIPE_LOCKED (1 << 25)
462 #define PIPEACONF_PALETTE 0
463 #define PIPECONF_FORCE_BORDER (1 << 25)
464 #define PIPEACONF_GAMMA (1 << 24)
465 #define PIPECONF_PROGRESSIVE (0 << 21)
466 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
467 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
468 #define PIPECONF_PLANE_OFF (1 << 19)
469 #define PIPECONF_CURSOR_OFF (1 << 18)
471 #define PIPEBCONF 0x71008
472 #define PIPEBCONF_ENABLE (1 << 31)
473 #define PIPEBCONF_DISABLE 0
474 #define PIPEBCONF_DOUBLE_WIDE (1 << 30)
475 #define PIPEBCONF_DISABLE 0
476 #define PIPEBCONF_GAMMA (1 << 24)
477 #define PIPEBCONF_PALETTE 0
479 #define PIPECCONF 0x72008
481 #define PIPEBGCMAXRED 0x71010
482 #define PIPEBGCMAXGREEN 0x71014
483 #define PIPEBGCMAXBLUE 0x71018
485 #define PIPEASTAT 0x70024
486 #define PIPEBSTAT 0x71024
487 #define PIPECSTAT 0x72024
488 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL << 1)
489 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL << 2)
490 #define PIPE_VBLANK_CLEAR (1 << 1)
491 #define PIPE_VBLANK_STATUS (1 << 1)
492 #define PIPE_TE_STATUS (1UL << 6)
493 #define PIPE_DPST_EVENT_STATUS (1UL << 7)
494 #define PIPE_VSYNC_CLEAR (1UL << 9)
495 #define PIPE_VSYNC_STATUS (1UL << 9)
496 #define PIPE_HDMI_AUDIO_UNDERRUN_STATUS (1UL << 10)
497 #define PIPE_HDMI_AUDIO_BUFFER_DONE_STATUS (1UL << 11)
498 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL << 17)
499 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL << 18)
500 #define PIPE_TE_ENABLE (1UL << 22)
501 #define PIPE_DPST_EVENT_ENABLE (1UL << 23)
502 #define PIPE_VSYNC_ENABL (1UL << 25)
503 #define PIPE_HDMI_AUDIO_UNDERRUN (1UL << 26)
504 #define PIPE_HDMI_AUDIO_BUFFER_DONE (1UL << 27)
505 #define PIPE_HDMI_AUDIO_INT_MASK (PIPE_HDMI_AUDIO_UNDERRUN | \
506 PIPE_HDMI_AUDIO_BUFFER_DONE)
507 #define PIPE_EVENT_MASK ((1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)|(1 << 24)|(1 << 23)|(1 << 22)|(1 << 21)|(1 << 20)|(1 << 16))
508 #define PIPE_VBLANK_MASK ((1 << 25)|(1 << 24)|(1 << 18)|(1 << 17))
509 #define HISTOGRAM_INT_CONTROL 0x61268
510 #define HISTOGRAM_BIN_DATA 0X61264
511 #define HISTOGRAM_LOGIC_CONTROL 0x61260
512 #define PWM_CONTROL_LOGIC 0x61250
513 #define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL << 10)
514 #define HISTOGRAM_INTERRUPT_ENABLE (1UL << 31)
515 #define HISTOGRAM_LOGIC_ENABLE (1UL << 31)
516 #define PWM_LOGIC_ENABLE (1UL << 31)
517 #define PWM_PHASEIN_ENABLE (1UL << 25)
518 #define PWM_PHASEIN_INT_ENABLE (1UL << 24)
519 #define PWM_PHASEIN_VB_COUNT 0x00001f00
520 #define PWM_PHASEIN_INC 0x0000001f
521 #define HISTOGRAM_INT_CTRL_CLEAR (1UL << 30)
522 #define DPST_YUV_LUMA_MODE 0
524 struct dpst_ie_histogram_control {
528 uint32_t bin_reg_index:7;
530 uint32_t bin_reg_func_select:1;
531 uint32_t sync_to_phase_in:1;
532 uint32_t alt_enhancement_mode:2;
533 uint32_t reserved1:1;
534 uint32_t sync_to_phase_in_count:8;
535 uint32_t histogram_mode_select:1;
536 uint32_t reserved2:4;
537 uint32_t ie_pipe_assignment:1;
538 uint32_t ie_mode_table_enabled:1;
539 uint32_t ie_histogram_enable:1;
544 struct dpst_guardband {
548 uint32_t guardband:22;
549 uint32_t guardband_interrupt_delay:8;
550 uint32_t interrupt_status:1;
551 uint32_t interrupt_enable:1;
556 #define PIPEAFRAMEHIGH 0x70040
557 #define PIPEAFRAMEPIXEL 0x70044
558 #define PIPEBFRAMEHIGH 0x71040
559 #define PIPEBFRAMEPIXEL 0x71044
560 #define PIPECFRAMEHIGH 0x72040
561 #define PIPECFRAMEPIXEL 0x72044
562 #define PIPE_FRAME_HIGH_MASK 0x0000ffff
563 #define PIPE_FRAME_HIGH_SHIFT 0
564 #define PIPE_FRAME_LOW_MASK 0xff000000
565 #define PIPE_FRAME_LOW_SHIFT 24
566 #define PIPE_PIXEL_MASK 0x00ffffff
567 #define PIPE_PIXEL_SHIFT 0
569 #define DSPARB 0x70030
570 #define DSPFW1 0x70034
571 #define DSPFW2 0x70038
572 #define DSPFW3 0x7003c
573 #define DSPFW4 0x70050
574 #define DSPFW5 0x70054
575 #define DSPFW6 0x70058
576 #define DSPCHICKENBIT 0x70400
577 #define DSPACNTR 0x70180
578 #define DSPBCNTR 0x71180
579 #define DSPCCNTR 0x72180
580 #define DISPLAY_PLANE_ENABLE (1 << 31)
581 #define DISPLAY_PLANE_DISABLE 0
582 #define DISPPLANE_GAMMA_ENABLE (1 << 30)
583 #define DISPPLANE_GAMMA_DISABLE 0
584 #define DISPPLANE_PIXFORMAT_MASK (0xf << 26)
585 #define DISPPLANE_8BPP (0x2 << 26)
586 #define DISPPLANE_15_16BPP (0x4 << 26)
587 #define DISPPLANE_16BPP (0x5 << 26)
588 #define DISPPLANE_32BPP_NO_ALPHA (0x6 << 26)
589 #define DISPPLANE_32BPP (0x7 << 26)
590 #define DISPPLANE_STEREO_ENABLE (1 << 25)
591 #define DISPPLANE_STEREO_DISABLE 0
592 #define DISPPLANE_SEL_PIPE_MASK (1 << 24)
593 #define DISPPLANE_SEL_PIPE_POS 24
594 #define DISPPLANE_SEL_PIPE_A 0
595 #define DISPPLANE_SEL_PIPE_B (1 << 24)
596 #define DISPPLANE_SRC_KEY_ENABLE (1 << 22)
597 #define DISPPLANE_SRC_KEY_DISABLE 0
598 #define DISPPLANE_LINE_DOUBLE (1 << 20)
599 #define DISPPLANE_NO_LINE_DOUBLE 0
600 #define DISPPLANE_STEREO_POLARITY_FIRST 0
601 #define DISPPLANE_STEREO_POLARITY_SECOND (1 << 18)
603 #define DISPPLANE_ALPHA_TRANS_ENABLE (1 << 15)
604 #define DISPPLANE_ALPHA_TRANS_DISABLE 0
605 #define DISPPLANE_SPRITE_ABOVE_DISPLAYA 0
606 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
607 #define DISPPLANE_BOTTOM (4)
609 #define DSPABASE 0x70184
610 #define DSPALINOFF 0x70184
611 #define DSPASTRIDE 0x70188
613 #define DSPBBASE 0x71184
614 #define DSPBLINOFF 0X71184
615 #define DSPBADDR DSPBBASE
616 #define DSPBSTRIDE 0x71188
618 #define DSPCBASE 0x72184
619 #define DSPCLINOFF 0x72184
620 #define DSPCSTRIDE 0x72188
622 #define DSPAKEYVAL 0x70194
623 #define DSPAKEYMASK 0x70198
625 #define DSPAPOS 0x7018C /* reserved */
626 #define DSPASIZE 0x70190
627 #define DSPBPOS 0x7118C
628 #define DSPBSIZE 0x71190
629 #define DSPCPOS 0x7218C
630 #define DSPCSIZE 0x72190
632 #define DSPASURF 0x7019C
633 #define DSPATILEOFF 0x701A4
635 #define DSPBSURF 0x7119C
636 #define DSPBTILEOFF 0x711A4
638 #define DSPCSURF 0x7219C
639 #define DSPCTILEOFF 0x721A4
640 #define DSPCKEYMAXVAL 0x721A0
641 #define DSPCKEYMINVAL 0x72194
642 #define DSPCKEYMSK 0x72198
644 #define VGACNTRL 0x71400
645 #define VGA_DISP_DISABLE (1 << 31)
646 #define VGA_2X_MODE (1 << 30)
647 #define VGA_PIPE_B_SELECT (1 << 29)
652 #define OV_C_OFFSET 0x08000
653 #define OV_OVADD 0x30000
654 #define OV_DOVASTA 0x30008
655 # define OV_PIPE_SELECT ((1 << 6)|(1 << 7))
656 # define OV_PIPE_SELECT_POS 6
659 #define OV_OGAMC5 0x30010
660 #define OV_OGAMC4 0x30014
661 #define OV_OGAMC3 0x30018
662 #define OV_OGAMC2 0x3001C
663 #define OV_OGAMC1 0x30020
664 #define OV_OGAMC0 0x30024
665 #define OVC_OVADD 0x38000
666 #define OVC_DOVCSTA 0x38008
667 #define OVC_OGAMC5 0x38010
668 #define OVC_OGAMC4 0x38014
669 #define OVC_OGAMC3 0x38018
670 #define OVC_OGAMC2 0x3801C
671 #define OVC_OGAMC1 0x38020
672 #define OVC_OGAMC0 0x38024
675 * Some BIOS scratch area registers. The 845 (and 830?) store the amount
676 * of video memory available to the BIOS in SWF1.
687 * 855 scratch registers.
689 #define SWF00 0x70410
690 #define SWF01 0x70414
691 #define SWF02 0x70418
692 #define SWF03 0x7041c
693 #define SWF04 0x70420
694 #define SWF05 0x70424
695 #define SWF06 0x70428
705 #define SWF30 0x72414
706 #define SWF31 0x72418
707 #define SWF32 0x7241c
713 #define PALETTE_A 0x0a000
714 #define PALETTE_B 0x0a800
715 #define PALETTE_C 0x0ac00
717 /* Cursor A & B regs */
718 #define CURACNTR 0x70080
719 #define CURSOR_MODE_DISABLE 0x00
720 #define CURSOR_MODE_64_32B_AX 0x07
721 #define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
722 #define MCURSOR_GAMMA_ENABLE (1 << 26)
723 #define CURABASE 0x70084
724 #define CURAPOS 0x70088
725 #define CURSOR_POS_MASK 0x007FF
726 #define CURSOR_POS_SIGN 0x8000
727 #define CURSOR_X_SHIFT 0
728 #define CURSOR_Y_SHIFT 16
729 #define CURBCNTR 0x700c0
730 #define CURBBASE 0x700c4
731 #define CURBPOS 0x700c8
732 #define CURCCNTR 0x700e0
733 #define CURCBASE 0x700e4
734 #define CURCPOS 0x700e8
737 * Interrupt Registers
745 * MOORESTOWN delta registers
747 #define MRST_DPLL_A 0x0f014
748 #define MDFLD_DPLL_B 0x0f018
749 #define MDFLD_INPUT_REF_SEL (1 << 14)
750 #define MDFLD_VCO_SEL (1 << 16)
751 #define DPLLA_MODE_LVDS (2 << 26) /* mrst */
752 #define MDFLD_PLL_LATCHEN (1 << 28)
753 #define MDFLD_PWR_GATE_EN (1 << 30)
754 #define MDFLD_P1_MASK (0x1FF << 17)
755 #define MRST_FPA0 0x0f040
756 #define MRST_FPA1 0x0f044
757 #define MDFLD_DPLL_DIV0 0x0f048
758 #define MDFLD_DPLL_DIV1 0x0f04c
759 #define MRST_PERF_MODE 0x020f4
762 * MEDFIELD HDMI registers
764 #define HDMIPHYMISCCTL 0x61134
765 #define HDMI_PHY_POWER_DOWN 0x7f
766 #define HDMIB_CONTROL 0x61140
767 #define HDMIB_PORT_EN (1 << 31)
768 #define HDMIB_PIPE_B_SELECT (1 << 30)
769 #define HDMIB_NULL_PACKET (1 << 9)
770 #define HDMIB_HDCP_PORT (1 << 5)
772 /* #define LVDS 0x61180 */
773 #define MRST_PANEL_8TO6_DITHER_ENABLE (1 << 25)
774 #define MRST_PANEL_24_DOT_1_FORMAT (1 << 24)
775 #define LVDS_A3_POWER_UP_0_OUTPUT (1 << 6)
778 #define MIPI_C 0x62190
779 #define MIPI_PORT_EN (1 << 31)
780 /* Turns on border drawing to allow centered display. */
781 #define SEL_FLOPPED_HSTX (1 << 23)
782 #define PASS_FROM_SPHY_TO_AFE (1 << 16)
783 #define MIPI_BORDER_EN (1 << 15)
784 #define MIPIA_3LANE_MIPIC_1LANE 0x1
785 #define MIPIA_2LANE_MIPIC_2LANE 0x2
786 #define TE_TRIGGER_DSI_PROTOCOL (1 << 2)
787 #define TE_TRIGGER_GPIO_PIN (1 << 3)
788 #define MIPI_TE_COUNT 0x61194
790 /* #define PP_CONTROL 0x61204 */
791 #define POWER_DOWN_ON_RESET (1 << 1)
793 /* #define PFIT_CONTROL 0x61230 */
794 #define PFIT_PIPE_SELECT (3 << 29)
795 #define PFIT_PIPE_SELECT_SHIFT (29)
797 /* #define BLC_PWM_CTL 0x61254 */
798 #define MRST_BACKLIGHT_MODULATION_FREQ_SHIFT (16)
799 #define MRST_BACKLIGHT_MODULATION_FREQ_MASK (0xffff << 16)
801 /* #define PIPEACONF 0x70008 */
802 #define PIPEACONF_PIPE_STATE (1 << 30)
803 /* #define DSPACNTR 0x70180 */
805 #define MRST_DSPABASE 0x7019c
806 #define MRST_DSPBBASE 0x7119c
807 #define MDFLD_DSPCBASE 0x7219c
810 * Moorestown registers.
816 #define MIPIC_REG_OFFSET 0x800
818 #define DEVICE_READY_REG 0xb000
819 #define LP_OUTPUT_HOLD (1 << 16)
820 #define EXIT_ULPS_DEV_READY 0x3
821 #define LP_OUTPUT_HOLD_RELEASE 0x810000
822 # define ENTERING_ULPS (2 << 1)
823 # define EXITING_ULPS (1 << 1)
824 # define ULPS_MASK (3 << 1)
825 # define BUS_POSSESSION (1 << 3)
826 #define INTR_STAT_REG 0xb004
827 #define RX_SOT_ERROR (1 << 0)
828 #define RX_SOT_SYNC_ERROR (1 << 1)
829 #define RX_ESCAPE_MODE_ENTRY_ERROR (1 << 3)
830 #define RX_LP_TX_SYNC_ERROR (1 << 4)
831 #define RX_HS_RECEIVE_TIMEOUT_ERROR (1 << 5)
832 #define RX_FALSE_CONTROL_ERROR (1 << 6)
833 #define RX_ECC_SINGLE_BIT_ERROR (1 << 7)
834 #define RX_ECC_MULTI_BIT_ERROR (1 << 8)
835 #define RX_CHECKSUM_ERROR (1 << 9)
836 #define RX_DSI_DATA_TYPE_NOT_RECOGNIZED (1 << 10)
837 #define RX_DSI_VC_ID_INVALID (1 << 11)
838 #define TX_FALSE_CONTROL_ERROR (1 << 12)
839 #define TX_ECC_SINGLE_BIT_ERROR (1 << 13)
840 #define TX_ECC_MULTI_BIT_ERROR (1 << 14)
841 #define TX_CHECKSUM_ERROR (1 << 15)
842 #define TX_DSI_DATA_TYPE_NOT_RECOGNIZED (1 << 16)
843 #define TX_DSI_VC_ID_INVALID (1 << 17)
844 #define HIGH_CONTENTION (1 << 18)
845 #define LOW_CONTENTION (1 << 19)
846 #define DPI_FIFO_UNDER_RUN (1 << 20)
847 #define HS_TX_TIMEOUT (1 << 21)
848 #define LP_RX_TIMEOUT (1 << 22)
849 #define TURN_AROUND_ACK_TIMEOUT (1 << 23)
850 #define ACK_WITH_NO_ERROR (1 << 24)
851 #define HS_GENERIC_WR_FIFO_FULL (1 << 27)
852 #define LP_GENERIC_WR_FIFO_FULL (1 << 28)
853 #define SPL_PKT_SENT (1 << 30)
854 #define INTR_EN_REG 0xb008
855 #define DSI_FUNC_PRG_REG 0xb00c
856 #define DPI_CHANNEL_NUMBER_POS 0x03
857 #define DBI_CHANNEL_NUMBER_POS 0x05
858 #define FMT_DPI_POS 0x07
859 #define FMT_DBI_POS 0x0A
860 #define DBI_DATA_WIDTH_POS 0x0D
862 /* DPI PIXEL FORMATS */
863 #define RGB_565_FMT 0x01 /* RGB 565 FORMAT */
864 #define RGB_666_FMT 0x02 /* RGB 666 FORMAT */
865 #define LRGB_666_FMT 0x03 /* RGB LOOSELY PACKED
868 #define RGB_888_FMT 0x04 /* RGB 888 FORMAT */
869 #define VIRTUAL_CHANNEL_NUMBER_0 0x00 /* Virtual channel 0 */
870 #define VIRTUAL_CHANNEL_NUMBER_1 0x01 /* Virtual channel 1 */
871 #define VIRTUAL_CHANNEL_NUMBER_2 0x02 /* Virtual channel 2 */
872 #define VIRTUAL_CHANNEL_NUMBER_3 0x03 /* Virtual channel 3 */
874 #define DBI_NOT_SUPPORTED 0x00 /* command mode
877 #define DBI_DATA_WIDTH_16BIT 0x01 /* 16 bit data */
878 #define DBI_DATA_WIDTH_9BIT 0x02 /* 9 bit data */
879 #define DBI_DATA_WIDTH_8BIT 0x03 /* 8 bit data */
880 #define DBI_DATA_WIDTH_OPT1 0x04 /* option 1 */
881 #define DBI_DATA_WIDTH_OPT2 0x05 /* option 2 */
883 #define HS_TX_TIMEOUT_REG 0xb010
884 #define LP_RX_TIMEOUT_REG 0xb014
885 #define TURN_AROUND_TIMEOUT_REG 0xb018
886 #define DEVICE_RESET_REG 0xb01C
887 #define DPI_RESOLUTION_REG 0xb020
888 #define RES_V_POS 0x10
889 #define DBI_RESOLUTION_REG 0xb024 /* Reserved for MDFLD */
890 #define HORIZ_SYNC_PAD_COUNT_REG 0xb028
891 #define HORIZ_BACK_PORCH_COUNT_REG 0xb02C
892 #define HORIZ_FRONT_PORCH_COUNT_REG 0xb030
893 #define HORIZ_ACTIVE_AREA_COUNT_REG 0xb034
894 #define VERT_SYNC_PAD_COUNT_REG 0xb038
895 #define VERT_BACK_PORCH_COUNT_REG 0xb03c
896 #define VERT_FRONT_PORCH_COUNT_REG 0xb040
897 #define HIGH_LOW_SWITCH_COUNT_REG 0xb044
898 #define DPI_CONTROL_REG 0xb048
899 #define DPI_SHUT_DOWN (1 << 0)
900 #define DPI_TURN_ON (1 << 1)
901 #define DPI_COLOR_MODE_ON (1 << 2)
902 #define DPI_COLOR_MODE_OFF (1 << 3)
903 #define DPI_BACK_LIGHT_ON (1 << 4)
904 #define DPI_BACK_LIGHT_OFF (1 << 5)
905 #define DPI_LP (1 << 6)
906 #define DPI_DATA_REG 0xb04c
907 #define DPI_BACK_LIGHT_ON_DATA 0x07
908 #define DPI_BACK_LIGHT_OFF_DATA 0x17
909 #define INIT_COUNT_REG 0xb050
910 #define MAX_RET_PAK_REG 0xb054
911 #define VIDEO_FMT_REG 0xb058
912 #define COMPLETE_LAST_PCKT (1 << 2)
913 #define EOT_DISABLE_REG 0xb05c
914 #define ENABLE_CLOCK_STOPPING (1 << 1)
915 #define LP_BYTECLK_REG 0xb060
916 #define LP_GEN_DATA_REG 0xb064
917 #define HS_GEN_DATA_REG 0xb068
918 #define LP_GEN_CTRL_REG 0xb06C
919 #define HS_GEN_CTRL_REG 0xb070
920 #define DCS_CHANNEL_NUMBER_POS 0x6
921 #define MCS_COMMANDS_POS 0x8
922 #define WORD_COUNTS_POS 0x8
923 #define MCS_PARAMETER_POS 0x10
924 #define GEN_FIFO_STAT_REG 0xb074
925 #define HS_DATA_FIFO_FULL (1 << 0)
926 #define HS_DATA_FIFO_HALF_EMPTY (1 << 1)
927 #define HS_DATA_FIFO_EMPTY (1 << 2)
928 #define LP_DATA_FIFO_FULL (1 << 8)
929 #define LP_DATA_FIFO_HALF_EMPTY (1 << 9)
930 #define LP_DATA_FIFO_EMPTY (1 << 10)
931 #define HS_CTRL_FIFO_FULL (1 << 16)
932 #define HS_CTRL_FIFO_HALF_EMPTY (1 << 17)
933 #define HS_CTRL_FIFO_EMPTY (1 << 18)
934 #define LP_CTRL_FIFO_FULL (1 << 24)
935 #define LP_CTRL_FIFO_HALF_EMPTY (1 << 25)
936 #define LP_CTRL_FIFO_EMPTY (1 << 26)
937 #define DBI_FIFO_EMPTY (1 << 27)
938 #define DPI_FIFO_EMPTY (1 << 28)
939 #define HS_LS_DBI_ENABLE_REG 0xb078
940 #define TXCLKESC_REG 0xb07c
941 #define DPHY_PARAM_REG 0xb080
942 #define DBI_BW_CTRL_REG 0xb084
943 #define CLK_LANE_SWT_REG 0xb088
946 * MIPI Adapter registers
948 #define MIPI_CONTROL_REG 0xb104
949 #define MIPI_2X_CLOCK_BITS ((1 << 0) | (1 << 1))
950 #define MIPI_DATA_ADDRESS_REG 0xb108
951 #define MIPI_DATA_LENGTH_REG 0xb10C
952 #define MIPI_COMMAND_ADDRESS_REG 0xb110
953 #define MIPI_COMMAND_LENGTH_REG 0xb114
954 #define MIPI_READ_DATA_RETURN_REG0 0xb118
955 #define MIPI_READ_DATA_RETURN_REG1 0xb11C
956 #define MIPI_READ_DATA_RETURN_REG2 0xb120
957 #define MIPI_READ_DATA_RETURN_REG3 0xb124
958 #define MIPI_READ_DATA_RETURN_REG4 0xb128
959 #define MIPI_READ_DATA_RETURN_REG5 0xb12C
960 #define MIPI_READ_DATA_RETURN_REG6 0xb130
961 #define MIPI_READ_DATA_RETURN_REG7 0xb134
962 #define MIPI_READ_DATA_VALID_REG 0xb138
965 #define soft_reset 0x01
967 * The display module performs a software reset.
968 * Registers are written with their SW Reset default values.
970 #define get_power_mode 0x0a
972 * The display module returns the current power mode
974 #define get_address_mode 0x0b
976 * The display module returns the current status.
978 #define get_pixel_format 0x0c
980 * This command gets the pixel format for the RGB image data
981 * used by the interface.
983 #define get_display_mode 0x0d
985 * The display module returns the Display Image Mode status.
987 #define get_signal_mode 0x0e
989 * The display module returns the Display Signal Mode.
991 #define get_diagnostic_result 0x0f
993 * The display module returns the self-diagnostic results following
994 * a Sleep Out command.
996 #define enter_sleep_mode 0x10
998 * This command causes the display module to enter the Sleep mode.
999 * In this mode, all unnecessary blocks inside the display module are
1000 * disabled except interface communication. This is the lowest power
1001 * mode the display module supports.
1003 #define exit_sleep_mode 0x11
1005 * This command causes the display module to exit Sleep mode.
1006 * All blocks inside the display module are enabled.
1008 #define enter_partial_mode 0x12
1010 * This command causes the display module to enter the Partial Display
1011 * Mode. The Partial Display Mode window is described by the
1012 * set_partial_area command.
1014 #define enter_normal_mode 0x13
1016 * This command causes the display module to enter the Normal mode.
1017 * Normal Mode is defined as Partial Display mode and Scroll mode are off
1019 #define exit_invert_mode 0x20
1021 * This command causes the display module to stop inverting the image
1022 * data on the display device. The frame memory contents remain unchanged.
1023 * No status bits are changed.
1025 #define enter_invert_mode 0x21
1027 * This command causes the display module to invert the image data only on
1028 * the display device. The frame memory contents remain unchanged.
1029 * No status bits are changed.
1031 #define set_gamma_curve 0x26
1033 * This command selects the desired gamma curve for the display device.
1034 * Four fixed gamma curves are defined in section DCS spec.
1036 #define set_display_off 0x28
1037 /* ************************************************************************* *\
1038 This command causes the display module to stop displaying the image data
1039 on the display device. The frame memory contents remain unchanged.
1040 No status bits are changed.
1041 \* ************************************************************************* */
1042 #define set_display_on 0x29
1043 /* ************************************************************************* *\
1044 This command causes the display module to start displaying the image data
1045 on the display device. The frame memory contents remain unchanged.
1046 No status bits are changed.
1047 \* ************************************************************************* */
1048 #define set_column_address 0x2a
1050 * This command defines the column extent of the frame memory accessed by
1051 * the hostprocessor with the read_memory_continue and
1052 * write_memory_continue commands.
1053 * No status bits are changed.
1055 #define set_page_addr 0x2b
1057 * This command defines the page extent of the frame memory accessed by
1058 * the host processor with the write_memory_continue and
1059 * read_memory_continue command.
1060 * No status bits are changed.
1062 #define write_mem_start 0x2c
1064 * This command transfers image data from the host processor to the
1065 * display modules frame memory starting at the pixel location specified
1066 * by preceding set_column_address and set_page_address commands.
1068 #define set_partial_area 0x30
1070 * This command defines the Partial Display mode s display area.
1071 * There are two parameters associated with this command, the first
1072 * defines the Start Row (SR) and the second the End Row (ER). SR and ER
1073 * refer to the Frame Memory Line Pointer.
1075 #define set_scroll_area 0x33
1077 * This command defines the display modules Vertical Scrolling Area.
1079 #define set_tear_off 0x34
1081 * This command turns off the display modules Tearing Effect output
1082 * signal on the TE signal line.
1084 #define set_tear_on 0x35
1086 * This command turns on the display modules Tearing Effect output signal
1087 * on the TE signal line.
1089 #define set_address_mode 0x36
1091 * This command sets the data order for transfers from the host processor
1092 * to display modules frame memory,bits B[7:5] and B3, and from the
1093 * display modules frame memory to the display device, bits B[2:0] and B4.
1095 #define set_scroll_start 0x37
1097 * This command sets the start of the vertical scrolling area in the frame
1098 * memory. The vertical scrolling area is fully defined when this command
1099 * is used with the set_scroll_area command The set_scroll_start command
1100 * has one parameter, the Vertical Scroll Pointer. The VSP defines the
1101 * line in the frame memory that is written to the display device as the
1102 * first line of the vertical scroll area.
1104 #define exit_idle_mode 0x38
1106 * This command causes the display module to exit Idle mode.
1108 #define enter_idle_mode 0x39
1110 * This command causes the display module to enter Idle Mode.
1111 * In Idle Mode, color expression is reduced. Colors are shown on the
1112 * display device using the MSB of each of the R, G and B color
1113 * components in the frame memory
1115 #define set_pixel_format 0x3a
1117 * This command sets the pixel format for the RGB image data used by the
1119 * Bits D[6:4] DPI Pixel Format Definition
1120 * Bits D[2:0] DBI Pixel Format Definition
1121 * Bits D7 and D3 are not used.
1123 #define DCS_PIXEL_FORMAT_3bpp 0x1
1124 #define DCS_PIXEL_FORMAT_8bpp 0x2
1125 #define DCS_PIXEL_FORMAT_12bpp 0x3
1126 #define DCS_PIXEL_FORMAT_16bpp 0x5
1127 #define DCS_PIXEL_FORMAT_18bpp 0x6
1128 #define DCS_PIXEL_FORMAT_24bpp 0x7
1130 #define write_mem_cont 0x3c
1133 * This command transfers image data from the host processor to the
1134 * display module's frame memory continuing from the pixel location
1135 * following the previous write_memory_continue or write_memory_start
1138 #define set_tear_scanline 0x44
1140 * This command turns on the display modules Tearing Effect output signal
1141 * on the TE signal line when the display module reaches line N.
1143 #define get_scanline 0x45
1145 * The display module returns the current scanline, N, used to update the
1146 * display device. The total number of scanlines on a display device is
1147 * defined as VSYNC + VBP + VACT + VFP.The first scanline is defined as
1148 * the first line of V Sync and is denoted as Line 0.
1149 * When in Sleep Mode, the value returned by get_scanline is undefined.
1152 /* MCS or Generic COMMANDS */
1153 /* MCS/generic data type */
1154 #define GEN_SHORT_WRITE_0 0x03 /* generic short write, no parameters */
1155 #define GEN_SHORT_WRITE_1 0x13 /* generic short write, 1 parameters */
1156 #define GEN_SHORT_WRITE_2 0x23 /* generic short write, 2 parameters */
1157 #define GEN_READ_0 0x04 /* generic read, no parameters */
1158 #define GEN_READ_1 0x14 /* generic read, 1 parameters */
1159 #define GEN_READ_2 0x24 /* generic read, 2 parameters */
1160 #define GEN_LONG_WRITE 0x29 /* generic long write */
1161 #define MCS_SHORT_WRITE_0 0x05 /* MCS short write, no parameters */
1162 #define MCS_SHORT_WRITE_1 0x15 /* MCS short write, 1 parameters */
1163 #define MCS_READ 0x06 /* MCS read, no parameters */
1164 #define MCS_LONG_WRITE 0x39 /* MCS long write */
1165 /* MCS/generic commands */
1167 #define write_display_profile 0x50
1168 #define write_display_brightness 0x51
1169 #define write_ctrl_display 0x53
1170 #define write_ctrl_cabc 0x55
1171 #define UI_IMAGE 0x01
1172 #define STILL_IMAGE 0x02
1173 #define MOVING_IMAGE 0x03
1174 #define write_hysteresis 0x57
1175 #define write_gamma_setting 0x58
1176 #define write_cabc_min_bright 0x5e
1177 #define write_kbbc_profile 0x60
1179 #define tmd_write_display_brightness 0x8c
1182 * This command is used to control ambient light, panel backlight
1183 * brightness and gamma settings.
1185 #define BRIGHT_CNTL_BLOCK_ON (1 << 5)
1186 #define AMBIENT_LIGHT_SENSE_ON (1 << 4)
1187 #define DISPLAY_DIMMING_ON (1 << 3)
1188 #define BACKLIGHT_ON (1 << 2)
1189 #define DISPLAY_BRIGHTNESS_AUTO (1 << 1)
1190 #define GAMMA_AUTO (1 << 0)
1192 /* DCS Interface Pixel Formats */
1193 #define DCS_PIXEL_FORMAT_3BPP 0x1
1194 #define DCS_PIXEL_FORMAT_8BPP 0x2
1195 #define DCS_PIXEL_FORMAT_12BPP 0x3
1196 #define DCS_PIXEL_FORMAT_16BPP 0x5
1197 #define DCS_PIXEL_FORMAT_18BPP 0x6
1198 #define DCS_PIXEL_FORMAT_24BPP 0x7
1199 /* ONE PARAMETER READ DATA */
1200 #define addr_mode_data 0xfc
1201 #define diag_res_data 0x00
1202 #define disp_mode_data 0x23
1203 #define pxl_fmt_data 0x77
1204 #define pwr_mode_data 0x74
1205 #define sig_mode_data 0x00
1206 /* TWO PARAMETERS READ DATA */
1207 #define scanline_data1 0xff
1208 #define scanline_data2 0xff
1209 #define NON_BURST_MODE_SYNC_PULSE 0x01 /* Non Burst Mode
1212 #define NON_BURST_MODE_SYNC_EVENTS 0x02 /* Non Burst Mode
1215 #define BURST_MODE 0x03 /* Burst Mode */
1216 #define DBI_COMMAND_BUFFER_SIZE 0x240 /* 0x32 */ /* 0x120 */
1217 /* Allocate at least
1218 * 0x100 Byte with 32
1221 #define DBI_DATA_BUFFER_SIZE 0x120 /* Allocate at least
1222 * 0x100 Byte with 32
1225 #define DBI_CB_TIME_OUT 0xFFFF
1227 #define GEN_FB_TIME_OUT 2000
1230 #define SKU_100 0x02
1231 #define SKU_100L 0x04
1232 #define SKU_BYPASS 0x08
1234 /* Some handy macros for playing with bitfields. */
1235 #define PSB_MASK(high, low) (((1<<((high)-(low)+1))-1)<<(low))
1236 #define SET_FIELD(value, field) (((value) << field ## _SHIFT) & field ## _MASK)
1237 #define GET_FIELD(word, field) (((word) & field ## _MASK) >> field ## _SHIFT)
1239 #define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
1241 /* PCI config space */
1243 #define SB_PCKT 0x02100 /* cedarview */
1244 # define SB_OPCODE_MASK PSB_MASK(31, 16)
1245 # define SB_OPCODE_SHIFT 16
1246 # define SB_OPCODE_READ 0
1247 # define SB_OPCODE_WRITE 1
1248 # define SB_DEST_MASK PSB_MASK(15, 8)
1249 # define SB_DEST_SHIFT 8
1250 # define SB_DEST_DPLL 0x88
1251 # define SB_BYTE_ENABLE_MASK PSB_MASK(7, 4)
1252 # define SB_BYTE_ENABLE_SHIFT 4
1253 # define SB_BUSY (1 << 0)
1256 /* 32-bit value read/written from the DPIO reg. */
1257 #define SB_DATA 0x02104 /* cedarview */
1258 /* 32-bit address of the DPIO reg to be read/written. */
1259 #define SB_ADDR 0x02108 /* cedarview */
1260 #define DPIO_CFG 0x02110 /* cedarview */
1261 # define DPIO_MODE_SELECT_1 (1 << 3)
1262 # define DPIO_MODE_SELECT_0 (1 << 2)
1263 # define DPIO_SFR_BYPASS (1 << 1)
1264 /* reset is active low */
1265 # define DPIO_CMN_RESET_N (1 << 0)
1267 /* Cedarview sideband registers */
1268 #define _SB_M_A 0x8008
1269 #define _SB_M_B 0x8028
1270 #define SB_M(pipe) _PIPE(pipe, _SB_M_A, _SB_M_B)
1271 # define SB_M_DIVIDER_MASK (0xFF << 24)
1272 # define SB_M_DIVIDER_SHIFT 24
1274 #define _SB_N_VCO_A 0x8014
1275 #define _SB_N_VCO_B 0x8034
1276 #define SB_N_VCO(pipe) _PIPE(pipe, _SB_N_VCO_A, _SB_N_VCO_B)
1277 #define SB_N_VCO_SEL_MASK PSB_MASK(31, 30)
1278 #define SB_N_VCO_SEL_SHIFT 30
1279 #define SB_N_DIVIDER_MASK PSB_MASK(29, 26)
1280 #define SB_N_DIVIDER_SHIFT 26
1281 #define SB_N_CB_TUNE_MASK PSB_MASK(25, 24)
1282 #define SB_N_CB_TUNE_SHIFT 24
1284 #define _SB_REF_A 0x8018
1285 #define _SB_REF_B 0x8038
1286 #define SB_REF_SFR(pipe) _PIPE(pipe, _SB_REF_A, _SB_REF_B)
1288 #define _SB_P_A 0x801c
1289 #define _SB_P_B 0x803c
1290 #define SB_P(pipe) _PIPE(pipe, _SB_P_A, _SB_P_B)
1291 #define SB_P2_DIVIDER_MASK PSB_MASK(31, 30)
1292 #define SB_P2_DIVIDER_SHIFT 30
1293 #define SB_P2_10 0 /* HDMI, DP, DAC */
1294 #define SB_P2_5 1 /* DAC */
1295 #define SB_P2_14 2 /* LVDS single */
1296 #define SB_P2_7 3 /* LVDS double */
1297 #define SB_P1_DIVIDER_MASK PSB_MASK(15, 12)
1298 #define SB_P1_DIVIDER_SHIFT 12
1300 #define PSB_LANE0 0x120
1301 #define PSB_LANE1 0x220
1302 #define PSB_LANE2 0x2320
1303 #define PSB_LANE3 0x2420
1305 #define LANE_PLL_MASK (0x7 << 20)
1306 #define LANE_PLL_ENABLE (0x3 << 20)