2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Kevin Tian <kevin.tian@intel.com>
25 * Eddie Dong <eddie.dong@intel.com>
28 * Niu Bing <bing.niu@intel.com>
29 * Zhi Wang <zhi.a.wang@intel.com>
37 #include "hypercall.h"
40 #define GVT_MAX_VGPU 8
43 INTEL_GVT_HYPERVISOR_XEN = 0,
44 INTEL_GVT_HYPERVISOR_KVM,
47 struct intel_gvt_host {
50 struct intel_gvt_mpt *mpt;
53 extern struct intel_gvt_host intel_gvt_host;
55 /* Describe per-platform limitations. */
56 struct intel_gvt_device_info {
57 u32 max_support_vgpus;
63 /* GM resources owned by a vGPU */
64 struct intel_vgpu_gm {
67 struct drm_mm_node low_gm_node;
68 struct drm_mm_node high_gm_node;
71 #define INTEL_GVT_MAX_NUM_FENCES 32
73 /* Fences owned by a vGPU */
74 struct intel_vgpu_fence {
75 struct drm_i915_fence_reg *regs[INTEL_GVT_MAX_NUM_FENCES];
81 struct intel_gvt *gvt;
83 unsigned long handle; /* vGPU handle used by hypervisor MPT modules */
85 struct intel_vgpu_fence fence;
86 struct intel_vgpu_gm gm;
90 unsigned long vgpu_allocated_low_gm_size;
91 unsigned long vgpu_allocated_high_gm_size;
94 struct intel_gvt_fence {
95 unsigned long vgpu_allocated_fence_num;
98 #define INTEL_GVT_MMIO_HASH_BITS 9
100 struct intel_gvt_mmio {
102 DECLARE_HASHTABLE(mmio_info_table, INTEL_GVT_MMIO_HASH_BITS);
105 struct intel_gvt_firmware {
108 bool firmware_loaded;
115 struct drm_i915_private *dev_priv;
116 struct idr vgpu_idr; /* vGPU IDR pool */
118 struct intel_gvt_device_info device_info;
119 struct intel_gvt_gm gm;
120 struct intel_gvt_fence fence;
121 struct intel_gvt_mmio mmio;
122 struct intel_gvt_firmware firmware;
125 void intel_gvt_free_firmware(struct intel_gvt *gvt);
126 int intel_gvt_load_firmware(struct intel_gvt *gvt);
128 /* Aperture/GM space definitions for GVT device */
129 #define gvt_aperture_sz(gvt) (gvt->dev_priv->ggtt.mappable_end)
130 #define gvt_aperture_pa_base(gvt) (gvt->dev_priv->ggtt.mappable_base)
132 #define gvt_ggtt_gm_sz(gvt) (gvt->dev_priv->ggtt.base.total)
133 #define gvt_hidden_sz(gvt) (gvt_ggtt_gm_sz(gvt) - gvt_aperture_sz(gvt))
135 #define gvt_aperture_gmadr_base(gvt) (0)
136 #define gvt_aperture_gmadr_end(gvt) (gvt_aperture_gmadr_base(gvt) \
137 + gvt_aperture_sz(gvt) - 1)
139 #define gvt_hidden_gmadr_base(gvt) (gvt_aperture_gmadr_base(gvt) \
140 + gvt_aperture_sz(gvt))
141 #define gvt_hidden_gmadr_end(gvt) (gvt_hidden_gmadr_base(gvt) \
142 + gvt_hidden_sz(gvt) - 1)
144 #define gvt_fence_sz(gvt) (gvt->dev_priv->num_fence_regs)
146 /* Aperture/GM space definitions for vGPU */
147 #define vgpu_aperture_offset(vgpu) ((vgpu)->gm.low_gm_node.start)
148 #define vgpu_hidden_offset(vgpu) ((vgpu)->gm.high_gm_node.start)
149 #define vgpu_aperture_sz(vgpu) ((vgpu)->gm.aperture_sz)
150 #define vgpu_hidden_sz(vgpu) ((vgpu)->gm.hidden_sz)
152 #define vgpu_aperture_pa_base(vgpu) \
153 (gvt_aperture_pa_base(vgpu->gvt) + vgpu_aperture_offset(vgpu))
155 #define vgpu_ggtt_gm_sz(vgpu) ((vgpu)->gm.aperture_sz + (vgpu)->gm.hidden_sz)
157 #define vgpu_aperture_pa_end(vgpu) \
158 (vgpu_aperture_pa_base(vgpu) + vgpu_aperture_sz(vgpu) - 1)
160 #define vgpu_aperture_gmadr_base(vgpu) (vgpu_aperture_offset(vgpu))
161 #define vgpu_aperture_gmadr_end(vgpu) \
162 (vgpu_aperture_gmadr_base(vgpu) + vgpu_aperture_sz(vgpu) - 1)
164 #define vgpu_hidden_gmadr_base(vgpu) (vgpu_hidden_offset(vgpu))
165 #define vgpu_hidden_gmadr_end(vgpu) \
166 (vgpu_hidden_gmadr_base(vgpu) + vgpu_hidden_sz(vgpu) - 1)
168 #define vgpu_fence_base(vgpu) (vgpu->fence.base)
169 #define vgpu_fence_sz(vgpu) (vgpu->fence.size)
171 struct intel_vgpu_creation_params {
173 __u64 low_gm_sz; /* in MB */
174 __u64 high_gm_sz; /* in MB */
180 int intel_vgpu_alloc_resource(struct intel_vgpu *vgpu,
181 struct intel_vgpu_creation_params *param);
182 void intel_vgpu_free_resource(struct intel_vgpu *vgpu);
183 void intel_vgpu_write_fence(struct intel_vgpu *vgpu,
184 u32 fence, u64 value);