drivers/gpu/drm/i915/gvt/scheduler.c

   1 /*
   2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Zhi Wang <zhi.a.wang@intel.com>
  25  *
  26  * Contributors:
  27  *    Ping Gao <ping.a.gao@intel.com>
  28  *    Tina Zhang <tina.zhang@intel.com>
  29  *    Chanbin Du <changbin.du@intel.com>
  30  *    Min He <min.he@intel.com>
  31  *    Bing Niu <bing.niu@intel.com>
  32  *    Zhenyu Wang <zhenyuw@linux.intel.com>
  33  *
  34  */
  35
  36 #include <linux/kthread.h>
  37
  38 #include "i915_drv.h"
  39 #include "gvt.h"
  40
  41 #define RING_CTX_OFF(x) \
  42         offsetof(struct execlist_ring_context, x)
  43
  44 static void set_context_pdp_root_pointer(
  45                 struct execlist_ring_context *ring_context,
  46                 u32 pdp[8])
  47 {
  48         struct execlist_mmio_pair *pdp_pair = &ring_context->pdp3_UDW;
  49         int i;
  50
  51         for (i = 0; i < 8; i++)
  52                 pdp_pair[i].val = pdp[7 - i];
  53 }
  54
  55 static int populate_shadow_context(struct intel_vgpu_workload *workload)
  56 {
  57         struct intel_vgpu *vgpu = workload->vgpu;
  58         struct intel_gvt *gvt = vgpu->gvt;
  59         int ring_id = workload->ring_id;
  60         struct i915_gem_context *shadow_ctx = workload->vgpu->shadow_ctx;
  61         struct drm_i915_gem_object *ctx_obj =
  62                 shadow_ctx->engine[ring_id].state->obj;
  63         struct execlist_ring_context *shadow_ring_context;
  64         struct page *page;
  65         void *dst;
  66         unsigned long context_gpa, context_page_num;
  67         int i;
  68
  69         gvt_dbg_sched("ring id %d workload lrca %x", ring_id,
  70                         workload->ctx_desc.lrca);
  71
  72         context_page_num = intel_lr_context_size(
  73                         gvt->dev_priv->engine[ring_id]);
  74
  75         context_page_num = context_page_num >> PAGE_SHIFT;
  76
  77         if (IS_BROADWELL(gvt->dev_priv) && ring_id == RCS)
  78                 context_page_num = 19;
  79
  80         i = 2;
  81
  82         while (i < context_page_num) {
  83                 context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
  84                                 (u32)((workload->ctx_desc.lrca + i) <<
  85                                 GTT_PAGE_SHIFT));
  86                 if (context_gpa == INTEL_GVT_INVALID_ADDR) {
  87                         gvt_err("Invalid guest context descriptor\n");
  88                         return -EINVAL;
  89                 }
  90
  91                 page = i915_gem_object_get_page(ctx_obj, LRC_PPHWSP_PN + i);
  92                 dst = kmap(page);
  93                 intel_gvt_hypervisor_read_gpa(vgpu, context_gpa, dst,
  94                                 GTT_PAGE_SIZE);
  95                 kunmap(page);
  96                 i++;
  97         }
  98
  99         page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
 100         shadow_ring_context = kmap(page);
 101
 102 #define COPY_REG(name) \
 103         intel_gvt_hypervisor_read_gpa(vgpu, workload->ring_context_gpa \
 104                 + RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4)
 105
 106         COPY_REG(ctx_ctrl);
 107         COPY_REG(ctx_timestamp);
 108
 109         if (ring_id == RCS) {
 110                 COPY_REG(bb_per_ctx_ptr);
 111                 COPY_REG(rcs_indirect_ctx);
 112                 COPY_REG(rcs_indirect_ctx_offset);
 113         }
 114 #undef COPY_REG
 115
 116         set_context_pdp_root_pointer(shadow_ring_context,
 117                                      workload->shadow_mm->shadow_page_table);
 118
 119         intel_gvt_hypervisor_read_gpa(vgpu,
 120                         workload->ring_context_gpa +
 121                         sizeof(*shadow_ring_context),
 122                         (void *)shadow_ring_context +
 123                         sizeof(*shadow_ring_context),
 124                         GTT_PAGE_SIZE - sizeof(*shadow_ring_context));
 125
 126         kunmap(page);
 127         return 0;
 128 }
 129
 130 static int shadow_context_status_change(struct notifier_block *nb,
 131                 unsigned long action, void *data)
 132 {
 133         struct drm_i915_gem_request *req = (struct drm_i915_gem_request *)data;
 134         struct intel_gvt *gvt = container_of(nb, struct intel_gvt,
 135                                 shadow_ctx_notifier_block[req->engine->id]);
 136         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
 137         struct intel_vgpu_workload *workload =
 138                 scheduler->current_workload[req->engine->id];
 139
 140         if (unlikely(!workload))
 141                 return NOTIFY_OK;
 142
 143         switch (action) {
 144         case INTEL_CONTEXT_SCHEDULE_IN:
 145                 intel_gvt_load_render_mmio(workload->vgpu,
 146                                            workload->ring_id);
 147                 atomic_set(&workload->shadow_ctx_active, 1);
 148                 break;
 149         case INTEL_CONTEXT_SCHEDULE_OUT:
 150                 intel_gvt_restore_render_mmio(workload->vgpu,
 151                                               workload->ring_id);
 152                 /* If the status is -EINPROGRESS means this workload
 153                  * doesn't meet any issue during dispatching so when
 154                  * get the SCHEDULE_OUT set the status to be zero for
 155                  * good. If the status is NOT -EINPROGRESS means there
 156                  * is something wrong happened during dispatching and
 157                  * the status should not be set to zero
 158                  */
 159                 if (workload->status == -EINPROGRESS)
 160                         workload->status = 0;
 161                 atomic_set(&workload->shadow_ctx_active, 0);
 162                 break;
 163         default:
 164                 WARN_ON(1);
 165                 return NOTIFY_OK;
 166         }
 167         wake_up(&workload->shadow_ctx_status_wq);
 168         return NOTIFY_OK;
 169 }
 170
 171 static int dispatch_workload(struct intel_vgpu_workload *workload)
 172 {
 173         int ring_id = workload->ring_id;
 174         struct i915_gem_context *shadow_ctx = workload->vgpu->shadow_ctx;
 175         struct drm_i915_private *dev_priv = workload->vgpu->gvt->dev_priv;
 176         struct drm_i915_gem_request *rq;
 177         int ret;
 178
 179         gvt_dbg_sched("ring id %d prepare to dispatch workload %p\n",
 180                 ring_id, workload);
 181
 182         shadow_ctx->desc_template &= ~(0x3 << GEN8_CTX_ADDRESSING_MODE_SHIFT);
 183         shadow_ctx->desc_template |= workload->ctx_desc.addressing_mode <<
 184                                     GEN8_CTX_ADDRESSING_MODE_SHIFT;
 185
 186         mutex_lock(&dev_priv->drm.struct_mutex);
 187
 188         rq = i915_gem_request_alloc(dev_priv->engine[ring_id], shadow_ctx);
 189         if (IS_ERR(rq)) {
 190                 gvt_err("fail to allocate gem request\n");
 191                 ret = PTR_ERR(rq);
 192                 goto out;
 193         }
 194
 195         gvt_dbg_sched("ring id %d get i915 gem request %p\n", ring_id, rq);
 196
 197         workload->req = i915_gem_request_get(rq);
 198
 199         ret = intel_gvt_scan_and_shadow_workload(workload);
 200         if (ret)
 201                 goto out;
 202
 203         ret = intel_gvt_scan_and_shadow_wa_ctx(&workload->wa_ctx);
 204         if (ret)
 205                 goto out;
 206
 207         ret = populate_shadow_context(workload);
 208         if (ret)
 209                 goto out;
 210
 211         if (workload->prepare) {
 212                 ret = workload->prepare(workload);
 213                 if (ret)
 214                         goto out;
 215         }
 216
 217         gvt_dbg_sched("ring id %d submit workload to i915 %p\n",
 218                         ring_id, workload->req);
 219
 220         ret = 0;
 221         workload->dispatched = true;
 222 out:
 223         if (ret)
 224                 workload->status = ret;
 225
 226         if (!IS_ERR_OR_NULL(rq))
 227                 i915_add_request(rq);
 228         mutex_unlock(&dev_priv->drm.struct_mutex);
 229         return ret;
 230 }
 231
 232 static struct intel_vgpu_workload *pick_next_workload(
 233                 struct intel_gvt *gvt, int ring_id)
 234 {
 235         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
 236         struct intel_vgpu_workload *workload = NULL;
 237
 238         mutex_lock(&gvt->lock);
 239
 240         /*
 241          * no current vgpu / will be scheduled out / no workload
 242          * bail out
 243          */
 244         if (!scheduler->current_vgpu) {
 245                 gvt_dbg_sched("ring id %d stop - no current vgpu\n", ring_id);
 246                 goto out;
 247         }
 248
 249         if (scheduler->need_reschedule) {
 250                 gvt_dbg_sched("ring id %d stop - will reschedule\n", ring_id);
 251                 goto out;
 252         }
 253
 254         if (list_empty(workload_q_head(scheduler->current_vgpu, ring_id))) {
 255                 gvt_dbg_sched("ring id %d stop - no available workload\n",
 256                                 ring_id);
 257                 goto out;
 258         }
 259
 260         /*
 261          * still have current workload, maybe the workload disptacher
 262          * fail to submit it for some reason, resubmit it.
 263          */
 264         if (scheduler->current_workload[ring_id]) {
 265                 workload = scheduler->current_workload[ring_id];
 266                 gvt_dbg_sched("ring id %d still have current workload %p\n",
 267                                 ring_id, workload);
 268                 goto out;
 269         }
 270
 271         /*
 272          * pick a workload as current workload
 273          * once current workload is set, schedule policy routines
 274          * will wait the current workload is finished when trying to
 275          * schedule out a vgpu.
 276          */
 277         scheduler->current_workload[ring_id] = container_of(
 278                         workload_q_head(scheduler->current_vgpu, ring_id)->next,
 279                         struct intel_vgpu_workload, list);
 280
 281         workload = scheduler->current_workload[ring_id];
 282
 283         gvt_dbg_sched("ring id %d pick new workload %p\n", ring_id, workload);
 284
 285         atomic_inc(&workload->vgpu->running_workload_num);
 286 out:
 287         mutex_unlock(&gvt->lock);
 288         return workload;
 289 }
 290
 291 static void update_guest_context(struct intel_vgpu_workload *workload)
 292 {
 293         struct intel_vgpu *vgpu = workload->vgpu;
 294         struct intel_gvt *gvt = vgpu->gvt;
 295         int ring_id = workload->ring_id;
 296         struct i915_gem_context *shadow_ctx = workload->vgpu->shadow_ctx;
 297         struct drm_i915_gem_object *ctx_obj =
 298                 shadow_ctx->engine[ring_id].state->obj;
 299         struct execlist_ring_context *shadow_ring_context;
 300         struct page *page;
 301         void *src;
 302         unsigned long context_gpa, context_page_num;
 303         int i;
 304
 305         gvt_dbg_sched("ring id %d workload lrca %x\n", ring_id,
 306                         workload->ctx_desc.lrca);
 307
 308         context_page_num = intel_lr_context_size(
 309                         gvt->dev_priv->engine[ring_id]);
 310
 311         context_page_num = context_page_num >> PAGE_SHIFT;
 312
 313         if (IS_BROADWELL(gvt->dev_priv) && ring_id == RCS)
 314                 context_page_num = 19;
 315
 316         i = 2;
 317
 318         while (i < context_page_num) {
 319                 context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
 320                                 (u32)((workload->ctx_desc.lrca + i) <<
 321                                         GTT_PAGE_SHIFT));
 322                 if (context_gpa == INTEL_GVT_INVALID_ADDR) {
 323                         gvt_err("invalid guest context descriptor\n");
 324                         return;
 325                 }
 326
 327                 page = i915_gem_object_get_page(ctx_obj, LRC_PPHWSP_PN + i);
 328                 src = kmap(page);
 329                 intel_gvt_hypervisor_write_gpa(vgpu, context_gpa, src,
 330                                 GTT_PAGE_SIZE);
 331                 kunmap(page);
 332                 i++;
 333         }
 334
 335         intel_gvt_hypervisor_write_gpa(vgpu, workload->ring_context_gpa +
 336                 RING_CTX_OFF(ring_header.val), &workload->rb_tail, 4);
 337
 338         page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
 339         shadow_ring_context = kmap(page);
 340
 341 #define COPY_REG(name) \
 342         intel_gvt_hypervisor_write_gpa(vgpu, workload->ring_context_gpa + \
 343                 RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4)
 344
 345         COPY_REG(ctx_ctrl);
 346         COPY_REG(ctx_timestamp);
 347
 348 #undef COPY_REG
 349
 350         intel_gvt_hypervisor_write_gpa(vgpu,
 351                         workload->ring_context_gpa +
 352                         sizeof(*shadow_ring_context),
 353                         (void *)shadow_ring_context +
 354                         sizeof(*shadow_ring_context),
 355                         GTT_PAGE_SIZE - sizeof(*shadow_ring_context));
 356
 357         kunmap(page);
 358 }
 359
 360 static void complete_current_workload(struct intel_gvt *gvt, int ring_id)
 361 {
 362         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
 363         struct intel_vgpu_workload *workload;
 364         struct intel_vgpu *vgpu;
 365         int event;
 366
 367         mutex_lock(&gvt->lock);
 368
 369         workload = scheduler->current_workload[ring_id];
 370         vgpu = workload->vgpu;
 371
 372         /* For the workload w/ request, needs to wait for the context
 373          * switch to make sure request is completed.
 374          * For the workload w/o request, directly complete the workload.
 375          */
 376         if (workload->req) {
 377                 wait_event(workload->shadow_ctx_status_wq,
 378                            !atomic_read(&workload->shadow_ctx_active));
 379
 380                 i915_gem_request_put(fetch_and_zero(&workload->req));
 381
 382                 if (!workload->status && !vgpu->resetting) {
 383                         update_guest_context(workload);
 384
 385                         for_each_set_bit(event, workload->pending_events,
 386                                          INTEL_GVT_EVENT_MAX)
 387                                 intel_vgpu_trigger_virtual_event(vgpu, event);
 388                 }
 389         }
 390
 391         gvt_dbg_sched("ring id %d complete workload %p status %d\n",
 392                         ring_id, workload, workload->status);
 393
 394         scheduler->current_workload[ring_id] = NULL;
 395
 396         list_del_init(&workload->list);
 397         workload->complete(workload);
 398
 399         atomic_dec(&vgpu->running_workload_num);
 400         wake_up(&scheduler->workload_complete_wq);
 401         mutex_unlock(&gvt->lock);
 402 }
 403
 404 struct workload_thread_param {
 405         struct intel_gvt *gvt;
 406         int ring_id;
 407 };
 408
 409 static DEFINE_MUTEX(scheduler_mutex);
 410
 411 static int workload_thread(void *priv)
 412 {
 413         struct workload_thread_param *p = (struct workload_thread_param *)priv;
 414         struct intel_gvt *gvt = p->gvt;
 415         int ring_id = p->ring_id;
 416         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
 417         struct intel_vgpu_workload *workload = NULL;
 418         int ret;
 419         bool need_force_wake = IS_SKYLAKE(gvt->dev_priv);
 420         DEFINE_WAIT_FUNC(wait, woken_wake_function);
 421
 422         kfree(p);
 423
 424         gvt_dbg_core("workload thread for ring %d started\n", ring_id);
 425
 426         while (!kthread_should_stop()) {
 427                 add_wait_queue(&scheduler->waitq[ring_id], &wait);
 428                 do {
 429                         workload = pick_next_workload(gvt, ring_id);
 430                         if (workload)
 431                                 break;
 432                         wait_woken(&wait, TASK_INTERRUPTIBLE,
 433                                    MAX_SCHEDULE_TIMEOUT);
 434                 } while (!kthread_should_stop());
 435                 remove_wait_queue(&scheduler->waitq[ring_id], &wait);
 436
 437                 if (!workload)
 438                         break;
 439
 440                 mutex_lock(&scheduler_mutex);
 441
 442                 gvt_dbg_sched("ring id %d next workload %p vgpu %d\n",
 443                                 workload->ring_id, workload,
 444                                 workload->vgpu->id);
 445
 446                 intel_runtime_pm_get(gvt->dev_priv);
 447
 448                 gvt_dbg_sched("ring id %d will dispatch workload %p\n",
 449                                 workload->ring_id, workload);
 450
 451                 if (need_force_wake)
 452                         intel_uncore_forcewake_get(gvt->dev_priv,
 453                                         FORCEWAKE_ALL);
 454
 455                 mutex_lock(&gvt->lock);
 456                 ret = dispatch_workload(workload);
 457                 mutex_unlock(&gvt->lock);
 458
 459                 if (ret) {
 460                         gvt_err("fail to dispatch workload, skip\n");
 461                         goto complete;
 462                 }
 463
 464                 gvt_dbg_sched("ring id %d wait workload %p\n",
 465                                 workload->ring_id, workload);
 466 retry:
 467                 i915_wait_request(workload->req,
 468                                          0, MAX_SCHEDULE_TIMEOUT);
 469                 /* I915 has replay mechanism and a request will be replayed
 470                  * if there is i915 reset. So the seqno will be updated anyway.
 471                  * If the seqno is not updated yet after waiting, which means
 472                  * the replay may still be in progress and we can wait again.
 473                  */
 474                 if (!i915_gem_request_completed(workload->req)) {
 475                         gvt_dbg_sched("workload %p not completed, wait again\n",
 476                                         workload);
 477                         goto retry;
 478                 }
 479
 480 complete:
 481                 gvt_dbg_sched("will complete workload %p, status: %d\n",
 482                                 workload, workload->status);
 483
 484                 complete_current_workload(gvt, ring_id);
 485
 486                 if (need_force_wake)
 487                         intel_uncore_forcewake_put(gvt->dev_priv,
 488                                         FORCEWAKE_ALL);
 489
 490                 intel_runtime_pm_put(gvt->dev_priv);
 491
 492                 mutex_unlock(&scheduler_mutex);
 493
 494         }
 495         return 0;
 496 }
 497
 498 void intel_gvt_wait_vgpu_idle(struct intel_vgpu *vgpu)
 499 {
 500         struct intel_gvt *gvt = vgpu->gvt;
 501         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
 502
 503         if (atomic_read(&vgpu->running_workload_num)) {
 504                 gvt_dbg_sched("wait vgpu idle\n");
 505
 506                 wait_event(scheduler->workload_complete_wq,
 507                                 !atomic_read(&vgpu->running_workload_num));
 508         }
 509 }
 510
 511 void intel_gvt_clean_workload_scheduler(struct intel_gvt *gvt)
 512 {
 513         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
 514         struct intel_engine_cs *engine;
 515         enum intel_engine_id i;
 516
 517         gvt_dbg_core("clean workload scheduler\n");
 518
 519         for_each_engine(engine, gvt->dev_priv, i) {
 520                 atomic_notifier_chain_unregister(
 521                                         &engine->context_status_notifier,
 522                                         &gvt->shadow_ctx_notifier_block[i]);
 523                 kthread_stop(scheduler->thread[i]);
 524         }
 525 }
 526
 527 int intel_gvt_init_workload_scheduler(struct intel_gvt *gvt)
 528 {
 529         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
 530         struct workload_thread_param *param = NULL;
 531         struct intel_engine_cs *engine;
 532         enum intel_engine_id i;
 533         int ret;
 534
 535         gvt_dbg_core("init workload scheduler\n");
 536
 537         init_waitqueue_head(&scheduler->workload_complete_wq);
 538
 539         for_each_engine(engine, gvt->dev_priv, i) {
 540                 init_waitqueue_head(&scheduler->waitq[i]);
 541
 542                 param = kzalloc(sizeof(*param), GFP_KERNEL);
 543                 if (!param) {
 544                         ret = -ENOMEM;
 545                         goto err;
 546                 }
 547
 548                 param->gvt = gvt;
 549                 param->ring_id = i;
 550
 551                 scheduler->thread[i] = kthread_run(workload_thread, param,
 552                         "gvt workload %d", i);
 553                 if (IS_ERR(scheduler->thread[i])) {
 554                         gvt_err("fail to create workload thread\n");
 555                         ret = PTR_ERR(scheduler->thread[i]);
 556                         goto err;
 557                 }
 558
 559                 gvt->shadow_ctx_notifier_block[i].notifier_call =
 560                                         shadow_context_status_change;
 561                 atomic_notifier_chain_register(&engine->context_status_notifier,
 562                                         &gvt->shadow_ctx_notifier_block[i]);
 563         }
 564         return 0;
 565 err:
 566         intel_gvt_clean_workload_scheduler(gvt);
 567         kfree(param);
 568         param = NULL;
 569         return ret;
 570 }
 571
 572 void intel_vgpu_clean_gvt_context(struct intel_vgpu *vgpu)
 573 {
 574         i915_gem_context_put_unlocked(vgpu->shadow_ctx);
 575 }
 576
 577 int intel_vgpu_init_gvt_context(struct intel_vgpu *vgpu)
 578 {
 579         atomic_set(&vgpu->running_workload_num, 0);
 580
 581         vgpu->shadow_ctx = i915_gem_context_create_gvt(
 582                         &vgpu->gvt->dev_priv->drm);
 583         if (IS_ERR(vgpu->shadow_ctx))
 584                 return PTR_ERR(vgpu->shadow_ctx);
 585
 586         vgpu->shadow_ctx->engine[RCS].initialised = true;
 587
 588         return 0;
 589 }