drivers/gpu/drm/i915/gvt/scheduler.c

   1 /*
   2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Zhi Wang <zhi.a.wang@intel.com>
  25  *
  26  * Contributors:
  27  *    Ping Gao <ping.a.gao@intel.com>
  28  *    Tina Zhang <tina.zhang@intel.com>
  29  *    Chanbin Du <changbin.du@intel.com>
  30  *    Min He <min.he@intel.com>
  31  *    Bing Niu <bing.niu@intel.com>
  32  *    Zhenyu Wang <zhenyuw@linux.intel.com>
  33  *
  34  */
  35
  36 #include <linux/kthread.h>
  37
  38 #include "i915_drv.h"
  39 #include "gvt.h"
  40
  41 #define RING_CTX_OFF(x) \
  42         offsetof(struct execlist_ring_context, x)
  43
  44 static void set_context_pdp_root_pointer(
  45                 struct execlist_ring_context *ring_context,
  46                 u32 pdp[8])
  47 {
  48         struct execlist_mmio_pair *pdp_pair = &ring_context->pdp3_UDW;
  49         int i;
  50
  51         for (i = 0; i < 8; i++)
  52                 pdp_pair[i].val = pdp[7 - i];
  53 }
  54
  55 static int populate_shadow_context(struct intel_vgpu_workload *workload)
  56 {
  57         struct intel_vgpu *vgpu = workload->vgpu;
  58         struct intel_gvt *gvt = vgpu->gvt;
  59         int ring_id = workload->ring_id;
  60         struct i915_gem_context *shadow_ctx = workload->vgpu->shadow_ctx;
  61         struct drm_i915_gem_object *ctx_obj =
  62                 shadow_ctx->engine[ring_id].state->obj;
  63         struct execlist_ring_context *shadow_ring_context;
  64         struct page *page;
  65         void *dst;
  66         unsigned long context_gpa, context_page_num;
  67         int i;
  68
  69         gvt_dbg_sched("ring id %d workload lrca %x", ring_id,
  70                         workload->ctx_desc.lrca);
  71
  72         context_page_num = intel_lr_context_size(
  73                         gvt->dev_priv->engine[ring_id]);
  74
  75         context_page_num = context_page_num >> PAGE_SHIFT;
  76
  77         if (IS_BROADWELL(gvt->dev_priv) && ring_id == RCS)
  78                 context_page_num = 19;
  79
  80         i = 2;
  81
  82         while (i < context_page_num) {
  83                 context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
  84                                 (u32)((workload->ctx_desc.lrca + i) <<
  85                                 GTT_PAGE_SHIFT));
  86                 if (context_gpa == INTEL_GVT_INVALID_ADDR) {
  87                         gvt_err("Invalid guest context descriptor\n");
  88                         return -EINVAL;
  89                 }
  90
  91                 page = i915_gem_object_get_page(ctx_obj, LRC_PPHWSP_PN + i);
  92                 dst = kmap(page);
  93                 intel_gvt_hypervisor_read_gpa(vgpu, context_gpa, dst,
  94                                 GTT_PAGE_SIZE);
  95                 kunmap(page);
  96                 i++;
  97         }
  98
  99         page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
 100         shadow_ring_context = kmap(page);
 101
 102 #define COPY_REG(name) \
 103         intel_gvt_hypervisor_read_gpa(vgpu, workload->ring_context_gpa \
 104                 + RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4)
 105
 106         COPY_REG(ctx_ctrl);
 107         COPY_REG(ctx_timestamp);
 108
 109         if (ring_id == RCS) {
 110                 COPY_REG(bb_per_ctx_ptr);
 111                 COPY_REG(rcs_indirect_ctx);
 112                 COPY_REG(rcs_indirect_ctx_offset);
 113         }
 114 #undef COPY_REG
 115
 116         set_context_pdp_root_pointer(shadow_ring_context,
 117                                      workload->shadow_mm->shadow_page_table);
 118
 119         intel_gvt_hypervisor_read_gpa(vgpu,
 120                         workload->ring_context_gpa +
 121                         sizeof(*shadow_ring_context),
 122                         (void *)shadow_ring_context +
 123                         sizeof(*shadow_ring_context),
 124                         GTT_PAGE_SIZE - sizeof(*shadow_ring_context));
 125
 126         kunmap(page);
 127         return 0;
 128 }
 129
 130 static int shadow_context_status_change(struct notifier_block *nb,
 131                 unsigned long action, void *data)
 132 {
 133         struct intel_vgpu *vgpu = container_of(nb,
 134                         struct intel_vgpu, shadow_ctx_notifier_block);
 135         struct drm_i915_gem_request *req =
 136                 (struct drm_i915_gem_request *)data;
 137         struct intel_gvt_workload_scheduler *scheduler =
 138                 &vgpu->gvt->scheduler;
 139         struct intel_vgpu_workload *workload =
 140                 scheduler->current_workload[req->engine->id];
 141
 142         if (unlikely(!workload))
 143                 return NOTIFY_OK;
 144
 145         switch (action) {
 146         case INTEL_CONTEXT_SCHEDULE_IN:
 147                 intel_gvt_load_render_mmio(workload->vgpu,
 148                                            workload->ring_id);
 149                 atomic_set(&workload->shadow_ctx_active, 1);
 150                 break;
 151         case INTEL_CONTEXT_SCHEDULE_OUT:
 152                 intel_gvt_restore_render_mmio(workload->vgpu,
 153                                               workload->ring_id);
 154                 /* If the status is -EINPROGRESS means this workload
 155                  * doesn't meet any issue during dispatching so when
 156                  * get the SCHEDULE_OUT set the status to be zero for
 157                  * good. If the status is NOT -EINPROGRESS means there
 158                  * is something wrong happened during dispatching and
 159                  * the status should not be set to zero
 160                  */
 161                 if (workload->status == -EINPROGRESS)
 162                         workload->status = 0;
 163                 atomic_set(&workload->shadow_ctx_active, 0);
 164                 break;
 165         default:
 166                 WARN_ON(1);
 167                 return NOTIFY_OK;
 168         }
 169         wake_up(&workload->shadow_ctx_status_wq);
 170         return NOTIFY_OK;
 171 }
 172
 173 static int dispatch_workload(struct intel_vgpu_workload *workload)
 174 {
 175         int ring_id = workload->ring_id;
 176         struct i915_gem_context *shadow_ctx = workload->vgpu->shadow_ctx;
 177         struct drm_i915_private *dev_priv = workload->vgpu->gvt->dev_priv;
 178         struct drm_i915_gem_request *rq;
 179         int ret;
 180
 181         gvt_dbg_sched("ring id %d prepare to dispatch workload %p\n",
 182                 ring_id, workload);
 183
 184         shadow_ctx->desc_template &= ~(0x3 << GEN8_CTX_ADDRESSING_MODE_SHIFT);
 185         shadow_ctx->desc_template |= workload->ctx_desc.addressing_mode <<
 186                                     GEN8_CTX_ADDRESSING_MODE_SHIFT;
 187
 188         mutex_lock(&dev_priv->drm.struct_mutex);
 189
 190         rq = i915_gem_request_alloc(dev_priv->engine[ring_id], shadow_ctx);
 191         if (IS_ERR(rq)) {
 192                 gvt_err("fail to allocate gem request\n");
 193                 ret = PTR_ERR(rq);
 194                 goto out;
 195         }
 196
 197         gvt_dbg_sched("ring id %d get i915 gem request %p\n", ring_id, rq);
 198
 199         workload->req = i915_gem_request_get(rq);
 200
 201         ret = intel_gvt_scan_and_shadow_workload(workload);
 202         if (ret)
 203                 goto out;
 204
 205         ret = intel_gvt_scan_and_shadow_wa_ctx(&workload->wa_ctx);
 206         if (ret)
 207                 goto out;
 208
 209         ret = populate_shadow_context(workload);
 210         if (ret)
 211                 goto out;
 212
 213         if (workload->prepare) {
 214                 ret = workload->prepare(workload);
 215                 if (ret)
 216                         goto out;
 217         }
 218
 219         gvt_dbg_sched("ring id %d submit workload to i915 %p\n",
 220                         ring_id, workload->req);
 221
 222         ret = 0;
 223         workload->dispatched = true;
 224 out:
 225         if (ret)
 226                 workload->status = ret;
 227
 228         if (!IS_ERR_OR_NULL(rq))
 229                 i915_add_request_no_flush(rq);
 230         mutex_unlock(&dev_priv->drm.struct_mutex);
 231         return ret;
 232 }
 233
 234 static struct intel_vgpu_workload *pick_next_workload(
 235                 struct intel_gvt *gvt, int ring_id)
 236 {
 237         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
 238         struct intel_vgpu_workload *workload = NULL;
 239
 240         mutex_lock(&gvt->lock);
 241
 242         /*
 243          * no current vgpu / will be scheduled out / no workload
 244          * bail out
 245          */
 246         if (!scheduler->current_vgpu) {
 247                 gvt_dbg_sched("ring id %d stop - no current vgpu\n", ring_id);
 248                 goto out;
 249         }
 250
 251         if (scheduler->need_reschedule) {
 252                 gvt_dbg_sched("ring id %d stop - will reschedule\n", ring_id);
 253                 goto out;
 254         }
 255
 256         if (list_empty(workload_q_head(scheduler->current_vgpu, ring_id))) {
 257                 gvt_dbg_sched("ring id %d stop - no available workload\n",
 258                                 ring_id);
 259                 goto out;
 260         }
 261
 262         /*
 263          * still have current workload, maybe the workload disptacher
 264          * fail to submit it for some reason, resubmit it.
 265          */
 266         if (scheduler->current_workload[ring_id]) {
 267                 workload = scheduler->current_workload[ring_id];
 268                 gvt_dbg_sched("ring id %d still have current workload %p\n",
 269                                 ring_id, workload);
 270                 goto out;
 271         }
 272
 273         /*
 274          * pick a workload as current workload
 275          * once current workload is set, schedule policy routines
 276          * will wait the current workload is finished when trying to
 277          * schedule out a vgpu.
 278          */
 279         scheduler->current_workload[ring_id] = container_of(
 280                         workload_q_head(scheduler->current_vgpu, ring_id)->next,
 281                         struct intel_vgpu_workload, list);
 282
 283         workload = scheduler->current_workload[ring_id];
 284
 285         gvt_dbg_sched("ring id %d pick new workload %p\n", ring_id, workload);
 286
 287         atomic_inc(&workload->vgpu->running_workload_num);
 288 out:
 289         mutex_unlock(&gvt->lock);
 290         return workload;
 291 }
 292
 293 static void update_guest_context(struct intel_vgpu_workload *workload)
 294 {
 295         struct intel_vgpu *vgpu = workload->vgpu;
 296         struct intel_gvt *gvt = vgpu->gvt;
 297         int ring_id = workload->ring_id;
 298         struct i915_gem_context *shadow_ctx = workload->vgpu->shadow_ctx;
 299         struct drm_i915_gem_object *ctx_obj =
 300                 shadow_ctx->engine[ring_id].state->obj;
 301         struct execlist_ring_context *shadow_ring_context;
 302         struct page *page;
 303         void *src;
 304         unsigned long context_gpa, context_page_num;
 305         int i;
 306
 307         gvt_dbg_sched("ring id %d workload lrca %x\n", ring_id,
 308                         workload->ctx_desc.lrca);
 309
 310         context_page_num = intel_lr_context_size(
 311                         gvt->dev_priv->engine[ring_id]);
 312
 313         context_page_num = context_page_num >> PAGE_SHIFT;
 314
 315         if (IS_BROADWELL(gvt->dev_priv) && ring_id == RCS)
 316                 context_page_num = 19;
 317
 318         i = 2;
 319
 320         while (i < context_page_num) {
 321                 context_gpa = intel_vgpu_gma_to_gpa(vgpu->gtt.ggtt_mm,
 322                                 (u32)((workload->ctx_desc.lrca + i) <<
 323                                         GTT_PAGE_SHIFT));
 324                 if (context_gpa == INTEL_GVT_INVALID_ADDR) {
 325                         gvt_err("invalid guest context descriptor\n");
 326                         return;
 327                 }
 328
 329                 page = i915_gem_object_get_page(ctx_obj, LRC_PPHWSP_PN + i);
 330                 src = kmap(page);
 331                 intel_gvt_hypervisor_write_gpa(vgpu, context_gpa, src,
 332                                 GTT_PAGE_SIZE);
 333                 kunmap(page);
 334                 i++;
 335         }
 336
 337         intel_gvt_hypervisor_write_gpa(vgpu, workload->ring_context_gpa +
 338                 RING_CTX_OFF(ring_header.val), &workload->rb_tail, 4);
 339
 340         page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
 341         shadow_ring_context = kmap(page);
 342
 343 #define COPY_REG(name) \
 344         intel_gvt_hypervisor_write_gpa(vgpu, workload->ring_context_gpa + \
 345                 RING_CTX_OFF(name.val), &shadow_ring_context->name.val, 4)
 346
 347         COPY_REG(ctx_ctrl);
 348         COPY_REG(ctx_timestamp);
 349
 350 #undef COPY_REG
 351
 352         intel_gvt_hypervisor_write_gpa(vgpu,
 353                         workload->ring_context_gpa +
 354                         sizeof(*shadow_ring_context),
 355                         (void *)shadow_ring_context +
 356                         sizeof(*shadow_ring_context),
 357                         GTT_PAGE_SIZE - sizeof(*shadow_ring_context));
 358
 359         kunmap(page);
 360 }
 361
 362 static void complete_current_workload(struct intel_gvt *gvt, int ring_id)
 363 {
 364         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
 365         struct intel_vgpu_workload *workload;
 366         struct intel_vgpu *vgpu;
 367         int event;
 368
 369         mutex_lock(&gvt->lock);
 370
 371         workload = scheduler->current_workload[ring_id];
 372         vgpu = workload->vgpu;
 373
 374         /* For the workload w/ request, needs to wait for the context
 375          * switch to make sure request is completed.
 376          * For the workload w/o request, directly complete the workload.
 377          */
 378         if (workload->req) {
 379                 wait_event(workload->shadow_ctx_status_wq,
 380                            !atomic_read(&workload->shadow_ctx_active));
 381
 382                 i915_gem_request_put(fetch_and_zero(&workload->req));
 383
 384                 if (!workload->status && !vgpu->resetting) {
 385                         update_guest_context(workload);
 386
 387                         for_each_set_bit(event, workload->pending_events,
 388                                          INTEL_GVT_EVENT_MAX)
 389                                 intel_vgpu_trigger_virtual_event(vgpu, event);
 390                 }
 391         }
 392
 393         gvt_dbg_sched("ring id %d complete workload %p status %d\n",
 394                         ring_id, workload, workload->status);
 395
 396         scheduler->current_workload[ring_id] = NULL;
 397
 398         list_del_init(&workload->list);
 399         workload->complete(workload);
 400
 401         atomic_dec(&vgpu->running_workload_num);
 402         wake_up(&scheduler->workload_complete_wq);
 403         mutex_unlock(&gvt->lock);
 404 }
 405
 406 struct workload_thread_param {
 407         struct intel_gvt *gvt;
 408         int ring_id;
 409 };
 410
 411 static DEFINE_MUTEX(scheduler_mutex);
 412
 413 static int workload_thread(void *priv)
 414 {
 415         struct workload_thread_param *p = (struct workload_thread_param *)priv;
 416         struct intel_gvt *gvt = p->gvt;
 417         int ring_id = p->ring_id;
 418         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
 419         struct intel_vgpu_workload *workload = NULL;
 420         int ret;
 421         bool need_force_wake = IS_SKYLAKE(gvt->dev_priv);
 422         DEFINE_WAIT_FUNC(wait, woken_wake_function);
 423
 424         kfree(p);
 425
 426         gvt_dbg_core("workload thread for ring %d started\n", ring_id);
 427
 428         while (!kthread_should_stop()) {
 429                 add_wait_queue(&scheduler->waitq[ring_id], &wait);
 430                 do {
 431                         workload = pick_next_workload(gvt, ring_id);
 432                         if (workload)
 433                                 break;
 434                         wait_woken(&wait, TASK_INTERRUPTIBLE,
 435                                    MAX_SCHEDULE_TIMEOUT);
 436                 } while (!kthread_should_stop());
 437                 remove_wait_queue(&scheduler->waitq[ring_id], &wait);
 438
 439                 if (!workload)
 440                         break;
 441
 442                 mutex_lock(&scheduler_mutex);
 443
 444                 gvt_dbg_sched("ring id %d next workload %p vgpu %d\n",
 445                                 workload->ring_id, workload,
 446                                 workload->vgpu->id);
 447
 448                 intel_runtime_pm_get(gvt->dev_priv);
 449
 450                 gvt_dbg_sched("ring id %d will dispatch workload %p\n",
 451                                 workload->ring_id, workload);
 452
 453                 if (need_force_wake)
 454                         intel_uncore_forcewake_get(gvt->dev_priv,
 455                                         FORCEWAKE_ALL);
 456
 457                 mutex_lock(&gvt->lock);
 458                 ret = dispatch_workload(workload);
 459                 mutex_unlock(&gvt->lock);
 460
 461                 if (ret) {
 462                         gvt_err("fail to dispatch workload, skip\n");
 463                         goto complete;
 464                 }
 465
 466                 gvt_dbg_sched("ring id %d wait workload %p\n",
 467                                 workload->ring_id, workload);
 468 retry:
 469                 i915_wait_request(workload->req,
 470                                          0, MAX_SCHEDULE_TIMEOUT);
 471                 /* I915 has replay mechanism and a request will be replayed
 472                  * if there is i915 reset. So the seqno will be updated anyway.
 473                  * If the seqno is not updated yet after waiting, which means
 474                  * the replay may still be in progress and we can wait again.
 475                  */
 476                 if (!i915_gem_request_completed(workload->req)) {
 477                         gvt_dbg_sched("workload %p not completed, wait again\n",
 478                                         workload);
 479                         goto retry;
 480                 }
 481
 482 complete:
 483                 gvt_dbg_sched("will complete workload %p, status: %d\n",
 484                                 workload, workload->status);
 485
 486                 complete_current_workload(gvt, ring_id);
 487
 488                 if (need_force_wake)
 489                         intel_uncore_forcewake_put(gvt->dev_priv,
 490                                         FORCEWAKE_ALL);
 491
 492                 intel_runtime_pm_put(gvt->dev_priv);
 493
 494                 mutex_unlock(&scheduler_mutex);
 495
 496         }
 497         return 0;
 498 }
 499
 500 void intel_gvt_wait_vgpu_idle(struct intel_vgpu *vgpu)
 501 {
 502         struct intel_gvt *gvt = vgpu->gvt;
 503         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
 504
 505         if (atomic_read(&vgpu->running_workload_num)) {
 506                 gvt_dbg_sched("wait vgpu idle\n");
 507
 508                 wait_event(scheduler->workload_complete_wq,
 509                                 !atomic_read(&vgpu->running_workload_num));
 510         }
 511 }
 512
 513 void intel_gvt_clean_workload_scheduler(struct intel_gvt *gvt)
 514 {
 515         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
 516         int i;
 517
 518         gvt_dbg_core("clean workload scheduler\n");
 519
 520         for (i = 0; i < I915_NUM_ENGINES; i++) {
 521                 if (scheduler->thread[i]) {
 522                         kthread_stop(scheduler->thread[i]);
 523                         scheduler->thread[i] = NULL;
 524                 }
 525         }
 526 }
 527
 528 int intel_gvt_init_workload_scheduler(struct intel_gvt *gvt)
 529 {
 530         struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
 531         struct workload_thread_param *param = NULL;
 532         int ret;
 533         int i;
 534
 535         gvt_dbg_core("init workload scheduler\n");
 536
 537         init_waitqueue_head(&scheduler->workload_complete_wq);
 538
 539         for (i = 0; i < I915_NUM_ENGINES; i++) {
 540                 /* check ring mask at init time */
 541                 if (!HAS_ENGINE(gvt->dev_priv, i))
 542                         continue;
 543
 544                 init_waitqueue_head(&scheduler->waitq[i]);
 545
 546                 param = kzalloc(sizeof(*param), GFP_KERNEL);
 547                 if (!param) {
 548                         ret = -ENOMEM;
 549                         goto err;
 550                 }
 551
 552                 param->gvt = gvt;
 553                 param->ring_id = i;
 554
 555                 scheduler->thread[i] = kthread_run(workload_thread, param,
 556                         "gvt workload %d", i);
 557                 if (IS_ERR(scheduler->thread[i])) {
 558                         gvt_err("fail to create workload thread\n");
 559                         ret = PTR_ERR(scheduler->thread[i]);
 560                         goto err;
 561                 }
 562         }
 563         return 0;
 564 err:
 565         intel_gvt_clean_workload_scheduler(gvt);
 566         kfree(param);
 567         param = NULL;
 568         return ret;
 569 }
 570
 571 void intel_vgpu_clean_gvt_context(struct intel_vgpu *vgpu)
 572 {
 573         atomic_notifier_chain_unregister(&vgpu->shadow_ctx->status_notifier,
 574                         &vgpu->shadow_ctx_notifier_block);
 575
 576         i915_gem_context_put_unlocked(vgpu->shadow_ctx);
 577 }
 578
 579 int intel_vgpu_init_gvt_context(struct intel_vgpu *vgpu)
 580 {
 581         atomic_set(&vgpu->running_workload_num, 0);
 582
 583         vgpu->shadow_ctx = i915_gem_context_create_gvt(
 584                         &vgpu->gvt->dev_priv->drm);
 585         if (IS_ERR(vgpu->shadow_ctx))
 586                 return PTR_ERR(vgpu->shadow_ctx);
 587
 588         vgpu->shadow_ctx->engine[RCS].initialised = true;
 589
 590         vgpu->shadow_ctx_notifier_block.notifier_call =
 591                 shadow_context_status_change;
 592
 593         atomic_notifier_chain_register(&vgpu->shadow_ctx->status_notifier,
 594                                        &vgpu->shadow_ctx_notifier_block);
 595         return 0;
 596 }