2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Eddie Dong <eddie.dong@intel.com>
25 * Kevin Tian <kevin.tian@intel.com>
28 * Ping Gao <ping.a.gao@intel.com>
29 * Zhi Wang <zhi.a.wang@intel.com>
30 * Bing Niu <bing.niu@intel.com>
36 #include "i915_pvinfo.h"
38 void populate_pvinfo_page(struct intel_vgpu *vgpu)
40 /* setup the ballooning information */
41 vgpu_vreg64(vgpu, vgtif_reg(magic)) = VGT_MAGIC;
42 vgpu_vreg(vgpu, vgtif_reg(version_major)) = 1;
43 vgpu_vreg(vgpu, vgtif_reg(version_minor)) = 0;
44 vgpu_vreg(vgpu, vgtif_reg(display_ready)) = 0;
45 vgpu_vreg(vgpu, vgtif_reg(vgt_id)) = vgpu->id;
46 vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.base)) =
47 vgpu_aperture_gmadr_base(vgpu);
48 vgpu_vreg(vgpu, vgtif_reg(avail_rs.mappable_gmadr.size)) =
49 vgpu_aperture_sz(vgpu);
50 vgpu_vreg(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.base)) =
51 vgpu_hidden_gmadr_base(vgpu);
52 vgpu_vreg(vgpu, vgtif_reg(avail_rs.nonmappable_gmadr.size)) =
55 vgpu_vreg(vgpu, vgtif_reg(avail_rs.fence_num)) = vgpu_fence_sz(vgpu);
57 gvt_dbg_core("Populate PVINFO PAGE for vGPU %d\n", vgpu->id);
58 gvt_dbg_core("aperture base [GMADR] 0x%llx size 0x%llx\n",
59 vgpu_aperture_gmadr_base(vgpu), vgpu_aperture_sz(vgpu));
60 gvt_dbg_core("hidden base [GMADR] 0x%llx size=0x%llx\n",
61 vgpu_hidden_gmadr_base(vgpu), vgpu_hidden_sz(vgpu));
62 gvt_dbg_core("fence size %d\n", vgpu_fence_sz(vgpu));
64 WARN_ON(sizeof(struct vgt_if) != VGT_PVINFO_SIZE);
68 * intel_gvt_init_vgpu_types - initialize vGPU type list
71 * Initialize vGPU type list based on available resource.
74 int intel_gvt_init_vgpu_types(struct intel_gvt *gvt)
76 unsigned int num_types;
77 unsigned int i, low_avail, high_avail;
80 /* vGPU type name is defined as GVTg_Vx_y which contains
81 * physical GPU generation type and 'y' means maximum vGPU
82 * instances user can create on one physical GPU for this
85 * Depend on physical SKU resource, might see vGPU types like
86 * GVTg_V4_8, GVTg_V4_4, GVTg_V4_2, etc. We can create
87 * different types of vGPU on same physical GPU depending on
88 * available resource. Each vGPU type will have "avail_instance"
89 * to indicate how many vGPU instance can be created for this
93 low_avail = gvt_aperture_sz(gvt) - HOST_LOW_GM_SIZE;
94 high_avail = gvt_hidden_sz(gvt) - HOST_HIGH_GM_SIZE;
97 gvt->types = kzalloc(num_types * sizeof(struct intel_vgpu_type),
102 min_low = MB_TO_BYTES(32);
103 for (i = 0; i < num_types; ++i) {
104 if (low_avail / min_low == 0)
106 gvt->types[i].low_gm_size = min_low;
107 gvt->types[i].high_gm_size = max((min_low<<3), MB_TO_BYTES(384U));
108 gvt->types[i].fence = 4;
109 gvt->types[i].max_instance = min(low_avail / min_low,
110 high_avail / gvt->types[i].high_gm_size);
111 gvt->types[i].avail_instance = gvt->types[i].max_instance;
113 if (IS_GEN8(gvt->dev_priv))
114 sprintf(gvt->types[i].name, "GVTg_V4_%u",
115 gvt->types[i].max_instance);
116 else if (IS_GEN9(gvt->dev_priv))
117 sprintf(gvt->types[i].name, "GVTg_V5_%u",
118 gvt->types[i].max_instance);
121 gvt_dbg_core("type[%d]: %s max %u avail %u low %u high %u fence %u\n",
122 i, gvt->types[i].name, gvt->types[i].max_instance,
123 gvt->types[i].avail_instance,
124 gvt->types[i].low_gm_size,
125 gvt->types[i].high_gm_size, gvt->types[i].fence);
132 void intel_gvt_clean_vgpu_types(struct intel_gvt *gvt)
137 static void intel_gvt_update_vgpu_types(struct intel_gvt *gvt)
140 unsigned int low_gm_avail, high_gm_avail, fence_avail;
141 unsigned int low_gm_min, high_gm_min, fence_min, total_min;
143 /* Need to depend on maxium hw resource size but keep on
144 * static config for now.
146 low_gm_avail = gvt_aperture_sz(gvt) - HOST_LOW_GM_SIZE -
147 gvt->gm.vgpu_allocated_low_gm_size;
148 high_gm_avail = gvt_hidden_sz(gvt) - HOST_HIGH_GM_SIZE -
149 gvt->gm.vgpu_allocated_high_gm_size;
150 fence_avail = gvt_fence_sz(gvt) - HOST_FENCE -
151 gvt->fence.vgpu_allocated_fence_num;
153 for (i = 0; i < gvt->num_types; i++) {
154 low_gm_min = low_gm_avail / gvt->types[i].low_gm_size;
155 high_gm_min = high_gm_avail / gvt->types[i].high_gm_size;
156 fence_min = fence_avail / gvt->types[i].fence;
157 total_min = min(min(low_gm_min, high_gm_min), fence_min);
158 gvt->types[i].avail_instance = min(gvt->types[i].max_instance,
161 gvt_dbg_core("update type[%d]: %s max %u avail %u low %u high %u fence %u\n",
162 i, gvt->types[i].name, gvt->types[i].max_instance,
163 gvt->types[i].avail_instance, gvt->types[i].low_gm_size,
164 gvt->types[i].high_gm_size, gvt->types[i].fence);
169 * intel_gvt_destroy_vgpu - destroy a virtual GPU
172 * This function is called when user wants to destroy a virtual GPU.
175 void intel_gvt_destroy_vgpu(struct intel_vgpu *vgpu)
177 struct intel_gvt *gvt = vgpu->gvt;
179 mutex_lock(&gvt->lock);
181 vgpu->active = false;
182 idr_remove(&gvt->vgpu_idr, vgpu->id);
184 if (atomic_read(&vgpu->running_workload_num)) {
185 mutex_unlock(&gvt->lock);
186 intel_gvt_wait_vgpu_idle(vgpu);
187 mutex_lock(&gvt->lock);
190 intel_vgpu_stop_schedule(vgpu);
191 intel_vgpu_clean_sched_policy(vgpu);
192 intel_vgpu_clean_gvt_context(vgpu);
193 intel_vgpu_clean_execlist(vgpu);
194 intel_vgpu_clean_display(vgpu);
195 intel_vgpu_clean_opregion(vgpu);
196 intel_vgpu_clean_gtt(vgpu);
197 intel_gvt_hypervisor_detach_vgpu(vgpu);
198 intel_vgpu_free_resource(vgpu);
199 intel_vgpu_clean_mmio(vgpu);
202 intel_gvt_update_vgpu_types(gvt);
203 mutex_unlock(&gvt->lock);
206 static struct intel_vgpu *__intel_gvt_create_vgpu(struct intel_gvt *gvt,
207 struct intel_vgpu_creation_params *param)
209 struct intel_vgpu *vgpu;
212 gvt_dbg_core("handle %llu low %llu MB high %llu MB fence %llu\n",
213 param->handle, param->low_gm_sz, param->high_gm_sz,
216 vgpu = vzalloc(sizeof(*vgpu));
218 return ERR_PTR(-ENOMEM);
220 mutex_lock(&gvt->lock);
222 ret = idr_alloc(&gvt->vgpu_idr, vgpu, 1, GVT_MAX_VGPU, GFP_KERNEL);
227 vgpu->handle = param->handle;
229 bitmap_zero(vgpu->tlb_handle_pending, I915_NUM_ENGINES);
231 intel_vgpu_init_cfg_space(vgpu, param->primary);
233 ret = intel_vgpu_init_mmio(vgpu);
237 ret = intel_vgpu_alloc_resource(vgpu, param);
239 goto out_clean_vgpu_mmio;
241 populate_pvinfo_page(vgpu);
243 ret = intel_gvt_hypervisor_attach_vgpu(vgpu);
245 goto out_clean_vgpu_resource;
247 ret = intel_vgpu_init_gtt(vgpu);
249 goto out_detach_hypervisor_vgpu;
251 ret = intel_vgpu_init_display(vgpu);
255 ret = intel_vgpu_init_execlist(vgpu);
257 goto out_clean_display;
259 ret = intel_vgpu_init_gvt_context(vgpu);
261 goto out_clean_execlist;
263 ret = intel_vgpu_init_sched_policy(vgpu);
265 goto out_clean_shadow_ctx;
268 mutex_unlock(&gvt->lock);
272 out_clean_shadow_ctx:
273 intel_vgpu_clean_gvt_context(vgpu);
275 intel_vgpu_clean_execlist(vgpu);
277 intel_vgpu_clean_display(vgpu);
279 intel_vgpu_clean_gtt(vgpu);
280 out_detach_hypervisor_vgpu:
281 intel_gvt_hypervisor_detach_vgpu(vgpu);
282 out_clean_vgpu_resource:
283 intel_vgpu_free_resource(vgpu);
285 intel_vgpu_clean_mmio(vgpu);
287 idr_remove(&gvt->vgpu_idr, vgpu->id);
290 mutex_unlock(&gvt->lock);
295 * intel_gvt_create_vgpu - create a virtual GPU
297 * @type: type of the vGPU to create
299 * This function is called when user wants to create a virtual GPU.
302 * pointer to intel_vgpu, error pointer if failed.
304 struct intel_vgpu *intel_gvt_create_vgpu(struct intel_gvt *gvt,
305 struct intel_vgpu_type *type)
307 struct intel_vgpu_creation_params param;
308 struct intel_vgpu *vgpu;
312 param.low_gm_sz = type->low_gm_size;
313 param.high_gm_sz = type->high_gm_size;
314 param.fence_sz = type->fence;
316 /* XXX current param based on MB */
317 param.low_gm_sz = BYTES_TO_MB(param.low_gm_sz);
318 param.high_gm_sz = BYTES_TO_MB(param.high_gm_sz);
320 vgpu = __intel_gvt_create_vgpu(gvt, ¶m);
324 /* calculate left instance change for types */
325 intel_gvt_update_vgpu_types(gvt);
331 * intel_gvt_reset_vgpu_locked - reset a virtual GPU by DMLR or GT reset
333 * @dmlr: vGPU Device Model Level Reset or GT Reset
334 * @engine_mask: engines to reset for GT reset
336 * This function is called when user wants to reset a virtual GPU through
337 * device model reset or GT reset. The caller should hold the gvt lock.
339 * vGPU Device Model Level Reset (DMLR) simulates the PCI level reset to reset
340 * the whole vGPU to default state as when it is created. This vGPU function
341 * is required both for functionary and security concerns.The ultimate goal
342 * of vGPU FLR is that reuse a vGPU instance by virtual machines. When we
343 * assign a vGPU to a virtual machine we must isse such reset first.
345 * Full GT Reset and Per-Engine GT Reset are soft reset flow for GPU engines
346 * (Render, Blitter, Video, Video Enhancement). It is defined by GPU Spec.
347 * Unlike the FLR, GT reset only reset particular resource of a vGPU per
348 * the reset request. Guest driver can issue a GT reset by programming the
349 * virtual GDRST register to reset specific virtual GPU engine or all
352 * The parameter dev_level is to identify if we will do DMLR or GT reset.
353 * The parameter engine_mask is to specific the engines that need to be
354 * resetted. If value ALL_ENGINES is given for engine_mask, it means
355 * the caller requests a full GT reset that we will reset all virtual
356 * GPU engines. For FLR, engine_mask is ignored.
358 void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr,
359 unsigned int engine_mask)
361 struct intel_gvt *gvt = vgpu->gvt;
362 struct intel_gvt_workload_scheduler *scheduler = &gvt->scheduler;
364 gvt_dbg_core("------------------------------------------\n");
365 gvt_dbg_core("resseting vgpu%d, dmlr %d, engine_mask %08x\n",
366 vgpu->id, dmlr, engine_mask);
367 vgpu->resetting = true;
369 intel_vgpu_stop_schedule(vgpu);
371 * The current_vgpu will set to NULL after stopping the
372 * scheduler when the reset is triggered by current vgpu.
374 if (scheduler->current_vgpu == NULL) {
375 mutex_unlock(&gvt->lock);
376 intel_gvt_wait_vgpu_idle(vgpu);
377 mutex_lock(&gvt->lock);
380 intel_vgpu_reset_execlist(vgpu, dmlr ? ALL_ENGINES : engine_mask);
382 /* full GPU reset or device model level reset */
383 if (engine_mask == ALL_ENGINES || dmlr) {
384 intel_vgpu_reset_gtt(vgpu, dmlr);
385 intel_vgpu_reset_resource(vgpu);
386 intel_vgpu_reset_mmio(vgpu);
387 populate_pvinfo_page(vgpu);
388 intel_vgpu_reset_display(vgpu);
391 intel_vgpu_reset_cfg_space(vgpu);
394 vgpu->resetting = false;
395 gvt_dbg_core("reset vgpu%d done\n", vgpu->id);
396 gvt_dbg_core("------------------------------------------\n");
400 * intel_gvt_reset_vgpu - reset a virtual GPU (Function Level)
403 * This function is called when user wants to reset a virtual GPU.
406 void intel_gvt_reset_vgpu(struct intel_vgpu *vgpu)
408 mutex_lock(&vgpu->gvt->lock);
409 intel_gvt_reset_vgpu_locked(vgpu, true, 0);
410 mutex_unlock(&vgpu->gvt->lock);