drivers/gpu/drm/i915/i915_debugfs.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *
  27  */
  28
  29 #include <linux/seq_file.h>
  30 #include <linux/circ_buf.h>
  31 #include <linux/ctype.h>
  32 #include <linux/debugfs.h>
  33 #include <linux/slab.h>
  34 #include <linux/export.h>
  35 #include <linux/list_sort.h>
  36 #include <asm/msr-index.h>
  37 #include <drm/drmP.h>
  38 #include "intel_drv.h"
  39 #include "intel_ringbuffer.h"
  40 #include <drm/i915_drm.h>
  41 #include "i915_drv.h"
  42
  43 enum {
  44         ACTIVE_LIST,
  45         INACTIVE_LIST,
  46         PINNED_LIST,
  47 };
  48
  49 /* As the drm_debugfs_init() routines are called before dev->dev_private is
  50  * allocated we need to hook into the minor for release. */
  51 static int
  52 drm_add_fake_info_node(struct drm_minor *minor,
  53                        struct dentry *ent,
  54                        const void *key)
  55 {
  56         struct drm_info_node *node;
  57
  58         node = kmalloc(sizeof(*node), GFP_KERNEL);
  59         if (node == NULL) {
  60                 debugfs_remove(ent);
  61                 return -ENOMEM;
  62         }
  63
  64         node->minor = minor;
  65         node->dent = ent;
  66         node->info_ent = (void *) key;
  67
  68         mutex_lock(&minor->debugfs_lock);
  69         list_add(&node->list, &minor->debugfs_list);
  70         mutex_unlock(&minor->debugfs_lock);
  71
  72         return 0;
  73 }
  74
  75 static int i915_capabilities(struct seq_file *m, void *data)
  76 {
  77         struct drm_info_node *node = m->private;
  78         struct drm_device *dev = node->minor->dev;
  79         const struct intel_device_info *info = INTEL_INFO(dev);
  80
  81         seq_printf(m, "gen: %d\n", info->gen);
  82         seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
  83 #define PRINT_FLAG(x)  seq_printf(m, #x ": %s\n", yesno(info->x))
  84 #define SEP_SEMICOLON ;
  85         DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
  86 #undef PRINT_FLAG
  87 #undef SEP_SEMICOLON
  88
  89         return 0;
  90 }
  91
  92 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
  93 {
  94         if (obj->pin_display)
  95                 return "p";
  96         else
  97                 return " ";
  98 }
  99
 100 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
 101 {
 102         switch (obj->tiling_mode) {
 103         default:
 104         case I915_TILING_NONE: return " ";
 105         case I915_TILING_X: return "X";
 106         case I915_TILING_Y: return "Y";
 107         }
 108 }
 109
 110 static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
 111 {
 112         return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
 113 }
 114
 115 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
 116 {
 117         u64 size = 0;
 118         struct i915_vma *vma;
 119
 120         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 121                 if (vma->is_ggtt && drm_mm_node_allocated(&vma->node))
 122                         size += vma->node.size;
 123         }
 124
 125         return size;
 126 }
 127
 128 static void
 129 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
 130 {
 131         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
 132         struct intel_engine_cs *ring;
 133         struct i915_vma *vma;
 134         int pin_count = 0;
 135         int i;
 136
 137         seq_printf(m, "%pK: %s%s%s%s %8zdKiB %02x %02x [ ",
 138                    &obj->base,
 139                    obj->active ? "*" : " ",
 140                    get_pin_flag(obj),
 141                    get_tiling_flag(obj),
 142                    get_global_flag(obj),
 143                    obj->base.size / 1024,
 144                    obj->base.read_domains,
 145                    obj->base.write_domain);
 146         for_each_ring(ring, dev_priv, i)
 147                 seq_printf(m, "%x ",
 148                                 i915_gem_request_get_seqno(obj->last_read_req[i]));
 149         seq_printf(m, "] %x %x%s%s%s",
 150                    i915_gem_request_get_seqno(obj->last_write_req),
 151                    i915_gem_request_get_seqno(obj->last_fenced_req),
 152                    i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
 153                    obj->dirty ? " dirty" : "",
 154                    obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
 155         if (obj->base.name)
 156                 seq_printf(m, " (name: %d)", obj->base.name);
 157         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 158                 if (vma->pin_count > 0)
 159                         pin_count++;
 160         }
 161         seq_printf(m, " (pinned x %d)", pin_count);
 162         if (obj->pin_display)
 163                 seq_printf(m, " (display)");
 164         if (obj->fence_reg != I915_FENCE_REG_NONE)
 165                 seq_printf(m, " (fence: %d)", obj->fence_reg);
 166         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 167                 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
 168                            vma->is_ggtt ? "g" : "pp",
 169                            vma->node.start, vma->node.size);
 170                 if (vma->is_ggtt)
 171                         seq_printf(m, ", type: %u", vma->ggtt_view.type);
 172                 seq_puts(m, ")");
 173         }
 174         if (obj->stolen)
 175                 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
 176         if (obj->pin_display || obj->fault_mappable) {
 177                 char s[3], *t = s;
 178                 if (obj->pin_display)
 179                         *t++ = 'p';
 180                 if (obj->fault_mappable)
 181                         *t++ = 'f';
 182                 *t = '\0';
 183                 seq_printf(m, " (%s mappable)", s);
 184         }
 185         if (obj->last_write_req != NULL)
 186                 seq_printf(m, " (%s)",
 187                            i915_gem_request_get_ring(obj->last_write_req)->name);
 188         if (obj->frontbuffer_bits)
 189                 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
 190 }
 191
 192 static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
 193 {
 194         seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
 195         seq_putc(m, ctx->remap_slice ? 'R' : 'r');
 196         seq_putc(m, ' ');
 197 }
 198
 199 static int i915_gem_object_list_info(struct seq_file *m, void *data)
 200 {
 201         struct drm_info_node *node = m->private;
 202         uintptr_t list = (uintptr_t) node->info_ent->data;
 203         struct list_head *head;
 204         struct drm_device *dev = node->minor->dev;
 205         struct drm_i915_private *dev_priv = dev->dev_private;
 206         struct i915_address_space *vm = &dev_priv->gtt.base;
 207         struct i915_vma *vma;
 208         u64 total_obj_size, total_gtt_size;
 209         int count, ret;
 210
 211         ret = mutex_lock_interruptible(&dev->struct_mutex);
 212         if (ret)
 213                 return ret;
 214
 215         /* FIXME: the user of this interface might want more than just GGTT */
 216         switch (list) {
 217         case ACTIVE_LIST:
 218                 seq_puts(m, "Active:\n");
 219                 head = &vm->active_list;
 220                 break;
 221         case INACTIVE_LIST:
 222                 seq_puts(m, "Inactive:\n");
 223                 head = &vm->inactive_list;
 224                 break;
 225         default:
 226                 mutex_unlock(&dev->struct_mutex);
 227                 return -EINVAL;
 228         }
 229
 230         total_obj_size = total_gtt_size = count = 0;
 231         list_for_each_entry(vma, head, vm_link) {
 232                 seq_printf(m, "   ");
 233                 describe_obj(m, vma->obj);
 234                 seq_printf(m, "\n");
 235                 total_obj_size += vma->obj->base.size;
 236                 total_gtt_size += vma->node.size;
 237                 count++;
 238         }
 239         mutex_unlock(&dev->struct_mutex);
 240
 241         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 242                    count, total_obj_size, total_gtt_size);
 243         return 0;
 244 }
 245
 246 static int obj_rank_by_stolen(void *priv,
 247                               struct list_head *A, struct list_head *B)
 248 {
 249         struct drm_i915_gem_object *a =
 250                 container_of(A, struct drm_i915_gem_object, obj_exec_link);
 251         struct drm_i915_gem_object *b =
 252                 container_of(B, struct drm_i915_gem_object, obj_exec_link);
 253
 254         if (a->stolen->start < b->stolen->start)
 255                 return -1;
 256         if (a->stolen->start > b->stolen->start)
 257                 return 1;
 258         return 0;
 259 }
 260
 261 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
 262 {
 263         struct drm_info_node *node = m->private;
 264         struct drm_device *dev = node->minor->dev;
 265         struct drm_i915_private *dev_priv = dev->dev_private;
 266         struct drm_i915_gem_object *obj;
 267         u64 total_obj_size, total_gtt_size;
 268         LIST_HEAD(stolen);
 269         int count, ret;
 270
 271         ret = mutex_lock_interruptible(&dev->struct_mutex);
 272         if (ret)
 273                 return ret;
 274
 275         total_obj_size = total_gtt_size = count = 0;
 276         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 277                 if (obj->stolen == NULL)
 278                         continue;
 279
 280                 list_add(&obj->obj_exec_link, &stolen);
 281
 282                 total_obj_size += obj->base.size;
 283                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 284                 count++;
 285         }
 286         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 287                 if (obj->stolen == NULL)
 288                         continue;
 289
 290                 list_add(&obj->obj_exec_link, &stolen);
 291
 292                 total_obj_size += obj->base.size;
 293                 count++;
 294         }
 295         list_sort(NULL, &stolen, obj_rank_by_stolen);
 296         seq_puts(m, "Stolen:\n");
 297         while (!list_empty(&stolen)) {
 298                 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
 299                 seq_puts(m, "   ");
 300                 describe_obj(m, obj);
 301                 seq_putc(m, '\n');
 302                 list_del_init(&obj->obj_exec_link);
 303         }
 304         mutex_unlock(&dev->struct_mutex);
 305
 306         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 307                    count, total_obj_size, total_gtt_size);
 308         return 0;
 309 }
 310
 311 #define count_objects(list, member) do { \
 312         list_for_each_entry(obj, list, member) { \
 313                 size += i915_gem_obj_total_ggtt_size(obj); \
 314                 ++count; \
 315                 if (obj->map_and_fenceable) { \
 316                         mappable_size += i915_gem_obj_ggtt_size(obj); \
 317                         ++mappable_count; \
 318                 } \
 319         } \
 320 } while (0)
 321
 322 struct file_stats {
 323         struct drm_i915_file_private *file_priv;
 324         unsigned long count;
 325         u64 total, unbound;
 326         u64 global, shared;
 327         u64 active, inactive;
 328 };
 329
 330 static int per_file_stats(int id, void *ptr, void *data)
 331 {
 332         struct drm_i915_gem_object *obj = ptr;
 333         struct file_stats *stats = data;
 334         struct i915_vma *vma;
 335
 336         stats->count++;
 337         stats->total += obj->base.size;
 338
 339         if (obj->base.name || obj->base.dma_buf)
 340                 stats->shared += obj->base.size;
 341
 342         if (USES_FULL_PPGTT(obj->base.dev)) {
 343                 list_for_each_entry(vma, &obj->vma_list, obj_link) {
 344                         struct i915_hw_ppgtt *ppgtt;
 345
 346                         if (!drm_mm_node_allocated(&vma->node))
 347                                 continue;
 348
 349                         if (vma->is_ggtt) {
 350                                 stats->global += obj->base.size;
 351                                 continue;
 352                         }
 353
 354                         ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
 355                         if (ppgtt->file_priv != stats->file_priv)
 356                                 continue;
 357
 358                         if (obj->active) /* XXX per-vma statistic */
 359                                 stats->active += obj->base.size;
 360                         else
 361                                 stats->inactive += obj->base.size;
 362
 363                         return 0;
 364                 }
 365         } else {
 366                 if (i915_gem_obj_ggtt_bound(obj)) {
 367                         stats->global += obj->base.size;
 368                         if (obj->active)
 369                                 stats->active += obj->base.size;
 370                         else
 371                                 stats->inactive += obj->base.size;
 372                         return 0;
 373                 }
 374         }
 375
 376         if (!list_empty(&obj->global_list))
 377                 stats->unbound += obj->base.size;
 378
 379         return 0;
 380 }
 381
 382 #define print_file_stats(m, name, stats) do { \
 383         if (stats.count) \
 384                 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
 385                            name, \
 386                            stats.count, \
 387                            stats.total, \
 388                            stats.active, \
 389                            stats.inactive, \
 390                            stats.global, \
 391                            stats.shared, \
 392                            stats.unbound); \
 393 } while (0)
 394
 395 static void print_batch_pool_stats(struct seq_file *m,
 396                                    struct drm_i915_private *dev_priv)
 397 {
 398         struct drm_i915_gem_object *obj;
 399         struct file_stats stats;
 400         struct intel_engine_cs *ring;
 401         int i, j;
 402
 403         memset(&stats, 0, sizeof(stats));
 404
 405         for_each_ring(ring, dev_priv, i) {
 406                 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
 407                         list_for_each_entry(obj,
 408                                             &ring->batch_pool.cache_list[j],
 409                                             batch_pool_link)
 410                                 per_file_stats(0, obj, &stats);
 411                 }
 412         }
 413
 414         print_file_stats(m, "[k]batch pool", stats);
 415 }
 416
 417 #define count_vmas(list, member) do { \
 418         list_for_each_entry(vma, list, member) { \
 419                 size += i915_gem_obj_total_ggtt_size(vma->obj); \
 420                 ++count; \
 421                 if (vma->obj->map_and_fenceable) { \
 422                         mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
 423                         ++mappable_count; \
 424                 } \
 425         } \
 426 } while (0)
 427
 428 static int i915_gem_object_info(struct seq_file *m, void* data)
 429 {
 430         struct drm_info_node *node = m->private;
 431         struct drm_device *dev = node->minor->dev;
 432         struct drm_i915_private *dev_priv = dev->dev_private;
 433         u32 count, mappable_count, purgeable_count;
 434         u64 size, mappable_size, purgeable_size;
 435         struct drm_i915_gem_object *obj;
 436         struct i915_address_space *vm = &dev_priv->gtt.base;
 437         struct drm_file *file;
 438         struct i915_vma *vma;
 439         int ret;
 440
 441         ret = mutex_lock_interruptible(&dev->struct_mutex);
 442         if (ret)
 443                 return ret;
 444
 445         seq_printf(m, "%u objects, %zu bytes\n",
 446                    dev_priv->mm.object_count,
 447                    dev_priv->mm.object_memory);
 448
 449         size = count = mappable_size = mappable_count = 0;
 450         count_objects(&dev_priv->mm.bound_list, global_list);
 451         seq_printf(m, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
 452                    count, mappable_count, size, mappable_size);
 453
 454         size = count = mappable_size = mappable_count = 0;
 455         count_vmas(&vm->active_list, vm_link);
 456         seq_printf(m, "  %u [%u] active objects, %llu [%llu] bytes\n",
 457                    count, mappable_count, size, mappable_size);
 458
 459         size = count = mappable_size = mappable_count = 0;
 460         count_vmas(&vm->inactive_list, vm_link);
 461         seq_printf(m, "  %u [%u] inactive objects, %llu [%llu] bytes\n",
 462                    count, mappable_count, size, mappable_size);
 463
 464         size = count = purgeable_size = purgeable_count = 0;
 465         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 466                 size += obj->base.size, ++count;
 467                 if (obj->madv == I915_MADV_DONTNEED)
 468                         purgeable_size += obj->base.size, ++purgeable_count;
 469         }
 470         seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
 471
 472         size = count = mappable_size = mappable_count = 0;
 473         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 474                 if (obj->fault_mappable) {
 475                         size += i915_gem_obj_ggtt_size(obj);
 476                         ++count;
 477                 }
 478                 if (obj->pin_display) {
 479                         mappable_size += i915_gem_obj_ggtt_size(obj);
 480                         ++mappable_count;
 481                 }
 482                 if (obj->madv == I915_MADV_DONTNEED) {
 483                         purgeable_size += obj->base.size;
 484                         ++purgeable_count;
 485                 }
 486         }
 487         seq_printf(m, "%u purgeable objects, %llu bytes\n",
 488                    purgeable_count, purgeable_size);
 489         seq_printf(m, "%u pinned mappable objects, %llu bytes\n",
 490                    mappable_count, mappable_size);
 491         seq_printf(m, "%u fault mappable objects, %llu bytes\n",
 492                    count, size);
 493
 494         seq_printf(m, "%llu [%llu] gtt total\n",
 495                    dev_priv->gtt.base.total,
 496                    (u64)dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
 497
 498         seq_putc(m, '\n');
 499         print_batch_pool_stats(m, dev_priv);
 500         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
 501                 struct file_stats stats;
 502                 struct task_struct *task;
 503
 504                 memset(&stats, 0, sizeof(stats));
 505                 stats.file_priv = file->driver_priv;
 506                 spin_lock(&file->table_lock);
 507                 idr_for_each(&file->object_idr, per_file_stats, &stats);
 508                 spin_unlock(&file->table_lock);
 509                 /*
 510                  * Although we have a valid reference on file->pid, that does
 511                  * not guarantee that the task_struct who called get_pid() is
 512                  * still alive (e.g. get_pid(current) => fork() => exit()).
 513                  * Therefore, we need to protect this ->comm access using RCU.
 514                  */
 515                 rcu_read_lock();
 516                 task = pid_task(file->pid, PIDTYPE_PID);
 517                 print_file_stats(m, task ? task->comm : "<unknown>", stats);
 518                 rcu_read_unlock();
 519         }
 520
 521         mutex_unlock(&dev->struct_mutex);
 522
 523         return 0;
 524 }
 525
 526 static int i915_gem_gtt_info(struct seq_file *m, void *data)
 527 {
 528         struct drm_info_node *node = m->private;
 529         struct drm_device *dev = node->minor->dev;
 530         uintptr_t list = (uintptr_t) node->info_ent->data;
 531         struct drm_i915_private *dev_priv = dev->dev_private;
 532         struct drm_i915_gem_object *obj;
 533         u64 total_obj_size, total_gtt_size;
 534         int count, ret;
 535
 536         ret = mutex_lock_interruptible(&dev->struct_mutex);
 537         if (ret)
 538                 return ret;
 539
 540         total_obj_size = total_gtt_size = count = 0;
 541         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 542                 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
 543                         continue;
 544
 545                 seq_puts(m, "   ");
 546                 describe_obj(m, obj);
 547                 seq_putc(m, '\n');
 548                 total_obj_size += obj->base.size;
 549                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 550                 count++;
 551         }
 552
 553         mutex_unlock(&dev->struct_mutex);
 554
 555         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 556                    count, total_obj_size, total_gtt_size);
 557
 558         return 0;
 559 }
 560
 561 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
 562 {
 563         struct drm_info_node *node = m->private;
 564         struct drm_device *dev = node->minor->dev;
 565         struct drm_i915_private *dev_priv = dev->dev_private;
 566         struct intel_crtc *crtc;
 567         int ret;
 568
 569         ret = mutex_lock_interruptible(&dev->struct_mutex);
 570         if (ret)
 571                 return ret;
 572
 573         for_each_intel_crtc(dev, crtc) {
 574                 const char pipe = pipe_name(crtc->pipe);
 575                 const char plane = plane_name(crtc->plane);
 576                 struct intel_unpin_work *work;
 577
 578                 spin_lock_irq(&dev->event_lock);
 579                 work = crtc->unpin_work;
 580                 if (work == NULL) {
 581                         seq_printf(m, "No flip due on pipe %c (plane %c)\n",
 582                                    pipe, plane);
 583                 } else {
 584                         u32 addr;
 585
 586                         if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
 587                                 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
 588                                            pipe, plane);
 589                         } else {
 590                                 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
 591                                            pipe, plane);
 592                         }
 593                         if (work->flip_queued_req) {
 594                                 struct intel_engine_cs *ring =
 595                                         i915_gem_request_get_ring(work->flip_queued_req);
 596
 597                                 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
 598                                            ring->name,
 599                                            i915_gem_request_get_seqno(work->flip_queued_req),
 600                                            dev_priv->next_seqno,
 601                                            ring->get_seqno(ring, true),
 602                                            i915_gem_request_completed(work->flip_queued_req, true));
 603                         } else
 604                                 seq_printf(m, "Flip not associated with any ring\n");
 605                         seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
 606                                    work->flip_queued_vblank,
 607                                    work->flip_ready_vblank,
 608                                    drm_crtc_vblank_count(&crtc->base));
 609                         if (work->enable_stall_check)
 610                                 seq_puts(m, "Stall check enabled, ");
 611                         else
 612                                 seq_puts(m, "Stall check waiting for page flip ioctl, ");
 613                         seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
 614
 615                         if (INTEL_INFO(dev)->gen >= 4)
 616                                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
 617                         else
 618                                 addr = I915_READ(DSPADDR(crtc->plane));
 619                         seq_printf(m, "Current scanout address 0x%08x\n", addr);
 620
 621                         if (work->pending_flip_obj) {
 622                                 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
 623                                 seq_printf(m, "MMIO update completed? %d\n",  addr == work->gtt_offset);
 624                         }
 625                 }
 626                 spin_unlock_irq(&dev->event_lock);
 627         }
 628
 629         mutex_unlock(&dev->struct_mutex);
 630
 631         return 0;
 632 }
 633
 634 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
 635 {
 636         struct drm_info_node *node = m->private;
 637         struct drm_device *dev = node->minor->dev;
 638         struct drm_i915_private *dev_priv = dev->dev_private;
 639         struct drm_i915_gem_object *obj;
 640         struct intel_engine_cs *ring;
 641         int total = 0;
 642         int ret, i, j;
 643
 644         ret = mutex_lock_interruptible(&dev->struct_mutex);
 645         if (ret)
 646                 return ret;
 647
 648         for_each_ring(ring, dev_priv, i) {
 649                 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
 650                         int count;
 651
 652                         count = 0;
 653                         list_for_each_entry(obj,
 654                                             &ring->batch_pool.cache_list[j],
 655                                             batch_pool_link)
 656                                 count++;
 657                         seq_printf(m, "%s cache[%d]: %d objects\n",
 658                                    ring->name, j, count);
 659
 660                         list_for_each_entry(obj,
 661                                             &ring->batch_pool.cache_list[j],
 662                                             batch_pool_link) {
 663                                 seq_puts(m, "   ");
 664                                 describe_obj(m, obj);
 665                                 seq_putc(m, '\n');
 666                         }
 667
 668                         total += count;
 669                 }
 670         }
 671
 672         seq_printf(m, "total: %d\n", total);
 673
 674         mutex_unlock(&dev->struct_mutex);
 675
 676         return 0;
 677 }
 678
 679 static int i915_gem_request_info(struct seq_file *m, void *data)
 680 {
 681         struct drm_info_node *node = m->private;
 682         struct drm_device *dev = node->minor->dev;
 683         struct drm_i915_private *dev_priv = dev->dev_private;
 684         struct intel_engine_cs *ring;
 685         struct drm_i915_gem_request *req;
 686         int ret, any, i;
 687
 688         ret = mutex_lock_interruptible(&dev->struct_mutex);
 689         if (ret)
 690                 return ret;
 691
 692         any = 0;
 693         for_each_ring(ring, dev_priv, i) {
 694                 int count;
 695
 696                 count = 0;
 697                 list_for_each_entry(req, &ring->request_list, list)
 698                         count++;
 699                 if (count == 0)
 700                         continue;
 701
 702                 seq_printf(m, "%s requests: %d\n", ring->name, count);
 703                 list_for_each_entry(req, &ring->request_list, list) {
 704                         struct task_struct *task;
 705
 706                         rcu_read_lock();
 707                         task = NULL;
 708                         if (req->pid)
 709                                 task = pid_task(req->pid, PIDTYPE_PID);
 710                         seq_printf(m, "    %x @ %d: %s [%d]\n",
 711                                    req->seqno,
 712                                    (int) (jiffies - req->emitted_jiffies),
 713                                    task ? task->comm : "<unknown>",
 714                                    task ? task->pid : -1);
 715                         rcu_read_unlock();
 716                 }
 717
 718                 any++;
 719         }
 720         mutex_unlock(&dev->struct_mutex);
 721
 722         if (any == 0)
 723                 seq_puts(m, "No requests\n");
 724
 725         return 0;
 726 }
 727
 728 static void i915_ring_seqno_info(struct seq_file *m,
 729                                  struct intel_engine_cs *ring)
 730 {
 731         if (ring->get_seqno) {
 732                 seq_printf(m, "Current sequence (%s): %x\n",
 733                            ring->name, ring->get_seqno(ring, false));
 734         }
 735 }
 736
 737 static int i915_gem_seqno_info(struct seq_file *m, void *data)
 738 {
 739         struct drm_info_node *node = m->private;
 740         struct drm_device *dev = node->minor->dev;
 741         struct drm_i915_private *dev_priv = dev->dev_private;
 742         struct intel_engine_cs *ring;
 743         int ret, i;
 744
 745         ret = mutex_lock_interruptible(&dev->struct_mutex);
 746         if (ret)
 747                 return ret;
 748         intel_runtime_pm_get(dev_priv);
 749
 750         for_each_ring(ring, dev_priv, i)
 751                 i915_ring_seqno_info(m, ring);
 752
 753         intel_runtime_pm_put(dev_priv);
 754         mutex_unlock(&dev->struct_mutex);
 755
 756         return 0;
 757 }
 758
 759
 760 static int i915_interrupt_info(struct seq_file *m, void *data)
 761 {
 762         struct drm_info_node *node = m->private;
 763         struct drm_device *dev = node->minor->dev;
 764         struct drm_i915_private *dev_priv = dev->dev_private;
 765         struct intel_engine_cs *ring;
 766         int ret, i, pipe;
 767
 768         ret = mutex_lock_interruptible(&dev->struct_mutex);
 769         if (ret)
 770                 return ret;
 771         intel_runtime_pm_get(dev_priv);
 772
 773         if (IS_CHERRYVIEW(dev)) {
 774                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 775                            I915_READ(GEN8_MASTER_IRQ));
 776
 777                 seq_printf(m, "Display IER:\t%08x\n",
 778                            I915_READ(VLV_IER));
 779                 seq_printf(m, "Display IIR:\t%08x\n",
 780                            I915_READ(VLV_IIR));
 781                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 782                            I915_READ(VLV_IIR_RW));
 783                 seq_printf(m, "Display IMR:\t%08x\n",
 784                            I915_READ(VLV_IMR));
 785                 for_each_pipe(dev_priv, pipe)
 786                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 787                                    pipe_name(pipe),
 788                                    I915_READ(PIPESTAT(pipe)));
 789
 790                 seq_printf(m, "Port hotplug:\t%08x\n",
 791                            I915_READ(PORT_HOTPLUG_EN));
 792                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 793                            I915_READ(VLV_DPFLIPSTAT));
 794                 seq_printf(m, "DPINVGTT:\t%08x\n",
 795                            I915_READ(DPINVGTT));
 796
 797                 for (i = 0; i < 4; i++) {
 798                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 799                                    i, I915_READ(GEN8_GT_IMR(i)));
 800                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 801                                    i, I915_READ(GEN8_GT_IIR(i)));
 802                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 803                                    i, I915_READ(GEN8_GT_IER(i)));
 804                 }
 805
 806                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 807                            I915_READ(GEN8_PCU_IMR));
 808                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 809                            I915_READ(GEN8_PCU_IIR));
 810                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 811                            I915_READ(GEN8_PCU_IER));
 812         } else if (INTEL_INFO(dev)->gen >= 8) {
 813                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 814                            I915_READ(GEN8_MASTER_IRQ));
 815
 816                 for (i = 0; i < 4; i++) {
 817                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 818                                    i, I915_READ(GEN8_GT_IMR(i)));
 819                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 820                                    i, I915_READ(GEN8_GT_IIR(i)));
 821                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 822                                    i, I915_READ(GEN8_GT_IER(i)));
 823                 }
 824
 825                 for_each_pipe(dev_priv, pipe) {
 826                         enum intel_display_power_domain power_domain;
 827
 828                         power_domain = POWER_DOMAIN_PIPE(pipe);
 829                         if (!intel_display_power_get_if_enabled(dev_priv,
 830                                                                 power_domain)) {
 831                                 seq_printf(m, "Pipe %c power disabled\n",
 832                                            pipe_name(pipe));
 833                                 continue;
 834                         }
 835                         seq_printf(m, "Pipe %c IMR:\t%08x\n",
 836                                    pipe_name(pipe),
 837                                    I915_READ(GEN8_DE_PIPE_IMR(pipe)));
 838                         seq_printf(m, "Pipe %c IIR:\t%08x\n",
 839                                    pipe_name(pipe),
 840                                    I915_READ(GEN8_DE_PIPE_IIR(pipe)));
 841                         seq_printf(m, "Pipe %c IER:\t%08x\n",
 842                                    pipe_name(pipe),
 843                                    I915_READ(GEN8_DE_PIPE_IER(pipe)));
 844
 845                         intel_display_power_put(dev_priv, power_domain);
 846                 }
 847
 848                 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
 849                            I915_READ(GEN8_DE_PORT_IMR));
 850                 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
 851                            I915_READ(GEN8_DE_PORT_IIR));
 852                 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
 853                            I915_READ(GEN8_DE_PORT_IER));
 854
 855                 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
 856                            I915_READ(GEN8_DE_MISC_IMR));
 857                 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
 858                            I915_READ(GEN8_DE_MISC_IIR));
 859                 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
 860                            I915_READ(GEN8_DE_MISC_IER));
 861
 862                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 863                            I915_READ(GEN8_PCU_IMR));
 864                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 865                            I915_READ(GEN8_PCU_IIR));
 866                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 867                            I915_READ(GEN8_PCU_IER));
 868         } else if (IS_VALLEYVIEW(dev)) {
 869                 seq_printf(m, "Display IER:\t%08x\n",
 870                            I915_READ(VLV_IER));
 871                 seq_printf(m, "Display IIR:\t%08x\n",
 872                            I915_READ(VLV_IIR));
 873                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 874                            I915_READ(VLV_IIR_RW));
 875                 seq_printf(m, "Display IMR:\t%08x\n",
 876                            I915_READ(VLV_IMR));
 877                 for_each_pipe(dev_priv, pipe)
 878                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 879                                    pipe_name(pipe),
 880                                    I915_READ(PIPESTAT(pipe)));
 881
 882                 seq_printf(m, "Master IER:\t%08x\n",
 883                            I915_READ(VLV_MASTER_IER));
 884
 885                 seq_printf(m, "Render IER:\t%08x\n",
 886                            I915_READ(GTIER));
 887                 seq_printf(m, "Render IIR:\t%08x\n",
 888                            I915_READ(GTIIR));
 889                 seq_printf(m, "Render IMR:\t%08x\n",
 890                            I915_READ(GTIMR));
 891
 892                 seq_printf(m, "PM IER:\t\t%08x\n",
 893                            I915_READ(GEN6_PMIER));
 894                 seq_printf(m, "PM IIR:\t\t%08x\n",
 895                            I915_READ(GEN6_PMIIR));
 896                 seq_printf(m, "PM IMR:\t\t%08x\n",
 897                            I915_READ(GEN6_PMIMR));
 898
 899                 seq_printf(m, "Port hotplug:\t%08x\n",
 900                            I915_READ(PORT_HOTPLUG_EN));
 901                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 902                            I915_READ(VLV_DPFLIPSTAT));
 903                 seq_printf(m, "DPINVGTT:\t%08x\n",
 904                            I915_READ(DPINVGTT));
 905
 906         } else if (!HAS_PCH_SPLIT(dev)) {
 907                 seq_printf(m, "Interrupt enable:    %08x\n",
 908                            I915_READ(IER));
 909                 seq_printf(m, "Interrupt identity:  %08x\n",
 910                            I915_READ(IIR));
 911                 seq_printf(m, "Interrupt mask:      %08x\n",
 912                            I915_READ(IMR));
 913                 for_each_pipe(dev_priv, pipe)
 914                         seq_printf(m, "Pipe %c stat:         %08x\n",
 915                                    pipe_name(pipe),
 916                                    I915_READ(PIPESTAT(pipe)));
 917         } else {
 918                 seq_printf(m, "North Display Interrupt enable:          %08x\n",
 919                            I915_READ(DEIER));
 920                 seq_printf(m, "North Display Interrupt identity:        %08x\n",
 921                            I915_READ(DEIIR));
 922                 seq_printf(m, "North Display Interrupt mask:            %08x\n",
 923                            I915_READ(DEIMR));
 924                 seq_printf(m, "South Display Interrupt enable:          %08x\n",
 925                            I915_READ(SDEIER));
 926                 seq_printf(m, "South Display Interrupt identity:        %08x\n",
 927                            I915_READ(SDEIIR));
 928                 seq_printf(m, "South Display Interrupt mask:            %08x\n",
 929                            I915_READ(SDEIMR));
 930                 seq_printf(m, "Graphics Interrupt enable:               %08x\n",
 931                            I915_READ(GTIER));
 932                 seq_printf(m, "Graphics Interrupt identity:             %08x\n",
 933                            I915_READ(GTIIR));
 934                 seq_printf(m, "Graphics Interrupt mask:         %08x\n",
 935                            I915_READ(GTIMR));
 936         }
 937         for_each_ring(ring, dev_priv, i) {
 938                 if (INTEL_INFO(dev)->gen >= 6) {
 939                         seq_printf(m,
 940                                    "Graphics Interrupt mask (%s):       %08x\n",
 941                                    ring->name, I915_READ_IMR(ring));
 942                 }
 943                 i915_ring_seqno_info(m, ring);
 944         }
 945         intel_runtime_pm_put(dev_priv);
 946         mutex_unlock(&dev->struct_mutex);
 947
 948         return 0;
 949 }
 950
 951 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
 952 {
 953         struct drm_info_node *node = m->private;
 954         struct drm_device *dev = node->minor->dev;
 955         struct drm_i915_private *dev_priv = dev->dev_private;
 956         int i, ret;
 957
 958         ret = mutex_lock_interruptible(&dev->struct_mutex);
 959         if (ret)
 960                 return ret;
 961
 962         seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
 963         for (i = 0; i < dev_priv->num_fence_regs; i++) {
 964                 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
 965
 966                 seq_printf(m, "Fence %d, pin count = %d, object = ",
 967                            i, dev_priv->fence_regs[i].pin_count);
 968                 if (obj == NULL)
 969                         seq_puts(m, "unused");
 970                 else
 971                         describe_obj(m, obj);
 972                 seq_putc(m, '\n');
 973         }
 974
 975         mutex_unlock(&dev->struct_mutex);
 976         return 0;
 977 }
 978
 979 static int i915_hws_info(struct seq_file *m, void *data)
 980 {
 981         struct drm_info_node *node = m->private;
 982         struct drm_device *dev = node->minor->dev;
 983         struct drm_i915_private *dev_priv = dev->dev_private;
 984         struct intel_engine_cs *ring;
 985         const u32 *hws;
 986         int i;
 987
 988         ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
 989         hws = ring->status_page.page_addr;
 990         if (hws == NULL)
 991                 return 0;
 992
 993         for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
 994                 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
 995                            i * 4,
 996                            hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
 997         }
 998         return 0;
 999 }
1000
1001 static ssize_t
1002 i915_error_state_write(struct file *filp,
1003                        const char __user *ubuf,
1004                        size_t cnt,
1005                        loff_t *ppos)
1006 {
1007         struct i915_error_state_file_priv *error_priv = filp->private_data;
1008         struct drm_device *dev = error_priv->dev;
1009         int ret;
1010
1011         DRM_DEBUG_DRIVER("Resetting error state\n");
1012
1013         ret = mutex_lock_interruptible(&dev->struct_mutex);
1014         if (ret)
1015                 return ret;
1016
1017         i915_destroy_error_state(dev);
1018         mutex_unlock(&dev->struct_mutex);
1019
1020         return cnt;
1021 }
1022
1023 static int i915_error_state_open(struct inode *inode, struct file *file)
1024 {
1025         struct drm_device *dev = inode->i_private;
1026         struct i915_error_state_file_priv *error_priv;
1027
1028         error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
1029         if (!error_priv)
1030                 return -ENOMEM;
1031
1032         error_priv->dev = dev;
1033
1034         i915_error_state_get(dev, error_priv);
1035
1036         file->private_data = error_priv;
1037
1038         return 0;
1039 }
1040
1041 static int i915_error_state_release(struct inode *inode, struct file *file)
1042 {
1043         struct i915_error_state_file_priv *error_priv = file->private_data;
1044
1045         i915_error_state_put(error_priv);
1046         kfree(error_priv);
1047
1048         return 0;
1049 }
1050
1051 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1052                                      size_t count, loff_t *pos)
1053 {
1054         struct i915_error_state_file_priv *error_priv = file->private_data;
1055         struct drm_i915_error_state_buf error_str;
1056         loff_t tmp_pos = 0;
1057         ssize_t ret_count = 0;
1058         int ret;
1059
1060         ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
1061         if (ret)
1062                 return ret;
1063
1064         ret = i915_error_state_to_str(&error_str, error_priv);
1065         if (ret)
1066                 goto out;
1067
1068         ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1069                                             error_str.buf,
1070                                             error_str.bytes);
1071
1072         if (ret_count < 0)
1073                 ret = ret_count;
1074         else
1075                 *pos = error_str.start + ret_count;
1076 out:
1077         i915_error_state_buf_release(&error_str);
1078         return ret ?: ret_count;
1079 }
1080
1081 static const struct file_operations i915_error_state_fops = {
1082         .owner = THIS_MODULE,
1083         .open = i915_error_state_open,
1084         .read = i915_error_state_read,
1085         .write = i915_error_state_write,
1086         .llseek = default_llseek,
1087         .release = i915_error_state_release,
1088 };
1089
1090 static int
1091 i915_next_seqno_get(void *data, u64 *val)
1092 {
1093         struct drm_device *dev = data;
1094         struct drm_i915_private *dev_priv = dev->dev_private;
1095         int ret;
1096
1097         ret = mutex_lock_interruptible(&dev->struct_mutex);
1098         if (ret)
1099                 return ret;
1100
1101         *val = dev_priv->next_seqno;
1102         mutex_unlock(&dev->struct_mutex);
1103
1104         return 0;
1105 }
1106
1107 static int
1108 i915_next_seqno_set(void *data, u64 val)
1109 {
1110         struct drm_device *dev = data;
1111         int ret;
1112
1113         ret = mutex_lock_interruptible(&dev->struct_mutex);
1114         if (ret)
1115                 return ret;
1116
1117         ret = i915_gem_set_seqno(dev, val);
1118         mutex_unlock(&dev->struct_mutex);
1119
1120         return ret;
1121 }
1122
1123 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1124                         i915_next_seqno_get, i915_next_seqno_set,
1125                         "0x%llx\n");
1126
1127 static int i915_frequency_info(struct seq_file *m, void *unused)
1128 {
1129         struct drm_info_node *node = m->private;
1130         struct drm_device *dev = node->minor->dev;
1131         struct drm_i915_private *dev_priv = dev->dev_private;
1132         int ret = 0;
1133
1134         intel_runtime_pm_get(dev_priv);
1135
1136         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1137
1138         if (IS_GEN5(dev)) {
1139                 u16 rgvswctl = I915_READ16(MEMSWCTL);
1140                 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1141
1142                 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1143                 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1144                 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1145                            MEMSTAT_VID_SHIFT);
1146                 seq_printf(m, "Current P-state: %d\n",
1147                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1148         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1149                 u32 freq_sts;
1150
1151                 mutex_lock(&dev_priv->rps.hw_lock);
1152                 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1153                 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1154                 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1155
1156                 seq_printf(m, "actual GPU freq: %d MHz\n",
1157                            intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1158
1159                 seq_printf(m, "current GPU freq: %d MHz\n",
1160                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1161
1162                 seq_printf(m, "max GPU freq: %d MHz\n",
1163                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1164
1165                 seq_printf(m, "min GPU freq: %d MHz\n",
1166                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1167
1168                 seq_printf(m, "idle GPU freq: %d MHz\n",
1169                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1170
1171                 seq_printf(m,
1172                            "efficient (RPe) frequency: %d MHz\n",
1173                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1174                 mutex_unlock(&dev_priv->rps.hw_lock);
1175         } else if (INTEL_INFO(dev)->gen >= 6) {
1176                 u32 rp_state_limits;
1177                 u32 gt_perf_status;
1178                 u32 rp_state_cap;
1179                 u32 rpmodectl, rpinclimit, rpdeclimit;
1180                 u32 rpstat, cagf, reqf;
1181                 u32 rpupei, rpcurup, rpprevup;
1182                 u32 rpdownei, rpcurdown, rpprevdown;
1183                 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1184                 int max_freq;
1185
1186                 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1187                 if (IS_BROXTON(dev)) {
1188                         rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1189                         gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1190                 } else {
1191                         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1192                         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1193                 }
1194
1195                 /* RPSTAT1 is in the GT power well */
1196                 ret = mutex_lock_interruptible(&dev->struct_mutex);
1197                 if (ret)
1198                         goto out;
1199
1200                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1201
1202                 reqf = I915_READ(GEN6_RPNSWREQ);
1203                 if (IS_GEN9(dev))
1204                         reqf >>= 23;
1205                 else {
1206                         reqf &= ~GEN6_TURBO_DISABLE;
1207                         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1208                                 reqf >>= 24;
1209                         else
1210                                 reqf >>= 25;
1211                 }
1212                 reqf = intel_gpu_freq(dev_priv, reqf);
1213
1214                 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1215                 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1216                 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1217
1218                 rpstat = I915_READ(GEN6_RPSTAT1);
1219                 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1220                 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1221                 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1222                 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1223                 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1224                 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
1225                 if (IS_GEN9(dev))
1226                         cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1227                 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1228                         cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1229                 else
1230                         cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1231                 cagf = intel_gpu_freq(dev_priv, cagf);
1232
1233                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1234                 mutex_unlock(&dev->struct_mutex);
1235
1236                 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1237                         pm_ier = I915_READ(GEN6_PMIER);
1238                         pm_imr = I915_READ(GEN6_PMIMR);
1239                         pm_isr = I915_READ(GEN6_PMISR);
1240                         pm_iir = I915_READ(GEN6_PMIIR);
1241                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1242                 } else {
1243                         pm_ier = I915_READ(GEN8_GT_IER(2));
1244                         pm_imr = I915_READ(GEN8_GT_IMR(2));
1245                         pm_isr = I915_READ(GEN8_GT_ISR(2));
1246                         pm_iir = I915_READ(GEN8_GT_IIR(2));
1247                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1248                 }
1249                 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1250                            pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1251                 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1252                 seq_printf(m, "Render p-state ratio: %d\n",
1253                            (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
1254                 seq_printf(m, "Render p-state VID: %d\n",
1255                            gt_perf_status & 0xff);
1256                 seq_printf(m, "Render p-state limit: %d\n",
1257                            rp_state_limits & 0xff);
1258                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1259                 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1260                 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1261                 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1262                 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1263                 seq_printf(m, "CAGF: %dMHz\n", cagf);
1264                 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1265                            GEN6_CURICONT_MASK);
1266                 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1267                            GEN6_CURBSYTAVG_MASK);
1268                 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1269                            GEN6_CURBSYTAVG_MASK);
1270                 seq_printf(m, "Up threshold: %d%%\n",
1271                            dev_priv->rps.up_threshold);
1272
1273                 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1274                            GEN6_CURIAVG_MASK);
1275                 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1276                            GEN6_CURBSYTAVG_MASK);
1277                 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1278                            GEN6_CURBSYTAVG_MASK);
1279                 seq_printf(m, "Down threshold: %d%%\n",
1280                            dev_priv->rps.down_threshold);
1281
1282                 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 :
1283                             rp_state_cap >> 16) & 0xff;
1284                 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1285                              GEN9_FREQ_SCALER : 1);
1286                 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1287                            intel_gpu_freq(dev_priv, max_freq));
1288
1289                 max_freq = (rp_state_cap & 0xff00) >> 8;
1290                 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1291                              GEN9_FREQ_SCALER : 1);
1292                 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1293                            intel_gpu_freq(dev_priv, max_freq));
1294
1295                 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 :
1296                             rp_state_cap >> 0) & 0xff;
1297                 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1298                              GEN9_FREQ_SCALER : 1);
1299                 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1300                            intel_gpu_freq(dev_priv, max_freq));
1301                 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1302                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1303
1304                 seq_printf(m, "Current freq: %d MHz\n",
1305                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1306                 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1307                 seq_printf(m, "Idle freq: %d MHz\n",
1308                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1309                 seq_printf(m, "Min freq: %d MHz\n",
1310                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1311                 seq_printf(m, "Max freq: %d MHz\n",
1312                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1313                 seq_printf(m,
1314                            "efficient (RPe) frequency: %d MHz\n",
1315                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1316         } else {
1317                 seq_puts(m, "no P-state info available\n");
1318         }
1319
1320         seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
1321         seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1322         seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1323
1324 out:
1325         intel_runtime_pm_put(dev_priv);
1326         return ret;
1327 }
1328
1329 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1330 {
1331         struct drm_info_node *node = m->private;
1332         struct drm_device *dev = node->minor->dev;
1333         struct drm_i915_private *dev_priv = dev->dev_private;
1334         struct intel_engine_cs *ring;
1335         u64 acthd[I915_NUM_RINGS];
1336         u32 seqno[I915_NUM_RINGS];
1337         u32 instdone[I915_NUM_INSTDONE_REG];
1338         int i, j;
1339
1340         if (!i915.enable_hangcheck) {
1341                 seq_printf(m, "Hangcheck disabled\n");
1342                 return 0;
1343         }
1344
1345         intel_runtime_pm_get(dev_priv);
1346
1347         for_each_ring(ring, dev_priv, i) {
1348                 seqno[i] = ring->get_seqno(ring, false);
1349                 acthd[i] = intel_ring_get_active_head(ring);
1350         }
1351
1352         i915_get_extra_instdone(dev, instdone);
1353
1354         intel_runtime_pm_put(dev_priv);
1355
1356         if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1357                 seq_printf(m, "Hangcheck active, fires in %dms\n",
1358                            jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1359                                             jiffies));
1360         } else
1361                 seq_printf(m, "Hangcheck inactive\n");
1362
1363         for_each_ring(ring, dev_priv, i) {
1364                 seq_printf(m, "%s:\n", ring->name);
1365                 seq_printf(m, "\tseqno = %x [current %x]\n",
1366                            ring->hangcheck.seqno, seqno[i]);
1367                 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1368                            (long long)ring->hangcheck.acthd,
1369                            (long long)acthd[i]);
1370                 seq_printf(m, "\tscore = %d\n", ring->hangcheck.score);
1371                 seq_printf(m, "\taction = %d\n", ring->hangcheck.action);
1372
1373                 if (ring->id == RCS) {
1374                         seq_puts(m, "\tinstdone read =");
1375
1376                         for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1377                                 seq_printf(m, " 0x%08x", instdone[j]);
1378
1379                         seq_puts(m, "\n\tinstdone accu =");
1380
1381                         for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1382                                 seq_printf(m, " 0x%08x",
1383                                            ring->hangcheck.instdone[j]);
1384
1385                         seq_puts(m, "\n");
1386                 }
1387         }
1388
1389         return 0;
1390 }
1391
1392 static int ironlake_drpc_info(struct seq_file *m)
1393 {
1394         struct drm_info_node *node = m->private;
1395         struct drm_device *dev = node->minor->dev;
1396         struct drm_i915_private *dev_priv = dev->dev_private;
1397         u32 rgvmodectl, rstdbyctl;
1398         u16 crstandvid;
1399         int ret;
1400
1401         ret = mutex_lock_interruptible(&dev->struct_mutex);
1402         if (ret)
1403                 return ret;
1404         intel_runtime_pm_get(dev_priv);
1405
1406         rgvmodectl = I915_READ(MEMMODECTL);
1407         rstdbyctl = I915_READ(RSTDBYCTL);
1408         crstandvid = I915_READ16(CRSTANDVID);
1409
1410         intel_runtime_pm_put(dev_priv);
1411         mutex_unlock(&dev->struct_mutex);
1412
1413         seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1414         seq_printf(m, "Boost freq: %d\n",
1415                    (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1416                    MEMMODE_BOOST_FREQ_SHIFT);
1417         seq_printf(m, "HW control enabled: %s\n",
1418                    yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1419         seq_printf(m, "SW control enabled: %s\n",
1420                    yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1421         seq_printf(m, "Gated voltage change: %s\n",
1422                    yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1423         seq_printf(m, "Starting frequency: P%d\n",
1424                    (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1425         seq_printf(m, "Max P-state: P%d\n",
1426                    (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1427         seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1428         seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1429         seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1430         seq_printf(m, "Render standby enabled: %s\n",
1431                    yesno(!(rstdbyctl & RCX_SW_EXIT)));
1432         seq_puts(m, "Current RS state: ");
1433         switch (rstdbyctl & RSX_STATUS_MASK) {
1434         case RSX_STATUS_ON:
1435                 seq_puts(m, "on\n");
1436                 break;
1437         case RSX_STATUS_RC1:
1438                 seq_puts(m, "RC1\n");
1439                 break;
1440         case RSX_STATUS_RC1E:
1441                 seq_puts(m, "RC1E\n");
1442                 break;
1443         case RSX_STATUS_RS1:
1444                 seq_puts(m, "RS1\n");
1445                 break;
1446         case RSX_STATUS_RS2:
1447                 seq_puts(m, "RS2 (RC6)\n");
1448                 break;
1449         case RSX_STATUS_RS3:
1450                 seq_puts(m, "RC3 (RC6+)\n");
1451                 break;
1452         default:
1453                 seq_puts(m, "unknown\n");
1454                 break;
1455         }
1456
1457         return 0;
1458 }
1459
1460 static int i915_forcewake_domains(struct seq_file *m, void *data)
1461 {
1462         struct drm_info_node *node = m->private;
1463         struct drm_device *dev = node->minor->dev;
1464         struct drm_i915_private *dev_priv = dev->dev_private;
1465         struct intel_uncore_forcewake_domain *fw_domain;
1466         int i;
1467
1468         spin_lock_irq(&dev_priv->uncore.lock);
1469         for_each_fw_domain(fw_domain, dev_priv, i) {
1470                 seq_printf(m, "%s.wake_count = %u\n",
1471                            intel_uncore_forcewake_domain_to_str(i),
1472                            fw_domain->wake_count);
1473         }
1474         spin_unlock_irq(&dev_priv->uncore.lock);
1475
1476         return 0;
1477 }
1478
1479 static int vlv_drpc_info(struct seq_file *m)
1480 {
1481         struct drm_info_node *node = m->private;
1482         struct drm_device *dev = node->minor->dev;
1483         struct drm_i915_private *dev_priv = dev->dev_private;
1484         u32 rpmodectl1, rcctl1, pw_status;
1485
1486         intel_runtime_pm_get(dev_priv);
1487
1488         pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1489         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1490         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1491
1492         intel_runtime_pm_put(dev_priv);
1493
1494         seq_printf(m, "Video Turbo Mode: %s\n",
1495                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1496         seq_printf(m, "Turbo enabled: %s\n",
1497                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1498         seq_printf(m, "HW control enabled: %s\n",
1499                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1500         seq_printf(m, "SW control enabled: %s\n",
1501                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1502                           GEN6_RP_MEDIA_SW_MODE));
1503         seq_printf(m, "RC6 Enabled: %s\n",
1504                    yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1505                                         GEN6_RC_CTL_EI_MODE(1))));
1506         seq_printf(m, "Render Power Well: %s\n",
1507                    (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1508         seq_printf(m, "Media Power Well: %s\n",
1509                    (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1510
1511         seq_printf(m, "Render RC6 residency since boot: %u\n",
1512                    I915_READ(VLV_GT_RENDER_RC6));
1513         seq_printf(m, "Media RC6 residency since boot: %u\n",
1514                    I915_READ(VLV_GT_MEDIA_RC6));
1515
1516         return i915_forcewake_domains(m, NULL);
1517 }
1518
1519 static int gen6_drpc_info(struct seq_file *m)
1520 {
1521         struct drm_info_node *node = m->private;
1522         struct drm_device *dev = node->minor->dev;
1523         struct drm_i915_private *dev_priv = dev->dev_private;
1524         u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1525         unsigned forcewake_count;
1526         int count = 0, ret;
1527
1528         ret = mutex_lock_interruptible(&dev->struct_mutex);
1529         if (ret)
1530                 return ret;
1531         intel_runtime_pm_get(dev_priv);
1532
1533         spin_lock_irq(&dev_priv->uncore.lock);
1534         forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1535         spin_unlock_irq(&dev_priv->uncore.lock);
1536
1537         if (forcewake_count) {
1538                 seq_puts(m, "RC information inaccurate because somebody "
1539                             "holds a forcewake reference \n");
1540         } else {
1541                 /* NB: we cannot use forcewake, else we read the wrong values */
1542                 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1543                         udelay(10);
1544                 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1545         }
1546
1547         gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1548         trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1549
1550         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1551         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1552         mutex_unlock(&dev->struct_mutex);
1553         mutex_lock(&dev_priv->rps.hw_lock);
1554         sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1555         mutex_unlock(&dev_priv->rps.hw_lock);
1556
1557         intel_runtime_pm_put(dev_priv);
1558
1559         seq_printf(m, "Video Turbo Mode: %s\n",
1560                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1561         seq_printf(m, "HW control enabled: %s\n",
1562                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1563         seq_printf(m, "SW control enabled: %s\n",
1564                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1565                           GEN6_RP_MEDIA_SW_MODE));
1566         seq_printf(m, "RC1e Enabled: %s\n",
1567                    yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1568         seq_printf(m, "RC6 Enabled: %s\n",
1569                    yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1570         seq_printf(m, "Deep RC6 Enabled: %s\n",
1571                    yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1572         seq_printf(m, "Deepest RC6 Enabled: %s\n",
1573                    yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1574         seq_puts(m, "Current RC state: ");
1575         switch (gt_core_status & GEN6_RCn_MASK) {
1576         case GEN6_RC0:
1577                 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1578                         seq_puts(m, "Core Power Down\n");
1579                 else
1580                         seq_puts(m, "on\n");
1581                 break;
1582         case GEN6_RC3:
1583                 seq_puts(m, "RC3\n");
1584                 break;
1585         case GEN6_RC6:
1586                 seq_puts(m, "RC6\n");
1587                 break;
1588         case GEN6_RC7:
1589                 seq_puts(m, "RC7\n");
1590                 break;
1591         default:
1592                 seq_puts(m, "Unknown\n");
1593                 break;
1594         }
1595
1596         seq_printf(m, "Core Power Down: %s\n",
1597                    yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1598
1599         /* Not exactly sure what this is */
1600         seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1601                    I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1602         seq_printf(m, "RC6 residency since boot: %u\n",
1603                    I915_READ(GEN6_GT_GFX_RC6));
1604         seq_printf(m, "RC6+ residency since boot: %u\n",
1605                    I915_READ(GEN6_GT_GFX_RC6p));
1606         seq_printf(m, "RC6++ residency since boot: %u\n",
1607                    I915_READ(GEN6_GT_GFX_RC6pp));
1608
1609         seq_printf(m, "RC6   voltage: %dmV\n",
1610                    GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1611         seq_printf(m, "RC6+  voltage: %dmV\n",
1612                    GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1613         seq_printf(m, "RC6++ voltage: %dmV\n",
1614                    GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1615         return 0;
1616 }
1617
1618 static int i915_drpc_info(struct seq_file *m, void *unused)
1619 {
1620         struct drm_info_node *node = m->private;
1621         struct drm_device *dev = node->minor->dev;
1622
1623         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
1624                 return vlv_drpc_info(m);
1625         else if (INTEL_INFO(dev)->gen >= 6)
1626                 return gen6_drpc_info(m);
1627         else
1628                 return ironlake_drpc_info(m);
1629 }
1630
1631 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1632 {
1633         struct drm_info_node *node = m->private;
1634         struct drm_device *dev = node->minor->dev;
1635         struct drm_i915_private *dev_priv = dev->dev_private;
1636
1637         seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1638                    dev_priv->fb_tracking.busy_bits);
1639
1640         seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1641                    dev_priv->fb_tracking.flip_bits);
1642
1643         return 0;
1644 }
1645
1646 static int i915_fbc_status(struct seq_file *m, void *unused)
1647 {
1648         struct drm_info_node *node = m->private;
1649         struct drm_device *dev = node->minor->dev;
1650         struct drm_i915_private *dev_priv = dev->dev_private;
1651
1652         if (!HAS_FBC(dev)) {
1653                 seq_puts(m, "FBC unsupported on this chipset\n");
1654                 return 0;
1655         }
1656
1657         intel_runtime_pm_get(dev_priv);
1658         mutex_lock(&dev_priv->fbc.lock);
1659
1660         if (intel_fbc_is_active(dev_priv))
1661                 seq_puts(m, "FBC enabled\n");
1662         else
1663                 seq_printf(m, "FBC disabled: %s\n",
1664                            dev_priv->fbc.no_fbc_reason);
1665
1666         if (INTEL_INFO(dev_priv)->gen >= 7)
1667                 seq_printf(m, "Compressing: %s\n",
1668                            yesno(I915_READ(FBC_STATUS2) &
1669                                  FBC_COMPRESSION_MASK));
1670
1671         mutex_unlock(&dev_priv->fbc.lock);
1672         intel_runtime_pm_put(dev_priv);
1673
1674         return 0;
1675 }
1676
1677 static int i915_fbc_fc_get(void *data, u64 *val)
1678 {
1679         struct drm_device *dev = data;
1680         struct drm_i915_private *dev_priv = dev->dev_private;
1681
1682         if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1683                 return -ENODEV;
1684
1685         *val = dev_priv->fbc.false_color;
1686
1687         return 0;
1688 }
1689
1690 static int i915_fbc_fc_set(void *data, u64 val)
1691 {
1692         struct drm_device *dev = data;
1693         struct drm_i915_private *dev_priv = dev->dev_private;
1694         u32 reg;
1695
1696         if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1697                 return -ENODEV;
1698
1699         mutex_lock(&dev_priv->fbc.lock);
1700
1701         reg = I915_READ(ILK_DPFC_CONTROL);
1702         dev_priv->fbc.false_color = val;
1703
1704         I915_WRITE(ILK_DPFC_CONTROL, val ?
1705                    (reg | FBC_CTL_FALSE_COLOR) :
1706                    (reg & ~FBC_CTL_FALSE_COLOR));
1707
1708         mutex_unlock(&dev_priv->fbc.lock);
1709         return 0;
1710 }
1711
1712 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1713                         i915_fbc_fc_get, i915_fbc_fc_set,
1714                         "%llu\n");
1715
1716 static int i915_ips_status(struct seq_file *m, void *unused)
1717 {
1718         struct drm_info_node *node = m->private;
1719         struct drm_device *dev = node->minor->dev;
1720         struct drm_i915_private *dev_priv = dev->dev_private;
1721
1722         if (!HAS_IPS(dev)) {
1723                 seq_puts(m, "not supported\n");
1724                 return 0;
1725         }
1726
1727         intel_runtime_pm_get(dev_priv);
1728
1729         seq_printf(m, "Enabled by kernel parameter: %s\n",
1730                    yesno(i915.enable_ips));
1731
1732         if (INTEL_INFO(dev)->gen >= 8) {
1733                 seq_puts(m, "Currently: unknown\n");
1734         } else {
1735                 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1736                         seq_puts(m, "Currently: enabled\n");
1737                 else
1738                         seq_puts(m, "Currently: disabled\n");
1739         }
1740
1741         intel_runtime_pm_put(dev_priv);
1742
1743         return 0;
1744 }
1745
1746 static int i915_sr_status(struct seq_file *m, void *unused)
1747 {
1748         struct drm_info_node *node = m->private;
1749         struct drm_device *dev = node->minor->dev;
1750         struct drm_i915_private *dev_priv = dev->dev_private;
1751         bool sr_enabled = false;
1752
1753         intel_runtime_pm_get(dev_priv);
1754
1755         if (HAS_PCH_SPLIT(dev))
1756                 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1757         else if (IS_CRESTLINE(dev) || IS_G4X(dev) ||
1758                  IS_I945G(dev) || IS_I945GM(dev))
1759                 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1760         else if (IS_I915GM(dev))
1761                 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1762         else if (IS_PINEVIEW(dev))
1763                 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1764         else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
1765                 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1766
1767         intel_runtime_pm_put(dev_priv);
1768
1769         seq_printf(m, "self-refresh: %s\n",
1770                    sr_enabled ? "enabled" : "disabled");
1771
1772         return 0;
1773 }
1774
1775 static int i915_emon_status(struct seq_file *m, void *unused)
1776 {
1777         struct drm_info_node *node = m->private;
1778         struct drm_device *dev = node->minor->dev;
1779         struct drm_i915_private *dev_priv = dev->dev_private;
1780         unsigned long temp, chipset, gfx;
1781         int ret;
1782
1783         if (!IS_GEN5(dev))
1784                 return -ENODEV;
1785
1786         ret = mutex_lock_interruptible(&dev->struct_mutex);
1787         if (ret)
1788                 return ret;
1789
1790         temp = i915_mch_val(dev_priv);
1791         chipset = i915_chipset_val(dev_priv);
1792         gfx = i915_gfx_val(dev_priv);
1793         mutex_unlock(&dev->struct_mutex);
1794
1795         seq_printf(m, "GMCH temp: %ld\n", temp);
1796         seq_printf(m, "Chipset power: %ld\n", chipset);
1797         seq_printf(m, "GFX power: %ld\n", gfx);
1798         seq_printf(m, "Total power: %ld\n", chipset + gfx);
1799
1800         return 0;
1801 }
1802
1803 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1804 {
1805         struct drm_info_node *node = m->private;
1806         struct drm_device *dev = node->minor->dev;
1807         struct drm_i915_private *dev_priv = dev->dev_private;
1808         int ret = 0;
1809         int gpu_freq, ia_freq;
1810         unsigned int max_gpu_freq, min_gpu_freq;
1811
1812         if (!HAS_CORE_RING_FREQ(dev)) {
1813                 seq_puts(m, "unsupported on this chipset\n");
1814                 return 0;
1815         }
1816
1817         intel_runtime_pm_get(dev_priv);
1818
1819         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1820
1821         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1822         if (ret)
1823                 goto out;
1824
1825         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
1826                 /* Convert GT frequency to 50 HZ units */
1827                 min_gpu_freq =
1828                         dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1829                 max_gpu_freq =
1830                         dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1831         } else {
1832                 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1833                 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1834         }
1835
1836         seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1837
1838         for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1839                 ia_freq = gpu_freq;
1840                 sandybridge_pcode_read(dev_priv,
1841                                        GEN6_PCODE_READ_MIN_FREQ_TABLE,
1842                                        &ia_freq);
1843                 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1844                            intel_gpu_freq(dev_priv, (gpu_freq *
1845                                 (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1846                                  GEN9_FREQ_SCALER : 1))),
1847                            ((ia_freq >> 0) & 0xff) * 100,
1848                            ((ia_freq >> 8) & 0xff) * 100);
1849         }
1850
1851         mutex_unlock(&dev_priv->rps.hw_lock);
1852
1853 out:
1854         intel_runtime_pm_put(dev_priv);
1855         return ret;
1856 }
1857
1858 static int i915_opregion(struct seq_file *m, void *unused)
1859 {
1860         struct drm_info_node *node = m->private;
1861         struct drm_device *dev = node->minor->dev;
1862         struct drm_i915_private *dev_priv = dev->dev_private;
1863         struct intel_opregion *opregion = &dev_priv->opregion;
1864         int ret;
1865
1866         ret = mutex_lock_interruptible(&dev->struct_mutex);
1867         if (ret)
1868                 goto out;
1869
1870         if (opregion->header)
1871                 seq_write(m, opregion->header, OPREGION_SIZE);
1872
1873         mutex_unlock(&dev->struct_mutex);
1874
1875 out:
1876         return 0;
1877 }
1878
1879 static int i915_vbt(struct seq_file *m, void *unused)
1880 {
1881         struct drm_info_node *node = m->private;
1882         struct drm_device *dev = node->minor->dev;
1883         struct drm_i915_private *dev_priv = dev->dev_private;
1884         struct intel_opregion *opregion = &dev_priv->opregion;
1885
1886         if (opregion->vbt)
1887                 seq_write(m, opregion->vbt, opregion->vbt_size);
1888
1889         return 0;
1890 }
1891
1892 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1893 {
1894         struct drm_info_node *node = m->private;
1895         struct drm_device *dev = node->minor->dev;
1896         struct intel_framebuffer *fbdev_fb = NULL;
1897         struct drm_framebuffer *drm_fb;
1898
1899 #ifdef CONFIG_DRM_FBDEV_EMULATION
1900        if (to_i915(dev)->fbdev) {
1901                fbdev_fb = to_intel_framebuffer(to_i915(dev)->fbdev->helper.fb);
1902
1903                seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1904                          fbdev_fb->base.width,
1905                          fbdev_fb->base.height,
1906                          fbdev_fb->base.depth,
1907                          fbdev_fb->base.bits_per_pixel,
1908                          fbdev_fb->base.modifier[0],
1909                          atomic_read(&fbdev_fb->base.refcount.refcount));
1910                describe_obj(m, fbdev_fb->obj);
1911                seq_putc(m, '\n');
1912        }
1913 #endif
1914
1915         mutex_lock(&dev->mode_config.fb_lock);
1916         drm_for_each_fb(drm_fb, dev) {
1917                 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
1918                 if (fb == fbdev_fb)
1919                         continue;
1920
1921                 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1922                            fb->base.width,
1923                            fb->base.height,
1924                            fb->base.depth,
1925                            fb->base.bits_per_pixel,
1926                            fb->base.modifier[0],
1927                            atomic_read(&fb->base.refcount.refcount));
1928                 describe_obj(m, fb->obj);
1929                 seq_putc(m, '\n');
1930         }
1931         mutex_unlock(&dev->mode_config.fb_lock);
1932
1933         return 0;
1934 }
1935
1936 static void describe_ctx_ringbuf(struct seq_file *m,
1937                                  struct intel_ringbuffer *ringbuf)
1938 {
1939         seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1940                    ringbuf->space, ringbuf->head, ringbuf->tail,
1941                    ringbuf->last_retired_head);
1942 }
1943
1944 static int i915_context_status(struct seq_file *m, void *unused)
1945 {
1946         struct drm_info_node *node = m->private;
1947         struct drm_device *dev = node->minor->dev;
1948         struct drm_i915_private *dev_priv = dev->dev_private;
1949         struct intel_engine_cs *ring;
1950         struct intel_context *ctx;
1951         int ret, i;
1952
1953         ret = mutex_lock_interruptible(&dev->struct_mutex);
1954         if (ret)
1955                 return ret;
1956
1957         list_for_each_entry(ctx, &dev_priv->context_list, link) {
1958                 if (!i915.enable_execlists &&
1959                     ctx->legacy_hw_ctx.rcs_state == NULL)
1960                         continue;
1961
1962                 seq_puts(m, "HW context ");
1963                 describe_ctx(m, ctx);
1964                 if (ctx == dev_priv->kernel_context)
1965                         seq_printf(m, "(kernel context) ");
1966
1967                 if (i915.enable_execlists) {
1968                         seq_putc(m, '\n');
1969                         for_each_ring(ring, dev_priv, i) {
1970                                 struct drm_i915_gem_object *ctx_obj =
1971                                         ctx->engine[i].state;
1972                                 struct intel_ringbuffer *ringbuf =
1973                                         ctx->engine[i].ringbuf;
1974
1975                                 seq_printf(m, "%s: ", ring->name);
1976                                 if (ctx_obj)
1977                                         describe_obj(m, ctx_obj);
1978                                 if (ringbuf)
1979                                         describe_ctx_ringbuf(m, ringbuf);
1980                                 seq_putc(m, '\n');
1981                         }
1982                 } else {
1983                         describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1984                 }
1985
1986                 seq_putc(m, '\n');
1987         }
1988
1989         mutex_unlock(&dev->struct_mutex);
1990
1991         return 0;
1992 }
1993
1994 static void i915_dump_lrc_obj(struct seq_file *m,
1995                               struct intel_context *ctx,
1996                               struct intel_engine_cs *ring)
1997 {
1998         struct page *page;
1999         uint32_t *reg_state;
2000         int j;
2001         struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state;
2002         unsigned long ggtt_offset = 0;
2003
2004         if (ctx_obj == NULL) {
2005                 seq_printf(m, "Context on %s with no gem object\n",
2006                            ring->name);
2007                 return;
2008         }
2009
2010         seq_printf(m, "CONTEXT: %s %u\n", ring->name,
2011                    intel_execlists_ctx_id(ctx, ring));
2012
2013         if (!i915_gem_obj_ggtt_bound(ctx_obj))
2014                 seq_puts(m, "\tNot bound in GGTT\n");
2015         else
2016                 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
2017
2018         if (i915_gem_object_get_pages(ctx_obj)) {
2019                 seq_puts(m, "\tFailed to get pages for context object\n");
2020                 return;
2021         }
2022
2023         page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
2024         if (!WARN_ON(page == NULL)) {
2025                 reg_state = kmap_atomic(page);
2026
2027                 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2028                         seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2029                                    ggtt_offset + 4096 + (j * 4),
2030                                    reg_state[j], reg_state[j + 1],
2031                                    reg_state[j + 2], reg_state[j + 3]);
2032                 }
2033                 kunmap_atomic(reg_state);
2034         }
2035
2036         seq_putc(m, '\n');
2037 }
2038
2039 static int i915_dump_lrc(struct seq_file *m, void *unused)
2040 {
2041         struct drm_info_node *node = (struct drm_info_node *) m->private;
2042         struct drm_device *dev = node->minor->dev;
2043         struct drm_i915_private *dev_priv = dev->dev_private;
2044         struct intel_engine_cs *ring;
2045         struct intel_context *ctx;
2046         int ret, i;
2047
2048         if (!i915.enable_execlists) {
2049                 seq_printf(m, "Logical Ring Contexts are disabled\n");
2050                 return 0;
2051         }
2052
2053         ret = mutex_lock_interruptible(&dev->struct_mutex);
2054         if (ret)
2055                 return ret;
2056
2057         list_for_each_entry(ctx, &dev_priv->context_list, link)
2058                 if (ctx != dev_priv->kernel_context)
2059                         for_each_ring(ring, dev_priv, i)
2060                                 i915_dump_lrc_obj(m, ctx, ring);
2061
2062         mutex_unlock(&dev->struct_mutex);
2063
2064         return 0;
2065 }
2066
2067 static int i915_execlists(struct seq_file *m, void *data)
2068 {
2069         struct drm_info_node *node = (struct drm_info_node *)m->private;
2070         struct drm_device *dev = node->minor->dev;
2071         struct drm_i915_private *dev_priv = dev->dev_private;
2072         struct intel_engine_cs *ring;
2073         u32 status_pointer;
2074         u8 read_pointer;
2075         u8 write_pointer;
2076         u32 status;
2077         u32 ctx_id;
2078         struct list_head *cursor;
2079         int ring_id, i;
2080         int ret;
2081
2082         if (!i915.enable_execlists) {
2083                 seq_puts(m, "Logical Ring Contexts are disabled\n");
2084                 return 0;
2085         }
2086
2087         ret = mutex_lock_interruptible(&dev->struct_mutex);
2088         if (ret)
2089                 return ret;
2090
2091         intel_runtime_pm_get(dev_priv);
2092
2093         for_each_ring(ring, dev_priv, ring_id) {
2094                 struct drm_i915_gem_request *head_req = NULL;
2095                 int count = 0;
2096                 unsigned long flags;
2097
2098                 seq_printf(m, "%s\n", ring->name);
2099
2100                 status = I915_READ(RING_EXECLIST_STATUS_LO(ring));
2101                 ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(ring));
2102                 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2103                            status, ctx_id);
2104
2105                 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
2106                 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2107
2108                 read_pointer = ring->next_context_status_buffer;
2109                 write_pointer = GEN8_CSB_WRITE_PTR(status_pointer);
2110                 if (read_pointer > write_pointer)
2111                         write_pointer += GEN8_CSB_ENTRIES;
2112                 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2113                            read_pointer, write_pointer);
2114
2115                 for (i = 0; i < GEN8_CSB_ENTRIES; i++) {
2116                         status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(ring, i));
2117                         ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(ring, i));
2118
2119                         seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2120                                    i, status, ctx_id);
2121                 }
2122
2123                 spin_lock_irqsave(&ring->execlist_lock, flags);
2124                 list_for_each(cursor, &ring->execlist_queue)
2125                         count++;
2126                 head_req = list_first_entry_or_null(&ring->execlist_queue,
2127                                 struct drm_i915_gem_request, execlist_link);
2128                 spin_unlock_irqrestore(&ring->execlist_lock, flags);
2129
2130                 seq_printf(m, "\t%d requests in queue\n", count);
2131                 if (head_req) {
2132                         seq_printf(m, "\tHead request id: %u\n",
2133                                    intel_execlists_ctx_id(head_req->ctx, ring));
2134                         seq_printf(m, "\tHead request tail: %u\n",
2135                                    head_req->tail);
2136                 }
2137
2138                 seq_putc(m, '\n');
2139         }
2140
2141         intel_runtime_pm_put(dev_priv);
2142         mutex_unlock(&dev->struct_mutex);
2143
2144         return 0;
2145 }
2146
2147 static const char *swizzle_string(unsigned swizzle)
2148 {
2149         switch (swizzle) {
2150         case I915_BIT_6_SWIZZLE_NONE:
2151                 return "none";
2152         case I915_BIT_6_SWIZZLE_9:
2153                 return "bit9";
2154         case I915_BIT_6_SWIZZLE_9_10:
2155                 return "bit9/bit10";
2156         case I915_BIT_6_SWIZZLE_9_11:
2157                 return "bit9/bit11";
2158         case I915_BIT_6_SWIZZLE_9_10_11:
2159                 return "bit9/bit10/bit11";
2160         case I915_BIT_6_SWIZZLE_9_17:
2161                 return "bit9/bit17";
2162         case I915_BIT_6_SWIZZLE_9_10_17:
2163                 return "bit9/bit10/bit17";
2164         case I915_BIT_6_SWIZZLE_UNKNOWN:
2165                 return "unknown";
2166         }
2167
2168         return "bug";
2169 }
2170
2171 static int i915_swizzle_info(struct seq_file *m, void *data)
2172 {
2173         struct drm_info_node *node = m->private;
2174         struct drm_device *dev = node->minor->dev;
2175         struct drm_i915_private *dev_priv = dev->dev_private;
2176         int ret;
2177
2178         ret = mutex_lock_interruptible(&dev->struct_mutex);
2179         if (ret)
2180                 return ret;
2181         intel_runtime_pm_get(dev_priv);
2182
2183         seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2184                    swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2185         seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2186                    swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2187
2188         if (IS_GEN3(dev) || IS_GEN4(dev)) {
2189                 seq_printf(m, "DDC = 0x%08x\n",
2190                            I915_READ(DCC));
2191                 seq_printf(m, "DDC2 = 0x%08x\n",
2192                            I915_READ(DCC2));
2193                 seq_printf(m, "C0DRB3 = 0x%04x\n",
2194                            I915_READ16(C0DRB3));
2195                 seq_printf(m, "C1DRB3 = 0x%04x\n",
2196                            I915_READ16(C1DRB3));
2197         } else if (INTEL_INFO(dev)->gen >= 6) {
2198                 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2199                            I915_READ(MAD_DIMM_C0));
2200                 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2201                            I915_READ(MAD_DIMM_C1));
2202                 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2203                            I915_READ(MAD_DIMM_C2));
2204                 seq_printf(m, "TILECTL = 0x%08x\n",
2205                            I915_READ(TILECTL));
2206                 if (INTEL_INFO(dev)->gen >= 8)
2207                         seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2208                                    I915_READ(GAMTARBMODE));
2209                 else
2210                         seq_printf(m, "ARB_MODE = 0x%08x\n",
2211                                    I915_READ(ARB_MODE));
2212                 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2213                            I915_READ(DISP_ARB_CTL));
2214         }
2215
2216         if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2217                 seq_puts(m, "L-shaped memory detected\n");
2218
2219         intel_runtime_pm_put(dev_priv);
2220         mutex_unlock(&dev->struct_mutex);
2221
2222         return 0;
2223 }
2224
2225 static int per_file_ctx(int id, void *ptr, void *data)
2226 {
2227         struct intel_context *ctx = ptr;
2228         struct seq_file *m = data;
2229         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2230
2231         if (!ppgtt) {
2232                 seq_printf(m, "  no ppgtt for context %d\n",
2233                            ctx->user_handle);
2234                 return 0;
2235         }
2236
2237         if (i915_gem_context_is_default(ctx))
2238                 seq_puts(m, "  default context:\n");
2239         else
2240                 seq_printf(m, "  context %d:\n", ctx->user_handle);
2241         ppgtt->debug_dump(ppgtt, m);
2242
2243         return 0;
2244 }
2245
2246 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2247 {
2248         struct drm_i915_private *dev_priv = dev->dev_private;
2249         struct intel_engine_cs *ring;
2250         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2251         int unused, i;
2252
2253         if (!ppgtt)
2254                 return;
2255
2256         for_each_ring(ring, dev_priv, unused) {
2257                 seq_printf(m, "%s\n", ring->name);
2258                 for (i = 0; i < 4; i++) {
2259                         u64 pdp = I915_READ(GEN8_RING_PDP_UDW(ring, i));
2260                         pdp <<= 32;
2261                         pdp |= I915_READ(GEN8_RING_PDP_LDW(ring, i));
2262                         seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2263                 }
2264         }
2265 }
2266
2267 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2268 {
2269         struct drm_i915_private *dev_priv = dev->dev_private;
2270         struct intel_engine_cs *ring;
2271         int i;
2272
2273         if (INTEL_INFO(dev)->gen == 6)
2274                 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2275
2276         for_each_ring(ring, dev_priv, i) {
2277                 seq_printf(m, "%s\n", ring->name);
2278                 if (INTEL_INFO(dev)->gen == 7)
2279                         seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
2280                 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
2281                 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
2282                 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
2283         }
2284         if (dev_priv->mm.aliasing_ppgtt) {
2285                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2286
2287                 seq_puts(m, "aliasing PPGTT:\n");
2288                 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2289
2290                 ppgtt->debug_dump(ppgtt, m);
2291         }
2292
2293         seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2294 }
2295
2296 static int i915_ppgtt_info(struct seq_file *m, void *data)
2297 {
2298         struct drm_info_node *node = m->private;
2299         struct drm_device *dev = node->minor->dev;
2300         struct drm_i915_private *dev_priv = dev->dev_private;
2301         struct drm_file *file;
2302
2303         int ret = mutex_lock_interruptible(&dev->struct_mutex);
2304         if (ret)
2305                 return ret;
2306         intel_runtime_pm_get(dev_priv);
2307
2308         if (INTEL_INFO(dev)->gen >= 8)
2309                 gen8_ppgtt_info(m, dev);
2310         else if (INTEL_INFO(dev)->gen >= 6)
2311                 gen6_ppgtt_info(m, dev);
2312
2313         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2314                 struct drm_i915_file_private *file_priv = file->driver_priv;
2315                 struct task_struct *task;
2316
2317                 task = get_pid_task(file->pid, PIDTYPE_PID);
2318                 if (!task) {
2319                         ret = -ESRCH;
2320                         goto out_put;
2321                 }
2322                 seq_printf(m, "\nproc: %s\n", task->comm);
2323                 put_task_struct(task);
2324                 idr_for_each(&file_priv->context_idr, per_file_ctx,
2325                              (void *)(unsigned long)m);
2326         }
2327
2328 out_put:
2329         intel_runtime_pm_put(dev_priv);
2330         mutex_unlock(&dev->struct_mutex);
2331
2332         return ret;
2333 }
2334
2335 static int count_irq_waiters(struct drm_i915_private *i915)
2336 {
2337         struct intel_engine_cs *ring;
2338         int count = 0;
2339         int i;
2340
2341         for_each_ring(ring, i915, i)
2342                 count += ring->irq_refcount;
2343
2344         return count;
2345 }
2346
2347 static int i915_rps_boost_info(struct seq_file *m, void *data)
2348 {
2349         struct drm_info_node *node = m->private;
2350         struct drm_device *dev = node->minor->dev;
2351         struct drm_i915_private *dev_priv = dev->dev_private;
2352         struct drm_file *file;
2353
2354         seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2355         seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy);
2356         seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2357         seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2358                    intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2359                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2360                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2361                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2362                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2363         spin_lock(&dev_priv->rps.client_lock);
2364         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2365                 struct drm_i915_file_private *file_priv = file->driver_priv;
2366                 struct task_struct *task;
2367
2368                 rcu_read_lock();
2369                 task = pid_task(file->pid, PIDTYPE_PID);
2370                 seq_printf(m, "%s [%d]: %d boosts%s\n",
2371                            task ? task->comm : "<unknown>",
2372                            task ? task->pid : -1,
2373                            file_priv->rps.boosts,
2374                            list_empty(&file_priv->rps.link) ? "" : ", active");
2375                 rcu_read_unlock();
2376         }
2377         seq_printf(m, "Semaphore boosts: %d%s\n",
2378                    dev_priv->rps.semaphores.boosts,
2379                    list_empty(&dev_priv->rps.semaphores.link) ? "" : ", active");
2380         seq_printf(m, "MMIO flip boosts: %d%s\n",
2381                    dev_priv->rps.mmioflips.boosts,
2382                    list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active");
2383         seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts);
2384         spin_unlock(&dev_priv->rps.client_lock);
2385
2386         return 0;
2387 }
2388
2389 static int i915_llc(struct seq_file *m, void *data)
2390 {
2391         struct drm_info_node *node = m->private;
2392         struct drm_device *dev = node->minor->dev;
2393         struct drm_i915_private *dev_priv = dev->dev_private;
2394
2395         /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2396         seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2397         seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2398
2399         return 0;
2400 }
2401
2402 static int i915_guc_load_status_info(struct seq_file *m, void *data)
2403 {
2404         struct drm_info_node *node = m->private;
2405         struct drm_i915_private *dev_priv = node->minor->dev->dev_private;
2406         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
2407         u32 tmp, i;
2408
2409         if (!HAS_GUC_UCODE(dev_priv->dev))
2410                 return 0;
2411
2412         seq_printf(m, "GuC firmware status:\n");
2413         seq_printf(m, "\tpath: %s\n",
2414                 guc_fw->guc_fw_path);
2415         seq_printf(m, "\tfetch: %s\n",
2416                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
2417         seq_printf(m, "\tload: %s\n",
2418                 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
2419         seq_printf(m, "\tversion wanted: %d.%d\n",
2420                 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2421         seq_printf(m, "\tversion found: %d.%d\n",
2422                 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
2423         seq_printf(m, "\theader: offset is %d; size = %d\n",
2424                 guc_fw->header_offset, guc_fw->header_size);
2425         seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2426                 guc_fw->ucode_offset, guc_fw->ucode_size);
2427         seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2428                 guc_fw->rsa_offset, guc_fw->rsa_size);
2429
2430         tmp = I915_READ(GUC_STATUS);
2431
2432         seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2433         seq_printf(m, "\tBootrom status = 0x%x\n",
2434                 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2435         seq_printf(m, "\tuKernel status = 0x%x\n",
2436                 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2437         seq_printf(m, "\tMIA Core status = 0x%x\n",
2438                 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2439         seq_puts(m, "\nScratch registers:\n");
2440         for (i = 0; i < 16; i++)
2441                 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2442
2443         return 0;
2444 }
2445
2446 static void i915_guc_client_info(struct seq_file *m,
2447                                  struct drm_i915_private *dev_priv,
2448                                  struct i915_guc_client *client)
2449 {
2450         struct intel_engine_cs *ring;
2451         uint64_t tot = 0;
2452         uint32_t i;
2453
2454         seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2455                 client->priority, client->ctx_index, client->proc_desc_offset);
2456         seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2457                 client->doorbell_id, client->doorbell_offset, client->cookie);
2458         seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2459                 client->wq_size, client->wq_offset, client->wq_tail);
2460
2461         seq_printf(m, "\tFailed to queue: %u\n", client->q_fail);
2462         seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2463         seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2464
2465         for_each_ring(ring, dev_priv, i) {
2466                 seq_printf(m, "\tSubmissions: %llu %s\n",
2467                                 client->submissions[ring->guc_id],
2468                                 ring->name);
2469                 tot += client->submissions[ring->guc_id];
2470         }
2471         seq_printf(m, "\tTotal: %llu\n", tot);
2472 }
2473
2474 static int i915_guc_info(struct seq_file *m, void *data)
2475 {
2476         struct drm_info_node *node = m->private;
2477         struct drm_device *dev = node->minor->dev;
2478         struct drm_i915_private *dev_priv = dev->dev_private;
2479         struct intel_guc guc;
2480         struct i915_guc_client client = {};
2481         struct intel_engine_cs *ring;
2482         enum intel_ring_id i;
2483         u64 total = 0;
2484
2485         if (!HAS_GUC_SCHED(dev_priv->dev))
2486                 return 0;
2487
2488         if (mutex_lock_interruptible(&dev->struct_mutex))
2489                 return 0;
2490
2491         /* Take a local copy of the GuC data, so we can dump it at leisure */
2492         guc = dev_priv->guc;
2493         if (guc.execbuf_client)
2494                 client = *guc.execbuf_client;
2495
2496         mutex_unlock(&dev->struct_mutex);
2497
2498         seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
2499         seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
2500         seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
2501         seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
2502         seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
2503
2504         seq_printf(m, "\nGuC submissions:\n");
2505         for_each_ring(ring, dev_priv, i) {
2506                 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",
2507                         ring->name, guc.submissions[ring->guc_id],
2508                         guc.last_seqno[ring->guc_id]);
2509                 total += guc.submissions[ring->guc_id];
2510         }
2511         seq_printf(m, "\t%s: %llu\n", "Total", total);
2512
2513         seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
2514         i915_guc_client_info(m, dev_priv, &client);
2515
2516         /* Add more as required ... */
2517
2518         return 0;
2519 }
2520
2521 static int i915_guc_log_dump(struct seq_file *m, void *data)
2522 {
2523         struct drm_info_node *node = m->private;
2524         struct drm_device *dev = node->minor->dev;
2525         struct drm_i915_private *dev_priv = dev->dev_private;
2526         struct drm_i915_gem_object *log_obj = dev_priv->guc.log_obj;
2527         u32 *log;
2528         int i = 0, pg;
2529
2530         if (!log_obj)
2531                 return 0;
2532
2533         for (pg = 0; pg < log_obj->base.size / PAGE_SIZE; pg++) {
2534                 log = kmap_atomic(i915_gem_object_get_page(log_obj, pg));
2535
2536                 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2537                         seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2538                                    *(log + i), *(log + i + 1),
2539                                    *(log + i + 2), *(log + i + 3));
2540
2541                 kunmap_atomic(log);
2542         }
2543
2544         seq_putc(m, '\n');
2545
2546         return 0;
2547 }
2548
2549 static int i915_edp_psr_status(struct seq_file *m, void *data)
2550 {
2551         struct drm_info_node *node = m->private;
2552         struct drm_device *dev = node->minor->dev;
2553         struct drm_i915_private *dev_priv = dev->dev_private;
2554         u32 psrperf = 0;
2555         u32 stat[3];
2556         enum pipe pipe;
2557         bool enabled = false;
2558
2559         if (!HAS_PSR(dev)) {
2560                 seq_puts(m, "PSR not supported\n");
2561                 return 0;
2562         }
2563
2564         intel_runtime_pm_get(dev_priv);
2565
2566         mutex_lock(&dev_priv->psr.lock);
2567         seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2568         seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2569         seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2570         seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2571         seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2572                    dev_priv->psr.busy_frontbuffer_bits);
2573         seq_printf(m, "Re-enable work scheduled: %s\n",
2574                    yesno(work_busy(&dev_priv->psr.work.work)));
2575
2576         if (HAS_DDI(dev))
2577                 enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2578         else {
2579                 for_each_pipe(dev_priv, pipe) {
2580                         stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2581                                 VLV_EDP_PSR_CURR_STATE_MASK;
2582                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2583                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2584                                 enabled = true;
2585                 }
2586         }
2587
2588         seq_printf(m, "Main link in standby mode: %s\n",
2589                    yesno(dev_priv->psr.link_standby));
2590
2591         seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2592
2593         if (!HAS_DDI(dev))
2594                 for_each_pipe(dev_priv, pipe) {
2595                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2596                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2597                                 seq_printf(m, " pipe %c", pipe_name(pipe));
2598                 }
2599         seq_puts(m, "\n");
2600
2601         /*
2602          * VLV/CHV PSR has no kind of performance counter
2603          * SKL+ Perf counter is reset to 0 everytime DC state is entered
2604          */
2605         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2606                 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
2607                         EDP_PSR_PERF_CNT_MASK;
2608
2609                 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2610         }
2611         mutex_unlock(&dev_priv->psr.lock);
2612
2613         intel_runtime_pm_put(dev_priv);
2614         return 0;
2615 }
2616
2617 static int i915_sink_crc(struct seq_file *m, void *data)
2618 {
2619         struct drm_info_node *node = m->private;
2620         struct drm_device *dev = node->minor->dev;
2621         struct intel_encoder *encoder;
2622         struct intel_connector *connector;
2623         struct intel_dp *intel_dp = NULL;
2624         int ret;
2625         u8 crc[6];
2626
2627         drm_modeset_lock_all(dev);
2628         for_each_intel_connector(dev, connector) {
2629
2630                 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2631                         continue;
2632
2633                 if (!connector->base.encoder)
2634                         continue;
2635
2636                 encoder = to_intel_encoder(connector->base.encoder);
2637                 if (encoder->type != INTEL_OUTPUT_EDP)
2638                         continue;
2639
2640                 intel_dp = enc_to_intel_dp(&encoder->base);
2641
2642                 ret = intel_dp_sink_crc(intel_dp, crc);
2643                 if (ret)
2644                         goto out;
2645
2646                 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2647                            crc[0], crc[1], crc[2],
2648                            crc[3], crc[4], crc[5]);
2649                 goto out;
2650         }
2651         ret = -ENODEV;
2652 out:
2653         drm_modeset_unlock_all(dev);
2654         return ret;
2655 }
2656
2657 static int i915_energy_uJ(struct seq_file *m, void *data)
2658 {
2659         struct drm_info_node *node = m->private;
2660         struct drm_device *dev = node->minor->dev;
2661         struct drm_i915_private *dev_priv = dev->dev_private;
2662         u64 power;
2663         u32 units;
2664
2665         if (INTEL_INFO(dev)->gen < 6)
2666                 return -ENODEV;
2667
2668         intel_runtime_pm_get(dev_priv);
2669
2670         rdmsrl(MSR_RAPL_POWER_UNIT, power);
2671         power = (power & 0x1f00) >> 8;
2672         units = 1000000 / (1 << power); /* convert to uJ */
2673         power = I915_READ(MCH_SECP_NRG_STTS);
2674         power *= units;
2675
2676         intel_runtime_pm_put(dev_priv);
2677
2678         seq_printf(m, "%llu", (long long unsigned)power);
2679
2680         return 0;
2681 }
2682
2683 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2684 {
2685         struct drm_info_node *node = m->private;
2686         struct drm_device *dev = node->minor->dev;
2687         struct drm_i915_private *dev_priv = dev->dev_private;
2688
2689         if (!HAS_RUNTIME_PM(dev)) {
2690                 seq_puts(m, "not supported\n");
2691                 return 0;
2692         }
2693
2694         seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
2695         seq_printf(m, "IRQs disabled: %s\n",
2696                    yesno(!intel_irqs_enabled(dev_priv)));
2697 #ifdef CONFIG_PM
2698         seq_printf(m, "Usage count: %d\n",
2699                    atomic_read(&dev->dev->power.usage_count));
2700 #else
2701         seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2702 #endif
2703
2704         return 0;
2705 }
2706
2707 static int i915_power_domain_info(struct seq_file *m, void *unused)
2708 {
2709         struct drm_info_node *node = m->private;
2710         struct drm_device *dev = node->minor->dev;
2711         struct drm_i915_private *dev_priv = dev->dev_private;
2712         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2713         int i;
2714
2715         mutex_lock(&power_domains->lock);
2716
2717         seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2718         for (i = 0; i < power_domains->power_well_count; i++) {
2719                 struct i915_power_well *power_well;
2720                 enum intel_display_power_domain power_domain;
2721
2722                 power_well = &power_domains->power_wells[i];
2723                 seq_printf(m, "%-25s %d\n", power_well->name,
2724                            power_well->count);
2725
2726                 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2727                      power_domain++) {
2728                         if (!(BIT(power_domain) & power_well->domains))
2729                                 continue;
2730
2731                         seq_printf(m, "  %-23s %d\n",
2732                                  intel_display_power_domain_str(power_domain),
2733                                  power_domains->domain_use_count[power_domain]);
2734                 }
2735         }
2736
2737         mutex_unlock(&power_domains->lock);
2738
2739         return 0;
2740 }
2741
2742 static int i915_dmc_info(struct seq_file *m, void *unused)
2743 {
2744         struct drm_info_node *node = m->private;
2745         struct drm_device *dev = node->minor->dev;
2746         struct drm_i915_private *dev_priv = dev->dev_private;
2747         struct intel_csr *csr;
2748
2749         if (!HAS_CSR(dev)) {
2750                 seq_puts(m, "not supported\n");
2751                 return 0;
2752         }
2753
2754         csr = &dev_priv->csr;
2755
2756         intel_runtime_pm_get(dev_priv);
2757
2758         seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2759         seq_printf(m, "path: %s\n", csr->fw_path);
2760
2761         if (!csr->dmc_payload)
2762                 goto out;
2763
2764         seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2765                    CSR_VERSION_MINOR(csr->version));
2766
2767         if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) {
2768                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2769                            I915_READ(SKL_CSR_DC3_DC5_COUNT));
2770                 seq_printf(m, "DC5 -> DC6 count: %d\n",
2771                            I915_READ(SKL_CSR_DC5_DC6_COUNT));
2772         } else if (IS_BROXTON(dev) && csr->version >= CSR_VERSION(1, 4)) {
2773                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2774                            I915_READ(BXT_CSR_DC3_DC5_COUNT));
2775         }
2776
2777 out:
2778         seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2779         seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2780         seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2781
2782         intel_runtime_pm_put(dev_priv);
2783
2784         return 0;
2785 }
2786
2787 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2788                                  struct drm_display_mode *mode)
2789 {
2790         int i;
2791
2792         for (i = 0; i < tabs; i++)
2793                 seq_putc(m, '\t');
2794
2795         seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2796                    mode->base.id, mode->name,
2797                    mode->vrefresh, mode->clock,
2798                    mode->hdisplay, mode->hsync_start,
2799                    mode->hsync_end, mode->htotal,
2800                    mode->vdisplay, mode->vsync_start,
2801                    mode->vsync_end, mode->vtotal,
2802                    mode->type, mode->flags);
2803 }
2804
2805 static void intel_encoder_info(struct seq_file *m,
2806                                struct intel_crtc *intel_crtc,
2807                                struct intel_encoder *intel_encoder)
2808 {
2809         struct drm_info_node *node = m->private;
2810         struct drm_device *dev = node->minor->dev;
2811         struct drm_crtc *crtc = &intel_crtc->base;
2812         struct intel_connector *intel_connector;
2813         struct drm_encoder *encoder;
2814
2815         encoder = &intel_encoder->base;
2816         seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2817                    encoder->base.id, encoder->name);
2818         for_each_connector_on_encoder(dev, encoder, intel_connector) {
2819                 struct drm_connector *connector = &intel_connector->base;
2820                 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2821                            connector->base.id,
2822                            connector->name,
2823                            drm_get_connector_status_name(connector->status));
2824                 if (connector->status == connector_status_connected) {
2825                         struct drm_display_mode *mode = &crtc->mode;
2826                         seq_printf(m, ", mode:\n");
2827                         intel_seq_print_mode(m, 2, mode);
2828                 } else {
2829                         seq_putc(m, '\n');
2830                 }
2831         }
2832 }
2833
2834 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2835 {
2836         struct drm_info_node *node = m->private;
2837         struct drm_device *dev = node->minor->dev;
2838         struct drm_crtc *crtc = &intel_crtc->base;
2839         struct intel_encoder *intel_encoder;
2840         struct drm_plane_state *plane_state = crtc->primary->state;
2841         struct drm_framebuffer *fb = plane_state->fb;
2842
2843         if (fb)
2844                 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2845                            fb->base.id, plane_state->src_x >> 16,
2846                            plane_state->src_y >> 16, fb->width, fb->height);
2847         else
2848                 seq_puts(m, "\tprimary plane disabled\n");
2849         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2850                 intel_encoder_info(m, intel_crtc, intel_encoder);
2851 }
2852
2853 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2854 {
2855         struct drm_display_mode *mode = panel->fixed_mode;
2856
2857         seq_printf(m, "\tfixed mode:\n");
2858         intel_seq_print_mode(m, 2, mode);
2859 }
2860
2861 static void intel_dp_info(struct seq_file *m,
2862                           struct intel_connector *intel_connector)
2863 {
2864         struct intel_encoder *intel_encoder = intel_connector->encoder;
2865         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2866
2867         seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2868         seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2869         if (intel_encoder->type == INTEL_OUTPUT_EDP)
2870                 intel_panel_info(m, &intel_connector->panel);
2871 }
2872
2873 static void intel_dp_mst_info(struct seq_file *m,
2874                           struct intel_connector *intel_connector)
2875 {
2876         struct intel_encoder *intel_encoder = intel_connector->encoder;
2877         struct intel_dp_mst_encoder *intel_mst =
2878                 enc_to_mst(&intel_encoder->base);
2879         struct intel_digital_port *intel_dig_port = intel_mst->primary;
2880         struct intel_dp *intel_dp = &intel_dig_port->dp;
2881         bool has_audio = drm_dp_mst_port_has_audio(&intel_dp->mst_mgr,
2882                                         intel_connector->port);
2883
2884         seq_printf(m, "\taudio support: %s\n", yesno(has_audio));
2885 }
2886
2887 static void intel_hdmi_info(struct seq_file *m,
2888                             struct intel_connector *intel_connector)
2889 {
2890         struct intel_encoder *intel_encoder = intel_connector->encoder;
2891         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2892
2893         seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
2894 }
2895
2896 static void intel_lvds_info(struct seq_file *m,
2897                             struct intel_connector *intel_connector)
2898 {
2899         intel_panel_info(m, &intel_connector->panel);
2900 }
2901
2902 static void intel_connector_info(struct seq_file *m,
2903                                  struct drm_connector *connector)
2904 {
2905         struct intel_connector *intel_connector = to_intel_connector(connector);
2906         struct intel_encoder *intel_encoder = intel_connector->encoder;
2907         struct drm_display_mode *mode;
2908
2909         seq_printf(m, "connector %d: type %s, status: %s\n",
2910                    connector->base.id, connector->name,
2911                    drm_get_connector_status_name(connector->status));
2912         if (connector->status == connector_status_connected) {
2913                 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2914                 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2915                            connector->display_info.width_mm,
2916                            connector->display_info.height_mm);
2917                 seq_printf(m, "\tsubpixel order: %s\n",
2918                            drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2919                 seq_printf(m, "\tCEA rev: %d\n",
2920                            connector->display_info.cea_rev);
2921         }
2922         if (intel_encoder) {
2923                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2924                     intel_encoder->type == INTEL_OUTPUT_EDP)
2925                         intel_dp_info(m, intel_connector);
2926                 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2927                         intel_hdmi_info(m, intel_connector);
2928                 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2929                         intel_lvds_info(m, intel_connector);
2930                 else if (intel_encoder->type == INTEL_OUTPUT_DP_MST)
2931                         intel_dp_mst_info(m, intel_connector);
2932         }
2933
2934         seq_printf(m, "\tmodes:\n");
2935         list_for_each_entry(mode, &connector->modes, head)
2936                 intel_seq_print_mode(m, 2, mode);
2937 }
2938
2939 static bool cursor_active(struct drm_device *dev, int pipe)
2940 {
2941         struct drm_i915_private *dev_priv = dev->dev_private;
2942         u32 state;
2943
2944         if (IS_845G(dev) || IS_I865G(dev))
2945                 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
2946         else
2947                 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2948
2949         return state;
2950 }
2951
2952 static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2953 {
2954         struct drm_i915_private *dev_priv = dev->dev_private;
2955         u32 pos;
2956
2957         pos = I915_READ(CURPOS(pipe));
2958
2959         *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2960         if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2961                 *x = -*x;
2962
2963         *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2964         if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2965                 *y = -*y;
2966
2967         return cursor_active(dev, pipe);
2968 }
2969
2970 static const char *plane_type(enum drm_plane_type type)
2971 {
2972         switch (type) {
2973         case DRM_PLANE_TYPE_OVERLAY:
2974                 return "OVL";
2975         case DRM_PLANE_TYPE_PRIMARY:
2976                 return "PRI";
2977         case DRM_PLANE_TYPE_CURSOR:
2978                 return "CUR";
2979         /*
2980          * Deliberately omitting default: to generate compiler warnings
2981          * when a new drm_plane_type gets added.
2982          */
2983         }
2984
2985         return "unknown";
2986 }
2987
2988 static const char *plane_rotation(unsigned int rotation)
2989 {
2990         static char buf[48];
2991         /*
2992          * According to doc only one DRM_ROTATE_ is allowed but this
2993          * will print them all to visualize if the values are misused
2994          */
2995         snprintf(buf, sizeof(buf),
2996                  "%s%s%s%s%s%s(0x%08x)",
2997                  (rotation & BIT(DRM_ROTATE_0)) ? "0 " : "",
2998                  (rotation & BIT(DRM_ROTATE_90)) ? "90 " : "",
2999                  (rotation & BIT(DRM_ROTATE_180)) ? "180 " : "",
3000                  (rotation & BIT(DRM_ROTATE_270)) ? "270 " : "",
3001                  (rotation & BIT(DRM_REFLECT_X)) ? "FLIPX " : "",
3002                  (rotation & BIT(DRM_REFLECT_Y)) ? "FLIPY " : "",
3003                  rotation);
3004
3005         return buf;
3006 }
3007
3008 static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3009 {
3010         struct drm_info_node *node = m->private;
3011         struct drm_device *dev = node->minor->dev;
3012         struct intel_plane *intel_plane;
3013
3014         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3015                 struct drm_plane_state *state;
3016                 struct drm_plane *plane = &intel_plane->base;
3017
3018                 if (!plane->state) {
3019                         seq_puts(m, "plane->state is NULL!\n");
3020                         continue;
3021                 }
3022
3023                 state = plane->state;
3024
3025                 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3026                            plane->base.id,
3027                            plane_type(intel_plane->base.type),
3028                            state->crtc_x, state->crtc_y,
3029                            state->crtc_w, state->crtc_h,
3030                            (state->src_x >> 16),
3031                            ((state->src_x & 0xffff) * 15625) >> 10,
3032                            (state->src_y >> 16),
3033                            ((state->src_y & 0xffff) * 15625) >> 10,
3034                            (state->src_w >> 16),
3035                            ((state->src_w & 0xffff) * 15625) >> 10,
3036                            (state->src_h >> 16),
3037                            ((state->src_h & 0xffff) * 15625) >> 10,
3038                            state->fb ? drm_get_format_name(state->fb->pixel_format) : "N/A",
3039                            plane_rotation(state->rotation));
3040         }
3041 }
3042
3043 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3044 {
3045         struct intel_crtc_state *pipe_config;
3046         int num_scalers = intel_crtc->num_scalers;
3047         int i;
3048
3049         pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3050
3051         /* Not all platformas have a scaler */
3052         if (num_scalers) {
3053                 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3054                            num_scalers,
3055                            pipe_config->scaler_state.scaler_users,
3056                            pipe_config->scaler_state.scaler_id);
3057
3058                 for (i = 0; i < SKL_NUM_SCALERS; i++) {
3059                         struct intel_scaler *sc =
3060                                         &pipe_config->scaler_state.scalers[i];
3061
3062                         seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3063                                    i, yesno(sc->in_use), sc->mode);
3064                 }
3065                 seq_puts(m, "\n");
3066         } else {
3067                 seq_puts(m, "\tNo scalers available on this platform\n");
3068         }
3069 }
3070
3071 static int i915_display_info(struct seq_file *m, void *unused)
3072 {
3073         struct drm_info_node *node = m->private;
3074         struct drm_device *dev = node->minor->dev;
3075         struct drm_i915_private *dev_priv = dev->dev_private;
3076         struct intel_crtc *crtc;
3077         struct drm_connector *connector;
3078
3079         intel_runtime_pm_get(dev_priv);
3080         drm_modeset_lock_all(dev);
3081         seq_printf(m, "CRTC info\n");
3082         seq_printf(m, "---------\n");
3083         for_each_intel_crtc(dev, crtc) {
3084                 bool active;
3085                 struct intel_crtc_state *pipe_config;
3086                 int x, y;
3087
3088                 pipe_config = to_intel_crtc_state(crtc->base.state);
3089
3090                 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3091                            crtc->base.base.id, pipe_name(crtc->pipe),
3092                            yesno(pipe_config->base.active),
3093                            pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3094                            yesno(pipe_config->dither), pipe_config->pipe_bpp);
3095
3096                 if (pipe_config->base.active) {
3097                         intel_crtc_info(m, crtc);
3098
3099                         active = cursor_position(dev, crtc->pipe, &x, &y);
3100                         seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
3101                                    yesno(crtc->cursor_base),
3102                                    x, y, crtc->base.cursor->state->crtc_w,
3103                                    crtc->base.cursor->state->crtc_h,
3104                                    crtc->cursor_addr, yesno(active));
3105                         intel_scaler_info(m, crtc);
3106                         intel_plane_info(m, crtc);
3107                 }
3108
3109                 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3110                            yesno(!crtc->cpu_fifo_underrun_disabled),
3111                            yesno(!crtc->pch_fifo_underrun_disabled));
3112         }
3113
3114         seq_printf(m, "\n");
3115         seq_printf(m, "Connector info\n");
3116         seq_printf(m, "--------------\n");
3117         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3118                 intel_connector_info(m, connector);
3119         }
3120         drm_modeset_unlock_all(dev);
3121         intel_runtime_pm_put(dev_priv);
3122
3123         return 0;
3124 }
3125
3126 static int i915_semaphore_status(struct seq_file *m, void *unused)
3127 {
3128         struct drm_info_node *node = (struct drm_info_node *) m->private;
3129         struct drm_device *dev = node->minor->dev;
3130         struct drm_i915_private *dev_priv = dev->dev_private;
3131         struct intel_engine_cs *ring;
3132         int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
3133         int i, j, ret;
3134
3135         if (!i915_semaphore_is_enabled(dev)) {
3136                 seq_puts(m, "Semaphores are disabled\n");
3137                 return 0;
3138         }
3139
3140         ret = mutex_lock_interruptible(&dev->struct_mutex);
3141         if (ret)
3142                 return ret;
3143         intel_runtime_pm_get(dev_priv);
3144
3145         if (IS_BROADWELL(dev)) {
3146                 struct page *page;
3147                 uint64_t *seqno;
3148
3149                 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
3150
3151                 seqno = (uint64_t *)kmap_atomic(page);
3152                 for_each_ring(ring, dev_priv, i) {
3153                         uint64_t offset;
3154
3155                         seq_printf(m, "%s\n", ring->name);
3156
3157                         seq_puts(m, "  Last signal:");
3158                         for (j = 0; j < num_rings; j++) {
3159                                 offset = i * I915_NUM_RINGS + j;
3160                                 seq_printf(m, "0x%08llx (0x%02llx) ",
3161                                            seqno[offset], offset * 8);
3162                         }
3163                         seq_putc(m, '\n');
3164
3165                         seq_puts(m, "  Last wait:  ");
3166                         for (j = 0; j < num_rings; j++) {
3167                                 offset = i + (j * I915_NUM_RINGS);
3168                                 seq_printf(m, "0x%08llx (0x%02llx) ",
3169                                            seqno[offset], offset * 8);
3170                         }
3171                         seq_putc(m, '\n');
3172
3173                 }
3174                 kunmap_atomic(seqno);
3175         } else {
3176                 seq_puts(m, "  Last signal:");
3177                 for_each_ring(ring, dev_priv, i)
3178                         for (j = 0; j < num_rings; j++)
3179                                 seq_printf(m, "0x%08x\n",
3180                                            I915_READ(ring->semaphore.mbox.signal[j]));
3181                 seq_putc(m, '\n');
3182         }
3183
3184         seq_puts(m, "\nSync seqno:\n");
3185         for_each_ring(ring, dev_priv, i) {
3186                 for (j = 0; j < num_rings; j++) {
3187                         seq_printf(m, "  0x%08x ", ring->semaphore.sync_seqno[j]);
3188                 }
3189                 seq_putc(m, '\n');
3190         }
3191         seq_putc(m, '\n');
3192
3193         intel_runtime_pm_put(dev_priv);
3194         mutex_unlock(&dev->struct_mutex);
3195         return 0;
3196 }
3197
3198 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3199 {
3200         struct drm_info_node *node = (struct drm_info_node *) m->private;
3201         struct drm_device *dev = node->minor->dev;
3202         struct drm_i915_private *dev_priv = dev->dev_private;
3203         int i;
3204
3205         drm_modeset_lock_all(dev);
3206         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3207                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3208
3209                 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3210                 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",
3211                            pll->config.crtc_mask, pll->active, yesno(pll->on));
3212                 seq_printf(m, " tracked hardware state:\n");
3213                 seq_printf(m, " dpll:    0x%08x\n", pll->config.hw_state.dpll);
3214                 seq_printf(m, " dpll_md: 0x%08x\n",
3215                            pll->config.hw_state.dpll_md);
3216                 seq_printf(m, " fp0:     0x%08x\n", pll->config.hw_state.fp0);
3217                 seq_printf(m, " fp1:     0x%08x\n", pll->config.hw_state.fp1);
3218                 seq_printf(m, " wrpll:   0x%08x\n", pll->config.hw_state.wrpll);
3219         }
3220         drm_modeset_unlock_all(dev);
3221
3222         return 0;
3223 }
3224
3225 static int i915_wa_registers(struct seq_file *m, void *unused)
3226 {
3227         int i;
3228         int ret;
3229         struct intel_engine_cs *ring;
3230         struct drm_info_node *node = (struct drm_info_node *) m->private;
3231         struct drm_device *dev = node->minor->dev;
3232         struct drm_i915_private *dev_priv = dev->dev_private;
3233         struct i915_workarounds *workarounds = &dev_priv->workarounds;
3234
3235         ret = mutex_lock_interruptible(&dev->struct_mutex);
3236         if (ret)
3237                 return ret;
3238
3239         intel_runtime_pm_get(dev_priv);
3240
3241         seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
3242         for_each_ring(ring, dev_priv, i)
3243                 seq_printf(m, "HW whitelist count for %s: %d\n",
3244                            ring->name, workarounds->hw_whitelist_count[i]);
3245         for (i = 0; i < workarounds->count; ++i) {
3246                 i915_reg_t addr;
3247                 u32 mask, value, read;
3248                 bool ok;
3249
3250                 addr = workarounds->reg[i].addr;
3251                 mask = workarounds->reg[i].mask;
3252                 value = workarounds->reg[i].value;
3253                 read = I915_READ(addr);
3254                 ok = (value & mask) == (read & mask);
3255                 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3256                            i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
3257         }
3258
3259         intel_runtime_pm_put(dev_priv);
3260         mutex_unlock(&dev->struct_mutex);
3261
3262         return 0;
3263 }
3264
3265 static int i915_ddb_info(struct seq_file *m, void *unused)
3266 {
3267         struct drm_info_node *node = m->private;
3268         struct drm_device *dev = node->minor->dev;
3269         struct drm_i915_private *dev_priv = dev->dev_private;
3270         struct skl_ddb_allocation *ddb;
3271         struct skl_ddb_entry *entry;
3272         enum pipe pipe;
3273         int plane;
3274
3275         if (INTEL_INFO(dev)->gen < 9)
3276                 return 0;
3277
3278         drm_modeset_lock_all(dev);
3279
3280         ddb = &dev_priv->wm.skl_hw.ddb;
3281
3282         seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3283
3284         for_each_pipe(dev_priv, pipe) {
3285                 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3286
3287                 for_each_plane(dev_priv, pipe, plane) {
3288                         entry = &ddb->plane[pipe][plane];
3289                         seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane + 1,
3290                                    entry->start, entry->end,
3291                                    skl_ddb_entry_size(entry));
3292                 }
3293
3294                 entry = &ddb->plane[pipe][PLANE_CURSOR];
3295                 seq_printf(m, "  %-13s%8u%8u%8u\n", "Cursor", entry->start,
3296                            entry->end, skl_ddb_entry_size(entry));
3297         }
3298
3299         drm_modeset_unlock_all(dev);
3300
3301         return 0;
3302 }
3303
3304 static void drrs_status_per_crtc(struct seq_file *m,
3305                 struct drm_device *dev, struct intel_crtc *intel_crtc)
3306 {
3307         struct intel_encoder *intel_encoder;
3308         struct drm_i915_private *dev_priv = dev->dev_private;
3309         struct i915_drrs *drrs = &dev_priv->drrs;
3310         int vrefresh = 0;
3311
3312         for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) {
3313                 /* Encoder connected on this CRTC */
3314                 switch (intel_encoder->type) {
3315                 case INTEL_OUTPUT_EDP:
3316                         seq_puts(m, "eDP:\n");
3317                         break;
3318                 case INTEL_OUTPUT_DSI:
3319                         seq_puts(m, "DSI:\n");
3320                         break;
3321                 case INTEL_OUTPUT_HDMI:
3322                         seq_puts(m, "HDMI:\n");
3323                         break;
3324                 case INTEL_OUTPUT_DISPLAYPORT:
3325                         seq_puts(m, "DP:\n");
3326                         break;
3327                 default:
3328                         seq_printf(m, "Other encoder (id=%d).\n",
3329                                                 intel_encoder->type);
3330                         return;
3331                 }
3332         }
3333
3334         if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3335                 seq_puts(m, "\tVBT: DRRS_type: Static");
3336         else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3337                 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3338         else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3339                 seq_puts(m, "\tVBT: DRRS_type: None");
3340         else
3341                 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3342
3343         seq_puts(m, "\n\n");
3344
3345         if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3346                 struct intel_panel *panel;
3347
3348                 mutex_lock(&drrs->mutex);
3349                 /* DRRS Supported */
3350                 seq_puts(m, "\tDRRS Supported: Yes\n");
3351
3352                 /* disable_drrs() will make drrs->dp NULL */
3353                 if (!drrs->dp) {
3354                         seq_puts(m, "Idleness DRRS: Disabled");
3355                         mutex_unlock(&drrs->mutex);
3356                         return;
3357                 }
3358
3359                 panel = &drrs->dp->attached_connector->panel;
3360                 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3361                                         drrs->busy_frontbuffer_bits);
3362
3363                 seq_puts(m, "\n\t\t");
3364                 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3365                         seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3366                         vrefresh = panel->fixed_mode->vrefresh;
3367                 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3368                         seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3369                         vrefresh = panel->downclock_mode->vrefresh;
3370                 } else {
3371                         seq_printf(m, "DRRS_State: Unknown(%d)\n",
3372                                                 drrs->refresh_rate_type);
3373                         mutex_unlock(&drrs->mutex);
3374                         return;
3375                 }
3376                 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3377
3378                 seq_puts(m, "\n\t\t");
3379                 mutex_unlock(&drrs->mutex);
3380         } else {
3381                 /* DRRS not supported. Print the VBT parameter*/
3382                 seq_puts(m, "\tDRRS Supported : No");
3383         }
3384         seq_puts(m, "\n");
3385 }
3386
3387 static int i915_drrs_status(struct seq_file *m, void *unused)
3388 {
3389         struct drm_info_node *node = m->private;
3390         struct drm_device *dev = node->minor->dev;
3391         struct intel_crtc *intel_crtc;
3392         int active_crtc_cnt = 0;
3393
3394         for_each_intel_crtc(dev, intel_crtc) {
3395                 drm_modeset_lock(&intel_crtc->base.mutex, NULL);
3396
3397                 if (intel_crtc->base.state->active) {
3398                         active_crtc_cnt++;
3399                         seq_printf(m, "\nCRTC %d:  ", active_crtc_cnt);
3400
3401                         drrs_status_per_crtc(m, dev, intel_crtc);
3402                 }
3403
3404                 drm_modeset_unlock(&intel_crtc->base.mutex);
3405         }
3406
3407         if (!active_crtc_cnt)
3408                 seq_puts(m, "No active crtc found\n");
3409
3410         return 0;
3411 }
3412
3413 struct pipe_crc_info {
3414         const char *name;
3415         struct drm_device *dev;
3416         enum pipe pipe;
3417 };
3418
3419 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3420 {
3421         struct drm_info_node *node = (struct drm_info_node *) m->private;
3422         struct drm_device *dev = node->minor->dev;
3423         struct drm_encoder *encoder;
3424         struct intel_encoder *intel_encoder;
3425         struct intel_digital_port *intel_dig_port;
3426         drm_modeset_lock_all(dev);
3427         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3428                 intel_encoder = to_intel_encoder(encoder);
3429                 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
3430                         continue;
3431                 intel_dig_port = enc_to_dig_port(encoder);
3432                 if (!intel_dig_port->dp.can_mst)
3433                         continue;
3434
3435                 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3436         }
3437         drm_modeset_unlock_all(dev);
3438         return 0;
3439 }
3440
3441 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3442 {
3443         struct pipe_crc_info *info = inode->i_private;
3444         struct drm_i915_private *dev_priv = info->dev->dev_private;
3445         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3446
3447         if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3448                 return -ENODEV;
3449
3450         spin_lock_irq(&pipe_crc->lock);
3451
3452         if (pipe_crc->opened) {
3453                 spin_unlock_irq(&pipe_crc->lock);
3454                 return -EBUSY; /* already open */
3455         }
3456
3457         pipe_crc->opened = true;
3458         filep->private_data = inode->i_private;
3459
3460         spin_unlock_irq(&pipe_crc->lock);
3461
3462         return 0;
3463 }
3464
3465 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3466 {
3467         struct pipe_crc_info *info = inode->i_private;
3468         struct drm_i915_private *dev_priv = info->dev->dev_private;
3469         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3470
3471         spin_lock_irq(&pipe_crc->lock);
3472         pipe_crc->opened = false;
3473         spin_unlock_irq(&pipe_crc->lock);
3474
3475         return 0;
3476 }
3477
3478 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3479 #define PIPE_CRC_LINE_LEN       (6 * 8 + 5 + 1)
3480 /* account for \'0' */
3481 #define PIPE_CRC_BUFFER_LEN     (PIPE_CRC_LINE_LEN + 1)
3482
3483 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
3484 {
3485         assert_spin_locked(&pipe_crc->lock);
3486         return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3487                         INTEL_PIPE_CRC_ENTRIES_NR);
3488 }
3489
3490 static ssize_t
3491 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3492                    loff_t *pos)
3493 {
3494         struct pipe_crc_info *info = filep->private_data;
3495         struct drm_device *dev = info->dev;
3496         struct drm_i915_private *dev_priv = dev->dev_private;
3497         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3498         char buf[PIPE_CRC_BUFFER_LEN];
3499         int n_entries;
3500         ssize_t bytes_read;
3501
3502         /*
3503          * Don't allow user space to provide buffers not big enough to hold
3504          * a line of data.
3505          */
3506         if (count < PIPE_CRC_LINE_LEN)
3507                 return -EINVAL;
3508
3509         if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
3510                 return 0;
3511
3512         /* nothing to read */
3513         spin_lock_irq(&pipe_crc->lock);
3514         while (pipe_crc_data_count(pipe_crc) == 0) {
3515                 int ret;
3516
3517                 if (filep->f_flags & O_NONBLOCK) {
3518                         spin_unlock_irq(&pipe_crc->lock);
3519                         return -EAGAIN;
3520                 }
3521
3522                 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3523                                 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3524                 if (ret) {
3525                         spin_unlock_irq(&pipe_crc->lock);
3526                         return ret;
3527                 }
3528         }
3529
3530         /* We now have one or more entries to read */
3531         n_entries = count / PIPE_CRC_LINE_LEN;
3532
3533         bytes_read = 0;
3534         while (n_entries > 0) {
3535                 struct intel_pipe_crc_entry *entry =
3536                         &pipe_crc->entries[pipe_crc->tail];
3537                 int ret;
3538
3539                 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3540                              INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3541                         break;
3542
3543                 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3544                 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3545
3546                 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3547                                        "%8u %8x %8x %8x %8x %8x\n",
3548                                        entry->frame, entry->crc[0],
3549                                        entry->crc[1], entry->crc[2],
3550                                        entry->crc[3], entry->crc[4]);
3551
3552                 spin_unlock_irq(&pipe_crc->lock);
3553
3554                 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
3555                 if (ret == PIPE_CRC_LINE_LEN)
3556                         return -EFAULT;
3557
3558                 user_buf += PIPE_CRC_LINE_LEN;
3559                 n_entries--;
3560
3561                 spin_lock_irq(&pipe_crc->lock);
3562         }
3563
3564         spin_unlock_irq(&pipe_crc->lock);
3565
3566         return bytes_read;
3567 }
3568
3569 static const struct file_operations i915_pipe_crc_fops = {
3570         .owner = THIS_MODULE,
3571         .open = i915_pipe_crc_open,
3572         .read = i915_pipe_crc_read,
3573         .release = i915_pipe_crc_release,
3574 };
3575
3576 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3577         {
3578                 .name = "i915_pipe_A_crc",
3579                 .pipe = PIPE_A,
3580         },
3581         {
3582                 .name = "i915_pipe_B_crc",
3583                 .pipe = PIPE_B,
3584         },
3585         {
3586                 .name = "i915_pipe_C_crc",
3587                 .pipe = PIPE_C,
3588         },
3589 };
3590
3591 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3592                                 enum pipe pipe)
3593 {
3594         struct drm_device *dev = minor->dev;
3595         struct dentry *ent;
3596         struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3597
3598         info->dev = dev;
3599         ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3600                                   &i915_pipe_crc_fops);
3601         if (!ent)
3602                 return -ENOMEM;
3603
3604         return drm_add_fake_info_node(minor, ent, info);
3605 }
3606
3607 static const char * const pipe_crc_sources[] = {
3608         "none",
3609         "plane1",
3610         "plane2",
3611         "pf",
3612         "pipe",
3613         "TV",
3614         "DP-B",
3615         "DP-C",
3616         "DP-D",
3617         "auto",
3618 };
3619
3620 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3621 {
3622         BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3623         return pipe_crc_sources[source];
3624 }
3625
3626 static int display_crc_ctl_show(struct seq_file *m, void *data)
3627 {
3628         struct drm_device *dev = m->private;
3629         struct drm_i915_private *dev_priv = dev->dev_private;
3630         int i;
3631
3632         for (i = 0; i < I915_MAX_PIPES; i++)
3633                 seq_printf(m, "%c %s\n", pipe_name(i),
3634                            pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3635
3636         return 0;
3637 }
3638
3639 static int display_crc_ctl_open(struct inode *inode, struct file *file)
3640 {
3641         struct drm_device *dev = inode->i_private;
3642
3643         return single_open(file, display_crc_ctl_show, dev);
3644 }
3645
3646 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3647                                  uint32_t *val)
3648 {
3649         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3650                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3651
3652         switch (*source) {
3653         case INTEL_PIPE_CRC_SOURCE_PIPE:
3654                 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3655                 break;
3656         case INTEL_PIPE_CRC_SOURCE_NONE:
3657                 *val = 0;
3658                 break;
3659         default:
3660                 return -EINVAL;
3661         }
3662
3663         return 0;
3664 }
3665
3666 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3667                                      enum intel_pipe_crc_source *source)
3668 {
3669         struct intel_encoder *encoder;
3670         struct intel_crtc *crtc;
3671         struct intel_digital_port *dig_port;
3672         int ret = 0;
3673
3674         *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3675
3676         drm_modeset_lock_all(dev);
3677         for_each_intel_encoder(dev, encoder) {
3678                 if (!encoder->base.crtc)
3679                         continue;
3680
3681                 crtc = to_intel_crtc(encoder->base.crtc);
3682
3683                 if (crtc->pipe != pipe)
3684                         continue;
3685
3686                 switch (encoder->type) {
3687                 case INTEL_OUTPUT_TVOUT:
3688                         *source = INTEL_PIPE_CRC_SOURCE_TV;
3689                         break;
3690                 case INTEL_OUTPUT_DISPLAYPORT:
3691                 case INTEL_OUTPUT_EDP:
3692                         dig_port = enc_to_dig_port(&encoder->base);
3693                         switch (dig_port->port) {
3694                         case PORT_B:
3695                                 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3696                                 break;
3697                         case PORT_C:
3698                                 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3699                                 break;
3700                         case PORT_D:
3701                                 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3702                                 break;
3703                         default:
3704                                 WARN(1, "nonexisting DP port %c\n",
3705                                      port_name(dig_port->port));
3706                                 break;
3707                         }
3708                         break;
3709                 default:
3710                         break;
3711                 }
3712         }
3713         drm_modeset_unlock_all(dev);
3714
3715         return ret;
3716 }
3717
3718 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3719                                 enum pipe pipe,
3720                                 enum intel_pipe_crc_source *source,
3721                                 uint32_t *val)
3722 {
3723         struct drm_i915_private *dev_priv = dev->dev_private;
3724         bool need_stable_symbols = false;
3725
3726         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3727                 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3728                 if (ret)
3729                         return ret;
3730         }
3731
3732         switch (*source) {
3733         case INTEL_PIPE_CRC_SOURCE_PIPE:
3734                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3735                 break;
3736         case INTEL_PIPE_CRC_SOURCE_DP_B:
3737                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3738                 need_stable_symbols = true;
3739                 break;
3740         case INTEL_PIPE_CRC_SOURCE_DP_C:
3741                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3742                 need_stable_symbols = true;
3743                 break;
3744         case INTEL_PIPE_CRC_SOURCE_DP_D:
3745                 if (!IS_CHERRYVIEW(dev))
3746                         return -EINVAL;
3747                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3748                 need_stable_symbols = true;
3749                 break;
3750         case INTEL_PIPE_CRC_SOURCE_NONE:
3751                 *val = 0;
3752                 break;
3753         default:
3754                 return -EINVAL;
3755         }
3756
3757         /*
3758          * When the pipe CRC tap point is after the transcoders we need
3759          * to tweak symbol-level features to produce a deterministic series of
3760          * symbols for a given frame. We need to reset those features only once
3761          * a frame (instead of every nth symbol):
3762          *   - DC-balance: used to ensure a better clock recovery from the data
3763          *     link (SDVO)
3764          *   - DisplayPort scrambling: used for EMI reduction
3765          */
3766         if (need_stable_symbols) {
3767                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3768
3769                 tmp |= DC_BALANCE_RESET_VLV;
3770                 switch (pipe) {
3771                 case PIPE_A:
3772                         tmp |= PIPE_A_SCRAMBLE_RESET;
3773                         break;
3774                 case PIPE_B:
3775                         tmp |= PIPE_B_SCRAMBLE_RESET;
3776                         break;
3777                 case PIPE_C:
3778                         tmp |= PIPE_C_SCRAMBLE_RESET;
3779                         break;
3780                 default:
3781                         return -EINVAL;
3782                 }
3783                 I915_WRITE(PORT_DFT2_G4X, tmp);
3784         }
3785
3786         return 0;
3787 }
3788
3789 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
3790                                  enum pipe pipe,
3791                                  enum intel_pipe_crc_source *source,
3792                                  uint32_t *val)
3793 {
3794         struct drm_i915_private *dev_priv = dev->dev_private;
3795         bool need_stable_symbols = false;
3796
3797         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3798                 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3799                 if (ret)
3800                         return ret;
3801         }
3802
3803         switch (*source) {
3804         case INTEL_PIPE_CRC_SOURCE_PIPE:
3805                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3806                 break;
3807         case INTEL_PIPE_CRC_SOURCE_TV:
3808                 if (!SUPPORTS_TV(dev))
3809                         return -EINVAL;
3810                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3811                 break;
3812         case INTEL_PIPE_CRC_SOURCE_DP_B:
3813                 if (!IS_G4X(dev))
3814                         return -EINVAL;
3815                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3816                 need_stable_symbols = true;
3817                 break;
3818         case INTEL_PIPE_CRC_SOURCE_DP_C:
3819                 if (!IS_G4X(dev))
3820                         return -EINVAL;
3821                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3822                 need_stable_symbols = true;
3823                 break;
3824         case INTEL_PIPE_CRC_SOURCE_DP_D:
3825                 if (!IS_G4X(dev))
3826                         return -EINVAL;
3827                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3828                 need_stable_symbols = true;
3829                 break;
3830         case INTEL_PIPE_CRC_SOURCE_NONE:
3831                 *val = 0;
3832                 break;
3833         default:
3834                 return -EINVAL;
3835         }
3836
3837         /*
3838          * When the pipe CRC tap point is after the transcoders we need
3839          * to tweak symbol-level features to produce a deterministic series of
3840          * symbols for a given frame. We need to reset those features only once
3841          * a frame (instead of every nth symbol):
3842          *   - DC-balance: used to ensure a better clock recovery from the data
3843          *     link (SDVO)
3844          *   - DisplayPort scrambling: used for EMI reduction
3845          */
3846         if (need_stable_symbols) {
3847                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3848
3849                 WARN_ON(!IS_G4X(dev));
3850
3851                 I915_WRITE(PORT_DFT_I9XX,
3852                            I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3853
3854                 if (pipe == PIPE_A)
3855                         tmp |= PIPE_A_SCRAMBLE_RESET;
3856                 else
3857                         tmp |= PIPE_B_SCRAMBLE_RESET;
3858
3859                 I915_WRITE(PORT_DFT2_G4X, tmp);
3860         }
3861
3862         return 0;
3863 }
3864
3865 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3866                                          enum pipe pipe)
3867 {
3868         struct drm_i915_private *dev_priv = dev->dev_private;
3869         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3870
3871         switch (pipe) {
3872         case PIPE_A:
3873                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3874                 break;
3875         case PIPE_B:
3876                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3877                 break;
3878         case PIPE_C:
3879                 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3880                 break;
3881         default:
3882                 return;
3883         }
3884         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3885                 tmp &= ~DC_BALANCE_RESET_VLV;
3886         I915_WRITE(PORT_DFT2_G4X, tmp);
3887
3888 }
3889
3890 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3891                                          enum pipe pipe)
3892 {
3893         struct drm_i915_private *dev_priv = dev->dev_private;
3894         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3895
3896         if (pipe == PIPE_A)
3897                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3898         else
3899                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3900         I915_WRITE(PORT_DFT2_G4X, tmp);
3901
3902         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3903                 I915_WRITE(PORT_DFT_I9XX,
3904                            I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3905         }
3906 }
3907
3908 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3909                                 uint32_t *val)
3910 {
3911         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3912                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3913
3914         switch (*source) {
3915         case INTEL_PIPE_CRC_SOURCE_PLANE1:
3916                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3917                 break;
3918         case INTEL_PIPE_CRC_SOURCE_PLANE2:
3919                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3920                 break;
3921         case INTEL_PIPE_CRC_SOURCE_PIPE:
3922                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3923                 break;
3924         case INTEL_PIPE_CRC_SOURCE_NONE:
3925                 *val = 0;
3926                 break;
3927         default:
3928                 return -EINVAL;
3929         }
3930
3931         return 0;
3932 }
3933
3934 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev, bool enable)
3935 {
3936         struct drm_i915_private *dev_priv = dev->dev_private;
3937         struct intel_crtc *crtc =
3938                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3939         struct intel_crtc_state *pipe_config;
3940         struct drm_atomic_state *state;
3941         int ret = 0;
3942
3943         drm_modeset_lock_all(dev);
3944         state = drm_atomic_state_alloc(dev);
3945         if (!state) {
3946                 ret = -ENOMEM;
3947                 goto out;
3948         }
3949
3950         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
3951         pipe_config = intel_atomic_get_crtc_state(state, crtc);
3952         if (IS_ERR(pipe_config)) {
3953                 ret = PTR_ERR(pipe_config);
3954                 goto out;
3955         }
3956
3957         pipe_config->pch_pfit.force_thru = enable;
3958         if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
3959             pipe_config->pch_pfit.enabled != enable)
3960                 pipe_config->base.connectors_changed = true;
3961
3962         ret = drm_atomic_commit(state);
3963 out:
3964         drm_modeset_unlock_all(dev);
3965         WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
3966         if (ret)
3967                 drm_atomic_state_free(state);
3968 }
3969
3970 static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3971                                 enum pipe pipe,
3972                                 enum intel_pipe_crc_source *source,
3973                                 uint32_t *val)
3974 {
3975         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3976                 *source = INTEL_PIPE_CRC_SOURCE_PF;
3977
3978         switch (*source) {
3979         case INTEL_PIPE_CRC_SOURCE_PLANE1:
3980                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3981                 break;
3982         case INTEL_PIPE_CRC_SOURCE_PLANE2:
3983                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3984                 break;
3985         case INTEL_PIPE_CRC_SOURCE_PF:
3986                 if (IS_HASWELL(dev) && pipe == PIPE_A)
3987                         hsw_trans_edp_pipe_A_crc_wa(dev, true);
3988
3989                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3990                 break;
3991         case INTEL_PIPE_CRC_SOURCE_NONE:
3992                 *val = 0;
3993                 break;
3994         default:
3995                 return -EINVAL;
3996         }
3997
3998         return 0;
3999 }
4000
4001 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
4002                                enum intel_pipe_crc_source source)
4003 {
4004         struct drm_i915_private *dev_priv = dev->dev_private;
4005         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
4006         struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
4007                                                                         pipe));
4008         enum intel_display_power_domain power_domain;
4009         u32 val = 0; /* shut up gcc */
4010         int ret;
4011
4012         if (pipe_crc->source == source)
4013                 return 0;
4014
4015         /* forbid changing the source without going back to 'none' */
4016         if (pipe_crc->source && source)
4017                 return -EINVAL;
4018
4019         power_domain = POWER_DOMAIN_PIPE(pipe);
4020         if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
4021                 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
4022                 return -EIO;
4023         }
4024
4025         if (IS_GEN2(dev))
4026                 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
4027         else if (INTEL_INFO(dev)->gen < 5)
4028                 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4029         else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4030                 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4031         else if (IS_GEN5(dev) || IS_GEN6(dev))
4032                 ret = ilk_pipe_crc_ctl_reg(&source, &val);
4033         else
4034                 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4035
4036         if (ret != 0)
4037                 goto out;
4038
4039         /* none -> real source transition */
4040         if (source) {
4041                 struct intel_pipe_crc_entry *entries;
4042
4043                 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4044                                  pipe_name(pipe), pipe_crc_source_name(source));
4045
4046                 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
4047                                   sizeof(pipe_crc->entries[0]),
4048                                   GFP_KERNEL);
4049                 if (!entries) {
4050                         ret = -ENOMEM;
4051                         goto out;
4052                 }
4053
4054                 /*
4055                  * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4056                  * enabled and disabled dynamically based on package C states,
4057                  * user space can't make reliable use of the CRCs, so let's just
4058                  * completely disable it.
4059                  */
4060                 hsw_disable_ips(crtc);
4061
4062                 spin_lock_irq(&pipe_crc->lock);
4063                 kfree(pipe_crc->entries);
4064                 pipe_crc->entries = entries;
4065                 pipe_crc->head = 0;
4066                 pipe_crc->tail = 0;
4067                 spin_unlock_irq(&pipe_crc->lock);
4068         }
4069
4070         pipe_crc->source = source;
4071
4072         I915_WRITE(PIPE_CRC_CTL(pipe), val);
4073         POSTING_READ(PIPE_CRC_CTL(pipe));
4074
4075         /* real source -> none transition */
4076         if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
4077                 struct intel_pipe_crc_entry *entries;
4078                 struct intel_crtc *crtc =
4079                         to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
4080
4081                 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4082                                  pipe_name(pipe));
4083
4084                 drm_modeset_lock(&crtc->base.mutex, NULL);
4085                 if (crtc->base.state->active)
4086                         intel_wait_for_vblank(dev, pipe);
4087                 drm_modeset_unlock(&crtc->base.mutex);
4088
4089                 spin_lock_irq(&pipe_crc->lock);
4090                 entries = pipe_crc->entries;
4091                 pipe_crc->entries = NULL;
4092                 pipe_crc->head = 0;
4093                 pipe_crc->tail = 0;
4094                 spin_unlock_irq(&pipe_crc->lock);
4095
4096                 kfree(entries);
4097
4098                 if (IS_G4X(dev))
4099                         g4x_undo_pipe_scramble_reset(dev, pipe);
4100                 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4101                         vlv_undo_pipe_scramble_reset(dev, pipe);
4102                 else if (IS_HASWELL(dev) && pipe == PIPE_A)
4103                         hsw_trans_edp_pipe_A_crc_wa(dev, false);
4104
4105                 hsw_enable_ips(crtc);
4106         }
4107
4108         ret = 0;
4109
4110 out:
4111         intel_display_power_put(dev_priv, power_domain);
4112
4113         return ret;
4114 }
4115
4116 /*
4117  * Parse pipe CRC command strings:
4118  *   command: wsp* object wsp+ name wsp+ source wsp*
4119  *   object: 'pipe'
4120  *   name: (A | B | C)
4121  *   source: (none | plane1 | plane2 | pf)
4122  *   wsp: (#0x20 | #0x9 | #0xA)+
4123  *
4124  * eg.:
4125  *  "pipe A plane1"  ->  Start CRC computations on plane1 of pipe A
4126  *  "pipe A none"    ->  Stop CRC
4127  */
4128 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
4129 {
4130         int n_words = 0;
4131
4132         while (*buf) {
4133                 char *end;
4134
4135                 /* skip leading white space */
4136                 buf = skip_spaces(buf);
4137                 if (!*buf)
4138                         break;  /* end of buffer */
4139
4140                 /* find end of word */
4141                 for (end = buf; *end && !isspace(*end); end++)
4142                         ;
4143
4144                 if (n_words == max_words) {
4145                         DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4146                                          max_words);
4147                         return -EINVAL; /* ran out of words[] before bytes */
4148                 }
4149
4150                 if (*end)
4151                         *end++ = '\0';
4152                 words[n_words++] = buf;
4153                 buf = end;
4154         }
4155
4156         return n_words;
4157 }
4158
4159 enum intel_pipe_crc_object {
4160         PIPE_CRC_OBJECT_PIPE,
4161 };
4162
4163 static const char * const pipe_crc_objects[] = {
4164         "pipe",
4165 };
4166
4167 static int
4168 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
4169 {
4170         int i;
4171
4172         for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
4173                 if (!strcmp(buf, pipe_crc_objects[i])) {
4174                         *o = i;
4175                         return 0;
4176                     }
4177
4178         return -EINVAL;
4179 }
4180
4181 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
4182 {
4183         const char name = buf[0];
4184
4185         if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
4186                 return -EINVAL;
4187
4188         *pipe = name - 'A';
4189
4190         return 0;
4191 }
4192
4193 static int
4194 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
4195 {
4196         int i;
4197
4198         for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
4199                 if (!strcmp(buf, pipe_crc_sources[i])) {
4200                         *s = i;
4201                         return 0;
4202                     }
4203
4204         return -EINVAL;
4205 }
4206
4207 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
4208 {
4209 #define N_WORDS 3
4210         int n_words;
4211         char *words[N_WORDS];
4212         enum pipe pipe;
4213         enum intel_pipe_crc_object object;
4214         enum intel_pipe_crc_source source;
4215
4216         n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
4217         if (n_words != N_WORDS) {
4218                 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4219                                  N_WORDS);
4220                 return -EINVAL;
4221         }
4222
4223         if (display_crc_ctl_parse_object(words[0], &object) < 0) {
4224                 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
4225                 return -EINVAL;
4226         }
4227
4228         if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
4229                 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
4230                 return -EINVAL;
4231         }
4232
4233         if (display_crc_ctl_parse_source(words[2], &source) < 0) {
4234                 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
4235                 return -EINVAL;
4236         }
4237
4238         return pipe_crc_set_source(dev, pipe, source);
4239 }
4240
4241 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
4242                                      size_t len, loff_t *offp)
4243 {
4244         struct seq_file *m = file->private_data;
4245         struct drm_device *dev = m->private;
4246         char *tmpbuf;
4247         int ret;
4248
4249         if (len == 0)
4250                 return 0;
4251
4252         if (len > PAGE_SIZE - 1) {
4253                 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4254                                  PAGE_SIZE);
4255                 return -E2BIG;
4256         }
4257
4258         tmpbuf = kmalloc(len + 1, GFP_KERNEL);
4259         if (!tmpbuf)
4260                 return -ENOMEM;
4261
4262         if (copy_from_user(tmpbuf, ubuf, len)) {
4263                 ret = -EFAULT;
4264                 goto out;
4265         }
4266         tmpbuf[len] = '\0';
4267
4268         ret = display_crc_ctl_parse(dev, tmpbuf, len);
4269
4270 out:
4271         kfree(tmpbuf);
4272         if (ret < 0)
4273                 return ret;
4274
4275         *offp += len;
4276         return len;
4277 }
4278
4279 static const struct file_operations i915_display_crc_ctl_fops = {
4280         .owner = THIS_MODULE,
4281         .open = display_crc_ctl_open,
4282         .read = seq_read,
4283         .llseek = seq_lseek,
4284         .release = single_release,
4285         .write = display_crc_ctl_write
4286 };
4287
4288 static ssize_t i915_displayport_test_active_write(struct file *file,
4289                                             const char __user *ubuf,
4290                                             size_t len, loff_t *offp)
4291 {
4292         char *input_buffer;
4293         int status = 0;
4294         struct drm_device *dev;
4295         struct drm_connector *connector;
4296         struct list_head *connector_list;
4297         struct intel_dp *intel_dp;
4298         int val = 0;
4299
4300         dev = ((struct seq_file *)file->private_data)->private;
4301
4302         connector_list = &dev->mode_config.connector_list;
4303
4304         if (len == 0)
4305                 return 0;
4306
4307         input_buffer = kmalloc(len + 1, GFP_KERNEL);
4308         if (!input_buffer)
4309                 return -ENOMEM;
4310
4311         if (copy_from_user(input_buffer, ubuf, len)) {
4312                 status = -EFAULT;
4313                 goto out;
4314         }
4315
4316         input_buffer[len] = '\0';
4317         DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4318
4319         list_for_each_entry(connector, connector_list, head) {
4320
4321                 if (connector->connector_type !=
4322                     DRM_MODE_CONNECTOR_DisplayPort)
4323                         continue;
4324
4325                 if (connector->status == connector_status_connected &&
4326                     connector->encoder != NULL) {
4327                         intel_dp = enc_to_intel_dp(connector->encoder);
4328                         status = kstrtoint(input_buffer, 10, &val);
4329                         if (status < 0)
4330                                 goto out;
4331                         DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4332                         /* To prevent erroneous activation of the compliance
4333                          * testing code, only accept an actual value of 1 here
4334                          */
4335                         if (val == 1)
4336                                 intel_dp->compliance_test_active = 1;
4337                         else
4338                                 intel_dp->compliance_test_active = 0;
4339                 }
4340         }
4341 out:
4342         kfree(input_buffer);
4343         if (status < 0)
4344                 return status;
4345
4346         *offp += len;
4347         return len;
4348 }
4349
4350 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4351 {
4352         struct drm_device *dev = m->private;
4353         struct drm_connector *connector;
4354         struct list_head *connector_list = &dev->mode_config.connector_list;
4355         struct intel_dp *intel_dp;
4356
4357         list_for_each_entry(connector, connector_list, head) {
4358
4359                 if (connector->connector_type !=
4360                     DRM_MODE_CONNECTOR_DisplayPort)
4361                         continue;
4362
4363                 if (connector->status == connector_status_connected &&
4364                     connector->encoder != NULL) {
4365                         intel_dp = enc_to_intel_dp(connector->encoder);
4366                         if (intel_dp->compliance_test_active)
4367                                 seq_puts(m, "1");
4368                         else
4369                                 seq_puts(m, "0");
4370                 } else
4371                         seq_puts(m, "0");
4372         }
4373
4374         return 0;
4375 }
4376
4377 static int i915_displayport_test_active_open(struct inode *inode,
4378                                        struct file *file)
4379 {
4380         struct drm_device *dev = inode->i_private;
4381
4382         return single_open(file, i915_displayport_test_active_show, dev);
4383 }
4384
4385 static const struct file_operations i915_displayport_test_active_fops = {
4386         .owner = THIS_MODULE,
4387         .open = i915_displayport_test_active_open,
4388         .read = seq_read,
4389         .llseek = seq_lseek,
4390         .release = single_release,
4391         .write = i915_displayport_test_active_write
4392 };
4393
4394 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4395 {
4396         struct drm_device *dev = m->private;
4397         struct drm_connector *connector;
4398         struct list_head *connector_list = &dev->mode_config.connector_list;
4399         struct intel_dp *intel_dp;
4400
4401         list_for_each_entry(connector, connector_list, head) {
4402
4403                 if (connector->connector_type !=
4404                     DRM_MODE_CONNECTOR_DisplayPort)
4405                         continue;
4406
4407                 if (connector->status == connector_status_connected &&
4408                     connector->encoder != NULL) {
4409                         intel_dp = enc_to_intel_dp(connector->encoder);
4410                         seq_printf(m, "%lx", intel_dp->compliance_test_data);
4411                 } else
4412                         seq_puts(m, "0");
4413         }
4414
4415         return 0;
4416 }
4417 static int i915_displayport_test_data_open(struct inode *inode,
4418                                        struct file *file)
4419 {
4420         struct drm_device *dev = inode->i_private;
4421
4422         return single_open(file, i915_displayport_test_data_show, dev);
4423 }
4424
4425 static const struct file_operations i915_displayport_test_data_fops = {
4426         .owner = THIS_MODULE,
4427         .open = i915_displayport_test_data_open,
4428         .read = seq_read,
4429         .llseek = seq_lseek,
4430         .release = single_release
4431 };
4432
4433 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4434 {
4435         struct drm_device *dev = m->private;
4436         struct drm_connector *connector;
4437         struct list_head *connector_list = &dev->mode_config.connector_list;
4438         struct intel_dp *intel_dp;
4439
4440         list_for_each_entry(connector, connector_list, head) {
4441
4442                 if (connector->connector_type !=
4443                     DRM_MODE_CONNECTOR_DisplayPort)
4444                         continue;
4445
4446                 if (connector->status == connector_status_connected &&
4447                     connector->encoder != NULL) {
4448                         intel_dp = enc_to_intel_dp(connector->encoder);
4449                         seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4450                 } else
4451                         seq_puts(m, "0");
4452         }
4453
4454         return 0;
4455 }
4456
4457 static int i915_displayport_test_type_open(struct inode *inode,
4458                                        struct file *file)
4459 {
4460         struct drm_device *dev = inode->i_private;
4461
4462         return single_open(file, i915_displayport_test_type_show, dev);
4463 }
4464
4465 static const struct file_operations i915_displayport_test_type_fops = {
4466         .owner = THIS_MODULE,
4467         .open = i915_displayport_test_type_open,
4468         .read = seq_read,
4469         .llseek = seq_lseek,
4470         .release = single_release
4471 };
4472
4473 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
4474 {
4475         struct drm_device *dev = m->private;
4476         int level;
4477         int num_levels;
4478
4479         if (IS_CHERRYVIEW(dev))
4480                 num_levels = 3;
4481         else if (IS_VALLEYVIEW(dev))
4482                 num_levels = 1;
4483         else
4484                 num_levels = ilk_wm_max_level(dev) + 1;
4485
4486         drm_modeset_lock_all(dev);
4487
4488         for (level = 0; level < num_levels; level++) {
4489                 unsigned int latency = wm[level];
4490
4491                 /*
4492                  * - WM1+ latency values in 0.5us units
4493                  * - latencies are in us on gen9/vlv/chv
4494                  */
4495                 if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev) ||
4496                     IS_CHERRYVIEW(dev))
4497                         latency *= 10;
4498                 else if (level > 0)
4499                         latency *= 5;
4500
4501                 seq_printf(m, "WM%d %u (%u.%u usec)\n",
4502                            level, wm[level], latency / 10, latency % 10);
4503         }
4504
4505         drm_modeset_unlock_all(dev);
4506 }
4507
4508 static int pri_wm_latency_show(struct seq_file *m, void *data)
4509 {
4510         struct drm_device *dev = m->private;
4511         struct drm_i915_private *dev_priv = dev->dev_private;
4512         const uint16_t *latencies;
4513
4514         if (INTEL_INFO(dev)->gen >= 9)
4515                 latencies = dev_priv->wm.skl_latency;
4516         else
4517                 latencies = to_i915(dev)->wm.pri_latency;
4518
4519         wm_latency_show(m, latencies);
4520
4521         return 0;
4522 }
4523
4524 static int spr_wm_latency_show(struct seq_file *m, void *data)
4525 {
4526         struct drm_device *dev = m->private;
4527         struct drm_i915_private *dev_priv = dev->dev_private;
4528         const uint16_t *latencies;
4529
4530         if (INTEL_INFO(dev)->gen >= 9)
4531                 latencies = dev_priv->wm.skl_latency;
4532         else
4533                 latencies = to_i915(dev)->wm.spr_latency;
4534
4535         wm_latency_show(m, latencies);
4536
4537         return 0;
4538 }
4539
4540 static int cur_wm_latency_show(struct seq_file *m, void *data)
4541 {
4542         struct drm_device *dev = m->private;
4543         struct drm_i915_private *dev_priv = dev->dev_private;
4544         const uint16_t *latencies;
4545
4546         if (INTEL_INFO(dev)->gen >= 9)
4547                 latencies = dev_priv->wm.skl_latency;
4548         else
4549                 latencies = to_i915(dev)->wm.cur_latency;
4550
4551         wm_latency_show(m, latencies);
4552
4553         return 0;
4554 }
4555
4556 static int pri_wm_latency_open(struct inode *inode, struct file *file)
4557 {
4558         struct drm_device *dev = inode->i_private;
4559
4560         if (INTEL_INFO(dev)->gen < 5)
4561                 return -ENODEV;
4562
4563         return single_open(file, pri_wm_latency_show, dev);
4564 }
4565
4566 static int spr_wm_latency_open(struct inode *inode, struct file *file)
4567 {
4568         struct drm_device *dev = inode->i_private;
4569
4570         if (HAS_GMCH_DISPLAY(dev))
4571                 return -ENODEV;
4572
4573         return single_open(file, spr_wm_latency_show, dev);
4574 }
4575
4576 static int cur_wm_latency_open(struct inode *inode, struct file *file)
4577 {
4578         struct drm_device *dev = inode->i_private;
4579
4580         if (HAS_GMCH_DISPLAY(dev))
4581                 return -ENODEV;
4582
4583         return single_open(file, cur_wm_latency_show, dev);
4584 }
4585
4586 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
4587                                 size_t len, loff_t *offp, uint16_t wm[8])
4588 {
4589         struct seq_file *m = file->private_data;
4590         struct drm_device *dev = m->private;
4591         uint16_t new[8] = { 0 };
4592         int num_levels;
4593         int level;
4594         int ret;
4595         char tmp[32];
4596
4597         if (IS_CHERRYVIEW(dev))
4598                 num_levels = 3;
4599         else if (IS_VALLEYVIEW(dev))
4600                 num_levels = 1;
4601         else
4602                 num_levels = ilk_wm_max_level(dev) + 1;
4603
4604         if (len >= sizeof(tmp))
4605                 return -EINVAL;
4606
4607         if (copy_from_user(tmp, ubuf, len))
4608                 return -EFAULT;
4609
4610         tmp[len] = '\0';
4611
4612         ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4613                      &new[0], &new[1], &new[2], &new[3],
4614                      &new[4], &new[5], &new[6], &new[7]);
4615         if (ret != num_levels)
4616                 return -EINVAL;
4617
4618         drm_modeset_lock_all(dev);
4619
4620         for (level = 0; level < num_levels; level++)
4621                 wm[level] = new[level];
4622
4623         drm_modeset_unlock_all(dev);
4624
4625         return len;
4626 }
4627
4628
4629 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4630                                     size_t len, loff_t *offp)
4631 {
4632         struct seq_file *m = file->private_data;
4633         struct drm_device *dev = m->private;
4634         struct drm_i915_private *dev_priv = dev->dev_private;
4635         uint16_t *latencies;
4636
4637         if (INTEL_INFO(dev)->gen >= 9)
4638                 latencies = dev_priv->wm.skl_latency;
4639         else
4640                 latencies = to_i915(dev)->wm.pri_latency;
4641
4642         return wm_latency_write(file, ubuf, len, offp, latencies);
4643 }
4644
4645 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4646                                     size_t len, loff_t *offp)
4647 {
4648         struct seq_file *m = file->private_data;
4649         struct drm_device *dev = m->private;
4650         struct drm_i915_private *dev_priv = dev->dev_private;
4651         uint16_t *latencies;
4652
4653         if (INTEL_INFO(dev)->gen >= 9)
4654                 latencies = dev_priv->wm.skl_latency;
4655         else
4656                 latencies = to_i915(dev)->wm.spr_latency;
4657
4658         return wm_latency_write(file, ubuf, len, offp, latencies);
4659 }
4660
4661 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4662                                     size_t len, loff_t *offp)
4663 {
4664         struct seq_file *m = file->private_data;
4665         struct drm_device *dev = m->private;
4666         struct drm_i915_private *dev_priv = dev->dev_private;
4667         uint16_t *latencies;
4668
4669         if (INTEL_INFO(dev)->gen >= 9)
4670                 latencies = dev_priv->wm.skl_latency;
4671         else
4672                 latencies = to_i915(dev)->wm.cur_latency;
4673
4674         return wm_latency_write(file, ubuf, len, offp, latencies);
4675 }
4676
4677 static const struct file_operations i915_pri_wm_latency_fops = {
4678         .owner = THIS_MODULE,
4679         .open = pri_wm_latency_open,
4680         .read = seq_read,
4681         .llseek = seq_lseek,
4682         .release = single_release,
4683         .write = pri_wm_latency_write
4684 };
4685
4686 static const struct file_operations i915_spr_wm_latency_fops = {
4687         .owner = THIS_MODULE,
4688         .open = spr_wm_latency_open,
4689         .read = seq_read,
4690         .llseek = seq_lseek,
4691         .release = single_release,
4692         .write = spr_wm_latency_write
4693 };
4694
4695 static const struct file_operations i915_cur_wm_latency_fops = {
4696         .owner = THIS_MODULE,
4697         .open = cur_wm_latency_open,
4698         .read = seq_read,
4699         .llseek = seq_lseek,
4700         .release = single_release,
4701         .write = cur_wm_latency_write
4702 };
4703
4704 static int
4705 i915_wedged_get(void *data, u64 *val)
4706 {
4707         struct drm_device *dev = data;
4708         struct drm_i915_private *dev_priv = dev->dev_private;
4709
4710         *val = atomic_read(&dev_priv->gpu_error.reset_counter);
4711
4712         return 0;
4713 }
4714
4715 static int
4716 i915_wedged_set(void *data, u64 val)
4717 {
4718         struct drm_device *dev = data;
4719         struct drm_i915_private *dev_priv = dev->dev_private;
4720
4721         /*
4722          * There is no safeguard against this debugfs entry colliding
4723          * with the hangcheck calling same i915_handle_error() in
4724          * parallel, causing an explosion. For now we assume that the
4725          * test harness is responsible enough not to inject gpu hangs
4726          * while it is writing to 'i915_wedged'
4727          */
4728
4729         if (i915_reset_in_progress(&dev_priv->gpu_error))
4730                 return -EAGAIN;
4731
4732         intel_runtime_pm_get(dev_priv);
4733
4734         i915_handle_error(dev, val,
4735                           "Manually setting wedged to %llu", val);
4736
4737         intel_runtime_pm_put(dev_priv);
4738
4739         return 0;
4740 }
4741
4742 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4743                         i915_wedged_get, i915_wedged_set,
4744                         "%llu\n");
4745
4746 static int
4747 i915_ring_stop_get(void *data, u64 *val)
4748 {
4749         struct drm_device *dev = data;
4750         struct drm_i915_private *dev_priv = dev->dev_private;
4751
4752         *val = dev_priv->gpu_error.stop_rings;
4753
4754         return 0;
4755 }
4756
4757 static int
4758 i915_ring_stop_set(void *data, u64 val)
4759 {
4760         struct drm_device *dev = data;
4761         struct drm_i915_private *dev_priv = dev->dev_private;
4762         int ret;
4763
4764         DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
4765
4766         ret = mutex_lock_interruptible(&dev->struct_mutex);
4767         if (ret)
4768                 return ret;
4769
4770         dev_priv->gpu_error.stop_rings = val;
4771         mutex_unlock(&dev->struct_mutex);
4772
4773         return 0;
4774 }
4775
4776 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
4777                         i915_ring_stop_get, i915_ring_stop_set,
4778                         "0x%08llx\n");
4779
4780 static int
4781 i915_ring_missed_irq_get(void *data, u64 *val)
4782 {
4783         struct drm_device *dev = data;
4784         struct drm_i915_private *dev_priv = dev->dev_private;
4785
4786         *val = dev_priv->gpu_error.missed_irq_rings;
4787         return 0;
4788 }
4789
4790 static int
4791 i915_ring_missed_irq_set(void *data, u64 val)
4792 {
4793         struct drm_device *dev = data;
4794         struct drm_i915_private *dev_priv = dev->dev_private;
4795         int ret;
4796
4797         /* Lock against concurrent debugfs callers */
4798         ret = mutex_lock_interruptible(&dev->struct_mutex);
4799         if (ret)
4800                 return ret;
4801         dev_priv->gpu_error.missed_irq_rings = val;
4802         mutex_unlock(&dev->struct_mutex);
4803
4804         return 0;
4805 }
4806
4807 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4808                         i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4809                         "0x%08llx\n");
4810
4811 static int
4812 i915_ring_test_irq_get(void *data, u64 *val)
4813 {
4814         struct drm_device *dev = data;
4815         struct drm_i915_private *dev_priv = dev->dev_private;
4816
4817         *val = dev_priv->gpu_error.test_irq_rings;
4818
4819         return 0;
4820 }
4821
4822 static int
4823 i915_ring_test_irq_set(void *data, u64 val)
4824 {
4825         struct drm_device *dev = data;
4826         struct drm_i915_private *dev_priv = dev->dev_private;
4827         int ret;
4828
4829         DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4830
4831         /* Lock against concurrent debugfs callers */
4832         ret = mutex_lock_interruptible(&dev->struct_mutex);
4833         if (ret)
4834                 return ret;
4835
4836         dev_priv->gpu_error.test_irq_rings = val;
4837         mutex_unlock(&dev->struct_mutex);
4838
4839         return 0;
4840 }
4841
4842 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4843                         i915_ring_test_irq_get, i915_ring_test_irq_set,
4844                         "0x%08llx\n");
4845
4846 #define DROP_UNBOUND 0x1
4847 #define DROP_BOUND 0x2
4848 #define DROP_RETIRE 0x4
4849 #define DROP_ACTIVE 0x8
4850 #define DROP_ALL (DROP_UNBOUND | \
4851                   DROP_BOUND | \
4852                   DROP_RETIRE | \
4853                   DROP_ACTIVE)
4854 static int
4855 i915_drop_caches_get(void *data, u64 *val)
4856 {
4857         *val = DROP_ALL;
4858
4859         return 0;
4860 }
4861
4862 static int
4863 i915_drop_caches_set(void *data, u64 val)
4864 {
4865         struct drm_device *dev = data;
4866         struct drm_i915_private *dev_priv = dev->dev_private;
4867         int ret;
4868
4869         DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4870
4871         /* No need to check and wait for gpu resets, only libdrm auto-restarts
4872          * on ioctls on -EAGAIN. */
4873         ret = mutex_lock_interruptible(&dev->struct_mutex);
4874         if (ret)
4875                 return ret;
4876
4877         if (val & DROP_ACTIVE) {
4878                 ret = i915_gpu_idle(dev);
4879                 if (ret)
4880                         goto unlock;
4881         }
4882
4883         if (val & (DROP_RETIRE | DROP_ACTIVE))
4884                 i915_gem_retire_requests(dev);
4885
4886         if (val & DROP_BOUND)
4887                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4888
4889         if (val & DROP_UNBOUND)
4890                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4891
4892 unlock:
4893         mutex_unlock(&dev->struct_mutex);
4894
4895         return ret;
4896 }
4897
4898 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4899                         i915_drop_caches_get, i915_drop_caches_set,
4900                         "0x%08llx\n");
4901
4902 static int
4903 i915_max_freq_get(void *data, u64 *val)
4904 {
4905         struct drm_device *dev = data;
4906         struct drm_i915_private *dev_priv = dev->dev_private;
4907         int ret;
4908
4909         if (INTEL_INFO(dev)->gen < 6)
4910                 return -ENODEV;
4911
4912         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4913
4914         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4915         if (ret)
4916                 return ret;
4917
4918         *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4919         mutex_unlock(&dev_priv->rps.hw_lock);
4920
4921         return 0;
4922 }
4923
4924 static int
4925 i915_max_freq_set(void *data, u64 val)
4926 {
4927         struct drm_device *dev = data;
4928         struct drm_i915_private *dev_priv = dev->dev_private;
4929         u32 hw_max, hw_min;
4930         int ret;
4931
4932         if (INTEL_INFO(dev)->gen < 6)
4933                 return -ENODEV;
4934
4935         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4936
4937         DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4938
4939         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4940         if (ret)
4941                 return ret;
4942
4943         /*
4944          * Turbo will still be enabled, but won't go above the set value.
4945          */
4946         val = intel_freq_opcode(dev_priv, val);
4947
4948         hw_max = dev_priv->rps.max_freq;
4949         hw_min = dev_priv->rps.min_freq;
4950
4951         if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4952                 mutex_unlock(&dev_priv->rps.hw_lock);
4953                 return -EINVAL;
4954         }
4955
4956         dev_priv->rps.max_freq_softlimit = val;
4957
4958         intel_set_rps(dev, val);
4959
4960         mutex_unlock(&dev_priv->rps.hw_lock);
4961
4962         return 0;
4963 }
4964
4965 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4966                         i915_max_freq_get, i915_max_freq_set,
4967                         "%llu\n");
4968
4969 static int
4970 i915_min_freq_get(void *data, u64 *val)
4971 {
4972         struct drm_device *dev = data;
4973         struct drm_i915_private *dev_priv = dev->dev_private;
4974         int ret;
4975
4976         if (INTEL_INFO(dev)->gen < 6)
4977                 return -ENODEV;
4978
4979         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4980
4981         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4982         if (ret)
4983                 return ret;
4984
4985         *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4986         mutex_unlock(&dev_priv->rps.hw_lock);
4987
4988         return 0;
4989 }
4990
4991 static int
4992 i915_min_freq_set(void *data, u64 val)
4993 {
4994         struct drm_device *dev = data;
4995         struct drm_i915_private *dev_priv = dev->dev_private;
4996         u32 hw_max, hw_min;
4997         int ret;
4998
4999         if (INTEL_INFO(dev)->gen < 6)
5000                 return -ENODEV;
5001
5002         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5003
5004         DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
5005
5006         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
5007         if (ret)
5008                 return ret;
5009
5010         /*
5011          * Turbo will still be enabled, but won't go below the set value.
5012          */
5013         val = intel_freq_opcode(dev_priv, val);
5014
5015         hw_max = dev_priv->rps.max_freq;
5016         hw_min = dev_priv->rps.min_freq;
5017
5018         if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
5019                 mutex_unlock(&dev_priv->rps.hw_lock);
5020                 return -EINVAL;
5021         }
5022
5023         dev_priv->rps.min_freq_softlimit = val;
5024
5025         intel_set_rps(dev, val);
5026
5027         mutex_unlock(&dev_priv->rps.hw_lock);
5028
5029         return 0;
5030 }
5031
5032 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
5033                         i915_min_freq_get, i915_min_freq_set,
5034                         "%llu\n");
5035
5036 static int
5037 i915_cache_sharing_get(void *data, u64 *val)
5038 {
5039         struct drm_device *dev = data;
5040         struct drm_i915_private *dev_priv = dev->dev_private;
5041         u32 snpcr;
5042         int ret;
5043
5044         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5045                 return -ENODEV;
5046
5047         ret = mutex_lock_interruptible(&dev->struct_mutex);
5048         if (ret)
5049                 return ret;
5050         intel_runtime_pm_get(dev_priv);
5051
5052         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5053
5054         intel_runtime_pm_put(dev_priv);
5055         mutex_unlock(&dev_priv->dev->struct_mutex);
5056
5057         *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
5058
5059         return 0;
5060 }
5061
5062 static int
5063 i915_cache_sharing_set(void *data, u64 val)
5064 {
5065         struct drm_device *dev = data;
5066         struct drm_i915_private *dev_priv = dev->dev_private;
5067         u32 snpcr;
5068
5069         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5070                 return -ENODEV;
5071
5072         if (val > 3)
5073                 return -EINVAL;
5074
5075         intel_runtime_pm_get(dev_priv);
5076         DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
5077
5078         /* Update the cache sharing policy here as well */
5079         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5080         snpcr &= ~GEN6_MBC_SNPCR_MASK;
5081         snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
5082         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5083
5084         intel_runtime_pm_put(dev_priv);
5085         return 0;
5086 }
5087
5088 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
5089                         i915_cache_sharing_get, i915_cache_sharing_set,
5090                         "%llu\n");
5091
5092 struct sseu_dev_status {
5093         unsigned int slice_total;
5094         unsigned int subslice_total;
5095         unsigned int subslice_per_slice;
5096         unsigned int eu_total;
5097         unsigned int eu_per_subslice;
5098 };
5099
5100 static void cherryview_sseu_device_status(struct drm_device *dev,
5101                                           struct sseu_dev_status *stat)
5102 {
5103         struct drm_i915_private *dev_priv = dev->dev_private;
5104         int ss_max = 2;
5105         int ss;
5106         u32 sig1[ss_max], sig2[ss_max];
5107
5108         sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
5109         sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
5110         sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
5111         sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
5112
5113         for (ss = 0; ss < ss_max; ss++) {
5114                 unsigned int eu_cnt;
5115
5116                 if (sig1[ss] & CHV_SS_PG_ENABLE)
5117                         /* skip disabled subslice */
5118                         continue;
5119
5120                 stat->slice_total = 1;
5121                 stat->subslice_per_slice++;
5122                 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
5123                          ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
5124                          ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
5125                          ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
5126                 stat->eu_total += eu_cnt;
5127                 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
5128         }
5129         stat->subslice_total = stat->subslice_per_slice;
5130 }
5131
5132 static void gen9_sseu_device_status(struct drm_device *dev,
5133                                     struct sseu_dev_status *stat)
5134 {
5135         struct drm_i915_private *dev_priv = dev->dev_private;
5136         int s_max = 3, ss_max = 4;
5137         int s, ss;
5138         u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
5139
5140         /* BXT has a single slice and at most 3 subslices. */
5141         if (IS_BROXTON(dev)) {
5142                 s_max = 1;
5143                 ss_max = 3;
5144         }
5145
5146         for (s = 0; s < s_max; s++) {
5147                 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
5148                 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
5149                 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
5150         }
5151
5152         eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
5153                      GEN9_PGCTL_SSA_EU19_ACK |
5154                      GEN9_PGCTL_SSA_EU210_ACK |
5155                      GEN9_PGCTL_SSA_EU311_ACK;
5156         eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
5157                      GEN9_PGCTL_SSB_EU19_ACK |
5158                      GEN9_PGCTL_SSB_EU210_ACK |
5159                      GEN9_PGCTL_SSB_EU311_ACK;
5160
5161         for (s = 0; s < s_max; s++) {
5162                 unsigned int ss_cnt = 0;
5163
5164                 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
5165                         /* skip disabled slice */
5166                         continue;
5167
5168                 stat->slice_total++;
5169
5170                 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
5171                         ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
5172
5173                 for (ss = 0; ss < ss_max; ss++) {
5174                         unsigned int eu_cnt;
5175
5176                         if (IS_BROXTON(dev) &&
5177                             !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
5178                                 /* skip disabled subslice */
5179                                 continue;
5180
5181                         if (IS_BROXTON(dev))
5182                                 ss_cnt++;
5183
5184                         eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
5185                                                eu_mask[ss%2]);
5186                         stat->eu_total += eu_cnt;
5187                         stat->eu_per_subslice = max(stat->eu_per_subslice,
5188                                                     eu_cnt);
5189                 }
5190
5191                 stat->subslice_total += ss_cnt;
5192                 stat->subslice_per_slice = max(stat->subslice_per_slice,
5193                                                ss_cnt);
5194         }
5195 }
5196
5197 static void broadwell_sseu_device_status(struct drm_device *dev,
5198                                          struct sseu_dev_status *stat)
5199 {
5200         struct drm_i915_private *dev_priv = dev->dev_private;
5201         int s;
5202         u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
5203
5204         stat->slice_total = hweight32(slice_info & GEN8_LSLICESTAT_MASK);
5205
5206         if (stat->slice_total) {
5207                 stat->subslice_per_slice = INTEL_INFO(dev)->subslice_per_slice;
5208                 stat->subslice_total = stat->slice_total *
5209                                        stat->subslice_per_slice;
5210                 stat->eu_per_subslice = INTEL_INFO(dev)->eu_per_subslice;
5211                 stat->eu_total = stat->eu_per_subslice * stat->subslice_total;
5212
5213                 /* subtract fused off EU(s) from enabled slice(s) */
5214                 for (s = 0; s < stat->slice_total; s++) {
5215                         u8 subslice_7eu = INTEL_INFO(dev)->subslice_7eu[s];
5216
5217                         stat->eu_total -= hweight8(subslice_7eu);
5218                 }
5219         }
5220 }
5221
5222 static int i915_sseu_status(struct seq_file *m, void *unused)
5223 {
5224         struct drm_info_node *node = (struct drm_info_node *) m->private;
5225         struct drm_device *dev = node->minor->dev;
5226         struct sseu_dev_status stat;
5227
5228         if (INTEL_INFO(dev)->gen < 8)
5229                 return -ENODEV;
5230
5231         seq_puts(m, "SSEU Device Info\n");
5232         seq_printf(m, "  Available Slice Total: %u\n",
5233                    INTEL_INFO(dev)->slice_total);
5234         seq_printf(m, "  Available Subslice Total: %u\n",
5235                    INTEL_INFO(dev)->subslice_total);
5236         seq_printf(m, "  Available Subslice Per Slice: %u\n",
5237                    INTEL_INFO(dev)->subslice_per_slice);
5238         seq_printf(m, "  Available EU Total: %u\n",
5239                    INTEL_INFO(dev)->eu_total);
5240         seq_printf(m, "  Available EU Per Subslice: %u\n",
5241                    INTEL_INFO(dev)->eu_per_subslice);
5242         seq_printf(m, "  Has Slice Power Gating: %s\n",
5243                    yesno(INTEL_INFO(dev)->has_slice_pg));
5244         seq_printf(m, "  Has Subslice Power Gating: %s\n",
5245                    yesno(INTEL_INFO(dev)->has_subslice_pg));
5246         seq_printf(m, "  Has EU Power Gating: %s\n",
5247                    yesno(INTEL_INFO(dev)->has_eu_pg));
5248
5249         seq_puts(m, "SSEU Device Status\n");
5250         memset(&stat, 0, sizeof(stat));
5251         if (IS_CHERRYVIEW(dev)) {
5252                 cherryview_sseu_device_status(dev, &stat);
5253         } else if (IS_BROADWELL(dev)) {
5254                 broadwell_sseu_device_status(dev, &stat);
5255         } else if (INTEL_INFO(dev)->gen >= 9) {
5256                 gen9_sseu_device_status(dev, &stat);
5257         }
5258         seq_printf(m, "  Enabled Slice Total: %u\n",
5259                    stat.slice_total);
5260         seq_printf(m, "  Enabled Subslice Total: %u\n",
5261                    stat.subslice_total);
5262         seq_printf(m, "  Enabled Subslice Per Slice: %u\n",
5263                    stat.subslice_per_slice);
5264         seq_printf(m, "  Enabled EU Total: %u\n",
5265                    stat.eu_total);
5266         seq_printf(m, "  Enabled EU Per Subslice: %u\n",
5267                    stat.eu_per_subslice);
5268
5269         return 0;
5270 }
5271
5272 static int i915_forcewake_open(struct inode *inode, struct file *file)
5273 {
5274         struct drm_device *dev = inode->i_private;
5275         struct drm_i915_private *dev_priv = dev->dev_private;
5276
5277         if (INTEL_INFO(dev)->gen < 6)
5278                 return 0;
5279
5280         intel_runtime_pm_get(dev_priv);
5281         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5282
5283         return 0;
5284 }
5285
5286 static int i915_forcewake_release(struct inode *inode, struct file *file)
5287 {
5288         struct drm_device *dev = inode->i_private;
5289         struct drm_i915_private *dev_priv = dev->dev_private;
5290
5291         if (INTEL_INFO(dev)->gen < 6)
5292                 return 0;
5293
5294         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5295         intel_runtime_pm_put(dev_priv);
5296
5297         return 0;
5298 }
5299
5300 static const struct file_operations i915_forcewake_fops = {
5301         .owner = THIS_MODULE,
5302         .open = i915_forcewake_open,
5303         .release = i915_forcewake_release,
5304 };
5305
5306 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5307 {
5308         struct drm_device *dev = minor->dev;
5309         struct dentry *ent;
5310
5311         ent = debugfs_create_file("i915_forcewake_user",
5312                                   S_IRUSR,
5313                                   root, dev,
5314                                   &i915_forcewake_fops);
5315         if (!ent)
5316                 return -ENOMEM;
5317
5318         return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
5319 }
5320
5321 static int i915_debugfs_create(struct dentry *root,
5322                                struct drm_minor *minor,
5323                                const char *name,
5324                                const struct file_operations *fops)
5325 {
5326         struct drm_device *dev = minor->dev;
5327         struct dentry *ent;
5328
5329         ent = debugfs_create_file(name,
5330                                   S_IRUGO | S_IWUSR,
5331                                   root, dev,
5332                                   fops);
5333         if (!ent)
5334                 return -ENOMEM;
5335
5336         return drm_add_fake_info_node(minor, ent, fops);
5337 }
5338
5339 static const struct drm_info_list i915_debugfs_list[] = {
5340         {"i915_capabilities", i915_capabilities, 0},
5341         {"i915_gem_objects", i915_gem_object_info, 0},
5342         {"i915_gem_gtt", i915_gem_gtt_info, 0},
5343         {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
5344         {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
5345         {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
5346         {"i915_gem_stolen", i915_gem_stolen_list_info },
5347         {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
5348         {"i915_gem_request", i915_gem_request_info, 0},
5349         {"i915_gem_seqno", i915_gem_seqno_info, 0},
5350         {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
5351         {"i915_gem_interrupt", i915_interrupt_info, 0},
5352         {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5353         {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5354         {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
5355         {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
5356         {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
5357         {"i915_guc_info", i915_guc_info, 0},
5358         {"i915_guc_load_status", i915_guc_load_status_info, 0},
5359         {"i915_guc_log_dump", i915_guc_log_dump, 0},
5360         {"i915_frequency_info", i915_frequency_info, 0},
5361         {"i915_hangcheck_info", i915_hangcheck_info, 0},
5362         {"i915_drpc_info", i915_drpc_info, 0},
5363         {"i915_emon_status", i915_emon_status, 0},
5364         {"i915_ring_freq_table", i915_ring_freq_table, 0},
5365         {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
5366         {"i915_fbc_status", i915_fbc_status, 0},
5367         {"i915_ips_status", i915_ips_status, 0},
5368         {"i915_sr_status", i915_sr_status, 0},
5369         {"i915_opregion", i915_opregion, 0},
5370         {"i915_vbt", i915_vbt, 0},
5371         {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
5372         {"i915_context_status", i915_context_status, 0},
5373         {"i915_dump_lrc", i915_dump_lrc, 0},
5374         {"i915_execlists", i915_execlists, 0},
5375         {"i915_forcewake_domains", i915_forcewake_domains, 0},
5376         {"i915_swizzle_info", i915_swizzle_info, 0},
5377         {"i915_ppgtt_info", i915_ppgtt_info, 0},
5378         {"i915_llc", i915_llc, 0},
5379         {"i915_edp_psr_status", i915_edp_psr_status, 0},
5380         {"i915_sink_crc_eDP1", i915_sink_crc, 0},
5381         {"i915_energy_uJ", i915_energy_uJ, 0},
5382         {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
5383         {"i915_power_domain_info", i915_power_domain_info, 0},
5384         {"i915_dmc_info", i915_dmc_info, 0},
5385         {"i915_display_info", i915_display_info, 0},
5386         {"i915_semaphore_status", i915_semaphore_status, 0},
5387         {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
5388         {"i915_dp_mst_info", i915_dp_mst_info, 0},
5389         {"i915_wa_registers", i915_wa_registers, 0},
5390         {"i915_ddb_info", i915_ddb_info, 0},
5391         {"i915_sseu_status", i915_sseu_status, 0},
5392         {"i915_drrs_status", i915_drrs_status, 0},
5393         {"i915_rps_boost_info", i915_rps_boost_info, 0},
5394 };
5395 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5396
5397 static const struct i915_debugfs_files {
5398         const char *name;
5399         const struct file_operations *fops;
5400 } i915_debugfs_files[] = {
5401         {"i915_wedged", &i915_wedged_fops},
5402         {"i915_max_freq", &i915_max_freq_fops},
5403         {"i915_min_freq", &i915_min_freq_fops},
5404         {"i915_cache_sharing", &i915_cache_sharing_fops},
5405         {"i915_ring_stop", &i915_ring_stop_fops},
5406         {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5407         {"i915_ring_test_irq", &i915_ring_test_irq_fops},
5408         {"i915_gem_drop_caches", &i915_drop_caches_fops},
5409         {"i915_error_state", &i915_error_state_fops},
5410         {"i915_next_seqno", &i915_next_seqno_fops},
5411         {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
5412         {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5413         {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5414         {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
5415         {"i915_fbc_false_color", &i915_fbc_fc_fops},
5416         {"i915_dp_test_data", &i915_displayport_test_data_fops},
5417         {"i915_dp_test_type", &i915_displayport_test_type_fops},
5418         {"i915_dp_test_active", &i915_displayport_test_active_fops}
5419 };
5420
5421 void intel_display_crc_init(struct drm_device *dev)
5422 {
5423         struct drm_i915_private *dev_priv = dev->dev_private;
5424         enum pipe pipe;
5425
5426         for_each_pipe(dev_priv, pipe) {
5427                 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
5428
5429                 pipe_crc->opened = false;
5430                 spin_lock_init(&pipe_crc->lock);
5431                 init_waitqueue_head(&pipe_crc->wq);
5432         }
5433 }
5434
5435 int i915_debugfs_init(struct drm_minor *minor)
5436 {
5437         int ret, i;
5438
5439         ret = i915_forcewake_create(minor->debugfs_root, minor);
5440         if (ret)
5441                 return ret;
5442
5443         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5444                 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5445                 if (ret)
5446                         return ret;
5447         }
5448
5449         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5450                 ret = i915_debugfs_create(minor->debugfs_root, minor,
5451                                           i915_debugfs_files[i].name,
5452                                           i915_debugfs_files[i].fops);
5453                 if (ret)
5454                         return ret;
5455         }
5456
5457         return drm_debugfs_create_files(i915_debugfs_list,
5458                                         I915_DEBUGFS_ENTRIES,
5459                                         minor->debugfs_root, minor);
5460 }
5461
5462 void i915_debugfs_cleanup(struct drm_minor *minor)
5463 {
5464         int i;
5465
5466         drm_debugfs_remove_files(i915_debugfs_list,
5467                                  I915_DEBUGFS_ENTRIES, minor);
5468
5469         drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
5470                                  1, minor);
5471
5472         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5473                 struct drm_info_list *info_list =
5474                         (struct drm_info_list *)&i915_pipe_crc_data[i];
5475
5476                 drm_debugfs_remove_files(info_list, 1, minor);
5477         }
5478
5479         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5480                 struct drm_info_list *info_list =
5481                         (struct drm_info_list *) i915_debugfs_files[i].fops;
5482
5483                 drm_debugfs_remove_files(info_list, 1, minor);
5484         }
5485 }
5486
5487 struct dpcd_block {
5488         /* DPCD dump start address. */
5489         unsigned int offset;
5490         /* DPCD dump end address, inclusive. If unset, .size will be used. */
5491         unsigned int end;
5492         /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5493         size_t size;
5494         /* Only valid for eDP. */
5495         bool edp;
5496 };
5497
5498 static const struct dpcd_block i915_dpcd_debug[] = {
5499         { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5500         { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5501         { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5502         { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5503         { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5504         { .offset = DP_SET_POWER },
5505         { .offset = DP_EDP_DPCD_REV },
5506         { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5507         { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5508         { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5509 };
5510
5511 static int i915_dpcd_show(struct seq_file *m, void *data)
5512 {
5513         struct drm_connector *connector = m->private;
5514         struct intel_dp *intel_dp =
5515                 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5516         uint8_t buf[16];
5517         ssize_t err;
5518         int i;
5519
5520         if (connector->status != connector_status_connected)
5521                 return -ENODEV;
5522
5523         for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5524                 const struct dpcd_block *b = &i915_dpcd_debug[i];
5525                 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5526
5527                 if (b->edp &&
5528                     connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5529                         continue;
5530
5531                 /* low tech for now */
5532                 if (WARN_ON(size > sizeof(buf)))
5533                         continue;
5534
5535                 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5536                 if (err <= 0) {
5537                         DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5538                                   size, b->offset, err);
5539                         continue;
5540                 }
5541
5542                 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
5543         }
5544
5545         return 0;
5546 }
5547
5548 static int i915_dpcd_open(struct inode *inode, struct file *file)
5549 {
5550         return single_open(file, i915_dpcd_show, inode->i_private);
5551 }
5552
5553 static const struct file_operations i915_dpcd_fops = {
5554         .owner = THIS_MODULE,
5555         .open = i915_dpcd_open,
5556         .read = seq_read,
5557         .llseek = seq_lseek,
5558         .release = single_release,
5559 };
5560
5561 /**
5562  * i915_debugfs_connector_add - add i915 specific connector debugfs files
5563  * @connector: pointer to a registered drm_connector
5564  *
5565  * Cleanup will be done by drm_connector_unregister() through a call to
5566  * drm_debugfs_connector_remove().
5567  *
5568  * Returns 0 on success, negative error codes on error.
5569  */
5570 int i915_debugfs_connector_add(struct drm_connector *connector)
5571 {
5572         struct dentry *root = connector->debugfs_entry;
5573
5574         /* The connector must have been registered beforehands. */
5575         if (!root)
5576                 return -ENODEV;
5577
5578         if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5579             connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5580                 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,
5581                                     &i915_dpcd_fops);
5582
5583         return 0;
5584 }