2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
49 /* As the drm_debugfs_init() routines are called before dev->dev_private is
50 * allocated we need to hook into the minor for release. */
52 drm_add_fake_info_node(struct drm_minor *minor,
56 struct drm_info_node *node;
58 node = kmalloc(sizeof(*node), GFP_KERNEL);
66 node->info_ent = (void *) key;
68 mutex_lock(&minor->debugfs_lock);
69 list_add(&node->list, &minor->debugfs_list);
70 mutex_unlock(&minor->debugfs_lock);
75 static int i915_capabilities(struct seq_file *m, void *data)
77 struct drm_info_node *node = m->private;
78 struct drm_device *dev = node->minor->dev;
79 const struct intel_device_info *info = INTEL_INFO(dev);
81 seq_printf(m, "gen: %d\n", info->gen);
82 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
83 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
84 #define SEP_SEMICOLON ;
85 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
92 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
100 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
102 switch (obj->tiling_mode) {
104 case I915_TILING_NONE: return " ";
105 case I915_TILING_X: return "X";
106 case I915_TILING_Y: return "Y";
110 static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
112 return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
115 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
118 struct i915_vma *vma;
120 list_for_each_entry(vma, &obj->vma_list, obj_link) {
121 if (vma->is_ggtt && drm_mm_node_allocated(&vma->node))
122 size += vma->node.size;
129 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
131 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
132 struct intel_engine_cs *ring;
133 struct i915_vma *vma;
137 seq_printf(m, "%pK: %s%s%s%s %8zdKiB %02x %02x [ ",
139 obj->active ? "*" : " ",
141 get_tiling_flag(obj),
142 get_global_flag(obj),
143 obj->base.size / 1024,
144 obj->base.read_domains,
145 obj->base.write_domain);
146 for_each_ring(ring, dev_priv, i)
148 i915_gem_request_get_seqno(obj->last_read_req[i]));
149 seq_printf(m, "] %x %x%s%s%s",
150 i915_gem_request_get_seqno(obj->last_write_req),
151 i915_gem_request_get_seqno(obj->last_fenced_req),
152 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
153 obj->dirty ? " dirty" : "",
154 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
156 seq_printf(m, " (name: %d)", obj->base.name);
157 list_for_each_entry(vma, &obj->vma_list, obj_link) {
158 if (vma->pin_count > 0)
161 seq_printf(m, " (pinned x %d)", pin_count);
162 if (obj->pin_display)
163 seq_printf(m, " (display)");
164 if (obj->fence_reg != I915_FENCE_REG_NONE)
165 seq_printf(m, " (fence: %d)", obj->fence_reg);
166 list_for_each_entry(vma, &obj->vma_list, obj_link) {
167 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
168 vma->is_ggtt ? "g" : "pp",
169 vma->node.start, vma->node.size);
171 seq_printf(m, ", type: %u", vma->ggtt_view.type);
175 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
176 if (obj->pin_display || obj->fault_mappable) {
178 if (obj->pin_display)
180 if (obj->fault_mappable)
183 seq_printf(m, " (%s mappable)", s);
185 if (obj->last_write_req != NULL)
186 seq_printf(m, " (%s)",
187 i915_gem_request_get_ring(obj->last_write_req)->name);
188 if (obj->frontbuffer_bits)
189 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
192 static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
194 seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
195 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
199 static int i915_gem_object_list_info(struct seq_file *m, void *data)
201 struct drm_info_node *node = m->private;
202 uintptr_t list = (uintptr_t) node->info_ent->data;
203 struct list_head *head;
204 struct drm_device *dev = node->minor->dev;
205 struct drm_i915_private *dev_priv = dev->dev_private;
206 struct i915_address_space *vm = &dev_priv->gtt.base;
207 struct i915_vma *vma;
208 u64 total_obj_size, total_gtt_size;
211 ret = mutex_lock_interruptible(&dev->struct_mutex);
215 /* FIXME: the user of this interface might want more than just GGTT */
218 seq_puts(m, "Active:\n");
219 head = &vm->active_list;
222 seq_puts(m, "Inactive:\n");
223 head = &vm->inactive_list;
226 mutex_unlock(&dev->struct_mutex);
230 total_obj_size = total_gtt_size = count = 0;
231 list_for_each_entry(vma, head, vm_link) {
233 describe_obj(m, vma->obj);
235 total_obj_size += vma->obj->base.size;
236 total_gtt_size += vma->node.size;
239 mutex_unlock(&dev->struct_mutex);
241 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
242 count, total_obj_size, total_gtt_size);
246 static int obj_rank_by_stolen(void *priv,
247 struct list_head *A, struct list_head *B)
249 struct drm_i915_gem_object *a =
250 container_of(A, struct drm_i915_gem_object, obj_exec_link);
251 struct drm_i915_gem_object *b =
252 container_of(B, struct drm_i915_gem_object, obj_exec_link);
254 if (a->stolen->start < b->stolen->start)
256 if (a->stolen->start > b->stolen->start)
261 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
263 struct drm_info_node *node = m->private;
264 struct drm_device *dev = node->minor->dev;
265 struct drm_i915_private *dev_priv = dev->dev_private;
266 struct drm_i915_gem_object *obj;
267 u64 total_obj_size, total_gtt_size;
271 ret = mutex_lock_interruptible(&dev->struct_mutex);
275 total_obj_size = total_gtt_size = count = 0;
276 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
277 if (obj->stolen == NULL)
280 list_add(&obj->obj_exec_link, &stolen);
282 total_obj_size += obj->base.size;
283 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
286 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
287 if (obj->stolen == NULL)
290 list_add(&obj->obj_exec_link, &stolen);
292 total_obj_size += obj->base.size;
295 list_sort(NULL, &stolen, obj_rank_by_stolen);
296 seq_puts(m, "Stolen:\n");
297 while (!list_empty(&stolen)) {
298 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
300 describe_obj(m, obj);
302 list_del_init(&obj->obj_exec_link);
304 mutex_unlock(&dev->struct_mutex);
306 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
307 count, total_obj_size, total_gtt_size);
311 #define count_objects(list, member) do { \
312 list_for_each_entry(obj, list, member) { \
313 size += i915_gem_obj_total_ggtt_size(obj); \
315 if (obj->map_and_fenceable) { \
316 mappable_size += i915_gem_obj_ggtt_size(obj); \
323 struct drm_i915_file_private *file_priv;
327 u64 active, inactive;
330 static int per_file_stats(int id, void *ptr, void *data)
332 struct drm_i915_gem_object *obj = ptr;
333 struct file_stats *stats = data;
334 struct i915_vma *vma;
337 stats->total += obj->base.size;
339 if (obj->base.name || obj->base.dma_buf)
340 stats->shared += obj->base.size;
342 if (USES_FULL_PPGTT(obj->base.dev)) {
343 list_for_each_entry(vma, &obj->vma_list, obj_link) {
344 struct i915_hw_ppgtt *ppgtt;
346 if (!drm_mm_node_allocated(&vma->node))
350 stats->global += obj->base.size;
354 ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
355 if (ppgtt->file_priv != stats->file_priv)
358 if (obj->active) /* XXX per-vma statistic */
359 stats->active += obj->base.size;
361 stats->inactive += obj->base.size;
366 if (i915_gem_obj_ggtt_bound(obj)) {
367 stats->global += obj->base.size;
369 stats->active += obj->base.size;
371 stats->inactive += obj->base.size;
376 if (!list_empty(&obj->global_list))
377 stats->unbound += obj->base.size;
382 #define print_file_stats(m, name, stats) do { \
384 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
395 static void print_batch_pool_stats(struct seq_file *m,
396 struct drm_i915_private *dev_priv)
398 struct drm_i915_gem_object *obj;
399 struct file_stats stats;
400 struct intel_engine_cs *ring;
403 memset(&stats, 0, sizeof(stats));
405 for_each_ring(ring, dev_priv, i) {
406 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
407 list_for_each_entry(obj,
408 &ring->batch_pool.cache_list[j],
410 per_file_stats(0, obj, &stats);
414 print_file_stats(m, "[k]batch pool", stats);
417 #define count_vmas(list, member) do { \
418 list_for_each_entry(vma, list, member) { \
419 size += i915_gem_obj_total_ggtt_size(vma->obj); \
421 if (vma->obj->map_and_fenceable) { \
422 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
428 static int i915_gem_object_info(struct seq_file *m, void* data)
430 struct drm_info_node *node = m->private;
431 struct drm_device *dev = node->minor->dev;
432 struct drm_i915_private *dev_priv = dev->dev_private;
433 u32 count, mappable_count, purgeable_count;
434 u64 size, mappable_size, purgeable_size;
435 struct drm_i915_gem_object *obj;
436 struct i915_address_space *vm = &dev_priv->gtt.base;
437 struct drm_file *file;
438 struct i915_vma *vma;
441 ret = mutex_lock_interruptible(&dev->struct_mutex);
445 seq_printf(m, "%u objects, %zu bytes\n",
446 dev_priv->mm.object_count,
447 dev_priv->mm.object_memory);
449 size = count = mappable_size = mappable_count = 0;
450 count_objects(&dev_priv->mm.bound_list, global_list);
451 seq_printf(m, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
452 count, mappable_count, size, mappable_size);
454 size = count = mappable_size = mappable_count = 0;
455 count_vmas(&vm->active_list, vm_link);
456 seq_printf(m, " %u [%u] active objects, %llu [%llu] bytes\n",
457 count, mappable_count, size, mappable_size);
459 size = count = mappable_size = mappable_count = 0;
460 count_vmas(&vm->inactive_list, vm_link);
461 seq_printf(m, " %u [%u] inactive objects, %llu [%llu] bytes\n",
462 count, mappable_count, size, mappable_size);
464 size = count = purgeable_size = purgeable_count = 0;
465 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
466 size += obj->base.size, ++count;
467 if (obj->madv == I915_MADV_DONTNEED)
468 purgeable_size += obj->base.size, ++purgeable_count;
470 seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
472 size = count = mappable_size = mappable_count = 0;
473 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
474 if (obj->fault_mappable) {
475 size += i915_gem_obj_ggtt_size(obj);
478 if (obj->pin_display) {
479 mappable_size += i915_gem_obj_ggtt_size(obj);
482 if (obj->madv == I915_MADV_DONTNEED) {
483 purgeable_size += obj->base.size;
487 seq_printf(m, "%u purgeable objects, %llu bytes\n",
488 purgeable_count, purgeable_size);
489 seq_printf(m, "%u pinned mappable objects, %llu bytes\n",
490 mappable_count, mappable_size);
491 seq_printf(m, "%u fault mappable objects, %llu bytes\n",
494 seq_printf(m, "%llu [%llu] gtt total\n",
495 dev_priv->gtt.base.total,
496 (u64)dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
499 print_batch_pool_stats(m, dev_priv);
500 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
501 struct file_stats stats;
502 struct task_struct *task;
504 memset(&stats, 0, sizeof(stats));
505 stats.file_priv = file->driver_priv;
506 spin_lock(&file->table_lock);
507 idr_for_each(&file->object_idr, per_file_stats, &stats);
508 spin_unlock(&file->table_lock);
510 * Although we have a valid reference on file->pid, that does
511 * not guarantee that the task_struct who called get_pid() is
512 * still alive (e.g. get_pid(current) => fork() => exit()).
513 * Therefore, we need to protect this ->comm access using RCU.
516 task = pid_task(file->pid, PIDTYPE_PID);
517 print_file_stats(m, task ? task->comm : "<unknown>", stats);
521 mutex_unlock(&dev->struct_mutex);
526 static int i915_gem_gtt_info(struct seq_file *m, void *data)
528 struct drm_info_node *node = m->private;
529 struct drm_device *dev = node->minor->dev;
530 uintptr_t list = (uintptr_t) node->info_ent->data;
531 struct drm_i915_private *dev_priv = dev->dev_private;
532 struct drm_i915_gem_object *obj;
533 u64 total_obj_size, total_gtt_size;
536 ret = mutex_lock_interruptible(&dev->struct_mutex);
540 total_obj_size = total_gtt_size = count = 0;
541 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
542 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
546 describe_obj(m, obj);
548 total_obj_size += obj->base.size;
549 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
553 mutex_unlock(&dev->struct_mutex);
555 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
556 count, total_obj_size, total_gtt_size);
561 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
563 struct drm_info_node *node = m->private;
564 struct drm_device *dev = node->minor->dev;
565 struct drm_i915_private *dev_priv = dev->dev_private;
566 struct intel_crtc *crtc;
569 ret = mutex_lock_interruptible(&dev->struct_mutex);
573 for_each_intel_crtc(dev, crtc) {
574 const char pipe = pipe_name(crtc->pipe);
575 const char plane = plane_name(crtc->plane);
576 struct intel_unpin_work *work;
578 spin_lock_irq(&dev->event_lock);
579 work = crtc->unpin_work;
581 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
586 if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
587 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
590 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
593 if (work->flip_queued_req) {
594 struct intel_engine_cs *ring =
595 i915_gem_request_get_ring(work->flip_queued_req);
597 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
599 i915_gem_request_get_seqno(work->flip_queued_req),
600 dev_priv->next_seqno,
601 ring->get_seqno(ring, true),
602 i915_gem_request_completed(work->flip_queued_req, true));
604 seq_printf(m, "Flip not associated with any ring\n");
605 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
606 work->flip_queued_vblank,
607 work->flip_ready_vblank,
608 drm_crtc_vblank_count(&crtc->base));
609 if (work->enable_stall_check)
610 seq_puts(m, "Stall check enabled, ");
612 seq_puts(m, "Stall check waiting for page flip ioctl, ");
613 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
615 if (INTEL_INFO(dev)->gen >= 4)
616 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
618 addr = I915_READ(DSPADDR(crtc->plane));
619 seq_printf(m, "Current scanout address 0x%08x\n", addr);
621 if (work->pending_flip_obj) {
622 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
623 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
626 spin_unlock_irq(&dev->event_lock);
629 mutex_unlock(&dev->struct_mutex);
634 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
636 struct drm_info_node *node = m->private;
637 struct drm_device *dev = node->minor->dev;
638 struct drm_i915_private *dev_priv = dev->dev_private;
639 struct drm_i915_gem_object *obj;
640 struct intel_engine_cs *ring;
644 ret = mutex_lock_interruptible(&dev->struct_mutex);
648 for_each_ring(ring, dev_priv, i) {
649 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
653 list_for_each_entry(obj,
654 &ring->batch_pool.cache_list[j],
657 seq_printf(m, "%s cache[%d]: %d objects\n",
658 ring->name, j, count);
660 list_for_each_entry(obj,
661 &ring->batch_pool.cache_list[j],
664 describe_obj(m, obj);
672 seq_printf(m, "total: %d\n", total);
674 mutex_unlock(&dev->struct_mutex);
679 static int i915_gem_request_info(struct seq_file *m, void *data)
681 struct drm_info_node *node = m->private;
682 struct drm_device *dev = node->minor->dev;
683 struct drm_i915_private *dev_priv = dev->dev_private;
684 struct intel_engine_cs *ring;
685 struct drm_i915_gem_request *req;
688 ret = mutex_lock_interruptible(&dev->struct_mutex);
693 for_each_ring(ring, dev_priv, i) {
697 list_for_each_entry(req, &ring->request_list, list)
702 seq_printf(m, "%s requests: %d\n", ring->name, count);
703 list_for_each_entry(req, &ring->request_list, list) {
704 struct task_struct *task;
709 task = pid_task(req->pid, PIDTYPE_PID);
710 seq_printf(m, " %x @ %d: %s [%d]\n",
712 (int) (jiffies - req->emitted_jiffies),
713 task ? task->comm : "<unknown>",
714 task ? task->pid : -1);
720 mutex_unlock(&dev->struct_mutex);
723 seq_puts(m, "No requests\n");
728 static void i915_ring_seqno_info(struct seq_file *m,
729 struct intel_engine_cs *ring)
731 if (ring->get_seqno) {
732 seq_printf(m, "Current sequence (%s): %x\n",
733 ring->name, ring->get_seqno(ring, false));
737 static int i915_gem_seqno_info(struct seq_file *m, void *data)
739 struct drm_info_node *node = m->private;
740 struct drm_device *dev = node->minor->dev;
741 struct drm_i915_private *dev_priv = dev->dev_private;
742 struct intel_engine_cs *ring;
745 ret = mutex_lock_interruptible(&dev->struct_mutex);
748 intel_runtime_pm_get(dev_priv);
750 for_each_ring(ring, dev_priv, i)
751 i915_ring_seqno_info(m, ring);
753 intel_runtime_pm_put(dev_priv);
754 mutex_unlock(&dev->struct_mutex);
760 static int i915_interrupt_info(struct seq_file *m, void *data)
762 struct drm_info_node *node = m->private;
763 struct drm_device *dev = node->minor->dev;
764 struct drm_i915_private *dev_priv = dev->dev_private;
765 struct intel_engine_cs *ring;
768 ret = mutex_lock_interruptible(&dev->struct_mutex);
771 intel_runtime_pm_get(dev_priv);
773 if (IS_CHERRYVIEW(dev)) {
774 seq_printf(m, "Master Interrupt Control:\t%08x\n",
775 I915_READ(GEN8_MASTER_IRQ));
777 seq_printf(m, "Display IER:\t%08x\n",
779 seq_printf(m, "Display IIR:\t%08x\n",
781 seq_printf(m, "Display IIR_RW:\t%08x\n",
782 I915_READ(VLV_IIR_RW));
783 seq_printf(m, "Display IMR:\t%08x\n",
785 for_each_pipe(dev_priv, pipe)
786 seq_printf(m, "Pipe %c stat:\t%08x\n",
788 I915_READ(PIPESTAT(pipe)));
790 seq_printf(m, "Port hotplug:\t%08x\n",
791 I915_READ(PORT_HOTPLUG_EN));
792 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
793 I915_READ(VLV_DPFLIPSTAT));
794 seq_printf(m, "DPINVGTT:\t%08x\n",
795 I915_READ(DPINVGTT));
797 for (i = 0; i < 4; i++) {
798 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
799 i, I915_READ(GEN8_GT_IMR(i)));
800 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
801 i, I915_READ(GEN8_GT_IIR(i)));
802 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
803 i, I915_READ(GEN8_GT_IER(i)));
806 seq_printf(m, "PCU interrupt mask:\t%08x\n",
807 I915_READ(GEN8_PCU_IMR));
808 seq_printf(m, "PCU interrupt identity:\t%08x\n",
809 I915_READ(GEN8_PCU_IIR));
810 seq_printf(m, "PCU interrupt enable:\t%08x\n",
811 I915_READ(GEN8_PCU_IER));
812 } else if (INTEL_INFO(dev)->gen >= 8) {
813 seq_printf(m, "Master Interrupt Control:\t%08x\n",
814 I915_READ(GEN8_MASTER_IRQ));
816 for (i = 0; i < 4; i++) {
817 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
818 i, I915_READ(GEN8_GT_IMR(i)));
819 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
820 i, I915_READ(GEN8_GT_IIR(i)));
821 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
822 i, I915_READ(GEN8_GT_IER(i)));
825 for_each_pipe(dev_priv, pipe) {
826 enum intel_display_power_domain power_domain;
828 power_domain = POWER_DOMAIN_PIPE(pipe);
829 if (!intel_display_power_get_if_enabled(dev_priv,
831 seq_printf(m, "Pipe %c power disabled\n",
835 seq_printf(m, "Pipe %c IMR:\t%08x\n",
837 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
838 seq_printf(m, "Pipe %c IIR:\t%08x\n",
840 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
841 seq_printf(m, "Pipe %c IER:\t%08x\n",
843 I915_READ(GEN8_DE_PIPE_IER(pipe)));
845 intel_display_power_put(dev_priv, power_domain);
848 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
849 I915_READ(GEN8_DE_PORT_IMR));
850 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
851 I915_READ(GEN8_DE_PORT_IIR));
852 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
853 I915_READ(GEN8_DE_PORT_IER));
855 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
856 I915_READ(GEN8_DE_MISC_IMR));
857 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
858 I915_READ(GEN8_DE_MISC_IIR));
859 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
860 I915_READ(GEN8_DE_MISC_IER));
862 seq_printf(m, "PCU interrupt mask:\t%08x\n",
863 I915_READ(GEN8_PCU_IMR));
864 seq_printf(m, "PCU interrupt identity:\t%08x\n",
865 I915_READ(GEN8_PCU_IIR));
866 seq_printf(m, "PCU interrupt enable:\t%08x\n",
867 I915_READ(GEN8_PCU_IER));
868 } else if (IS_VALLEYVIEW(dev)) {
869 seq_printf(m, "Display IER:\t%08x\n",
871 seq_printf(m, "Display IIR:\t%08x\n",
873 seq_printf(m, "Display IIR_RW:\t%08x\n",
874 I915_READ(VLV_IIR_RW));
875 seq_printf(m, "Display IMR:\t%08x\n",
877 for_each_pipe(dev_priv, pipe)
878 seq_printf(m, "Pipe %c stat:\t%08x\n",
880 I915_READ(PIPESTAT(pipe)));
882 seq_printf(m, "Master IER:\t%08x\n",
883 I915_READ(VLV_MASTER_IER));
885 seq_printf(m, "Render IER:\t%08x\n",
887 seq_printf(m, "Render IIR:\t%08x\n",
889 seq_printf(m, "Render IMR:\t%08x\n",
892 seq_printf(m, "PM IER:\t\t%08x\n",
893 I915_READ(GEN6_PMIER));
894 seq_printf(m, "PM IIR:\t\t%08x\n",
895 I915_READ(GEN6_PMIIR));
896 seq_printf(m, "PM IMR:\t\t%08x\n",
897 I915_READ(GEN6_PMIMR));
899 seq_printf(m, "Port hotplug:\t%08x\n",
900 I915_READ(PORT_HOTPLUG_EN));
901 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
902 I915_READ(VLV_DPFLIPSTAT));
903 seq_printf(m, "DPINVGTT:\t%08x\n",
904 I915_READ(DPINVGTT));
906 } else if (!HAS_PCH_SPLIT(dev)) {
907 seq_printf(m, "Interrupt enable: %08x\n",
909 seq_printf(m, "Interrupt identity: %08x\n",
911 seq_printf(m, "Interrupt mask: %08x\n",
913 for_each_pipe(dev_priv, pipe)
914 seq_printf(m, "Pipe %c stat: %08x\n",
916 I915_READ(PIPESTAT(pipe)));
918 seq_printf(m, "North Display Interrupt enable: %08x\n",
920 seq_printf(m, "North Display Interrupt identity: %08x\n",
922 seq_printf(m, "North Display Interrupt mask: %08x\n",
924 seq_printf(m, "South Display Interrupt enable: %08x\n",
926 seq_printf(m, "South Display Interrupt identity: %08x\n",
928 seq_printf(m, "South Display Interrupt mask: %08x\n",
930 seq_printf(m, "Graphics Interrupt enable: %08x\n",
932 seq_printf(m, "Graphics Interrupt identity: %08x\n",
934 seq_printf(m, "Graphics Interrupt mask: %08x\n",
937 for_each_ring(ring, dev_priv, i) {
938 if (INTEL_INFO(dev)->gen >= 6) {
940 "Graphics Interrupt mask (%s): %08x\n",
941 ring->name, I915_READ_IMR(ring));
943 i915_ring_seqno_info(m, ring);
945 intel_runtime_pm_put(dev_priv);
946 mutex_unlock(&dev->struct_mutex);
951 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
953 struct drm_info_node *node = m->private;
954 struct drm_device *dev = node->minor->dev;
955 struct drm_i915_private *dev_priv = dev->dev_private;
958 ret = mutex_lock_interruptible(&dev->struct_mutex);
962 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
963 for (i = 0; i < dev_priv->num_fence_regs; i++) {
964 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
966 seq_printf(m, "Fence %d, pin count = %d, object = ",
967 i, dev_priv->fence_regs[i].pin_count);
969 seq_puts(m, "unused");
971 describe_obj(m, obj);
975 mutex_unlock(&dev->struct_mutex);
979 static int i915_hws_info(struct seq_file *m, void *data)
981 struct drm_info_node *node = m->private;
982 struct drm_device *dev = node->minor->dev;
983 struct drm_i915_private *dev_priv = dev->dev_private;
984 struct intel_engine_cs *ring;
988 ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
989 hws = ring->status_page.page_addr;
993 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
994 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
996 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
1002 i915_error_state_write(struct file *filp,
1003 const char __user *ubuf,
1007 struct i915_error_state_file_priv *error_priv = filp->private_data;
1008 struct drm_device *dev = error_priv->dev;
1011 DRM_DEBUG_DRIVER("Resetting error state\n");
1013 ret = mutex_lock_interruptible(&dev->struct_mutex);
1017 i915_destroy_error_state(dev);
1018 mutex_unlock(&dev->struct_mutex);
1023 static int i915_error_state_open(struct inode *inode, struct file *file)
1025 struct drm_device *dev = inode->i_private;
1026 struct i915_error_state_file_priv *error_priv;
1028 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
1032 error_priv->dev = dev;
1034 i915_error_state_get(dev, error_priv);
1036 file->private_data = error_priv;
1041 static int i915_error_state_release(struct inode *inode, struct file *file)
1043 struct i915_error_state_file_priv *error_priv = file->private_data;
1045 i915_error_state_put(error_priv);
1051 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1052 size_t count, loff_t *pos)
1054 struct i915_error_state_file_priv *error_priv = file->private_data;
1055 struct drm_i915_error_state_buf error_str;
1057 ssize_t ret_count = 0;
1060 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
1064 ret = i915_error_state_to_str(&error_str, error_priv);
1068 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1075 *pos = error_str.start + ret_count;
1077 i915_error_state_buf_release(&error_str);
1078 return ret ?: ret_count;
1081 static const struct file_operations i915_error_state_fops = {
1082 .owner = THIS_MODULE,
1083 .open = i915_error_state_open,
1084 .read = i915_error_state_read,
1085 .write = i915_error_state_write,
1086 .llseek = default_llseek,
1087 .release = i915_error_state_release,
1091 i915_next_seqno_get(void *data, u64 *val)
1093 struct drm_device *dev = data;
1094 struct drm_i915_private *dev_priv = dev->dev_private;
1097 ret = mutex_lock_interruptible(&dev->struct_mutex);
1101 *val = dev_priv->next_seqno;
1102 mutex_unlock(&dev->struct_mutex);
1108 i915_next_seqno_set(void *data, u64 val)
1110 struct drm_device *dev = data;
1113 ret = mutex_lock_interruptible(&dev->struct_mutex);
1117 ret = i915_gem_set_seqno(dev, val);
1118 mutex_unlock(&dev->struct_mutex);
1123 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1124 i915_next_seqno_get, i915_next_seqno_set,
1127 static int i915_frequency_info(struct seq_file *m, void *unused)
1129 struct drm_info_node *node = m->private;
1130 struct drm_device *dev = node->minor->dev;
1131 struct drm_i915_private *dev_priv = dev->dev_private;
1134 intel_runtime_pm_get(dev_priv);
1136 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1139 u16 rgvswctl = I915_READ16(MEMSWCTL);
1140 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1142 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1143 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1144 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1146 seq_printf(m, "Current P-state: %d\n",
1147 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1148 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1151 mutex_lock(&dev_priv->rps.hw_lock);
1152 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1153 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1154 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1156 seq_printf(m, "actual GPU freq: %d MHz\n",
1157 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1159 seq_printf(m, "current GPU freq: %d MHz\n",
1160 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1162 seq_printf(m, "max GPU freq: %d MHz\n",
1163 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1165 seq_printf(m, "min GPU freq: %d MHz\n",
1166 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1168 seq_printf(m, "idle GPU freq: %d MHz\n",
1169 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1172 "efficient (RPe) frequency: %d MHz\n",
1173 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1174 mutex_unlock(&dev_priv->rps.hw_lock);
1175 } else if (INTEL_INFO(dev)->gen >= 6) {
1176 u32 rp_state_limits;
1179 u32 rpmodectl, rpinclimit, rpdeclimit;
1180 u32 rpstat, cagf, reqf;
1181 u32 rpupei, rpcurup, rpprevup;
1182 u32 rpdownei, rpcurdown, rpprevdown;
1183 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1186 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1187 if (IS_BROXTON(dev)) {
1188 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1189 gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1191 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1192 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1195 /* RPSTAT1 is in the GT power well */
1196 ret = mutex_lock_interruptible(&dev->struct_mutex);
1200 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1202 reqf = I915_READ(GEN6_RPNSWREQ);
1206 reqf &= ~GEN6_TURBO_DISABLE;
1207 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1212 reqf = intel_gpu_freq(dev_priv, reqf);
1214 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1215 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1216 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1218 rpstat = I915_READ(GEN6_RPSTAT1);
1219 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1220 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1221 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1222 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1223 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1224 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
1226 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1227 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1228 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1230 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1231 cagf = intel_gpu_freq(dev_priv, cagf);
1233 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1234 mutex_unlock(&dev->struct_mutex);
1236 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1237 pm_ier = I915_READ(GEN6_PMIER);
1238 pm_imr = I915_READ(GEN6_PMIMR);
1239 pm_isr = I915_READ(GEN6_PMISR);
1240 pm_iir = I915_READ(GEN6_PMIIR);
1241 pm_mask = I915_READ(GEN6_PMINTRMSK);
1243 pm_ier = I915_READ(GEN8_GT_IER(2));
1244 pm_imr = I915_READ(GEN8_GT_IMR(2));
1245 pm_isr = I915_READ(GEN8_GT_ISR(2));
1246 pm_iir = I915_READ(GEN8_GT_IIR(2));
1247 pm_mask = I915_READ(GEN6_PMINTRMSK);
1249 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1250 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1251 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1252 seq_printf(m, "Render p-state ratio: %d\n",
1253 (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
1254 seq_printf(m, "Render p-state VID: %d\n",
1255 gt_perf_status & 0xff);
1256 seq_printf(m, "Render p-state limit: %d\n",
1257 rp_state_limits & 0xff);
1258 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1259 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1260 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1261 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1262 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1263 seq_printf(m, "CAGF: %dMHz\n", cagf);
1264 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1265 GEN6_CURICONT_MASK);
1266 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1267 GEN6_CURBSYTAVG_MASK);
1268 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1269 GEN6_CURBSYTAVG_MASK);
1270 seq_printf(m, "Up threshold: %d%%\n",
1271 dev_priv->rps.up_threshold);
1273 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1275 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1276 GEN6_CURBSYTAVG_MASK);
1277 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1278 GEN6_CURBSYTAVG_MASK);
1279 seq_printf(m, "Down threshold: %d%%\n",
1280 dev_priv->rps.down_threshold);
1282 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 :
1283 rp_state_cap >> 16) & 0xff;
1284 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1285 GEN9_FREQ_SCALER : 1);
1286 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1287 intel_gpu_freq(dev_priv, max_freq));
1289 max_freq = (rp_state_cap & 0xff00) >> 8;
1290 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1291 GEN9_FREQ_SCALER : 1);
1292 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1293 intel_gpu_freq(dev_priv, max_freq));
1295 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 :
1296 rp_state_cap >> 0) & 0xff;
1297 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1298 GEN9_FREQ_SCALER : 1);
1299 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1300 intel_gpu_freq(dev_priv, max_freq));
1301 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1302 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1304 seq_printf(m, "Current freq: %d MHz\n",
1305 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1306 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1307 seq_printf(m, "Idle freq: %d MHz\n",
1308 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1309 seq_printf(m, "Min freq: %d MHz\n",
1310 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1311 seq_printf(m, "Max freq: %d MHz\n",
1312 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1314 "efficient (RPe) frequency: %d MHz\n",
1315 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1317 seq_puts(m, "no P-state info available\n");
1320 seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
1321 seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1322 seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1325 intel_runtime_pm_put(dev_priv);
1329 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1331 struct drm_info_node *node = m->private;
1332 struct drm_device *dev = node->minor->dev;
1333 struct drm_i915_private *dev_priv = dev->dev_private;
1334 struct intel_engine_cs *ring;
1335 u64 acthd[I915_NUM_RINGS];
1336 u32 seqno[I915_NUM_RINGS];
1337 u32 instdone[I915_NUM_INSTDONE_REG];
1340 if (!i915.enable_hangcheck) {
1341 seq_printf(m, "Hangcheck disabled\n");
1345 intel_runtime_pm_get(dev_priv);
1347 for_each_ring(ring, dev_priv, i) {
1348 seqno[i] = ring->get_seqno(ring, false);
1349 acthd[i] = intel_ring_get_active_head(ring);
1352 i915_get_extra_instdone(dev, instdone);
1354 intel_runtime_pm_put(dev_priv);
1356 if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1357 seq_printf(m, "Hangcheck active, fires in %dms\n",
1358 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1361 seq_printf(m, "Hangcheck inactive\n");
1363 for_each_ring(ring, dev_priv, i) {
1364 seq_printf(m, "%s:\n", ring->name);
1365 seq_printf(m, "\tseqno = %x [current %x]\n",
1366 ring->hangcheck.seqno, seqno[i]);
1367 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1368 (long long)ring->hangcheck.acthd,
1369 (long long)acthd[i]);
1370 seq_printf(m, "\tscore = %d\n", ring->hangcheck.score);
1371 seq_printf(m, "\taction = %d\n", ring->hangcheck.action);
1373 if (ring->id == RCS) {
1374 seq_puts(m, "\tinstdone read =");
1376 for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1377 seq_printf(m, " 0x%08x", instdone[j]);
1379 seq_puts(m, "\n\tinstdone accu =");
1381 for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1382 seq_printf(m, " 0x%08x",
1383 ring->hangcheck.instdone[j]);
1392 static int ironlake_drpc_info(struct seq_file *m)
1394 struct drm_info_node *node = m->private;
1395 struct drm_device *dev = node->minor->dev;
1396 struct drm_i915_private *dev_priv = dev->dev_private;
1397 u32 rgvmodectl, rstdbyctl;
1401 ret = mutex_lock_interruptible(&dev->struct_mutex);
1404 intel_runtime_pm_get(dev_priv);
1406 rgvmodectl = I915_READ(MEMMODECTL);
1407 rstdbyctl = I915_READ(RSTDBYCTL);
1408 crstandvid = I915_READ16(CRSTANDVID);
1410 intel_runtime_pm_put(dev_priv);
1411 mutex_unlock(&dev->struct_mutex);
1413 seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1414 seq_printf(m, "Boost freq: %d\n",
1415 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1416 MEMMODE_BOOST_FREQ_SHIFT);
1417 seq_printf(m, "HW control enabled: %s\n",
1418 yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1419 seq_printf(m, "SW control enabled: %s\n",
1420 yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1421 seq_printf(m, "Gated voltage change: %s\n",
1422 yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1423 seq_printf(m, "Starting frequency: P%d\n",
1424 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1425 seq_printf(m, "Max P-state: P%d\n",
1426 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1427 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1428 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1429 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1430 seq_printf(m, "Render standby enabled: %s\n",
1431 yesno(!(rstdbyctl & RCX_SW_EXIT)));
1432 seq_puts(m, "Current RS state: ");
1433 switch (rstdbyctl & RSX_STATUS_MASK) {
1435 seq_puts(m, "on\n");
1437 case RSX_STATUS_RC1:
1438 seq_puts(m, "RC1\n");
1440 case RSX_STATUS_RC1E:
1441 seq_puts(m, "RC1E\n");
1443 case RSX_STATUS_RS1:
1444 seq_puts(m, "RS1\n");
1446 case RSX_STATUS_RS2:
1447 seq_puts(m, "RS2 (RC6)\n");
1449 case RSX_STATUS_RS3:
1450 seq_puts(m, "RC3 (RC6+)\n");
1453 seq_puts(m, "unknown\n");
1460 static int i915_forcewake_domains(struct seq_file *m, void *data)
1462 struct drm_info_node *node = m->private;
1463 struct drm_device *dev = node->minor->dev;
1464 struct drm_i915_private *dev_priv = dev->dev_private;
1465 struct intel_uncore_forcewake_domain *fw_domain;
1468 spin_lock_irq(&dev_priv->uncore.lock);
1469 for_each_fw_domain(fw_domain, dev_priv, i) {
1470 seq_printf(m, "%s.wake_count = %u\n",
1471 intel_uncore_forcewake_domain_to_str(i),
1472 fw_domain->wake_count);
1474 spin_unlock_irq(&dev_priv->uncore.lock);
1479 static int vlv_drpc_info(struct seq_file *m)
1481 struct drm_info_node *node = m->private;
1482 struct drm_device *dev = node->minor->dev;
1483 struct drm_i915_private *dev_priv = dev->dev_private;
1484 u32 rpmodectl1, rcctl1, pw_status;
1486 intel_runtime_pm_get(dev_priv);
1488 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1489 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1490 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1492 intel_runtime_pm_put(dev_priv);
1494 seq_printf(m, "Video Turbo Mode: %s\n",
1495 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1496 seq_printf(m, "Turbo enabled: %s\n",
1497 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1498 seq_printf(m, "HW control enabled: %s\n",
1499 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1500 seq_printf(m, "SW control enabled: %s\n",
1501 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1502 GEN6_RP_MEDIA_SW_MODE));
1503 seq_printf(m, "RC6 Enabled: %s\n",
1504 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1505 GEN6_RC_CTL_EI_MODE(1))));
1506 seq_printf(m, "Render Power Well: %s\n",
1507 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1508 seq_printf(m, "Media Power Well: %s\n",
1509 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1511 seq_printf(m, "Render RC6 residency since boot: %u\n",
1512 I915_READ(VLV_GT_RENDER_RC6));
1513 seq_printf(m, "Media RC6 residency since boot: %u\n",
1514 I915_READ(VLV_GT_MEDIA_RC6));
1516 return i915_forcewake_domains(m, NULL);
1519 static int gen6_drpc_info(struct seq_file *m)
1521 struct drm_info_node *node = m->private;
1522 struct drm_device *dev = node->minor->dev;
1523 struct drm_i915_private *dev_priv = dev->dev_private;
1524 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1525 unsigned forcewake_count;
1528 ret = mutex_lock_interruptible(&dev->struct_mutex);
1531 intel_runtime_pm_get(dev_priv);
1533 spin_lock_irq(&dev_priv->uncore.lock);
1534 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1535 spin_unlock_irq(&dev_priv->uncore.lock);
1537 if (forcewake_count) {
1538 seq_puts(m, "RC information inaccurate because somebody "
1539 "holds a forcewake reference \n");
1541 /* NB: we cannot use forcewake, else we read the wrong values */
1542 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1544 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1547 gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1548 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1550 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1551 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1552 mutex_unlock(&dev->struct_mutex);
1553 mutex_lock(&dev_priv->rps.hw_lock);
1554 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1555 mutex_unlock(&dev_priv->rps.hw_lock);
1557 intel_runtime_pm_put(dev_priv);
1559 seq_printf(m, "Video Turbo Mode: %s\n",
1560 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1561 seq_printf(m, "HW control enabled: %s\n",
1562 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1563 seq_printf(m, "SW control enabled: %s\n",
1564 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1565 GEN6_RP_MEDIA_SW_MODE));
1566 seq_printf(m, "RC1e Enabled: %s\n",
1567 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1568 seq_printf(m, "RC6 Enabled: %s\n",
1569 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1570 seq_printf(m, "Deep RC6 Enabled: %s\n",
1571 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1572 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1573 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1574 seq_puts(m, "Current RC state: ");
1575 switch (gt_core_status & GEN6_RCn_MASK) {
1577 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1578 seq_puts(m, "Core Power Down\n");
1580 seq_puts(m, "on\n");
1583 seq_puts(m, "RC3\n");
1586 seq_puts(m, "RC6\n");
1589 seq_puts(m, "RC7\n");
1592 seq_puts(m, "Unknown\n");
1596 seq_printf(m, "Core Power Down: %s\n",
1597 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1599 /* Not exactly sure what this is */
1600 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1601 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1602 seq_printf(m, "RC6 residency since boot: %u\n",
1603 I915_READ(GEN6_GT_GFX_RC6));
1604 seq_printf(m, "RC6+ residency since boot: %u\n",
1605 I915_READ(GEN6_GT_GFX_RC6p));
1606 seq_printf(m, "RC6++ residency since boot: %u\n",
1607 I915_READ(GEN6_GT_GFX_RC6pp));
1609 seq_printf(m, "RC6 voltage: %dmV\n",
1610 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1611 seq_printf(m, "RC6+ voltage: %dmV\n",
1612 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1613 seq_printf(m, "RC6++ voltage: %dmV\n",
1614 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1618 static int i915_drpc_info(struct seq_file *m, void *unused)
1620 struct drm_info_node *node = m->private;
1621 struct drm_device *dev = node->minor->dev;
1623 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
1624 return vlv_drpc_info(m);
1625 else if (INTEL_INFO(dev)->gen >= 6)
1626 return gen6_drpc_info(m);
1628 return ironlake_drpc_info(m);
1631 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1633 struct drm_info_node *node = m->private;
1634 struct drm_device *dev = node->minor->dev;
1635 struct drm_i915_private *dev_priv = dev->dev_private;
1637 seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1638 dev_priv->fb_tracking.busy_bits);
1640 seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1641 dev_priv->fb_tracking.flip_bits);
1646 static int i915_fbc_status(struct seq_file *m, void *unused)
1648 struct drm_info_node *node = m->private;
1649 struct drm_device *dev = node->minor->dev;
1650 struct drm_i915_private *dev_priv = dev->dev_private;
1652 if (!HAS_FBC(dev)) {
1653 seq_puts(m, "FBC unsupported on this chipset\n");
1657 intel_runtime_pm_get(dev_priv);
1658 mutex_lock(&dev_priv->fbc.lock);
1660 if (intel_fbc_is_active(dev_priv))
1661 seq_puts(m, "FBC enabled\n");
1663 seq_printf(m, "FBC disabled: %s\n",
1664 dev_priv->fbc.no_fbc_reason);
1666 if (INTEL_INFO(dev_priv)->gen >= 7)
1667 seq_printf(m, "Compressing: %s\n",
1668 yesno(I915_READ(FBC_STATUS2) &
1669 FBC_COMPRESSION_MASK));
1671 mutex_unlock(&dev_priv->fbc.lock);
1672 intel_runtime_pm_put(dev_priv);
1677 static int i915_fbc_fc_get(void *data, u64 *val)
1679 struct drm_device *dev = data;
1680 struct drm_i915_private *dev_priv = dev->dev_private;
1682 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1685 *val = dev_priv->fbc.false_color;
1690 static int i915_fbc_fc_set(void *data, u64 val)
1692 struct drm_device *dev = data;
1693 struct drm_i915_private *dev_priv = dev->dev_private;
1696 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1699 mutex_lock(&dev_priv->fbc.lock);
1701 reg = I915_READ(ILK_DPFC_CONTROL);
1702 dev_priv->fbc.false_color = val;
1704 I915_WRITE(ILK_DPFC_CONTROL, val ?
1705 (reg | FBC_CTL_FALSE_COLOR) :
1706 (reg & ~FBC_CTL_FALSE_COLOR));
1708 mutex_unlock(&dev_priv->fbc.lock);
1712 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1713 i915_fbc_fc_get, i915_fbc_fc_set,
1716 static int i915_ips_status(struct seq_file *m, void *unused)
1718 struct drm_info_node *node = m->private;
1719 struct drm_device *dev = node->minor->dev;
1720 struct drm_i915_private *dev_priv = dev->dev_private;
1722 if (!HAS_IPS(dev)) {
1723 seq_puts(m, "not supported\n");
1727 intel_runtime_pm_get(dev_priv);
1729 seq_printf(m, "Enabled by kernel parameter: %s\n",
1730 yesno(i915.enable_ips));
1732 if (INTEL_INFO(dev)->gen >= 8) {
1733 seq_puts(m, "Currently: unknown\n");
1735 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1736 seq_puts(m, "Currently: enabled\n");
1738 seq_puts(m, "Currently: disabled\n");
1741 intel_runtime_pm_put(dev_priv);
1746 static int i915_sr_status(struct seq_file *m, void *unused)
1748 struct drm_info_node *node = m->private;
1749 struct drm_device *dev = node->minor->dev;
1750 struct drm_i915_private *dev_priv = dev->dev_private;
1751 bool sr_enabled = false;
1753 intel_runtime_pm_get(dev_priv);
1755 if (HAS_PCH_SPLIT(dev))
1756 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1757 else if (IS_CRESTLINE(dev) || IS_G4X(dev) ||
1758 IS_I945G(dev) || IS_I945GM(dev))
1759 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1760 else if (IS_I915GM(dev))
1761 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1762 else if (IS_PINEVIEW(dev))
1763 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1764 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
1765 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1767 intel_runtime_pm_put(dev_priv);
1769 seq_printf(m, "self-refresh: %s\n",
1770 sr_enabled ? "enabled" : "disabled");
1775 static int i915_emon_status(struct seq_file *m, void *unused)
1777 struct drm_info_node *node = m->private;
1778 struct drm_device *dev = node->minor->dev;
1779 struct drm_i915_private *dev_priv = dev->dev_private;
1780 unsigned long temp, chipset, gfx;
1786 ret = mutex_lock_interruptible(&dev->struct_mutex);
1790 temp = i915_mch_val(dev_priv);
1791 chipset = i915_chipset_val(dev_priv);
1792 gfx = i915_gfx_val(dev_priv);
1793 mutex_unlock(&dev->struct_mutex);
1795 seq_printf(m, "GMCH temp: %ld\n", temp);
1796 seq_printf(m, "Chipset power: %ld\n", chipset);
1797 seq_printf(m, "GFX power: %ld\n", gfx);
1798 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1803 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1805 struct drm_info_node *node = m->private;
1806 struct drm_device *dev = node->minor->dev;
1807 struct drm_i915_private *dev_priv = dev->dev_private;
1809 int gpu_freq, ia_freq;
1810 unsigned int max_gpu_freq, min_gpu_freq;
1812 if (!HAS_CORE_RING_FREQ(dev)) {
1813 seq_puts(m, "unsupported on this chipset\n");
1817 intel_runtime_pm_get(dev_priv);
1819 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1821 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1825 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
1826 /* Convert GT frequency to 50 HZ units */
1828 dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1830 dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1832 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1833 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1836 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1838 for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1840 sandybridge_pcode_read(dev_priv,
1841 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1843 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1844 intel_gpu_freq(dev_priv, (gpu_freq *
1845 (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1846 GEN9_FREQ_SCALER : 1))),
1847 ((ia_freq >> 0) & 0xff) * 100,
1848 ((ia_freq >> 8) & 0xff) * 100);
1851 mutex_unlock(&dev_priv->rps.hw_lock);
1854 intel_runtime_pm_put(dev_priv);
1858 static int i915_opregion(struct seq_file *m, void *unused)
1860 struct drm_info_node *node = m->private;
1861 struct drm_device *dev = node->minor->dev;
1862 struct drm_i915_private *dev_priv = dev->dev_private;
1863 struct intel_opregion *opregion = &dev_priv->opregion;
1866 ret = mutex_lock_interruptible(&dev->struct_mutex);
1870 if (opregion->header)
1871 seq_write(m, opregion->header, OPREGION_SIZE);
1873 mutex_unlock(&dev->struct_mutex);
1879 static int i915_vbt(struct seq_file *m, void *unused)
1881 struct drm_info_node *node = m->private;
1882 struct drm_device *dev = node->minor->dev;
1883 struct drm_i915_private *dev_priv = dev->dev_private;
1884 struct intel_opregion *opregion = &dev_priv->opregion;
1887 seq_write(m, opregion->vbt, opregion->vbt_size);
1892 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1894 struct drm_info_node *node = m->private;
1895 struct drm_device *dev = node->minor->dev;
1896 struct intel_framebuffer *fbdev_fb = NULL;
1897 struct drm_framebuffer *drm_fb;
1899 #ifdef CONFIG_DRM_FBDEV_EMULATION
1900 if (to_i915(dev)->fbdev) {
1901 fbdev_fb = to_intel_framebuffer(to_i915(dev)->fbdev->helper.fb);
1903 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1904 fbdev_fb->base.width,
1905 fbdev_fb->base.height,
1906 fbdev_fb->base.depth,
1907 fbdev_fb->base.bits_per_pixel,
1908 fbdev_fb->base.modifier[0],
1909 atomic_read(&fbdev_fb->base.refcount.refcount));
1910 describe_obj(m, fbdev_fb->obj);
1915 mutex_lock(&dev->mode_config.fb_lock);
1916 drm_for_each_fb(drm_fb, dev) {
1917 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
1921 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1925 fb->base.bits_per_pixel,
1926 fb->base.modifier[0],
1927 atomic_read(&fb->base.refcount.refcount));
1928 describe_obj(m, fb->obj);
1931 mutex_unlock(&dev->mode_config.fb_lock);
1936 static void describe_ctx_ringbuf(struct seq_file *m,
1937 struct intel_ringbuffer *ringbuf)
1939 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1940 ringbuf->space, ringbuf->head, ringbuf->tail,
1941 ringbuf->last_retired_head);
1944 static int i915_context_status(struct seq_file *m, void *unused)
1946 struct drm_info_node *node = m->private;
1947 struct drm_device *dev = node->minor->dev;
1948 struct drm_i915_private *dev_priv = dev->dev_private;
1949 struct intel_engine_cs *ring;
1950 struct intel_context *ctx;
1953 ret = mutex_lock_interruptible(&dev->struct_mutex);
1957 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1958 if (!i915.enable_execlists &&
1959 ctx->legacy_hw_ctx.rcs_state == NULL)
1962 seq_puts(m, "HW context ");
1963 describe_ctx(m, ctx);
1964 if (ctx == dev_priv->kernel_context)
1965 seq_printf(m, "(kernel context) ");
1967 if (i915.enable_execlists) {
1969 for_each_ring(ring, dev_priv, i) {
1970 struct drm_i915_gem_object *ctx_obj =
1971 ctx->engine[i].state;
1972 struct intel_ringbuffer *ringbuf =
1973 ctx->engine[i].ringbuf;
1975 seq_printf(m, "%s: ", ring->name);
1977 describe_obj(m, ctx_obj);
1979 describe_ctx_ringbuf(m, ringbuf);
1983 describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1989 mutex_unlock(&dev->struct_mutex);
1994 static void i915_dump_lrc_obj(struct seq_file *m,
1995 struct intel_context *ctx,
1996 struct intel_engine_cs *ring)
1999 uint32_t *reg_state;
2001 struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state;
2002 unsigned long ggtt_offset = 0;
2004 if (ctx_obj == NULL) {
2005 seq_printf(m, "Context on %s with no gem object\n",
2010 seq_printf(m, "CONTEXT: %s %u\n", ring->name,
2011 intel_execlists_ctx_id(ctx, ring));
2013 if (!i915_gem_obj_ggtt_bound(ctx_obj))
2014 seq_puts(m, "\tNot bound in GGTT\n");
2016 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
2018 if (i915_gem_object_get_pages(ctx_obj)) {
2019 seq_puts(m, "\tFailed to get pages for context object\n");
2023 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
2024 if (!WARN_ON(page == NULL)) {
2025 reg_state = kmap_atomic(page);
2027 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2028 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2029 ggtt_offset + 4096 + (j * 4),
2030 reg_state[j], reg_state[j + 1],
2031 reg_state[j + 2], reg_state[j + 3]);
2033 kunmap_atomic(reg_state);
2039 static int i915_dump_lrc(struct seq_file *m, void *unused)
2041 struct drm_info_node *node = (struct drm_info_node *) m->private;
2042 struct drm_device *dev = node->minor->dev;
2043 struct drm_i915_private *dev_priv = dev->dev_private;
2044 struct intel_engine_cs *ring;
2045 struct intel_context *ctx;
2048 if (!i915.enable_execlists) {
2049 seq_printf(m, "Logical Ring Contexts are disabled\n");
2053 ret = mutex_lock_interruptible(&dev->struct_mutex);
2057 list_for_each_entry(ctx, &dev_priv->context_list, link)
2058 if (ctx != dev_priv->kernel_context)
2059 for_each_ring(ring, dev_priv, i)
2060 i915_dump_lrc_obj(m, ctx, ring);
2062 mutex_unlock(&dev->struct_mutex);
2067 static int i915_execlists(struct seq_file *m, void *data)
2069 struct drm_info_node *node = (struct drm_info_node *)m->private;
2070 struct drm_device *dev = node->minor->dev;
2071 struct drm_i915_private *dev_priv = dev->dev_private;
2072 struct intel_engine_cs *ring;
2078 struct list_head *cursor;
2082 if (!i915.enable_execlists) {
2083 seq_puts(m, "Logical Ring Contexts are disabled\n");
2087 ret = mutex_lock_interruptible(&dev->struct_mutex);
2091 intel_runtime_pm_get(dev_priv);
2093 for_each_ring(ring, dev_priv, ring_id) {
2094 struct drm_i915_gem_request *head_req = NULL;
2096 unsigned long flags;
2098 seq_printf(m, "%s\n", ring->name);
2100 status = I915_READ(RING_EXECLIST_STATUS_LO(ring));
2101 ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(ring));
2102 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2105 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
2106 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2108 read_pointer = ring->next_context_status_buffer;
2109 write_pointer = GEN8_CSB_WRITE_PTR(status_pointer);
2110 if (read_pointer > write_pointer)
2111 write_pointer += GEN8_CSB_ENTRIES;
2112 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2113 read_pointer, write_pointer);
2115 for (i = 0; i < GEN8_CSB_ENTRIES; i++) {
2116 status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(ring, i));
2117 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(ring, i));
2119 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2123 spin_lock_irqsave(&ring->execlist_lock, flags);
2124 list_for_each(cursor, &ring->execlist_queue)
2126 head_req = list_first_entry_or_null(&ring->execlist_queue,
2127 struct drm_i915_gem_request, execlist_link);
2128 spin_unlock_irqrestore(&ring->execlist_lock, flags);
2130 seq_printf(m, "\t%d requests in queue\n", count);
2132 seq_printf(m, "\tHead request id: %u\n",
2133 intel_execlists_ctx_id(head_req->ctx, ring));
2134 seq_printf(m, "\tHead request tail: %u\n",
2141 intel_runtime_pm_put(dev_priv);
2142 mutex_unlock(&dev->struct_mutex);
2147 static const char *swizzle_string(unsigned swizzle)
2150 case I915_BIT_6_SWIZZLE_NONE:
2152 case I915_BIT_6_SWIZZLE_9:
2154 case I915_BIT_6_SWIZZLE_9_10:
2155 return "bit9/bit10";
2156 case I915_BIT_6_SWIZZLE_9_11:
2157 return "bit9/bit11";
2158 case I915_BIT_6_SWIZZLE_9_10_11:
2159 return "bit9/bit10/bit11";
2160 case I915_BIT_6_SWIZZLE_9_17:
2161 return "bit9/bit17";
2162 case I915_BIT_6_SWIZZLE_9_10_17:
2163 return "bit9/bit10/bit17";
2164 case I915_BIT_6_SWIZZLE_UNKNOWN:
2171 static int i915_swizzle_info(struct seq_file *m, void *data)
2173 struct drm_info_node *node = m->private;
2174 struct drm_device *dev = node->minor->dev;
2175 struct drm_i915_private *dev_priv = dev->dev_private;
2178 ret = mutex_lock_interruptible(&dev->struct_mutex);
2181 intel_runtime_pm_get(dev_priv);
2183 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2184 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2185 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2186 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2188 if (IS_GEN3(dev) || IS_GEN4(dev)) {
2189 seq_printf(m, "DDC = 0x%08x\n",
2191 seq_printf(m, "DDC2 = 0x%08x\n",
2193 seq_printf(m, "C0DRB3 = 0x%04x\n",
2194 I915_READ16(C0DRB3));
2195 seq_printf(m, "C1DRB3 = 0x%04x\n",
2196 I915_READ16(C1DRB3));
2197 } else if (INTEL_INFO(dev)->gen >= 6) {
2198 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2199 I915_READ(MAD_DIMM_C0));
2200 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2201 I915_READ(MAD_DIMM_C1));
2202 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2203 I915_READ(MAD_DIMM_C2));
2204 seq_printf(m, "TILECTL = 0x%08x\n",
2205 I915_READ(TILECTL));
2206 if (INTEL_INFO(dev)->gen >= 8)
2207 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2208 I915_READ(GAMTARBMODE));
2210 seq_printf(m, "ARB_MODE = 0x%08x\n",
2211 I915_READ(ARB_MODE));
2212 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2213 I915_READ(DISP_ARB_CTL));
2216 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2217 seq_puts(m, "L-shaped memory detected\n");
2219 intel_runtime_pm_put(dev_priv);
2220 mutex_unlock(&dev->struct_mutex);
2225 static int per_file_ctx(int id, void *ptr, void *data)
2227 struct intel_context *ctx = ptr;
2228 struct seq_file *m = data;
2229 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2232 seq_printf(m, " no ppgtt for context %d\n",
2237 if (i915_gem_context_is_default(ctx))
2238 seq_puts(m, " default context:\n");
2240 seq_printf(m, " context %d:\n", ctx->user_handle);
2241 ppgtt->debug_dump(ppgtt, m);
2246 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2248 struct drm_i915_private *dev_priv = dev->dev_private;
2249 struct intel_engine_cs *ring;
2250 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2256 for_each_ring(ring, dev_priv, unused) {
2257 seq_printf(m, "%s\n", ring->name);
2258 for (i = 0; i < 4; i++) {
2259 u64 pdp = I915_READ(GEN8_RING_PDP_UDW(ring, i));
2261 pdp |= I915_READ(GEN8_RING_PDP_LDW(ring, i));
2262 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2267 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2269 struct drm_i915_private *dev_priv = dev->dev_private;
2270 struct intel_engine_cs *ring;
2273 if (INTEL_INFO(dev)->gen == 6)
2274 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2276 for_each_ring(ring, dev_priv, i) {
2277 seq_printf(m, "%s\n", ring->name);
2278 if (INTEL_INFO(dev)->gen == 7)
2279 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
2280 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
2281 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
2282 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
2284 if (dev_priv->mm.aliasing_ppgtt) {
2285 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2287 seq_puts(m, "aliasing PPGTT:\n");
2288 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2290 ppgtt->debug_dump(ppgtt, m);
2293 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2296 static int i915_ppgtt_info(struct seq_file *m, void *data)
2298 struct drm_info_node *node = m->private;
2299 struct drm_device *dev = node->minor->dev;
2300 struct drm_i915_private *dev_priv = dev->dev_private;
2301 struct drm_file *file;
2303 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2306 intel_runtime_pm_get(dev_priv);
2308 if (INTEL_INFO(dev)->gen >= 8)
2309 gen8_ppgtt_info(m, dev);
2310 else if (INTEL_INFO(dev)->gen >= 6)
2311 gen6_ppgtt_info(m, dev);
2313 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2314 struct drm_i915_file_private *file_priv = file->driver_priv;
2315 struct task_struct *task;
2317 task = get_pid_task(file->pid, PIDTYPE_PID);
2322 seq_printf(m, "\nproc: %s\n", task->comm);
2323 put_task_struct(task);
2324 idr_for_each(&file_priv->context_idr, per_file_ctx,
2325 (void *)(unsigned long)m);
2329 intel_runtime_pm_put(dev_priv);
2330 mutex_unlock(&dev->struct_mutex);
2335 static int count_irq_waiters(struct drm_i915_private *i915)
2337 struct intel_engine_cs *ring;
2341 for_each_ring(ring, i915, i)
2342 count += ring->irq_refcount;
2347 static int i915_rps_boost_info(struct seq_file *m, void *data)
2349 struct drm_info_node *node = m->private;
2350 struct drm_device *dev = node->minor->dev;
2351 struct drm_i915_private *dev_priv = dev->dev_private;
2352 struct drm_file *file;
2354 seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2355 seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy);
2356 seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2357 seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2358 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2359 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2360 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2361 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2362 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2363 spin_lock(&dev_priv->rps.client_lock);
2364 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2365 struct drm_i915_file_private *file_priv = file->driver_priv;
2366 struct task_struct *task;
2369 task = pid_task(file->pid, PIDTYPE_PID);
2370 seq_printf(m, "%s [%d]: %d boosts%s\n",
2371 task ? task->comm : "<unknown>",
2372 task ? task->pid : -1,
2373 file_priv->rps.boosts,
2374 list_empty(&file_priv->rps.link) ? "" : ", active");
2377 seq_printf(m, "Semaphore boosts: %d%s\n",
2378 dev_priv->rps.semaphores.boosts,
2379 list_empty(&dev_priv->rps.semaphores.link) ? "" : ", active");
2380 seq_printf(m, "MMIO flip boosts: %d%s\n",
2381 dev_priv->rps.mmioflips.boosts,
2382 list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active");
2383 seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts);
2384 spin_unlock(&dev_priv->rps.client_lock);
2389 static int i915_llc(struct seq_file *m, void *data)
2391 struct drm_info_node *node = m->private;
2392 struct drm_device *dev = node->minor->dev;
2393 struct drm_i915_private *dev_priv = dev->dev_private;
2395 /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2396 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2397 seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2402 static int i915_guc_load_status_info(struct seq_file *m, void *data)
2404 struct drm_info_node *node = m->private;
2405 struct drm_i915_private *dev_priv = node->minor->dev->dev_private;
2406 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
2409 if (!HAS_GUC_UCODE(dev_priv->dev))
2412 seq_printf(m, "GuC firmware status:\n");
2413 seq_printf(m, "\tpath: %s\n",
2414 guc_fw->guc_fw_path);
2415 seq_printf(m, "\tfetch: %s\n",
2416 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
2417 seq_printf(m, "\tload: %s\n",
2418 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
2419 seq_printf(m, "\tversion wanted: %d.%d\n",
2420 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2421 seq_printf(m, "\tversion found: %d.%d\n",
2422 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
2423 seq_printf(m, "\theader: offset is %d; size = %d\n",
2424 guc_fw->header_offset, guc_fw->header_size);
2425 seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2426 guc_fw->ucode_offset, guc_fw->ucode_size);
2427 seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2428 guc_fw->rsa_offset, guc_fw->rsa_size);
2430 tmp = I915_READ(GUC_STATUS);
2432 seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2433 seq_printf(m, "\tBootrom status = 0x%x\n",
2434 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2435 seq_printf(m, "\tuKernel status = 0x%x\n",
2436 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2437 seq_printf(m, "\tMIA Core status = 0x%x\n",
2438 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2439 seq_puts(m, "\nScratch registers:\n");
2440 for (i = 0; i < 16; i++)
2441 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2446 static void i915_guc_client_info(struct seq_file *m,
2447 struct drm_i915_private *dev_priv,
2448 struct i915_guc_client *client)
2450 struct intel_engine_cs *ring;
2454 seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2455 client->priority, client->ctx_index, client->proc_desc_offset);
2456 seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2457 client->doorbell_id, client->doorbell_offset, client->cookie);
2458 seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2459 client->wq_size, client->wq_offset, client->wq_tail);
2461 seq_printf(m, "\tFailed to queue: %u\n", client->q_fail);
2462 seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2463 seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2465 for_each_ring(ring, dev_priv, i) {
2466 seq_printf(m, "\tSubmissions: %llu %s\n",
2467 client->submissions[ring->guc_id],
2469 tot += client->submissions[ring->guc_id];
2471 seq_printf(m, "\tTotal: %llu\n", tot);
2474 static int i915_guc_info(struct seq_file *m, void *data)
2476 struct drm_info_node *node = m->private;
2477 struct drm_device *dev = node->minor->dev;
2478 struct drm_i915_private *dev_priv = dev->dev_private;
2479 struct intel_guc guc;
2480 struct i915_guc_client client = {};
2481 struct intel_engine_cs *ring;
2482 enum intel_ring_id i;
2485 if (!HAS_GUC_SCHED(dev_priv->dev))
2488 if (mutex_lock_interruptible(&dev->struct_mutex))
2491 /* Take a local copy of the GuC data, so we can dump it at leisure */
2492 guc = dev_priv->guc;
2493 if (guc.execbuf_client)
2494 client = *guc.execbuf_client;
2496 mutex_unlock(&dev->struct_mutex);
2498 seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
2499 seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
2500 seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
2501 seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
2502 seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
2504 seq_printf(m, "\nGuC submissions:\n");
2505 for_each_ring(ring, dev_priv, i) {
2506 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",
2507 ring->name, guc.submissions[ring->guc_id],
2508 guc.last_seqno[ring->guc_id]);
2509 total += guc.submissions[ring->guc_id];
2511 seq_printf(m, "\t%s: %llu\n", "Total", total);
2513 seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
2514 i915_guc_client_info(m, dev_priv, &client);
2516 /* Add more as required ... */
2521 static int i915_guc_log_dump(struct seq_file *m, void *data)
2523 struct drm_info_node *node = m->private;
2524 struct drm_device *dev = node->minor->dev;
2525 struct drm_i915_private *dev_priv = dev->dev_private;
2526 struct drm_i915_gem_object *log_obj = dev_priv->guc.log_obj;
2533 for (pg = 0; pg < log_obj->base.size / PAGE_SIZE; pg++) {
2534 log = kmap_atomic(i915_gem_object_get_page(log_obj, pg));
2536 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2537 seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2538 *(log + i), *(log + i + 1),
2539 *(log + i + 2), *(log + i + 3));
2549 static int i915_edp_psr_status(struct seq_file *m, void *data)
2551 struct drm_info_node *node = m->private;
2552 struct drm_device *dev = node->minor->dev;
2553 struct drm_i915_private *dev_priv = dev->dev_private;
2557 bool enabled = false;
2559 if (!HAS_PSR(dev)) {
2560 seq_puts(m, "PSR not supported\n");
2564 intel_runtime_pm_get(dev_priv);
2566 mutex_lock(&dev_priv->psr.lock);
2567 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2568 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2569 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2570 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2571 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2572 dev_priv->psr.busy_frontbuffer_bits);
2573 seq_printf(m, "Re-enable work scheduled: %s\n",
2574 yesno(work_busy(&dev_priv->psr.work.work)));
2577 enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2579 for_each_pipe(dev_priv, pipe) {
2580 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2581 VLV_EDP_PSR_CURR_STATE_MASK;
2582 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2583 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2588 seq_printf(m, "Main link in standby mode: %s\n",
2589 yesno(dev_priv->psr.link_standby));
2591 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2594 for_each_pipe(dev_priv, pipe) {
2595 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2596 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2597 seq_printf(m, " pipe %c", pipe_name(pipe));
2602 * VLV/CHV PSR has no kind of performance counter
2603 * SKL+ Perf counter is reset to 0 everytime DC state is entered
2605 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2606 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
2607 EDP_PSR_PERF_CNT_MASK;
2609 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2611 mutex_unlock(&dev_priv->psr.lock);
2613 intel_runtime_pm_put(dev_priv);
2617 static int i915_sink_crc(struct seq_file *m, void *data)
2619 struct drm_info_node *node = m->private;
2620 struct drm_device *dev = node->minor->dev;
2621 struct intel_encoder *encoder;
2622 struct intel_connector *connector;
2623 struct intel_dp *intel_dp = NULL;
2627 drm_modeset_lock_all(dev);
2628 for_each_intel_connector(dev, connector) {
2630 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2633 if (!connector->base.encoder)
2636 encoder = to_intel_encoder(connector->base.encoder);
2637 if (encoder->type != INTEL_OUTPUT_EDP)
2640 intel_dp = enc_to_intel_dp(&encoder->base);
2642 ret = intel_dp_sink_crc(intel_dp, crc);
2646 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2647 crc[0], crc[1], crc[2],
2648 crc[3], crc[4], crc[5]);
2653 drm_modeset_unlock_all(dev);
2657 static int i915_energy_uJ(struct seq_file *m, void *data)
2659 struct drm_info_node *node = m->private;
2660 struct drm_device *dev = node->minor->dev;
2661 struct drm_i915_private *dev_priv = dev->dev_private;
2665 if (INTEL_INFO(dev)->gen < 6)
2668 intel_runtime_pm_get(dev_priv);
2670 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2671 power = (power & 0x1f00) >> 8;
2672 units = 1000000 / (1 << power); /* convert to uJ */
2673 power = I915_READ(MCH_SECP_NRG_STTS);
2676 intel_runtime_pm_put(dev_priv);
2678 seq_printf(m, "%llu", (long long unsigned)power);
2683 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2685 struct drm_info_node *node = m->private;
2686 struct drm_device *dev = node->minor->dev;
2687 struct drm_i915_private *dev_priv = dev->dev_private;
2689 if (!HAS_RUNTIME_PM(dev)) {
2690 seq_puts(m, "not supported\n");
2694 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
2695 seq_printf(m, "IRQs disabled: %s\n",
2696 yesno(!intel_irqs_enabled(dev_priv)));
2698 seq_printf(m, "Usage count: %d\n",
2699 atomic_read(&dev->dev->power.usage_count));
2701 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2707 static int i915_power_domain_info(struct seq_file *m, void *unused)
2709 struct drm_info_node *node = m->private;
2710 struct drm_device *dev = node->minor->dev;
2711 struct drm_i915_private *dev_priv = dev->dev_private;
2712 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2715 mutex_lock(&power_domains->lock);
2717 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2718 for (i = 0; i < power_domains->power_well_count; i++) {
2719 struct i915_power_well *power_well;
2720 enum intel_display_power_domain power_domain;
2722 power_well = &power_domains->power_wells[i];
2723 seq_printf(m, "%-25s %d\n", power_well->name,
2726 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2728 if (!(BIT(power_domain) & power_well->domains))
2731 seq_printf(m, " %-23s %d\n",
2732 intel_display_power_domain_str(power_domain),
2733 power_domains->domain_use_count[power_domain]);
2737 mutex_unlock(&power_domains->lock);
2742 static int i915_dmc_info(struct seq_file *m, void *unused)
2744 struct drm_info_node *node = m->private;
2745 struct drm_device *dev = node->minor->dev;
2746 struct drm_i915_private *dev_priv = dev->dev_private;
2747 struct intel_csr *csr;
2749 if (!HAS_CSR(dev)) {
2750 seq_puts(m, "not supported\n");
2754 csr = &dev_priv->csr;
2756 intel_runtime_pm_get(dev_priv);
2758 seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2759 seq_printf(m, "path: %s\n", csr->fw_path);
2761 if (!csr->dmc_payload)
2764 seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2765 CSR_VERSION_MINOR(csr->version));
2767 if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) {
2768 seq_printf(m, "DC3 -> DC5 count: %d\n",
2769 I915_READ(SKL_CSR_DC3_DC5_COUNT));
2770 seq_printf(m, "DC5 -> DC6 count: %d\n",
2771 I915_READ(SKL_CSR_DC5_DC6_COUNT));
2772 } else if (IS_BROXTON(dev) && csr->version >= CSR_VERSION(1, 4)) {
2773 seq_printf(m, "DC3 -> DC5 count: %d\n",
2774 I915_READ(BXT_CSR_DC3_DC5_COUNT));
2778 seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2779 seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2780 seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2782 intel_runtime_pm_put(dev_priv);
2787 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2788 struct drm_display_mode *mode)
2792 for (i = 0; i < tabs; i++)
2795 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2796 mode->base.id, mode->name,
2797 mode->vrefresh, mode->clock,
2798 mode->hdisplay, mode->hsync_start,
2799 mode->hsync_end, mode->htotal,
2800 mode->vdisplay, mode->vsync_start,
2801 mode->vsync_end, mode->vtotal,
2802 mode->type, mode->flags);
2805 static void intel_encoder_info(struct seq_file *m,
2806 struct intel_crtc *intel_crtc,
2807 struct intel_encoder *intel_encoder)
2809 struct drm_info_node *node = m->private;
2810 struct drm_device *dev = node->minor->dev;
2811 struct drm_crtc *crtc = &intel_crtc->base;
2812 struct intel_connector *intel_connector;
2813 struct drm_encoder *encoder;
2815 encoder = &intel_encoder->base;
2816 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2817 encoder->base.id, encoder->name);
2818 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2819 struct drm_connector *connector = &intel_connector->base;
2820 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2823 drm_get_connector_status_name(connector->status));
2824 if (connector->status == connector_status_connected) {
2825 struct drm_display_mode *mode = &crtc->mode;
2826 seq_printf(m, ", mode:\n");
2827 intel_seq_print_mode(m, 2, mode);
2834 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2836 struct drm_info_node *node = m->private;
2837 struct drm_device *dev = node->minor->dev;
2838 struct drm_crtc *crtc = &intel_crtc->base;
2839 struct intel_encoder *intel_encoder;
2840 struct drm_plane_state *plane_state = crtc->primary->state;
2841 struct drm_framebuffer *fb = plane_state->fb;
2844 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2845 fb->base.id, plane_state->src_x >> 16,
2846 plane_state->src_y >> 16, fb->width, fb->height);
2848 seq_puts(m, "\tprimary plane disabled\n");
2849 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2850 intel_encoder_info(m, intel_crtc, intel_encoder);
2853 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2855 struct drm_display_mode *mode = panel->fixed_mode;
2857 seq_printf(m, "\tfixed mode:\n");
2858 intel_seq_print_mode(m, 2, mode);
2861 static void intel_dp_info(struct seq_file *m,
2862 struct intel_connector *intel_connector)
2864 struct intel_encoder *intel_encoder = intel_connector->encoder;
2865 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2867 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2868 seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2869 if (intel_encoder->type == INTEL_OUTPUT_EDP)
2870 intel_panel_info(m, &intel_connector->panel);
2873 static void intel_dp_mst_info(struct seq_file *m,
2874 struct intel_connector *intel_connector)
2876 struct intel_encoder *intel_encoder = intel_connector->encoder;
2877 struct intel_dp_mst_encoder *intel_mst =
2878 enc_to_mst(&intel_encoder->base);
2879 struct intel_digital_port *intel_dig_port = intel_mst->primary;
2880 struct intel_dp *intel_dp = &intel_dig_port->dp;
2881 bool has_audio = drm_dp_mst_port_has_audio(&intel_dp->mst_mgr,
2882 intel_connector->port);
2884 seq_printf(m, "\taudio support: %s\n", yesno(has_audio));
2887 static void intel_hdmi_info(struct seq_file *m,
2888 struct intel_connector *intel_connector)
2890 struct intel_encoder *intel_encoder = intel_connector->encoder;
2891 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2893 seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
2896 static void intel_lvds_info(struct seq_file *m,
2897 struct intel_connector *intel_connector)
2899 intel_panel_info(m, &intel_connector->panel);
2902 static void intel_connector_info(struct seq_file *m,
2903 struct drm_connector *connector)
2905 struct intel_connector *intel_connector = to_intel_connector(connector);
2906 struct intel_encoder *intel_encoder = intel_connector->encoder;
2907 struct drm_display_mode *mode;
2909 seq_printf(m, "connector %d: type %s, status: %s\n",
2910 connector->base.id, connector->name,
2911 drm_get_connector_status_name(connector->status));
2912 if (connector->status == connector_status_connected) {
2913 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2914 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2915 connector->display_info.width_mm,
2916 connector->display_info.height_mm);
2917 seq_printf(m, "\tsubpixel order: %s\n",
2918 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2919 seq_printf(m, "\tCEA rev: %d\n",
2920 connector->display_info.cea_rev);
2922 if (intel_encoder) {
2923 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2924 intel_encoder->type == INTEL_OUTPUT_EDP)
2925 intel_dp_info(m, intel_connector);
2926 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2927 intel_hdmi_info(m, intel_connector);
2928 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2929 intel_lvds_info(m, intel_connector);
2930 else if (intel_encoder->type == INTEL_OUTPUT_DP_MST)
2931 intel_dp_mst_info(m, intel_connector);
2934 seq_printf(m, "\tmodes:\n");
2935 list_for_each_entry(mode, &connector->modes, head)
2936 intel_seq_print_mode(m, 2, mode);
2939 static bool cursor_active(struct drm_device *dev, int pipe)
2941 struct drm_i915_private *dev_priv = dev->dev_private;
2944 if (IS_845G(dev) || IS_I865G(dev))
2945 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
2947 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2952 static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2954 struct drm_i915_private *dev_priv = dev->dev_private;
2957 pos = I915_READ(CURPOS(pipe));
2959 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2960 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2963 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2964 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2967 return cursor_active(dev, pipe);
2970 static const char *plane_type(enum drm_plane_type type)
2973 case DRM_PLANE_TYPE_OVERLAY:
2975 case DRM_PLANE_TYPE_PRIMARY:
2977 case DRM_PLANE_TYPE_CURSOR:
2980 * Deliberately omitting default: to generate compiler warnings
2981 * when a new drm_plane_type gets added.
2988 static const char *plane_rotation(unsigned int rotation)
2990 static char buf[48];
2992 * According to doc only one DRM_ROTATE_ is allowed but this
2993 * will print them all to visualize if the values are misused
2995 snprintf(buf, sizeof(buf),
2996 "%s%s%s%s%s%s(0x%08x)",
2997 (rotation & BIT(DRM_ROTATE_0)) ? "0 " : "",
2998 (rotation & BIT(DRM_ROTATE_90)) ? "90 " : "",
2999 (rotation & BIT(DRM_ROTATE_180)) ? "180 " : "",
3000 (rotation & BIT(DRM_ROTATE_270)) ? "270 " : "",
3001 (rotation & BIT(DRM_REFLECT_X)) ? "FLIPX " : "",
3002 (rotation & BIT(DRM_REFLECT_Y)) ? "FLIPY " : "",
3008 static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3010 struct drm_info_node *node = m->private;
3011 struct drm_device *dev = node->minor->dev;
3012 struct intel_plane *intel_plane;
3014 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3015 struct drm_plane_state *state;
3016 struct drm_plane *plane = &intel_plane->base;
3018 if (!plane->state) {
3019 seq_puts(m, "plane->state is NULL!\n");
3023 state = plane->state;
3025 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3027 plane_type(intel_plane->base.type),
3028 state->crtc_x, state->crtc_y,
3029 state->crtc_w, state->crtc_h,
3030 (state->src_x >> 16),
3031 ((state->src_x & 0xffff) * 15625) >> 10,
3032 (state->src_y >> 16),
3033 ((state->src_y & 0xffff) * 15625) >> 10,
3034 (state->src_w >> 16),
3035 ((state->src_w & 0xffff) * 15625) >> 10,
3036 (state->src_h >> 16),
3037 ((state->src_h & 0xffff) * 15625) >> 10,
3038 state->fb ? drm_get_format_name(state->fb->pixel_format) : "N/A",
3039 plane_rotation(state->rotation));
3043 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3045 struct intel_crtc_state *pipe_config;
3046 int num_scalers = intel_crtc->num_scalers;
3049 pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3051 /* Not all platformas have a scaler */
3053 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3055 pipe_config->scaler_state.scaler_users,
3056 pipe_config->scaler_state.scaler_id);
3058 for (i = 0; i < SKL_NUM_SCALERS; i++) {
3059 struct intel_scaler *sc =
3060 &pipe_config->scaler_state.scalers[i];
3062 seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3063 i, yesno(sc->in_use), sc->mode);
3067 seq_puts(m, "\tNo scalers available on this platform\n");
3071 static int i915_display_info(struct seq_file *m, void *unused)
3073 struct drm_info_node *node = m->private;
3074 struct drm_device *dev = node->minor->dev;
3075 struct drm_i915_private *dev_priv = dev->dev_private;
3076 struct intel_crtc *crtc;
3077 struct drm_connector *connector;
3079 intel_runtime_pm_get(dev_priv);
3080 drm_modeset_lock_all(dev);
3081 seq_printf(m, "CRTC info\n");
3082 seq_printf(m, "---------\n");
3083 for_each_intel_crtc(dev, crtc) {
3085 struct intel_crtc_state *pipe_config;
3088 pipe_config = to_intel_crtc_state(crtc->base.state);
3090 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3091 crtc->base.base.id, pipe_name(crtc->pipe),
3092 yesno(pipe_config->base.active),
3093 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3094 yesno(pipe_config->dither), pipe_config->pipe_bpp);
3096 if (pipe_config->base.active) {
3097 intel_crtc_info(m, crtc);
3099 active = cursor_position(dev, crtc->pipe, &x, &y);
3100 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
3101 yesno(crtc->cursor_base),
3102 x, y, crtc->base.cursor->state->crtc_w,
3103 crtc->base.cursor->state->crtc_h,
3104 crtc->cursor_addr, yesno(active));
3105 intel_scaler_info(m, crtc);
3106 intel_plane_info(m, crtc);
3109 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3110 yesno(!crtc->cpu_fifo_underrun_disabled),
3111 yesno(!crtc->pch_fifo_underrun_disabled));
3114 seq_printf(m, "\n");
3115 seq_printf(m, "Connector info\n");
3116 seq_printf(m, "--------------\n");
3117 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3118 intel_connector_info(m, connector);
3120 drm_modeset_unlock_all(dev);
3121 intel_runtime_pm_put(dev_priv);
3126 static int i915_semaphore_status(struct seq_file *m, void *unused)
3128 struct drm_info_node *node = (struct drm_info_node *) m->private;
3129 struct drm_device *dev = node->minor->dev;
3130 struct drm_i915_private *dev_priv = dev->dev_private;
3131 struct intel_engine_cs *ring;
3132 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
3135 if (!i915_semaphore_is_enabled(dev)) {
3136 seq_puts(m, "Semaphores are disabled\n");
3140 ret = mutex_lock_interruptible(&dev->struct_mutex);
3143 intel_runtime_pm_get(dev_priv);
3145 if (IS_BROADWELL(dev)) {
3149 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
3151 seqno = (uint64_t *)kmap_atomic(page);
3152 for_each_ring(ring, dev_priv, i) {
3155 seq_printf(m, "%s\n", ring->name);
3157 seq_puts(m, " Last signal:");
3158 for (j = 0; j < num_rings; j++) {
3159 offset = i * I915_NUM_RINGS + j;
3160 seq_printf(m, "0x%08llx (0x%02llx) ",
3161 seqno[offset], offset * 8);
3165 seq_puts(m, " Last wait: ");
3166 for (j = 0; j < num_rings; j++) {
3167 offset = i + (j * I915_NUM_RINGS);
3168 seq_printf(m, "0x%08llx (0x%02llx) ",
3169 seqno[offset], offset * 8);
3174 kunmap_atomic(seqno);
3176 seq_puts(m, " Last signal:");
3177 for_each_ring(ring, dev_priv, i)
3178 for (j = 0; j < num_rings; j++)
3179 seq_printf(m, "0x%08x\n",
3180 I915_READ(ring->semaphore.mbox.signal[j]));
3184 seq_puts(m, "\nSync seqno:\n");
3185 for_each_ring(ring, dev_priv, i) {
3186 for (j = 0; j < num_rings; j++) {
3187 seq_printf(m, " 0x%08x ", ring->semaphore.sync_seqno[j]);
3193 intel_runtime_pm_put(dev_priv);
3194 mutex_unlock(&dev->struct_mutex);
3198 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3200 struct drm_info_node *node = (struct drm_info_node *) m->private;
3201 struct drm_device *dev = node->minor->dev;
3202 struct drm_i915_private *dev_priv = dev->dev_private;
3205 drm_modeset_lock_all(dev);
3206 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3207 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3209 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3210 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",
3211 pll->config.crtc_mask, pll->active, yesno(pll->on));
3212 seq_printf(m, " tracked hardware state:\n");
3213 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
3214 seq_printf(m, " dpll_md: 0x%08x\n",
3215 pll->config.hw_state.dpll_md);
3216 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
3217 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
3218 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
3220 drm_modeset_unlock_all(dev);
3225 static int i915_wa_registers(struct seq_file *m, void *unused)
3229 struct intel_engine_cs *ring;
3230 struct drm_info_node *node = (struct drm_info_node *) m->private;
3231 struct drm_device *dev = node->minor->dev;
3232 struct drm_i915_private *dev_priv = dev->dev_private;
3233 struct i915_workarounds *workarounds = &dev_priv->workarounds;
3235 ret = mutex_lock_interruptible(&dev->struct_mutex);
3239 intel_runtime_pm_get(dev_priv);
3241 seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
3242 for_each_ring(ring, dev_priv, i)
3243 seq_printf(m, "HW whitelist count for %s: %d\n",
3244 ring->name, workarounds->hw_whitelist_count[i]);
3245 for (i = 0; i < workarounds->count; ++i) {
3247 u32 mask, value, read;
3250 addr = workarounds->reg[i].addr;
3251 mask = workarounds->reg[i].mask;
3252 value = workarounds->reg[i].value;
3253 read = I915_READ(addr);
3254 ok = (value & mask) == (read & mask);
3255 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3256 i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
3259 intel_runtime_pm_put(dev_priv);
3260 mutex_unlock(&dev->struct_mutex);
3265 static int i915_ddb_info(struct seq_file *m, void *unused)
3267 struct drm_info_node *node = m->private;
3268 struct drm_device *dev = node->minor->dev;
3269 struct drm_i915_private *dev_priv = dev->dev_private;
3270 struct skl_ddb_allocation *ddb;
3271 struct skl_ddb_entry *entry;
3275 if (INTEL_INFO(dev)->gen < 9)
3278 drm_modeset_lock_all(dev);
3280 ddb = &dev_priv->wm.skl_hw.ddb;
3282 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3284 for_each_pipe(dev_priv, pipe) {
3285 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3287 for_each_plane(dev_priv, pipe, plane) {
3288 entry = &ddb->plane[pipe][plane];
3289 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
3290 entry->start, entry->end,
3291 skl_ddb_entry_size(entry));
3294 entry = &ddb->plane[pipe][PLANE_CURSOR];
3295 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
3296 entry->end, skl_ddb_entry_size(entry));
3299 drm_modeset_unlock_all(dev);
3304 static void drrs_status_per_crtc(struct seq_file *m,
3305 struct drm_device *dev, struct intel_crtc *intel_crtc)
3307 struct intel_encoder *intel_encoder;
3308 struct drm_i915_private *dev_priv = dev->dev_private;
3309 struct i915_drrs *drrs = &dev_priv->drrs;
3312 for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) {
3313 /* Encoder connected on this CRTC */
3314 switch (intel_encoder->type) {
3315 case INTEL_OUTPUT_EDP:
3316 seq_puts(m, "eDP:\n");
3318 case INTEL_OUTPUT_DSI:
3319 seq_puts(m, "DSI:\n");
3321 case INTEL_OUTPUT_HDMI:
3322 seq_puts(m, "HDMI:\n");
3324 case INTEL_OUTPUT_DISPLAYPORT:
3325 seq_puts(m, "DP:\n");
3328 seq_printf(m, "Other encoder (id=%d).\n",
3329 intel_encoder->type);
3334 if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3335 seq_puts(m, "\tVBT: DRRS_type: Static");
3336 else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3337 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3338 else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3339 seq_puts(m, "\tVBT: DRRS_type: None");
3341 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3343 seq_puts(m, "\n\n");
3345 if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3346 struct intel_panel *panel;
3348 mutex_lock(&drrs->mutex);
3349 /* DRRS Supported */
3350 seq_puts(m, "\tDRRS Supported: Yes\n");
3352 /* disable_drrs() will make drrs->dp NULL */
3354 seq_puts(m, "Idleness DRRS: Disabled");
3355 mutex_unlock(&drrs->mutex);
3359 panel = &drrs->dp->attached_connector->panel;
3360 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3361 drrs->busy_frontbuffer_bits);
3363 seq_puts(m, "\n\t\t");
3364 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3365 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3366 vrefresh = panel->fixed_mode->vrefresh;
3367 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3368 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3369 vrefresh = panel->downclock_mode->vrefresh;
3371 seq_printf(m, "DRRS_State: Unknown(%d)\n",
3372 drrs->refresh_rate_type);
3373 mutex_unlock(&drrs->mutex);
3376 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3378 seq_puts(m, "\n\t\t");
3379 mutex_unlock(&drrs->mutex);
3381 /* DRRS not supported. Print the VBT parameter*/
3382 seq_puts(m, "\tDRRS Supported : No");
3387 static int i915_drrs_status(struct seq_file *m, void *unused)
3389 struct drm_info_node *node = m->private;
3390 struct drm_device *dev = node->minor->dev;
3391 struct intel_crtc *intel_crtc;
3392 int active_crtc_cnt = 0;
3394 for_each_intel_crtc(dev, intel_crtc) {
3395 drm_modeset_lock(&intel_crtc->base.mutex, NULL);
3397 if (intel_crtc->base.state->active) {
3399 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt);
3401 drrs_status_per_crtc(m, dev, intel_crtc);
3404 drm_modeset_unlock(&intel_crtc->base.mutex);
3407 if (!active_crtc_cnt)
3408 seq_puts(m, "No active crtc found\n");
3413 struct pipe_crc_info {
3415 struct drm_device *dev;
3419 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3421 struct drm_info_node *node = (struct drm_info_node *) m->private;
3422 struct drm_device *dev = node->minor->dev;
3423 struct drm_encoder *encoder;
3424 struct intel_encoder *intel_encoder;
3425 struct intel_digital_port *intel_dig_port;
3426 drm_modeset_lock_all(dev);
3427 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3428 intel_encoder = to_intel_encoder(encoder);
3429 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
3431 intel_dig_port = enc_to_dig_port(encoder);
3432 if (!intel_dig_port->dp.can_mst)
3435 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3437 drm_modeset_unlock_all(dev);
3441 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3443 struct pipe_crc_info *info = inode->i_private;
3444 struct drm_i915_private *dev_priv = info->dev->dev_private;
3445 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3447 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3450 spin_lock_irq(&pipe_crc->lock);
3452 if (pipe_crc->opened) {
3453 spin_unlock_irq(&pipe_crc->lock);
3454 return -EBUSY; /* already open */
3457 pipe_crc->opened = true;
3458 filep->private_data = inode->i_private;
3460 spin_unlock_irq(&pipe_crc->lock);
3465 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3467 struct pipe_crc_info *info = inode->i_private;
3468 struct drm_i915_private *dev_priv = info->dev->dev_private;
3469 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3471 spin_lock_irq(&pipe_crc->lock);
3472 pipe_crc->opened = false;
3473 spin_unlock_irq(&pipe_crc->lock);
3478 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3479 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3480 /* account for \'0' */
3481 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3483 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
3485 assert_spin_locked(&pipe_crc->lock);
3486 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3487 INTEL_PIPE_CRC_ENTRIES_NR);
3491 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3494 struct pipe_crc_info *info = filep->private_data;
3495 struct drm_device *dev = info->dev;
3496 struct drm_i915_private *dev_priv = dev->dev_private;
3497 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3498 char buf[PIPE_CRC_BUFFER_LEN];
3503 * Don't allow user space to provide buffers not big enough to hold
3506 if (count < PIPE_CRC_LINE_LEN)
3509 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
3512 /* nothing to read */
3513 spin_lock_irq(&pipe_crc->lock);
3514 while (pipe_crc_data_count(pipe_crc) == 0) {
3517 if (filep->f_flags & O_NONBLOCK) {
3518 spin_unlock_irq(&pipe_crc->lock);
3522 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3523 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3525 spin_unlock_irq(&pipe_crc->lock);
3530 /* We now have one or more entries to read */
3531 n_entries = count / PIPE_CRC_LINE_LEN;
3534 while (n_entries > 0) {
3535 struct intel_pipe_crc_entry *entry =
3536 &pipe_crc->entries[pipe_crc->tail];
3539 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3540 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3543 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3544 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3546 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3547 "%8u %8x %8x %8x %8x %8x\n",
3548 entry->frame, entry->crc[0],
3549 entry->crc[1], entry->crc[2],
3550 entry->crc[3], entry->crc[4]);
3552 spin_unlock_irq(&pipe_crc->lock);
3554 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
3555 if (ret == PIPE_CRC_LINE_LEN)
3558 user_buf += PIPE_CRC_LINE_LEN;
3561 spin_lock_irq(&pipe_crc->lock);
3564 spin_unlock_irq(&pipe_crc->lock);
3569 static const struct file_operations i915_pipe_crc_fops = {
3570 .owner = THIS_MODULE,
3571 .open = i915_pipe_crc_open,
3572 .read = i915_pipe_crc_read,
3573 .release = i915_pipe_crc_release,
3576 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3578 .name = "i915_pipe_A_crc",
3582 .name = "i915_pipe_B_crc",
3586 .name = "i915_pipe_C_crc",
3591 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3594 struct drm_device *dev = minor->dev;
3596 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3599 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3600 &i915_pipe_crc_fops);
3604 return drm_add_fake_info_node(minor, ent, info);
3607 static const char * const pipe_crc_sources[] = {
3620 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3622 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3623 return pipe_crc_sources[source];
3626 static int display_crc_ctl_show(struct seq_file *m, void *data)
3628 struct drm_device *dev = m->private;
3629 struct drm_i915_private *dev_priv = dev->dev_private;
3632 for (i = 0; i < I915_MAX_PIPES; i++)
3633 seq_printf(m, "%c %s\n", pipe_name(i),
3634 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3639 static int display_crc_ctl_open(struct inode *inode, struct file *file)
3641 struct drm_device *dev = inode->i_private;
3643 return single_open(file, display_crc_ctl_show, dev);
3646 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3649 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3650 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3653 case INTEL_PIPE_CRC_SOURCE_PIPE:
3654 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3656 case INTEL_PIPE_CRC_SOURCE_NONE:
3666 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3667 enum intel_pipe_crc_source *source)
3669 struct intel_encoder *encoder;
3670 struct intel_crtc *crtc;
3671 struct intel_digital_port *dig_port;
3674 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3676 drm_modeset_lock_all(dev);
3677 for_each_intel_encoder(dev, encoder) {
3678 if (!encoder->base.crtc)
3681 crtc = to_intel_crtc(encoder->base.crtc);
3683 if (crtc->pipe != pipe)
3686 switch (encoder->type) {
3687 case INTEL_OUTPUT_TVOUT:
3688 *source = INTEL_PIPE_CRC_SOURCE_TV;
3690 case INTEL_OUTPUT_DISPLAYPORT:
3691 case INTEL_OUTPUT_EDP:
3692 dig_port = enc_to_dig_port(&encoder->base);
3693 switch (dig_port->port) {
3695 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3698 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3701 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3704 WARN(1, "nonexisting DP port %c\n",
3705 port_name(dig_port->port));
3713 drm_modeset_unlock_all(dev);
3718 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3720 enum intel_pipe_crc_source *source,
3723 struct drm_i915_private *dev_priv = dev->dev_private;
3724 bool need_stable_symbols = false;
3726 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3727 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3733 case INTEL_PIPE_CRC_SOURCE_PIPE:
3734 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3736 case INTEL_PIPE_CRC_SOURCE_DP_B:
3737 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3738 need_stable_symbols = true;
3740 case INTEL_PIPE_CRC_SOURCE_DP_C:
3741 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3742 need_stable_symbols = true;
3744 case INTEL_PIPE_CRC_SOURCE_DP_D:
3745 if (!IS_CHERRYVIEW(dev))
3747 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3748 need_stable_symbols = true;
3750 case INTEL_PIPE_CRC_SOURCE_NONE:
3758 * When the pipe CRC tap point is after the transcoders we need
3759 * to tweak symbol-level features to produce a deterministic series of
3760 * symbols for a given frame. We need to reset those features only once
3761 * a frame (instead of every nth symbol):
3762 * - DC-balance: used to ensure a better clock recovery from the data
3764 * - DisplayPort scrambling: used for EMI reduction
3766 if (need_stable_symbols) {
3767 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3769 tmp |= DC_BALANCE_RESET_VLV;
3772 tmp |= PIPE_A_SCRAMBLE_RESET;
3775 tmp |= PIPE_B_SCRAMBLE_RESET;
3778 tmp |= PIPE_C_SCRAMBLE_RESET;
3783 I915_WRITE(PORT_DFT2_G4X, tmp);
3789 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
3791 enum intel_pipe_crc_source *source,
3794 struct drm_i915_private *dev_priv = dev->dev_private;
3795 bool need_stable_symbols = false;
3797 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3798 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3804 case INTEL_PIPE_CRC_SOURCE_PIPE:
3805 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3807 case INTEL_PIPE_CRC_SOURCE_TV:
3808 if (!SUPPORTS_TV(dev))
3810 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3812 case INTEL_PIPE_CRC_SOURCE_DP_B:
3815 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3816 need_stable_symbols = true;
3818 case INTEL_PIPE_CRC_SOURCE_DP_C:
3821 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3822 need_stable_symbols = true;
3824 case INTEL_PIPE_CRC_SOURCE_DP_D:
3827 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3828 need_stable_symbols = true;
3830 case INTEL_PIPE_CRC_SOURCE_NONE:
3838 * When the pipe CRC tap point is after the transcoders we need
3839 * to tweak symbol-level features to produce a deterministic series of
3840 * symbols for a given frame. We need to reset those features only once
3841 * a frame (instead of every nth symbol):
3842 * - DC-balance: used to ensure a better clock recovery from the data
3844 * - DisplayPort scrambling: used for EMI reduction
3846 if (need_stable_symbols) {
3847 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3849 WARN_ON(!IS_G4X(dev));
3851 I915_WRITE(PORT_DFT_I9XX,
3852 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3855 tmp |= PIPE_A_SCRAMBLE_RESET;
3857 tmp |= PIPE_B_SCRAMBLE_RESET;
3859 I915_WRITE(PORT_DFT2_G4X, tmp);
3865 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3868 struct drm_i915_private *dev_priv = dev->dev_private;
3869 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3873 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3876 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3879 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3884 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3885 tmp &= ~DC_BALANCE_RESET_VLV;
3886 I915_WRITE(PORT_DFT2_G4X, tmp);
3890 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3893 struct drm_i915_private *dev_priv = dev->dev_private;
3894 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3897 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3899 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3900 I915_WRITE(PORT_DFT2_G4X, tmp);
3902 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3903 I915_WRITE(PORT_DFT_I9XX,
3904 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3908 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3911 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3912 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3915 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3916 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3918 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3919 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3921 case INTEL_PIPE_CRC_SOURCE_PIPE:
3922 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3924 case INTEL_PIPE_CRC_SOURCE_NONE:
3934 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev, bool enable)
3936 struct drm_i915_private *dev_priv = dev->dev_private;
3937 struct intel_crtc *crtc =
3938 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3939 struct intel_crtc_state *pipe_config;
3940 struct drm_atomic_state *state;
3943 drm_modeset_lock_all(dev);
3944 state = drm_atomic_state_alloc(dev);
3950 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
3951 pipe_config = intel_atomic_get_crtc_state(state, crtc);
3952 if (IS_ERR(pipe_config)) {
3953 ret = PTR_ERR(pipe_config);
3957 pipe_config->pch_pfit.force_thru = enable;
3958 if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
3959 pipe_config->pch_pfit.enabled != enable)
3960 pipe_config->base.connectors_changed = true;
3962 ret = drm_atomic_commit(state);
3964 drm_modeset_unlock_all(dev);
3965 WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
3967 drm_atomic_state_free(state);
3970 static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3972 enum intel_pipe_crc_source *source,
3975 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3976 *source = INTEL_PIPE_CRC_SOURCE_PF;
3979 case INTEL_PIPE_CRC_SOURCE_PLANE1:
3980 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3982 case INTEL_PIPE_CRC_SOURCE_PLANE2:
3983 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3985 case INTEL_PIPE_CRC_SOURCE_PF:
3986 if (IS_HASWELL(dev) && pipe == PIPE_A)
3987 hsw_trans_edp_pipe_A_crc_wa(dev, true);
3989 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3991 case INTEL_PIPE_CRC_SOURCE_NONE:
4001 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
4002 enum intel_pipe_crc_source source)
4004 struct drm_i915_private *dev_priv = dev->dev_private;
4005 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
4006 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
4008 enum intel_display_power_domain power_domain;
4009 u32 val = 0; /* shut up gcc */
4012 if (pipe_crc->source == source)
4015 /* forbid changing the source without going back to 'none' */
4016 if (pipe_crc->source && source)
4019 power_domain = POWER_DOMAIN_PIPE(pipe);
4020 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
4021 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
4026 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
4027 else if (INTEL_INFO(dev)->gen < 5)
4028 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4029 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4030 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4031 else if (IS_GEN5(dev) || IS_GEN6(dev))
4032 ret = ilk_pipe_crc_ctl_reg(&source, &val);
4034 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4039 /* none -> real source transition */
4041 struct intel_pipe_crc_entry *entries;
4043 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4044 pipe_name(pipe), pipe_crc_source_name(source));
4046 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
4047 sizeof(pipe_crc->entries[0]),
4055 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4056 * enabled and disabled dynamically based on package C states,
4057 * user space can't make reliable use of the CRCs, so let's just
4058 * completely disable it.
4060 hsw_disable_ips(crtc);
4062 spin_lock_irq(&pipe_crc->lock);
4063 kfree(pipe_crc->entries);
4064 pipe_crc->entries = entries;
4067 spin_unlock_irq(&pipe_crc->lock);
4070 pipe_crc->source = source;
4072 I915_WRITE(PIPE_CRC_CTL(pipe), val);
4073 POSTING_READ(PIPE_CRC_CTL(pipe));
4075 /* real source -> none transition */
4076 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
4077 struct intel_pipe_crc_entry *entries;
4078 struct intel_crtc *crtc =
4079 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
4081 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4084 drm_modeset_lock(&crtc->base.mutex, NULL);
4085 if (crtc->base.state->active)
4086 intel_wait_for_vblank(dev, pipe);
4087 drm_modeset_unlock(&crtc->base.mutex);
4089 spin_lock_irq(&pipe_crc->lock);
4090 entries = pipe_crc->entries;
4091 pipe_crc->entries = NULL;
4094 spin_unlock_irq(&pipe_crc->lock);
4099 g4x_undo_pipe_scramble_reset(dev, pipe);
4100 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4101 vlv_undo_pipe_scramble_reset(dev, pipe);
4102 else if (IS_HASWELL(dev) && pipe == PIPE_A)
4103 hsw_trans_edp_pipe_A_crc_wa(dev, false);
4105 hsw_enable_ips(crtc);
4111 intel_display_power_put(dev_priv, power_domain);
4117 * Parse pipe CRC command strings:
4118 * command: wsp* object wsp+ name wsp+ source wsp*
4121 * source: (none | plane1 | plane2 | pf)
4122 * wsp: (#0x20 | #0x9 | #0xA)+
4125 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
4126 * "pipe A none" -> Stop CRC
4128 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
4135 /* skip leading white space */
4136 buf = skip_spaces(buf);
4138 break; /* end of buffer */
4140 /* find end of word */
4141 for (end = buf; *end && !isspace(*end); end++)
4144 if (n_words == max_words) {
4145 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4147 return -EINVAL; /* ran out of words[] before bytes */
4152 words[n_words++] = buf;
4159 enum intel_pipe_crc_object {
4160 PIPE_CRC_OBJECT_PIPE,
4163 static const char * const pipe_crc_objects[] = {
4168 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
4172 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
4173 if (!strcmp(buf, pipe_crc_objects[i])) {
4181 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
4183 const char name = buf[0];
4185 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
4194 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
4198 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
4199 if (!strcmp(buf, pipe_crc_sources[i])) {
4207 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
4211 char *words[N_WORDS];
4213 enum intel_pipe_crc_object object;
4214 enum intel_pipe_crc_source source;
4216 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
4217 if (n_words != N_WORDS) {
4218 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4223 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
4224 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
4228 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
4229 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
4233 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
4234 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
4238 return pipe_crc_set_source(dev, pipe, source);
4241 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
4242 size_t len, loff_t *offp)
4244 struct seq_file *m = file->private_data;
4245 struct drm_device *dev = m->private;
4252 if (len > PAGE_SIZE - 1) {
4253 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4258 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
4262 if (copy_from_user(tmpbuf, ubuf, len)) {
4268 ret = display_crc_ctl_parse(dev, tmpbuf, len);
4279 static const struct file_operations i915_display_crc_ctl_fops = {
4280 .owner = THIS_MODULE,
4281 .open = display_crc_ctl_open,
4283 .llseek = seq_lseek,
4284 .release = single_release,
4285 .write = display_crc_ctl_write
4288 static ssize_t i915_displayport_test_active_write(struct file *file,
4289 const char __user *ubuf,
4290 size_t len, loff_t *offp)
4294 struct drm_device *dev;
4295 struct drm_connector *connector;
4296 struct list_head *connector_list;
4297 struct intel_dp *intel_dp;
4300 dev = ((struct seq_file *)file->private_data)->private;
4302 connector_list = &dev->mode_config.connector_list;
4307 input_buffer = kmalloc(len + 1, GFP_KERNEL);
4311 if (copy_from_user(input_buffer, ubuf, len)) {
4316 input_buffer[len] = '\0';
4317 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4319 list_for_each_entry(connector, connector_list, head) {
4321 if (connector->connector_type !=
4322 DRM_MODE_CONNECTOR_DisplayPort)
4325 if (connector->status == connector_status_connected &&
4326 connector->encoder != NULL) {
4327 intel_dp = enc_to_intel_dp(connector->encoder);
4328 status = kstrtoint(input_buffer, 10, &val);
4331 DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4332 /* To prevent erroneous activation of the compliance
4333 * testing code, only accept an actual value of 1 here
4336 intel_dp->compliance_test_active = 1;
4338 intel_dp->compliance_test_active = 0;
4342 kfree(input_buffer);
4350 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4352 struct drm_device *dev = m->private;
4353 struct drm_connector *connector;
4354 struct list_head *connector_list = &dev->mode_config.connector_list;
4355 struct intel_dp *intel_dp;
4357 list_for_each_entry(connector, connector_list, head) {
4359 if (connector->connector_type !=
4360 DRM_MODE_CONNECTOR_DisplayPort)
4363 if (connector->status == connector_status_connected &&
4364 connector->encoder != NULL) {
4365 intel_dp = enc_to_intel_dp(connector->encoder);
4366 if (intel_dp->compliance_test_active)
4377 static int i915_displayport_test_active_open(struct inode *inode,
4380 struct drm_device *dev = inode->i_private;
4382 return single_open(file, i915_displayport_test_active_show, dev);
4385 static const struct file_operations i915_displayport_test_active_fops = {
4386 .owner = THIS_MODULE,
4387 .open = i915_displayport_test_active_open,
4389 .llseek = seq_lseek,
4390 .release = single_release,
4391 .write = i915_displayport_test_active_write
4394 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4396 struct drm_device *dev = m->private;
4397 struct drm_connector *connector;
4398 struct list_head *connector_list = &dev->mode_config.connector_list;
4399 struct intel_dp *intel_dp;
4401 list_for_each_entry(connector, connector_list, head) {
4403 if (connector->connector_type !=
4404 DRM_MODE_CONNECTOR_DisplayPort)
4407 if (connector->status == connector_status_connected &&
4408 connector->encoder != NULL) {
4409 intel_dp = enc_to_intel_dp(connector->encoder);
4410 seq_printf(m, "%lx", intel_dp->compliance_test_data);
4417 static int i915_displayport_test_data_open(struct inode *inode,
4420 struct drm_device *dev = inode->i_private;
4422 return single_open(file, i915_displayport_test_data_show, dev);
4425 static const struct file_operations i915_displayport_test_data_fops = {
4426 .owner = THIS_MODULE,
4427 .open = i915_displayport_test_data_open,
4429 .llseek = seq_lseek,
4430 .release = single_release
4433 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4435 struct drm_device *dev = m->private;
4436 struct drm_connector *connector;
4437 struct list_head *connector_list = &dev->mode_config.connector_list;
4438 struct intel_dp *intel_dp;
4440 list_for_each_entry(connector, connector_list, head) {
4442 if (connector->connector_type !=
4443 DRM_MODE_CONNECTOR_DisplayPort)
4446 if (connector->status == connector_status_connected &&
4447 connector->encoder != NULL) {
4448 intel_dp = enc_to_intel_dp(connector->encoder);
4449 seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4457 static int i915_displayport_test_type_open(struct inode *inode,
4460 struct drm_device *dev = inode->i_private;
4462 return single_open(file, i915_displayport_test_type_show, dev);
4465 static const struct file_operations i915_displayport_test_type_fops = {
4466 .owner = THIS_MODULE,
4467 .open = i915_displayport_test_type_open,
4469 .llseek = seq_lseek,
4470 .release = single_release
4473 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
4475 struct drm_device *dev = m->private;
4479 if (IS_CHERRYVIEW(dev))
4481 else if (IS_VALLEYVIEW(dev))
4484 num_levels = ilk_wm_max_level(dev) + 1;
4486 drm_modeset_lock_all(dev);
4488 for (level = 0; level < num_levels; level++) {
4489 unsigned int latency = wm[level];
4492 * - WM1+ latency values in 0.5us units
4493 * - latencies are in us on gen9/vlv/chv
4495 if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev) ||
4501 seq_printf(m, "WM%d %u (%u.%u usec)\n",
4502 level, wm[level], latency / 10, latency % 10);
4505 drm_modeset_unlock_all(dev);
4508 static int pri_wm_latency_show(struct seq_file *m, void *data)
4510 struct drm_device *dev = m->private;
4511 struct drm_i915_private *dev_priv = dev->dev_private;
4512 const uint16_t *latencies;
4514 if (INTEL_INFO(dev)->gen >= 9)
4515 latencies = dev_priv->wm.skl_latency;
4517 latencies = to_i915(dev)->wm.pri_latency;
4519 wm_latency_show(m, latencies);
4524 static int spr_wm_latency_show(struct seq_file *m, void *data)
4526 struct drm_device *dev = m->private;
4527 struct drm_i915_private *dev_priv = dev->dev_private;
4528 const uint16_t *latencies;
4530 if (INTEL_INFO(dev)->gen >= 9)
4531 latencies = dev_priv->wm.skl_latency;
4533 latencies = to_i915(dev)->wm.spr_latency;
4535 wm_latency_show(m, latencies);
4540 static int cur_wm_latency_show(struct seq_file *m, void *data)
4542 struct drm_device *dev = m->private;
4543 struct drm_i915_private *dev_priv = dev->dev_private;
4544 const uint16_t *latencies;
4546 if (INTEL_INFO(dev)->gen >= 9)
4547 latencies = dev_priv->wm.skl_latency;
4549 latencies = to_i915(dev)->wm.cur_latency;
4551 wm_latency_show(m, latencies);
4556 static int pri_wm_latency_open(struct inode *inode, struct file *file)
4558 struct drm_device *dev = inode->i_private;
4560 if (INTEL_INFO(dev)->gen < 5)
4563 return single_open(file, pri_wm_latency_show, dev);
4566 static int spr_wm_latency_open(struct inode *inode, struct file *file)
4568 struct drm_device *dev = inode->i_private;
4570 if (HAS_GMCH_DISPLAY(dev))
4573 return single_open(file, spr_wm_latency_show, dev);
4576 static int cur_wm_latency_open(struct inode *inode, struct file *file)
4578 struct drm_device *dev = inode->i_private;
4580 if (HAS_GMCH_DISPLAY(dev))
4583 return single_open(file, cur_wm_latency_show, dev);
4586 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
4587 size_t len, loff_t *offp, uint16_t wm[8])
4589 struct seq_file *m = file->private_data;
4590 struct drm_device *dev = m->private;
4591 uint16_t new[8] = { 0 };
4597 if (IS_CHERRYVIEW(dev))
4599 else if (IS_VALLEYVIEW(dev))
4602 num_levels = ilk_wm_max_level(dev) + 1;
4604 if (len >= sizeof(tmp))
4607 if (copy_from_user(tmp, ubuf, len))
4612 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4613 &new[0], &new[1], &new[2], &new[3],
4614 &new[4], &new[5], &new[6], &new[7]);
4615 if (ret != num_levels)
4618 drm_modeset_lock_all(dev);
4620 for (level = 0; level < num_levels; level++)
4621 wm[level] = new[level];
4623 drm_modeset_unlock_all(dev);
4629 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4630 size_t len, loff_t *offp)
4632 struct seq_file *m = file->private_data;
4633 struct drm_device *dev = m->private;
4634 struct drm_i915_private *dev_priv = dev->dev_private;
4635 uint16_t *latencies;
4637 if (INTEL_INFO(dev)->gen >= 9)
4638 latencies = dev_priv->wm.skl_latency;
4640 latencies = to_i915(dev)->wm.pri_latency;
4642 return wm_latency_write(file, ubuf, len, offp, latencies);
4645 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4646 size_t len, loff_t *offp)
4648 struct seq_file *m = file->private_data;
4649 struct drm_device *dev = m->private;
4650 struct drm_i915_private *dev_priv = dev->dev_private;
4651 uint16_t *latencies;
4653 if (INTEL_INFO(dev)->gen >= 9)
4654 latencies = dev_priv->wm.skl_latency;
4656 latencies = to_i915(dev)->wm.spr_latency;
4658 return wm_latency_write(file, ubuf, len, offp, latencies);
4661 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4662 size_t len, loff_t *offp)
4664 struct seq_file *m = file->private_data;
4665 struct drm_device *dev = m->private;
4666 struct drm_i915_private *dev_priv = dev->dev_private;
4667 uint16_t *latencies;
4669 if (INTEL_INFO(dev)->gen >= 9)
4670 latencies = dev_priv->wm.skl_latency;
4672 latencies = to_i915(dev)->wm.cur_latency;
4674 return wm_latency_write(file, ubuf, len, offp, latencies);
4677 static const struct file_operations i915_pri_wm_latency_fops = {
4678 .owner = THIS_MODULE,
4679 .open = pri_wm_latency_open,
4681 .llseek = seq_lseek,
4682 .release = single_release,
4683 .write = pri_wm_latency_write
4686 static const struct file_operations i915_spr_wm_latency_fops = {
4687 .owner = THIS_MODULE,
4688 .open = spr_wm_latency_open,
4690 .llseek = seq_lseek,
4691 .release = single_release,
4692 .write = spr_wm_latency_write
4695 static const struct file_operations i915_cur_wm_latency_fops = {
4696 .owner = THIS_MODULE,
4697 .open = cur_wm_latency_open,
4699 .llseek = seq_lseek,
4700 .release = single_release,
4701 .write = cur_wm_latency_write
4705 i915_wedged_get(void *data, u64 *val)
4707 struct drm_device *dev = data;
4708 struct drm_i915_private *dev_priv = dev->dev_private;
4710 *val = atomic_read(&dev_priv->gpu_error.reset_counter);
4716 i915_wedged_set(void *data, u64 val)
4718 struct drm_device *dev = data;
4719 struct drm_i915_private *dev_priv = dev->dev_private;
4722 * There is no safeguard against this debugfs entry colliding
4723 * with the hangcheck calling same i915_handle_error() in
4724 * parallel, causing an explosion. For now we assume that the
4725 * test harness is responsible enough not to inject gpu hangs
4726 * while it is writing to 'i915_wedged'
4729 if (i915_reset_in_progress(&dev_priv->gpu_error))
4732 intel_runtime_pm_get(dev_priv);
4734 i915_handle_error(dev, val,
4735 "Manually setting wedged to %llu", val);
4737 intel_runtime_pm_put(dev_priv);
4742 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4743 i915_wedged_get, i915_wedged_set,
4747 i915_ring_stop_get(void *data, u64 *val)
4749 struct drm_device *dev = data;
4750 struct drm_i915_private *dev_priv = dev->dev_private;
4752 *val = dev_priv->gpu_error.stop_rings;
4758 i915_ring_stop_set(void *data, u64 val)
4760 struct drm_device *dev = data;
4761 struct drm_i915_private *dev_priv = dev->dev_private;
4764 DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
4766 ret = mutex_lock_interruptible(&dev->struct_mutex);
4770 dev_priv->gpu_error.stop_rings = val;
4771 mutex_unlock(&dev->struct_mutex);
4776 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
4777 i915_ring_stop_get, i915_ring_stop_set,
4781 i915_ring_missed_irq_get(void *data, u64 *val)
4783 struct drm_device *dev = data;
4784 struct drm_i915_private *dev_priv = dev->dev_private;
4786 *val = dev_priv->gpu_error.missed_irq_rings;
4791 i915_ring_missed_irq_set(void *data, u64 val)
4793 struct drm_device *dev = data;
4794 struct drm_i915_private *dev_priv = dev->dev_private;
4797 /* Lock against concurrent debugfs callers */
4798 ret = mutex_lock_interruptible(&dev->struct_mutex);
4801 dev_priv->gpu_error.missed_irq_rings = val;
4802 mutex_unlock(&dev->struct_mutex);
4807 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4808 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4812 i915_ring_test_irq_get(void *data, u64 *val)
4814 struct drm_device *dev = data;
4815 struct drm_i915_private *dev_priv = dev->dev_private;
4817 *val = dev_priv->gpu_error.test_irq_rings;
4823 i915_ring_test_irq_set(void *data, u64 val)
4825 struct drm_device *dev = data;
4826 struct drm_i915_private *dev_priv = dev->dev_private;
4829 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4831 /* Lock against concurrent debugfs callers */
4832 ret = mutex_lock_interruptible(&dev->struct_mutex);
4836 dev_priv->gpu_error.test_irq_rings = val;
4837 mutex_unlock(&dev->struct_mutex);
4842 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4843 i915_ring_test_irq_get, i915_ring_test_irq_set,
4846 #define DROP_UNBOUND 0x1
4847 #define DROP_BOUND 0x2
4848 #define DROP_RETIRE 0x4
4849 #define DROP_ACTIVE 0x8
4850 #define DROP_ALL (DROP_UNBOUND | \
4855 i915_drop_caches_get(void *data, u64 *val)
4863 i915_drop_caches_set(void *data, u64 val)
4865 struct drm_device *dev = data;
4866 struct drm_i915_private *dev_priv = dev->dev_private;
4869 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4871 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4872 * on ioctls on -EAGAIN. */
4873 ret = mutex_lock_interruptible(&dev->struct_mutex);
4877 if (val & DROP_ACTIVE) {
4878 ret = i915_gpu_idle(dev);
4883 if (val & (DROP_RETIRE | DROP_ACTIVE))
4884 i915_gem_retire_requests(dev);
4886 if (val & DROP_BOUND)
4887 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4889 if (val & DROP_UNBOUND)
4890 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4893 mutex_unlock(&dev->struct_mutex);
4898 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4899 i915_drop_caches_get, i915_drop_caches_set,
4903 i915_max_freq_get(void *data, u64 *val)
4905 struct drm_device *dev = data;
4906 struct drm_i915_private *dev_priv = dev->dev_private;
4909 if (INTEL_INFO(dev)->gen < 6)
4912 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4914 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4918 *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4919 mutex_unlock(&dev_priv->rps.hw_lock);
4925 i915_max_freq_set(void *data, u64 val)
4927 struct drm_device *dev = data;
4928 struct drm_i915_private *dev_priv = dev->dev_private;
4932 if (INTEL_INFO(dev)->gen < 6)
4935 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4937 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4939 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4944 * Turbo will still be enabled, but won't go above the set value.
4946 val = intel_freq_opcode(dev_priv, val);
4948 hw_max = dev_priv->rps.max_freq;
4949 hw_min = dev_priv->rps.min_freq;
4951 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4952 mutex_unlock(&dev_priv->rps.hw_lock);
4956 dev_priv->rps.max_freq_softlimit = val;
4958 intel_set_rps(dev, val);
4960 mutex_unlock(&dev_priv->rps.hw_lock);
4965 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4966 i915_max_freq_get, i915_max_freq_set,
4970 i915_min_freq_get(void *data, u64 *val)
4972 struct drm_device *dev = data;
4973 struct drm_i915_private *dev_priv = dev->dev_private;
4976 if (INTEL_INFO(dev)->gen < 6)
4979 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4981 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4985 *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4986 mutex_unlock(&dev_priv->rps.hw_lock);
4992 i915_min_freq_set(void *data, u64 val)
4994 struct drm_device *dev = data;
4995 struct drm_i915_private *dev_priv = dev->dev_private;
4999 if (INTEL_INFO(dev)->gen < 6)
5002 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5004 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
5006 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
5011 * Turbo will still be enabled, but won't go below the set value.
5013 val = intel_freq_opcode(dev_priv, val);
5015 hw_max = dev_priv->rps.max_freq;
5016 hw_min = dev_priv->rps.min_freq;
5018 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
5019 mutex_unlock(&dev_priv->rps.hw_lock);
5023 dev_priv->rps.min_freq_softlimit = val;
5025 intel_set_rps(dev, val);
5027 mutex_unlock(&dev_priv->rps.hw_lock);
5032 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
5033 i915_min_freq_get, i915_min_freq_set,
5037 i915_cache_sharing_get(void *data, u64 *val)
5039 struct drm_device *dev = data;
5040 struct drm_i915_private *dev_priv = dev->dev_private;
5044 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5047 ret = mutex_lock_interruptible(&dev->struct_mutex);
5050 intel_runtime_pm_get(dev_priv);
5052 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5054 intel_runtime_pm_put(dev_priv);
5055 mutex_unlock(&dev_priv->dev->struct_mutex);
5057 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
5063 i915_cache_sharing_set(void *data, u64 val)
5065 struct drm_device *dev = data;
5066 struct drm_i915_private *dev_priv = dev->dev_private;
5069 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5075 intel_runtime_pm_get(dev_priv);
5076 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
5078 /* Update the cache sharing policy here as well */
5079 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5080 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5081 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
5082 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5084 intel_runtime_pm_put(dev_priv);
5088 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
5089 i915_cache_sharing_get, i915_cache_sharing_set,
5092 struct sseu_dev_status {
5093 unsigned int slice_total;
5094 unsigned int subslice_total;
5095 unsigned int subslice_per_slice;
5096 unsigned int eu_total;
5097 unsigned int eu_per_subslice;
5100 static void cherryview_sseu_device_status(struct drm_device *dev,
5101 struct sseu_dev_status *stat)
5103 struct drm_i915_private *dev_priv = dev->dev_private;
5106 u32 sig1[ss_max], sig2[ss_max];
5108 sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
5109 sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
5110 sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
5111 sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
5113 for (ss = 0; ss < ss_max; ss++) {
5114 unsigned int eu_cnt;
5116 if (sig1[ss] & CHV_SS_PG_ENABLE)
5117 /* skip disabled subslice */
5120 stat->slice_total = 1;
5121 stat->subslice_per_slice++;
5122 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
5123 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
5124 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
5125 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
5126 stat->eu_total += eu_cnt;
5127 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
5129 stat->subslice_total = stat->subslice_per_slice;
5132 static void gen9_sseu_device_status(struct drm_device *dev,
5133 struct sseu_dev_status *stat)
5135 struct drm_i915_private *dev_priv = dev->dev_private;
5136 int s_max = 3, ss_max = 4;
5138 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
5140 /* BXT has a single slice and at most 3 subslices. */
5141 if (IS_BROXTON(dev)) {
5146 for (s = 0; s < s_max; s++) {
5147 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
5148 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
5149 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
5152 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
5153 GEN9_PGCTL_SSA_EU19_ACK |
5154 GEN9_PGCTL_SSA_EU210_ACK |
5155 GEN9_PGCTL_SSA_EU311_ACK;
5156 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
5157 GEN9_PGCTL_SSB_EU19_ACK |
5158 GEN9_PGCTL_SSB_EU210_ACK |
5159 GEN9_PGCTL_SSB_EU311_ACK;
5161 for (s = 0; s < s_max; s++) {
5162 unsigned int ss_cnt = 0;
5164 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
5165 /* skip disabled slice */
5168 stat->slice_total++;
5170 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
5171 ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
5173 for (ss = 0; ss < ss_max; ss++) {
5174 unsigned int eu_cnt;
5176 if (IS_BROXTON(dev) &&
5177 !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
5178 /* skip disabled subslice */
5181 if (IS_BROXTON(dev))
5184 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
5186 stat->eu_total += eu_cnt;
5187 stat->eu_per_subslice = max(stat->eu_per_subslice,
5191 stat->subslice_total += ss_cnt;
5192 stat->subslice_per_slice = max(stat->subslice_per_slice,
5197 static void broadwell_sseu_device_status(struct drm_device *dev,
5198 struct sseu_dev_status *stat)
5200 struct drm_i915_private *dev_priv = dev->dev_private;
5202 u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
5204 stat->slice_total = hweight32(slice_info & GEN8_LSLICESTAT_MASK);
5206 if (stat->slice_total) {
5207 stat->subslice_per_slice = INTEL_INFO(dev)->subslice_per_slice;
5208 stat->subslice_total = stat->slice_total *
5209 stat->subslice_per_slice;
5210 stat->eu_per_subslice = INTEL_INFO(dev)->eu_per_subslice;
5211 stat->eu_total = stat->eu_per_subslice * stat->subslice_total;
5213 /* subtract fused off EU(s) from enabled slice(s) */
5214 for (s = 0; s < stat->slice_total; s++) {
5215 u8 subslice_7eu = INTEL_INFO(dev)->subslice_7eu[s];
5217 stat->eu_total -= hweight8(subslice_7eu);
5222 static int i915_sseu_status(struct seq_file *m, void *unused)
5224 struct drm_info_node *node = (struct drm_info_node *) m->private;
5225 struct drm_device *dev = node->minor->dev;
5226 struct sseu_dev_status stat;
5228 if (INTEL_INFO(dev)->gen < 8)
5231 seq_puts(m, "SSEU Device Info\n");
5232 seq_printf(m, " Available Slice Total: %u\n",
5233 INTEL_INFO(dev)->slice_total);
5234 seq_printf(m, " Available Subslice Total: %u\n",
5235 INTEL_INFO(dev)->subslice_total);
5236 seq_printf(m, " Available Subslice Per Slice: %u\n",
5237 INTEL_INFO(dev)->subslice_per_slice);
5238 seq_printf(m, " Available EU Total: %u\n",
5239 INTEL_INFO(dev)->eu_total);
5240 seq_printf(m, " Available EU Per Subslice: %u\n",
5241 INTEL_INFO(dev)->eu_per_subslice);
5242 seq_printf(m, " Has Slice Power Gating: %s\n",
5243 yesno(INTEL_INFO(dev)->has_slice_pg));
5244 seq_printf(m, " Has Subslice Power Gating: %s\n",
5245 yesno(INTEL_INFO(dev)->has_subslice_pg));
5246 seq_printf(m, " Has EU Power Gating: %s\n",
5247 yesno(INTEL_INFO(dev)->has_eu_pg));
5249 seq_puts(m, "SSEU Device Status\n");
5250 memset(&stat, 0, sizeof(stat));
5251 if (IS_CHERRYVIEW(dev)) {
5252 cherryview_sseu_device_status(dev, &stat);
5253 } else if (IS_BROADWELL(dev)) {
5254 broadwell_sseu_device_status(dev, &stat);
5255 } else if (INTEL_INFO(dev)->gen >= 9) {
5256 gen9_sseu_device_status(dev, &stat);
5258 seq_printf(m, " Enabled Slice Total: %u\n",
5260 seq_printf(m, " Enabled Subslice Total: %u\n",
5261 stat.subslice_total);
5262 seq_printf(m, " Enabled Subslice Per Slice: %u\n",
5263 stat.subslice_per_slice);
5264 seq_printf(m, " Enabled EU Total: %u\n",
5266 seq_printf(m, " Enabled EU Per Subslice: %u\n",
5267 stat.eu_per_subslice);
5272 static int i915_forcewake_open(struct inode *inode, struct file *file)
5274 struct drm_device *dev = inode->i_private;
5275 struct drm_i915_private *dev_priv = dev->dev_private;
5277 if (INTEL_INFO(dev)->gen < 6)
5280 intel_runtime_pm_get(dev_priv);
5281 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5286 static int i915_forcewake_release(struct inode *inode, struct file *file)
5288 struct drm_device *dev = inode->i_private;
5289 struct drm_i915_private *dev_priv = dev->dev_private;
5291 if (INTEL_INFO(dev)->gen < 6)
5294 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5295 intel_runtime_pm_put(dev_priv);
5300 static const struct file_operations i915_forcewake_fops = {
5301 .owner = THIS_MODULE,
5302 .open = i915_forcewake_open,
5303 .release = i915_forcewake_release,
5306 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5308 struct drm_device *dev = minor->dev;
5311 ent = debugfs_create_file("i915_forcewake_user",
5314 &i915_forcewake_fops);
5318 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
5321 static int i915_debugfs_create(struct dentry *root,
5322 struct drm_minor *minor,
5324 const struct file_operations *fops)
5326 struct drm_device *dev = minor->dev;
5329 ent = debugfs_create_file(name,
5336 return drm_add_fake_info_node(minor, ent, fops);
5339 static const struct drm_info_list i915_debugfs_list[] = {
5340 {"i915_capabilities", i915_capabilities, 0},
5341 {"i915_gem_objects", i915_gem_object_info, 0},
5342 {"i915_gem_gtt", i915_gem_gtt_info, 0},
5343 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
5344 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
5345 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
5346 {"i915_gem_stolen", i915_gem_stolen_list_info },
5347 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
5348 {"i915_gem_request", i915_gem_request_info, 0},
5349 {"i915_gem_seqno", i915_gem_seqno_info, 0},
5350 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
5351 {"i915_gem_interrupt", i915_interrupt_info, 0},
5352 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5353 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5354 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
5355 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
5356 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
5357 {"i915_guc_info", i915_guc_info, 0},
5358 {"i915_guc_load_status", i915_guc_load_status_info, 0},
5359 {"i915_guc_log_dump", i915_guc_log_dump, 0},
5360 {"i915_frequency_info", i915_frequency_info, 0},
5361 {"i915_hangcheck_info", i915_hangcheck_info, 0},
5362 {"i915_drpc_info", i915_drpc_info, 0},
5363 {"i915_emon_status", i915_emon_status, 0},
5364 {"i915_ring_freq_table", i915_ring_freq_table, 0},
5365 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
5366 {"i915_fbc_status", i915_fbc_status, 0},
5367 {"i915_ips_status", i915_ips_status, 0},
5368 {"i915_sr_status", i915_sr_status, 0},
5369 {"i915_opregion", i915_opregion, 0},
5370 {"i915_vbt", i915_vbt, 0},
5371 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
5372 {"i915_context_status", i915_context_status, 0},
5373 {"i915_dump_lrc", i915_dump_lrc, 0},
5374 {"i915_execlists", i915_execlists, 0},
5375 {"i915_forcewake_domains", i915_forcewake_domains, 0},
5376 {"i915_swizzle_info", i915_swizzle_info, 0},
5377 {"i915_ppgtt_info", i915_ppgtt_info, 0},
5378 {"i915_llc", i915_llc, 0},
5379 {"i915_edp_psr_status", i915_edp_psr_status, 0},
5380 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
5381 {"i915_energy_uJ", i915_energy_uJ, 0},
5382 {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
5383 {"i915_power_domain_info", i915_power_domain_info, 0},
5384 {"i915_dmc_info", i915_dmc_info, 0},
5385 {"i915_display_info", i915_display_info, 0},
5386 {"i915_semaphore_status", i915_semaphore_status, 0},
5387 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
5388 {"i915_dp_mst_info", i915_dp_mst_info, 0},
5389 {"i915_wa_registers", i915_wa_registers, 0},
5390 {"i915_ddb_info", i915_ddb_info, 0},
5391 {"i915_sseu_status", i915_sseu_status, 0},
5392 {"i915_drrs_status", i915_drrs_status, 0},
5393 {"i915_rps_boost_info", i915_rps_boost_info, 0},
5395 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5397 static const struct i915_debugfs_files {
5399 const struct file_operations *fops;
5400 } i915_debugfs_files[] = {
5401 {"i915_wedged", &i915_wedged_fops},
5402 {"i915_max_freq", &i915_max_freq_fops},
5403 {"i915_min_freq", &i915_min_freq_fops},
5404 {"i915_cache_sharing", &i915_cache_sharing_fops},
5405 {"i915_ring_stop", &i915_ring_stop_fops},
5406 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5407 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
5408 {"i915_gem_drop_caches", &i915_drop_caches_fops},
5409 {"i915_error_state", &i915_error_state_fops},
5410 {"i915_next_seqno", &i915_next_seqno_fops},
5411 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
5412 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5413 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5414 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
5415 {"i915_fbc_false_color", &i915_fbc_fc_fops},
5416 {"i915_dp_test_data", &i915_displayport_test_data_fops},
5417 {"i915_dp_test_type", &i915_displayport_test_type_fops},
5418 {"i915_dp_test_active", &i915_displayport_test_active_fops}
5421 void intel_display_crc_init(struct drm_device *dev)
5423 struct drm_i915_private *dev_priv = dev->dev_private;
5426 for_each_pipe(dev_priv, pipe) {
5427 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
5429 pipe_crc->opened = false;
5430 spin_lock_init(&pipe_crc->lock);
5431 init_waitqueue_head(&pipe_crc->wq);
5435 int i915_debugfs_init(struct drm_minor *minor)
5439 ret = i915_forcewake_create(minor->debugfs_root, minor);
5443 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5444 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5449 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5450 ret = i915_debugfs_create(minor->debugfs_root, minor,
5451 i915_debugfs_files[i].name,
5452 i915_debugfs_files[i].fops);
5457 return drm_debugfs_create_files(i915_debugfs_list,
5458 I915_DEBUGFS_ENTRIES,
5459 minor->debugfs_root, minor);
5462 void i915_debugfs_cleanup(struct drm_minor *minor)
5466 drm_debugfs_remove_files(i915_debugfs_list,
5467 I915_DEBUGFS_ENTRIES, minor);
5469 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
5472 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5473 struct drm_info_list *info_list =
5474 (struct drm_info_list *)&i915_pipe_crc_data[i];
5476 drm_debugfs_remove_files(info_list, 1, minor);
5479 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5480 struct drm_info_list *info_list =
5481 (struct drm_info_list *) i915_debugfs_files[i].fops;
5483 drm_debugfs_remove_files(info_list, 1, minor);
5488 /* DPCD dump start address. */
5489 unsigned int offset;
5490 /* DPCD dump end address, inclusive. If unset, .size will be used. */
5492 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5494 /* Only valid for eDP. */
5498 static const struct dpcd_block i915_dpcd_debug[] = {
5499 { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5500 { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5501 { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5502 { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5503 { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5504 { .offset = DP_SET_POWER },
5505 { .offset = DP_EDP_DPCD_REV },
5506 { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5507 { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5508 { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5511 static int i915_dpcd_show(struct seq_file *m, void *data)
5513 struct drm_connector *connector = m->private;
5514 struct intel_dp *intel_dp =
5515 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5520 if (connector->status != connector_status_connected)
5523 for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5524 const struct dpcd_block *b = &i915_dpcd_debug[i];
5525 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5528 connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5531 /* low tech for now */
5532 if (WARN_ON(size > sizeof(buf)))
5535 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5537 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5538 size, b->offset, err);
5542 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
5548 static int i915_dpcd_open(struct inode *inode, struct file *file)
5550 return single_open(file, i915_dpcd_show, inode->i_private);
5553 static const struct file_operations i915_dpcd_fops = {
5554 .owner = THIS_MODULE,
5555 .open = i915_dpcd_open,
5557 .llseek = seq_lseek,
5558 .release = single_release,
5562 * i915_debugfs_connector_add - add i915 specific connector debugfs files
5563 * @connector: pointer to a registered drm_connector
5565 * Cleanup will be done by drm_connector_unregister() through a call to
5566 * drm_debugfs_connector_remove().
5568 * Returns 0 on success, negative error codes on error.
5570 int i915_debugfs_connector_add(struct drm_connector *connector)
5572 struct dentry *root = connector->debugfs_entry;
5574 /* The connector must have been registered beforehands. */
5578 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5579 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5580 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,