drivers/gpu/drm/i915/i915_debugfs.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *
  27  */
  28
  29 #include <linux/seq_file.h>
  30 #include <linux/circ_buf.h>
  31 #include <linux/ctype.h>
  32 #include <linux/debugfs.h>
  33 #include <linux/slab.h>
  34 #include <linux/export.h>
  35 #include <linux/list_sort.h>
  36 #include <asm/msr-index.h>
  37 #include <drm/drmP.h>
  38 #include "intel_drv.h"
  39 #include "intel_ringbuffer.h"
  40 #include <drm/i915_drm.h>
  41 #include "i915_drv.h"
  42
  43 static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
  44 {
  45         return to_i915(node->minor->dev);
  46 }
  47
  48 /* As the drm_debugfs_init() routines are called before dev->dev_private is
  49  * allocated we need to hook into the minor for release. */
  50 static int
  51 drm_add_fake_info_node(struct drm_minor *minor,
  52                        struct dentry *ent,
  53                        const void *key)
  54 {
  55         struct drm_info_node *node;
  56
  57         node = kmalloc(sizeof(*node), GFP_KERNEL);
  58         if (node == NULL) {
  59                 debugfs_remove(ent);
  60                 return -ENOMEM;
  61         }
  62
  63         node->minor = minor;
  64         node->dent = ent;
  65         node->info_ent = (void *)key;
  66
  67         mutex_lock(&minor->debugfs_lock);
  68         list_add(&node->list, &minor->debugfs_list);
  69         mutex_unlock(&minor->debugfs_lock);
  70
  71         return 0;
  72 }
  73
  74 static int i915_capabilities(struct seq_file *m, void *data)
  75 {
  76         struct drm_i915_private *dev_priv = node_to_i915(m->private);
  77         const struct intel_device_info *info = INTEL_INFO(dev_priv);
  78
  79         seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv));
  80         seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv));
  81 #define PRINT_FLAG(x)  seq_printf(m, #x ": %s\n", yesno(info->x))
  82 #define SEP_SEMICOLON ;
  83         DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
  84 #undef PRINT_FLAG
  85 #undef SEP_SEMICOLON
  86
  87         return 0;
  88 }
  89
  90 static char get_active_flag(struct drm_i915_gem_object *obj)
  91 {
  92         return i915_gem_object_is_active(obj) ? '*' : ' ';
  93 }
  94
  95 static char get_pin_flag(struct drm_i915_gem_object *obj)
  96 {
  97         return obj->pin_display ? 'p' : ' ';
  98 }
  99
 100 static char get_tiling_flag(struct drm_i915_gem_object *obj)
 101 {
 102         switch (i915_gem_object_get_tiling(obj)) {
 103         default:
 104         case I915_TILING_NONE: return ' ';
 105         case I915_TILING_X: return 'X';
 106         case I915_TILING_Y: return 'Y';
 107         }
 108 }
 109
 110 static char get_global_flag(struct drm_i915_gem_object *obj)
 111 {
 112         return i915_gem_object_to_ggtt(obj, NULL) ?  'g' : ' ';
 113 }
 114
 115 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
 116 {
 117         return obj->mapping ? 'M' : ' ';
 118 }
 119
 120 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
 121 {
 122         u64 size = 0;
 123         struct i915_vma *vma;
 124
 125         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 126                 if (i915_vma_is_ggtt(vma) && drm_mm_node_allocated(&vma->node))
 127                         size += vma->node.size;
 128         }
 129
 130         return size;
 131 }
 132
 133 static void
 134 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
 135 {
 136         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
 137         struct intel_engine_cs *engine;
 138         struct i915_vma *vma;
 139         unsigned int frontbuffer_bits;
 140         int pin_count = 0;
 141         enum intel_engine_id id;
 142
 143         lockdep_assert_held(&obj->base.dev->struct_mutex);
 144
 145         seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x [ ",
 146                    &obj->base,
 147                    get_active_flag(obj),
 148                    get_pin_flag(obj),
 149                    get_tiling_flag(obj),
 150                    get_global_flag(obj),
 151                    get_pin_mapped_flag(obj),
 152                    obj->base.size / 1024,
 153                    obj->base.read_domains,
 154                    obj->base.write_domain);
 155         for_each_engine_id(engine, dev_priv, id)
 156                 seq_printf(m, "%x ",
 157                            i915_gem_active_get_seqno(&obj->last_read[id],
 158                                                      &obj->base.dev->struct_mutex));
 159         seq_printf(m, "] %x %s%s%s",
 160                    i915_gem_active_get_seqno(&obj->last_write,
 161                                              &obj->base.dev->struct_mutex),
 162                    i915_cache_level_str(dev_priv, obj->cache_level),
 163                    obj->dirty ? " dirty" : "",
 164                    obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
 165         if (obj->base.name)
 166                 seq_printf(m, " (name: %d)", obj->base.name);
 167         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 168                 if (i915_vma_is_pinned(vma))
 169                         pin_count++;
 170         }
 171         seq_printf(m, " (pinned x %d)", pin_count);
 172         if (obj->pin_display)
 173                 seq_printf(m, " (display)");
 174         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 175                 if (!drm_mm_node_allocated(&vma->node))
 176                         continue;
 177
 178                 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
 179                            i915_vma_is_ggtt(vma) ? "g" : "pp",
 180                            vma->node.start, vma->node.size);
 181                 if (i915_vma_is_ggtt(vma))
 182                         seq_printf(m, ", type: %u", vma->ggtt_view.type);
 183                 if (vma->fence)
 184                         seq_printf(m, " , fence: %d%s",
 185                                    vma->fence->id,
 186                                    i915_gem_active_isset(&vma->last_fence) ? "*" : "");
 187                 seq_puts(m, ")");
 188         }
 189         if (obj->stolen)
 190                 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
 191         if (obj->pin_display || obj->fault_mappable) {
 192                 char s[3], *t = s;
 193                 if (obj->pin_display)
 194                         *t++ = 'p';
 195                 if (obj->fault_mappable)
 196                         *t++ = 'f';
 197                 *t = '\0';
 198                 seq_printf(m, " (%s mappable)", s);
 199         }
 200
 201         engine = i915_gem_active_get_engine(&obj->last_write,
 202                                             &dev_priv->drm.struct_mutex);
 203         if (engine)
 204                 seq_printf(m, " (%s)", engine->name);
 205
 206         frontbuffer_bits = atomic_read(&obj->frontbuffer_bits);
 207         if (frontbuffer_bits)
 208                 seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits);
 209 }
 210
 211 static int obj_rank_by_stolen(void *priv,
 212                               struct list_head *A, struct list_head *B)
 213 {
 214         struct drm_i915_gem_object *a =
 215                 container_of(A, struct drm_i915_gem_object, obj_exec_link);
 216         struct drm_i915_gem_object *b =
 217                 container_of(B, struct drm_i915_gem_object, obj_exec_link);
 218
 219         if (a->stolen->start < b->stolen->start)
 220                 return -1;
 221         if (a->stolen->start > b->stolen->start)
 222                 return 1;
 223         return 0;
 224 }
 225
 226 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
 227 {
 228         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 229         struct drm_device *dev = &dev_priv->drm;
 230         struct drm_i915_gem_object *obj;
 231         u64 total_obj_size, total_gtt_size;
 232         LIST_HEAD(stolen);
 233         int count, ret;
 234
 235         ret = mutex_lock_interruptible(&dev->struct_mutex);
 236         if (ret)
 237                 return ret;
 238
 239         total_obj_size = total_gtt_size = count = 0;
 240         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 241                 if (obj->stolen == NULL)
 242                         continue;
 243
 244                 list_add(&obj->obj_exec_link, &stolen);
 245
 246                 total_obj_size += obj->base.size;
 247                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 248                 count++;
 249         }
 250         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 251                 if (obj->stolen == NULL)
 252                         continue;
 253
 254                 list_add(&obj->obj_exec_link, &stolen);
 255
 256                 total_obj_size += obj->base.size;
 257                 count++;
 258         }
 259         list_sort(NULL, &stolen, obj_rank_by_stolen);
 260         seq_puts(m, "Stolen:\n");
 261         while (!list_empty(&stolen)) {
 262                 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
 263                 seq_puts(m, "   ");
 264                 describe_obj(m, obj);
 265                 seq_putc(m, '\n');
 266                 list_del_init(&obj->obj_exec_link);
 267         }
 268         mutex_unlock(&dev->struct_mutex);
 269
 270         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 271                    count, total_obj_size, total_gtt_size);
 272         return 0;
 273 }
 274
 275 struct file_stats {
 276         struct drm_i915_file_private *file_priv;
 277         unsigned long count;
 278         u64 total, unbound;
 279         u64 global, shared;
 280         u64 active, inactive;
 281 };
 282
 283 static int per_file_stats(int id, void *ptr, void *data)
 284 {
 285         struct drm_i915_gem_object *obj = ptr;
 286         struct file_stats *stats = data;
 287         struct i915_vma *vma;
 288
 289         stats->count++;
 290         stats->total += obj->base.size;
 291         if (!obj->bind_count)
 292                 stats->unbound += obj->base.size;
 293         if (obj->base.name || obj->base.dma_buf)
 294                 stats->shared += obj->base.size;
 295
 296         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 297                 if (!drm_mm_node_allocated(&vma->node))
 298                         continue;
 299
 300                 if (i915_vma_is_ggtt(vma)) {
 301                         stats->global += vma->node.size;
 302                 } else {
 303                         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm);
 304
 305                         if (ppgtt->base.file != stats->file_priv)
 306                                 continue;
 307                 }
 308
 309                 if (i915_vma_is_active(vma))
 310                         stats->active += vma->node.size;
 311                 else
 312                         stats->inactive += vma->node.size;
 313         }
 314
 315         return 0;
 316 }
 317
 318 #define print_file_stats(m, name, stats) do { \
 319         if (stats.count) \
 320                 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
 321                            name, \
 322                            stats.count, \
 323                            stats.total, \
 324                            stats.active, \
 325                            stats.inactive, \
 326                            stats.global, \
 327                            stats.shared, \
 328                            stats.unbound); \
 329 } while (0)
 330
 331 static void print_batch_pool_stats(struct seq_file *m,
 332                                    struct drm_i915_private *dev_priv)
 333 {
 334         struct drm_i915_gem_object *obj;
 335         struct file_stats stats;
 336         struct intel_engine_cs *engine;
 337         int j;
 338
 339         memset(&stats, 0, sizeof(stats));
 340
 341         for_each_engine(engine, dev_priv) {
 342                 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
 343                         list_for_each_entry(obj,
 344                                             &engine->batch_pool.cache_list[j],
 345                                             batch_pool_link)
 346                                 per_file_stats(0, obj, &stats);
 347                 }
 348         }
 349
 350         print_file_stats(m, "[k]batch pool", stats);
 351 }
 352
 353 static int per_file_ctx_stats(int id, void *ptr, void *data)
 354 {
 355         struct i915_gem_context *ctx = ptr;
 356         int n;
 357
 358         for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) {
 359                 if (ctx->engine[n].state)
 360                         per_file_stats(0, ctx->engine[n].state->obj, data);
 361                 if (ctx->engine[n].ring)
 362                         per_file_stats(0, ctx->engine[n].ring->vma->obj, data);
 363         }
 364
 365         return 0;
 366 }
 367
 368 static void print_context_stats(struct seq_file *m,
 369                                 struct drm_i915_private *dev_priv)
 370 {
 371         struct drm_device *dev = &dev_priv->drm;
 372         struct file_stats stats;
 373         struct drm_file *file;
 374
 375         memset(&stats, 0, sizeof(stats));
 376
 377         mutex_lock(&dev->struct_mutex);
 378         if (dev_priv->kernel_context)
 379                 per_file_ctx_stats(0, dev_priv->kernel_context, &stats);
 380
 381         list_for_each_entry(file, &dev->filelist, lhead) {
 382                 struct drm_i915_file_private *fpriv = file->driver_priv;
 383                 idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats);
 384         }
 385         mutex_unlock(&dev->struct_mutex);
 386
 387         print_file_stats(m, "[k]contexts", stats);
 388 }
 389
 390 static int i915_gem_object_info(struct seq_file *m, void *data)
 391 {
 392         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 393         struct drm_device *dev = &dev_priv->drm;
 394         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 395         u32 count, mapped_count, purgeable_count, dpy_count;
 396         u64 size, mapped_size, purgeable_size, dpy_size;
 397         struct drm_i915_gem_object *obj;
 398         struct drm_file *file;
 399         int ret;
 400
 401         ret = mutex_lock_interruptible(&dev->struct_mutex);
 402         if (ret)
 403                 return ret;
 404
 405         seq_printf(m, "%u objects, %zu bytes\n",
 406                    dev_priv->mm.object_count,
 407                    dev_priv->mm.object_memory);
 408
 409         size = count = 0;
 410         mapped_size = mapped_count = 0;
 411         purgeable_size = purgeable_count = 0;
 412         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 413                 size += obj->base.size;
 414                 ++count;
 415
 416                 if (obj->madv == I915_MADV_DONTNEED) {
 417                         purgeable_size += obj->base.size;
 418                         ++purgeable_count;
 419                 }
 420
 421                 if (obj->mapping) {
 422                         mapped_count++;
 423                         mapped_size += obj->base.size;
 424                 }
 425         }
 426         seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
 427
 428         size = count = dpy_size = dpy_count = 0;
 429         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 430                 size += obj->base.size;
 431                 ++count;
 432
 433                 if (obj->pin_display) {
 434                         dpy_size += obj->base.size;
 435                         ++dpy_count;
 436                 }
 437
 438                 if (obj->madv == I915_MADV_DONTNEED) {
 439                         purgeable_size += obj->base.size;
 440                         ++purgeable_count;
 441                 }
 442
 443                 if (obj->mapping) {
 444                         mapped_count++;
 445                         mapped_size += obj->base.size;
 446                 }
 447         }
 448         seq_printf(m, "%u bound objects, %llu bytes\n",
 449                    count, size);
 450         seq_printf(m, "%u purgeable objects, %llu bytes\n",
 451                    purgeable_count, purgeable_size);
 452         seq_printf(m, "%u mapped objects, %llu bytes\n",
 453                    mapped_count, mapped_size);
 454         seq_printf(m, "%u display objects (pinned), %llu bytes\n",
 455                    dpy_count, dpy_size);
 456
 457         seq_printf(m, "%llu [%llu] gtt total\n",
 458                    ggtt->base.total, ggtt->mappable_end - ggtt->base.start);
 459
 460         seq_putc(m, '\n');
 461         print_batch_pool_stats(m, dev_priv);
 462         mutex_unlock(&dev->struct_mutex);
 463
 464         mutex_lock(&dev->filelist_mutex);
 465         print_context_stats(m, dev_priv);
 466         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
 467                 struct file_stats stats;
 468                 struct drm_i915_file_private *file_priv = file->driver_priv;
 469                 struct drm_i915_gem_request *request;
 470                 struct task_struct *task;
 471
 472                 memset(&stats, 0, sizeof(stats));
 473                 stats.file_priv = file->driver_priv;
 474                 spin_lock(&file->table_lock);
 475                 idr_for_each(&file->object_idr, per_file_stats, &stats);
 476                 spin_unlock(&file->table_lock);
 477                 /*
 478                  * Although we have a valid reference on file->pid, that does
 479                  * not guarantee that the task_struct who called get_pid() is
 480                  * still alive (e.g. get_pid(current) => fork() => exit()).
 481                  * Therefore, we need to protect this ->comm access using RCU.
 482                  */
 483                 mutex_lock(&dev->struct_mutex);
 484                 request = list_first_entry_or_null(&file_priv->mm.request_list,
 485                                                    struct drm_i915_gem_request,
 486                                                    client_list);
 487                 rcu_read_lock();
 488                 task = pid_task(request && request->ctx->pid ?
 489                                 request->ctx->pid : file->pid,
 490                                 PIDTYPE_PID);
 491                 print_file_stats(m, task ? task->comm : "<unknown>", stats);
 492                 rcu_read_unlock();
 493                 mutex_unlock(&dev->struct_mutex);
 494         }
 495         mutex_unlock(&dev->filelist_mutex);
 496
 497         return 0;
 498 }
 499
 500 static int i915_gem_gtt_info(struct seq_file *m, void *data)
 501 {
 502         struct drm_info_node *node = m->private;
 503         struct drm_i915_private *dev_priv = node_to_i915(node);
 504         struct drm_device *dev = &dev_priv->drm;
 505         bool show_pin_display_only = !!node->info_ent->data;
 506         struct drm_i915_gem_object *obj;
 507         u64 total_obj_size, total_gtt_size;
 508         int count, ret;
 509
 510         ret = mutex_lock_interruptible(&dev->struct_mutex);
 511         if (ret)
 512                 return ret;
 513
 514         total_obj_size = total_gtt_size = count = 0;
 515         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 516                 if (show_pin_display_only && !obj->pin_display)
 517                         continue;
 518
 519                 seq_puts(m, "   ");
 520                 describe_obj(m, obj);
 521                 seq_putc(m, '\n');
 522                 total_obj_size += obj->base.size;
 523                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 524                 count++;
 525         }
 526
 527         mutex_unlock(&dev->struct_mutex);
 528
 529         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 530                    count, total_obj_size, total_gtt_size);
 531
 532         return 0;
 533 }
 534
 535 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
 536 {
 537         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 538         struct drm_device *dev = &dev_priv->drm;
 539         struct intel_crtc *crtc;
 540         int ret;
 541
 542         ret = mutex_lock_interruptible(&dev->struct_mutex);
 543         if (ret)
 544                 return ret;
 545
 546         for_each_intel_crtc(dev, crtc) {
 547                 const char pipe = pipe_name(crtc->pipe);
 548                 const char plane = plane_name(crtc->plane);
 549                 struct intel_flip_work *work;
 550
 551                 spin_lock_irq(&dev->event_lock);
 552                 work = crtc->flip_work;
 553                 if (work == NULL) {
 554                         seq_printf(m, "No flip due on pipe %c (plane %c)\n",
 555                                    pipe, plane);
 556                 } else {
 557                         u32 pending;
 558                         u32 addr;
 559
 560                         pending = atomic_read(&work->pending);
 561                         if (pending) {
 562                                 seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n",
 563                                            pipe, plane);
 564                         } else {
 565                                 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
 566                                            pipe, plane);
 567                         }
 568                         if (work->flip_queued_req) {
 569                                 struct intel_engine_cs *engine = i915_gem_request_get_engine(work->flip_queued_req);
 570
 571                                 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
 572                                            engine->name,
 573                                            i915_gem_request_get_seqno(work->flip_queued_req),
 574                                            dev_priv->next_seqno,
 575                                            intel_engine_get_seqno(engine),
 576                                            i915_gem_request_completed(work->flip_queued_req));
 577                         } else
 578                                 seq_printf(m, "Flip not associated with any ring\n");
 579                         seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
 580                                    work->flip_queued_vblank,
 581                                    work->flip_ready_vblank,
 582                                    intel_crtc_get_vblank_counter(crtc));
 583                         seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
 584
 585                         if (INTEL_GEN(dev_priv) >= 4)
 586                                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
 587                         else
 588                                 addr = I915_READ(DSPADDR(crtc->plane));
 589                         seq_printf(m, "Current scanout address 0x%08x\n", addr);
 590
 591                         if (work->pending_flip_obj) {
 592                                 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
 593                                 seq_printf(m, "MMIO update completed? %d\n",  addr == work->gtt_offset);
 594                         }
 595                 }
 596                 spin_unlock_irq(&dev->event_lock);
 597         }
 598
 599         mutex_unlock(&dev->struct_mutex);
 600
 601         return 0;
 602 }
 603
 604 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
 605 {
 606         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 607         struct drm_device *dev = &dev_priv->drm;
 608         struct drm_i915_gem_object *obj;
 609         struct intel_engine_cs *engine;
 610         int total = 0;
 611         int ret, j;
 612
 613         ret = mutex_lock_interruptible(&dev->struct_mutex);
 614         if (ret)
 615                 return ret;
 616
 617         for_each_engine(engine, dev_priv) {
 618                 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
 619                         int count;
 620
 621                         count = 0;
 622                         list_for_each_entry(obj,
 623                                             &engine->batch_pool.cache_list[j],
 624                                             batch_pool_link)
 625                                 count++;
 626                         seq_printf(m, "%s cache[%d]: %d objects\n",
 627                                    engine->name, j, count);
 628
 629                         list_for_each_entry(obj,
 630                                             &engine->batch_pool.cache_list[j],
 631                                             batch_pool_link) {
 632                                 seq_puts(m, "   ");
 633                                 describe_obj(m, obj);
 634                                 seq_putc(m, '\n');
 635                         }
 636
 637                         total += count;
 638                 }
 639         }
 640
 641         seq_printf(m, "total: %d\n", total);
 642
 643         mutex_unlock(&dev->struct_mutex);
 644
 645         return 0;
 646 }
 647
 648 static int i915_gem_request_info(struct seq_file *m, void *data)
 649 {
 650         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 651         struct drm_device *dev = &dev_priv->drm;
 652         struct intel_engine_cs *engine;
 653         struct drm_i915_gem_request *req;
 654         int ret, any;
 655
 656         ret = mutex_lock_interruptible(&dev->struct_mutex);
 657         if (ret)
 658                 return ret;
 659
 660         any = 0;
 661         for_each_engine(engine, dev_priv) {
 662                 int count;
 663
 664                 count = 0;
 665                 list_for_each_entry(req, &engine->request_list, link)
 666                         count++;
 667                 if (count == 0)
 668                         continue;
 669
 670                 seq_printf(m, "%s requests: %d\n", engine->name, count);
 671                 list_for_each_entry(req, &engine->request_list, link) {
 672                         struct pid *pid = req->ctx->pid;
 673                         struct task_struct *task;
 674
 675                         rcu_read_lock();
 676                         task = pid ? pid_task(pid, PIDTYPE_PID) : NULL;
 677                         seq_printf(m, "    %x @ %d: %s [%d]\n",
 678                                    req->fence.seqno,
 679                                    (int) (jiffies - req->emitted_jiffies),
 680                                    task ? task->comm : "<unknown>",
 681                                    task ? task->pid : -1);
 682                         rcu_read_unlock();
 683                 }
 684
 685                 any++;
 686         }
 687         mutex_unlock(&dev->struct_mutex);
 688
 689         if (any == 0)
 690                 seq_puts(m, "No requests\n");
 691
 692         return 0;
 693 }
 694
 695 static void i915_ring_seqno_info(struct seq_file *m,
 696                                  struct intel_engine_cs *engine)
 697 {
 698         struct intel_breadcrumbs *b = &engine->breadcrumbs;
 699         struct rb_node *rb;
 700
 701         seq_printf(m, "Current sequence (%s): %x\n",
 702                    engine->name, intel_engine_get_seqno(engine));
 703
 704         spin_lock(&b->lock);
 705         for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
 706                 struct intel_wait *w = container_of(rb, typeof(*w), node);
 707
 708                 seq_printf(m, "Waiting (%s): %s [%d] on %x\n",
 709                            engine->name, w->tsk->comm, w->tsk->pid, w->seqno);
 710         }
 711         spin_unlock(&b->lock);
 712 }
 713
 714 static int i915_gem_seqno_info(struct seq_file *m, void *data)
 715 {
 716         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 717         struct drm_device *dev = &dev_priv->drm;
 718         struct intel_engine_cs *engine;
 719         int ret;
 720
 721         ret = mutex_lock_interruptible(&dev->struct_mutex);
 722         if (ret)
 723                 return ret;
 724         intel_runtime_pm_get(dev_priv);
 725
 726         for_each_engine(engine, dev_priv)
 727                 i915_ring_seqno_info(m, engine);
 728
 729         intel_runtime_pm_put(dev_priv);
 730         mutex_unlock(&dev->struct_mutex);
 731
 732         return 0;
 733 }
 734
 735
 736 static int i915_interrupt_info(struct seq_file *m, void *data)
 737 {
 738         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 739         struct drm_device *dev = &dev_priv->drm;
 740         struct intel_engine_cs *engine;
 741         int ret, i, pipe;
 742
 743         ret = mutex_lock_interruptible(&dev->struct_mutex);
 744         if (ret)
 745                 return ret;
 746         intel_runtime_pm_get(dev_priv);
 747
 748         if (IS_CHERRYVIEW(dev_priv)) {
 749                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 750                            I915_READ(GEN8_MASTER_IRQ));
 751
 752                 seq_printf(m, "Display IER:\t%08x\n",
 753                            I915_READ(VLV_IER));
 754                 seq_printf(m, "Display IIR:\t%08x\n",
 755                            I915_READ(VLV_IIR));
 756                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 757                            I915_READ(VLV_IIR_RW));
 758                 seq_printf(m, "Display IMR:\t%08x\n",
 759                            I915_READ(VLV_IMR));
 760                 for_each_pipe(dev_priv, pipe)
 761                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 762                                    pipe_name(pipe),
 763                                    I915_READ(PIPESTAT(pipe)));
 764
 765                 seq_printf(m, "Port hotplug:\t%08x\n",
 766                            I915_READ(PORT_HOTPLUG_EN));
 767                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 768                            I915_READ(VLV_DPFLIPSTAT));
 769                 seq_printf(m, "DPINVGTT:\t%08x\n",
 770                            I915_READ(DPINVGTT));
 771
 772                 for (i = 0; i < 4; i++) {
 773                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 774                                    i, I915_READ(GEN8_GT_IMR(i)));
 775                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 776                                    i, I915_READ(GEN8_GT_IIR(i)));
 777                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 778                                    i, I915_READ(GEN8_GT_IER(i)));
 779                 }
 780
 781                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 782                            I915_READ(GEN8_PCU_IMR));
 783                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 784                            I915_READ(GEN8_PCU_IIR));
 785                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 786                            I915_READ(GEN8_PCU_IER));
 787         } else if (INTEL_GEN(dev_priv) >= 8) {
 788                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 789                            I915_READ(GEN8_MASTER_IRQ));
 790
 791                 for (i = 0; i < 4; i++) {
 792                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 793                                    i, I915_READ(GEN8_GT_IMR(i)));
 794                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 795                                    i, I915_READ(GEN8_GT_IIR(i)));
 796                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 797                                    i, I915_READ(GEN8_GT_IER(i)));
 798                 }
 799
 800                 for_each_pipe(dev_priv, pipe) {
 801                         enum intel_display_power_domain power_domain;
 802
 803                         power_domain = POWER_DOMAIN_PIPE(pipe);
 804                         if (!intel_display_power_get_if_enabled(dev_priv,
 805                                                                 power_domain)) {
 806                                 seq_printf(m, "Pipe %c power disabled\n",
 807                                            pipe_name(pipe));
 808                                 continue;
 809                         }
 810                         seq_printf(m, "Pipe %c IMR:\t%08x\n",
 811                                    pipe_name(pipe),
 812                                    I915_READ(GEN8_DE_PIPE_IMR(pipe)));
 813                         seq_printf(m, "Pipe %c IIR:\t%08x\n",
 814                                    pipe_name(pipe),
 815                                    I915_READ(GEN8_DE_PIPE_IIR(pipe)));
 816                         seq_printf(m, "Pipe %c IER:\t%08x\n",
 817                                    pipe_name(pipe),
 818                                    I915_READ(GEN8_DE_PIPE_IER(pipe)));
 819
 820                         intel_display_power_put(dev_priv, power_domain);
 821                 }
 822
 823                 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
 824                            I915_READ(GEN8_DE_PORT_IMR));
 825                 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
 826                            I915_READ(GEN8_DE_PORT_IIR));
 827                 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
 828                            I915_READ(GEN8_DE_PORT_IER));
 829
 830                 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
 831                            I915_READ(GEN8_DE_MISC_IMR));
 832                 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
 833                            I915_READ(GEN8_DE_MISC_IIR));
 834                 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
 835                            I915_READ(GEN8_DE_MISC_IER));
 836
 837                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 838                            I915_READ(GEN8_PCU_IMR));
 839                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 840                            I915_READ(GEN8_PCU_IIR));
 841                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 842                            I915_READ(GEN8_PCU_IER));
 843         } else if (IS_VALLEYVIEW(dev_priv)) {
 844                 seq_printf(m, "Display IER:\t%08x\n",
 845                            I915_READ(VLV_IER));
 846                 seq_printf(m, "Display IIR:\t%08x\n",
 847                            I915_READ(VLV_IIR));
 848                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 849                            I915_READ(VLV_IIR_RW));
 850                 seq_printf(m, "Display IMR:\t%08x\n",
 851                            I915_READ(VLV_IMR));
 852                 for_each_pipe(dev_priv, pipe)
 853                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 854                                    pipe_name(pipe),
 855                                    I915_READ(PIPESTAT(pipe)));
 856
 857                 seq_printf(m, "Master IER:\t%08x\n",
 858                            I915_READ(VLV_MASTER_IER));
 859
 860                 seq_printf(m, "Render IER:\t%08x\n",
 861                            I915_READ(GTIER));
 862                 seq_printf(m, "Render IIR:\t%08x\n",
 863                            I915_READ(GTIIR));
 864                 seq_printf(m, "Render IMR:\t%08x\n",
 865                            I915_READ(GTIMR));
 866
 867                 seq_printf(m, "PM IER:\t\t%08x\n",
 868                            I915_READ(GEN6_PMIER));
 869                 seq_printf(m, "PM IIR:\t\t%08x\n",
 870                            I915_READ(GEN6_PMIIR));
 871                 seq_printf(m, "PM IMR:\t\t%08x\n",
 872                            I915_READ(GEN6_PMIMR));
 873
 874                 seq_printf(m, "Port hotplug:\t%08x\n",
 875                            I915_READ(PORT_HOTPLUG_EN));
 876                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 877                            I915_READ(VLV_DPFLIPSTAT));
 878                 seq_printf(m, "DPINVGTT:\t%08x\n",
 879                            I915_READ(DPINVGTT));
 880
 881         } else if (!HAS_PCH_SPLIT(dev_priv)) {
 882                 seq_printf(m, "Interrupt enable:    %08x\n",
 883                            I915_READ(IER));
 884                 seq_printf(m, "Interrupt identity:  %08x\n",
 885                            I915_READ(IIR));
 886                 seq_printf(m, "Interrupt mask:      %08x\n",
 887                            I915_READ(IMR));
 888                 for_each_pipe(dev_priv, pipe)
 889                         seq_printf(m, "Pipe %c stat:         %08x\n",
 890                                    pipe_name(pipe),
 891                                    I915_READ(PIPESTAT(pipe)));
 892         } else {
 893                 seq_printf(m, "North Display Interrupt enable:          %08x\n",
 894                            I915_READ(DEIER));
 895                 seq_printf(m, "North Display Interrupt identity:        %08x\n",
 896                            I915_READ(DEIIR));
 897                 seq_printf(m, "North Display Interrupt mask:            %08x\n",
 898                            I915_READ(DEIMR));
 899                 seq_printf(m, "South Display Interrupt enable:          %08x\n",
 900                            I915_READ(SDEIER));
 901                 seq_printf(m, "South Display Interrupt identity:        %08x\n",
 902                            I915_READ(SDEIIR));
 903                 seq_printf(m, "South Display Interrupt mask:            %08x\n",
 904                            I915_READ(SDEIMR));
 905                 seq_printf(m, "Graphics Interrupt enable:               %08x\n",
 906                            I915_READ(GTIER));
 907                 seq_printf(m, "Graphics Interrupt identity:             %08x\n",
 908                            I915_READ(GTIIR));
 909                 seq_printf(m, "Graphics Interrupt mask:         %08x\n",
 910                            I915_READ(GTIMR));
 911         }
 912         for_each_engine(engine, dev_priv) {
 913                 if (INTEL_GEN(dev_priv) >= 6) {
 914                         seq_printf(m,
 915                                    "Graphics Interrupt mask (%s):       %08x\n",
 916                                    engine->name, I915_READ_IMR(engine));
 917                 }
 918                 i915_ring_seqno_info(m, engine);
 919         }
 920         intel_runtime_pm_put(dev_priv);
 921         mutex_unlock(&dev->struct_mutex);
 922
 923         return 0;
 924 }
 925
 926 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
 927 {
 928         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 929         struct drm_device *dev = &dev_priv->drm;
 930         int i, ret;
 931
 932         ret = mutex_lock_interruptible(&dev->struct_mutex);
 933         if (ret)
 934                 return ret;
 935
 936         seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
 937         for (i = 0; i < dev_priv->num_fence_regs; i++) {
 938                 struct i915_vma *vma = dev_priv->fence_regs[i].vma;
 939
 940                 seq_printf(m, "Fence %d, pin count = %d, object = ",
 941                            i, dev_priv->fence_regs[i].pin_count);
 942                 if (!vma)
 943                         seq_puts(m, "unused");
 944                 else
 945                         describe_obj(m, vma->obj);
 946                 seq_putc(m, '\n');
 947         }
 948
 949         mutex_unlock(&dev->struct_mutex);
 950         return 0;
 951 }
 952
 953 static int i915_hws_info(struct seq_file *m, void *data)
 954 {
 955         struct drm_info_node *node = m->private;
 956         struct drm_i915_private *dev_priv = node_to_i915(node);
 957         struct intel_engine_cs *engine;
 958         const u32 *hws;
 959         int i;
 960
 961         engine = &dev_priv->engine[(uintptr_t)node->info_ent->data];
 962         hws = engine->status_page.page_addr;
 963         if (hws == NULL)
 964                 return 0;
 965
 966         for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
 967                 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
 968                            i * 4,
 969                            hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
 970         }
 971         return 0;
 972 }
 973
 974 static ssize_t
 975 i915_error_state_write(struct file *filp,
 976                        const char __user *ubuf,
 977                        size_t cnt,
 978                        loff_t *ppos)
 979 {
 980         struct i915_error_state_file_priv *error_priv = filp->private_data;
 981
 982         DRM_DEBUG_DRIVER("Resetting error state\n");
 983         i915_destroy_error_state(error_priv->dev);
 984
 985         return cnt;
 986 }
 987
 988 static int i915_error_state_open(struct inode *inode, struct file *file)
 989 {
 990         struct drm_i915_private *dev_priv = inode->i_private;
 991         struct i915_error_state_file_priv *error_priv;
 992
 993         error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
 994         if (!error_priv)
 995                 return -ENOMEM;
 996
 997         error_priv->dev = &dev_priv->drm;
 998
 999         i915_error_state_get(&dev_priv->drm, error_priv);
1000
1001         file->private_data = error_priv;
1002
1003         return 0;
1004 }
1005
1006 static int i915_error_state_release(struct inode *inode, struct file *file)
1007 {
1008         struct i915_error_state_file_priv *error_priv = file->private_data;
1009
1010         i915_error_state_put(error_priv);
1011         kfree(error_priv);
1012
1013         return 0;
1014 }
1015
1016 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1017                                      size_t count, loff_t *pos)
1018 {
1019         struct i915_error_state_file_priv *error_priv = file->private_data;
1020         struct drm_i915_error_state_buf error_str;
1021         loff_t tmp_pos = 0;
1022         ssize_t ret_count = 0;
1023         int ret;
1024
1025         ret = i915_error_state_buf_init(&error_str,
1026                                         to_i915(error_priv->dev), count, *pos);
1027         if (ret)
1028                 return ret;
1029
1030         ret = i915_error_state_to_str(&error_str, error_priv);
1031         if (ret)
1032                 goto out;
1033
1034         ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1035                                             error_str.buf,
1036                                             error_str.bytes);
1037
1038         if (ret_count < 0)
1039                 ret = ret_count;
1040         else
1041                 *pos = error_str.start + ret_count;
1042 out:
1043         i915_error_state_buf_release(&error_str);
1044         return ret ?: ret_count;
1045 }
1046
1047 static const struct file_operations i915_error_state_fops = {
1048         .owner = THIS_MODULE,
1049         .open = i915_error_state_open,
1050         .read = i915_error_state_read,
1051         .write = i915_error_state_write,
1052         .llseek = default_llseek,
1053         .release = i915_error_state_release,
1054 };
1055
1056 static int
1057 i915_next_seqno_get(void *data, u64 *val)
1058 {
1059         struct drm_i915_private *dev_priv = data;
1060         int ret;
1061
1062         ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
1063         if (ret)
1064                 return ret;
1065
1066         *val = dev_priv->next_seqno;
1067         mutex_unlock(&dev_priv->drm.struct_mutex);
1068
1069         return 0;
1070 }
1071
1072 static int
1073 i915_next_seqno_set(void *data, u64 val)
1074 {
1075         struct drm_i915_private *dev_priv = data;
1076         struct drm_device *dev = &dev_priv->drm;
1077         int ret;
1078
1079         ret = mutex_lock_interruptible(&dev->struct_mutex);
1080         if (ret)
1081                 return ret;
1082
1083         ret = i915_gem_set_seqno(dev, val);
1084         mutex_unlock(&dev->struct_mutex);
1085
1086         return ret;
1087 }
1088
1089 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1090                         i915_next_seqno_get, i915_next_seqno_set,
1091                         "0x%llx\n");
1092
1093 static int i915_frequency_info(struct seq_file *m, void *unused)
1094 {
1095         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1096         struct drm_device *dev = &dev_priv->drm;
1097         int ret = 0;
1098
1099         intel_runtime_pm_get(dev_priv);
1100
1101         if (IS_GEN5(dev_priv)) {
1102                 u16 rgvswctl = I915_READ16(MEMSWCTL);
1103                 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1104
1105                 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1106                 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1107                 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1108                            MEMSTAT_VID_SHIFT);
1109                 seq_printf(m, "Current P-state: %d\n",
1110                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1111         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1112                 u32 freq_sts;
1113
1114                 mutex_lock(&dev_priv->rps.hw_lock);
1115                 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1116                 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1117                 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1118
1119                 seq_printf(m, "actual GPU freq: %d MHz\n",
1120                            intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1121
1122                 seq_printf(m, "current GPU freq: %d MHz\n",
1123                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1124
1125                 seq_printf(m, "max GPU freq: %d MHz\n",
1126                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1127
1128                 seq_printf(m, "min GPU freq: %d MHz\n",
1129                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1130
1131                 seq_printf(m, "idle GPU freq: %d MHz\n",
1132                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1133
1134                 seq_printf(m,
1135                            "efficient (RPe) frequency: %d MHz\n",
1136                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1137                 mutex_unlock(&dev_priv->rps.hw_lock);
1138         } else if (INTEL_GEN(dev_priv) >= 6) {
1139                 u32 rp_state_limits;
1140                 u32 gt_perf_status;
1141                 u32 rp_state_cap;
1142                 u32 rpmodectl, rpinclimit, rpdeclimit;
1143                 u32 rpstat, cagf, reqf;
1144                 u32 rpupei, rpcurup, rpprevup;
1145                 u32 rpdownei, rpcurdown, rpprevdown;
1146                 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1147                 int max_freq;
1148
1149                 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1150                 if (IS_BROXTON(dev_priv)) {
1151                         rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1152                         gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1153                 } else {
1154                         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1155                         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1156                 }
1157
1158                 /* RPSTAT1 is in the GT power well */
1159                 ret = mutex_lock_interruptible(&dev->struct_mutex);
1160                 if (ret)
1161                         goto out;
1162
1163                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1164
1165                 reqf = I915_READ(GEN6_RPNSWREQ);
1166                 if (IS_GEN9(dev_priv))
1167                         reqf >>= 23;
1168                 else {
1169                         reqf &= ~GEN6_TURBO_DISABLE;
1170                         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1171                                 reqf >>= 24;
1172                         else
1173                                 reqf >>= 25;
1174                 }
1175                 reqf = intel_gpu_freq(dev_priv, reqf);
1176
1177                 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1178                 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1179                 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1180
1181                 rpstat = I915_READ(GEN6_RPSTAT1);
1182                 rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
1183                 rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
1184                 rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
1185                 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
1186                 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
1187                 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
1188                 if (IS_GEN9(dev_priv))
1189                         cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1190                 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1191                         cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1192                 else
1193                         cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1194                 cagf = intel_gpu_freq(dev_priv, cagf);
1195
1196                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1197                 mutex_unlock(&dev->struct_mutex);
1198
1199                 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
1200                         pm_ier = I915_READ(GEN6_PMIER);
1201                         pm_imr = I915_READ(GEN6_PMIMR);
1202                         pm_isr = I915_READ(GEN6_PMISR);
1203                         pm_iir = I915_READ(GEN6_PMIIR);
1204                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1205                 } else {
1206                         pm_ier = I915_READ(GEN8_GT_IER(2));
1207                         pm_imr = I915_READ(GEN8_GT_IMR(2));
1208                         pm_isr = I915_READ(GEN8_GT_ISR(2));
1209                         pm_iir = I915_READ(GEN8_GT_IIR(2));
1210                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1211                 }
1212                 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1213                            pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1214                 seq_printf(m, "pm_intr_keep: 0x%08x\n", dev_priv->rps.pm_intr_keep);
1215                 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1216                 seq_printf(m, "Render p-state ratio: %d\n",
1217                            (gt_perf_status & (IS_GEN9(dev_priv) ? 0x1ff00 : 0xff00)) >> 8);
1218                 seq_printf(m, "Render p-state VID: %d\n",
1219                            gt_perf_status & 0xff);
1220                 seq_printf(m, "Render p-state limit: %d\n",
1221                            rp_state_limits & 0xff);
1222                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1223                 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1224                 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1225                 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1226                 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1227                 seq_printf(m, "CAGF: %dMHz\n", cagf);
1228                 seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
1229                            rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei));
1230                 seq_printf(m, "RP CUR UP: %d (%dus)\n",
1231                            rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
1232                 seq_printf(m, "RP PREV UP: %d (%dus)\n",
1233                            rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
1234                 seq_printf(m, "Up threshold: %d%%\n",
1235                            dev_priv->rps.up_threshold);
1236
1237                 seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
1238                            rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
1239                 seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
1240                            rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown));
1241                 seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
1242                            rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown));
1243                 seq_printf(m, "Down threshold: %d%%\n",
1244                            dev_priv->rps.down_threshold);
1245
1246                 max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 0 :
1247                             rp_state_cap >> 16) & 0xff;
1248                 max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1249                              GEN9_FREQ_SCALER : 1);
1250                 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1251                            intel_gpu_freq(dev_priv, max_freq));
1252
1253                 max_freq = (rp_state_cap & 0xff00) >> 8;
1254                 max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1255                              GEN9_FREQ_SCALER : 1);
1256                 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1257                            intel_gpu_freq(dev_priv, max_freq));
1258
1259                 max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 16 :
1260                             rp_state_cap >> 0) & 0xff;
1261                 max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1262                              GEN9_FREQ_SCALER : 1);
1263                 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1264                            intel_gpu_freq(dev_priv, max_freq));
1265                 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1266                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1267
1268                 seq_printf(m, "Current freq: %d MHz\n",
1269                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1270                 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1271                 seq_printf(m, "Idle freq: %d MHz\n",
1272                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1273                 seq_printf(m, "Min freq: %d MHz\n",
1274                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1275                 seq_printf(m, "Boost freq: %d MHz\n",
1276                            intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
1277                 seq_printf(m, "Max freq: %d MHz\n",
1278                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1279                 seq_printf(m,
1280                            "efficient (RPe) frequency: %d MHz\n",
1281                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1282         } else {
1283                 seq_puts(m, "no P-state info available\n");
1284         }
1285
1286         seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
1287         seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1288         seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1289
1290 out:
1291         intel_runtime_pm_put(dev_priv);
1292         return ret;
1293 }
1294
1295 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1296 {
1297         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1298         struct intel_engine_cs *engine;
1299         u64 acthd[I915_NUM_ENGINES];
1300         u32 seqno[I915_NUM_ENGINES];
1301         u32 instdone[I915_NUM_INSTDONE_REG];
1302         enum intel_engine_id id;
1303         int j;
1304
1305         if (!i915.enable_hangcheck) {
1306                 seq_printf(m, "Hangcheck disabled\n");
1307                 return 0;
1308         }
1309
1310         intel_runtime_pm_get(dev_priv);
1311
1312         for_each_engine_id(engine, dev_priv, id) {
1313                 acthd[id] = intel_engine_get_active_head(engine);
1314                 seqno[id] = intel_engine_get_seqno(engine);
1315         }
1316
1317         i915_get_extra_instdone(dev_priv, instdone);
1318
1319         intel_runtime_pm_put(dev_priv);
1320
1321         if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1322                 seq_printf(m, "Hangcheck active, fires in %dms\n",
1323                            jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1324                                             jiffies));
1325         } else
1326                 seq_printf(m, "Hangcheck inactive\n");
1327
1328         for_each_engine_id(engine, dev_priv, id) {
1329                 seq_printf(m, "%s:\n", engine->name);
1330                 seq_printf(m, "\tseqno = %x [current %x, last %x]\n",
1331                            engine->hangcheck.seqno,
1332                            seqno[id],
1333                            engine->last_submitted_seqno);
1334                 seq_printf(m, "\twaiters? %s, fake irq active? %s\n",
1335                            yesno(intel_engine_has_waiter(engine)),
1336                            yesno(test_bit(engine->id,
1337                                           &dev_priv->gpu_error.missed_irq_rings)));
1338                 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1339                            (long long)engine->hangcheck.acthd,
1340                            (long long)acthd[id]);
1341                 seq_printf(m, "\tscore = %d\n", engine->hangcheck.score);
1342                 seq_printf(m, "\taction = %d\n", engine->hangcheck.action);
1343
1344                 if (engine->id == RCS) {
1345                         seq_puts(m, "\tinstdone read =");
1346
1347                         for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1348                                 seq_printf(m, " 0x%08x", instdone[j]);
1349
1350                         seq_puts(m, "\n\tinstdone accu =");
1351
1352                         for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1353                                 seq_printf(m, " 0x%08x",
1354                                            engine->hangcheck.instdone[j]);
1355
1356                         seq_puts(m, "\n");
1357                 }
1358         }
1359
1360         return 0;
1361 }
1362
1363 static int ironlake_drpc_info(struct seq_file *m)
1364 {
1365         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1366         struct drm_device *dev = &dev_priv->drm;
1367         u32 rgvmodectl, rstdbyctl;
1368         u16 crstandvid;
1369         int ret;
1370
1371         ret = mutex_lock_interruptible(&dev->struct_mutex);
1372         if (ret)
1373                 return ret;
1374         intel_runtime_pm_get(dev_priv);
1375
1376         rgvmodectl = I915_READ(MEMMODECTL);
1377         rstdbyctl = I915_READ(RSTDBYCTL);
1378         crstandvid = I915_READ16(CRSTANDVID);
1379
1380         intel_runtime_pm_put(dev_priv);
1381         mutex_unlock(&dev->struct_mutex);
1382
1383         seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1384         seq_printf(m, "Boost freq: %d\n",
1385                    (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1386                    MEMMODE_BOOST_FREQ_SHIFT);
1387         seq_printf(m, "HW control enabled: %s\n",
1388                    yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1389         seq_printf(m, "SW control enabled: %s\n",
1390                    yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1391         seq_printf(m, "Gated voltage change: %s\n",
1392                    yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1393         seq_printf(m, "Starting frequency: P%d\n",
1394                    (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1395         seq_printf(m, "Max P-state: P%d\n",
1396                    (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1397         seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1398         seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1399         seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1400         seq_printf(m, "Render standby enabled: %s\n",
1401                    yesno(!(rstdbyctl & RCX_SW_EXIT)));
1402         seq_puts(m, "Current RS state: ");
1403         switch (rstdbyctl & RSX_STATUS_MASK) {
1404         case RSX_STATUS_ON:
1405                 seq_puts(m, "on\n");
1406                 break;
1407         case RSX_STATUS_RC1:
1408                 seq_puts(m, "RC1\n");
1409                 break;
1410         case RSX_STATUS_RC1E:
1411                 seq_puts(m, "RC1E\n");
1412                 break;
1413         case RSX_STATUS_RS1:
1414                 seq_puts(m, "RS1\n");
1415                 break;
1416         case RSX_STATUS_RS2:
1417                 seq_puts(m, "RS2 (RC6)\n");
1418                 break;
1419         case RSX_STATUS_RS3:
1420                 seq_puts(m, "RC3 (RC6+)\n");
1421                 break;
1422         default:
1423                 seq_puts(m, "unknown\n");
1424                 break;
1425         }
1426
1427         return 0;
1428 }
1429
1430 static int i915_forcewake_domains(struct seq_file *m, void *data)
1431 {
1432         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1433         struct intel_uncore_forcewake_domain *fw_domain;
1434
1435         spin_lock_irq(&dev_priv->uncore.lock);
1436         for_each_fw_domain(fw_domain, dev_priv) {
1437                 seq_printf(m, "%s.wake_count = %u\n",
1438                            intel_uncore_forcewake_domain_to_str(fw_domain->id),
1439                            fw_domain->wake_count);
1440         }
1441         spin_unlock_irq(&dev_priv->uncore.lock);
1442
1443         return 0;
1444 }
1445
1446 static int vlv_drpc_info(struct seq_file *m)
1447 {
1448         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1449         u32 rpmodectl1, rcctl1, pw_status;
1450
1451         intel_runtime_pm_get(dev_priv);
1452
1453         pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1454         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1455         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1456
1457         intel_runtime_pm_put(dev_priv);
1458
1459         seq_printf(m, "Video Turbo Mode: %s\n",
1460                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1461         seq_printf(m, "Turbo enabled: %s\n",
1462                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1463         seq_printf(m, "HW control enabled: %s\n",
1464                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1465         seq_printf(m, "SW control enabled: %s\n",
1466                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1467                           GEN6_RP_MEDIA_SW_MODE));
1468         seq_printf(m, "RC6 Enabled: %s\n",
1469                    yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1470                                         GEN6_RC_CTL_EI_MODE(1))));
1471         seq_printf(m, "Render Power Well: %s\n",
1472                    (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1473         seq_printf(m, "Media Power Well: %s\n",
1474                    (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1475
1476         seq_printf(m, "Render RC6 residency since boot: %u\n",
1477                    I915_READ(VLV_GT_RENDER_RC6));
1478         seq_printf(m, "Media RC6 residency since boot: %u\n",
1479                    I915_READ(VLV_GT_MEDIA_RC6));
1480
1481         return i915_forcewake_domains(m, NULL);
1482 }
1483
1484 static int gen6_drpc_info(struct seq_file *m)
1485 {
1486         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1487         struct drm_device *dev = &dev_priv->drm;
1488         u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1489         u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
1490         unsigned forcewake_count;
1491         int count = 0, ret;
1492
1493         ret = mutex_lock_interruptible(&dev->struct_mutex);
1494         if (ret)
1495                 return ret;
1496         intel_runtime_pm_get(dev_priv);
1497
1498         spin_lock_irq(&dev_priv->uncore.lock);
1499         forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1500         spin_unlock_irq(&dev_priv->uncore.lock);
1501
1502         if (forcewake_count) {
1503                 seq_puts(m, "RC information inaccurate because somebody "
1504                             "holds a forcewake reference \n");
1505         } else {
1506                 /* NB: we cannot use forcewake, else we read the wrong values */
1507                 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1508                         udelay(10);
1509                 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1510         }
1511
1512         gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1513         trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1514
1515         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1516         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1517         if (INTEL_GEN(dev_priv) >= 9) {
1518                 gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE);
1519                 gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
1520         }
1521         mutex_unlock(&dev->struct_mutex);
1522         mutex_lock(&dev_priv->rps.hw_lock);
1523         sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1524         mutex_unlock(&dev_priv->rps.hw_lock);
1525
1526         intel_runtime_pm_put(dev_priv);
1527
1528         seq_printf(m, "Video Turbo Mode: %s\n",
1529                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1530         seq_printf(m, "HW control enabled: %s\n",
1531                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1532         seq_printf(m, "SW control enabled: %s\n",
1533                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1534                           GEN6_RP_MEDIA_SW_MODE));
1535         seq_printf(m, "RC1e Enabled: %s\n",
1536                    yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1537         seq_printf(m, "RC6 Enabled: %s\n",
1538                    yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1539         if (INTEL_GEN(dev_priv) >= 9) {
1540                 seq_printf(m, "Render Well Gating Enabled: %s\n",
1541                         yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
1542                 seq_printf(m, "Media Well Gating Enabled: %s\n",
1543                         yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE));
1544         }
1545         seq_printf(m, "Deep RC6 Enabled: %s\n",
1546                    yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1547         seq_printf(m, "Deepest RC6 Enabled: %s\n",
1548                    yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1549         seq_puts(m, "Current RC state: ");
1550         switch (gt_core_status & GEN6_RCn_MASK) {
1551         case GEN6_RC0:
1552                 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1553                         seq_puts(m, "Core Power Down\n");
1554                 else
1555                         seq_puts(m, "on\n");
1556                 break;
1557         case GEN6_RC3:
1558                 seq_puts(m, "RC3\n");
1559                 break;
1560         case GEN6_RC6:
1561                 seq_puts(m, "RC6\n");
1562                 break;
1563         case GEN6_RC7:
1564                 seq_puts(m, "RC7\n");
1565                 break;
1566         default:
1567                 seq_puts(m, "Unknown\n");
1568                 break;
1569         }
1570
1571         seq_printf(m, "Core Power Down: %s\n",
1572                    yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1573         if (INTEL_GEN(dev_priv) >= 9) {
1574                 seq_printf(m, "Render Power Well: %s\n",
1575                         (gen9_powergate_status &
1576                          GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
1577                 seq_printf(m, "Media Power Well: %s\n",
1578                         (gen9_powergate_status &
1579                          GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
1580         }
1581
1582         /* Not exactly sure what this is */
1583         seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1584                    I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1585         seq_printf(m, "RC6 residency since boot: %u\n",
1586                    I915_READ(GEN6_GT_GFX_RC6));
1587         seq_printf(m, "RC6+ residency since boot: %u\n",
1588                    I915_READ(GEN6_GT_GFX_RC6p));
1589         seq_printf(m, "RC6++ residency since boot: %u\n",
1590                    I915_READ(GEN6_GT_GFX_RC6pp));
1591
1592         seq_printf(m, "RC6   voltage: %dmV\n",
1593                    GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1594         seq_printf(m, "RC6+  voltage: %dmV\n",
1595                    GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1596         seq_printf(m, "RC6++ voltage: %dmV\n",
1597                    GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1598         return i915_forcewake_domains(m, NULL);
1599 }
1600
1601 static int i915_drpc_info(struct seq_file *m, void *unused)
1602 {
1603         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1604
1605         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1606                 return vlv_drpc_info(m);
1607         else if (INTEL_GEN(dev_priv) >= 6)
1608                 return gen6_drpc_info(m);
1609         else
1610                 return ironlake_drpc_info(m);
1611 }
1612
1613 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1614 {
1615         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1616
1617         seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1618                    dev_priv->fb_tracking.busy_bits);
1619
1620         seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1621                    dev_priv->fb_tracking.flip_bits);
1622
1623         return 0;
1624 }
1625
1626 static int i915_fbc_status(struct seq_file *m, void *unused)
1627 {
1628         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1629
1630         if (!HAS_FBC(dev_priv)) {
1631                 seq_puts(m, "FBC unsupported on this chipset\n");
1632                 return 0;
1633         }
1634
1635         intel_runtime_pm_get(dev_priv);
1636         mutex_lock(&dev_priv->fbc.lock);
1637
1638         if (intel_fbc_is_active(dev_priv))
1639                 seq_puts(m, "FBC enabled\n");
1640         else
1641                 seq_printf(m, "FBC disabled: %s\n",
1642                            dev_priv->fbc.no_fbc_reason);
1643
1644         if (INTEL_GEN(dev_priv) >= 7)
1645                 seq_printf(m, "Compressing: %s\n",
1646                            yesno(I915_READ(FBC_STATUS2) &
1647                                  FBC_COMPRESSION_MASK));
1648
1649         mutex_unlock(&dev_priv->fbc.lock);
1650         intel_runtime_pm_put(dev_priv);
1651
1652         return 0;
1653 }
1654
1655 static int i915_fbc_fc_get(void *data, u64 *val)
1656 {
1657         struct drm_i915_private *dev_priv = data;
1658
1659         if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1660                 return -ENODEV;
1661
1662         *val = dev_priv->fbc.false_color;
1663
1664         return 0;
1665 }
1666
1667 static int i915_fbc_fc_set(void *data, u64 val)
1668 {
1669         struct drm_i915_private *dev_priv = data;
1670         u32 reg;
1671
1672         if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1673                 return -ENODEV;
1674
1675         mutex_lock(&dev_priv->fbc.lock);
1676
1677         reg = I915_READ(ILK_DPFC_CONTROL);
1678         dev_priv->fbc.false_color = val;
1679
1680         I915_WRITE(ILK_DPFC_CONTROL, val ?
1681                    (reg | FBC_CTL_FALSE_COLOR) :
1682                    (reg & ~FBC_CTL_FALSE_COLOR));
1683
1684         mutex_unlock(&dev_priv->fbc.lock);
1685         return 0;
1686 }
1687
1688 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1689                         i915_fbc_fc_get, i915_fbc_fc_set,
1690                         "%llu\n");
1691
1692 static int i915_ips_status(struct seq_file *m, void *unused)
1693 {
1694         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1695
1696         if (!HAS_IPS(dev_priv)) {
1697                 seq_puts(m, "not supported\n");
1698                 return 0;
1699         }
1700
1701         intel_runtime_pm_get(dev_priv);
1702
1703         seq_printf(m, "Enabled by kernel parameter: %s\n",
1704                    yesno(i915.enable_ips));
1705
1706         if (INTEL_GEN(dev_priv) >= 8) {
1707                 seq_puts(m, "Currently: unknown\n");
1708         } else {
1709                 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1710                         seq_puts(m, "Currently: enabled\n");
1711                 else
1712                         seq_puts(m, "Currently: disabled\n");
1713         }
1714
1715         intel_runtime_pm_put(dev_priv);
1716
1717         return 0;
1718 }
1719
1720 static int i915_sr_status(struct seq_file *m, void *unused)
1721 {
1722         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1723         bool sr_enabled = false;
1724
1725         intel_runtime_pm_get(dev_priv);
1726
1727         if (HAS_PCH_SPLIT(dev_priv))
1728                 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1729         else if (IS_CRESTLINE(dev_priv) || IS_G4X(dev_priv) ||
1730                  IS_I945G(dev_priv) || IS_I945GM(dev_priv))
1731                 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1732         else if (IS_I915GM(dev_priv))
1733                 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1734         else if (IS_PINEVIEW(dev_priv))
1735                 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1736         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1737                 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1738
1739         intel_runtime_pm_put(dev_priv);
1740
1741         seq_printf(m, "self-refresh: %s\n",
1742                    sr_enabled ? "enabled" : "disabled");
1743
1744         return 0;
1745 }
1746
1747 static int i915_emon_status(struct seq_file *m, void *unused)
1748 {
1749         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1750         struct drm_device *dev = &dev_priv->drm;
1751         unsigned long temp, chipset, gfx;
1752         int ret;
1753
1754         if (!IS_GEN5(dev_priv))
1755                 return -ENODEV;
1756
1757         ret = mutex_lock_interruptible(&dev->struct_mutex);
1758         if (ret)
1759                 return ret;
1760
1761         temp = i915_mch_val(dev_priv);
1762         chipset = i915_chipset_val(dev_priv);
1763         gfx = i915_gfx_val(dev_priv);
1764         mutex_unlock(&dev->struct_mutex);
1765
1766         seq_printf(m, "GMCH temp: %ld\n", temp);
1767         seq_printf(m, "Chipset power: %ld\n", chipset);
1768         seq_printf(m, "GFX power: %ld\n", gfx);
1769         seq_printf(m, "Total power: %ld\n", chipset + gfx);
1770
1771         return 0;
1772 }
1773
1774 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1775 {
1776         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1777         int ret = 0;
1778         int gpu_freq, ia_freq;
1779         unsigned int max_gpu_freq, min_gpu_freq;
1780
1781         if (!HAS_CORE_RING_FREQ(dev_priv)) {
1782                 seq_puts(m, "unsupported on this chipset\n");
1783                 return 0;
1784         }
1785
1786         intel_runtime_pm_get(dev_priv);
1787
1788         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1789         if (ret)
1790                 goto out;
1791
1792         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
1793                 /* Convert GT frequency to 50 HZ units */
1794                 min_gpu_freq =
1795                         dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1796                 max_gpu_freq =
1797                         dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1798         } else {
1799                 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1800                 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1801         }
1802
1803         seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1804
1805         for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1806                 ia_freq = gpu_freq;
1807                 sandybridge_pcode_read(dev_priv,
1808                                        GEN6_PCODE_READ_MIN_FREQ_TABLE,
1809                                        &ia_freq);
1810                 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1811                            intel_gpu_freq(dev_priv, (gpu_freq *
1812                                 (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1813                                  GEN9_FREQ_SCALER : 1))),
1814                            ((ia_freq >> 0) & 0xff) * 100,
1815                            ((ia_freq >> 8) & 0xff) * 100);
1816         }
1817
1818         mutex_unlock(&dev_priv->rps.hw_lock);
1819
1820 out:
1821         intel_runtime_pm_put(dev_priv);
1822         return ret;
1823 }
1824
1825 static int i915_opregion(struct seq_file *m, void *unused)
1826 {
1827         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1828         struct drm_device *dev = &dev_priv->drm;
1829         struct intel_opregion *opregion = &dev_priv->opregion;
1830         int ret;
1831
1832         ret = mutex_lock_interruptible(&dev->struct_mutex);
1833         if (ret)
1834                 goto out;
1835
1836         if (opregion->header)
1837                 seq_write(m, opregion->header, OPREGION_SIZE);
1838
1839         mutex_unlock(&dev->struct_mutex);
1840
1841 out:
1842         return 0;
1843 }
1844
1845 static int i915_vbt(struct seq_file *m, void *unused)
1846 {
1847         struct intel_opregion *opregion = &node_to_i915(m->private)->opregion;
1848
1849         if (opregion->vbt)
1850                 seq_write(m, opregion->vbt, opregion->vbt_size);
1851
1852         return 0;
1853 }
1854
1855 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1856 {
1857         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1858         struct drm_device *dev = &dev_priv->drm;
1859         struct intel_framebuffer *fbdev_fb = NULL;
1860         struct drm_framebuffer *drm_fb;
1861         int ret;
1862
1863         ret = mutex_lock_interruptible(&dev->struct_mutex);
1864         if (ret)
1865                 return ret;
1866
1867 #ifdef CONFIG_DRM_FBDEV_EMULATION
1868         if (dev_priv->fbdev) {
1869                 fbdev_fb = to_intel_framebuffer(dev_priv->fbdev->helper.fb);
1870
1871                 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1872                            fbdev_fb->base.width,
1873                            fbdev_fb->base.height,
1874                            fbdev_fb->base.depth,
1875                            fbdev_fb->base.bits_per_pixel,
1876                            fbdev_fb->base.modifier[0],
1877                            drm_framebuffer_read_refcount(&fbdev_fb->base));
1878                 describe_obj(m, fbdev_fb->obj);
1879                 seq_putc(m, '\n');
1880         }
1881 #endif
1882
1883         mutex_lock(&dev->mode_config.fb_lock);
1884         drm_for_each_fb(drm_fb, dev) {
1885                 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
1886                 if (fb == fbdev_fb)
1887                         continue;
1888
1889                 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1890                            fb->base.width,
1891                            fb->base.height,
1892                            fb->base.depth,
1893                            fb->base.bits_per_pixel,
1894                            fb->base.modifier[0],
1895                            drm_framebuffer_read_refcount(&fb->base));
1896                 describe_obj(m, fb->obj);
1897                 seq_putc(m, '\n');
1898         }
1899         mutex_unlock(&dev->mode_config.fb_lock);
1900         mutex_unlock(&dev->struct_mutex);
1901
1902         return 0;
1903 }
1904
1905 static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring)
1906 {
1907         seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1908                    ring->space, ring->head, ring->tail,
1909                    ring->last_retired_head);
1910 }
1911
1912 static int i915_context_status(struct seq_file *m, void *unused)
1913 {
1914         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1915         struct drm_device *dev = &dev_priv->drm;
1916         struct intel_engine_cs *engine;
1917         struct i915_gem_context *ctx;
1918         int ret;
1919
1920         ret = mutex_lock_interruptible(&dev->struct_mutex);
1921         if (ret)
1922                 return ret;
1923
1924         list_for_each_entry(ctx, &dev_priv->context_list, link) {
1925                 seq_printf(m, "HW context %u ", ctx->hw_id);
1926                 if (ctx->pid) {
1927                         struct task_struct *task;
1928
1929                         task = get_pid_task(ctx->pid, PIDTYPE_PID);
1930                         if (task) {
1931                                 seq_printf(m, "(%s [%d]) ",
1932                                            task->comm, task->pid);
1933                                 put_task_struct(task);
1934                         }
1935                 } else if (IS_ERR(ctx->file_priv)) {
1936                         seq_puts(m, "(deleted) ");
1937                 } else {
1938                         seq_puts(m, "(kernel) ");
1939                 }
1940
1941                 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
1942                 seq_putc(m, '\n');
1943
1944                 for_each_engine(engine, dev_priv) {
1945                         struct intel_context *ce = &ctx->engine[engine->id];
1946
1947                         seq_printf(m, "%s: ", engine->name);
1948                         seq_putc(m, ce->initialised ? 'I' : 'i');
1949                         if (ce->state)
1950                                 describe_obj(m, ce->state->obj);
1951                         if (ce->ring)
1952                                 describe_ctx_ring(m, ce->ring);
1953                         seq_putc(m, '\n');
1954                 }
1955
1956                 seq_putc(m, '\n');
1957         }
1958
1959         mutex_unlock(&dev->struct_mutex);
1960
1961         return 0;
1962 }
1963
1964 static void i915_dump_lrc_obj(struct seq_file *m,
1965                               struct i915_gem_context *ctx,
1966                               struct intel_engine_cs *engine)
1967 {
1968         struct i915_vma *vma = ctx->engine[engine->id].state;
1969         struct page *page;
1970         int j;
1971
1972         seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id);
1973
1974         if (!vma) {
1975                 seq_puts(m, "\tFake context\n");
1976                 return;
1977         }
1978
1979         if (vma->flags & I915_VMA_GLOBAL_BIND)
1980                 seq_printf(m, "\tBound in GGTT at 0x%08x\n",
1981                            i915_ggtt_offset(vma));
1982
1983         if (i915_gem_object_get_pages(vma->obj)) {
1984                 seq_puts(m, "\tFailed to get pages for context object\n\n");
1985                 return;
1986         }
1987
1988         page = i915_gem_object_get_page(vma->obj, LRC_STATE_PN);
1989         if (page) {
1990                 u32 *reg_state = kmap_atomic(page);
1991
1992                 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
1993                         seq_printf(m,
1994                                    "\t[0x%04x] 0x%08x 0x%08x 0x%08x 0x%08x\n",
1995                                    j * 4,
1996                                    reg_state[j], reg_state[j + 1],
1997                                    reg_state[j + 2], reg_state[j + 3]);
1998                 }
1999                 kunmap_atomic(reg_state);
2000         }
2001
2002         seq_putc(m, '\n');
2003 }
2004
2005 static int i915_dump_lrc(struct seq_file *m, void *unused)
2006 {
2007         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2008         struct drm_device *dev = &dev_priv->drm;
2009         struct intel_engine_cs *engine;
2010         struct i915_gem_context *ctx;
2011         int ret;
2012
2013         if (!i915.enable_execlists) {
2014                 seq_printf(m, "Logical Ring Contexts are disabled\n");
2015                 return 0;
2016         }
2017
2018         ret = mutex_lock_interruptible(&dev->struct_mutex);
2019         if (ret)
2020                 return ret;
2021
2022         list_for_each_entry(ctx, &dev_priv->context_list, link)
2023                 for_each_engine(engine, dev_priv)
2024                         i915_dump_lrc_obj(m, ctx, engine);
2025
2026         mutex_unlock(&dev->struct_mutex);
2027
2028         return 0;
2029 }
2030
2031 static int i915_execlists(struct seq_file *m, void *data)
2032 {
2033         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2034         struct drm_device *dev = &dev_priv->drm;
2035         struct intel_engine_cs *engine;
2036         u32 status_pointer;
2037         u8 read_pointer;
2038         u8 write_pointer;
2039         u32 status;
2040         u32 ctx_id;
2041         struct list_head *cursor;
2042         int i, ret;
2043
2044         if (!i915.enable_execlists) {
2045                 seq_puts(m, "Logical Ring Contexts are disabled\n");
2046                 return 0;
2047         }
2048
2049         ret = mutex_lock_interruptible(&dev->struct_mutex);
2050         if (ret)
2051                 return ret;
2052
2053         intel_runtime_pm_get(dev_priv);
2054
2055         for_each_engine(engine, dev_priv) {
2056                 struct drm_i915_gem_request *head_req = NULL;
2057                 int count = 0;
2058
2059                 seq_printf(m, "%s\n", engine->name);
2060
2061                 status = I915_READ(RING_EXECLIST_STATUS_LO(engine));
2062                 ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(engine));
2063                 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2064                            status, ctx_id);
2065
2066                 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
2067                 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2068
2069                 read_pointer = engine->next_context_status_buffer;
2070                 write_pointer = GEN8_CSB_WRITE_PTR(status_pointer);
2071                 if (read_pointer > write_pointer)
2072                         write_pointer += GEN8_CSB_ENTRIES;
2073                 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2074                            read_pointer, write_pointer);
2075
2076                 for (i = 0; i < GEN8_CSB_ENTRIES; i++) {
2077                         status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, i));
2078                         ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, i));
2079
2080                         seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2081                                    i, status, ctx_id);
2082                 }
2083
2084                 spin_lock_bh(&engine->execlist_lock);
2085                 list_for_each(cursor, &engine->execlist_queue)
2086                         count++;
2087                 head_req = list_first_entry_or_null(&engine->execlist_queue,
2088                                                     struct drm_i915_gem_request,
2089                                                     execlist_link);
2090                 spin_unlock_bh(&engine->execlist_lock);
2091
2092                 seq_printf(m, "\t%d requests in queue\n", count);
2093                 if (head_req) {
2094                         seq_printf(m, "\tHead request context: %u\n",
2095                                    head_req->ctx->hw_id);
2096                         seq_printf(m, "\tHead request tail: %u\n",
2097                                    head_req->tail);
2098                 }
2099
2100                 seq_putc(m, '\n');
2101         }
2102
2103         intel_runtime_pm_put(dev_priv);
2104         mutex_unlock(&dev->struct_mutex);
2105
2106         return 0;
2107 }
2108
2109 static const char *swizzle_string(unsigned swizzle)
2110 {
2111         switch (swizzle) {
2112         case I915_BIT_6_SWIZZLE_NONE:
2113                 return "none";
2114         case I915_BIT_6_SWIZZLE_9:
2115                 return "bit9";
2116         case I915_BIT_6_SWIZZLE_9_10:
2117                 return "bit9/bit10";
2118         case I915_BIT_6_SWIZZLE_9_11:
2119                 return "bit9/bit11";
2120         case I915_BIT_6_SWIZZLE_9_10_11:
2121                 return "bit9/bit10/bit11";
2122         case I915_BIT_6_SWIZZLE_9_17:
2123                 return "bit9/bit17";
2124         case I915_BIT_6_SWIZZLE_9_10_17:
2125                 return "bit9/bit10/bit17";
2126         case I915_BIT_6_SWIZZLE_UNKNOWN:
2127                 return "unknown";
2128         }
2129
2130         return "bug";
2131 }
2132
2133 static int i915_swizzle_info(struct seq_file *m, void *data)
2134 {
2135         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2136         struct drm_device *dev = &dev_priv->drm;
2137         int ret;
2138
2139         ret = mutex_lock_interruptible(&dev->struct_mutex);
2140         if (ret)
2141                 return ret;
2142         intel_runtime_pm_get(dev_priv);
2143
2144         seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2145                    swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2146         seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2147                    swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2148
2149         if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) {
2150                 seq_printf(m, "DDC = 0x%08x\n",
2151                            I915_READ(DCC));
2152                 seq_printf(m, "DDC2 = 0x%08x\n",
2153                            I915_READ(DCC2));
2154                 seq_printf(m, "C0DRB3 = 0x%04x\n",
2155                            I915_READ16(C0DRB3));
2156                 seq_printf(m, "C1DRB3 = 0x%04x\n",
2157                            I915_READ16(C1DRB3));
2158         } else if (INTEL_GEN(dev_priv) >= 6) {
2159                 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2160                            I915_READ(MAD_DIMM_C0));
2161                 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2162                            I915_READ(MAD_DIMM_C1));
2163                 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2164                            I915_READ(MAD_DIMM_C2));
2165                 seq_printf(m, "TILECTL = 0x%08x\n",
2166                            I915_READ(TILECTL));
2167                 if (INTEL_GEN(dev_priv) >= 8)
2168                         seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2169                                    I915_READ(GAMTARBMODE));
2170                 else
2171                         seq_printf(m, "ARB_MODE = 0x%08x\n",
2172                                    I915_READ(ARB_MODE));
2173                 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2174                            I915_READ(DISP_ARB_CTL));
2175         }
2176
2177         if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2178                 seq_puts(m, "L-shaped memory detected\n");
2179
2180         intel_runtime_pm_put(dev_priv);
2181         mutex_unlock(&dev->struct_mutex);
2182
2183         return 0;
2184 }
2185
2186 static int per_file_ctx(int id, void *ptr, void *data)
2187 {
2188         struct i915_gem_context *ctx = ptr;
2189         struct seq_file *m = data;
2190         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2191
2192         if (!ppgtt) {
2193                 seq_printf(m, "  no ppgtt for context %d\n",
2194                            ctx->user_handle);
2195                 return 0;
2196         }
2197
2198         if (i915_gem_context_is_default(ctx))
2199                 seq_puts(m, "  default context:\n");
2200         else
2201                 seq_printf(m, "  context %d:\n", ctx->user_handle);
2202         ppgtt->debug_dump(ppgtt, m);
2203
2204         return 0;
2205 }
2206
2207 static void gen8_ppgtt_info(struct seq_file *m,
2208                             struct drm_i915_private *dev_priv)
2209 {
2210         struct intel_engine_cs *engine;
2211         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2212         int i;
2213
2214         if (!ppgtt)
2215                 return;
2216
2217         for_each_engine(engine, dev_priv) {
2218                 seq_printf(m, "%s\n", engine->name);
2219                 for (i = 0; i < 4; i++) {
2220                         u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
2221                         pdp <<= 32;
2222                         pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
2223                         seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2224                 }
2225         }
2226 }
2227
2228 static void gen6_ppgtt_info(struct seq_file *m,
2229                             struct drm_i915_private *dev_priv)
2230 {
2231         struct intel_engine_cs *engine;
2232
2233         if (IS_GEN6(dev_priv))
2234                 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2235
2236         for_each_engine(engine, dev_priv) {
2237                 seq_printf(m, "%s\n", engine->name);
2238                 if (IS_GEN7(dev_priv))
2239                         seq_printf(m, "GFX_MODE: 0x%08x\n",
2240                                    I915_READ(RING_MODE_GEN7(engine)));
2241                 seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
2242                            I915_READ(RING_PP_DIR_BASE(engine)));
2243                 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
2244                            I915_READ(RING_PP_DIR_BASE_READ(engine)));
2245                 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
2246                            I915_READ(RING_PP_DIR_DCLV(engine)));
2247         }
2248         if (dev_priv->mm.aliasing_ppgtt) {
2249                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2250
2251                 seq_puts(m, "aliasing PPGTT:\n");
2252                 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2253
2254                 ppgtt->debug_dump(ppgtt, m);
2255         }
2256
2257         seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2258 }
2259
2260 static int i915_ppgtt_info(struct seq_file *m, void *data)
2261 {
2262         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2263         struct drm_device *dev = &dev_priv->drm;
2264         struct drm_file *file;
2265         int ret;
2266
2267         mutex_lock(&dev->filelist_mutex);
2268         ret = mutex_lock_interruptible(&dev->struct_mutex);
2269         if (ret)
2270                 goto out_unlock;
2271
2272         intel_runtime_pm_get(dev_priv);
2273
2274         if (INTEL_GEN(dev_priv) >= 8)
2275                 gen8_ppgtt_info(m, dev_priv);
2276         else if (INTEL_GEN(dev_priv) >= 6)
2277                 gen6_ppgtt_info(m, dev_priv);
2278
2279         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2280                 struct drm_i915_file_private *file_priv = file->driver_priv;
2281                 struct task_struct *task;
2282
2283                 task = get_pid_task(file->pid, PIDTYPE_PID);
2284                 if (!task) {
2285                         ret = -ESRCH;
2286                         goto out_rpm;
2287                 }
2288                 seq_printf(m, "\nproc: %s\n", task->comm);
2289                 put_task_struct(task);
2290                 idr_for_each(&file_priv->context_idr, per_file_ctx,
2291                              (void *)(unsigned long)m);
2292         }
2293
2294 out_rpm:
2295         intel_runtime_pm_put(dev_priv);
2296         mutex_unlock(&dev->struct_mutex);
2297 out_unlock:
2298         mutex_unlock(&dev->filelist_mutex);
2299         return ret;
2300 }
2301
2302 static int count_irq_waiters(struct drm_i915_private *i915)
2303 {
2304         struct intel_engine_cs *engine;
2305         int count = 0;
2306
2307         for_each_engine(engine, i915)
2308                 count += intel_engine_has_waiter(engine);
2309
2310         return count;
2311 }
2312
2313 static const char *rps_power_to_str(unsigned int power)
2314 {
2315         static const char * const strings[] = {
2316                 [LOW_POWER] = "low power",
2317                 [BETWEEN] = "mixed",
2318                 [HIGH_POWER] = "high power",
2319         };
2320
2321         if (power >= ARRAY_SIZE(strings) || !strings[power])
2322                 return "unknown";
2323
2324         return strings[power];
2325 }
2326
2327 static int i915_rps_boost_info(struct seq_file *m, void *data)
2328 {
2329         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2330         struct drm_device *dev = &dev_priv->drm;
2331         struct drm_file *file;
2332
2333         seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2334         seq_printf(m, "GPU busy? %s [%x]\n",
2335                    yesno(dev_priv->gt.awake), dev_priv->gt.active_engines);
2336         seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2337         seq_printf(m, "Frequency requested %d\n",
2338                    intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
2339         seq_printf(m, "  min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2340                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2341                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2342                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2343                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2344         seq_printf(m, "  idle:%d, efficient:%d, boost:%d\n",
2345                    intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
2346                    intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2347                    intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
2348
2349         mutex_lock(&dev->filelist_mutex);
2350         spin_lock(&dev_priv->rps.client_lock);
2351         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2352                 struct drm_i915_file_private *file_priv = file->driver_priv;
2353                 struct task_struct *task;
2354
2355                 rcu_read_lock();
2356                 task = pid_task(file->pid, PIDTYPE_PID);
2357                 seq_printf(m, "%s [%d]: %d boosts%s\n",
2358                            task ? task->comm : "<unknown>",
2359                            task ? task->pid : -1,
2360                            file_priv->rps.boosts,
2361                            list_empty(&file_priv->rps.link) ? "" : ", active");
2362                 rcu_read_unlock();
2363         }
2364         seq_printf(m, "Kernel (anonymous) boosts: %d\n", dev_priv->rps.boosts);
2365         spin_unlock(&dev_priv->rps.client_lock);
2366         mutex_unlock(&dev->filelist_mutex);
2367
2368         if (INTEL_GEN(dev_priv) >= 6 &&
2369             dev_priv->rps.enabled &&
2370             dev_priv->gt.active_engines) {
2371                 u32 rpup, rpupei;
2372                 u32 rpdown, rpdownei;
2373
2374                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2375                 rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK;
2376                 rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK;
2377                 rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK;
2378                 rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK;
2379                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2380
2381                 seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n",
2382                            rps_power_to_str(dev_priv->rps.power));
2383                 seq_printf(m, "  Avg. up: %d%% [above threshold? %d%%]\n",
2384                            100 * rpup / rpupei,
2385                            dev_priv->rps.up_threshold);
2386                 seq_printf(m, "  Avg. down: %d%% [below threshold? %d%%]\n",
2387                            100 * rpdown / rpdownei,
2388                            dev_priv->rps.down_threshold);
2389         } else {
2390                 seq_puts(m, "\nRPS Autotuning inactive\n");
2391         }
2392
2393         return 0;
2394 }
2395
2396 static int i915_llc(struct seq_file *m, void *data)
2397 {
2398         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2399         const bool edram = INTEL_GEN(dev_priv) > 8;
2400
2401         seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv)));
2402         seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
2403                    intel_uncore_edram_size(dev_priv)/1024/1024);
2404
2405         return 0;
2406 }
2407
2408 static int i915_guc_load_status_info(struct seq_file *m, void *data)
2409 {
2410         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2411         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
2412         u32 tmp, i;
2413
2414         if (!HAS_GUC_UCODE(dev_priv))
2415                 return 0;
2416
2417         seq_printf(m, "GuC firmware status:\n");
2418         seq_printf(m, "\tpath: %s\n",
2419                 guc_fw->guc_fw_path);
2420         seq_printf(m, "\tfetch: %s\n",
2421                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
2422         seq_printf(m, "\tload: %s\n",
2423                 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
2424         seq_printf(m, "\tversion wanted: %d.%d\n",
2425                 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2426         seq_printf(m, "\tversion found: %d.%d\n",
2427                 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
2428         seq_printf(m, "\theader: offset is %d; size = %d\n",
2429                 guc_fw->header_offset, guc_fw->header_size);
2430         seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2431                 guc_fw->ucode_offset, guc_fw->ucode_size);
2432         seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2433                 guc_fw->rsa_offset, guc_fw->rsa_size);
2434
2435         tmp = I915_READ(GUC_STATUS);
2436
2437         seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2438         seq_printf(m, "\tBootrom status = 0x%x\n",
2439                 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2440         seq_printf(m, "\tuKernel status = 0x%x\n",
2441                 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2442         seq_printf(m, "\tMIA Core status = 0x%x\n",
2443                 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2444         seq_puts(m, "\nScratch registers:\n");
2445         for (i = 0; i < 16; i++)
2446                 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2447
2448         return 0;
2449 }
2450
2451 static void i915_guc_client_info(struct seq_file *m,
2452                                  struct drm_i915_private *dev_priv,
2453                                  struct i915_guc_client *client)
2454 {
2455         struct intel_engine_cs *engine;
2456         enum intel_engine_id id;
2457         uint64_t tot = 0;
2458
2459         seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2460                 client->priority, client->ctx_index, client->proc_desc_offset);
2461         seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2462                 client->doorbell_id, client->doorbell_offset, client->cookie);
2463         seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2464                 client->wq_size, client->wq_offset, client->wq_tail);
2465
2466         seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space);
2467         seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2468         seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2469
2470         for_each_engine_id(engine, dev_priv, id) {
2471                 u64 submissions = client->submissions[id];
2472                 tot += submissions;
2473                 seq_printf(m, "\tSubmissions: %llu %s\n",
2474                                 submissions, engine->name);
2475         }
2476         seq_printf(m, "\tTotal: %llu\n", tot);
2477 }
2478
2479 static int i915_guc_info(struct seq_file *m, void *data)
2480 {
2481         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2482         struct drm_device *dev = &dev_priv->drm;
2483         struct intel_guc guc;
2484         struct i915_guc_client client = {};
2485         struct intel_engine_cs *engine;
2486         enum intel_engine_id id;
2487         u64 total = 0;
2488
2489         if (!HAS_GUC_SCHED(dev_priv))
2490                 return 0;
2491
2492         if (mutex_lock_interruptible(&dev->struct_mutex))
2493                 return 0;
2494
2495         /* Take a local copy of the GuC data, so we can dump it at leisure */
2496         guc = dev_priv->guc;
2497         if (guc.execbuf_client)
2498                 client = *guc.execbuf_client;
2499
2500         mutex_unlock(&dev->struct_mutex);
2501
2502         seq_printf(m, "Doorbell map:\n");
2503         seq_printf(m, "\t%*pb\n", GUC_MAX_DOORBELLS, guc.doorbell_bitmap);
2504         seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc.db_cacheline);
2505
2506         seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
2507         seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
2508         seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
2509         seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
2510         seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
2511
2512         seq_printf(m, "\nGuC submissions:\n");
2513         for_each_engine_id(engine, dev_priv, id) {
2514                 u64 submissions = guc.submissions[id];
2515                 total += submissions;
2516                 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",
2517                         engine->name, submissions, guc.last_seqno[id]);
2518         }
2519         seq_printf(m, "\t%s: %llu\n", "Total", total);
2520
2521         seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
2522         i915_guc_client_info(m, dev_priv, &client);
2523
2524         /* Add more as required ... */
2525
2526         return 0;
2527 }
2528
2529 static int i915_guc_log_dump(struct seq_file *m, void *data)
2530 {
2531         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2532         struct drm_i915_gem_object *obj;
2533         int i = 0, pg;
2534
2535         if (!dev_priv->guc.log_vma)
2536                 return 0;
2537
2538         obj = dev_priv->guc.log_vma->obj;
2539         for (pg = 0; pg < obj->base.size / PAGE_SIZE; pg++) {
2540                 u32 *log = kmap_atomic(i915_gem_object_get_page(obj, pg));
2541
2542                 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2543                         seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2544                                    *(log + i), *(log + i + 1),
2545                                    *(log + i + 2), *(log + i + 3));
2546
2547                 kunmap_atomic(log);
2548         }
2549
2550         seq_putc(m, '\n');
2551
2552         return 0;
2553 }
2554
2555 static int i915_edp_psr_status(struct seq_file *m, void *data)
2556 {
2557         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2558         u32 psrperf = 0;
2559         u32 stat[3];
2560         enum pipe pipe;
2561         bool enabled = false;
2562
2563         if (!HAS_PSR(dev_priv)) {
2564                 seq_puts(m, "PSR not supported\n");
2565                 return 0;
2566         }
2567
2568         intel_runtime_pm_get(dev_priv);
2569
2570         mutex_lock(&dev_priv->psr.lock);
2571         seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2572         seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2573         seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2574         seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2575         seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2576                    dev_priv->psr.busy_frontbuffer_bits);
2577         seq_printf(m, "Re-enable work scheduled: %s\n",
2578                    yesno(work_busy(&dev_priv->psr.work.work)));
2579
2580         if (HAS_DDI(dev_priv))
2581                 enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2582         else {
2583                 for_each_pipe(dev_priv, pipe) {
2584                         stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2585                                 VLV_EDP_PSR_CURR_STATE_MASK;
2586                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2587                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2588                                 enabled = true;
2589                 }
2590         }
2591
2592         seq_printf(m, "Main link in standby mode: %s\n",
2593                    yesno(dev_priv->psr.link_standby));
2594
2595         seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2596
2597         if (!HAS_DDI(dev_priv))
2598                 for_each_pipe(dev_priv, pipe) {
2599                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2600                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2601                                 seq_printf(m, " pipe %c", pipe_name(pipe));
2602                 }
2603         seq_puts(m, "\n");
2604
2605         /*
2606          * VLV/CHV PSR has no kind of performance counter
2607          * SKL+ Perf counter is reset to 0 everytime DC state is entered
2608          */
2609         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2610                 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
2611                         EDP_PSR_PERF_CNT_MASK;
2612
2613                 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2614         }
2615         mutex_unlock(&dev_priv->psr.lock);
2616
2617         intel_runtime_pm_put(dev_priv);
2618         return 0;
2619 }
2620
2621 static int i915_sink_crc(struct seq_file *m, void *data)
2622 {
2623         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2624         struct drm_device *dev = &dev_priv->drm;
2625         struct intel_connector *connector;
2626         struct intel_dp *intel_dp = NULL;
2627         int ret;
2628         u8 crc[6];
2629
2630         drm_modeset_lock_all(dev);
2631         for_each_intel_connector(dev, connector) {
2632                 struct drm_crtc *crtc;
2633
2634                 if (!connector->base.state->best_encoder)
2635                         continue;
2636
2637                 crtc = connector->base.state->crtc;
2638                 if (!crtc->state->active)
2639                         continue;
2640
2641                 if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
2642                         continue;
2643
2644                 intel_dp = enc_to_intel_dp(connector->base.state->best_encoder);
2645
2646                 ret = intel_dp_sink_crc(intel_dp, crc);
2647                 if (ret)
2648                         goto out;
2649
2650                 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2651                            crc[0], crc[1], crc[2],
2652                            crc[3], crc[4], crc[5]);
2653                 goto out;
2654         }
2655         ret = -ENODEV;
2656 out:
2657         drm_modeset_unlock_all(dev);
2658         return ret;
2659 }
2660
2661 static int i915_energy_uJ(struct seq_file *m, void *data)
2662 {
2663         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2664         u64 power;
2665         u32 units;
2666
2667         if (INTEL_GEN(dev_priv) < 6)
2668                 return -ENODEV;
2669
2670         intel_runtime_pm_get(dev_priv);
2671
2672         rdmsrl(MSR_RAPL_POWER_UNIT, power);
2673         power = (power & 0x1f00) >> 8;
2674         units = 1000000 / (1 << power); /* convert to uJ */
2675         power = I915_READ(MCH_SECP_NRG_STTS);
2676         power *= units;
2677
2678         intel_runtime_pm_put(dev_priv);
2679
2680         seq_printf(m, "%llu", (long long unsigned)power);
2681
2682         return 0;
2683 }
2684
2685 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2686 {
2687         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2688         struct pci_dev *pdev = dev_priv->drm.pdev;
2689
2690         if (!HAS_RUNTIME_PM(dev_priv))
2691                 seq_puts(m, "Runtime power management not supported\n");
2692
2693         seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
2694         seq_printf(m, "IRQs disabled: %s\n",
2695                    yesno(!intel_irqs_enabled(dev_priv)));
2696 #ifdef CONFIG_PM
2697         seq_printf(m, "Usage count: %d\n",
2698                    atomic_read(&dev_priv->drm.dev->power.usage_count));
2699 #else
2700         seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2701 #endif
2702         seq_printf(m, "PCI device power state: %s [%d]\n",
2703                    pci_power_name(pdev->current_state),
2704                    pdev->current_state);
2705
2706         return 0;
2707 }
2708
2709 static int i915_power_domain_info(struct seq_file *m, void *unused)
2710 {
2711         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2712         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2713         int i;
2714
2715         mutex_lock(&power_domains->lock);
2716
2717         seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2718         for (i = 0; i < power_domains->power_well_count; i++) {
2719                 struct i915_power_well *power_well;
2720                 enum intel_display_power_domain power_domain;
2721
2722                 power_well = &power_domains->power_wells[i];
2723                 seq_printf(m, "%-25s %d\n", power_well->name,
2724                            power_well->count);
2725
2726                 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2727                      power_domain++) {
2728                         if (!(BIT(power_domain) & power_well->domains))
2729                                 continue;
2730
2731                         seq_printf(m, "  %-23s %d\n",
2732                                  intel_display_power_domain_str(power_domain),
2733                                  power_domains->domain_use_count[power_domain]);
2734                 }
2735         }
2736
2737         mutex_unlock(&power_domains->lock);
2738
2739         return 0;
2740 }
2741
2742 static int i915_dmc_info(struct seq_file *m, void *unused)
2743 {
2744         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2745         struct intel_csr *csr;
2746
2747         if (!HAS_CSR(dev_priv)) {
2748                 seq_puts(m, "not supported\n");
2749                 return 0;
2750         }
2751
2752         csr = &dev_priv->csr;
2753
2754         intel_runtime_pm_get(dev_priv);
2755
2756         seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2757         seq_printf(m, "path: %s\n", csr->fw_path);
2758
2759         if (!csr->dmc_payload)
2760                 goto out;
2761
2762         seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2763                    CSR_VERSION_MINOR(csr->version));
2764
2765         if (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6)) {
2766                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2767                            I915_READ(SKL_CSR_DC3_DC5_COUNT));
2768                 seq_printf(m, "DC5 -> DC6 count: %d\n",
2769                            I915_READ(SKL_CSR_DC5_DC6_COUNT));
2770         } else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) {
2771                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2772                            I915_READ(BXT_CSR_DC3_DC5_COUNT));
2773         }
2774
2775 out:
2776         seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2777         seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2778         seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2779
2780         intel_runtime_pm_put(dev_priv);
2781
2782         return 0;
2783 }
2784
2785 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2786                                  struct drm_display_mode *mode)
2787 {
2788         int i;
2789
2790         for (i = 0; i < tabs; i++)
2791                 seq_putc(m, '\t');
2792
2793         seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2794                    mode->base.id, mode->name,
2795                    mode->vrefresh, mode->clock,
2796                    mode->hdisplay, mode->hsync_start,
2797                    mode->hsync_end, mode->htotal,
2798                    mode->vdisplay, mode->vsync_start,
2799                    mode->vsync_end, mode->vtotal,
2800                    mode->type, mode->flags);
2801 }
2802
2803 static void intel_encoder_info(struct seq_file *m,
2804                                struct intel_crtc *intel_crtc,
2805                                struct intel_encoder *intel_encoder)
2806 {
2807         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2808         struct drm_device *dev = &dev_priv->drm;
2809         struct drm_crtc *crtc = &intel_crtc->base;
2810         struct intel_connector *intel_connector;
2811         struct drm_encoder *encoder;
2812
2813         encoder = &intel_encoder->base;
2814         seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2815                    encoder->base.id, encoder->name);
2816         for_each_connector_on_encoder(dev, encoder, intel_connector) {
2817                 struct drm_connector *connector = &intel_connector->base;
2818                 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2819                            connector->base.id,
2820                            connector->name,
2821                            drm_get_connector_status_name(connector->status));
2822                 if (connector->status == connector_status_connected) {
2823                         struct drm_display_mode *mode = &crtc->mode;
2824                         seq_printf(m, ", mode:\n");
2825                         intel_seq_print_mode(m, 2, mode);
2826                 } else {
2827                         seq_putc(m, '\n');
2828                 }
2829         }
2830 }
2831
2832 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2833 {
2834         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2835         struct drm_device *dev = &dev_priv->drm;
2836         struct drm_crtc *crtc = &intel_crtc->base;
2837         struct intel_encoder *intel_encoder;
2838         struct drm_plane_state *plane_state = crtc->primary->state;
2839         struct drm_framebuffer *fb = plane_state->fb;
2840
2841         if (fb)
2842                 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2843                            fb->base.id, plane_state->src_x >> 16,
2844                            plane_state->src_y >> 16, fb->width, fb->height);
2845         else
2846                 seq_puts(m, "\tprimary plane disabled\n");
2847         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2848                 intel_encoder_info(m, intel_crtc, intel_encoder);
2849 }
2850
2851 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2852 {
2853         struct drm_display_mode *mode = panel->fixed_mode;
2854
2855         seq_printf(m, "\tfixed mode:\n");
2856         intel_seq_print_mode(m, 2, mode);
2857 }
2858
2859 static void intel_dp_info(struct seq_file *m,
2860                           struct intel_connector *intel_connector)
2861 {
2862         struct intel_encoder *intel_encoder = intel_connector->encoder;
2863         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2864
2865         seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2866         seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2867         if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
2868                 intel_panel_info(m, &intel_connector->panel);
2869 }
2870
2871 static void intel_hdmi_info(struct seq_file *m,
2872                             struct intel_connector *intel_connector)
2873 {
2874         struct intel_encoder *intel_encoder = intel_connector->encoder;
2875         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2876
2877         seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
2878 }
2879
2880 static void intel_lvds_info(struct seq_file *m,
2881                             struct intel_connector *intel_connector)
2882 {
2883         intel_panel_info(m, &intel_connector->panel);
2884 }
2885
2886 static void intel_connector_info(struct seq_file *m,
2887                                  struct drm_connector *connector)
2888 {
2889         struct intel_connector *intel_connector = to_intel_connector(connector);
2890         struct intel_encoder *intel_encoder = intel_connector->encoder;
2891         struct drm_display_mode *mode;
2892
2893         seq_printf(m, "connector %d: type %s, status: %s\n",
2894                    connector->base.id, connector->name,
2895                    drm_get_connector_status_name(connector->status));
2896         if (connector->status == connector_status_connected) {
2897                 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2898                 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2899                            connector->display_info.width_mm,
2900                            connector->display_info.height_mm);
2901                 seq_printf(m, "\tsubpixel order: %s\n",
2902                            drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2903                 seq_printf(m, "\tCEA rev: %d\n",
2904                            connector->display_info.cea_rev);
2905         }
2906
2907         if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
2908                 return;
2909
2910         switch (connector->connector_type) {
2911         case DRM_MODE_CONNECTOR_DisplayPort:
2912         case DRM_MODE_CONNECTOR_eDP:
2913                 intel_dp_info(m, intel_connector);
2914                 break;
2915         case DRM_MODE_CONNECTOR_LVDS:
2916                 if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2917                         intel_lvds_info(m, intel_connector);
2918                 break;
2919         case DRM_MODE_CONNECTOR_HDMIA:
2920                 if (intel_encoder->type == INTEL_OUTPUT_HDMI ||
2921                     intel_encoder->type == INTEL_OUTPUT_UNKNOWN)
2922                         intel_hdmi_info(m, intel_connector);
2923                 break;
2924         default:
2925                 break;
2926         }
2927
2928         seq_printf(m, "\tmodes:\n");
2929         list_for_each_entry(mode, &connector->modes, head)
2930                 intel_seq_print_mode(m, 2, mode);
2931 }
2932
2933 static bool cursor_active(struct drm_i915_private *dev_priv, int pipe)
2934 {
2935         u32 state;
2936
2937         if (IS_845G(dev_priv) || IS_I865G(dev_priv))
2938                 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
2939         else
2940                 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2941
2942         return state;
2943 }
2944
2945 static bool cursor_position(struct drm_i915_private *dev_priv,
2946                             int pipe, int *x, int *y)
2947 {
2948         u32 pos;
2949
2950         pos = I915_READ(CURPOS(pipe));
2951
2952         *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2953         if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2954                 *x = -*x;
2955
2956         *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2957         if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2958                 *y = -*y;
2959
2960         return cursor_active(dev_priv, pipe);
2961 }
2962
2963 static const char *plane_type(enum drm_plane_type type)
2964 {
2965         switch (type) {
2966         case DRM_PLANE_TYPE_OVERLAY:
2967                 return "OVL";
2968         case DRM_PLANE_TYPE_PRIMARY:
2969                 return "PRI";
2970         case DRM_PLANE_TYPE_CURSOR:
2971                 return "CUR";
2972         /*
2973          * Deliberately omitting default: to generate compiler warnings
2974          * when a new drm_plane_type gets added.
2975          */
2976         }
2977
2978         return "unknown";
2979 }
2980
2981 static const char *plane_rotation(unsigned int rotation)
2982 {
2983         static char buf[48];
2984         /*
2985          * According to doc only one DRM_ROTATE_ is allowed but this
2986          * will print them all to visualize if the values are misused
2987          */
2988         snprintf(buf, sizeof(buf),
2989                  "%s%s%s%s%s%s(0x%08x)",
2990                  (rotation & DRM_ROTATE_0) ? "0 " : "",
2991                  (rotation & DRM_ROTATE_90) ? "90 " : "",
2992                  (rotation & DRM_ROTATE_180) ? "180 " : "",
2993                  (rotation & DRM_ROTATE_270) ? "270 " : "",
2994                  (rotation & DRM_REFLECT_X) ? "FLIPX " : "",
2995                  (rotation & DRM_REFLECT_Y) ? "FLIPY " : "",
2996                  rotation);
2997
2998         return buf;
2999 }
3000
3001 static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3002 {
3003         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3004         struct drm_device *dev = &dev_priv->drm;
3005         struct intel_plane *intel_plane;
3006
3007         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3008                 struct drm_plane_state *state;
3009                 struct drm_plane *plane = &intel_plane->base;
3010
3011                 if (!plane->state) {
3012                         seq_puts(m, "plane->state is NULL!\n");
3013                         continue;
3014                 }
3015
3016                 state = plane->state;
3017
3018                 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3019                            plane->base.id,
3020                            plane_type(intel_plane->base.type),
3021                            state->crtc_x, state->crtc_y,
3022                            state->crtc_w, state->crtc_h,
3023                            (state->src_x >> 16),
3024                            ((state->src_x & 0xffff) * 15625) >> 10,
3025                            (state->src_y >> 16),
3026                            ((state->src_y & 0xffff) * 15625) >> 10,
3027                            (state->src_w >> 16),
3028                            ((state->src_w & 0xffff) * 15625) >> 10,
3029                            (state->src_h >> 16),
3030                            ((state->src_h & 0xffff) * 15625) >> 10,
3031                            state->fb ? drm_get_format_name(state->fb->pixel_format) : "N/A",
3032                            plane_rotation(state->rotation));
3033         }
3034 }
3035
3036 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3037 {
3038         struct intel_crtc_state *pipe_config;
3039         int num_scalers = intel_crtc->num_scalers;
3040         int i;
3041
3042         pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3043
3044         /* Not all platformas have a scaler */
3045         if (num_scalers) {
3046                 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3047                            num_scalers,
3048                            pipe_config->scaler_state.scaler_users,
3049                            pipe_config->scaler_state.scaler_id);
3050
3051                 for (i = 0; i < SKL_NUM_SCALERS; i++) {
3052                         struct intel_scaler *sc =
3053                                         &pipe_config->scaler_state.scalers[i];
3054
3055                         seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3056                                    i, yesno(sc->in_use), sc->mode);
3057                 }
3058                 seq_puts(m, "\n");
3059         } else {
3060                 seq_puts(m, "\tNo scalers available on this platform\n");
3061         }
3062 }
3063
3064 static int i915_display_info(struct seq_file *m, void *unused)
3065 {
3066         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3067         struct drm_device *dev = &dev_priv->drm;
3068         struct intel_crtc *crtc;
3069         struct drm_connector *connector;
3070
3071         intel_runtime_pm_get(dev_priv);
3072         drm_modeset_lock_all(dev);
3073         seq_printf(m, "CRTC info\n");
3074         seq_printf(m, "---------\n");
3075         for_each_intel_crtc(dev, crtc) {
3076                 bool active;
3077                 struct intel_crtc_state *pipe_config;
3078                 int x, y;
3079
3080                 pipe_config = to_intel_crtc_state(crtc->base.state);
3081
3082                 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3083                            crtc->base.base.id, pipe_name(crtc->pipe),
3084                            yesno(pipe_config->base.active),
3085                            pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3086                            yesno(pipe_config->dither), pipe_config->pipe_bpp);
3087
3088                 if (pipe_config->base.active) {
3089                         intel_crtc_info(m, crtc);
3090
3091                         active = cursor_position(dev_priv, crtc->pipe, &x, &y);
3092                         seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
3093                                    yesno(crtc->cursor_base),
3094                                    x, y, crtc->base.cursor->state->crtc_w,
3095                                    crtc->base.cursor->state->crtc_h,
3096                                    crtc->cursor_addr, yesno(active));
3097                         intel_scaler_info(m, crtc);
3098                         intel_plane_info(m, crtc);
3099                 }
3100
3101                 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3102                            yesno(!crtc->cpu_fifo_underrun_disabled),
3103                            yesno(!crtc->pch_fifo_underrun_disabled));
3104         }
3105
3106         seq_printf(m, "\n");
3107         seq_printf(m, "Connector info\n");
3108         seq_printf(m, "--------------\n");
3109         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3110                 intel_connector_info(m, connector);
3111         }
3112         drm_modeset_unlock_all(dev);
3113         intel_runtime_pm_put(dev_priv);
3114
3115         return 0;
3116 }
3117
3118 static int i915_semaphore_status(struct seq_file *m, void *unused)
3119 {
3120         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3121         struct drm_device *dev = &dev_priv->drm;
3122         struct intel_engine_cs *engine;
3123         int num_rings = INTEL_INFO(dev_priv)->num_rings;
3124         enum intel_engine_id id;
3125         int j, ret;
3126
3127         if (!i915.semaphores) {
3128                 seq_puts(m, "Semaphores are disabled\n");
3129                 return 0;
3130         }
3131
3132         ret = mutex_lock_interruptible(&dev->struct_mutex);
3133         if (ret)
3134                 return ret;
3135         intel_runtime_pm_get(dev_priv);
3136
3137         if (IS_BROADWELL(dev_priv)) {
3138                 struct page *page;
3139                 uint64_t *seqno;
3140
3141                 page = i915_gem_object_get_page(dev_priv->semaphore->obj, 0);
3142
3143                 seqno = (uint64_t *)kmap_atomic(page);
3144                 for_each_engine_id(engine, dev_priv, id) {
3145                         uint64_t offset;
3146
3147                         seq_printf(m, "%s\n", engine->name);
3148
3149                         seq_puts(m, "  Last signal:");
3150                         for (j = 0; j < num_rings; j++) {
3151                                 offset = id * I915_NUM_ENGINES + j;
3152                                 seq_printf(m, "0x%08llx (0x%02llx) ",
3153                                            seqno[offset], offset * 8);
3154                         }
3155                         seq_putc(m, '\n');
3156
3157                         seq_puts(m, "  Last wait:  ");
3158                         for (j = 0; j < num_rings; j++) {
3159                                 offset = id + (j * I915_NUM_ENGINES);
3160                                 seq_printf(m, "0x%08llx (0x%02llx) ",
3161                                            seqno[offset], offset * 8);
3162                         }
3163                         seq_putc(m, '\n');
3164
3165                 }
3166                 kunmap_atomic(seqno);
3167         } else {
3168                 seq_puts(m, "  Last signal:");
3169                 for_each_engine(engine, dev_priv)
3170                         for (j = 0; j < num_rings; j++)
3171                                 seq_printf(m, "0x%08x\n",
3172                                            I915_READ(engine->semaphore.mbox.signal[j]));
3173                 seq_putc(m, '\n');
3174         }
3175
3176         seq_puts(m, "\nSync seqno:\n");
3177         for_each_engine(engine, dev_priv) {
3178                 for (j = 0; j < num_rings; j++)
3179                         seq_printf(m, "  0x%08x ",
3180                                    engine->semaphore.sync_seqno[j]);
3181                 seq_putc(m, '\n');
3182         }
3183         seq_putc(m, '\n');
3184
3185         intel_runtime_pm_put(dev_priv);
3186         mutex_unlock(&dev->struct_mutex);
3187         return 0;
3188 }
3189
3190 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3191 {
3192         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3193         struct drm_device *dev = &dev_priv->drm;
3194         int i;
3195
3196         drm_modeset_lock_all(dev);
3197         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3198                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3199
3200                 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3201                 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3202                            pll->config.crtc_mask, pll->active_mask, yesno(pll->on));
3203                 seq_printf(m, " tracked hardware state:\n");
3204                 seq_printf(m, " dpll:    0x%08x\n", pll->config.hw_state.dpll);
3205                 seq_printf(m, " dpll_md: 0x%08x\n",
3206                            pll->config.hw_state.dpll_md);
3207                 seq_printf(m, " fp0:     0x%08x\n", pll->config.hw_state.fp0);
3208                 seq_printf(m, " fp1:     0x%08x\n", pll->config.hw_state.fp1);
3209                 seq_printf(m, " wrpll:   0x%08x\n", pll->config.hw_state.wrpll);
3210         }
3211         drm_modeset_unlock_all(dev);
3212
3213         return 0;
3214 }
3215
3216 static int i915_wa_registers(struct seq_file *m, void *unused)
3217 {
3218         int i;
3219         int ret;
3220         struct intel_engine_cs *engine;
3221         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3222         struct drm_device *dev = &dev_priv->drm;
3223         struct i915_workarounds *workarounds = &dev_priv->workarounds;
3224         enum intel_engine_id id;
3225
3226         ret = mutex_lock_interruptible(&dev->struct_mutex);
3227         if (ret)
3228                 return ret;
3229
3230         intel_runtime_pm_get(dev_priv);
3231
3232         seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
3233         for_each_engine_id(engine, dev_priv, id)
3234                 seq_printf(m, "HW whitelist count for %s: %d\n",
3235                            engine->name, workarounds->hw_whitelist_count[id]);
3236         for (i = 0; i < workarounds->count; ++i) {
3237                 i915_reg_t addr;
3238                 u32 mask, value, read;
3239                 bool ok;
3240
3241                 addr = workarounds->reg[i].addr;
3242                 mask = workarounds->reg[i].mask;
3243                 value = workarounds->reg[i].value;
3244                 read = I915_READ(addr);
3245                 ok = (value & mask) == (read & mask);
3246                 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3247                            i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
3248         }
3249
3250         intel_runtime_pm_put(dev_priv);
3251         mutex_unlock(&dev->struct_mutex);
3252
3253         return 0;
3254 }
3255
3256 static int i915_ddb_info(struct seq_file *m, void *unused)
3257 {
3258         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3259         struct drm_device *dev = &dev_priv->drm;
3260         struct skl_ddb_allocation *ddb;
3261         struct skl_ddb_entry *entry;
3262         enum pipe pipe;
3263         int plane;
3264
3265         if (INTEL_GEN(dev_priv) < 9)
3266                 return 0;
3267
3268         drm_modeset_lock_all(dev);
3269
3270         ddb = &dev_priv->wm.skl_hw.ddb;
3271
3272         seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3273
3274         for_each_pipe(dev_priv, pipe) {
3275                 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3276
3277                 for_each_plane(dev_priv, pipe, plane) {
3278                         entry = &ddb->plane[pipe][plane];
3279                         seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane + 1,
3280                                    entry->start, entry->end,
3281                                    skl_ddb_entry_size(entry));
3282                 }
3283
3284                 entry = &ddb->plane[pipe][PLANE_CURSOR];
3285                 seq_printf(m, "  %-13s%8u%8u%8u\n", "Cursor", entry->start,
3286                            entry->end, skl_ddb_entry_size(entry));
3287         }
3288
3289         drm_modeset_unlock_all(dev);
3290
3291         return 0;
3292 }
3293
3294 static void drrs_status_per_crtc(struct seq_file *m,
3295                                  struct drm_device *dev,
3296                                  struct intel_crtc *intel_crtc)
3297 {
3298         struct drm_i915_private *dev_priv = to_i915(dev);
3299         struct i915_drrs *drrs = &dev_priv->drrs;
3300         int vrefresh = 0;
3301         struct drm_connector *connector;
3302
3303         drm_for_each_connector(connector, dev) {
3304                 if (connector->state->crtc != &intel_crtc->base)
3305                         continue;
3306
3307                 seq_printf(m, "%s:\n", connector->name);
3308         }
3309
3310         if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3311                 seq_puts(m, "\tVBT: DRRS_type: Static");
3312         else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3313                 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3314         else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3315                 seq_puts(m, "\tVBT: DRRS_type: None");
3316         else
3317                 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3318
3319         seq_puts(m, "\n\n");
3320
3321         if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3322                 struct intel_panel *panel;
3323
3324                 mutex_lock(&drrs->mutex);
3325                 /* DRRS Supported */
3326                 seq_puts(m, "\tDRRS Supported: Yes\n");
3327
3328                 /* disable_drrs() will make drrs->dp NULL */
3329                 if (!drrs->dp) {
3330                         seq_puts(m, "Idleness DRRS: Disabled");
3331                         mutex_unlock(&drrs->mutex);
3332                         return;
3333                 }
3334
3335                 panel = &drrs->dp->attached_connector->panel;
3336                 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3337                                         drrs->busy_frontbuffer_bits);
3338
3339                 seq_puts(m, "\n\t\t");
3340                 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3341                         seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3342                         vrefresh = panel->fixed_mode->vrefresh;
3343                 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3344                         seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3345                         vrefresh = panel->downclock_mode->vrefresh;
3346                 } else {
3347                         seq_printf(m, "DRRS_State: Unknown(%d)\n",
3348                                                 drrs->refresh_rate_type);
3349                         mutex_unlock(&drrs->mutex);
3350                         return;
3351                 }
3352                 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3353
3354                 seq_puts(m, "\n\t\t");
3355                 mutex_unlock(&drrs->mutex);
3356         } else {
3357                 /* DRRS not supported. Print the VBT parameter*/
3358                 seq_puts(m, "\tDRRS Supported : No");
3359         }
3360         seq_puts(m, "\n");
3361 }
3362
3363 static int i915_drrs_status(struct seq_file *m, void *unused)
3364 {
3365         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3366         struct drm_device *dev = &dev_priv->drm;
3367         struct intel_crtc *intel_crtc;
3368         int active_crtc_cnt = 0;
3369
3370         drm_modeset_lock_all(dev);
3371         for_each_intel_crtc(dev, intel_crtc) {
3372                 if (intel_crtc->base.state->active) {
3373                         active_crtc_cnt++;
3374                         seq_printf(m, "\nCRTC %d:  ", active_crtc_cnt);
3375
3376                         drrs_status_per_crtc(m, dev, intel_crtc);
3377                 }
3378         }
3379         drm_modeset_unlock_all(dev);
3380
3381         if (!active_crtc_cnt)
3382                 seq_puts(m, "No active crtc found\n");
3383
3384         return 0;
3385 }
3386
3387 struct pipe_crc_info {
3388         const char *name;
3389         struct drm_i915_private *dev_priv;
3390         enum pipe pipe;
3391 };
3392
3393 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3394 {
3395         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3396         struct drm_device *dev = &dev_priv->drm;
3397         struct intel_encoder *intel_encoder;
3398         struct intel_digital_port *intel_dig_port;
3399         struct drm_connector *connector;
3400
3401         drm_modeset_lock_all(dev);
3402         drm_for_each_connector(connector, dev) {
3403                 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
3404                         continue;
3405
3406                 intel_encoder = intel_attached_encoder(connector);
3407                 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
3408                         continue;
3409
3410                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
3411                 if (!intel_dig_port->dp.can_mst)
3412                         continue;
3413
3414                 seq_printf(m, "MST Source Port %c\n",
3415                            port_name(intel_dig_port->port));
3416                 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3417         }
3418         drm_modeset_unlock_all(dev);
3419         return 0;
3420 }
3421
3422 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3423 {
3424         struct pipe_crc_info *info = inode->i_private;
3425         struct drm_i915_private *dev_priv = info->dev_priv;
3426         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3427
3428         if (info->pipe >= INTEL_INFO(dev_priv)->num_pipes)
3429                 return -ENODEV;
3430
3431         spin_lock_irq(&pipe_crc->lock);
3432
3433         if (pipe_crc->opened) {
3434                 spin_unlock_irq(&pipe_crc->lock);
3435                 return -EBUSY; /* already open */
3436         }
3437
3438         pipe_crc->opened = true;
3439         filep->private_data = inode->i_private;
3440
3441         spin_unlock_irq(&pipe_crc->lock);
3442
3443         return 0;
3444 }
3445
3446 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3447 {
3448         struct pipe_crc_info *info = inode->i_private;
3449         struct drm_i915_private *dev_priv = info->dev_priv;
3450         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3451
3452         spin_lock_irq(&pipe_crc->lock);
3453         pipe_crc->opened = false;
3454         spin_unlock_irq(&pipe_crc->lock);
3455
3456         return 0;
3457 }
3458
3459 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3460 #define PIPE_CRC_LINE_LEN       (6 * 8 + 5 + 1)
3461 /* account for \'0' */
3462 #define PIPE_CRC_BUFFER_LEN     (PIPE_CRC_LINE_LEN + 1)
3463
3464 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
3465 {
3466         assert_spin_locked(&pipe_crc->lock);
3467         return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3468                         INTEL_PIPE_CRC_ENTRIES_NR);
3469 }
3470
3471 static ssize_t
3472 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3473                    loff_t *pos)
3474 {
3475         struct pipe_crc_info *info = filep->private_data;
3476         struct drm_i915_private *dev_priv = info->dev_priv;
3477         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3478         char buf[PIPE_CRC_BUFFER_LEN];
3479         int n_entries;
3480         ssize_t bytes_read;
3481
3482         /*
3483          * Don't allow user space to provide buffers not big enough to hold
3484          * a line of data.
3485          */
3486         if (count < PIPE_CRC_LINE_LEN)
3487                 return -EINVAL;
3488
3489         if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
3490                 return 0;
3491
3492         /* nothing to read */
3493         spin_lock_irq(&pipe_crc->lock);
3494         while (pipe_crc_data_count(pipe_crc) == 0) {
3495                 int ret;
3496
3497                 if (filep->f_flags & O_NONBLOCK) {
3498                         spin_unlock_irq(&pipe_crc->lock);
3499                         return -EAGAIN;
3500                 }
3501
3502                 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3503                                 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3504                 if (ret) {
3505                         spin_unlock_irq(&pipe_crc->lock);
3506                         return ret;
3507                 }
3508         }
3509
3510         /* We now have one or more entries to read */
3511         n_entries = count / PIPE_CRC_LINE_LEN;
3512
3513         bytes_read = 0;
3514         while (n_entries > 0) {
3515                 struct intel_pipe_crc_entry *entry =
3516                         &pipe_crc->entries[pipe_crc->tail];
3517
3518                 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3519                              INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3520                         break;
3521
3522                 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3523                 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3524
3525                 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3526                                        "%8u %8x %8x %8x %8x %8x\n",
3527                                        entry->frame, entry->crc[0],
3528                                        entry->crc[1], entry->crc[2],
3529                                        entry->crc[3], entry->crc[4]);
3530
3531                 spin_unlock_irq(&pipe_crc->lock);
3532
3533                 if (copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN))
3534                         return -EFAULT;
3535
3536                 user_buf += PIPE_CRC_LINE_LEN;
3537                 n_entries--;
3538
3539                 spin_lock_irq(&pipe_crc->lock);
3540         }
3541
3542         spin_unlock_irq(&pipe_crc->lock);
3543
3544         return bytes_read;
3545 }
3546
3547 static const struct file_operations i915_pipe_crc_fops = {
3548         .owner = THIS_MODULE,
3549         .open = i915_pipe_crc_open,
3550         .read = i915_pipe_crc_read,
3551         .release = i915_pipe_crc_release,
3552 };
3553
3554 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3555         {
3556                 .name = "i915_pipe_A_crc",
3557                 .pipe = PIPE_A,
3558         },
3559         {
3560                 .name = "i915_pipe_B_crc",
3561                 .pipe = PIPE_B,
3562         },
3563         {
3564                 .name = "i915_pipe_C_crc",
3565                 .pipe = PIPE_C,
3566         },
3567 };
3568
3569 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3570                                 enum pipe pipe)
3571 {
3572         struct drm_i915_private *dev_priv = to_i915(minor->dev);
3573         struct dentry *ent;
3574         struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3575
3576         info->dev_priv = dev_priv;
3577         ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3578                                   &i915_pipe_crc_fops);
3579         if (!ent)
3580                 return -ENOMEM;
3581
3582         return drm_add_fake_info_node(minor, ent, info);
3583 }
3584
3585 static const char * const pipe_crc_sources[] = {
3586         "none",
3587         "plane1",
3588         "plane2",
3589         "pf",
3590         "pipe",
3591         "TV",
3592         "DP-B",
3593         "DP-C",
3594         "DP-D",
3595         "auto",
3596 };
3597
3598 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3599 {
3600         BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3601         return pipe_crc_sources[source];
3602 }
3603
3604 static int display_crc_ctl_show(struct seq_file *m, void *data)
3605 {
3606         struct drm_i915_private *dev_priv = m->private;
3607         int i;
3608
3609         for (i = 0; i < I915_MAX_PIPES; i++)
3610                 seq_printf(m, "%c %s\n", pipe_name(i),
3611                            pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3612
3613         return 0;
3614 }
3615
3616 static int display_crc_ctl_open(struct inode *inode, struct file *file)
3617 {
3618         return single_open(file, display_crc_ctl_show, inode->i_private);
3619 }
3620
3621 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3622                                  uint32_t *val)
3623 {
3624         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3625                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3626
3627         switch (*source) {
3628         case INTEL_PIPE_CRC_SOURCE_PIPE:
3629                 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3630                 break;
3631         case INTEL_PIPE_CRC_SOURCE_NONE:
3632                 *val = 0;
3633                 break;
3634         default:
3635                 return -EINVAL;
3636         }
3637
3638         return 0;
3639 }
3640
3641 static int i9xx_pipe_crc_auto_source(struct drm_i915_private *dev_priv,
3642                                      enum pipe pipe,
3643                                      enum intel_pipe_crc_source *source)
3644 {
3645         struct drm_device *dev = &dev_priv->drm;
3646         struct intel_encoder *encoder;
3647         struct intel_crtc *crtc;
3648         struct intel_digital_port *dig_port;
3649         int ret = 0;
3650
3651         *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3652
3653         drm_modeset_lock_all(dev);
3654         for_each_intel_encoder(dev, encoder) {
3655                 if (!encoder->base.crtc)
3656                         continue;
3657
3658                 crtc = to_intel_crtc(encoder->base.crtc);
3659
3660                 if (crtc->pipe != pipe)
3661                         continue;
3662
3663                 switch (encoder->type) {
3664                 case INTEL_OUTPUT_TVOUT:
3665                         *source = INTEL_PIPE_CRC_SOURCE_TV;
3666                         break;
3667                 case INTEL_OUTPUT_DP:
3668                 case INTEL_OUTPUT_EDP:
3669                         dig_port = enc_to_dig_port(&encoder->base);
3670                         switch (dig_port->port) {
3671                         case PORT_B:
3672                                 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3673                                 break;
3674                         case PORT_C:
3675                                 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3676                                 break;
3677                         case PORT_D:
3678                                 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3679                                 break;
3680                         default:
3681                                 WARN(1, "nonexisting DP port %c\n",
3682                                      port_name(dig_port->port));
3683                                 break;
3684                         }
3685                         break;
3686                 default:
3687                         break;
3688                 }
3689         }
3690         drm_modeset_unlock_all(dev);
3691
3692         return ret;
3693 }
3694
3695 static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
3696                                 enum pipe pipe,
3697                                 enum intel_pipe_crc_source *source,
3698                                 uint32_t *val)
3699 {
3700         bool need_stable_symbols = false;
3701
3702         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3703                 int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
3704                 if (ret)
3705                         return ret;
3706         }
3707
3708         switch (*source) {
3709         case INTEL_PIPE_CRC_SOURCE_PIPE:
3710                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3711                 break;
3712         case INTEL_PIPE_CRC_SOURCE_DP_B:
3713                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3714                 need_stable_symbols = true;
3715                 break;
3716         case INTEL_PIPE_CRC_SOURCE_DP_C:
3717                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3718                 need_stable_symbols = true;
3719                 break;
3720         case INTEL_PIPE_CRC_SOURCE_DP_D:
3721                 if (!IS_CHERRYVIEW(dev_priv))
3722                         return -EINVAL;
3723                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3724                 need_stable_symbols = true;
3725                 break;
3726         case INTEL_PIPE_CRC_SOURCE_NONE:
3727                 *val = 0;
3728                 break;
3729         default:
3730                 return -EINVAL;
3731         }
3732
3733         /*
3734          * When the pipe CRC tap point is after the transcoders we need
3735          * to tweak symbol-level features to produce a deterministic series of
3736          * symbols for a given frame. We need to reset those features only once
3737          * a frame (instead of every nth symbol):
3738          *   - DC-balance: used to ensure a better clock recovery from the data
3739          *     link (SDVO)
3740          *   - DisplayPort scrambling: used for EMI reduction
3741          */
3742         if (need_stable_symbols) {
3743                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3744
3745                 tmp |= DC_BALANCE_RESET_VLV;
3746                 switch (pipe) {
3747                 case PIPE_A:
3748                         tmp |= PIPE_A_SCRAMBLE_RESET;
3749                         break;
3750                 case PIPE_B:
3751                         tmp |= PIPE_B_SCRAMBLE_RESET;
3752                         break;
3753                 case PIPE_C:
3754                         tmp |= PIPE_C_SCRAMBLE_RESET;
3755                         break;
3756                 default:
3757                         return -EINVAL;
3758                 }
3759                 I915_WRITE(PORT_DFT2_G4X, tmp);
3760         }
3761
3762         return 0;
3763 }
3764
3765 static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
3766                                  enum pipe pipe,
3767                                  enum intel_pipe_crc_source *source,
3768                                  uint32_t *val)
3769 {
3770         bool need_stable_symbols = false;
3771
3772         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3773                 int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
3774                 if (ret)
3775                         return ret;
3776         }
3777
3778         switch (*source) {
3779         case INTEL_PIPE_CRC_SOURCE_PIPE:
3780                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3781                 break;
3782         case INTEL_PIPE_CRC_SOURCE_TV:
3783                 if (!SUPPORTS_TV(dev_priv))
3784                         return -EINVAL;
3785                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3786                 break;
3787         case INTEL_PIPE_CRC_SOURCE_DP_B:
3788                 if (!IS_G4X(dev_priv))
3789                         return -EINVAL;
3790                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3791                 need_stable_symbols = true;
3792                 break;
3793         case INTEL_PIPE_CRC_SOURCE_DP_C:
3794                 if (!IS_G4X(dev_priv))
3795                         return -EINVAL;
3796                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3797                 need_stable_symbols = true;
3798                 break;
3799         case INTEL_PIPE_CRC_SOURCE_DP_D:
3800                 if (!IS_G4X(dev_priv))
3801                         return -EINVAL;
3802                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3803                 need_stable_symbols = true;
3804                 break;
3805         case INTEL_PIPE_CRC_SOURCE_NONE:
3806                 *val = 0;
3807                 break;
3808         default:
3809                 return -EINVAL;
3810         }
3811
3812         /*
3813          * When the pipe CRC tap point is after the transcoders we need
3814          * to tweak symbol-level features to produce a deterministic series of
3815          * symbols for a given frame. We need to reset those features only once
3816          * a frame (instead of every nth symbol):
3817          *   - DC-balance: used to ensure a better clock recovery from the data
3818          *     link (SDVO)
3819          *   - DisplayPort scrambling: used for EMI reduction
3820          */
3821         if (need_stable_symbols) {
3822                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3823
3824                 WARN_ON(!IS_G4X(dev_priv));
3825
3826                 I915_WRITE(PORT_DFT_I9XX,
3827                            I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3828
3829                 if (pipe == PIPE_A)
3830                         tmp |= PIPE_A_SCRAMBLE_RESET;
3831                 else
3832                         tmp |= PIPE_B_SCRAMBLE_RESET;
3833
3834                 I915_WRITE(PORT_DFT2_G4X, tmp);
3835         }
3836
3837         return 0;
3838 }
3839
3840 static void vlv_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
3841                                          enum pipe pipe)
3842 {
3843         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3844
3845         switch (pipe) {
3846         case PIPE_A:
3847                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3848                 break;
3849         case PIPE_B:
3850                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3851                 break;
3852         case PIPE_C:
3853                 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3854                 break;
3855         default:
3856                 return;
3857         }
3858         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3859                 tmp &= ~DC_BALANCE_RESET_VLV;
3860         I915_WRITE(PORT_DFT2_G4X, tmp);
3861
3862 }
3863
3864 static void g4x_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
3865                                          enum pipe pipe)
3866 {
3867         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3868
3869         if (pipe == PIPE_A)
3870                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3871         else
3872                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3873         I915_WRITE(PORT_DFT2_G4X, tmp);
3874
3875         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3876                 I915_WRITE(PORT_DFT_I9XX,
3877                            I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3878         }
3879 }
3880
3881 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3882                                 uint32_t *val)
3883 {
3884         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3885                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3886
3887         switch (*source) {
3888         case INTEL_PIPE_CRC_SOURCE_PLANE1:
3889                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3890                 break;
3891         case INTEL_PIPE_CRC_SOURCE_PLANE2:
3892                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3893                 break;
3894         case INTEL_PIPE_CRC_SOURCE_PIPE:
3895                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3896                 break;
3897         case INTEL_PIPE_CRC_SOURCE_NONE:
3898                 *val = 0;
3899                 break;
3900         default:
3901                 return -EINVAL;
3902         }
3903
3904         return 0;
3905 }
3906
3907 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_i915_private *dev_priv,
3908                                         bool enable)
3909 {
3910         struct drm_device *dev = &dev_priv->drm;
3911         struct intel_crtc *crtc =
3912                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3913         struct intel_crtc_state *pipe_config;
3914         struct drm_atomic_state *state;
3915         int ret = 0;
3916
3917         drm_modeset_lock_all(dev);
3918         state = drm_atomic_state_alloc(dev);
3919         if (!state) {
3920                 ret = -ENOMEM;
3921                 goto out;
3922         }
3923
3924         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
3925         pipe_config = intel_atomic_get_crtc_state(state, crtc);
3926         if (IS_ERR(pipe_config)) {
3927                 ret = PTR_ERR(pipe_config);
3928                 goto out;
3929         }
3930
3931         pipe_config->pch_pfit.force_thru = enable;
3932         if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
3933             pipe_config->pch_pfit.enabled != enable)
3934                 pipe_config->base.connectors_changed = true;
3935
3936         ret = drm_atomic_commit(state);
3937 out:
3938         drm_modeset_unlock_all(dev);
3939         WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
3940         if (ret)
3941                 drm_atomic_state_free(state);
3942 }
3943
3944 static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
3945                                 enum pipe pipe,
3946                                 enum intel_pipe_crc_source *source,
3947                                 uint32_t *val)
3948 {
3949         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3950                 *source = INTEL_PIPE_CRC_SOURCE_PF;
3951
3952         switch (*source) {
3953         case INTEL_PIPE_CRC_SOURCE_PLANE1:
3954                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3955                 break;
3956         case INTEL_PIPE_CRC_SOURCE_PLANE2:
3957                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3958                 break;
3959         case INTEL_PIPE_CRC_SOURCE_PF:
3960                 if (IS_HASWELL(dev_priv) && pipe == PIPE_A)
3961                         hsw_trans_edp_pipe_A_crc_wa(dev_priv, true);
3962
3963                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3964                 break;
3965         case INTEL_PIPE_CRC_SOURCE_NONE:
3966                 *val = 0;
3967                 break;
3968         default:
3969                 return -EINVAL;
3970         }
3971
3972         return 0;
3973 }
3974
3975 static int pipe_crc_set_source(struct drm_i915_private *dev_priv,
3976                                enum pipe pipe,
3977                                enum intel_pipe_crc_source source)
3978 {
3979         struct drm_device *dev = &dev_priv->drm;
3980         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
3981         struct intel_crtc *crtc =
3982                         to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
3983         enum intel_display_power_domain power_domain;
3984         u32 val = 0; /* shut up gcc */
3985         int ret;
3986
3987         if (pipe_crc->source == source)
3988                 return 0;
3989
3990         /* forbid changing the source without going back to 'none' */
3991         if (pipe_crc->source && source)
3992                 return -EINVAL;
3993
3994         power_domain = POWER_DOMAIN_PIPE(pipe);
3995         if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
3996                 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
3997                 return -EIO;
3998         }
3999
4000         if (IS_GEN2(dev_priv))
4001                 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
4002         else if (INTEL_GEN(dev_priv) < 5)
4003                 ret = i9xx_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val);
4004         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4005                 ret = vlv_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val);
4006         else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv))
4007                 ret = ilk_pipe_crc_ctl_reg(&source, &val);
4008         else
4009                 ret = ivb_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val);
4010
4011         if (ret != 0)
4012                 goto out;
4013
4014         /* none -> real source transition */
4015         if (source) {
4016                 struct intel_pipe_crc_entry *entries;
4017
4018                 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4019                                  pipe_name(pipe), pipe_crc_source_name(source));
4020
4021                 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
4022                                   sizeof(pipe_crc->entries[0]),
4023                                   GFP_KERNEL);
4024                 if (!entries) {
4025                         ret = -ENOMEM;
4026                         goto out;
4027                 }
4028
4029                 /*
4030                  * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4031                  * enabled and disabled dynamically based on package C states,
4032                  * user space can't make reliable use of the CRCs, so let's just
4033                  * completely disable it.
4034                  */
4035                 hsw_disable_ips(crtc);
4036
4037                 spin_lock_irq(&pipe_crc->lock);
4038                 kfree(pipe_crc->entries);
4039                 pipe_crc->entries = entries;
4040                 pipe_crc->head = 0;
4041                 pipe_crc->tail = 0;
4042                 spin_unlock_irq(&pipe_crc->lock);
4043         }
4044
4045         pipe_crc->source = source;
4046
4047         I915_WRITE(PIPE_CRC_CTL(pipe), val);
4048         POSTING_READ(PIPE_CRC_CTL(pipe));
4049
4050         /* real source -> none transition */
4051         if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
4052                 struct intel_pipe_crc_entry *entries;
4053                 struct intel_crtc *crtc =
4054                         to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
4055
4056                 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4057                                  pipe_name(pipe));
4058
4059                 drm_modeset_lock(&crtc->base.mutex, NULL);
4060                 if (crtc->base.state->active)
4061                         intel_wait_for_vblank(dev, pipe);
4062                 drm_modeset_unlock(&crtc->base.mutex);
4063
4064                 spin_lock_irq(&pipe_crc->lock);
4065                 entries = pipe_crc->entries;
4066                 pipe_crc->entries = NULL;
4067                 pipe_crc->head = 0;
4068                 pipe_crc->tail = 0;
4069                 spin_unlock_irq(&pipe_crc->lock);
4070
4071                 kfree(entries);
4072
4073                 if (IS_G4X(dev_priv))
4074                         g4x_undo_pipe_scramble_reset(dev_priv, pipe);
4075                 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4076                         vlv_undo_pipe_scramble_reset(dev_priv, pipe);
4077                 else if (IS_HASWELL(dev_priv) && pipe == PIPE_A)
4078                         hsw_trans_edp_pipe_A_crc_wa(dev_priv, false);
4079
4080                 hsw_enable_ips(crtc);
4081         }
4082
4083         ret = 0;
4084
4085 out:
4086         intel_display_power_put(dev_priv, power_domain);
4087
4088         return ret;
4089 }
4090
4091 /*
4092  * Parse pipe CRC command strings:
4093  *   command: wsp* object wsp+ name wsp+ source wsp*
4094  *   object: 'pipe'
4095  *   name: (A | B | C)
4096  *   source: (none | plane1 | plane2 | pf)
4097  *   wsp: (#0x20 | #0x9 | #0xA)+
4098  *
4099  * eg.:
4100  *  "pipe A plane1"  ->  Start CRC computations on plane1 of pipe A
4101  *  "pipe A none"    ->  Stop CRC
4102  */
4103 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
4104 {
4105         int n_words = 0;
4106
4107         while (*buf) {
4108                 char *end;
4109
4110                 /* skip leading white space */
4111                 buf = skip_spaces(buf);
4112                 if (!*buf)
4113                         break;  /* end of buffer */
4114
4115                 /* find end of word */
4116                 for (end = buf; *end && !isspace(*end); end++)
4117                         ;
4118
4119                 if (n_words == max_words) {
4120                         DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4121                                          max_words);
4122                         return -EINVAL; /* ran out of words[] before bytes */
4123                 }
4124
4125                 if (*end)
4126                         *end++ = '\0';
4127                 words[n_words++] = buf;
4128                 buf = end;
4129         }
4130
4131         return n_words;
4132 }
4133
4134 enum intel_pipe_crc_object {
4135         PIPE_CRC_OBJECT_PIPE,
4136 };
4137
4138 static const char * const pipe_crc_objects[] = {
4139         "pipe",
4140 };
4141
4142 static int
4143 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
4144 {
4145         int i;
4146
4147         for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
4148                 if (!strcmp(buf, pipe_crc_objects[i])) {
4149                         *o = i;
4150                         return 0;
4151                     }
4152
4153         return -EINVAL;
4154 }
4155
4156 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
4157 {
4158         const char name = buf[0];
4159
4160         if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
4161                 return -EINVAL;
4162
4163         *pipe = name - 'A';
4164
4165         return 0;
4166 }
4167
4168 static int
4169 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
4170 {
4171         int i;
4172
4173         for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
4174                 if (!strcmp(buf, pipe_crc_sources[i])) {
4175                         *s = i;
4176                         return 0;
4177                     }
4178
4179         return -EINVAL;
4180 }
4181
4182 static int display_crc_ctl_parse(struct drm_i915_private *dev_priv,
4183                                  char *buf, size_t len)
4184 {
4185 #define N_WORDS 3
4186         int n_words;
4187         char *words[N_WORDS];
4188         enum pipe pipe;
4189         enum intel_pipe_crc_object object;
4190         enum intel_pipe_crc_source source;
4191
4192         n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
4193         if (n_words != N_WORDS) {
4194                 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4195                                  N_WORDS);
4196                 return -EINVAL;
4197         }
4198
4199         if (display_crc_ctl_parse_object(words[0], &object) < 0) {
4200                 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
4201                 return -EINVAL;
4202         }
4203
4204         if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
4205                 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
4206                 return -EINVAL;
4207         }
4208
4209         if (display_crc_ctl_parse_source(words[2], &source) < 0) {
4210                 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
4211                 return -EINVAL;
4212         }
4213
4214         return pipe_crc_set_source(dev_priv, pipe, source);
4215 }
4216
4217 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
4218                                      size_t len, loff_t *offp)
4219 {
4220         struct seq_file *m = file->private_data;
4221         struct drm_i915_private *dev_priv = m->private;
4222         char *tmpbuf;
4223         int ret;
4224
4225         if (len == 0)
4226                 return 0;
4227
4228         if (len > PAGE_SIZE - 1) {
4229                 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4230                                  PAGE_SIZE);
4231                 return -E2BIG;
4232         }
4233
4234         tmpbuf = kmalloc(len + 1, GFP_KERNEL);
4235         if (!tmpbuf)
4236                 return -ENOMEM;
4237
4238         if (copy_from_user(tmpbuf, ubuf, len)) {
4239                 ret = -EFAULT;
4240                 goto out;
4241         }
4242         tmpbuf[len] = '\0';
4243
4244         ret = display_crc_ctl_parse(dev_priv, tmpbuf, len);
4245
4246 out:
4247         kfree(tmpbuf);
4248         if (ret < 0)
4249                 return ret;
4250
4251         *offp += len;
4252         return len;
4253 }
4254
4255 static const struct file_operations i915_display_crc_ctl_fops = {
4256         .owner = THIS_MODULE,
4257         .open = display_crc_ctl_open,
4258         .read = seq_read,
4259         .llseek = seq_lseek,
4260         .release = single_release,
4261         .write = display_crc_ctl_write
4262 };
4263
4264 static ssize_t i915_displayport_test_active_write(struct file *file,
4265                                                   const char __user *ubuf,
4266                                                   size_t len, loff_t *offp)
4267 {
4268         char *input_buffer;
4269         int status = 0;
4270         struct drm_device *dev;
4271         struct drm_connector *connector;
4272         struct list_head *connector_list;
4273         struct intel_dp *intel_dp;
4274         int val = 0;
4275
4276         dev = ((struct seq_file *)file->private_data)->private;
4277
4278         connector_list = &dev->mode_config.connector_list;
4279
4280         if (len == 0)
4281                 return 0;
4282
4283         input_buffer = kmalloc(len + 1, GFP_KERNEL);
4284         if (!input_buffer)
4285                 return -ENOMEM;
4286
4287         if (copy_from_user(input_buffer, ubuf, len)) {
4288                 status = -EFAULT;
4289                 goto out;
4290         }
4291
4292         input_buffer[len] = '\0';
4293         DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4294
4295         list_for_each_entry(connector, connector_list, head) {
4296                 if (connector->connector_type !=
4297                     DRM_MODE_CONNECTOR_DisplayPort)
4298                         continue;
4299
4300                 if (connector->status == connector_status_connected &&
4301                     connector->encoder != NULL) {
4302                         intel_dp = enc_to_intel_dp(connector->encoder);
4303                         status = kstrtoint(input_buffer, 10, &val);
4304                         if (status < 0)
4305                                 goto out;
4306                         DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4307                         /* To prevent erroneous activation of the compliance
4308                          * testing code, only accept an actual value of 1 here
4309                          */
4310                         if (val == 1)
4311                                 intel_dp->compliance_test_active = 1;
4312                         else
4313                                 intel_dp->compliance_test_active = 0;
4314                 }
4315         }
4316 out:
4317         kfree(input_buffer);
4318         if (status < 0)
4319                 return status;
4320
4321         *offp += len;
4322         return len;
4323 }
4324
4325 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4326 {
4327         struct drm_device *dev = m->private;
4328         struct drm_connector *connector;
4329         struct list_head *connector_list = &dev->mode_config.connector_list;
4330         struct intel_dp *intel_dp;
4331
4332         list_for_each_entry(connector, connector_list, head) {
4333                 if (connector->connector_type !=
4334                     DRM_MODE_CONNECTOR_DisplayPort)
4335                         continue;
4336
4337                 if (connector->status == connector_status_connected &&
4338                     connector->encoder != NULL) {
4339                         intel_dp = enc_to_intel_dp(connector->encoder);
4340                         if (intel_dp->compliance_test_active)
4341                                 seq_puts(m, "1");
4342                         else
4343                                 seq_puts(m, "0");
4344                 } else
4345                         seq_puts(m, "0");
4346         }
4347
4348         return 0;
4349 }
4350
4351 static int i915_displayport_test_active_open(struct inode *inode,
4352                                              struct file *file)
4353 {
4354         struct drm_i915_private *dev_priv = inode->i_private;
4355
4356         return single_open(file, i915_displayport_test_active_show,
4357                            &dev_priv->drm);
4358 }
4359
4360 static const struct file_operations i915_displayport_test_active_fops = {
4361         .owner = THIS_MODULE,
4362         .open = i915_displayport_test_active_open,
4363         .read = seq_read,
4364         .llseek = seq_lseek,
4365         .release = single_release,
4366         .write = i915_displayport_test_active_write
4367 };
4368
4369 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4370 {
4371         struct drm_device *dev = m->private;
4372         struct drm_connector *connector;
4373         struct list_head *connector_list = &dev->mode_config.connector_list;
4374         struct intel_dp *intel_dp;
4375
4376         list_for_each_entry(connector, connector_list, head) {
4377                 if (connector->connector_type !=
4378                     DRM_MODE_CONNECTOR_DisplayPort)
4379                         continue;
4380
4381                 if (connector->status == connector_status_connected &&
4382                     connector->encoder != NULL) {
4383                         intel_dp = enc_to_intel_dp(connector->encoder);
4384                         seq_printf(m, "%lx", intel_dp->compliance_test_data);
4385                 } else
4386                         seq_puts(m, "0");
4387         }
4388
4389         return 0;
4390 }
4391 static int i915_displayport_test_data_open(struct inode *inode,
4392                                            struct file *file)
4393 {
4394         struct drm_i915_private *dev_priv = inode->i_private;
4395
4396         return single_open(file, i915_displayport_test_data_show,
4397                            &dev_priv->drm);
4398 }
4399
4400 static const struct file_operations i915_displayport_test_data_fops = {
4401         .owner = THIS_MODULE,
4402         .open = i915_displayport_test_data_open,
4403         .read = seq_read,
4404         .llseek = seq_lseek,
4405         .release = single_release
4406 };
4407
4408 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4409 {
4410         struct drm_device *dev = m->private;
4411         struct drm_connector *connector;
4412         struct list_head *connector_list = &dev->mode_config.connector_list;
4413         struct intel_dp *intel_dp;
4414
4415         list_for_each_entry(connector, connector_list, head) {
4416                 if (connector->connector_type !=
4417                     DRM_MODE_CONNECTOR_DisplayPort)
4418                         continue;
4419
4420                 if (connector->status == connector_status_connected &&
4421                     connector->encoder != NULL) {
4422                         intel_dp = enc_to_intel_dp(connector->encoder);
4423                         seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4424                 } else
4425                         seq_puts(m, "0");
4426         }
4427
4428         return 0;
4429 }
4430
4431 static int i915_displayport_test_type_open(struct inode *inode,
4432                                        struct file *file)
4433 {
4434         struct drm_i915_private *dev_priv = inode->i_private;
4435
4436         return single_open(file, i915_displayport_test_type_show,
4437                            &dev_priv->drm);
4438 }
4439
4440 static const struct file_operations i915_displayport_test_type_fops = {
4441         .owner = THIS_MODULE,
4442         .open = i915_displayport_test_type_open,
4443         .read = seq_read,
4444         .llseek = seq_lseek,
4445         .release = single_release
4446 };
4447
4448 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
4449 {
4450         struct drm_i915_private *dev_priv = m->private;
4451         struct drm_device *dev = &dev_priv->drm;
4452         int level;
4453         int num_levels;
4454
4455         if (IS_CHERRYVIEW(dev_priv))
4456                 num_levels = 3;
4457         else if (IS_VALLEYVIEW(dev_priv))
4458                 num_levels = 1;
4459         else
4460                 num_levels = ilk_wm_max_level(dev) + 1;
4461
4462         drm_modeset_lock_all(dev);
4463
4464         for (level = 0; level < num_levels; level++) {
4465                 unsigned int latency = wm[level];
4466
4467                 /*
4468                  * - WM1+ latency values in 0.5us units
4469                  * - latencies are in us on gen9/vlv/chv
4470                  */
4471                 if (INTEL_GEN(dev_priv) >= 9 || IS_VALLEYVIEW(dev_priv) ||
4472                     IS_CHERRYVIEW(dev_priv))
4473                         latency *= 10;
4474                 else if (level > 0)
4475                         latency *= 5;
4476
4477                 seq_printf(m, "WM%d %u (%u.%u usec)\n",
4478                            level, wm[level], latency / 10, latency % 10);
4479         }
4480
4481         drm_modeset_unlock_all(dev);
4482 }
4483
4484 static int pri_wm_latency_show(struct seq_file *m, void *data)
4485 {
4486         struct drm_i915_private *dev_priv = m->private;
4487         const uint16_t *latencies;
4488
4489         if (INTEL_GEN(dev_priv) >= 9)
4490                 latencies = dev_priv->wm.skl_latency;
4491         else
4492                 latencies = dev_priv->wm.pri_latency;
4493
4494         wm_latency_show(m, latencies);
4495
4496         return 0;
4497 }
4498
4499 static int spr_wm_latency_show(struct seq_file *m, void *data)
4500 {
4501         struct drm_i915_private *dev_priv = m->private;
4502         const uint16_t *latencies;
4503
4504         if (INTEL_GEN(dev_priv) >= 9)
4505                 latencies = dev_priv->wm.skl_latency;
4506         else
4507                 latencies = dev_priv->wm.spr_latency;
4508
4509         wm_latency_show(m, latencies);
4510
4511         return 0;
4512 }
4513
4514 static int cur_wm_latency_show(struct seq_file *m, void *data)
4515 {
4516         struct drm_i915_private *dev_priv = m->private;
4517         const uint16_t *latencies;
4518
4519         if (INTEL_GEN(dev_priv) >= 9)
4520                 latencies = dev_priv->wm.skl_latency;
4521         else
4522                 latencies = dev_priv->wm.cur_latency;
4523
4524         wm_latency_show(m, latencies);
4525
4526         return 0;
4527 }
4528
4529 static int pri_wm_latency_open(struct inode *inode, struct file *file)
4530 {
4531         struct drm_i915_private *dev_priv = inode->i_private;
4532
4533         if (INTEL_GEN(dev_priv) < 5)
4534                 return -ENODEV;
4535
4536         return single_open(file, pri_wm_latency_show, dev_priv);
4537 }
4538
4539 static int spr_wm_latency_open(struct inode *inode, struct file *file)
4540 {
4541         struct drm_i915_private *dev_priv = inode->i_private;
4542
4543         if (HAS_GMCH_DISPLAY(dev_priv))
4544                 return -ENODEV;
4545
4546         return single_open(file, spr_wm_latency_show, dev_priv);
4547 }
4548
4549 static int cur_wm_latency_open(struct inode *inode, struct file *file)
4550 {
4551         struct drm_i915_private *dev_priv = inode->i_private;
4552
4553         if (HAS_GMCH_DISPLAY(dev_priv))
4554                 return -ENODEV;
4555
4556         return single_open(file, cur_wm_latency_show, dev_priv);
4557 }
4558
4559 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
4560                                 size_t len, loff_t *offp, uint16_t wm[8])
4561 {
4562         struct seq_file *m = file->private_data;
4563         struct drm_i915_private *dev_priv = m->private;
4564         struct drm_device *dev = &dev_priv->drm;
4565         uint16_t new[8] = { 0 };
4566         int num_levels;
4567         int level;
4568         int ret;
4569         char tmp[32];
4570
4571         if (IS_CHERRYVIEW(dev_priv))
4572                 num_levels = 3;
4573         else if (IS_VALLEYVIEW(dev_priv))
4574                 num_levels = 1;
4575         else
4576                 num_levels = ilk_wm_max_level(dev) + 1;
4577
4578         if (len >= sizeof(tmp))
4579                 return -EINVAL;
4580
4581         if (copy_from_user(tmp, ubuf, len))
4582                 return -EFAULT;
4583
4584         tmp[len] = '\0';
4585
4586         ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4587                      &new[0], &new[1], &new[2], &new[3],
4588                      &new[4], &new[5], &new[6], &new[7]);
4589         if (ret != num_levels)
4590                 return -EINVAL;
4591
4592         drm_modeset_lock_all(dev);
4593
4594         for (level = 0; level < num_levels; level++)
4595                 wm[level] = new[level];
4596
4597         drm_modeset_unlock_all(dev);
4598
4599         return len;
4600 }
4601
4602
4603 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4604                                     size_t len, loff_t *offp)
4605 {
4606         struct seq_file *m = file->private_data;
4607         struct drm_i915_private *dev_priv = m->private;
4608         uint16_t *latencies;
4609
4610         if (INTEL_GEN(dev_priv) >= 9)
4611                 latencies = dev_priv->wm.skl_latency;
4612         else
4613                 latencies = dev_priv->wm.pri_latency;
4614
4615         return wm_latency_write(file, ubuf, len, offp, latencies);
4616 }
4617
4618 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4619                                     size_t len, loff_t *offp)
4620 {
4621         struct seq_file *m = file->private_data;
4622         struct drm_i915_private *dev_priv = m->private;
4623         uint16_t *latencies;
4624
4625         if (INTEL_GEN(dev_priv) >= 9)
4626                 latencies = dev_priv->wm.skl_latency;
4627         else
4628                 latencies = dev_priv->wm.spr_latency;
4629
4630         return wm_latency_write(file, ubuf, len, offp, latencies);
4631 }
4632
4633 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4634                                     size_t len, loff_t *offp)
4635 {
4636         struct seq_file *m = file->private_data;
4637         struct drm_i915_private *dev_priv = m->private;
4638         uint16_t *latencies;
4639
4640         if (INTEL_GEN(dev_priv) >= 9)
4641                 latencies = dev_priv->wm.skl_latency;
4642         else
4643                 latencies = dev_priv->wm.cur_latency;
4644
4645         return wm_latency_write(file, ubuf, len, offp, latencies);
4646 }
4647
4648 static const struct file_operations i915_pri_wm_latency_fops = {
4649         .owner = THIS_MODULE,
4650         .open = pri_wm_latency_open,
4651         .read = seq_read,
4652         .llseek = seq_lseek,
4653         .release = single_release,
4654         .write = pri_wm_latency_write
4655 };
4656
4657 static const struct file_operations i915_spr_wm_latency_fops = {
4658         .owner = THIS_MODULE,
4659         .open = spr_wm_latency_open,
4660         .read = seq_read,
4661         .llseek = seq_lseek,
4662         .release = single_release,
4663         .write = spr_wm_latency_write
4664 };
4665
4666 static const struct file_operations i915_cur_wm_latency_fops = {
4667         .owner = THIS_MODULE,
4668         .open = cur_wm_latency_open,
4669         .read = seq_read,
4670         .llseek = seq_lseek,
4671         .release = single_release,
4672         .write = cur_wm_latency_write
4673 };
4674
4675 static int
4676 i915_wedged_get(void *data, u64 *val)
4677 {
4678         struct drm_i915_private *dev_priv = data;
4679
4680         *val = i915_terminally_wedged(&dev_priv->gpu_error);
4681
4682         return 0;
4683 }
4684
4685 static int
4686 i915_wedged_set(void *data, u64 val)
4687 {
4688         struct drm_i915_private *dev_priv = data;
4689
4690         /*
4691          * There is no safeguard against this debugfs entry colliding
4692          * with the hangcheck calling same i915_handle_error() in
4693          * parallel, causing an explosion. For now we assume that the
4694          * test harness is responsible enough not to inject gpu hangs
4695          * while it is writing to 'i915_wedged'
4696          */
4697
4698         if (i915_reset_in_progress(&dev_priv->gpu_error))
4699                 return -EAGAIN;
4700
4701         intel_runtime_pm_get(dev_priv);
4702
4703         i915_handle_error(dev_priv, val,
4704                           "Manually setting wedged to %llu", val);
4705
4706         intel_runtime_pm_put(dev_priv);
4707
4708         return 0;
4709 }
4710
4711 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4712                         i915_wedged_get, i915_wedged_set,
4713                         "%llu\n");
4714
4715 static int
4716 i915_ring_missed_irq_get(void *data, u64 *val)
4717 {
4718         struct drm_i915_private *dev_priv = data;
4719
4720         *val = dev_priv->gpu_error.missed_irq_rings;
4721         return 0;
4722 }
4723
4724 static int
4725 i915_ring_missed_irq_set(void *data, u64 val)
4726 {
4727         struct drm_i915_private *dev_priv = data;
4728         struct drm_device *dev = &dev_priv->drm;
4729         int ret;
4730
4731         /* Lock against concurrent debugfs callers */
4732         ret = mutex_lock_interruptible(&dev->struct_mutex);
4733         if (ret)
4734                 return ret;
4735         dev_priv->gpu_error.missed_irq_rings = val;
4736         mutex_unlock(&dev->struct_mutex);
4737
4738         return 0;
4739 }
4740
4741 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4742                         i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4743                         "0x%08llx\n");
4744
4745 static int
4746 i915_ring_test_irq_get(void *data, u64 *val)
4747 {
4748         struct drm_i915_private *dev_priv = data;
4749
4750         *val = dev_priv->gpu_error.test_irq_rings;
4751
4752         return 0;
4753 }
4754
4755 static int
4756 i915_ring_test_irq_set(void *data, u64 val)
4757 {
4758         struct drm_i915_private *dev_priv = data;
4759
4760         val &= INTEL_INFO(dev_priv)->ring_mask;
4761         DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4762         dev_priv->gpu_error.test_irq_rings = val;
4763
4764         return 0;
4765 }
4766
4767 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4768                         i915_ring_test_irq_get, i915_ring_test_irq_set,
4769                         "0x%08llx\n");
4770
4771 #define DROP_UNBOUND 0x1
4772 #define DROP_BOUND 0x2
4773 #define DROP_RETIRE 0x4
4774 #define DROP_ACTIVE 0x8
4775 #define DROP_ALL (DROP_UNBOUND | \
4776                   DROP_BOUND | \
4777                   DROP_RETIRE | \
4778                   DROP_ACTIVE)
4779 static int
4780 i915_drop_caches_get(void *data, u64 *val)
4781 {
4782         *val = DROP_ALL;
4783
4784         return 0;
4785 }
4786
4787 static int
4788 i915_drop_caches_set(void *data, u64 val)
4789 {
4790         struct drm_i915_private *dev_priv = data;
4791         struct drm_device *dev = &dev_priv->drm;
4792         int ret;
4793
4794         DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4795
4796         /* No need to check and wait for gpu resets, only libdrm auto-restarts
4797          * on ioctls on -EAGAIN. */
4798         ret = mutex_lock_interruptible(&dev->struct_mutex);
4799         if (ret)
4800                 return ret;
4801
4802         if (val & DROP_ACTIVE) {
4803                 ret = i915_gem_wait_for_idle(dev_priv, true);
4804                 if (ret)
4805                         goto unlock;
4806         }
4807
4808         if (val & (DROP_RETIRE | DROP_ACTIVE))
4809                 i915_gem_retire_requests(dev_priv);
4810
4811         if (val & DROP_BOUND)
4812                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4813
4814         if (val & DROP_UNBOUND)
4815                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4816
4817 unlock:
4818         mutex_unlock(&dev->struct_mutex);
4819
4820         return ret;
4821 }
4822
4823 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4824                         i915_drop_caches_get, i915_drop_caches_set,
4825                         "0x%08llx\n");
4826
4827 static int
4828 i915_max_freq_get(void *data, u64 *val)
4829 {
4830         struct drm_i915_private *dev_priv = data;
4831
4832         if (INTEL_GEN(dev_priv) < 6)
4833                 return -ENODEV;
4834
4835         *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4836         return 0;
4837 }
4838
4839 static int
4840 i915_max_freq_set(void *data, u64 val)
4841 {
4842         struct drm_i915_private *dev_priv = data;
4843         u32 hw_max, hw_min;
4844         int ret;
4845
4846         if (INTEL_GEN(dev_priv) < 6)
4847                 return -ENODEV;
4848
4849         DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4850
4851         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4852         if (ret)
4853                 return ret;
4854
4855         /*
4856          * Turbo will still be enabled, but won't go above the set value.
4857          */
4858         val = intel_freq_opcode(dev_priv, val);
4859
4860         hw_max = dev_priv->rps.max_freq;
4861         hw_min = dev_priv->rps.min_freq;
4862
4863         if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4864                 mutex_unlock(&dev_priv->rps.hw_lock);
4865                 return -EINVAL;
4866         }
4867
4868         dev_priv->rps.max_freq_softlimit = val;
4869
4870         intel_set_rps(dev_priv, val);
4871
4872         mutex_unlock(&dev_priv->rps.hw_lock);
4873
4874         return 0;
4875 }
4876
4877 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4878                         i915_max_freq_get, i915_max_freq_set,
4879                         "%llu\n");
4880
4881 static int
4882 i915_min_freq_get(void *data, u64 *val)
4883 {
4884         struct drm_i915_private *dev_priv = data;
4885
4886         if (INTEL_GEN(dev_priv) < 6)
4887                 return -ENODEV;
4888
4889         *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4890         return 0;
4891 }
4892
4893 static int
4894 i915_min_freq_set(void *data, u64 val)
4895 {
4896         struct drm_i915_private *dev_priv = data;
4897         u32 hw_max, hw_min;
4898         int ret;
4899
4900         if (INTEL_GEN(dev_priv) < 6)
4901                 return -ENODEV;
4902
4903         DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
4904
4905         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4906         if (ret)
4907                 return ret;
4908
4909         /*
4910          * Turbo will still be enabled, but won't go below the set value.
4911          */
4912         val = intel_freq_opcode(dev_priv, val);
4913
4914         hw_max = dev_priv->rps.max_freq;
4915         hw_min = dev_priv->rps.min_freq;
4916
4917         if (val < hw_min ||
4918             val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
4919                 mutex_unlock(&dev_priv->rps.hw_lock);
4920                 return -EINVAL;
4921         }
4922
4923         dev_priv->rps.min_freq_softlimit = val;
4924
4925         intel_set_rps(dev_priv, val);
4926
4927         mutex_unlock(&dev_priv->rps.hw_lock);
4928
4929         return 0;
4930 }
4931
4932 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4933                         i915_min_freq_get, i915_min_freq_set,
4934                         "%llu\n");
4935
4936 static int
4937 i915_cache_sharing_get(void *data, u64 *val)
4938 {
4939         struct drm_i915_private *dev_priv = data;
4940         struct drm_device *dev = &dev_priv->drm;
4941         u32 snpcr;
4942         int ret;
4943
4944         if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
4945                 return -ENODEV;
4946
4947         ret = mutex_lock_interruptible(&dev->struct_mutex);
4948         if (ret)
4949                 return ret;
4950         intel_runtime_pm_get(dev_priv);
4951
4952         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4953
4954         intel_runtime_pm_put(dev_priv);
4955         mutex_unlock(&dev->struct_mutex);
4956
4957         *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
4958
4959         return 0;
4960 }
4961
4962 static int
4963 i915_cache_sharing_set(void *data, u64 val)
4964 {
4965         struct drm_i915_private *dev_priv = data;
4966         u32 snpcr;
4967
4968         if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
4969                 return -ENODEV;
4970
4971         if (val > 3)
4972                 return -EINVAL;
4973
4974         intel_runtime_pm_get(dev_priv);
4975         DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
4976
4977         /* Update the cache sharing policy here as well */
4978         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4979         snpcr &= ~GEN6_MBC_SNPCR_MASK;
4980         snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4981         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4982
4983         intel_runtime_pm_put(dev_priv);
4984         return 0;
4985 }
4986
4987 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4988                         i915_cache_sharing_get, i915_cache_sharing_set,
4989                         "%llu\n");
4990
4991 static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
4992                                           struct sseu_dev_info *sseu)
4993 {
4994         int ss_max = 2;
4995         int ss;
4996         u32 sig1[ss_max], sig2[ss_max];
4997
4998         sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
4999         sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
5000         sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
5001         sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
5002
5003         for (ss = 0; ss < ss_max; ss++) {
5004                 unsigned int eu_cnt;
5005
5006                 if (sig1[ss] & CHV_SS_PG_ENABLE)
5007                         /* skip disabled subslice */
5008                         continue;
5009
5010                 sseu->slice_mask = BIT(0);
5011                 sseu->subslice_mask |= BIT(ss);
5012                 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
5013                          ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
5014                          ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
5015                          ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
5016                 sseu->eu_total += eu_cnt;
5017                 sseu->eu_per_subslice = max_t(unsigned int,
5018                                               sseu->eu_per_subslice, eu_cnt);
5019         }
5020 }
5021
5022 static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
5023                                     struct sseu_dev_info *sseu)
5024 {
5025         int s_max = 3, ss_max = 4;
5026         int s, ss;
5027         u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
5028
5029         /* BXT has a single slice and at most 3 subslices. */
5030         if (IS_BROXTON(dev_priv)) {
5031                 s_max = 1;
5032                 ss_max = 3;
5033         }
5034
5035         for (s = 0; s < s_max; s++) {
5036                 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
5037                 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
5038                 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
5039         }
5040
5041         eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
5042                      GEN9_PGCTL_SSA_EU19_ACK |
5043                      GEN9_PGCTL_SSA_EU210_ACK |
5044                      GEN9_PGCTL_SSA_EU311_ACK;
5045         eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
5046                      GEN9_PGCTL_SSB_EU19_ACK |
5047                      GEN9_PGCTL_SSB_EU210_ACK |
5048                      GEN9_PGCTL_SSB_EU311_ACK;
5049
5050         for (s = 0; s < s_max; s++) {
5051                 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
5052                         /* skip disabled slice */
5053                         continue;
5054
5055                 sseu->slice_mask |= BIT(s);
5056
5057                 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
5058                         sseu->subslice_mask =
5059                                 INTEL_INFO(dev_priv)->sseu.subslice_mask;
5060
5061                 for (ss = 0; ss < ss_max; ss++) {
5062                         unsigned int eu_cnt;
5063
5064                         if (IS_BROXTON(dev_priv)) {
5065                                 if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
5066                                         /* skip disabled subslice */
5067                                         continue;
5068
5069                                 sseu->subslice_mask |= BIT(ss);
5070                         }
5071
5072                         eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
5073                                                eu_mask[ss%2]);
5074                         sseu->eu_total += eu_cnt;
5075                         sseu->eu_per_subslice = max_t(unsigned int,
5076                                                       sseu->eu_per_subslice,
5077                                                       eu_cnt);
5078                 }
5079         }
5080 }
5081
5082 static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
5083                                          struct sseu_dev_info *sseu)
5084 {
5085         u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
5086         int s;
5087
5088         sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK;
5089
5090         if (sseu->slice_mask) {
5091                 sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask;
5092                 sseu->eu_per_subslice =
5093                                 INTEL_INFO(dev_priv)->sseu.eu_per_subslice;
5094                 sseu->eu_total = sseu->eu_per_subslice *
5095                                  sseu_subslice_total(sseu);
5096
5097                 /* subtract fused off EU(s) from enabled slice(s) */
5098                 for (s = 0; s < hweight8(sseu->slice_mask); s++) {
5099                         u8 subslice_7eu =
5100                                 INTEL_INFO(dev_priv)->sseu.subslice_7eu[s];
5101
5102                         sseu->eu_total -= hweight8(subslice_7eu);
5103                 }
5104         }
5105 }
5106
5107 static void i915_print_sseu_info(struct seq_file *m, bool is_available_info,
5108                                  const struct sseu_dev_info *sseu)
5109 {
5110         struct drm_i915_private *dev_priv = node_to_i915(m->private);
5111         const char *type = is_available_info ? "Available" : "Enabled";
5112
5113         seq_printf(m, "  %s Slice Mask: %04x\n", type,
5114                    sseu->slice_mask);
5115         seq_printf(m, "  %s Slice Total: %u\n", type,
5116                    hweight8(sseu->slice_mask));
5117         seq_printf(m, "  %s Subslice Total: %u\n", type,
5118                    sseu_subslice_total(sseu));
5119         seq_printf(m, "  %s Subslice Mask: %04x\n", type,
5120                    sseu->subslice_mask);
5121         seq_printf(m, "  %s Subslice Per Slice: %u\n", type,
5122                    hweight8(sseu->subslice_mask));
5123         seq_printf(m, "  %s EU Total: %u\n", type,
5124                    sseu->eu_total);
5125         seq_printf(m, "  %s EU Per Subslice: %u\n", type,
5126                    sseu->eu_per_subslice);
5127
5128         if (!is_available_info)
5129                 return;
5130
5131         seq_printf(m, "  Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv)));
5132         if (HAS_POOLED_EU(dev_priv))
5133                 seq_printf(m, "  Min EU in pool: %u\n", sseu->min_eu_in_pool);
5134
5135         seq_printf(m, "  Has Slice Power Gating: %s\n",
5136                    yesno(sseu->has_slice_pg));
5137         seq_printf(m, "  Has Subslice Power Gating: %s\n",
5138                    yesno(sseu->has_subslice_pg));
5139         seq_printf(m, "  Has EU Power Gating: %s\n",
5140                    yesno(sseu->has_eu_pg));
5141 }
5142
5143 static int i915_sseu_status(struct seq_file *m, void *unused)
5144 {
5145         struct drm_i915_private *dev_priv = node_to_i915(m->private);
5146         struct sseu_dev_info sseu;
5147
5148         if (INTEL_GEN(dev_priv) < 8)
5149                 return -ENODEV;
5150
5151         seq_puts(m, "SSEU Device Info\n");
5152         i915_print_sseu_info(m, true, &INTEL_INFO(dev_priv)->sseu);
5153
5154         seq_puts(m, "SSEU Device Status\n");
5155         memset(&sseu, 0, sizeof(sseu));
5156
5157         intel_runtime_pm_get(dev_priv);
5158
5159         if (IS_CHERRYVIEW(dev_priv)) {
5160                 cherryview_sseu_device_status(dev_priv, &sseu);
5161         } else if (IS_BROADWELL(dev_priv)) {
5162                 broadwell_sseu_device_status(dev_priv, &sseu);
5163         } else if (INTEL_GEN(dev_priv) >= 9) {
5164                 gen9_sseu_device_status(dev_priv, &sseu);
5165         }
5166
5167         intel_runtime_pm_put(dev_priv);
5168
5169         i915_print_sseu_info(m, false, &sseu);
5170
5171         return 0;
5172 }
5173
5174 static int i915_forcewake_open(struct inode *inode, struct file *file)
5175 {
5176         struct drm_i915_private *dev_priv = inode->i_private;
5177
5178         if (INTEL_GEN(dev_priv) < 6)
5179                 return 0;
5180
5181         intel_runtime_pm_get(dev_priv);
5182         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5183
5184         return 0;
5185 }
5186
5187 static int i915_forcewake_release(struct inode *inode, struct file *file)
5188 {
5189         struct drm_i915_private *dev_priv = inode->i_private;
5190
5191         if (INTEL_GEN(dev_priv) < 6)
5192                 return 0;
5193
5194         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5195         intel_runtime_pm_put(dev_priv);
5196
5197         return 0;
5198 }
5199
5200 static const struct file_operations i915_forcewake_fops = {
5201         .owner = THIS_MODULE,
5202         .open = i915_forcewake_open,
5203         .release = i915_forcewake_release,
5204 };
5205
5206 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5207 {
5208         struct dentry *ent;
5209
5210         ent = debugfs_create_file("i915_forcewake_user",
5211                                   S_IRUSR,
5212                                   root, to_i915(minor->dev),
5213                                   &i915_forcewake_fops);
5214         if (!ent)
5215                 return -ENOMEM;
5216
5217         return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
5218 }
5219
5220 static int i915_debugfs_create(struct dentry *root,
5221                                struct drm_minor *minor,
5222                                const char *name,
5223                                const struct file_operations *fops)
5224 {
5225         struct dentry *ent;
5226
5227         ent = debugfs_create_file(name,
5228                                   S_IRUGO | S_IWUSR,
5229                                   root, to_i915(minor->dev),
5230                                   fops);
5231         if (!ent)
5232                 return -ENOMEM;
5233
5234         return drm_add_fake_info_node(minor, ent, fops);
5235 }
5236
5237 static const struct drm_info_list i915_debugfs_list[] = {
5238         {"i915_capabilities", i915_capabilities, 0},
5239         {"i915_gem_objects", i915_gem_object_info, 0},
5240         {"i915_gem_gtt", i915_gem_gtt_info, 0},
5241         {"i915_gem_pin_display", i915_gem_gtt_info, 0, (void *)1},
5242         {"i915_gem_stolen", i915_gem_stolen_list_info },
5243         {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
5244         {"i915_gem_request", i915_gem_request_info, 0},
5245         {"i915_gem_seqno", i915_gem_seqno_info, 0},
5246         {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
5247         {"i915_gem_interrupt", i915_interrupt_info, 0},
5248         {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5249         {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5250         {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
5251         {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
5252         {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
5253         {"i915_guc_info", i915_guc_info, 0},
5254         {"i915_guc_load_status", i915_guc_load_status_info, 0},
5255         {"i915_guc_log_dump", i915_guc_log_dump, 0},
5256         {"i915_frequency_info", i915_frequency_info, 0},
5257         {"i915_hangcheck_info", i915_hangcheck_info, 0},
5258         {"i915_drpc_info", i915_drpc_info, 0},
5259         {"i915_emon_status", i915_emon_status, 0},
5260         {"i915_ring_freq_table", i915_ring_freq_table, 0},
5261         {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
5262         {"i915_fbc_status", i915_fbc_status, 0},
5263         {"i915_ips_status", i915_ips_status, 0},
5264         {"i915_sr_status", i915_sr_status, 0},
5265         {"i915_opregion", i915_opregion, 0},
5266         {"i915_vbt", i915_vbt, 0},
5267         {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
5268         {"i915_context_status", i915_context_status, 0},
5269         {"i915_dump_lrc", i915_dump_lrc, 0},
5270         {"i915_execlists", i915_execlists, 0},
5271         {"i915_forcewake_domains", i915_forcewake_domains, 0},
5272         {"i915_swizzle_info", i915_swizzle_info, 0},
5273         {"i915_ppgtt_info", i915_ppgtt_info, 0},
5274         {"i915_llc", i915_llc, 0},
5275         {"i915_edp_psr_status", i915_edp_psr_status, 0},
5276         {"i915_sink_crc_eDP1", i915_sink_crc, 0},
5277         {"i915_energy_uJ", i915_energy_uJ, 0},
5278         {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
5279         {"i915_power_domain_info", i915_power_domain_info, 0},
5280         {"i915_dmc_info", i915_dmc_info, 0},
5281         {"i915_display_info", i915_display_info, 0},
5282         {"i915_semaphore_status", i915_semaphore_status, 0},
5283         {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
5284         {"i915_dp_mst_info", i915_dp_mst_info, 0},
5285         {"i915_wa_registers", i915_wa_registers, 0},
5286         {"i915_ddb_info", i915_ddb_info, 0},
5287         {"i915_sseu_status", i915_sseu_status, 0},
5288         {"i915_drrs_status", i915_drrs_status, 0},
5289         {"i915_rps_boost_info", i915_rps_boost_info, 0},
5290 };
5291 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5292
5293 static const struct i915_debugfs_files {
5294         const char *name;
5295         const struct file_operations *fops;
5296 } i915_debugfs_files[] = {
5297         {"i915_wedged", &i915_wedged_fops},
5298         {"i915_max_freq", &i915_max_freq_fops},
5299         {"i915_min_freq", &i915_min_freq_fops},
5300         {"i915_cache_sharing", &i915_cache_sharing_fops},
5301         {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5302         {"i915_ring_test_irq", &i915_ring_test_irq_fops},
5303         {"i915_gem_drop_caches", &i915_drop_caches_fops},
5304         {"i915_error_state", &i915_error_state_fops},
5305         {"i915_next_seqno", &i915_next_seqno_fops},
5306         {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
5307         {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5308         {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5309         {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
5310         {"i915_fbc_false_color", &i915_fbc_fc_fops},
5311         {"i915_dp_test_data", &i915_displayport_test_data_fops},
5312         {"i915_dp_test_type", &i915_displayport_test_type_fops},
5313         {"i915_dp_test_active", &i915_displayport_test_active_fops}
5314 };
5315
5316 void intel_display_crc_init(struct drm_i915_private *dev_priv)
5317 {
5318         enum pipe pipe;
5319
5320         for_each_pipe(dev_priv, pipe) {
5321                 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
5322
5323                 pipe_crc->opened = false;
5324                 spin_lock_init(&pipe_crc->lock);
5325                 init_waitqueue_head(&pipe_crc->wq);
5326         }
5327 }
5328
5329 int i915_debugfs_register(struct drm_i915_private *dev_priv)
5330 {
5331         struct drm_minor *minor = dev_priv->drm.primary;
5332         int ret, i;
5333
5334         ret = i915_forcewake_create(minor->debugfs_root, minor);
5335         if (ret)
5336                 return ret;
5337
5338         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5339                 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5340                 if (ret)
5341                         return ret;
5342         }
5343
5344         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5345                 ret = i915_debugfs_create(minor->debugfs_root, minor,
5346                                           i915_debugfs_files[i].name,
5347                                           i915_debugfs_files[i].fops);
5348                 if (ret)
5349                         return ret;
5350         }
5351
5352         return drm_debugfs_create_files(i915_debugfs_list,
5353                                         I915_DEBUGFS_ENTRIES,
5354                                         minor->debugfs_root, minor);
5355 }
5356
5357 void i915_debugfs_unregister(struct drm_i915_private *dev_priv)
5358 {
5359         struct drm_minor *minor = dev_priv->drm.primary;
5360         int i;
5361
5362         drm_debugfs_remove_files(i915_debugfs_list,
5363                                  I915_DEBUGFS_ENTRIES, minor);
5364
5365         drm_debugfs_remove_files((struct drm_info_list *)&i915_forcewake_fops,
5366                                  1, minor);
5367
5368         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5369                 struct drm_info_list *info_list =
5370                         (struct drm_info_list *)&i915_pipe_crc_data[i];
5371
5372                 drm_debugfs_remove_files(info_list, 1, minor);
5373         }
5374
5375         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5376                 struct drm_info_list *info_list =
5377                         (struct drm_info_list *)i915_debugfs_files[i].fops;
5378
5379                 drm_debugfs_remove_files(info_list, 1, minor);
5380         }
5381 }
5382
5383 struct dpcd_block {
5384         /* DPCD dump start address. */
5385         unsigned int offset;
5386         /* DPCD dump end address, inclusive. If unset, .size will be used. */
5387         unsigned int end;
5388         /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5389         size_t size;
5390         /* Only valid for eDP. */
5391         bool edp;
5392 };
5393
5394 static const struct dpcd_block i915_dpcd_debug[] = {
5395         { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5396         { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5397         { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5398         { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5399         { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5400         { .offset = DP_SET_POWER },
5401         { .offset = DP_EDP_DPCD_REV },
5402         { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5403         { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5404         { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5405 };
5406
5407 static int i915_dpcd_show(struct seq_file *m, void *data)
5408 {
5409         struct drm_connector *connector = m->private;
5410         struct intel_dp *intel_dp =
5411                 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5412         uint8_t buf[16];
5413         ssize_t err;
5414         int i;
5415
5416         if (connector->status != connector_status_connected)
5417                 return -ENODEV;
5418
5419         for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5420                 const struct dpcd_block *b = &i915_dpcd_debug[i];
5421                 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5422
5423                 if (b->edp &&
5424                     connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5425                         continue;
5426
5427                 /* low tech for now */
5428                 if (WARN_ON(size > sizeof(buf)))
5429                         continue;
5430
5431                 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5432                 if (err <= 0) {
5433                         DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5434                                   size, b->offset, err);
5435                         continue;
5436                 }
5437
5438                 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
5439         }
5440
5441         return 0;
5442 }
5443
5444 static int i915_dpcd_open(struct inode *inode, struct file *file)
5445 {
5446         return single_open(file, i915_dpcd_show, inode->i_private);
5447 }
5448
5449 static const struct file_operations i915_dpcd_fops = {
5450         .owner = THIS_MODULE,
5451         .open = i915_dpcd_open,
5452         .read = seq_read,
5453         .llseek = seq_lseek,
5454         .release = single_release,
5455 };
5456
5457 static int i915_panel_show(struct seq_file *m, void *data)
5458 {
5459         struct drm_connector *connector = m->private;
5460         struct intel_dp *intel_dp =
5461                 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5462
5463         if (connector->status != connector_status_connected)
5464                 return -ENODEV;
5465
5466         seq_printf(m, "Panel power up delay: %d\n",
5467                    intel_dp->panel_power_up_delay);
5468         seq_printf(m, "Panel power down delay: %d\n",
5469                    intel_dp->panel_power_down_delay);
5470         seq_printf(m, "Backlight on delay: %d\n",
5471                    intel_dp->backlight_on_delay);
5472         seq_printf(m, "Backlight off delay: %d\n",
5473                    intel_dp->backlight_off_delay);
5474
5475         return 0;
5476 }
5477
5478 static int i915_panel_open(struct inode *inode, struct file *file)
5479 {
5480         return single_open(file, i915_panel_show, inode->i_private);
5481 }
5482
5483 static const struct file_operations i915_panel_fops = {
5484         .owner = THIS_MODULE,
5485         .open = i915_panel_open,
5486         .read = seq_read,
5487         .llseek = seq_lseek,
5488         .release = single_release,
5489 };
5490
5491 /**
5492  * i915_debugfs_connector_add - add i915 specific connector debugfs files
5493  * @connector: pointer to a registered drm_connector
5494  *
5495  * Cleanup will be done by drm_connector_unregister() through a call to
5496  * drm_debugfs_connector_remove().
5497  *
5498  * Returns 0 on success, negative error codes on error.
5499  */
5500 int i915_debugfs_connector_add(struct drm_connector *connector)
5501 {
5502         struct dentry *root = connector->debugfs_entry;
5503
5504         /* The connector must have been registered beforehands. */
5505         if (!root)
5506                 return -ENODEV;
5507
5508         if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5509             connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5510                 debugfs_create_file("i915_dpcd", S_IRUGO, root,
5511                                     connector, &i915_dpcd_fops);
5512
5513         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5514                 debugfs_create_file("i915_panel_timings", S_IRUGO, root,
5515                                     connector, &i915_panel_fops);
5516
5517         return 0;
5518 }