drivers/gpu/drm/i915/i915_debugfs.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *
  27  */
  28
  29 #include <linux/seq_file.h>
  30 #include <linux/circ_buf.h>
  31 #include <linux/ctype.h>
  32 #include <linux/debugfs.h>
  33 #include <linux/slab.h>
  34 #include <linux/export.h>
  35 #include <linux/list_sort.h>
  36 #include <asm/msr-index.h>
  37 #include <drm/drmP.h>
  38 #include "intel_drv.h"
  39 #include "intel_ringbuffer.h"
  40 #include <drm/i915_drm.h>
  41 #include "i915_drv.h"
  42
  43 static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
  44 {
  45         return to_i915(node->minor->dev);
  46 }
  47
  48 /* As the drm_debugfs_init() routines are called before dev->dev_private is
  49  * allocated we need to hook into the minor for release. */
  50 static int
  51 drm_add_fake_info_node(struct drm_minor *minor,
  52                        struct dentry *ent,
  53                        const void *key)
  54 {
  55         struct drm_info_node *node;
  56
  57         node = kmalloc(sizeof(*node), GFP_KERNEL);
  58         if (node == NULL) {
  59                 debugfs_remove(ent);
  60                 return -ENOMEM;
  61         }
  62
  63         node->minor = minor;
  64         node->dent = ent;
  65         node->info_ent = (void *)key;
  66
  67         mutex_lock(&minor->debugfs_lock);
  68         list_add(&node->list, &minor->debugfs_list);
  69         mutex_unlock(&minor->debugfs_lock);
  70
  71         return 0;
  72 }
  73
  74 static int i915_capabilities(struct seq_file *m, void *data)
  75 {
  76         struct drm_i915_private *dev_priv = node_to_i915(m->private);
  77         const struct intel_device_info *info = INTEL_INFO(dev_priv);
  78
  79         seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv));
  80         seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv));
  81 #define PRINT_FLAG(x)  seq_printf(m, #x ": %s\n", yesno(info->x))
  82         DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
  83 #undef PRINT_FLAG
  84
  85         return 0;
  86 }
  87
  88 static char get_active_flag(struct drm_i915_gem_object *obj)
  89 {
  90         return i915_gem_object_is_active(obj) ? '*' : ' ';
  91 }
  92
  93 static char get_pin_flag(struct drm_i915_gem_object *obj)
  94 {
  95         return obj->pin_display ? 'p' : ' ';
  96 }
  97
  98 static char get_tiling_flag(struct drm_i915_gem_object *obj)
  99 {
 100         switch (i915_gem_object_get_tiling(obj)) {
 101         default:
 102         case I915_TILING_NONE: return ' ';
 103         case I915_TILING_X: return 'X';
 104         case I915_TILING_Y: return 'Y';
 105         }
 106 }
 107
 108 static char get_global_flag(struct drm_i915_gem_object *obj)
 109 {
 110         return !list_empty(&obj->userfault_link) ? 'g' : ' ';
 111 }
 112
 113 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
 114 {
 115         return obj->mm.mapping ? 'M' : ' ';
 116 }
 117
 118 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
 119 {
 120         u64 size = 0;
 121         struct i915_vma *vma;
 122
 123         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 124                 if (i915_vma_is_ggtt(vma) && drm_mm_node_allocated(&vma->node))
 125                         size += vma->node.size;
 126         }
 127
 128         return size;
 129 }
 130
 131 static void
 132 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
 133 {
 134         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
 135         struct intel_engine_cs *engine;
 136         struct i915_vma *vma;
 137         unsigned int frontbuffer_bits;
 138         int pin_count = 0;
 139
 140         lockdep_assert_held(&obj->base.dev->struct_mutex);
 141
 142         seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x %s%s%s",
 143                    &obj->base,
 144                    get_active_flag(obj),
 145                    get_pin_flag(obj),
 146                    get_tiling_flag(obj),
 147                    get_global_flag(obj),
 148                    get_pin_mapped_flag(obj),
 149                    obj->base.size / 1024,
 150                    obj->base.read_domains,
 151                    obj->base.write_domain,
 152                    i915_cache_level_str(dev_priv, obj->cache_level),
 153                    obj->mm.dirty ? " dirty" : "",
 154                    obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : "");
 155         if (obj->base.name)
 156                 seq_printf(m, " (name: %d)", obj->base.name);
 157         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 158                 if (i915_vma_is_pinned(vma))
 159                         pin_count++;
 160         }
 161         seq_printf(m, " (pinned x %d)", pin_count);
 162         if (obj->pin_display)
 163                 seq_printf(m, " (display)");
 164         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 165                 if (!drm_mm_node_allocated(&vma->node))
 166                         continue;
 167
 168                 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
 169                            i915_vma_is_ggtt(vma) ? "g" : "pp",
 170                            vma->node.start, vma->node.size);
 171                 if (i915_vma_is_ggtt(vma))
 172                         seq_printf(m, ", type: %u", vma->ggtt_view.type);
 173                 if (vma->fence)
 174                         seq_printf(m, " , fence: %d%s",
 175                                    vma->fence->id,
 176                                    i915_gem_active_isset(&vma->last_fence) ? "*" : "");
 177                 seq_puts(m, ")");
 178         }
 179         if (obj->stolen)
 180                 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
 181
 182         engine = i915_gem_object_last_write_engine(obj);
 183         if (engine)
 184                 seq_printf(m, " (%s)", engine->name);
 185
 186         frontbuffer_bits = atomic_read(&obj->frontbuffer_bits);
 187         if (frontbuffer_bits)
 188                 seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits);
 189 }
 190
 191 static int obj_rank_by_stolen(void *priv,
 192                               struct list_head *A, struct list_head *B)
 193 {
 194         struct drm_i915_gem_object *a =
 195                 container_of(A, struct drm_i915_gem_object, obj_exec_link);
 196         struct drm_i915_gem_object *b =
 197                 container_of(B, struct drm_i915_gem_object, obj_exec_link);
 198
 199         if (a->stolen->start < b->stolen->start)
 200                 return -1;
 201         if (a->stolen->start > b->stolen->start)
 202                 return 1;
 203         return 0;
 204 }
 205
 206 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
 207 {
 208         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 209         struct drm_device *dev = &dev_priv->drm;
 210         struct drm_i915_gem_object *obj;
 211         u64 total_obj_size, total_gtt_size;
 212         LIST_HEAD(stolen);
 213         int count, ret;
 214
 215         ret = mutex_lock_interruptible(&dev->struct_mutex);
 216         if (ret)
 217                 return ret;
 218
 219         total_obj_size = total_gtt_size = count = 0;
 220         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 221                 if (obj->stolen == NULL)
 222                         continue;
 223
 224                 list_add(&obj->obj_exec_link, &stolen);
 225
 226                 total_obj_size += obj->base.size;
 227                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 228                 count++;
 229         }
 230         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 231                 if (obj->stolen == NULL)
 232                         continue;
 233
 234                 list_add(&obj->obj_exec_link, &stolen);
 235
 236                 total_obj_size += obj->base.size;
 237                 count++;
 238         }
 239         list_sort(NULL, &stolen, obj_rank_by_stolen);
 240         seq_puts(m, "Stolen:\n");
 241         while (!list_empty(&stolen)) {
 242                 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
 243                 seq_puts(m, "   ");
 244                 describe_obj(m, obj);
 245                 seq_putc(m, '\n');
 246                 list_del_init(&obj->obj_exec_link);
 247         }
 248         mutex_unlock(&dev->struct_mutex);
 249
 250         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 251                    count, total_obj_size, total_gtt_size);
 252         return 0;
 253 }
 254
 255 struct file_stats {
 256         struct drm_i915_file_private *file_priv;
 257         unsigned long count;
 258         u64 total, unbound;
 259         u64 global, shared;
 260         u64 active, inactive;
 261 };
 262
 263 static int per_file_stats(int id, void *ptr, void *data)
 264 {
 265         struct drm_i915_gem_object *obj = ptr;
 266         struct file_stats *stats = data;
 267         struct i915_vma *vma;
 268
 269         stats->count++;
 270         stats->total += obj->base.size;
 271         if (!obj->bind_count)
 272                 stats->unbound += obj->base.size;
 273         if (obj->base.name || obj->base.dma_buf)
 274                 stats->shared += obj->base.size;
 275
 276         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 277                 if (!drm_mm_node_allocated(&vma->node))
 278                         continue;
 279
 280                 if (i915_vma_is_ggtt(vma)) {
 281                         stats->global += vma->node.size;
 282                 } else {
 283                         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm);
 284
 285                         if (ppgtt->base.file != stats->file_priv)
 286                                 continue;
 287                 }
 288
 289                 if (i915_vma_is_active(vma))
 290                         stats->active += vma->node.size;
 291                 else
 292                         stats->inactive += vma->node.size;
 293         }
 294
 295         return 0;
 296 }
 297
 298 #define print_file_stats(m, name, stats) do { \
 299         if (stats.count) \
 300                 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
 301                            name, \
 302                            stats.count, \
 303                            stats.total, \
 304                            stats.active, \
 305                            stats.inactive, \
 306                            stats.global, \
 307                            stats.shared, \
 308                            stats.unbound); \
 309 } while (0)
 310
 311 static void print_batch_pool_stats(struct seq_file *m,
 312                                    struct drm_i915_private *dev_priv)
 313 {
 314         struct drm_i915_gem_object *obj;
 315         struct file_stats stats;
 316         struct intel_engine_cs *engine;
 317         enum intel_engine_id id;
 318         int j;
 319
 320         memset(&stats, 0, sizeof(stats));
 321
 322         for_each_engine(engine, dev_priv, id) {
 323                 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
 324                         list_for_each_entry(obj,
 325                                             &engine->batch_pool.cache_list[j],
 326                                             batch_pool_link)
 327                                 per_file_stats(0, obj, &stats);
 328                 }
 329         }
 330
 331         print_file_stats(m, "[k]batch pool", stats);
 332 }
 333
 334 static int per_file_ctx_stats(int id, void *ptr, void *data)
 335 {
 336         struct i915_gem_context *ctx = ptr;
 337         int n;
 338
 339         for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) {
 340                 if (ctx->engine[n].state)
 341                         per_file_stats(0, ctx->engine[n].state->obj, data);
 342                 if (ctx->engine[n].ring)
 343                         per_file_stats(0, ctx->engine[n].ring->vma->obj, data);
 344         }
 345
 346         return 0;
 347 }
 348
 349 static void print_context_stats(struct seq_file *m,
 350                                 struct drm_i915_private *dev_priv)
 351 {
 352         struct drm_device *dev = &dev_priv->drm;
 353         struct file_stats stats;
 354         struct drm_file *file;
 355
 356         memset(&stats, 0, sizeof(stats));
 357
 358         mutex_lock(&dev->struct_mutex);
 359         if (dev_priv->kernel_context)
 360                 per_file_ctx_stats(0, dev_priv->kernel_context, &stats);
 361
 362         list_for_each_entry(file, &dev->filelist, lhead) {
 363                 struct drm_i915_file_private *fpriv = file->driver_priv;
 364                 idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats);
 365         }
 366         mutex_unlock(&dev->struct_mutex);
 367
 368         print_file_stats(m, "[k]contexts", stats);
 369 }
 370
 371 static int i915_gem_object_info(struct seq_file *m, void *data)
 372 {
 373         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 374         struct drm_device *dev = &dev_priv->drm;
 375         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 376         u32 count, mapped_count, purgeable_count, dpy_count;
 377         u64 size, mapped_size, purgeable_size, dpy_size;
 378         struct drm_i915_gem_object *obj;
 379         struct drm_file *file;
 380         int ret;
 381
 382         ret = mutex_lock_interruptible(&dev->struct_mutex);
 383         if (ret)
 384                 return ret;
 385
 386         seq_printf(m, "%u objects, %llu bytes\n",
 387                    dev_priv->mm.object_count,
 388                    dev_priv->mm.object_memory);
 389
 390         size = count = 0;
 391         mapped_size = mapped_count = 0;
 392         purgeable_size = purgeable_count = 0;
 393         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 394                 size += obj->base.size;
 395                 ++count;
 396
 397                 if (obj->mm.madv == I915_MADV_DONTNEED) {
 398                         purgeable_size += obj->base.size;
 399                         ++purgeable_count;
 400                 }
 401
 402                 if (obj->mm.mapping) {
 403                         mapped_count++;
 404                         mapped_size += obj->base.size;
 405                 }
 406         }
 407         seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
 408
 409         size = count = dpy_size = dpy_count = 0;
 410         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 411                 size += obj->base.size;
 412                 ++count;
 413
 414                 if (obj->pin_display) {
 415                         dpy_size += obj->base.size;
 416                         ++dpy_count;
 417                 }
 418
 419                 if (obj->mm.madv == I915_MADV_DONTNEED) {
 420                         purgeable_size += obj->base.size;
 421                         ++purgeable_count;
 422                 }
 423
 424                 if (obj->mm.mapping) {
 425                         mapped_count++;
 426                         mapped_size += obj->base.size;
 427                 }
 428         }
 429         seq_printf(m, "%u bound objects, %llu bytes\n",
 430                    count, size);
 431         seq_printf(m, "%u purgeable objects, %llu bytes\n",
 432                    purgeable_count, purgeable_size);
 433         seq_printf(m, "%u mapped objects, %llu bytes\n",
 434                    mapped_count, mapped_size);
 435         seq_printf(m, "%u display objects (pinned), %llu bytes\n",
 436                    dpy_count, dpy_size);
 437
 438         seq_printf(m, "%llu [%llu] gtt total\n",
 439                    ggtt->base.total, ggtt->mappable_end - ggtt->base.start);
 440
 441         seq_putc(m, '\n');
 442         print_batch_pool_stats(m, dev_priv);
 443         mutex_unlock(&dev->struct_mutex);
 444
 445         mutex_lock(&dev->filelist_mutex);
 446         print_context_stats(m, dev_priv);
 447         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
 448                 struct file_stats stats;
 449                 struct drm_i915_file_private *file_priv = file->driver_priv;
 450                 struct drm_i915_gem_request *request;
 451                 struct task_struct *task;
 452
 453                 memset(&stats, 0, sizeof(stats));
 454                 stats.file_priv = file->driver_priv;
 455                 spin_lock(&file->table_lock);
 456                 idr_for_each(&file->object_idr, per_file_stats, &stats);
 457                 spin_unlock(&file->table_lock);
 458                 /*
 459                  * Although we have a valid reference on file->pid, that does
 460                  * not guarantee that the task_struct who called get_pid() is
 461                  * still alive (e.g. get_pid(current) => fork() => exit()).
 462                  * Therefore, we need to protect this ->comm access using RCU.
 463                  */
 464                 mutex_lock(&dev->struct_mutex);
 465                 request = list_first_entry_or_null(&file_priv->mm.request_list,
 466                                                    struct drm_i915_gem_request,
 467                                                    client_list);
 468                 rcu_read_lock();
 469                 task = pid_task(request && request->ctx->pid ?
 470                                 request->ctx->pid : file->pid,
 471                                 PIDTYPE_PID);
 472                 print_file_stats(m, task ? task->comm : "<unknown>", stats);
 473                 rcu_read_unlock();
 474                 mutex_unlock(&dev->struct_mutex);
 475         }
 476         mutex_unlock(&dev->filelist_mutex);
 477
 478         return 0;
 479 }
 480
 481 static int i915_gem_gtt_info(struct seq_file *m, void *data)
 482 {
 483         struct drm_info_node *node = m->private;
 484         struct drm_i915_private *dev_priv = node_to_i915(node);
 485         struct drm_device *dev = &dev_priv->drm;
 486         bool show_pin_display_only = !!node->info_ent->data;
 487         struct drm_i915_gem_object *obj;
 488         u64 total_obj_size, total_gtt_size;
 489         int count, ret;
 490
 491         ret = mutex_lock_interruptible(&dev->struct_mutex);
 492         if (ret)
 493                 return ret;
 494
 495         total_obj_size = total_gtt_size = count = 0;
 496         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 497                 if (show_pin_display_only && !obj->pin_display)
 498                         continue;
 499
 500                 seq_puts(m, "   ");
 501                 describe_obj(m, obj);
 502                 seq_putc(m, '\n');
 503                 total_obj_size += obj->base.size;
 504                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 505                 count++;
 506         }
 507
 508         mutex_unlock(&dev->struct_mutex);
 509
 510         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 511                    count, total_obj_size, total_gtt_size);
 512
 513         return 0;
 514 }
 515
 516 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
 517 {
 518         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 519         struct drm_device *dev = &dev_priv->drm;
 520         struct intel_crtc *crtc;
 521         int ret;
 522
 523         ret = mutex_lock_interruptible(&dev->struct_mutex);
 524         if (ret)
 525                 return ret;
 526
 527         for_each_intel_crtc(dev, crtc) {
 528                 const char pipe = pipe_name(crtc->pipe);
 529                 const char plane = plane_name(crtc->plane);
 530                 struct intel_flip_work *work;
 531
 532                 spin_lock_irq(&dev->event_lock);
 533                 work = crtc->flip_work;
 534                 if (work == NULL) {
 535                         seq_printf(m, "No flip due on pipe %c (plane %c)\n",
 536                                    pipe, plane);
 537                 } else {
 538                         u32 pending;
 539                         u32 addr;
 540
 541                         pending = atomic_read(&work->pending);
 542                         if (pending) {
 543                                 seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n",
 544                                            pipe, plane);
 545                         } else {
 546                                 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
 547                                            pipe, plane);
 548                         }
 549                         if (work->flip_queued_req) {
 550                                 struct intel_engine_cs *engine = i915_gem_request_get_engine(work->flip_queued_req);
 551
 552                                 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
 553                                            engine->name,
 554                                            i915_gem_request_get_seqno(work->flip_queued_req),
 555                                            dev_priv->gt.global_timeline.next_seqno,
 556                                            intel_engine_get_seqno(engine),
 557                                            i915_gem_request_completed(work->flip_queued_req));
 558                         } else
 559                                 seq_printf(m, "Flip not associated with any ring\n");
 560                         seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
 561                                    work->flip_queued_vblank,
 562                                    work->flip_ready_vblank,
 563                                    intel_crtc_get_vblank_counter(crtc));
 564                         seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
 565
 566                         if (INTEL_GEN(dev_priv) >= 4)
 567                                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
 568                         else
 569                                 addr = I915_READ(DSPADDR(crtc->plane));
 570                         seq_printf(m, "Current scanout address 0x%08x\n", addr);
 571
 572                         if (work->pending_flip_obj) {
 573                                 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
 574                                 seq_printf(m, "MMIO update completed? %d\n",  addr == work->gtt_offset);
 575                         }
 576                 }
 577                 spin_unlock_irq(&dev->event_lock);
 578         }
 579
 580         mutex_unlock(&dev->struct_mutex);
 581
 582         return 0;
 583 }
 584
 585 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
 586 {
 587         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 588         struct drm_device *dev = &dev_priv->drm;
 589         struct drm_i915_gem_object *obj;
 590         struct intel_engine_cs *engine;
 591         enum intel_engine_id id;
 592         int total = 0;
 593         int ret, j;
 594
 595         ret = mutex_lock_interruptible(&dev->struct_mutex);
 596         if (ret)
 597                 return ret;
 598
 599         for_each_engine(engine, dev_priv, id) {
 600                 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
 601                         int count;
 602
 603                         count = 0;
 604                         list_for_each_entry(obj,
 605                                             &engine->batch_pool.cache_list[j],
 606                                             batch_pool_link)
 607                                 count++;
 608                         seq_printf(m, "%s cache[%d]: %d objects\n",
 609                                    engine->name, j, count);
 610
 611                         list_for_each_entry(obj,
 612                                             &engine->batch_pool.cache_list[j],
 613                                             batch_pool_link) {
 614                                 seq_puts(m, "   ");
 615                                 describe_obj(m, obj);
 616                                 seq_putc(m, '\n');
 617                         }
 618
 619                         total += count;
 620                 }
 621         }
 622
 623         seq_printf(m, "total: %d\n", total);
 624
 625         mutex_unlock(&dev->struct_mutex);
 626
 627         return 0;
 628 }
 629
 630 static void print_request(struct seq_file *m,
 631                           struct drm_i915_gem_request *rq,
 632                           const char *prefix)
 633 {
 634         struct pid *pid = rq->ctx->pid;
 635         struct task_struct *task;
 636
 637         rcu_read_lock();
 638         task = pid ? pid_task(pid, PIDTYPE_PID) : NULL;
 639         seq_printf(m, "%s%x [%x:%x] @ %d: %s [%d]\n", prefix,
 640                    rq->global_seqno, rq->ctx->hw_id, rq->fence.seqno,
 641                    jiffies_to_msecs(jiffies - rq->emitted_jiffies),
 642                    task ? task->comm : "<unknown>",
 643                    task ? task->pid : -1);
 644         rcu_read_unlock();
 645 }
 646
 647 static int i915_gem_request_info(struct seq_file *m, void *data)
 648 {
 649         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 650         struct drm_device *dev = &dev_priv->drm;
 651         struct drm_i915_gem_request *req;
 652         struct intel_engine_cs *engine;
 653         enum intel_engine_id id;
 654         int ret, any;
 655
 656         ret = mutex_lock_interruptible(&dev->struct_mutex);
 657         if (ret)
 658                 return ret;
 659
 660         any = 0;
 661         for_each_engine(engine, dev_priv, id) {
 662                 int count;
 663
 664                 count = 0;
 665                 list_for_each_entry(req, &engine->timeline->requests, link)
 666                         count++;
 667                 if (count == 0)
 668                         continue;
 669
 670                 seq_printf(m, "%s requests: %d\n", engine->name, count);
 671                 list_for_each_entry(req, &engine->timeline->requests, link)
 672                         print_request(m, req, "    ");
 673
 674                 any++;
 675         }
 676         mutex_unlock(&dev->struct_mutex);
 677
 678         if (any == 0)
 679                 seq_puts(m, "No requests\n");
 680
 681         return 0;
 682 }
 683
 684 static void i915_ring_seqno_info(struct seq_file *m,
 685                                  struct intel_engine_cs *engine)
 686 {
 687         struct intel_breadcrumbs *b = &engine->breadcrumbs;
 688         struct rb_node *rb;
 689
 690         seq_printf(m, "Current sequence (%s): %x\n",
 691                    engine->name, intel_engine_get_seqno(engine));
 692
 693         spin_lock(&b->lock);
 694         for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
 695                 struct intel_wait *w = container_of(rb, typeof(*w), node);
 696
 697                 seq_printf(m, "Waiting (%s): %s [%d] on %x\n",
 698                            engine->name, w->tsk->comm, w->tsk->pid, w->seqno);
 699         }
 700         spin_unlock(&b->lock);
 701 }
 702
 703 static int i915_gem_seqno_info(struct seq_file *m, void *data)
 704 {
 705         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 706         struct intel_engine_cs *engine;
 707         enum intel_engine_id id;
 708
 709         for_each_engine(engine, dev_priv, id)
 710                 i915_ring_seqno_info(m, engine);
 711
 712         return 0;
 713 }
 714
 715
 716 static int i915_interrupt_info(struct seq_file *m, void *data)
 717 {
 718         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 719         struct intel_engine_cs *engine;
 720         enum intel_engine_id id;
 721         int i, pipe;
 722
 723         intel_runtime_pm_get(dev_priv);
 724
 725         if (IS_CHERRYVIEW(dev_priv)) {
 726                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 727                            I915_READ(GEN8_MASTER_IRQ));
 728
 729                 seq_printf(m, "Display IER:\t%08x\n",
 730                            I915_READ(VLV_IER));
 731                 seq_printf(m, "Display IIR:\t%08x\n",
 732                            I915_READ(VLV_IIR));
 733                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 734                            I915_READ(VLV_IIR_RW));
 735                 seq_printf(m, "Display IMR:\t%08x\n",
 736                            I915_READ(VLV_IMR));
 737                 for_each_pipe(dev_priv, pipe) {
 738                         enum intel_display_power_domain power_domain;
 739
 740                         power_domain = POWER_DOMAIN_PIPE(pipe);
 741                         if (!intel_display_power_get_if_enabled(dev_priv,
 742                                                                 power_domain)) {
 743                                 seq_printf(m, "Pipe %c power disabled\n",
 744                                            pipe_name(pipe));
 745                                 continue;
 746                         }
 747
 748                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 749                                    pipe_name(pipe),
 750                                    I915_READ(PIPESTAT(pipe)));
 751
 752                         intel_display_power_put(dev_priv, power_domain);
 753                 }
 754
 755                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 756                 seq_printf(m, "Port hotplug:\t%08x\n",
 757                            I915_READ(PORT_HOTPLUG_EN));
 758                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 759                            I915_READ(VLV_DPFLIPSTAT));
 760                 seq_printf(m, "DPINVGTT:\t%08x\n",
 761                            I915_READ(DPINVGTT));
 762                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 763
 764                 for (i = 0; i < 4; i++) {
 765                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 766                                    i, I915_READ(GEN8_GT_IMR(i)));
 767                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 768                                    i, I915_READ(GEN8_GT_IIR(i)));
 769                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 770                                    i, I915_READ(GEN8_GT_IER(i)));
 771                 }
 772
 773                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 774                            I915_READ(GEN8_PCU_IMR));
 775                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 776                            I915_READ(GEN8_PCU_IIR));
 777                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 778                            I915_READ(GEN8_PCU_IER));
 779         } else if (INTEL_GEN(dev_priv) >= 8) {
 780                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 781                            I915_READ(GEN8_MASTER_IRQ));
 782
 783                 for (i = 0; i < 4; i++) {
 784                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 785                                    i, I915_READ(GEN8_GT_IMR(i)));
 786                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 787                                    i, I915_READ(GEN8_GT_IIR(i)));
 788                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 789                                    i, I915_READ(GEN8_GT_IER(i)));
 790                 }
 791
 792                 for_each_pipe(dev_priv, pipe) {
 793                         enum intel_display_power_domain power_domain;
 794
 795                         power_domain = POWER_DOMAIN_PIPE(pipe);
 796                         if (!intel_display_power_get_if_enabled(dev_priv,
 797                                                                 power_domain)) {
 798                                 seq_printf(m, "Pipe %c power disabled\n",
 799                                            pipe_name(pipe));
 800                                 continue;
 801                         }
 802                         seq_printf(m, "Pipe %c IMR:\t%08x\n",
 803                                    pipe_name(pipe),
 804                                    I915_READ(GEN8_DE_PIPE_IMR(pipe)));
 805                         seq_printf(m, "Pipe %c IIR:\t%08x\n",
 806                                    pipe_name(pipe),
 807                                    I915_READ(GEN8_DE_PIPE_IIR(pipe)));
 808                         seq_printf(m, "Pipe %c IER:\t%08x\n",
 809                                    pipe_name(pipe),
 810                                    I915_READ(GEN8_DE_PIPE_IER(pipe)));
 811
 812                         intel_display_power_put(dev_priv, power_domain);
 813                 }
 814
 815                 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
 816                            I915_READ(GEN8_DE_PORT_IMR));
 817                 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
 818                            I915_READ(GEN8_DE_PORT_IIR));
 819                 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
 820                            I915_READ(GEN8_DE_PORT_IER));
 821
 822                 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
 823                            I915_READ(GEN8_DE_MISC_IMR));
 824                 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
 825                            I915_READ(GEN8_DE_MISC_IIR));
 826                 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
 827                            I915_READ(GEN8_DE_MISC_IER));
 828
 829                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 830                            I915_READ(GEN8_PCU_IMR));
 831                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 832                            I915_READ(GEN8_PCU_IIR));
 833                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 834                            I915_READ(GEN8_PCU_IER));
 835         } else if (IS_VALLEYVIEW(dev_priv)) {
 836                 seq_printf(m, "Display IER:\t%08x\n",
 837                            I915_READ(VLV_IER));
 838                 seq_printf(m, "Display IIR:\t%08x\n",
 839                            I915_READ(VLV_IIR));
 840                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 841                            I915_READ(VLV_IIR_RW));
 842                 seq_printf(m, "Display IMR:\t%08x\n",
 843                            I915_READ(VLV_IMR));
 844                 for_each_pipe(dev_priv, pipe)
 845                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 846                                    pipe_name(pipe),
 847                                    I915_READ(PIPESTAT(pipe)));
 848
 849                 seq_printf(m, "Master IER:\t%08x\n",
 850                            I915_READ(VLV_MASTER_IER));
 851
 852                 seq_printf(m, "Render IER:\t%08x\n",
 853                            I915_READ(GTIER));
 854                 seq_printf(m, "Render IIR:\t%08x\n",
 855                            I915_READ(GTIIR));
 856                 seq_printf(m, "Render IMR:\t%08x\n",
 857                            I915_READ(GTIMR));
 858
 859                 seq_printf(m, "PM IER:\t\t%08x\n",
 860                            I915_READ(GEN6_PMIER));
 861                 seq_printf(m, "PM IIR:\t\t%08x\n",
 862                            I915_READ(GEN6_PMIIR));
 863                 seq_printf(m, "PM IMR:\t\t%08x\n",
 864                            I915_READ(GEN6_PMIMR));
 865
 866                 seq_printf(m, "Port hotplug:\t%08x\n",
 867                            I915_READ(PORT_HOTPLUG_EN));
 868                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 869                            I915_READ(VLV_DPFLIPSTAT));
 870                 seq_printf(m, "DPINVGTT:\t%08x\n",
 871                            I915_READ(DPINVGTT));
 872
 873         } else if (!HAS_PCH_SPLIT(dev_priv)) {
 874                 seq_printf(m, "Interrupt enable:    %08x\n",
 875                            I915_READ(IER));
 876                 seq_printf(m, "Interrupt identity:  %08x\n",
 877                            I915_READ(IIR));
 878                 seq_printf(m, "Interrupt mask:      %08x\n",
 879                            I915_READ(IMR));
 880                 for_each_pipe(dev_priv, pipe)
 881                         seq_printf(m, "Pipe %c stat:         %08x\n",
 882                                    pipe_name(pipe),
 883                                    I915_READ(PIPESTAT(pipe)));
 884         } else {
 885                 seq_printf(m, "North Display Interrupt enable:          %08x\n",
 886                            I915_READ(DEIER));
 887                 seq_printf(m, "North Display Interrupt identity:        %08x\n",
 888                            I915_READ(DEIIR));
 889                 seq_printf(m, "North Display Interrupt mask:            %08x\n",
 890                            I915_READ(DEIMR));
 891                 seq_printf(m, "South Display Interrupt enable:          %08x\n",
 892                            I915_READ(SDEIER));
 893                 seq_printf(m, "South Display Interrupt identity:        %08x\n",
 894                            I915_READ(SDEIIR));
 895                 seq_printf(m, "South Display Interrupt mask:            %08x\n",
 896                            I915_READ(SDEIMR));
 897                 seq_printf(m, "Graphics Interrupt enable:               %08x\n",
 898                            I915_READ(GTIER));
 899                 seq_printf(m, "Graphics Interrupt identity:             %08x\n",
 900                            I915_READ(GTIIR));
 901                 seq_printf(m, "Graphics Interrupt mask:         %08x\n",
 902                            I915_READ(GTIMR));
 903         }
 904         for_each_engine(engine, dev_priv, id) {
 905                 if (INTEL_GEN(dev_priv) >= 6) {
 906                         seq_printf(m,
 907                                    "Graphics Interrupt mask (%s):       %08x\n",
 908                                    engine->name, I915_READ_IMR(engine));
 909                 }
 910                 i915_ring_seqno_info(m, engine);
 911         }
 912         intel_runtime_pm_put(dev_priv);
 913
 914         return 0;
 915 }
 916
 917 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
 918 {
 919         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 920         struct drm_device *dev = &dev_priv->drm;
 921         int i, ret;
 922
 923         ret = mutex_lock_interruptible(&dev->struct_mutex);
 924         if (ret)
 925                 return ret;
 926
 927         seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
 928         for (i = 0; i < dev_priv->num_fence_regs; i++) {
 929                 struct i915_vma *vma = dev_priv->fence_regs[i].vma;
 930
 931                 seq_printf(m, "Fence %d, pin count = %d, object = ",
 932                            i, dev_priv->fence_regs[i].pin_count);
 933                 if (!vma)
 934                         seq_puts(m, "unused");
 935                 else
 936                         describe_obj(m, vma->obj);
 937                 seq_putc(m, '\n');
 938         }
 939
 940         mutex_unlock(&dev->struct_mutex);
 941         return 0;
 942 }
 943
 944 static int i915_hws_info(struct seq_file *m, void *data)
 945 {
 946         struct drm_info_node *node = m->private;
 947         struct drm_i915_private *dev_priv = node_to_i915(node);
 948         struct intel_engine_cs *engine;
 949         const u32 *hws;
 950         int i;
 951
 952         engine = dev_priv->engine[(uintptr_t)node->info_ent->data];
 953         hws = engine->status_page.page_addr;
 954         if (hws == NULL)
 955                 return 0;
 956
 957         for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
 958                 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
 959                            i * 4,
 960                            hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
 961         }
 962         return 0;
 963 }
 964
 965 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
 966
 967 static ssize_t
 968 i915_error_state_write(struct file *filp,
 969                        const char __user *ubuf,
 970                        size_t cnt,
 971                        loff_t *ppos)
 972 {
 973         struct i915_error_state_file_priv *error_priv = filp->private_data;
 974
 975         DRM_DEBUG_DRIVER("Resetting error state\n");
 976         i915_destroy_error_state(error_priv->dev);
 977
 978         return cnt;
 979 }
 980
 981 static int i915_error_state_open(struct inode *inode, struct file *file)
 982 {
 983         struct drm_i915_private *dev_priv = inode->i_private;
 984         struct i915_error_state_file_priv *error_priv;
 985
 986         error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
 987         if (!error_priv)
 988                 return -ENOMEM;
 989
 990         error_priv->dev = &dev_priv->drm;
 991
 992         i915_error_state_get(&dev_priv->drm, error_priv);
 993
 994         file->private_data = error_priv;
 995
 996         return 0;
 997 }
 998
 999 static int i915_error_state_release(struct inode *inode, struct file *file)
1000 {
1001         struct i915_error_state_file_priv *error_priv = file->private_data;
1002
1003         i915_error_state_put(error_priv);
1004         kfree(error_priv);
1005
1006         return 0;
1007 }
1008
1009 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1010                                      size_t count, loff_t *pos)
1011 {
1012         struct i915_error_state_file_priv *error_priv = file->private_data;
1013         struct drm_i915_error_state_buf error_str;
1014         loff_t tmp_pos = 0;
1015         ssize_t ret_count = 0;
1016         int ret;
1017
1018         ret = i915_error_state_buf_init(&error_str,
1019                                         to_i915(error_priv->dev), count, *pos);
1020         if (ret)
1021                 return ret;
1022
1023         ret = i915_error_state_to_str(&error_str, error_priv);
1024         if (ret)
1025                 goto out;
1026
1027         ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1028                                             error_str.buf,
1029                                             error_str.bytes);
1030
1031         if (ret_count < 0)
1032                 ret = ret_count;
1033         else
1034                 *pos = error_str.start + ret_count;
1035 out:
1036         i915_error_state_buf_release(&error_str);
1037         return ret ?: ret_count;
1038 }
1039
1040 static const struct file_operations i915_error_state_fops = {
1041         .owner = THIS_MODULE,
1042         .open = i915_error_state_open,
1043         .read = i915_error_state_read,
1044         .write = i915_error_state_write,
1045         .llseek = default_llseek,
1046         .release = i915_error_state_release,
1047 };
1048
1049 #endif
1050
1051 static int
1052 i915_next_seqno_get(void *data, u64 *val)
1053 {
1054         struct drm_i915_private *dev_priv = data;
1055
1056         *val = READ_ONCE(dev_priv->gt.global_timeline.next_seqno);
1057         return 0;
1058 }
1059
1060 static int
1061 i915_next_seqno_set(void *data, u64 val)
1062 {
1063         struct drm_i915_private *dev_priv = data;
1064         struct drm_device *dev = &dev_priv->drm;
1065         int ret;
1066
1067         ret = mutex_lock_interruptible(&dev->struct_mutex);
1068         if (ret)
1069                 return ret;
1070
1071         ret = i915_gem_set_global_seqno(dev, val);
1072         mutex_unlock(&dev->struct_mutex);
1073
1074         return ret;
1075 }
1076
1077 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1078                         i915_next_seqno_get, i915_next_seqno_set,
1079                         "0x%llx\n");
1080
1081 static int i915_frequency_info(struct seq_file *m, void *unused)
1082 {
1083         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1084         struct drm_device *dev = &dev_priv->drm;
1085         int ret = 0;
1086
1087         intel_runtime_pm_get(dev_priv);
1088
1089         if (IS_GEN5(dev_priv)) {
1090                 u16 rgvswctl = I915_READ16(MEMSWCTL);
1091                 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1092
1093                 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1094                 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1095                 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1096                            MEMSTAT_VID_SHIFT);
1097                 seq_printf(m, "Current P-state: %d\n",
1098                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1099         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1100                 u32 freq_sts;
1101
1102                 mutex_lock(&dev_priv->rps.hw_lock);
1103                 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1104                 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1105                 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1106
1107                 seq_printf(m, "actual GPU freq: %d MHz\n",
1108                            intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1109
1110                 seq_printf(m, "current GPU freq: %d MHz\n",
1111                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1112
1113                 seq_printf(m, "max GPU freq: %d MHz\n",
1114                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1115
1116                 seq_printf(m, "min GPU freq: %d MHz\n",
1117                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1118
1119                 seq_printf(m, "idle GPU freq: %d MHz\n",
1120                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1121
1122                 seq_printf(m,
1123                            "efficient (RPe) frequency: %d MHz\n",
1124                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1125                 mutex_unlock(&dev_priv->rps.hw_lock);
1126         } else if (INTEL_GEN(dev_priv) >= 6) {
1127                 u32 rp_state_limits;
1128                 u32 gt_perf_status;
1129                 u32 rp_state_cap;
1130                 u32 rpmodectl, rpinclimit, rpdeclimit;
1131                 u32 rpstat, cagf, reqf;
1132                 u32 rpupei, rpcurup, rpprevup;
1133                 u32 rpdownei, rpcurdown, rpprevdown;
1134                 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1135                 int max_freq;
1136
1137                 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1138                 if (IS_BROXTON(dev_priv)) {
1139                         rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1140                         gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1141                 } else {
1142                         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1143                         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1144                 }
1145
1146                 /* RPSTAT1 is in the GT power well */
1147                 ret = mutex_lock_interruptible(&dev->struct_mutex);
1148                 if (ret)
1149                         goto out;
1150
1151                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1152
1153                 reqf = I915_READ(GEN6_RPNSWREQ);
1154                 if (IS_GEN9(dev_priv))
1155                         reqf >>= 23;
1156                 else {
1157                         reqf &= ~GEN6_TURBO_DISABLE;
1158                         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1159                                 reqf >>= 24;
1160                         else
1161                                 reqf >>= 25;
1162                 }
1163                 reqf = intel_gpu_freq(dev_priv, reqf);
1164
1165                 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1166                 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1167                 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1168
1169                 rpstat = I915_READ(GEN6_RPSTAT1);
1170                 rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
1171                 rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
1172                 rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
1173                 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
1174                 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
1175                 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
1176                 if (IS_GEN9(dev_priv))
1177                         cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1178                 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1179                         cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1180                 else
1181                         cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1182                 cagf = intel_gpu_freq(dev_priv, cagf);
1183
1184                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1185                 mutex_unlock(&dev->struct_mutex);
1186
1187                 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
1188                         pm_ier = I915_READ(GEN6_PMIER);
1189                         pm_imr = I915_READ(GEN6_PMIMR);
1190                         pm_isr = I915_READ(GEN6_PMISR);
1191                         pm_iir = I915_READ(GEN6_PMIIR);
1192                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1193                 } else {
1194                         pm_ier = I915_READ(GEN8_GT_IER(2));
1195                         pm_imr = I915_READ(GEN8_GT_IMR(2));
1196                         pm_isr = I915_READ(GEN8_GT_ISR(2));
1197                         pm_iir = I915_READ(GEN8_GT_IIR(2));
1198                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1199                 }
1200                 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1201                            pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1202                 seq_printf(m, "pm_intr_keep: 0x%08x\n", dev_priv->rps.pm_intr_keep);
1203                 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1204                 seq_printf(m, "Render p-state ratio: %d\n",
1205                            (gt_perf_status & (IS_GEN9(dev_priv) ? 0x1ff00 : 0xff00)) >> 8);
1206                 seq_printf(m, "Render p-state VID: %d\n",
1207                            gt_perf_status & 0xff);
1208                 seq_printf(m, "Render p-state limit: %d\n",
1209                            rp_state_limits & 0xff);
1210                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1211                 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1212                 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1213                 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1214                 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1215                 seq_printf(m, "CAGF: %dMHz\n", cagf);
1216                 seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
1217                            rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei));
1218                 seq_printf(m, "RP CUR UP: %d (%dus)\n",
1219                            rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
1220                 seq_printf(m, "RP PREV UP: %d (%dus)\n",
1221                            rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
1222                 seq_printf(m, "Up threshold: %d%%\n",
1223                            dev_priv->rps.up_threshold);
1224
1225                 seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
1226                            rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
1227                 seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
1228                            rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown));
1229                 seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
1230                            rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown));
1231                 seq_printf(m, "Down threshold: %d%%\n",
1232                            dev_priv->rps.down_threshold);
1233
1234                 max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 0 :
1235                             rp_state_cap >> 16) & 0xff;
1236                 max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1237                              GEN9_FREQ_SCALER : 1);
1238                 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1239                            intel_gpu_freq(dev_priv, max_freq));
1240
1241                 max_freq = (rp_state_cap & 0xff00) >> 8;
1242                 max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1243                              GEN9_FREQ_SCALER : 1);
1244                 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1245                            intel_gpu_freq(dev_priv, max_freq));
1246
1247                 max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 16 :
1248                             rp_state_cap >> 0) & 0xff;
1249                 max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1250                              GEN9_FREQ_SCALER : 1);
1251                 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1252                            intel_gpu_freq(dev_priv, max_freq));
1253                 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1254                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1255
1256                 seq_printf(m, "Current freq: %d MHz\n",
1257                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1258                 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1259                 seq_printf(m, "Idle freq: %d MHz\n",
1260                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1261                 seq_printf(m, "Min freq: %d MHz\n",
1262                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1263                 seq_printf(m, "Boost freq: %d MHz\n",
1264                            intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
1265                 seq_printf(m, "Max freq: %d MHz\n",
1266                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1267                 seq_printf(m,
1268                            "efficient (RPe) frequency: %d MHz\n",
1269                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1270         } else {
1271                 seq_puts(m, "no P-state info available\n");
1272         }
1273
1274         seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
1275         seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1276         seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1277
1278 out:
1279         intel_runtime_pm_put(dev_priv);
1280         return ret;
1281 }
1282
1283 static void i915_instdone_info(struct drm_i915_private *dev_priv,
1284                                struct seq_file *m,
1285                                struct intel_instdone *instdone)
1286 {
1287         int slice;
1288         int subslice;
1289
1290         seq_printf(m, "\t\tINSTDONE: 0x%08x\n",
1291                    instdone->instdone);
1292
1293         if (INTEL_GEN(dev_priv) <= 3)
1294                 return;
1295
1296         seq_printf(m, "\t\tSC_INSTDONE: 0x%08x\n",
1297                    instdone->slice_common);
1298
1299         if (INTEL_GEN(dev_priv) <= 6)
1300                 return;
1301
1302         for_each_instdone_slice_subslice(dev_priv, slice, subslice)
1303                 seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
1304                            slice, subslice, instdone->sampler[slice][subslice]);
1305
1306         for_each_instdone_slice_subslice(dev_priv, slice, subslice)
1307                 seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n",
1308                            slice, subslice, instdone->row[slice][subslice]);
1309 }
1310
1311 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1312 {
1313         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1314         struct intel_engine_cs *engine;
1315         u64 acthd[I915_NUM_ENGINES];
1316         u32 seqno[I915_NUM_ENGINES];
1317         struct intel_instdone instdone;
1318         enum intel_engine_id id;
1319
1320         if (test_bit(I915_WEDGED, &dev_priv->gpu_error.flags))
1321                 seq_printf(m, "Wedged\n");
1322         if (test_bit(I915_RESET_IN_PROGRESS, &dev_priv->gpu_error.flags))
1323                 seq_printf(m, "Reset in progress\n");
1324         if (waitqueue_active(&dev_priv->gpu_error.wait_queue))
1325                 seq_printf(m, "Waiter holding struct mutex\n");
1326         if (waitqueue_active(&dev_priv->gpu_error.reset_queue))
1327                 seq_printf(m, "struct_mutex blocked for reset\n");
1328
1329         if (!i915.enable_hangcheck) {
1330                 seq_printf(m, "Hangcheck disabled\n");
1331                 return 0;
1332         }
1333
1334         intel_runtime_pm_get(dev_priv);
1335
1336         for_each_engine(engine, dev_priv, id) {
1337                 acthd[id] = intel_engine_get_active_head(engine);
1338                 seqno[id] = intel_engine_get_seqno(engine);
1339         }
1340
1341         intel_engine_get_instdone(dev_priv->engine[RCS], &instdone);
1342
1343         intel_runtime_pm_put(dev_priv);
1344
1345         if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1346                 seq_printf(m, "Hangcheck active, fires in %dms\n",
1347                            jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1348                                             jiffies));
1349         } else
1350                 seq_printf(m, "Hangcheck inactive\n");
1351
1352         for_each_engine(engine, dev_priv, id) {
1353                 struct intel_breadcrumbs *b = &engine->breadcrumbs;
1354                 struct rb_node *rb;
1355
1356                 seq_printf(m, "%s:\n", engine->name);
1357                 seq_printf(m, "\tseqno = %x [current %x, last %x]\n",
1358                            engine->hangcheck.seqno,
1359                            seqno[id],
1360                            engine->timeline->last_submitted_seqno);
1361                 seq_printf(m, "\twaiters? %s, fake irq active? %s\n",
1362                            yesno(intel_engine_has_waiter(engine)),
1363                            yesno(test_bit(engine->id,
1364                                           &dev_priv->gpu_error.missed_irq_rings)));
1365                 spin_lock(&b->lock);
1366                 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
1367                         struct intel_wait *w = container_of(rb, typeof(*w), node);
1368
1369                         seq_printf(m, "\t%s [%d] waiting for %x\n",
1370                                    w->tsk->comm, w->tsk->pid, w->seqno);
1371                 }
1372                 spin_unlock(&b->lock);
1373
1374                 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1375                            (long long)engine->hangcheck.acthd,
1376                            (long long)acthd[id]);
1377                 seq_printf(m, "\tscore = %d\n", engine->hangcheck.score);
1378                 seq_printf(m, "\taction = %d\n", engine->hangcheck.action);
1379
1380                 if (engine->id == RCS) {
1381                         seq_puts(m, "\tinstdone read =\n");
1382
1383                         i915_instdone_info(dev_priv, m, &instdone);
1384
1385                         seq_puts(m, "\tinstdone accu =\n");
1386
1387                         i915_instdone_info(dev_priv, m,
1388                                            &engine->hangcheck.instdone);
1389                 }
1390         }
1391
1392         return 0;
1393 }
1394
1395 static int ironlake_drpc_info(struct seq_file *m)
1396 {
1397         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1398         u32 rgvmodectl, rstdbyctl;
1399         u16 crstandvid;
1400
1401         intel_runtime_pm_get(dev_priv);
1402
1403         rgvmodectl = I915_READ(MEMMODECTL);
1404         rstdbyctl = I915_READ(RSTDBYCTL);
1405         crstandvid = I915_READ16(CRSTANDVID);
1406
1407         intel_runtime_pm_put(dev_priv);
1408
1409         seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1410         seq_printf(m, "Boost freq: %d\n",
1411                    (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1412                    MEMMODE_BOOST_FREQ_SHIFT);
1413         seq_printf(m, "HW control enabled: %s\n",
1414                    yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1415         seq_printf(m, "SW control enabled: %s\n",
1416                    yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1417         seq_printf(m, "Gated voltage change: %s\n",
1418                    yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1419         seq_printf(m, "Starting frequency: P%d\n",
1420                    (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1421         seq_printf(m, "Max P-state: P%d\n",
1422                    (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1423         seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1424         seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1425         seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1426         seq_printf(m, "Render standby enabled: %s\n",
1427                    yesno(!(rstdbyctl & RCX_SW_EXIT)));
1428         seq_puts(m, "Current RS state: ");
1429         switch (rstdbyctl & RSX_STATUS_MASK) {
1430         case RSX_STATUS_ON:
1431                 seq_puts(m, "on\n");
1432                 break;
1433         case RSX_STATUS_RC1:
1434                 seq_puts(m, "RC1\n");
1435                 break;
1436         case RSX_STATUS_RC1E:
1437                 seq_puts(m, "RC1E\n");
1438                 break;
1439         case RSX_STATUS_RS1:
1440                 seq_puts(m, "RS1\n");
1441                 break;
1442         case RSX_STATUS_RS2:
1443                 seq_puts(m, "RS2 (RC6)\n");
1444                 break;
1445         case RSX_STATUS_RS3:
1446                 seq_puts(m, "RC3 (RC6+)\n");
1447                 break;
1448         default:
1449                 seq_puts(m, "unknown\n");
1450                 break;
1451         }
1452
1453         return 0;
1454 }
1455
1456 static int i915_forcewake_domains(struct seq_file *m, void *data)
1457 {
1458         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1459         struct intel_uncore_forcewake_domain *fw_domain;
1460
1461         spin_lock_irq(&dev_priv->uncore.lock);
1462         for_each_fw_domain(fw_domain, dev_priv) {
1463                 seq_printf(m, "%s.wake_count = %u\n",
1464                            intel_uncore_forcewake_domain_to_str(fw_domain->id),
1465                            fw_domain->wake_count);
1466         }
1467         spin_unlock_irq(&dev_priv->uncore.lock);
1468
1469         return 0;
1470 }
1471
1472 static int vlv_drpc_info(struct seq_file *m)
1473 {
1474         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1475         u32 rpmodectl1, rcctl1, pw_status;
1476
1477         intel_runtime_pm_get(dev_priv);
1478
1479         pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1480         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1481         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1482
1483         intel_runtime_pm_put(dev_priv);
1484
1485         seq_printf(m, "Video Turbo Mode: %s\n",
1486                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1487         seq_printf(m, "Turbo enabled: %s\n",
1488                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1489         seq_printf(m, "HW control enabled: %s\n",
1490                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1491         seq_printf(m, "SW control enabled: %s\n",
1492                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1493                           GEN6_RP_MEDIA_SW_MODE));
1494         seq_printf(m, "RC6 Enabled: %s\n",
1495                    yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1496                                         GEN6_RC_CTL_EI_MODE(1))));
1497         seq_printf(m, "Render Power Well: %s\n",
1498                    (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1499         seq_printf(m, "Media Power Well: %s\n",
1500                    (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1501
1502         seq_printf(m, "Render RC6 residency since boot: %u\n",
1503                    I915_READ(VLV_GT_RENDER_RC6));
1504         seq_printf(m, "Media RC6 residency since boot: %u\n",
1505                    I915_READ(VLV_GT_MEDIA_RC6));
1506
1507         return i915_forcewake_domains(m, NULL);
1508 }
1509
1510 static int gen6_drpc_info(struct seq_file *m)
1511 {
1512         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1513         struct drm_device *dev = &dev_priv->drm;
1514         u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1515         u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
1516         unsigned forcewake_count;
1517         int count = 0, ret;
1518
1519         ret = mutex_lock_interruptible(&dev->struct_mutex);
1520         if (ret)
1521                 return ret;
1522         intel_runtime_pm_get(dev_priv);
1523
1524         spin_lock_irq(&dev_priv->uncore.lock);
1525         forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1526         spin_unlock_irq(&dev_priv->uncore.lock);
1527
1528         if (forcewake_count) {
1529                 seq_puts(m, "RC information inaccurate because somebody "
1530                             "holds a forcewake reference \n");
1531         } else {
1532                 /* NB: we cannot use forcewake, else we read the wrong values */
1533                 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1534                         udelay(10);
1535                 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1536         }
1537
1538         gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1539         trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1540
1541         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1542         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1543         if (INTEL_GEN(dev_priv) >= 9) {
1544                 gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE);
1545                 gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
1546         }
1547         mutex_unlock(&dev->struct_mutex);
1548         mutex_lock(&dev_priv->rps.hw_lock);
1549         sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1550         mutex_unlock(&dev_priv->rps.hw_lock);
1551
1552         intel_runtime_pm_put(dev_priv);
1553
1554         seq_printf(m, "Video Turbo Mode: %s\n",
1555                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1556         seq_printf(m, "HW control enabled: %s\n",
1557                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1558         seq_printf(m, "SW control enabled: %s\n",
1559                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1560                           GEN6_RP_MEDIA_SW_MODE));
1561         seq_printf(m, "RC1e Enabled: %s\n",
1562                    yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1563         seq_printf(m, "RC6 Enabled: %s\n",
1564                    yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1565         if (INTEL_GEN(dev_priv) >= 9) {
1566                 seq_printf(m, "Render Well Gating Enabled: %s\n",
1567                         yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
1568                 seq_printf(m, "Media Well Gating Enabled: %s\n",
1569                         yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE));
1570         }
1571         seq_printf(m, "Deep RC6 Enabled: %s\n",
1572                    yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1573         seq_printf(m, "Deepest RC6 Enabled: %s\n",
1574                    yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1575         seq_puts(m, "Current RC state: ");
1576         switch (gt_core_status & GEN6_RCn_MASK) {
1577         case GEN6_RC0:
1578                 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1579                         seq_puts(m, "Core Power Down\n");
1580                 else
1581                         seq_puts(m, "on\n");
1582                 break;
1583         case GEN6_RC3:
1584                 seq_puts(m, "RC3\n");
1585                 break;
1586         case GEN6_RC6:
1587                 seq_puts(m, "RC6\n");
1588                 break;
1589         case GEN6_RC7:
1590                 seq_puts(m, "RC7\n");
1591                 break;
1592         default:
1593                 seq_puts(m, "Unknown\n");
1594                 break;
1595         }
1596
1597         seq_printf(m, "Core Power Down: %s\n",
1598                    yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1599         if (INTEL_GEN(dev_priv) >= 9) {
1600                 seq_printf(m, "Render Power Well: %s\n",
1601                         (gen9_powergate_status &
1602                          GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
1603                 seq_printf(m, "Media Power Well: %s\n",
1604                         (gen9_powergate_status &
1605                          GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
1606         }
1607
1608         /* Not exactly sure what this is */
1609         seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1610                    I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1611         seq_printf(m, "RC6 residency since boot: %u\n",
1612                    I915_READ(GEN6_GT_GFX_RC6));
1613         seq_printf(m, "RC6+ residency since boot: %u\n",
1614                    I915_READ(GEN6_GT_GFX_RC6p));
1615         seq_printf(m, "RC6++ residency since boot: %u\n",
1616                    I915_READ(GEN6_GT_GFX_RC6pp));
1617
1618         seq_printf(m, "RC6   voltage: %dmV\n",
1619                    GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1620         seq_printf(m, "RC6+  voltage: %dmV\n",
1621                    GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1622         seq_printf(m, "RC6++ voltage: %dmV\n",
1623                    GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1624         return i915_forcewake_domains(m, NULL);
1625 }
1626
1627 static int i915_drpc_info(struct seq_file *m, void *unused)
1628 {
1629         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1630
1631         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1632                 return vlv_drpc_info(m);
1633         else if (INTEL_GEN(dev_priv) >= 6)
1634                 return gen6_drpc_info(m);
1635         else
1636                 return ironlake_drpc_info(m);
1637 }
1638
1639 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1640 {
1641         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1642
1643         seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1644                    dev_priv->fb_tracking.busy_bits);
1645
1646         seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1647                    dev_priv->fb_tracking.flip_bits);
1648
1649         return 0;
1650 }
1651
1652 static int i915_fbc_status(struct seq_file *m, void *unused)
1653 {
1654         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1655
1656         if (!HAS_FBC(dev_priv)) {
1657                 seq_puts(m, "FBC unsupported on this chipset\n");
1658                 return 0;
1659         }
1660
1661         intel_runtime_pm_get(dev_priv);
1662         mutex_lock(&dev_priv->fbc.lock);
1663
1664         if (intel_fbc_is_active(dev_priv))
1665                 seq_puts(m, "FBC enabled\n");
1666         else
1667                 seq_printf(m, "FBC disabled: %s\n",
1668                            dev_priv->fbc.no_fbc_reason);
1669
1670         if (intel_fbc_is_active(dev_priv) && INTEL_GEN(dev_priv) >= 7) {
1671                 uint32_t mask = INTEL_GEN(dev_priv) >= 8 ?
1672                                 BDW_FBC_COMPRESSION_MASK :
1673                                 IVB_FBC_COMPRESSION_MASK;
1674                 seq_printf(m, "Compressing: %s\n",
1675                            yesno(I915_READ(FBC_STATUS2) & mask));
1676         }
1677
1678         mutex_unlock(&dev_priv->fbc.lock);
1679         intel_runtime_pm_put(dev_priv);
1680
1681         return 0;
1682 }
1683
1684 static int i915_fbc_fc_get(void *data, u64 *val)
1685 {
1686         struct drm_i915_private *dev_priv = data;
1687
1688         if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1689                 return -ENODEV;
1690
1691         *val = dev_priv->fbc.false_color;
1692
1693         return 0;
1694 }
1695
1696 static int i915_fbc_fc_set(void *data, u64 val)
1697 {
1698         struct drm_i915_private *dev_priv = data;
1699         u32 reg;
1700
1701         if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1702                 return -ENODEV;
1703
1704         mutex_lock(&dev_priv->fbc.lock);
1705
1706         reg = I915_READ(ILK_DPFC_CONTROL);
1707         dev_priv->fbc.false_color = val;
1708
1709         I915_WRITE(ILK_DPFC_CONTROL, val ?
1710                    (reg | FBC_CTL_FALSE_COLOR) :
1711                    (reg & ~FBC_CTL_FALSE_COLOR));
1712
1713         mutex_unlock(&dev_priv->fbc.lock);
1714         return 0;
1715 }
1716
1717 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1718                         i915_fbc_fc_get, i915_fbc_fc_set,
1719                         "%llu\n");
1720
1721 static int i915_ips_status(struct seq_file *m, void *unused)
1722 {
1723         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1724
1725         if (!HAS_IPS(dev_priv)) {
1726                 seq_puts(m, "not supported\n");
1727                 return 0;
1728         }
1729
1730         intel_runtime_pm_get(dev_priv);
1731
1732         seq_printf(m, "Enabled by kernel parameter: %s\n",
1733                    yesno(i915.enable_ips));
1734
1735         if (INTEL_GEN(dev_priv) >= 8) {
1736                 seq_puts(m, "Currently: unknown\n");
1737         } else {
1738                 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1739                         seq_puts(m, "Currently: enabled\n");
1740                 else
1741                         seq_puts(m, "Currently: disabled\n");
1742         }
1743
1744         intel_runtime_pm_put(dev_priv);
1745
1746         return 0;
1747 }
1748
1749 static int i915_sr_status(struct seq_file *m, void *unused)
1750 {
1751         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1752         bool sr_enabled = false;
1753
1754         intel_runtime_pm_get(dev_priv);
1755         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1756
1757         if (HAS_PCH_SPLIT(dev_priv))
1758                 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1759         else if (IS_CRESTLINE(dev_priv) || IS_G4X(dev_priv) ||
1760                  IS_I945G(dev_priv) || IS_I945GM(dev_priv))
1761                 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1762         else if (IS_I915GM(dev_priv))
1763                 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1764         else if (IS_PINEVIEW(dev_priv))
1765                 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1766         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1767                 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1768
1769         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1770         intel_runtime_pm_put(dev_priv);
1771
1772         seq_printf(m, "self-refresh: %s\n",
1773                    sr_enabled ? "enabled" : "disabled");
1774
1775         return 0;
1776 }
1777
1778 static int i915_emon_status(struct seq_file *m, void *unused)
1779 {
1780         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1781         struct drm_device *dev = &dev_priv->drm;
1782         unsigned long temp, chipset, gfx;
1783         int ret;
1784
1785         if (!IS_GEN5(dev_priv))
1786                 return -ENODEV;
1787
1788         ret = mutex_lock_interruptible(&dev->struct_mutex);
1789         if (ret)
1790                 return ret;
1791
1792         temp = i915_mch_val(dev_priv);
1793         chipset = i915_chipset_val(dev_priv);
1794         gfx = i915_gfx_val(dev_priv);
1795         mutex_unlock(&dev->struct_mutex);
1796
1797         seq_printf(m, "GMCH temp: %ld\n", temp);
1798         seq_printf(m, "Chipset power: %ld\n", chipset);
1799         seq_printf(m, "GFX power: %ld\n", gfx);
1800         seq_printf(m, "Total power: %ld\n", chipset + gfx);
1801
1802         return 0;
1803 }
1804
1805 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1806 {
1807         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1808         int ret = 0;
1809         int gpu_freq, ia_freq;
1810         unsigned int max_gpu_freq, min_gpu_freq;
1811
1812         if (!HAS_LLC(dev_priv)) {
1813                 seq_puts(m, "unsupported on this chipset\n");
1814                 return 0;
1815         }
1816
1817         intel_runtime_pm_get(dev_priv);
1818
1819         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1820         if (ret)
1821                 goto out;
1822
1823         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
1824                 /* Convert GT frequency to 50 HZ units */
1825                 min_gpu_freq =
1826                         dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1827                 max_gpu_freq =
1828                         dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1829         } else {
1830                 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1831                 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1832         }
1833
1834         seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1835
1836         for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1837                 ia_freq = gpu_freq;
1838                 sandybridge_pcode_read(dev_priv,
1839                                        GEN6_PCODE_READ_MIN_FREQ_TABLE,
1840                                        &ia_freq);
1841                 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1842                            intel_gpu_freq(dev_priv, (gpu_freq *
1843                                 (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1844                                  GEN9_FREQ_SCALER : 1))),
1845                            ((ia_freq >> 0) & 0xff) * 100,
1846                            ((ia_freq >> 8) & 0xff) * 100);
1847         }
1848
1849         mutex_unlock(&dev_priv->rps.hw_lock);
1850
1851 out:
1852         intel_runtime_pm_put(dev_priv);
1853         return ret;
1854 }
1855
1856 static int i915_opregion(struct seq_file *m, void *unused)
1857 {
1858         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1859         struct drm_device *dev = &dev_priv->drm;
1860         struct intel_opregion *opregion = &dev_priv->opregion;
1861         int ret;
1862
1863         ret = mutex_lock_interruptible(&dev->struct_mutex);
1864         if (ret)
1865                 goto out;
1866
1867         if (opregion->header)
1868                 seq_write(m, opregion->header, OPREGION_SIZE);
1869
1870         mutex_unlock(&dev->struct_mutex);
1871
1872 out:
1873         return 0;
1874 }
1875
1876 static int i915_vbt(struct seq_file *m, void *unused)
1877 {
1878         struct intel_opregion *opregion = &node_to_i915(m->private)->opregion;
1879
1880         if (opregion->vbt)
1881                 seq_write(m, opregion->vbt, opregion->vbt_size);
1882
1883         return 0;
1884 }
1885
1886 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1887 {
1888         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1889         struct drm_device *dev = &dev_priv->drm;
1890         struct intel_framebuffer *fbdev_fb = NULL;
1891         struct drm_framebuffer *drm_fb;
1892         int ret;
1893
1894         ret = mutex_lock_interruptible(&dev->struct_mutex);
1895         if (ret)
1896                 return ret;
1897
1898 #ifdef CONFIG_DRM_FBDEV_EMULATION
1899         if (dev_priv->fbdev) {
1900                 fbdev_fb = to_intel_framebuffer(dev_priv->fbdev->helper.fb);
1901
1902                 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1903                            fbdev_fb->base.width,
1904                            fbdev_fb->base.height,
1905                            fbdev_fb->base.depth,
1906                            fbdev_fb->base.bits_per_pixel,
1907                            fbdev_fb->base.modifier[0],
1908                            drm_framebuffer_read_refcount(&fbdev_fb->base));
1909                 describe_obj(m, fbdev_fb->obj);
1910                 seq_putc(m, '\n');
1911         }
1912 #endif
1913
1914         mutex_lock(&dev->mode_config.fb_lock);
1915         drm_for_each_fb(drm_fb, dev) {
1916                 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
1917                 if (fb == fbdev_fb)
1918                         continue;
1919
1920                 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1921                            fb->base.width,
1922                            fb->base.height,
1923                            fb->base.depth,
1924                            fb->base.bits_per_pixel,
1925                            fb->base.modifier[0],
1926                            drm_framebuffer_read_refcount(&fb->base));
1927                 describe_obj(m, fb->obj);
1928                 seq_putc(m, '\n');
1929         }
1930         mutex_unlock(&dev->mode_config.fb_lock);
1931         mutex_unlock(&dev->struct_mutex);
1932
1933         return 0;
1934 }
1935
1936 static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring)
1937 {
1938         seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1939                    ring->space, ring->head, ring->tail,
1940                    ring->last_retired_head);
1941 }
1942
1943 static int i915_context_status(struct seq_file *m, void *unused)
1944 {
1945         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1946         struct drm_device *dev = &dev_priv->drm;
1947         struct intel_engine_cs *engine;
1948         struct i915_gem_context *ctx;
1949         enum intel_engine_id id;
1950         int ret;
1951
1952         ret = mutex_lock_interruptible(&dev->struct_mutex);
1953         if (ret)
1954                 return ret;
1955
1956         list_for_each_entry(ctx, &dev_priv->context_list, link) {
1957                 seq_printf(m, "HW context %u ", ctx->hw_id);
1958                 if (ctx->pid) {
1959                         struct task_struct *task;
1960
1961                         task = get_pid_task(ctx->pid, PIDTYPE_PID);
1962                         if (task) {
1963                                 seq_printf(m, "(%s [%d]) ",
1964                                            task->comm, task->pid);
1965                                 put_task_struct(task);
1966                         }
1967                 } else if (IS_ERR(ctx->file_priv)) {
1968                         seq_puts(m, "(deleted) ");
1969                 } else {
1970                         seq_puts(m, "(kernel) ");
1971                 }
1972
1973                 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
1974                 seq_putc(m, '\n');
1975
1976                 for_each_engine(engine, dev_priv, id) {
1977                         struct intel_context *ce = &ctx->engine[engine->id];
1978
1979                         seq_printf(m, "%s: ", engine->name);
1980                         seq_putc(m, ce->initialised ? 'I' : 'i');
1981                         if (ce->state)
1982                                 describe_obj(m, ce->state->obj);
1983                         if (ce->ring)
1984                                 describe_ctx_ring(m, ce->ring);
1985                         seq_putc(m, '\n');
1986                 }
1987
1988                 seq_putc(m, '\n');
1989         }
1990
1991         mutex_unlock(&dev->struct_mutex);
1992
1993         return 0;
1994 }
1995
1996 static void i915_dump_lrc_obj(struct seq_file *m,
1997                               struct i915_gem_context *ctx,
1998                               struct intel_engine_cs *engine)
1999 {
2000         struct i915_vma *vma = ctx->engine[engine->id].state;
2001         struct page *page;
2002         int j;
2003
2004         seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id);
2005
2006         if (!vma) {
2007                 seq_puts(m, "\tFake context\n");
2008                 return;
2009         }
2010
2011         if (vma->flags & I915_VMA_GLOBAL_BIND)
2012                 seq_printf(m, "\tBound in GGTT at 0x%08x\n",
2013                            i915_ggtt_offset(vma));
2014
2015         if (i915_gem_object_pin_pages(vma->obj)) {
2016                 seq_puts(m, "\tFailed to get pages for context object\n\n");
2017                 return;
2018         }
2019
2020         page = i915_gem_object_get_page(vma->obj, LRC_STATE_PN);
2021         if (page) {
2022                 u32 *reg_state = kmap_atomic(page);
2023
2024                 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2025                         seq_printf(m,
2026                                    "\t[0x%04x] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2027                                    j * 4,
2028                                    reg_state[j], reg_state[j + 1],
2029                                    reg_state[j + 2], reg_state[j + 3]);
2030                 }
2031                 kunmap_atomic(reg_state);
2032         }
2033
2034         i915_gem_object_unpin_pages(vma->obj);
2035         seq_putc(m, '\n');
2036 }
2037
2038 static int i915_dump_lrc(struct seq_file *m, void *unused)
2039 {
2040         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2041         struct drm_device *dev = &dev_priv->drm;
2042         struct intel_engine_cs *engine;
2043         struct i915_gem_context *ctx;
2044         enum intel_engine_id id;
2045         int ret;
2046
2047         if (!i915.enable_execlists) {
2048                 seq_printf(m, "Logical Ring Contexts are disabled\n");
2049                 return 0;
2050         }
2051
2052         ret = mutex_lock_interruptible(&dev->struct_mutex);
2053         if (ret)
2054                 return ret;
2055
2056         list_for_each_entry(ctx, &dev_priv->context_list, link)
2057                 for_each_engine(engine, dev_priv, id)
2058                         i915_dump_lrc_obj(m, ctx, engine);
2059
2060         mutex_unlock(&dev->struct_mutex);
2061
2062         return 0;
2063 }
2064
2065 static const char *swizzle_string(unsigned swizzle)
2066 {
2067         switch (swizzle) {
2068         case I915_BIT_6_SWIZZLE_NONE:
2069                 return "none";
2070         case I915_BIT_6_SWIZZLE_9:
2071                 return "bit9";
2072         case I915_BIT_6_SWIZZLE_9_10:
2073                 return "bit9/bit10";
2074         case I915_BIT_6_SWIZZLE_9_11:
2075                 return "bit9/bit11";
2076         case I915_BIT_6_SWIZZLE_9_10_11:
2077                 return "bit9/bit10/bit11";
2078         case I915_BIT_6_SWIZZLE_9_17:
2079                 return "bit9/bit17";
2080         case I915_BIT_6_SWIZZLE_9_10_17:
2081                 return "bit9/bit10/bit17";
2082         case I915_BIT_6_SWIZZLE_UNKNOWN:
2083                 return "unknown";
2084         }
2085
2086         return "bug";
2087 }
2088
2089 static int i915_swizzle_info(struct seq_file *m, void *data)
2090 {
2091         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2092
2093         intel_runtime_pm_get(dev_priv);
2094
2095         seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2096                    swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2097         seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2098                    swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2099
2100         if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) {
2101                 seq_printf(m, "DDC = 0x%08x\n",
2102                            I915_READ(DCC));
2103                 seq_printf(m, "DDC2 = 0x%08x\n",
2104                            I915_READ(DCC2));
2105                 seq_printf(m, "C0DRB3 = 0x%04x\n",
2106                            I915_READ16(C0DRB3));
2107                 seq_printf(m, "C1DRB3 = 0x%04x\n",
2108                            I915_READ16(C1DRB3));
2109         } else if (INTEL_GEN(dev_priv) >= 6) {
2110                 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2111                            I915_READ(MAD_DIMM_C0));
2112                 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2113                            I915_READ(MAD_DIMM_C1));
2114                 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2115                            I915_READ(MAD_DIMM_C2));
2116                 seq_printf(m, "TILECTL = 0x%08x\n",
2117                            I915_READ(TILECTL));
2118                 if (INTEL_GEN(dev_priv) >= 8)
2119                         seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2120                                    I915_READ(GAMTARBMODE));
2121                 else
2122                         seq_printf(m, "ARB_MODE = 0x%08x\n",
2123                                    I915_READ(ARB_MODE));
2124                 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2125                            I915_READ(DISP_ARB_CTL));
2126         }
2127
2128         if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2129                 seq_puts(m, "L-shaped memory detected\n");
2130
2131         intel_runtime_pm_put(dev_priv);
2132
2133         return 0;
2134 }
2135
2136 static int per_file_ctx(int id, void *ptr, void *data)
2137 {
2138         struct i915_gem_context *ctx = ptr;
2139         struct seq_file *m = data;
2140         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2141
2142         if (!ppgtt) {
2143                 seq_printf(m, "  no ppgtt for context %d\n",
2144                            ctx->user_handle);
2145                 return 0;
2146         }
2147
2148         if (i915_gem_context_is_default(ctx))
2149                 seq_puts(m, "  default context:\n");
2150         else
2151                 seq_printf(m, "  context %d:\n", ctx->user_handle);
2152         ppgtt->debug_dump(ppgtt, m);
2153
2154         return 0;
2155 }
2156
2157 static void gen8_ppgtt_info(struct seq_file *m,
2158                             struct drm_i915_private *dev_priv)
2159 {
2160         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2161         struct intel_engine_cs *engine;
2162         enum intel_engine_id id;
2163         int i;
2164
2165         if (!ppgtt)
2166                 return;
2167
2168         for_each_engine(engine, dev_priv, id) {
2169                 seq_printf(m, "%s\n", engine->name);
2170                 for (i = 0; i < 4; i++) {
2171                         u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
2172                         pdp <<= 32;
2173                         pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
2174                         seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2175                 }
2176         }
2177 }
2178
2179 static void gen6_ppgtt_info(struct seq_file *m,
2180                             struct drm_i915_private *dev_priv)
2181 {
2182         struct intel_engine_cs *engine;
2183         enum intel_engine_id id;
2184
2185         if (IS_GEN6(dev_priv))
2186                 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2187
2188         for_each_engine(engine, dev_priv, id) {
2189                 seq_printf(m, "%s\n", engine->name);
2190                 if (IS_GEN7(dev_priv))
2191                         seq_printf(m, "GFX_MODE: 0x%08x\n",
2192                                    I915_READ(RING_MODE_GEN7(engine)));
2193                 seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
2194                            I915_READ(RING_PP_DIR_BASE(engine)));
2195                 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
2196                            I915_READ(RING_PP_DIR_BASE_READ(engine)));
2197                 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
2198                            I915_READ(RING_PP_DIR_DCLV(engine)));
2199         }
2200         if (dev_priv->mm.aliasing_ppgtt) {
2201                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2202
2203                 seq_puts(m, "aliasing PPGTT:\n");
2204                 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2205
2206                 ppgtt->debug_dump(ppgtt, m);
2207         }
2208
2209         seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2210 }
2211
2212 static int i915_ppgtt_info(struct seq_file *m, void *data)
2213 {
2214         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2215         struct drm_device *dev = &dev_priv->drm;
2216         struct drm_file *file;
2217         int ret;
2218
2219         mutex_lock(&dev->filelist_mutex);
2220         ret = mutex_lock_interruptible(&dev->struct_mutex);
2221         if (ret)
2222                 goto out_unlock;
2223
2224         intel_runtime_pm_get(dev_priv);
2225
2226         if (INTEL_GEN(dev_priv) >= 8)
2227                 gen8_ppgtt_info(m, dev_priv);
2228         else if (INTEL_GEN(dev_priv) >= 6)
2229                 gen6_ppgtt_info(m, dev_priv);
2230
2231         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2232                 struct drm_i915_file_private *file_priv = file->driver_priv;
2233                 struct task_struct *task;
2234
2235                 task = get_pid_task(file->pid, PIDTYPE_PID);
2236                 if (!task) {
2237                         ret = -ESRCH;
2238                         goto out_rpm;
2239                 }
2240                 seq_printf(m, "\nproc: %s\n", task->comm);
2241                 put_task_struct(task);
2242                 idr_for_each(&file_priv->context_idr, per_file_ctx,
2243                              (void *)(unsigned long)m);
2244         }
2245
2246 out_rpm:
2247         intel_runtime_pm_put(dev_priv);
2248         mutex_unlock(&dev->struct_mutex);
2249 out_unlock:
2250         mutex_unlock(&dev->filelist_mutex);
2251         return ret;
2252 }
2253
2254 static int count_irq_waiters(struct drm_i915_private *i915)
2255 {
2256         struct intel_engine_cs *engine;
2257         enum intel_engine_id id;
2258         int count = 0;
2259
2260         for_each_engine(engine, i915, id)
2261                 count += intel_engine_has_waiter(engine);
2262
2263         return count;
2264 }
2265
2266 static const char *rps_power_to_str(unsigned int power)
2267 {
2268         static const char * const strings[] = {
2269                 [LOW_POWER] = "low power",
2270                 [BETWEEN] = "mixed",
2271                 [HIGH_POWER] = "high power",
2272         };
2273
2274         if (power >= ARRAY_SIZE(strings) || !strings[power])
2275                 return "unknown";
2276
2277         return strings[power];
2278 }
2279
2280 static int i915_rps_boost_info(struct seq_file *m, void *data)
2281 {
2282         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2283         struct drm_device *dev = &dev_priv->drm;
2284         struct drm_file *file;
2285
2286         seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2287         seq_printf(m, "GPU busy? %s [%x]\n",
2288                    yesno(dev_priv->gt.awake), dev_priv->gt.active_engines);
2289         seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2290         seq_printf(m, "Frequency requested %d\n",
2291                    intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
2292         seq_printf(m, "  min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2293                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2294                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2295                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2296                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2297         seq_printf(m, "  idle:%d, efficient:%d, boost:%d\n",
2298                    intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
2299                    intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2300                    intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
2301
2302         mutex_lock(&dev->filelist_mutex);
2303         spin_lock(&dev_priv->rps.client_lock);
2304         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2305                 struct drm_i915_file_private *file_priv = file->driver_priv;
2306                 struct task_struct *task;
2307
2308                 rcu_read_lock();
2309                 task = pid_task(file->pid, PIDTYPE_PID);
2310                 seq_printf(m, "%s [%d]: %d boosts%s\n",
2311                            task ? task->comm : "<unknown>",
2312                            task ? task->pid : -1,
2313                            file_priv->rps.boosts,
2314                            list_empty(&file_priv->rps.link) ? "" : ", active");
2315                 rcu_read_unlock();
2316         }
2317         seq_printf(m, "Kernel (anonymous) boosts: %d\n", dev_priv->rps.boosts);
2318         spin_unlock(&dev_priv->rps.client_lock);
2319         mutex_unlock(&dev->filelist_mutex);
2320
2321         if (INTEL_GEN(dev_priv) >= 6 &&
2322             dev_priv->rps.enabled &&
2323             dev_priv->gt.active_engines) {
2324                 u32 rpup, rpupei;
2325                 u32 rpdown, rpdownei;
2326
2327                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2328                 rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK;
2329                 rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK;
2330                 rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK;
2331                 rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK;
2332                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2333
2334                 seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n",
2335                            rps_power_to_str(dev_priv->rps.power));
2336                 seq_printf(m, "  Avg. up: %d%% [above threshold? %d%%]\n",
2337                            100 * rpup / rpupei,
2338                            dev_priv->rps.up_threshold);
2339                 seq_printf(m, "  Avg. down: %d%% [below threshold? %d%%]\n",
2340                            100 * rpdown / rpdownei,
2341                            dev_priv->rps.down_threshold);
2342         } else {
2343                 seq_puts(m, "\nRPS Autotuning inactive\n");
2344         }
2345
2346         return 0;
2347 }
2348
2349 static int i915_llc(struct seq_file *m, void *data)
2350 {
2351         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2352         const bool edram = INTEL_GEN(dev_priv) > 8;
2353
2354         seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv)));
2355         seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
2356                    intel_uncore_edram_size(dev_priv)/1024/1024);
2357
2358         return 0;
2359 }
2360
2361 static int i915_guc_load_status_info(struct seq_file *m, void *data)
2362 {
2363         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2364         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
2365         u32 tmp, i;
2366
2367         if (!HAS_GUC_UCODE(dev_priv))
2368                 return 0;
2369
2370         seq_printf(m, "GuC firmware status:\n");
2371         seq_printf(m, "\tpath: %s\n",
2372                 guc_fw->guc_fw_path);
2373         seq_printf(m, "\tfetch: %s\n",
2374                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
2375         seq_printf(m, "\tload: %s\n",
2376                 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
2377         seq_printf(m, "\tversion wanted: %d.%d\n",
2378                 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2379         seq_printf(m, "\tversion found: %d.%d\n",
2380                 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
2381         seq_printf(m, "\theader: offset is %d; size = %d\n",
2382                 guc_fw->header_offset, guc_fw->header_size);
2383         seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2384                 guc_fw->ucode_offset, guc_fw->ucode_size);
2385         seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2386                 guc_fw->rsa_offset, guc_fw->rsa_size);
2387
2388         tmp = I915_READ(GUC_STATUS);
2389
2390         seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2391         seq_printf(m, "\tBootrom status = 0x%x\n",
2392                 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2393         seq_printf(m, "\tuKernel status = 0x%x\n",
2394                 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2395         seq_printf(m, "\tMIA Core status = 0x%x\n",
2396                 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2397         seq_puts(m, "\nScratch registers:\n");
2398         for (i = 0; i < 16; i++)
2399                 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2400
2401         return 0;
2402 }
2403
2404 static void i915_guc_log_info(struct seq_file *m,
2405                               struct drm_i915_private *dev_priv)
2406 {
2407         struct intel_guc *guc = &dev_priv->guc;
2408
2409         seq_puts(m, "\nGuC logging stats:\n");
2410
2411         seq_printf(m, "\tISR:   flush count %10u, overflow count %10u\n",
2412                    guc->log.flush_count[GUC_ISR_LOG_BUFFER],
2413                    guc->log.total_overflow_count[GUC_ISR_LOG_BUFFER]);
2414
2415         seq_printf(m, "\tDPC:   flush count %10u, overflow count %10u\n",
2416                    guc->log.flush_count[GUC_DPC_LOG_BUFFER],
2417                    guc->log.total_overflow_count[GUC_DPC_LOG_BUFFER]);
2418
2419         seq_printf(m, "\tCRASH: flush count %10u, overflow count %10u\n",
2420                    guc->log.flush_count[GUC_CRASH_DUMP_LOG_BUFFER],
2421                    guc->log.total_overflow_count[GUC_CRASH_DUMP_LOG_BUFFER]);
2422
2423         seq_printf(m, "\tTotal flush interrupt count: %u\n",
2424                    guc->log.flush_interrupt_count);
2425
2426         seq_printf(m, "\tCapture miss count: %u\n",
2427                    guc->log.capture_miss_count);
2428 }
2429
2430 static void i915_guc_client_info(struct seq_file *m,
2431                                  struct drm_i915_private *dev_priv,
2432                                  struct i915_guc_client *client)
2433 {
2434         struct intel_engine_cs *engine;
2435         enum intel_engine_id id;
2436         uint64_t tot = 0;
2437
2438         seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2439                 client->priority, client->ctx_index, client->proc_desc_offset);
2440         seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2441                 client->doorbell_id, client->doorbell_offset, client->cookie);
2442         seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2443                 client->wq_size, client->wq_offset, client->wq_tail);
2444
2445         seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space);
2446         seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2447         seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2448
2449         for_each_engine(engine, dev_priv, id) {
2450                 u64 submissions = client->submissions[id];
2451                 tot += submissions;
2452                 seq_printf(m, "\tSubmissions: %llu %s\n",
2453                                 submissions, engine->name);
2454         }
2455         seq_printf(m, "\tTotal: %llu\n", tot);
2456 }
2457
2458 static int i915_guc_info(struct seq_file *m, void *data)
2459 {
2460         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2461         struct drm_device *dev = &dev_priv->drm;
2462         struct intel_guc guc;
2463         struct i915_guc_client client = {};
2464         struct intel_engine_cs *engine;
2465         enum intel_engine_id id;
2466         u64 total = 0;
2467
2468         if (!HAS_GUC_SCHED(dev_priv))
2469                 return 0;
2470
2471         if (mutex_lock_interruptible(&dev->struct_mutex))
2472                 return 0;
2473
2474         /* Take a local copy of the GuC data, so we can dump it at leisure */
2475         guc = dev_priv->guc;
2476         if (guc.execbuf_client)
2477                 client = *guc.execbuf_client;
2478
2479         mutex_unlock(&dev->struct_mutex);
2480
2481         seq_printf(m, "Doorbell map:\n");
2482         seq_printf(m, "\t%*pb\n", GUC_MAX_DOORBELLS, guc.doorbell_bitmap);
2483         seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc.db_cacheline);
2484
2485         seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
2486         seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
2487         seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
2488         seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
2489         seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
2490
2491         seq_printf(m, "\nGuC submissions:\n");
2492         for_each_engine(engine, dev_priv, id) {
2493                 u64 submissions = guc.submissions[id];
2494                 total += submissions;
2495                 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",
2496                         engine->name, submissions, guc.last_seqno[id]);
2497         }
2498         seq_printf(m, "\t%s: %llu\n", "Total", total);
2499
2500         seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
2501         i915_guc_client_info(m, dev_priv, &client);
2502
2503         i915_guc_log_info(m, dev_priv);
2504
2505         /* Add more as required ... */
2506
2507         return 0;
2508 }
2509
2510 static int i915_guc_log_dump(struct seq_file *m, void *data)
2511 {
2512         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2513         struct drm_i915_gem_object *obj;
2514         int i = 0, pg;
2515
2516         if (!dev_priv->guc.log.vma)
2517                 return 0;
2518
2519         obj = dev_priv->guc.log.vma->obj;
2520         for (pg = 0; pg < obj->base.size / PAGE_SIZE; pg++) {
2521                 u32 *log = kmap_atomic(i915_gem_object_get_page(obj, pg));
2522
2523                 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2524                         seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2525                                    *(log + i), *(log + i + 1),
2526                                    *(log + i + 2), *(log + i + 3));
2527
2528                 kunmap_atomic(log);
2529         }
2530
2531         seq_putc(m, '\n');
2532
2533         return 0;
2534 }
2535
2536 static int i915_guc_log_control_get(void *data, u64 *val)
2537 {
2538         struct drm_device *dev = data;
2539         struct drm_i915_private *dev_priv = to_i915(dev);
2540
2541         if (!dev_priv->guc.log.vma)
2542                 return -EINVAL;
2543
2544         *val = i915.guc_log_level;
2545
2546         return 0;
2547 }
2548
2549 static int i915_guc_log_control_set(void *data, u64 val)
2550 {
2551         struct drm_device *dev = data;
2552         struct drm_i915_private *dev_priv = to_i915(dev);
2553         int ret;
2554
2555         if (!dev_priv->guc.log.vma)
2556                 return -EINVAL;
2557
2558         ret = mutex_lock_interruptible(&dev->struct_mutex);
2559         if (ret)
2560                 return ret;
2561
2562         intel_runtime_pm_get(dev_priv);
2563         ret = i915_guc_log_control(dev_priv, val);
2564         intel_runtime_pm_put(dev_priv);
2565
2566         mutex_unlock(&dev->struct_mutex);
2567         return ret;
2568 }
2569
2570 DEFINE_SIMPLE_ATTRIBUTE(i915_guc_log_control_fops,
2571                         i915_guc_log_control_get, i915_guc_log_control_set,
2572                         "%lld\n");
2573
2574 static int i915_edp_psr_status(struct seq_file *m, void *data)
2575 {
2576         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2577         u32 psrperf = 0;
2578         u32 stat[3];
2579         enum pipe pipe;
2580         bool enabled = false;
2581
2582         if (!HAS_PSR(dev_priv)) {
2583                 seq_puts(m, "PSR not supported\n");
2584                 return 0;
2585         }
2586
2587         intel_runtime_pm_get(dev_priv);
2588
2589         mutex_lock(&dev_priv->psr.lock);
2590         seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2591         seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2592         seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2593         seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2594         seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2595                    dev_priv->psr.busy_frontbuffer_bits);
2596         seq_printf(m, "Re-enable work scheduled: %s\n",
2597                    yesno(work_busy(&dev_priv->psr.work.work)));
2598
2599         if (HAS_DDI(dev_priv))
2600                 enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2601         else {
2602                 for_each_pipe(dev_priv, pipe) {
2603                         enum transcoder cpu_transcoder =
2604                                 intel_pipe_to_cpu_transcoder(dev_priv, pipe);
2605                         enum intel_display_power_domain power_domain;
2606
2607                         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
2608                         if (!intel_display_power_get_if_enabled(dev_priv,
2609                                                                 power_domain))
2610                                 continue;
2611
2612                         stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2613                                 VLV_EDP_PSR_CURR_STATE_MASK;
2614                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2615                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2616                                 enabled = true;
2617
2618                         intel_display_power_put(dev_priv, power_domain);
2619                 }
2620         }
2621
2622         seq_printf(m, "Main link in standby mode: %s\n",
2623                    yesno(dev_priv->psr.link_standby));
2624
2625         seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2626
2627         if (!HAS_DDI(dev_priv))
2628                 for_each_pipe(dev_priv, pipe) {
2629                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2630                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2631                                 seq_printf(m, " pipe %c", pipe_name(pipe));
2632                 }
2633         seq_puts(m, "\n");
2634
2635         /*
2636          * VLV/CHV PSR has no kind of performance counter
2637          * SKL+ Perf counter is reset to 0 everytime DC state is entered
2638          */
2639         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2640                 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
2641                         EDP_PSR_PERF_CNT_MASK;
2642
2643                 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2644         }
2645         mutex_unlock(&dev_priv->psr.lock);
2646
2647         intel_runtime_pm_put(dev_priv);
2648         return 0;
2649 }
2650
2651 static int i915_sink_crc(struct seq_file *m, void *data)
2652 {
2653         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2654         struct drm_device *dev = &dev_priv->drm;
2655         struct intel_connector *connector;
2656         struct intel_dp *intel_dp = NULL;
2657         int ret;
2658         u8 crc[6];
2659
2660         drm_modeset_lock_all(dev);
2661         for_each_intel_connector(dev, connector) {
2662                 struct drm_crtc *crtc;
2663
2664                 if (!connector->base.state->best_encoder)
2665                         continue;
2666
2667                 crtc = connector->base.state->crtc;
2668                 if (!crtc->state->active)
2669                         continue;
2670
2671                 if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
2672                         continue;
2673
2674                 intel_dp = enc_to_intel_dp(connector->base.state->best_encoder);
2675
2676                 ret = intel_dp_sink_crc(intel_dp, crc);
2677                 if (ret)
2678                         goto out;
2679
2680                 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2681                            crc[0], crc[1], crc[2],
2682                            crc[3], crc[4], crc[5]);
2683                 goto out;
2684         }
2685         ret = -ENODEV;
2686 out:
2687         drm_modeset_unlock_all(dev);
2688         return ret;
2689 }
2690
2691 static int i915_energy_uJ(struct seq_file *m, void *data)
2692 {
2693         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2694         u64 power;
2695         u32 units;
2696
2697         if (INTEL_GEN(dev_priv) < 6)
2698                 return -ENODEV;
2699
2700         intel_runtime_pm_get(dev_priv);
2701
2702         rdmsrl(MSR_RAPL_POWER_UNIT, power);
2703         power = (power & 0x1f00) >> 8;
2704         units = 1000000 / (1 << power); /* convert to uJ */
2705         power = I915_READ(MCH_SECP_NRG_STTS);
2706         power *= units;
2707
2708         intel_runtime_pm_put(dev_priv);
2709
2710         seq_printf(m, "%llu", (long long unsigned)power);
2711
2712         return 0;
2713 }
2714
2715 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2716 {
2717         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2718         struct pci_dev *pdev = dev_priv->drm.pdev;
2719
2720         if (!HAS_RUNTIME_PM(dev_priv))
2721                 seq_puts(m, "Runtime power management not supported\n");
2722
2723         seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
2724         seq_printf(m, "IRQs disabled: %s\n",
2725                    yesno(!intel_irqs_enabled(dev_priv)));
2726 #ifdef CONFIG_PM
2727         seq_printf(m, "Usage count: %d\n",
2728                    atomic_read(&dev_priv->drm.dev->power.usage_count));
2729 #else
2730         seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2731 #endif
2732         seq_printf(m, "PCI device power state: %s [%d]\n",
2733                    pci_power_name(pdev->current_state),
2734                    pdev->current_state);
2735
2736         return 0;
2737 }
2738
2739 static int i915_power_domain_info(struct seq_file *m, void *unused)
2740 {
2741         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2742         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2743         int i;
2744
2745         mutex_lock(&power_domains->lock);
2746
2747         seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2748         for (i = 0; i < power_domains->power_well_count; i++) {
2749                 struct i915_power_well *power_well;
2750                 enum intel_display_power_domain power_domain;
2751
2752                 power_well = &power_domains->power_wells[i];
2753                 seq_printf(m, "%-25s %d\n", power_well->name,
2754                            power_well->count);
2755
2756                 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2757                      power_domain++) {
2758                         if (!(BIT(power_domain) & power_well->domains))
2759                                 continue;
2760
2761                         seq_printf(m, "  %-23s %d\n",
2762                                  intel_display_power_domain_str(power_domain),
2763                                  power_domains->domain_use_count[power_domain]);
2764                 }
2765         }
2766
2767         mutex_unlock(&power_domains->lock);
2768
2769         return 0;
2770 }
2771
2772 static int i915_dmc_info(struct seq_file *m, void *unused)
2773 {
2774         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2775         struct intel_csr *csr;
2776
2777         if (!HAS_CSR(dev_priv)) {
2778                 seq_puts(m, "not supported\n");
2779                 return 0;
2780         }
2781
2782         csr = &dev_priv->csr;
2783
2784         intel_runtime_pm_get(dev_priv);
2785
2786         seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2787         seq_printf(m, "path: %s\n", csr->fw_path);
2788
2789         if (!csr->dmc_payload)
2790                 goto out;
2791
2792         seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2793                    CSR_VERSION_MINOR(csr->version));
2794
2795         if (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6)) {
2796                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2797                            I915_READ(SKL_CSR_DC3_DC5_COUNT));
2798                 seq_printf(m, "DC5 -> DC6 count: %d\n",
2799                            I915_READ(SKL_CSR_DC5_DC6_COUNT));
2800         } else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) {
2801                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2802                            I915_READ(BXT_CSR_DC3_DC5_COUNT));
2803         }
2804
2805 out:
2806         seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2807         seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2808         seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2809
2810         intel_runtime_pm_put(dev_priv);
2811
2812         return 0;
2813 }
2814
2815 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2816                                  struct drm_display_mode *mode)
2817 {
2818         int i;
2819
2820         for (i = 0; i < tabs; i++)
2821                 seq_putc(m, '\t');
2822
2823         seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2824                    mode->base.id, mode->name,
2825                    mode->vrefresh, mode->clock,
2826                    mode->hdisplay, mode->hsync_start,
2827                    mode->hsync_end, mode->htotal,
2828                    mode->vdisplay, mode->vsync_start,
2829                    mode->vsync_end, mode->vtotal,
2830                    mode->type, mode->flags);
2831 }
2832
2833 static void intel_encoder_info(struct seq_file *m,
2834                                struct intel_crtc *intel_crtc,
2835                                struct intel_encoder *intel_encoder)
2836 {
2837         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2838         struct drm_device *dev = &dev_priv->drm;
2839         struct drm_crtc *crtc = &intel_crtc->base;
2840         struct intel_connector *intel_connector;
2841         struct drm_encoder *encoder;
2842
2843         encoder = &intel_encoder->base;
2844         seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2845                    encoder->base.id, encoder->name);
2846         for_each_connector_on_encoder(dev, encoder, intel_connector) {
2847                 struct drm_connector *connector = &intel_connector->base;
2848                 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2849                            connector->base.id,
2850                            connector->name,
2851                            drm_get_connector_status_name(connector->status));
2852                 if (connector->status == connector_status_connected) {
2853                         struct drm_display_mode *mode = &crtc->mode;
2854                         seq_printf(m, ", mode:\n");
2855                         intel_seq_print_mode(m, 2, mode);
2856                 } else {
2857                         seq_putc(m, '\n');
2858                 }
2859         }
2860 }
2861
2862 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2863 {
2864         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2865         struct drm_device *dev = &dev_priv->drm;
2866         struct drm_crtc *crtc = &intel_crtc->base;
2867         struct intel_encoder *intel_encoder;
2868         struct drm_plane_state *plane_state = crtc->primary->state;
2869         struct drm_framebuffer *fb = plane_state->fb;
2870
2871         if (fb)
2872                 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2873                            fb->base.id, plane_state->src_x >> 16,
2874                            plane_state->src_y >> 16, fb->width, fb->height);
2875         else
2876                 seq_puts(m, "\tprimary plane disabled\n");
2877         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2878                 intel_encoder_info(m, intel_crtc, intel_encoder);
2879 }
2880
2881 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2882 {
2883         struct drm_display_mode *mode = panel->fixed_mode;
2884
2885         seq_printf(m, "\tfixed mode:\n");
2886         intel_seq_print_mode(m, 2, mode);
2887 }
2888
2889 static void intel_dp_info(struct seq_file *m,
2890                           struct intel_connector *intel_connector)
2891 {
2892         struct intel_encoder *intel_encoder = intel_connector->encoder;
2893         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2894
2895         seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2896         seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2897         if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
2898                 intel_panel_info(m, &intel_connector->panel);
2899
2900         drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports,
2901                                 &intel_dp->aux);
2902 }
2903
2904 static void intel_hdmi_info(struct seq_file *m,
2905                             struct intel_connector *intel_connector)
2906 {
2907         struct intel_encoder *intel_encoder = intel_connector->encoder;
2908         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2909
2910         seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
2911 }
2912
2913 static void intel_lvds_info(struct seq_file *m,
2914                             struct intel_connector *intel_connector)
2915 {
2916         intel_panel_info(m, &intel_connector->panel);
2917 }
2918
2919 static void intel_connector_info(struct seq_file *m,
2920                                  struct drm_connector *connector)
2921 {
2922         struct intel_connector *intel_connector = to_intel_connector(connector);
2923         struct intel_encoder *intel_encoder = intel_connector->encoder;
2924         struct drm_display_mode *mode;
2925
2926         seq_printf(m, "connector %d: type %s, status: %s\n",
2927                    connector->base.id, connector->name,
2928                    drm_get_connector_status_name(connector->status));
2929         if (connector->status == connector_status_connected) {
2930                 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2931                 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2932                            connector->display_info.width_mm,
2933                            connector->display_info.height_mm);
2934                 seq_printf(m, "\tsubpixel order: %s\n",
2935                            drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2936                 seq_printf(m, "\tCEA rev: %d\n",
2937                            connector->display_info.cea_rev);
2938         }
2939
2940         if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
2941                 return;
2942
2943         switch (connector->connector_type) {
2944         case DRM_MODE_CONNECTOR_DisplayPort:
2945         case DRM_MODE_CONNECTOR_eDP:
2946                 intel_dp_info(m, intel_connector);
2947                 break;
2948         case DRM_MODE_CONNECTOR_LVDS:
2949                 if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2950                         intel_lvds_info(m, intel_connector);
2951                 break;
2952         case DRM_MODE_CONNECTOR_HDMIA:
2953                 if (intel_encoder->type == INTEL_OUTPUT_HDMI ||
2954                     intel_encoder->type == INTEL_OUTPUT_UNKNOWN)
2955                         intel_hdmi_info(m, intel_connector);
2956                 break;
2957         default:
2958                 break;
2959         }
2960
2961         seq_printf(m, "\tmodes:\n");
2962         list_for_each_entry(mode, &connector->modes, head)
2963                 intel_seq_print_mode(m, 2, mode);
2964 }
2965
2966 static bool cursor_active(struct drm_i915_private *dev_priv, int pipe)
2967 {
2968         u32 state;
2969
2970         if (IS_845G(dev_priv) || IS_I865G(dev_priv))
2971                 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
2972         else
2973                 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2974
2975         return state;
2976 }
2977
2978 static bool cursor_position(struct drm_i915_private *dev_priv,
2979                             int pipe, int *x, int *y)
2980 {
2981         u32 pos;
2982
2983         pos = I915_READ(CURPOS(pipe));
2984
2985         *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2986         if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2987                 *x = -*x;
2988
2989         *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2990         if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2991                 *y = -*y;
2992
2993         return cursor_active(dev_priv, pipe);
2994 }
2995
2996 static const char *plane_type(enum drm_plane_type type)
2997 {
2998         switch (type) {
2999         case DRM_PLANE_TYPE_OVERLAY:
3000                 return "OVL";
3001         case DRM_PLANE_TYPE_PRIMARY:
3002                 return "PRI";
3003         case DRM_PLANE_TYPE_CURSOR:
3004                 return "CUR";
3005         /*
3006          * Deliberately omitting default: to generate compiler warnings
3007          * when a new drm_plane_type gets added.
3008          */
3009         }
3010
3011         return "unknown";
3012 }
3013
3014 static const char *plane_rotation(unsigned int rotation)
3015 {
3016         static char buf[48];
3017         /*
3018          * According to doc only one DRM_ROTATE_ is allowed but this
3019          * will print them all to visualize if the values are misused
3020          */
3021         snprintf(buf, sizeof(buf),
3022                  "%s%s%s%s%s%s(0x%08x)",
3023                  (rotation & DRM_ROTATE_0) ? "0 " : "",
3024                  (rotation & DRM_ROTATE_90) ? "90 " : "",
3025                  (rotation & DRM_ROTATE_180) ? "180 " : "",
3026                  (rotation & DRM_ROTATE_270) ? "270 " : "",
3027                  (rotation & DRM_REFLECT_X) ? "FLIPX " : "",
3028                  (rotation & DRM_REFLECT_Y) ? "FLIPY " : "",
3029                  rotation);
3030
3031         return buf;
3032 }
3033
3034 static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3035 {
3036         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3037         struct drm_device *dev = &dev_priv->drm;
3038         struct intel_plane *intel_plane;
3039
3040         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3041                 struct drm_plane_state *state;
3042                 struct drm_plane *plane = &intel_plane->base;
3043                 char *format_name;
3044
3045                 if (!plane->state) {
3046                         seq_puts(m, "plane->state is NULL!\n");
3047                         continue;
3048                 }
3049
3050                 state = plane->state;
3051
3052                 if (state->fb) {
3053                         format_name = drm_get_format_name(state->fb->pixel_format);
3054                 } else {
3055                         format_name = kstrdup("N/A", GFP_KERNEL);
3056                 }
3057
3058                 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3059                            plane->base.id,
3060                            plane_type(intel_plane->base.type),
3061                            state->crtc_x, state->crtc_y,
3062                            state->crtc_w, state->crtc_h,
3063                            (state->src_x >> 16),
3064                            ((state->src_x & 0xffff) * 15625) >> 10,
3065                            (state->src_y >> 16),
3066                            ((state->src_y & 0xffff) * 15625) >> 10,
3067                            (state->src_w >> 16),
3068                            ((state->src_w & 0xffff) * 15625) >> 10,
3069                            (state->src_h >> 16),
3070                            ((state->src_h & 0xffff) * 15625) >> 10,
3071                            format_name,
3072                            plane_rotation(state->rotation));
3073
3074                 kfree(format_name);
3075         }
3076 }
3077
3078 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3079 {
3080         struct intel_crtc_state *pipe_config;
3081         int num_scalers = intel_crtc->num_scalers;
3082         int i;
3083
3084         pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3085
3086         /* Not all platformas have a scaler */
3087         if (num_scalers) {
3088                 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3089                            num_scalers,
3090                            pipe_config->scaler_state.scaler_users,
3091                            pipe_config->scaler_state.scaler_id);
3092
3093                 for (i = 0; i < SKL_NUM_SCALERS; i++) {
3094                         struct intel_scaler *sc =
3095                                         &pipe_config->scaler_state.scalers[i];
3096
3097                         seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3098                                    i, yesno(sc->in_use), sc->mode);
3099                 }
3100                 seq_puts(m, "\n");
3101         } else {
3102                 seq_puts(m, "\tNo scalers available on this platform\n");
3103         }
3104 }
3105
3106 static int i915_display_info(struct seq_file *m, void *unused)
3107 {
3108         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3109         struct drm_device *dev = &dev_priv->drm;
3110         struct intel_crtc *crtc;
3111         struct drm_connector *connector;
3112
3113         intel_runtime_pm_get(dev_priv);
3114         drm_modeset_lock_all(dev);
3115         seq_printf(m, "CRTC info\n");
3116         seq_printf(m, "---------\n");
3117         for_each_intel_crtc(dev, crtc) {
3118                 bool active;
3119                 struct intel_crtc_state *pipe_config;
3120                 int x, y;
3121
3122                 pipe_config = to_intel_crtc_state(crtc->base.state);
3123
3124                 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3125                            crtc->base.base.id, pipe_name(crtc->pipe),
3126                            yesno(pipe_config->base.active),
3127                            pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3128                            yesno(pipe_config->dither), pipe_config->pipe_bpp);
3129
3130                 if (pipe_config->base.active) {
3131                         intel_crtc_info(m, crtc);
3132
3133                         active = cursor_position(dev_priv, crtc->pipe, &x, &y);
3134                         seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
3135                                    yesno(crtc->cursor_base),
3136                                    x, y, crtc->base.cursor->state->crtc_w,
3137                                    crtc->base.cursor->state->crtc_h,
3138                                    crtc->cursor_addr, yesno(active));
3139                         intel_scaler_info(m, crtc);
3140                         intel_plane_info(m, crtc);
3141                 }
3142
3143                 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3144                            yesno(!crtc->cpu_fifo_underrun_disabled),
3145                            yesno(!crtc->pch_fifo_underrun_disabled));
3146         }
3147
3148         seq_printf(m, "\n");
3149         seq_printf(m, "Connector info\n");
3150         seq_printf(m, "--------------\n");
3151         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3152                 intel_connector_info(m, connector);
3153         }
3154         drm_modeset_unlock_all(dev);
3155         intel_runtime_pm_put(dev_priv);
3156
3157         return 0;
3158 }
3159
3160 static int i915_engine_info(struct seq_file *m, void *unused)
3161 {
3162         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3163         struct intel_engine_cs *engine;
3164         enum intel_engine_id id;
3165
3166         intel_runtime_pm_get(dev_priv);
3167
3168         for_each_engine(engine, dev_priv, id) {
3169                 struct intel_breadcrumbs *b = &engine->breadcrumbs;
3170                 struct drm_i915_gem_request *rq;
3171                 struct rb_node *rb;
3172                 u64 addr;
3173
3174                 seq_printf(m, "%s\n", engine->name);
3175                 seq_printf(m, "\tcurrent seqno %x, last %x, hangcheck %x [score %d]\n",
3176                            intel_engine_get_seqno(engine),
3177                            engine->timeline->last_submitted_seqno,
3178                            engine->hangcheck.seqno,
3179                            engine->hangcheck.score);
3180
3181                 rcu_read_lock();
3182
3183                 seq_printf(m, "\tRequests:\n");
3184
3185                 rq = list_first_entry(&engine->timeline->requests,
3186                                       struct drm_i915_gem_request, link);
3187                 if (&rq->link != &engine->timeline->requests)
3188                         print_request(m, rq, "\t\tfirst  ");
3189
3190                 rq = list_last_entry(&engine->timeline->requests,
3191                                      struct drm_i915_gem_request, link);
3192                 if (&rq->link != &engine->timeline->requests)
3193                         print_request(m, rq, "\t\tlast   ");
3194
3195                 rq = i915_gem_find_active_request(engine);
3196                 if (rq) {
3197                         print_request(m, rq, "\t\tactive ");
3198                         seq_printf(m,
3199                                    "\t\t[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]\n",
3200                                    rq->head, rq->postfix, rq->tail,
3201                                    rq->batch ? upper_32_bits(rq->batch->node.start) : ~0u,
3202                                    rq->batch ? lower_32_bits(rq->batch->node.start) : ~0u);
3203                 }
3204
3205                 seq_printf(m, "\tRING_START: 0x%08x [0x%08x]\n",
3206                            I915_READ(RING_START(engine->mmio_base)),
3207                            rq ? i915_ggtt_offset(rq->ring->vma) : 0);
3208                 seq_printf(m, "\tRING_HEAD:  0x%08x [0x%08x]\n",
3209                            I915_READ(RING_HEAD(engine->mmio_base)) & HEAD_ADDR,
3210                            rq ? rq->ring->head : 0);
3211                 seq_printf(m, "\tRING_TAIL:  0x%08x [0x%08x]\n",
3212                            I915_READ(RING_TAIL(engine->mmio_base)) & TAIL_ADDR,
3213                            rq ? rq->ring->tail : 0);
3214                 seq_printf(m, "\tRING_CTL:   0x%08x [%s]\n",
3215                            I915_READ(RING_CTL(engine->mmio_base)),
3216                            I915_READ(RING_CTL(engine->mmio_base)) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? "waiting" : "");
3217
3218                 rcu_read_unlock();
3219
3220                 addr = intel_engine_get_active_head(engine);
3221                 seq_printf(m, "\tACTHD:  0x%08x_%08x\n",
3222                            upper_32_bits(addr), lower_32_bits(addr));
3223                 addr = intel_engine_get_last_batch_head(engine);
3224                 seq_printf(m, "\tBBADDR: 0x%08x_%08x\n",
3225                            upper_32_bits(addr), lower_32_bits(addr));
3226
3227                 if (i915.enable_execlists) {
3228                         u32 ptr, read, write;
3229
3230                         seq_printf(m, "\tExeclist status: 0x%08x %08x\n",
3231                                    I915_READ(RING_EXECLIST_STATUS_LO(engine)),
3232                                    I915_READ(RING_EXECLIST_STATUS_HI(engine)));
3233
3234                         ptr = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
3235                         read = GEN8_CSB_READ_PTR(ptr);
3236                         write = GEN8_CSB_WRITE_PTR(ptr);
3237                         seq_printf(m, "\tExeclist CSB read %d, write %d\n",
3238                                    read, write);
3239                         if (read >= GEN8_CSB_ENTRIES)
3240                                 read = 0;
3241                         if (write >= GEN8_CSB_ENTRIES)
3242                                 write = 0;
3243                         if (read > write)
3244                                 write += GEN8_CSB_ENTRIES;
3245                         while (read < write) {
3246                                 unsigned int idx = ++read % GEN8_CSB_ENTRIES;
3247
3248                                 seq_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n",
3249                                            idx,
3250                                            I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, idx)),
3251                                            I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, idx)));
3252                         }
3253
3254                         rcu_read_lock();
3255                         rq = READ_ONCE(engine->execlist_port[0].request);
3256                         if (rq)
3257                                 print_request(m, rq, "\t\tELSP[0] ");
3258                         else
3259                                 seq_printf(m, "\t\tELSP[0] idle\n");
3260                         rq = READ_ONCE(engine->execlist_port[1].request);
3261                         if (rq)
3262                                 print_request(m, rq, "\t\tELSP[1] ");
3263                         else
3264                                 seq_printf(m, "\t\tELSP[1] idle\n");
3265                         rcu_read_unlock();
3266                 } else if (INTEL_GEN(dev_priv) > 6) {
3267                         seq_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
3268                                    I915_READ(RING_PP_DIR_BASE(engine)));
3269                         seq_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n",
3270                                    I915_READ(RING_PP_DIR_BASE_READ(engine)));
3271                         seq_printf(m, "\tPP_DIR_DCLV: 0x%08x\n",
3272                                    I915_READ(RING_PP_DIR_DCLV(engine)));
3273                 }
3274
3275                 spin_lock(&b->lock);
3276                 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
3277                         struct intel_wait *w = container_of(rb, typeof(*w), node);
3278
3279                         seq_printf(m, "\t%s [%d] waiting for %x\n",
3280                                    w->tsk->comm, w->tsk->pid, w->seqno);
3281                 }
3282                 spin_unlock(&b->lock);
3283
3284                 seq_puts(m, "\n");
3285         }
3286
3287         intel_runtime_pm_put(dev_priv);
3288
3289         return 0;
3290 }
3291
3292 static int i915_semaphore_status(struct seq_file *m, void *unused)
3293 {
3294         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3295         struct drm_device *dev = &dev_priv->drm;
3296         struct intel_engine_cs *engine;
3297         int num_rings = INTEL_INFO(dev_priv)->num_rings;
3298         enum intel_engine_id id;
3299         int j, ret;
3300
3301         if (!i915.semaphores) {
3302                 seq_puts(m, "Semaphores are disabled\n");
3303                 return 0;
3304         }
3305
3306         ret = mutex_lock_interruptible(&dev->struct_mutex);
3307         if (ret)
3308                 return ret;
3309         intel_runtime_pm_get(dev_priv);
3310
3311         if (IS_BROADWELL(dev_priv)) {
3312                 struct page *page;
3313                 uint64_t *seqno;
3314
3315                 page = i915_gem_object_get_page(dev_priv->semaphore->obj, 0);
3316
3317                 seqno = (uint64_t *)kmap_atomic(page);
3318                 for_each_engine(engine, dev_priv, id) {
3319                         uint64_t offset;
3320
3321                         seq_printf(m, "%s\n", engine->name);
3322
3323                         seq_puts(m, "  Last signal:");
3324                         for (j = 0; j < num_rings; j++) {
3325                                 offset = id * I915_NUM_ENGINES + j;
3326                                 seq_printf(m, "0x%08llx (0x%02llx) ",
3327                                            seqno[offset], offset * 8);
3328                         }
3329                         seq_putc(m, '\n');
3330
3331                         seq_puts(m, "  Last wait:  ");
3332                         for (j = 0; j < num_rings; j++) {
3333                                 offset = id + (j * I915_NUM_ENGINES);
3334                                 seq_printf(m, "0x%08llx (0x%02llx) ",
3335                                            seqno[offset], offset * 8);
3336                         }
3337                         seq_putc(m, '\n');
3338
3339                 }
3340                 kunmap_atomic(seqno);
3341         } else {
3342                 seq_puts(m, "  Last signal:");
3343                 for_each_engine(engine, dev_priv, id)
3344                         for (j = 0; j < num_rings; j++)
3345                                 seq_printf(m, "0x%08x\n",
3346                                            I915_READ(engine->semaphore.mbox.signal[j]));
3347                 seq_putc(m, '\n');
3348         }
3349
3350         intel_runtime_pm_put(dev_priv);
3351         mutex_unlock(&dev->struct_mutex);
3352         return 0;
3353 }
3354
3355 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3356 {
3357         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3358         struct drm_device *dev = &dev_priv->drm;
3359         int i;
3360
3361         drm_modeset_lock_all(dev);
3362         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3363                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3364
3365                 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3366                 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3367                            pll->config.crtc_mask, pll->active_mask, yesno(pll->on));
3368                 seq_printf(m, " tracked hardware state:\n");
3369                 seq_printf(m, " dpll:    0x%08x\n", pll->config.hw_state.dpll);
3370                 seq_printf(m, " dpll_md: 0x%08x\n",
3371                            pll->config.hw_state.dpll_md);
3372                 seq_printf(m, " fp0:     0x%08x\n", pll->config.hw_state.fp0);
3373                 seq_printf(m, " fp1:     0x%08x\n", pll->config.hw_state.fp1);
3374                 seq_printf(m, " wrpll:   0x%08x\n", pll->config.hw_state.wrpll);
3375         }
3376         drm_modeset_unlock_all(dev);
3377
3378         return 0;
3379 }
3380
3381 static int i915_wa_registers(struct seq_file *m, void *unused)
3382 {
3383         int i;
3384         int ret;
3385         struct intel_engine_cs *engine;
3386         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3387         struct drm_device *dev = &dev_priv->drm;
3388         struct i915_workarounds *workarounds = &dev_priv->workarounds;
3389         enum intel_engine_id id;
3390
3391         ret = mutex_lock_interruptible(&dev->struct_mutex);
3392         if (ret)
3393                 return ret;
3394
3395         intel_runtime_pm_get(dev_priv);
3396
3397         seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
3398         for_each_engine(engine, dev_priv, id)
3399                 seq_printf(m, "HW whitelist count for %s: %d\n",
3400                            engine->name, workarounds->hw_whitelist_count[id]);
3401         for (i = 0; i < workarounds->count; ++i) {
3402                 i915_reg_t addr;
3403                 u32 mask, value, read;
3404                 bool ok;
3405
3406                 addr = workarounds->reg[i].addr;
3407                 mask = workarounds->reg[i].mask;
3408                 value = workarounds->reg[i].value;
3409                 read = I915_READ(addr);
3410                 ok = (value & mask) == (read & mask);
3411                 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3412                            i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
3413         }
3414
3415         intel_runtime_pm_put(dev_priv);
3416         mutex_unlock(&dev->struct_mutex);
3417
3418         return 0;
3419 }
3420
3421 static int i915_ddb_info(struct seq_file *m, void *unused)
3422 {
3423         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3424         struct drm_device *dev = &dev_priv->drm;
3425         struct skl_ddb_allocation *ddb;
3426         struct skl_ddb_entry *entry;
3427         enum pipe pipe;
3428         int plane;
3429
3430         if (INTEL_GEN(dev_priv) < 9)
3431                 return 0;
3432
3433         drm_modeset_lock_all(dev);
3434
3435         ddb = &dev_priv->wm.skl_hw.ddb;
3436
3437         seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3438
3439         for_each_pipe(dev_priv, pipe) {
3440                 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3441
3442                 for_each_universal_plane(dev_priv, pipe, plane) {
3443                         entry = &ddb->plane[pipe][plane];
3444                         seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane + 1,
3445                                    entry->start, entry->end,
3446                                    skl_ddb_entry_size(entry));
3447                 }
3448
3449                 entry = &ddb->plane[pipe][PLANE_CURSOR];
3450                 seq_printf(m, "  %-13s%8u%8u%8u\n", "Cursor", entry->start,
3451                            entry->end, skl_ddb_entry_size(entry));
3452         }
3453
3454         drm_modeset_unlock_all(dev);
3455
3456         return 0;
3457 }
3458
3459 static void drrs_status_per_crtc(struct seq_file *m,
3460                                  struct drm_device *dev,
3461                                  struct intel_crtc *intel_crtc)
3462 {
3463         struct drm_i915_private *dev_priv = to_i915(dev);
3464         struct i915_drrs *drrs = &dev_priv->drrs;
3465         int vrefresh = 0;
3466         struct drm_connector *connector;
3467
3468         drm_for_each_connector(connector, dev) {
3469                 if (connector->state->crtc != &intel_crtc->base)
3470                         continue;
3471
3472                 seq_printf(m, "%s:\n", connector->name);
3473         }
3474
3475         if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3476                 seq_puts(m, "\tVBT: DRRS_type: Static");
3477         else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3478                 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3479         else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3480                 seq_puts(m, "\tVBT: DRRS_type: None");
3481         else
3482                 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3483
3484         seq_puts(m, "\n\n");
3485
3486         if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3487                 struct intel_panel *panel;
3488
3489                 mutex_lock(&drrs->mutex);
3490                 /* DRRS Supported */
3491                 seq_puts(m, "\tDRRS Supported: Yes\n");
3492
3493                 /* disable_drrs() will make drrs->dp NULL */
3494                 if (!drrs->dp) {
3495                         seq_puts(m, "Idleness DRRS: Disabled");
3496                         mutex_unlock(&drrs->mutex);
3497                         return;
3498                 }
3499
3500                 panel = &drrs->dp->attached_connector->panel;
3501                 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3502                                         drrs->busy_frontbuffer_bits);
3503
3504                 seq_puts(m, "\n\t\t");
3505                 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3506                         seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3507                         vrefresh = panel->fixed_mode->vrefresh;
3508                 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3509                         seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3510                         vrefresh = panel->downclock_mode->vrefresh;
3511                 } else {
3512                         seq_printf(m, "DRRS_State: Unknown(%d)\n",
3513                                                 drrs->refresh_rate_type);
3514                         mutex_unlock(&drrs->mutex);
3515                         return;
3516                 }
3517                 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3518
3519                 seq_puts(m, "\n\t\t");
3520                 mutex_unlock(&drrs->mutex);
3521         } else {
3522                 /* DRRS not supported. Print the VBT parameter*/
3523                 seq_puts(m, "\tDRRS Supported : No");
3524         }
3525         seq_puts(m, "\n");
3526 }
3527
3528 static int i915_drrs_status(struct seq_file *m, void *unused)
3529 {
3530         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3531         struct drm_device *dev = &dev_priv->drm;
3532         struct intel_crtc *intel_crtc;
3533         int active_crtc_cnt = 0;
3534
3535         drm_modeset_lock_all(dev);
3536         for_each_intel_crtc(dev, intel_crtc) {
3537                 if (intel_crtc->base.state->active) {
3538                         active_crtc_cnt++;
3539                         seq_printf(m, "\nCRTC %d:  ", active_crtc_cnt);
3540
3541                         drrs_status_per_crtc(m, dev, intel_crtc);
3542                 }
3543         }
3544         drm_modeset_unlock_all(dev);
3545
3546         if (!active_crtc_cnt)
3547                 seq_puts(m, "No active crtc found\n");
3548
3549         return 0;
3550 }
3551
3552 struct pipe_crc_info {
3553         const char *name;
3554         struct drm_i915_private *dev_priv;
3555         enum pipe pipe;
3556 };
3557
3558 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3559 {
3560         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3561         struct drm_device *dev = &dev_priv->drm;
3562         struct intel_encoder *intel_encoder;
3563         struct intel_digital_port *intel_dig_port;
3564         struct drm_connector *connector;
3565
3566         drm_modeset_lock_all(dev);
3567         drm_for_each_connector(connector, dev) {
3568                 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
3569                         continue;
3570
3571                 intel_encoder = intel_attached_encoder(connector);
3572                 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
3573                         continue;
3574
3575                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
3576                 if (!intel_dig_port->dp.can_mst)
3577                         continue;
3578
3579                 seq_printf(m, "MST Source Port %c\n",
3580                            port_name(intel_dig_port->port));
3581                 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3582         }
3583         drm_modeset_unlock_all(dev);
3584         return 0;
3585 }
3586
3587 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3588 {
3589         struct pipe_crc_info *info = inode->i_private;
3590         struct drm_i915_private *dev_priv = info->dev_priv;
3591         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3592
3593         if (info->pipe >= INTEL_INFO(dev_priv)->num_pipes)
3594                 return -ENODEV;
3595
3596         spin_lock_irq(&pipe_crc->lock);
3597
3598         if (pipe_crc->opened) {
3599                 spin_unlock_irq(&pipe_crc->lock);
3600                 return -EBUSY; /* already open */
3601         }
3602
3603         pipe_crc->opened = true;
3604         filep->private_data = inode->i_private;
3605
3606         spin_unlock_irq(&pipe_crc->lock);
3607
3608         return 0;
3609 }
3610
3611 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3612 {
3613         struct pipe_crc_info *info = inode->i_private;
3614         struct drm_i915_private *dev_priv = info->dev_priv;
3615         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3616
3617         spin_lock_irq(&pipe_crc->lock);
3618         pipe_crc->opened = false;
3619         spin_unlock_irq(&pipe_crc->lock);
3620
3621         return 0;
3622 }
3623
3624 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3625 #define PIPE_CRC_LINE_LEN       (6 * 8 + 5 + 1)
3626 /* account for \'0' */
3627 #define PIPE_CRC_BUFFER_LEN     (PIPE_CRC_LINE_LEN + 1)
3628
3629 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
3630 {
3631         assert_spin_locked(&pipe_crc->lock);
3632         return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3633                         INTEL_PIPE_CRC_ENTRIES_NR);
3634 }
3635
3636 static ssize_t
3637 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3638                    loff_t *pos)
3639 {
3640         struct pipe_crc_info *info = filep->private_data;
3641         struct drm_i915_private *dev_priv = info->dev_priv;
3642         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3643         char buf[PIPE_CRC_BUFFER_LEN];
3644         int n_entries;
3645         ssize_t bytes_read;
3646
3647         /*
3648          * Don't allow user space to provide buffers not big enough to hold
3649          * a line of data.
3650          */
3651         if (count < PIPE_CRC_LINE_LEN)
3652                 return -EINVAL;
3653
3654         if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
3655                 return 0;
3656
3657         /* nothing to read */
3658         spin_lock_irq(&pipe_crc->lock);
3659         while (pipe_crc_data_count(pipe_crc) == 0) {
3660                 int ret;
3661
3662                 if (filep->f_flags & O_NONBLOCK) {
3663                         spin_unlock_irq(&pipe_crc->lock);
3664                         return -EAGAIN;
3665                 }
3666
3667                 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3668                                 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3669                 if (ret) {
3670                         spin_unlock_irq(&pipe_crc->lock);
3671                         return ret;
3672                 }
3673         }
3674
3675         /* We now have one or more entries to read */
3676         n_entries = count / PIPE_CRC_LINE_LEN;
3677
3678         bytes_read = 0;
3679         while (n_entries > 0) {
3680                 struct intel_pipe_crc_entry *entry =
3681                         &pipe_crc->entries[pipe_crc->tail];
3682
3683                 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3684                              INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3685                         break;
3686
3687                 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3688                 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3689
3690                 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3691                                        "%8u %8x %8x %8x %8x %8x\n",
3692                                        entry->frame, entry->crc[0],
3693                                        entry->crc[1], entry->crc[2],
3694                                        entry->crc[3], entry->crc[4]);
3695
3696                 spin_unlock_irq(&pipe_crc->lock);
3697
3698                 if (copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN))
3699                         return -EFAULT;
3700
3701                 user_buf += PIPE_CRC_LINE_LEN;
3702                 n_entries--;
3703
3704                 spin_lock_irq(&pipe_crc->lock);
3705         }
3706
3707         spin_unlock_irq(&pipe_crc->lock);
3708
3709         return bytes_read;
3710 }
3711
3712 static const struct file_operations i915_pipe_crc_fops = {
3713         .owner = THIS_MODULE,
3714         .open = i915_pipe_crc_open,
3715         .read = i915_pipe_crc_read,
3716         .release = i915_pipe_crc_release,
3717 };
3718
3719 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3720         {
3721                 .name = "i915_pipe_A_crc",
3722                 .pipe = PIPE_A,
3723         },
3724         {
3725                 .name = "i915_pipe_B_crc",
3726                 .pipe = PIPE_B,
3727         },
3728         {
3729                 .name = "i915_pipe_C_crc",
3730                 .pipe = PIPE_C,
3731         },
3732 };
3733
3734 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3735                                 enum pipe pipe)
3736 {
3737         struct drm_i915_private *dev_priv = to_i915(minor->dev);
3738         struct dentry *ent;
3739         struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3740
3741         info->dev_priv = dev_priv;
3742         ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3743                                   &i915_pipe_crc_fops);
3744         if (!ent)
3745                 return -ENOMEM;
3746
3747         return drm_add_fake_info_node(minor, ent, info);
3748 }
3749
3750 static const char * const pipe_crc_sources[] = {
3751         "none",
3752         "plane1",
3753         "plane2",
3754         "pf",
3755         "pipe",
3756         "TV",
3757         "DP-B",
3758         "DP-C",
3759         "DP-D",
3760         "auto",
3761 };
3762
3763 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3764 {
3765         BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3766         return pipe_crc_sources[source];
3767 }
3768
3769 static int display_crc_ctl_show(struct seq_file *m, void *data)
3770 {
3771         struct drm_i915_private *dev_priv = m->private;
3772         int i;
3773
3774         for (i = 0; i < I915_MAX_PIPES; i++)
3775                 seq_printf(m, "%c %s\n", pipe_name(i),
3776                            pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3777
3778         return 0;
3779 }
3780
3781 static int display_crc_ctl_open(struct inode *inode, struct file *file)
3782 {
3783         return single_open(file, display_crc_ctl_show, inode->i_private);
3784 }
3785
3786 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3787                                  uint32_t *val)
3788 {
3789         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3790                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3791
3792         switch (*source) {
3793         case INTEL_PIPE_CRC_SOURCE_PIPE:
3794                 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3795                 break;
3796         case INTEL_PIPE_CRC_SOURCE_NONE:
3797                 *val = 0;
3798                 break;
3799         default:
3800                 return -EINVAL;
3801         }
3802
3803         return 0;
3804 }
3805
3806 static int i9xx_pipe_crc_auto_source(struct drm_i915_private *dev_priv,
3807                                      enum pipe pipe,
3808                                      enum intel_pipe_crc_source *source)
3809 {
3810         struct drm_device *dev = &dev_priv->drm;
3811         struct intel_encoder *encoder;
3812         struct intel_crtc *crtc;
3813         struct intel_digital_port *dig_port;
3814         int ret = 0;
3815
3816         *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3817
3818         drm_modeset_lock_all(dev);
3819         for_each_intel_encoder(dev, encoder) {
3820                 if (!encoder->base.crtc)
3821                         continue;
3822
3823                 crtc = to_intel_crtc(encoder->base.crtc);
3824
3825                 if (crtc->pipe != pipe)
3826                         continue;
3827
3828                 switch (encoder->type) {
3829                 case INTEL_OUTPUT_TVOUT:
3830                         *source = INTEL_PIPE_CRC_SOURCE_TV;
3831                         break;
3832                 case INTEL_OUTPUT_DP:
3833                 case INTEL_OUTPUT_EDP:
3834                         dig_port = enc_to_dig_port(&encoder->base);
3835                         switch (dig_port->port) {
3836                         case PORT_B:
3837                                 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3838                                 break;
3839                         case PORT_C:
3840                                 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3841                                 break;
3842                         case PORT_D:
3843                                 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3844                                 break;
3845                         default:
3846                                 WARN(1, "nonexisting DP port %c\n",
3847                                      port_name(dig_port->port));
3848                                 break;
3849                         }
3850                         break;
3851                 default:
3852                         break;
3853                 }
3854         }
3855         drm_modeset_unlock_all(dev);
3856
3857         return ret;
3858 }
3859
3860 static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
3861                                 enum pipe pipe,
3862                                 enum intel_pipe_crc_source *source,
3863                                 uint32_t *val)
3864 {
3865         bool need_stable_symbols = false;
3866
3867         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3868                 int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
3869                 if (ret)
3870                         return ret;
3871         }
3872
3873         switch (*source) {
3874         case INTEL_PIPE_CRC_SOURCE_PIPE:
3875                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3876                 break;
3877         case INTEL_PIPE_CRC_SOURCE_DP_B:
3878                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3879                 need_stable_symbols = true;
3880                 break;
3881         case INTEL_PIPE_CRC_SOURCE_DP_C:
3882                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3883                 need_stable_symbols = true;
3884                 break;
3885         case INTEL_PIPE_CRC_SOURCE_DP_D:
3886                 if (!IS_CHERRYVIEW(dev_priv))
3887                         return -EINVAL;
3888                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3889                 need_stable_symbols = true;
3890                 break;
3891         case INTEL_PIPE_CRC_SOURCE_NONE:
3892                 *val = 0;
3893                 break;
3894         default:
3895                 return -EINVAL;
3896         }
3897
3898         /*
3899          * When the pipe CRC tap point is after the transcoders we need
3900          * to tweak symbol-level features to produce a deterministic series of
3901          * symbols for a given frame. We need to reset those features only once
3902          * a frame (instead of every nth symbol):
3903          *   - DC-balance: used to ensure a better clock recovery from the data
3904          *     link (SDVO)
3905          *   - DisplayPort scrambling: used for EMI reduction
3906          */
3907         if (need_stable_symbols) {
3908                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3909
3910                 tmp |= DC_BALANCE_RESET_VLV;
3911                 switch (pipe) {
3912                 case PIPE_A:
3913                         tmp |= PIPE_A_SCRAMBLE_RESET;
3914                         break;
3915                 case PIPE_B:
3916                         tmp |= PIPE_B_SCRAMBLE_RESET;
3917                         break;
3918                 case PIPE_C:
3919                         tmp |= PIPE_C_SCRAMBLE_RESET;
3920                         break;
3921                 default:
3922                         return -EINVAL;
3923                 }
3924                 I915_WRITE(PORT_DFT2_G4X, tmp);
3925         }
3926
3927         return 0;
3928 }
3929
3930 static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
3931                                  enum pipe pipe,
3932                                  enum intel_pipe_crc_source *source,
3933                                  uint32_t *val)
3934 {
3935         bool need_stable_symbols = false;
3936
3937         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3938                 int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
3939                 if (ret)
3940                         return ret;
3941         }
3942
3943         switch (*source) {
3944         case INTEL_PIPE_CRC_SOURCE_PIPE:
3945                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3946                 break;
3947         case INTEL_PIPE_CRC_SOURCE_TV:
3948                 if (!SUPPORTS_TV(dev_priv))
3949                         return -EINVAL;
3950                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3951                 break;
3952         case INTEL_PIPE_CRC_SOURCE_DP_B:
3953                 if (!IS_G4X(dev_priv))
3954                         return -EINVAL;
3955                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3956                 need_stable_symbols = true;
3957                 break;
3958         case INTEL_PIPE_CRC_SOURCE_DP_C:
3959                 if (!IS_G4X(dev_priv))
3960                         return -EINVAL;
3961                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3962                 need_stable_symbols = true;
3963                 break;
3964         case INTEL_PIPE_CRC_SOURCE_DP_D:
3965                 if (!IS_G4X(dev_priv))
3966                         return -EINVAL;
3967                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3968                 need_stable_symbols = true;
3969                 break;
3970         case INTEL_PIPE_CRC_SOURCE_NONE:
3971                 *val = 0;
3972                 break;
3973         default:
3974                 return -EINVAL;
3975         }
3976
3977         /*
3978          * When the pipe CRC tap point is after the transcoders we need
3979          * to tweak symbol-level features to produce a deterministic series of
3980          * symbols for a given frame. We need to reset those features only once
3981          * a frame (instead of every nth symbol):
3982          *   - DC-balance: used to ensure a better clock recovery from the data
3983          *     link (SDVO)
3984          *   - DisplayPort scrambling: used for EMI reduction
3985          */
3986         if (need_stable_symbols) {
3987                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3988
3989                 WARN_ON(!IS_G4X(dev_priv));
3990
3991                 I915_WRITE(PORT_DFT_I9XX,
3992                            I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3993
3994                 if (pipe == PIPE_A)
3995                         tmp |= PIPE_A_SCRAMBLE_RESET;
3996                 else
3997                         tmp |= PIPE_B_SCRAMBLE_RESET;
3998
3999                 I915_WRITE(PORT_DFT2_G4X, tmp);
4000         }
4001
4002         return 0;
4003 }
4004
4005 static void vlv_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
4006                                          enum pipe pipe)
4007 {
4008         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
4009
4010         switch (pipe) {
4011         case PIPE_A:
4012                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
4013                 break;
4014         case PIPE_B:
4015                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
4016                 break;
4017         case PIPE_C:
4018                 tmp &= ~PIPE_C_SCRAMBLE_RESET;
4019                 break;
4020         default:
4021                 return;
4022         }
4023         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
4024                 tmp &= ~DC_BALANCE_RESET_VLV;
4025         I915_WRITE(PORT_DFT2_G4X, tmp);
4026
4027 }
4028
4029 static void g4x_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
4030                                          enum pipe pipe)
4031 {
4032         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
4033
4034         if (pipe == PIPE_A)
4035                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
4036         else
4037                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
4038         I915_WRITE(PORT_DFT2_G4X, tmp);
4039
4040         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
4041                 I915_WRITE(PORT_DFT_I9XX,
4042                            I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
4043         }
4044 }
4045
4046 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
4047                                 uint32_t *val)
4048 {
4049         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
4050                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
4051
4052         switch (*source) {
4053         case INTEL_PIPE_CRC_SOURCE_PLANE1:
4054                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
4055                 break;
4056         case INTEL_PIPE_CRC_SOURCE_PLANE2:
4057                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
4058                 break;
4059         case INTEL_PIPE_CRC_SOURCE_PIPE:
4060                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
4061                 break;
4062         case INTEL_PIPE_CRC_SOURCE_NONE:
4063                 *val = 0;
4064                 break;
4065         default:
4066                 return -EINVAL;
4067         }
4068
4069         return 0;
4070 }
4071
4072 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_i915_private *dev_priv,
4073                                         bool enable)
4074 {
4075         struct drm_device *dev = &dev_priv->drm;
4076         struct intel_crtc *crtc =
4077                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
4078         struct intel_crtc_state *pipe_config;
4079         struct drm_atomic_state *state;
4080         int ret = 0;
4081
4082         drm_modeset_lock_all(dev);
4083         state = drm_atomic_state_alloc(dev);
4084         if (!state) {
4085                 ret = -ENOMEM;
4086                 goto out;
4087         }
4088
4089         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
4090         pipe_config = intel_atomic_get_crtc_state(state, crtc);
4091         if (IS_ERR(pipe_config)) {
4092                 ret = PTR_ERR(pipe_config);
4093                 goto out;
4094         }
4095
4096         pipe_config->pch_pfit.force_thru = enable;
4097         if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
4098             pipe_config->pch_pfit.enabled != enable)
4099                 pipe_config->base.connectors_changed = true;
4100
4101         ret = drm_atomic_commit(state);
4102 out:
4103         WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
4104         drm_modeset_unlock_all(dev);
4105         drm_atomic_state_put(state);
4106 }
4107
4108 static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
4109                                 enum pipe pipe,
4110                                 enum intel_pipe_crc_source *source,
4111                                 uint32_t *val)
4112 {
4113         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
4114                 *source = INTEL_PIPE_CRC_SOURCE_PF;
4115
4116         switch (*source) {
4117         case INTEL_PIPE_CRC_SOURCE_PLANE1:
4118                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
4119                 break;
4120         case INTEL_PIPE_CRC_SOURCE_PLANE2:
4121                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
4122                 break;
4123         case INTEL_PIPE_CRC_SOURCE_PF:
4124                 if (IS_HASWELL(dev_priv) && pipe == PIPE_A)
4125                         hsw_trans_edp_pipe_A_crc_wa(dev_priv, true);
4126
4127                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
4128                 break;
4129         case INTEL_PIPE_CRC_SOURCE_NONE:
4130                 *val = 0;
4131                 break;
4132         default:
4133                 return -EINVAL;
4134         }
4135
4136         return 0;
4137 }
4138
4139 static int pipe_crc_set_source(struct drm_i915_private *dev_priv,
4140                                enum pipe pipe,
4141                                enum intel_pipe_crc_source source)
4142 {
4143         struct drm_device *dev = &dev_priv->drm;
4144         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
4145         struct intel_crtc *crtc =
4146                         to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
4147         enum intel_display_power_domain power_domain;
4148         u32 val = 0; /* shut up gcc */
4149         int ret;
4150
4151         if (pipe_crc->source == source)
4152                 return 0;
4153
4154         /* forbid changing the source without going back to 'none' */
4155         if (pipe_crc->source && source)
4156                 return -EINVAL;
4157
4158         power_domain = POWER_DOMAIN_PIPE(pipe);
4159         if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
4160                 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
4161                 return -EIO;
4162         }
4163
4164         if (IS_GEN2(dev_priv))
4165                 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
4166         else if (INTEL_GEN(dev_priv) < 5)
4167                 ret = i9xx_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val);
4168         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4169                 ret = vlv_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val);
4170         else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv))
4171                 ret = ilk_pipe_crc_ctl_reg(&source, &val);
4172         else
4173                 ret = ivb_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val);
4174
4175         if (ret != 0)
4176                 goto out;
4177
4178         /* none -> real source transition */
4179         if (source) {
4180                 struct intel_pipe_crc_entry *entries;
4181
4182                 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4183                                  pipe_name(pipe), pipe_crc_source_name(source));
4184
4185                 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
4186                                   sizeof(pipe_crc->entries[0]),
4187                                   GFP_KERNEL);
4188                 if (!entries) {
4189                         ret = -ENOMEM;
4190                         goto out;
4191                 }
4192
4193                 /*
4194                  * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4195                  * enabled and disabled dynamically based on package C states,
4196                  * user space can't make reliable use of the CRCs, so let's just
4197                  * completely disable it.
4198                  */
4199                 hsw_disable_ips(crtc);
4200
4201                 spin_lock_irq(&pipe_crc->lock);
4202                 kfree(pipe_crc->entries);
4203                 pipe_crc->entries = entries;
4204                 pipe_crc->head = 0;
4205                 pipe_crc->tail = 0;
4206                 spin_unlock_irq(&pipe_crc->lock);
4207         }
4208
4209         pipe_crc->source = source;
4210
4211         I915_WRITE(PIPE_CRC_CTL(pipe), val);
4212         POSTING_READ(PIPE_CRC_CTL(pipe));
4213
4214         /* real source -> none transition */
4215         if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
4216                 struct intel_pipe_crc_entry *entries;
4217                 struct intel_crtc *crtc =
4218                         to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
4219
4220                 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4221                                  pipe_name(pipe));
4222
4223                 drm_modeset_lock(&crtc->base.mutex, NULL);
4224                 if (crtc->base.state->active)
4225                         intel_wait_for_vblank(dev, pipe);
4226                 drm_modeset_unlock(&crtc->base.mutex);
4227
4228                 spin_lock_irq(&pipe_crc->lock);
4229                 entries = pipe_crc->entries;
4230                 pipe_crc->entries = NULL;
4231                 pipe_crc->head = 0;
4232                 pipe_crc->tail = 0;
4233                 spin_unlock_irq(&pipe_crc->lock);
4234
4235                 kfree(entries);
4236
4237                 if (IS_G4X(dev_priv))
4238                         g4x_undo_pipe_scramble_reset(dev_priv, pipe);
4239                 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4240                         vlv_undo_pipe_scramble_reset(dev_priv, pipe);
4241                 else if (IS_HASWELL(dev_priv) && pipe == PIPE_A)
4242                         hsw_trans_edp_pipe_A_crc_wa(dev_priv, false);
4243
4244                 hsw_enable_ips(crtc);
4245         }
4246
4247         ret = 0;
4248
4249 out:
4250         intel_display_power_put(dev_priv, power_domain);
4251
4252         return ret;
4253 }
4254
4255 /*
4256  * Parse pipe CRC command strings:
4257  *   command: wsp* object wsp+ name wsp+ source wsp*
4258  *   object: 'pipe'
4259  *   name: (A | B | C)
4260  *   source: (none | plane1 | plane2 | pf)
4261  *   wsp: (#0x20 | #0x9 | #0xA)+
4262  *
4263  * eg.:
4264  *  "pipe A plane1"  ->  Start CRC computations on plane1 of pipe A
4265  *  "pipe A none"    ->  Stop CRC
4266  */
4267 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
4268 {
4269         int n_words = 0;
4270
4271         while (*buf) {
4272                 char *end;
4273
4274                 /* skip leading white space */
4275                 buf = skip_spaces(buf);
4276                 if (!*buf)
4277                         break;  /* end of buffer */
4278
4279                 /* find end of word */
4280                 for (end = buf; *end && !isspace(*end); end++)
4281                         ;
4282
4283                 if (n_words == max_words) {
4284                         DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4285                                          max_words);
4286                         return -EINVAL; /* ran out of words[] before bytes */
4287                 }
4288
4289                 if (*end)
4290                         *end++ = '\0';
4291                 words[n_words++] = buf;
4292                 buf = end;
4293         }
4294
4295         return n_words;
4296 }
4297
4298 enum intel_pipe_crc_object {
4299         PIPE_CRC_OBJECT_PIPE,
4300 };
4301
4302 static const char * const pipe_crc_objects[] = {
4303         "pipe",
4304 };
4305
4306 static int
4307 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
4308 {
4309         int i;
4310
4311         for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
4312                 if (!strcmp(buf, pipe_crc_objects[i])) {
4313                         *o = i;
4314                         return 0;
4315                     }
4316
4317         return -EINVAL;
4318 }
4319
4320 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
4321 {
4322         const char name = buf[0];
4323
4324         if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
4325                 return -EINVAL;
4326
4327         *pipe = name - 'A';
4328
4329         return 0;
4330 }
4331
4332 static int
4333 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
4334 {
4335         int i;
4336
4337         for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
4338                 if (!strcmp(buf, pipe_crc_sources[i])) {
4339                         *s = i;
4340                         return 0;
4341                     }
4342
4343         return -EINVAL;
4344 }
4345
4346 static int display_crc_ctl_parse(struct drm_i915_private *dev_priv,
4347                                  char *buf, size_t len)
4348 {
4349 #define N_WORDS 3
4350         int n_words;
4351         char *words[N_WORDS];
4352         enum pipe pipe;
4353         enum intel_pipe_crc_object object;
4354         enum intel_pipe_crc_source source;
4355
4356         n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
4357         if (n_words != N_WORDS) {
4358                 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4359                                  N_WORDS);
4360                 return -EINVAL;
4361         }
4362
4363         if (display_crc_ctl_parse_object(words[0], &object) < 0) {
4364                 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
4365                 return -EINVAL;
4366         }
4367
4368         if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
4369                 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
4370                 return -EINVAL;
4371         }
4372
4373         if (display_crc_ctl_parse_source(words[2], &source) < 0) {
4374                 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
4375                 return -EINVAL;
4376         }
4377
4378         return pipe_crc_set_source(dev_priv, pipe, source);
4379 }
4380
4381 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
4382                                      size_t len, loff_t *offp)
4383 {
4384         struct seq_file *m = file->private_data;
4385         struct drm_i915_private *dev_priv = m->private;
4386         char *tmpbuf;
4387         int ret;
4388
4389         if (len == 0)
4390                 return 0;
4391
4392         if (len > PAGE_SIZE - 1) {
4393                 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4394                                  PAGE_SIZE);
4395                 return -E2BIG;
4396         }
4397
4398         tmpbuf = kmalloc(len + 1, GFP_KERNEL);
4399         if (!tmpbuf)
4400                 return -ENOMEM;
4401
4402         if (copy_from_user(tmpbuf, ubuf, len)) {
4403                 ret = -EFAULT;
4404                 goto out;
4405         }
4406         tmpbuf[len] = '\0';
4407
4408         ret = display_crc_ctl_parse(dev_priv, tmpbuf, len);
4409
4410 out:
4411         kfree(tmpbuf);
4412         if (ret < 0)
4413                 return ret;
4414
4415         *offp += len;
4416         return len;
4417 }
4418
4419 static const struct file_operations i915_display_crc_ctl_fops = {
4420         .owner = THIS_MODULE,
4421         .open = display_crc_ctl_open,
4422         .read = seq_read,
4423         .llseek = seq_lseek,
4424         .release = single_release,
4425         .write = display_crc_ctl_write
4426 };
4427
4428 static ssize_t i915_displayport_test_active_write(struct file *file,
4429                                                   const char __user *ubuf,
4430                                                   size_t len, loff_t *offp)
4431 {
4432         char *input_buffer;
4433         int status = 0;
4434         struct drm_device *dev;
4435         struct drm_connector *connector;
4436         struct list_head *connector_list;
4437         struct intel_dp *intel_dp;
4438         int val = 0;
4439
4440         dev = ((struct seq_file *)file->private_data)->private;
4441
4442         connector_list = &dev->mode_config.connector_list;
4443
4444         if (len == 0)
4445                 return 0;
4446
4447         input_buffer = kmalloc(len + 1, GFP_KERNEL);
4448         if (!input_buffer)
4449                 return -ENOMEM;
4450
4451         if (copy_from_user(input_buffer, ubuf, len)) {
4452                 status = -EFAULT;
4453                 goto out;
4454         }
4455
4456         input_buffer[len] = '\0';
4457         DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4458
4459         list_for_each_entry(connector, connector_list, head) {
4460                 if (connector->connector_type !=
4461                     DRM_MODE_CONNECTOR_DisplayPort)
4462                         continue;
4463
4464                 if (connector->status == connector_status_connected &&
4465                     connector->encoder != NULL) {
4466                         intel_dp = enc_to_intel_dp(connector->encoder);
4467                         status = kstrtoint(input_buffer, 10, &val);
4468                         if (status < 0)
4469                                 goto out;
4470                         DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4471                         /* To prevent erroneous activation of the compliance
4472                          * testing code, only accept an actual value of 1 here
4473                          */
4474                         if (val == 1)
4475                                 intel_dp->compliance_test_active = 1;
4476                         else
4477                                 intel_dp->compliance_test_active = 0;
4478                 }
4479         }
4480 out:
4481         kfree(input_buffer);
4482         if (status < 0)
4483                 return status;
4484
4485         *offp += len;
4486         return len;
4487 }
4488
4489 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4490 {
4491         struct drm_device *dev = m->private;
4492         struct drm_connector *connector;
4493         struct list_head *connector_list = &dev->mode_config.connector_list;
4494         struct intel_dp *intel_dp;
4495
4496         list_for_each_entry(connector, connector_list, head) {
4497                 if (connector->connector_type !=
4498                     DRM_MODE_CONNECTOR_DisplayPort)
4499                         continue;
4500
4501                 if (connector->status == connector_status_connected &&
4502                     connector->encoder != NULL) {
4503                         intel_dp = enc_to_intel_dp(connector->encoder);
4504                         if (intel_dp->compliance_test_active)
4505                                 seq_puts(m, "1");
4506                         else
4507                                 seq_puts(m, "0");
4508                 } else
4509                         seq_puts(m, "0");
4510         }
4511
4512         return 0;
4513 }
4514
4515 static int i915_displayport_test_active_open(struct inode *inode,
4516                                              struct file *file)
4517 {
4518         struct drm_i915_private *dev_priv = inode->i_private;
4519
4520         return single_open(file, i915_displayport_test_active_show,
4521                            &dev_priv->drm);
4522 }
4523
4524 static const struct file_operations i915_displayport_test_active_fops = {
4525         .owner = THIS_MODULE,
4526         .open = i915_displayport_test_active_open,
4527         .read = seq_read,
4528         .llseek = seq_lseek,
4529         .release = single_release,
4530         .write = i915_displayport_test_active_write
4531 };
4532
4533 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4534 {
4535         struct drm_device *dev = m->private;
4536         struct drm_connector *connector;
4537         struct list_head *connector_list = &dev->mode_config.connector_list;
4538         struct intel_dp *intel_dp;
4539
4540         list_for_each_entry(connector, connector_list, head) {
4541                 if (connector->connector_type !=
4542                     DRM_MODE_CONNECTOR_DisplayPort)
4543                         continue;
4544
4545                 if (connector->status == connector_status_connected &&
4546                     connector->encoder != NULL) {
4547                         intel_dp = enc_to_intel_dp(connector->encoder);
4548                         seq_printf(m, "%lx", intel_dp->compliance_test_data);
4549                 } else
4550                         seq_puts(m, "0");
4551         }
4552
4553         return 0;
4554 }
4555 static int i915_displayport_test_data_open(struct inode *inode,
4556                                            struct file *file)
4557 {
4558         struct drm_i915_private *dev_priv = inode->i_private;
4559
4560         return single_open(file, i915_displayport_test_data_show,
4561                            &dev_priv->drm);
4562 }
4563
4564 static const struct file_operations i915_displayport_test_data_fops = {
4565         .owner = THIS_MODULE,
4566         .open = i915_displayport_test_data_open,
4567         .read = seq_read,
4568         .llseek = seq_lseek,
4569         .release = single_release
4570 };
4571
4572 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4573 {
4574         struct drm_device *dev = m->private;
4575         struct drm_connector *connector;
4576         struct list_head *connector_list = &dev->mode_config.connector_list;
4577         struct intel_dp *intel_dp;
4578
4579         list_for_each_entry(connector, connector_list, head) {
4580                 if (connector->connector_type !=
4581                     DRM_MODE_CONNECTOR_DisplayPort)
4582                         continue;
4583
4584                 if (connector->status == connector_status_connected &&
4585                     connector->encoder != NULL) {
4586                         intel_dp = enc_to_intel_dp(connector->encoder);
4587                         seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4588                 } else
4589                         seq_puts(m, "0");
4590         }
4591
4592         return 0;
4593 }
4594
4595 static int i915_displayport_test_type_open(struct inode *inode,
4596                                        struct file *file)
4597 {
4598         struct drm_i915_private *dev_priv = inode->i_private;
4599
4600         return single_open(file, i915_displayport_test_type_show,
4601                            &dev_priv->drm);
4602 }
4603
4604 static const struct file_operations i915_displayport_test_type_fops = {
4605         .owner = THIS_MODULE,
4606         .open = i915_displayport_test_type_open,
4607         .read = seq_read,
4608         .llseek = seq_lseek,
4609         .release = single_release
4610 };
4611
4612 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
4613 {
4614         struct drm_i915_private *dev_priv = m->private;
4615         struct drm_device *dev = &dev_priv->drm;
4616         int level;
4617         int num_levels;
4618
4619         if (IS_CHERRYVIEW(dev_priv))
4620                 num_levels = 3;
4621         else if (IS_VALLEYVIEW(dev_priv))
4622                 num_levels = 1;
4623         else
4624                 num_levels = ilk_wm_max_level(dev_priv) + 1;
4625
4626         drm_modeset_lock_all(dev);
4627
4628         for (level = 0; level < num_levels; level++) {
4629                 unsigned int latency = wm[level];
4630
4631                 /*
4632                  * - WM1+ latency values in 0.5us units
4633                  * - latencies are in us on gen9/vlv/chv
4634                  */
4635                 if (INTEL_GEN(dev_priv) >= 9 || IS_VALLEYVIEW(dev_priv) ||
4636                     IS_CHERRYVIEW(dev_priv))
4637                         latency *= 10;
4638                 else if (level > 0)
4639                         latency *= 5;
4640
4641                 seq_printf(m, "WM%d %u (%u.%u usec)\n",
4642                            level, wm[level], latency / 10, latency % 10);
4643         }
4644
4645         drm_modeset_unlock_all(dev);
4646 }
4647
4648 static int pri_wm_latency_show(struct seq_file *m, void *data)
4649 {
4650         struct drm_i915_private *dev_priv = m->private;
4651         const uint16_t *latencies;
4652
4653         if (INTEL_GEN(dev_priv) >= 9)
4654                 latencies = dev_priv->wm.skl_latency;
4655         else
4656                 latencies = dev_priv->wm.pri_latency;
4657
4658         wm_latency_show(m, latencies);
4659
4660         return 0;
4661 }
4662
4663 static int spr_wm_latency_show(struct seq_file *m, void *data)
4664 {
4665         struct drm_i915_private *dev_priv = m->private;
4666         const uint16_t *latencies;
4667
4668         if (INTEL_GEN(dev_priv) >= 9)
4669                 latencies = dev_priv->wm.skl_latency;
4670         else
4671                 latencies = dev_priv->wm.spr_latency;
4672
4673         wm_latency_show(m, latencies);
4674
4675         return 0;
4676 }
4677
4678 static int cur_wm_latency_show(struct seq_file *m, void *data)
4679 {
4680         struct drm_i915_private *dev_priv = m->private;
4681         const uint16_t *latencies;
4682
4683         if (INTEL_GEN(dev_priv) >= 9)
4684                 latencies = dev_priv->wm.skl_latency;
4685         else
4686                 latencies = dev_priv->wm.cur_latency;
4687
4688         wm_latency_show(m, latencies);
4689
4690         return 0;
4691 }
4692
4693 static int pri_wm_latency_open(struct inode *inode, struct file *file)
4694 {
4695         struct drm_i915_private *dev_priv = inode->i_private;
4696
4697         if (INTEL_GEN(dev_priv) < 5)
4698                 return -ENODEV;
4699
4700         return single_open(file, pri_wm_latency_show, dev_priv);
4701 }
4702
4703 static int spr_wm_latency_open(struct inode *inode, struct file *file)
4704 {
4705         struct drm_i915_private *dev_priv = inode->i_private;
4706
4707         if (HAS_GMCH_DISPLAY(dev_priv))
4708                 return -ENODEV;
4709
4710         return single_open(file, spr_wm_latency_show, dev_priv);
4711 }
4712
4713 static int cur_wm_latency_open(struct inode *inode, struct file *file)
4714 {
4715         struct drm_i915_private *dev_priv = inode->i_private;
4716
4717         if (HAS_GMCH_DISPLAY(dev_priv))
4718                 return -ENODEV;
4719
4720         return single_open(file, cur_wm_latency_show, dev_priv);
4721 }
4722
4723 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
4724                                 size_t len, loff_t *offp, uint16_t wm[8])
4725 {
4726         struct seq_file *m = file->private_data;
4727         struct drm_i915_private *dev_priv = m->private;
4728         struct drm_device *dev = &dev_priv->drm;
4729         uint16_t new[8] = { 0 };
4730         int num_levels;
4731         int level;
4732         int ret;
4733         char tmp[32];
4734
4735         if (IS_CHERRYVIEW(dev_priv))
4736                 num_levels = 3;
4737         else if (IS_VALLEYVIEW(dev_priv))
4738                 num_levels = 1;
4739         else
4740                 num_levels = ilk_wm_max_level(dev_priv) + 1;
4741
4742         if (len >= sizeof(tmp))
4743                 return -EINVAL;
4744
4745         if (copy_from_user(tmp, ubuf, len))
4746                 return -EFAULT;
4747
4748         tmp[len] = '\0';
4749
4750         ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4751                      &new[0], &new[1], &new[2], &new[3],
4752                      &new[4], &new[5], &new[6], &new[7]);
4753         if (ret != num_levels)
4754                 return -EINVAL;
4755
4756         drm_modeset_lock_all(dev);
4757
4758         for (level = 0; level < num_levels; level++)
4759                 wm[level] = new[level];
4760
4761         drm_modeset_unlock_all(dev);
4762
4763         return len;
4764 }
4765
4766
4767 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4768                                     size_t len, loff_t *offp)
4769 {
4770         struct seq_file *m = file->private_data;
4771         struct drm_i915_private *dev_priv = m->private;
4772         uint16_t *latencies;
4773
4774         if (INTEL_GEN(dev_priv) >= 9)
4775                 latencies = dev_priv->wm.skl_latency;
4776         else
4777                 latencies = dev_priv->wm.pri_latency;
4778
4779         return wm_latency_write(file, ubuf, len, offp, latencies);
4780 }
4781
4782 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4783                                     size_t len, loff_t *offp)
4784 {
4785         struct seq_file *m = file->private_data;
4786         struct drm_i915_private *dev_priv = m->private;
4787         uint16_t *latencies;
4788
4789         if (INTEL_GEN(dev_priv) >= 9)
4790                 latencies = dev_priv->wm.skl_latency;
4791         else
4792                 latencies = dev_priv->wm.spr_latency;
4793
4794         return wm_latency_write(file, ubuf, len, offp, latencies);
4795 }
4796
4797 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4798                                     size_t len, loff_t *offp)
4799 {
4800         struct seq_file *m = file->private_data;
4801         struct drm_i915_private *dev_priv = m->private;
4802         uint16_t *latencies;
4803
4804         if (INTEL_GEN(dev_priv) >= 9)
4805                 latencies = dev_priv->wm.skl_latency;
4806         else
4807                 latencies = dev_priv->wm.cur_latency;
4808
4809         return wm_latency_write(file, ubuf, len, offp, latencies);
4810 }
4811
4812 static const struct file_operations i915_pri_wm_latency_fops = {
4813         .owner = THIS_MODULE,
4814         .open = pri_wm_latency_open,
4815         .read = seq_read,
4816         .llseek = seq_lseek,
4817         .release = single_release,
4818         .write = pri_wm_latency_write
4819 };
4820
4821 static const struct file_operations i915_spr_wm_latency_fops = {
4822         .owner = THIS_MODULE,
4823         .open = spr_wm_latency_open,
4824         .read = seq_read,
4825         .llseek = seq_lseek,
4826         .release = single_release,
4827         .write = spr_wm_latency_write
4828 };
4829
4830 static const struct file_operations i915_cur_wm_latency_fops = {
4831         .owner = THIS_MODULE,
4832         .open = cur_wm_latency_open,
4833         .read = seq_read,
4834         .llseek = seq_lseek,
4835         .release = single_release,
4836         .write = cur_wm_latency_write
4837 };
4838
4839 static int
4840 i915_wedged_get(void *data, u64 *val)
4841 {
4842         struct drm_i915_private *dev_priv = data;
4843
4844         *val = i915_terminally_wedged(&dev_priv->gpu_error);
4845
4846         return 0;
4847 }
4848
4849 static int
4850 i915_wedged_set(void *data, u64 val)
4851 {
4852         struct drm_i915_private *dev_priv = data;
4853
4854         /*
4855          * There is no safeguard against this debugfs entry colliding
4856          * with the hangcheck calling same i915_handle_error() in
4857          * parallel, causing an explosion. For now we assume that the
4858          * test harness is responsible enough not to inject gpu hangs
4859          * while it is writing to 'i915_wedged'
4860          */
4861
4862         if (i915_reset_in_progress(&dev_priv->gpu_error))
4863                 return -EAGAIN;
4864
4865         i915_handle_error(dev_priv, val,
4866                           "Manually setting wedged to %llu", val);
4867
4868         return 0;
4869 }
4870
4871 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4872                         i915_wedged_get, i915_wedged_set,
4873                         "%llu\n");
4874
4875 static int
4876 i915_ring_missed_irq_get(void *data, u64 *val)
4877 {
4878         struct drm_i915_private *dev_priv = data;
4879
4880         *val = dev_priv->gpu_error.missed_irq_rings;
4881         return 0;
4882 }
4883
4884 static int
4885 i915_ring_missed_irq_set(void *data, u64 val)
4886 {
4887         struct drm_i915_private *dev_priv = data;
4888         struct drm_device *dev = &dev_priv->drm;
4889         int ret;
4890
4891         /* Lock against concurrent debugfs callers */
4892         ret = mutex_lock_interruptible(&dev->struct_mutex);
4893         if (ret)
4894                 return ret;
4895         dev_priv->gpu_error.missed_irq_rings = val;
4896         mutex_unlock(&dev->struct_mutex);
4897
4898         return 0;
4899 }
4900
4901 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4902                         i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4903                         "0x%08llx\n");
4904
4905 static int
4906 i915_ring_test_irq_get(void *data, u64 *val)
4907 {
4908         struct drm_i915_private *dev_priv = data;
4909
4910         *val = dev_priv->gpu_error.test_irq_rings;
4911
4912         return 0;
4913 }
4914
4915 static int
4916 i915_ring_test_irq_set(void *data, u64 val)
4917 {
4918         struct drm_i915_private *dev_priv = data;
4919
4920         val &= INTEL_INFO(dev_priv)->ring_mask;
4921         DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4922         dev_priv->gpu_error.test_irq_rings = val;
4923
4924         return 0;
4925 }
4926
4927 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4928                         i915_ring_test_irq_get, i915_ring_test_irq_set,
4929                         "0x%08llx\n");
4930
4931 #define DROP_UNBOUND 0x1
4932 #define DROP_BOUND 0x2
4933 #define DROP_RETIRE 0x4
4934 #define DROP_ACTIVE 0x8
4935 #define DROP_FREED 0x10
4936 #define DROP_ALL (DROP_UNBOUND  | \
4937                   DROP_BOUND    | \
4938                   DROP_RETIRE   | \
4939                   DROP_ACTIVE   | \
4940                   DROP_FREED)
4941 static int
4942 i915_drop_caches_get(void *data, u64 *val)
4943 {
4944         *val = DROP_ALL;
4945
4946         return 0;
4947 }
4948
4949 static int
4950 i915_drop_caches_set(void *data, u64 val)
4951 {
4952         struct drm_i915_private *dev_priv = data;
4953         struct drm_device *dev = &dev_priv->drm;
4954         int ret;
4955
4956         DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4957
4958         /* No need to check and wait for gpu resets, only libdrm auto-restarts
4959          * on ioctls on -EAGAIN. */
4960         ret = mutex_lock_interruptible(&dev->struct_mutex);
4961         if (ret)
4962                 return ret;
4963
4964         if (val & DROP_ACTIVE) {
4965                 ret = i915_gem_wait_for_idle(dev_priv,
4966                                              I915_WAIT_INTERRUPTIBLE |
4967                                              I915_WAIT_LOCKED);
4968                 if (ret)
4969                         goto unlock;
4970         }
4971
4972         if (val & (DROP_RETIRE | DROP_ACTIVE))
4973                 i915_gem_retire_requests(dev_priv);
4974
4975         if (val & DROP_BOUND)
4976                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4977
4978         if (val & DROP_UNBOUND)
4979                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4980
4981 unlock:
4982         mutex_unlock(&dev->struct_mutex);
4983
4984         if (val & DROP_FREED) {
4985                 synchronize_rcu();
4986                 flush_work(&dev_priv->mm.free_work);
4987         }
4988
4989         return ret;
4990 }
4991
4992 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4993                         i915_drop_caches_get, i915_drop_caches_set,
4994                         "0x%08llx\n");
4995
4996 static int
4997 i915_max_freq_get(void *data, u64 *val)
4998 {
4999         struct drm_i915_private *dev_priv = data;
5000
5001         if (INTEL_GEN(dev_priv) < 6)
5002                 return -ENODEV;
5003
5004         *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
5005         return 0;
5006 }
5007
5008 static int
5009 i915_max_freq_set(void *data, u64 val)
5010 {
5011         struct drm_i915_private *dev_priv = data;
5012         u32 hw_max, hw_min;
5013         int ret;
5014
5015         if (INTEL_GEN(dev_priv) < 6)
5016                 return -ENODEV;
5017
5018         DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
5019
5020         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
5021         if (ret)
5022                 return ret;
5023
5024         /*
5025          * Turbo will still be enabled, but won't go above the set value.
5026          */
5027         val = intel_freq_opcode(dev_priv, val);
5028
5029         hw_max = dev_priv->rps.max_freq;
5030         hw_min = dev_priv->rps.min_freq;
5031
5032         if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
5033                 mutex_unlock(&dev_priv->rps.hw_lock);
5034                 return -EINVAL;
5035         }
5036
5037         dev_priv->rps.max_freq_softlimit = val;
5038
5039         intel_set_rps(dev_priv, val);
5040
5041         mutex_unlock(&dev_priv->rps.hw_lock);
5042
5043         return 0;
5044 }
5045
5046 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
5047                         i915_max_freq_get, i915_max_freq_set,
5048                         "%llu\n");
5049
5050 static int
5051 i915_min_freq_get(void *data, u64 *val)
5052 {
5053         struct drm_i915_private *dev_priv = data;
5054
5055         if (INTEL_GEN(dev_priv) < 6)
5056                 return -ENODEV;
5057
5058         *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
5059         return 0;
5060 }
5061
5062 static int
5063 i915_min_freq_set(void *data, u64 val)
5064 {
5065         struct drm_i915_private *dev_priv = data;
5066         u32 hw_max, hw_min;
5067         int ret;
5068
5069         if (INTEL_GEN(dev_priv) < 6)
5070                 return -ENODEV;
5071
5072         DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
5073
5074         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
5075         if (ret)
5076                 return ret;
5077
5078         /*
5079          * Turbo will still be enabled, but won't go below the set value.
5080          */
5081         val = intel_freq_opcode(dev_priv, val);
5082
5083         hw_max = dev_priv->rps.max_freq;
5084         hw_min = dev_priv->rps.min_freq;
5085
5086         if (val < hw_min ||
5087             val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
5088                 mutex_unlock(&dev_priv->rps.hw_lock);
5089                 return -EINVAL;
5090         }
5091
5092         dev_priv->rps.min_freq_softlimit = val;
5093
5094         intel_set_rps(dev_priv, val);
5095
5096         mutex_unlock(&dev_priv->rps.hw_lock);
5097
5098         return 0;
5099 }
5100
5101 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
5102                         i915_min_freq_get, i915_min_freq_set,
5103                         "%llu\n");
5104
5105 static int
5106 i915_cache_sharing_get(void *data, u64 *val)
5107 {
5108         struct drm_i915_private *dev_priv = data;
5109         u32 snpcr;
5110
5111         if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
5112                 return -ENODEV;
5113
5114         intel_runtime_pm_get(dev_priv);
5115
5116         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5117
5118         intel_runtime_pm_put(dev_priv);
5119
5120         *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
5121
5122         return 0;
5123 }
5124
5125 static int
5126 i915_cache_sharing_set(void *data, u64 val)
5127 {
5128         struct drm_i915_private *dev_priv = data;
5129         u32 snpcr;
5130
5131         if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
5132                 return -ENODEV;
5133
5134         if (val > 3)
5135                 return -EINVAL;
5136
5137         intel_runtime_pm_get(dev_priv);
5138         DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
5139
5140         /* Update the cache sharing policy here as well */
5141         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5142         snpcr &= ~GEN6_MBC_SNPCR_MASK;
5143         snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
5144         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5145
5146         intel_runtime_pm_put(dev_priv);
5147         return 0;
5148 }
5149
5150 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
5151                         i915_cache_sharing_get, i915_cache_sharing_set,
5152                         "%llu\n");
5153
5154 static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
5155                                           struct sseu_dev_info *sseu)
5156 {
5157         int ss_max = 2;
5158         int ss;
5159         u32 sig1[ss_max], sig2[ss_max];
5160
5161         sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
5162         sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
5163         sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
5164         sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
5165
5166         for (ss = 0; ss < ss_max; ss++) {
5167                 unsigned int eu_cnt;
5168
5169                 if (sig1[ss] & CHV_SS_PG_ENABLE)
5170                         /* skip disabled subslice */
5171                         continue;
5172
5173                 sseu->slice_mask = BIT(0);
5174                 sseu->subslice_mask |= BIT(ss);
5175                 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
5176                          ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
5177                          ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
5178                          ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
5179                 sseu->eu_total += eu_cnt;
5180                 sseu->eu_per_subslice = max_t(unsigned int,
5181                                               sseu->eu_per_subslice, eu_cnt);
5182         }
5183 }
5184
5185 static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
5186                                     struct sseu_dev_info *sseu)
5187 {
5188         int s_max = 3, ss_max = 4;
5189         int s, ss;
5190         u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
5191
5192         /* BXT has a single slice and at most 3 subslices. */
5193         if (IS_BROXTON(dev_priv)) {
5194                 s_max = 1;
5195                 ss_max = 3;
5196         }
5197
5198         for (s = 0; s < s_max; s++) {
5199                 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
5200                 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
5201                 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
5202         }
5203
5204         eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
5205                      GEN9_PGCTL_SSA_EU19_ACK |
5206                      GEN9_PGCTL_SSA_EU210_ACK |
5207                      GEN9_PGCTL_SSA_EU311_ACK;
5208         eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
5209                      GEN9_PGCTL_SSB_EU19_ACK |
5210                      GEN9_PGCTL_SSB_EU210_ACK |
5211                      GEN9_PGCTL_SSB_EU311_ACK;
5212
5213         for (s = 0; s < s_max; s++) {
5214                 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
5215                         /* skip disabled slice */
5216                         continue;
5217
5218                 sseu->slice_mask |= BIT(s);
5219
5220                 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
5221                         sseu->subslice_mask =
5222                                 INTEL_INFO(dev_priv)->sseu.subslice_mask;
5223
5224                 for (ss = 0; ss < ss_max; ss++) {
5225                         unsigned int eu_cnt;
5226
5227                         if (IS_BROXTON(dev_priv)) {
5228                                 if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
5229                                         /* skip disabled subslice */
5230                                         continue;
5231
5232                                 sseu->subslice_mask |= BIT(ss);
5233                         }
5234
5235                         eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
5236                                                eu_mask[ss%2]);
5237                         sseu->eu_total += eu_cnt;
5238                         sseu->eu_per_subslice = max_t(unsigned int,
5239                                                       sseu->eu_per_subslice,
5240                                                       eu_cnt);
5241                 }
5242         }
5243 }
5244
5245 static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
5246                                          struct sseu_dev_info *sseu)
5247 {
5248         u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
5249         int s;
5250
5251         sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK;
5252
5253         if (sseu->slice_mask) {
5254                 sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask;
5255                 sseu->eu_per_subslice =
5256                                 INTEL_INFO(dev_priv)->sseu.eu_per_subslice;
5257                 sseu->eu_total = sseu->eu_per_subslice *
5258                                  sseu_subslice_total(sseu);
5259
5260                 /* subtract fused off EU(s) from enabled slice(s) */
5261                 for (s = 0; s < fls(sseu->slice_mask); s++) {
5262                         u8 subslice_7eu =
5263                                 INTEL_INFO(dev_priv)->sseu.subslice_7eu[s];
5264
5265                         sseu->eu_total -= hweight8(subslice_7eu);
5266                 }
5267         }
5268 }
5269
5270 static void i915_print_sseu_info(struct seq_file *m, bool is_available_info,
5271                                  const struct sseu_dev_info *sseu)
5272 {
5273         struct drm_i915_private *dev_priv = node_to_i915(m->private);
5274         const char *type = is_available_info ? "Available" : "Enabled";
5275
5276         seq_printf(m, "  %s Slice Mask: %04x\n", type,
5277                    sseu->slice_mask);
5278         seq_printf(m, "  %s Slice Total: %u\n", type,
5279                    hweight8(sseu->slice_mask));
5280         seq_printf(m, "  %s Subslice Total: %u\n", type,
5281                    sseu_subslice_total(sseu));
5282         seq_printf(m, "  %s Subslice Mask: %04x\n", type,
5283                    sseu->subslice_mask);
5284         seq_printf(m, "  %s Subslice Per Slice: %u\n", type,
5285                    hweight8(sseu->subslice_mask));
5286         seq_printf(m, "  %s EU Total: %u\n", type,
5287                    sseu->eu_total);
5288         seq_printf(m, "  %s EU Per Subslice: %u\n", type,
5289                    sseu->eu_per_subslice);
5290
5291         if (!is_available_info)
5292                 return;
5293
5294         seq_printf(m, "  Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv)));
5295         if (HAS_POOLED_EU(dev_priv))
5296                 seq_printf(m, "  Min EU in pool: %u\n", sseu->min_eu_in_pool);
5297
5298         seq_printf(m, "  Has Slice Power Gating: %s\n",
5299                    yesno(sseu->has_slice_pg));
5300         seq_printf(m, "  Has Subslice Power Gating: %s\n",
5301                    yesno(sseu->has_subslice_pg));
5302         seq_printf(m, "  Has EU Power Gating: %s\n",
5303                    yesno(sseu->has_eu_pg));
5304 }
5305
5306 static int i915_sseu_status(struct seq_file *m, void *unused)
5307 {
5308         struct drm_i915_private *dev_priv = node_to_i915(m->private);
5309         struct sseu_dev_info sseu;
5310
5311         if (INTEL_GEN(dev_priv) < 8)
5312                 return -ENODEV;
5313
5314         seq_puts(m, "SSEU Device Info\n");
5315         i915_print_sseu_info(m, true, &INTEL_INFO(dev_priv)->sseu);
5316
5317         seq_puts(m, "SSEU Device Status\n");
5318         memset(&sseu, 0, sizeof(sseu));
5319
5320         intel_runtime_pm_get(dev_priv);
5321
5322         if (IS_CHERRYVIEW(dev_priv)) {
5323                 cherryview_sseu_device_status(dev_priv, &sseu);
5324         } else if (IS_BROADWELL(dev_priv)) {
5325                 broadwell_sseu_device_status(dev_priv, &sseu);
5326         } else if (INTEL_GEN(dev_priv) >= 9) {
5327                 gen9_sseu_device_status(dev_priv, &sseu);
5328         }
5329
5330         intel_runtime_pm_put(dev_priv);
5331
5332         i915_print_sseu_info(m, false, &sseu);
5333
5334         return 0;
5335 }
5336
5337 static int i915_forcewake_open(struct inode *inode, struct file *file)
5338 {
5339         struct drm_i915_private *dev_priv = inode->i_private;
5340
5341         if (INTEL_GEN(dev_priv) < 6)
5342                 return 0;
5343
5344         intel_runtime_pm_get(dev_priv);
5345         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5346
5347         return 0;
5348 }
5349
5350 static int i915_forcewake_release(struct inode *inode, struct file *file)
5351 {
5352         struct drm_i915_private *dev_priv = inode->i_private;
5353
5354         if (INTEL_GEN(dev_priv) < 6)
5355                 return 0;
5356
5357         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5358         intel_runtime_pm_put(dev_priv);
5359
5360         return 0;
5361 }
5362
5363 static const struct file_operations i915_forcewake_fops = {
5364         .owner = THIS_MODULE,
5365         .open = i915_forcewake_open,
5366         .release = i915_forcewake_release,
5367 };
5368
5369 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5370 {
5371         struct dentry *ent;
5372
5373         ent = debugfs_create_file("i915_forcewake_user",
5374                                   S_IRUSR,
5375                                   root, to_i915(minor->dev),
5376                                   &i915_forcewake_fops);
5377         if (!ent)
5378                 return -ENOMEM;
5379
5380         return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
5381 }
5382
5383 static int i915_debugfs_create(struct dentry *root,
5384                                struct drm_minor *minor,
5385                                const char *name,
5386                                const struct file_operations *fops)
5387 {
5388         struct dentry *ent;
5389
5390         ent = debugfs_create_file(name,
5391                                   S_IRUGO | S_IWUSR,
5392                                   root, to_i915(minor->dev),
5393                                   fops);
5394         if (!ent)
5395                 return -ENOMEM;
5396
5397         return drm_add_fake_info_node(minor, ent, fops);
5398 }
5399
5400 static const struct drm_info_list i915_debugfs_list[] = {
5401         {"i915_capabilities", i915_capabilities, 0},
5402         {"i915_gem_objects", i915_gem_object_info, 0},
5403         {"i915_gem_gtt", i915_gem_gtt_info, 0},
5404         {"i915_gem_pin_display", i915_gem_gtt_info, 0, (void *)1},
5405         {"i915_gem_stolen", i915_gem_stolen_list_info },
5406         {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
5407         {"i915_gem_request", i915_gem_request_info, 0},
5408         {"i915_gem_seqno", i915_gem_seqno_info, 0},
5409         {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
5410         {"i915_gem_interrupt", i915_interrupt_info, 0},
5411         {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5412         {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5413         {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
5414         {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
5415         {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
5416         {"i915_guc_info", i915_guc_info, 0},
5417         {"i915_guc_load_status", i915_guc_load_status_info, 0},
5418         {"i915_guc_log_dump", i915_guc_log_dump, 0},
5419         {"i915_frequency_info", i915_frequency_info, 0},
5420         {"i915_hangcheck_info", i915_hangcheck_info, 0},
5421         {"i915_drpc_info", i915_drpc_info, 0},
5422         {"i915_emon_status", i915_emon_status, 0},
5423         {"i915_ring_freq_table", i915_ring_freq_table, 0},
5424         {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
5425         {"i915_fbc_status", i915_fbc_status, 0},
5426         {"i915_ips_status", i915_ips_status, 0},
5427         {"i915_sr_status", i915_sr_status, 0},
5428         {"i915_opregion", i915_opregion, 0},
5429         {"i915_vbt", i915_vbt, 0},
5430         {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
5431         {"i915_context_status", i915_context_status, 0},
5432         {"i915_dump_lrc", i915_dump_lrc, 0},
5433         {"i915_forcewake_domains", i915_forcewake_domains, 0},
5434         {"i915_swizzle_info", i915_swizzle_info, 0},
5435         {"i915_ppgtt_info", i915_ppgtt_info, 0},
5436         {"i915_llc", i915_llc, 0},
5437         {"i915_edp_psr_status", i915_edp_psr_status, 0},
5438         {"i915_sink_crc_eDP1", i915_sink_crc, 0},
5439         {"i915_energy_uJ", i915_energy_uJ, 0},
5440         {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
5441         {"i915_power_domain_info", i915_power_domain_info, 0},
5442         {"i915_dmc_info", i915_dmc_info, 0},
5443         {"i915_display_info", i915_display_info, 0},
5444         {"i915_engine_info", i915_engine_info, 0},
5445         {"i915_semaphore_status", i915_semaphore_status, 0},
5446         {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
5447         {"i915_dp_mst_info", i915_dp_mst_info, 0},
5448         {"i915_wa_registers", i915_wa_registers, 0},
5449         {"i915_ddb_info", i915_ddb_info, 0},
5450         {"i915_sseu_status", i915_sseu_status, 0},
5451         {"i915_drrs_status", i915_drrs_status, 0},
5452         {"i915_rps_boost_info", i915_rps_boost_info, 0},
5453 };
5454 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5455
5456 static const struct i915_debugfs_files {
5457         const char *name;
5458         const struct file_operations *fops;
5459 } i915_debugfs_files[] = {
5460         {"i915_wedged", &i915_wedged_fops},
5461         {"i915_max_freq", &i915_max_freq_fops},
5462         {"i915_min_freq", &i915_min_freq_fops},
5463         {"i915_cache_sharing", &i915_cache_sharing_fops},
5464         {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5465         {"i915_ring_test_irq", &i915_ring_test_irq_fops},
5466         {"i915_gem_drop_caches", &i915_drop_caches_fops},
5467 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
5468         {"i915_error_state", &i915_error_state_fops},
5469 #endif
5470         {"i915_next_seqno", &i915_next_seqno_fops},
5471         {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
5472         {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5473         {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5474         {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
5475         {"i915_fbc_false_color", &i915_fbc_fc_fops},
5476         {"i915_dp_test_data", &i915_displayport_test_data_fops},
5477         {"i915_dp_test_type", &i915_displayport_test_type_fops},
5478         {"i915_dp_test_active", &i915_displayport_test_active_fops},
5479         {"i915_guc_log_control", &i915_guc_log_control_fops}
5480 };
5481
5482 void intel_display_crc_init(struct drm_i915_private *dev_priv)
5483 {
5484         enum pipe pipe;
5485
5486         for_each_pipe(dev_priv, pipe) {
5487                 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
5488
5489                 pipe_crc->opened = false;
5490                 spin_lock_init(&pipe_crc->lock);
5491                 init_waitqueue_head(&pipe_crc->wq);
5492         }
5493 }
5494
5495 int i915_debugfs_register(struct drm_i915_private *dev_priv)
5496 {
5497         struct drm_minor *minor = dev_priv->drm.primary;
5498         int ret, i;
5499
5500         ret = i915_forcewake_create(minor->debugfs_root, minor);
5501         if (ret)
5502                 return ret;
5503
5504         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5505                 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5506                 if (ret)
5507                         return ret;
5508         }
5509
5510         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5511                 ret = i915_debugfs_create(minor->debugfs_root, minor,
5512                                           i915_debugfs_files[i].name,
5513                                           i915_debugfs_files[i].fops);
5514                 if (ret)
5515                         return ret;
5516         }
5517
5518         return drm_debugfs_create_files(i915_debugfs_list,
5519                                         I915_DEBUGFS_ENTRIES,
5520                                         minor->debugfs_root, minor);
5521 }
5522
5523 void i915_debugfs_unregister(struct drm_i915_private *dev_priv)
5524 {
5525         struct drm_minor *minor = dev_priv->drm.primary;
5526         int i;
5527
5528         drm_debugfs_remove_files(i915_debugfs_list,
5529                                  I915_DEBUGFS_ENTRIES, minor);
5530
5531         drm_debugfs_remove_files((struct drm_info_list *)&i915_forcewake_fops,
5532                                  1, minor);
5533
5534         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5535                 struct drm_info_list *info_list =
5536                         (struct drm_info_list *)&i915_pipe_crc_data[i];
5537
5538                 drm_debugfs_remove_files(info_list, 1, minor);
5539         }
5540
5541         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5542                 struct drm_info_list *info_list =
5543                         (struct drm_info_list *)i915_debugfs_files[i].fops;
5544
5545                 drm_debugfs_remove_files(info_list, 1, minor);
5546         }
5547 }
5548
5549 struct dpcd_block {
5550         /* DPCD dump start address. */
5551         unsigned int offset;
5552         /* DPCD dump end address, inclusive. If unset, .size will be used. */
5553         unsigned int end;
5554         /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5555         size_t size;
5556         /* Only valid for eDP. */
5557         bool edp;
5558 };
5559
5560 static const struct dpcd_block i915_dpcd_debug[] = {
5561         { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5562         { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5563         { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5564         { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5565         { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5566         { .offset = DP_SET_POWER },
5567         { .offset = DP_EDP_DPCD_REV },
5568         { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5569         { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5570         { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5571 };
5572
5573 static int i915_dpcd_show(struct seq_file *m, void *data)
5574 {
5575         struct drm_connector *connector = m->private;
5576         struct intel_dp *intel_dp =
5577                 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5578         uint8_t buf[16];
5579         ssize_t err;
5580         int i;
5581
5582         if (connector->status != connector_status_connected)
5583                 return -ENODEV;
5584
5585         for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5586                 const struct dpcd_block *b = &i915_dpcd_debug[i];
5587                 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5588
5589                 if (b->edp &&
5590                     connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5591                         continue;
5592
5593                 /* low tech for now */
5594                 if (WARN_ON(size > sizeof(buf)))
5595                         continue;
5596
5597                 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5598                 if (err <= 0) {
5599                         DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5600                                   size, b->offset, err);
5601                         continue;
5602                 }
5603
5604                 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
5605         }
5606
5607         return 0;
5608 }
5609
5610 static int i915_dpcd_open(struct inode *inode, struct file *file)
5611 {
5612         return single_open(file, i915_dpcd_show, inode->i_private);
5613 }
5614
5615 static const struct file_operations i915_dpcd_fops = {
5616         .owner = THIS_MODULE,
5617         .open = i915_dpcd_open,
5618         .read = seq_read,
5619         .llseek = seq_lseek,
5620         .release = single_release,
5621 };
5622
5623 static int i915_panel_show(struct seq_file *m, void *data)
5624 {
5625         struct drm_connector *connector = m->private;
5626         struct intel_dp *intel_dp =
5627                 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5628
5629         if (connector->status != connector_status_connected)
5630                 return -ENODEV;
5631
5632         seq_printf(m, "Panel power up delay: %d\n",
5633                    intel_dp->panel_power_up_delay);
5634         seq_printf(m, "Panel power down delay: %d\n",
5635                    intel_dp->panel_power_down_delay);
5636         seq_printf(m, "Backlight on delay: %d\n",
5637                    intel_dp->backlight_on_delay);
5638         seq_printf(m, "Backlight off delay: %d\n",
5639                    intel_dp->backlight_off_delay);
5640
5641         return 0;
5642 }
5643
5644 static int i915_panel_open(struct inode *inode, struct file *file)
5645 {
5646         return single_open(file, i915_panel_show, inode->i_private);
5647 }
5648
5649 static const struct file_operations i915_panel_fops = {
5650         .owner = THIS_MODULE,
5651         .open = i915_panel_open,
5652         .read = seq_read,
5653         .llseek = seq_lseek,
5654         .release = single_release,
5655 };
5656
5657 /**
5658  * i915_debugfs_connector_add - add i915 specific connector debugfs files
5659  * @connector: pointer to a registered drm_connector
5660  *
5661  * Cleanup will be done by drm_connector_unregister() through a call to
5662  * drm_debugfs_connector_remove().
5663  *
5664  * Returns 0 on success, negative error codes on error.
5665  */
5666 int i915_debugfs_connector_add(struct drm_connector *connector)
5667 {
5668         struct dentry *root = connector->debugfs_entry;
5669
5670         /* The connector must have been registered beforehands. */
5671         if (!root)
5672                 return -ENODEV;
5673
5674         if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5675             connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5676                 debugfs_create_file("i915_dpcd", S_IRUGO, root,
5677                                     connector, &i915_dpcd_fops);
5678
5679         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5680                 debugfs_create_file("i915_panel_timings", S_IRUGO, root,
5681                                     connector, &i915_panel_fops);
5682
5683         return 0;
5684 }