drivers/gpu/drm/i915/i915_debugfs.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *
  27  */
  28
  29 #include <linux/seq_file.h>
  30 #include <linux/circ_buf.h>
  31 #include <linux/ctype.h>
  32 #include <linux/debugfs.h>
  33 #include <linux/slab.h>
  34 #include <linux/export.h>
  35 #include <linux/list_sort.h>
  36 #include <asm/msr-index.h>
  37 #include <drm/drmP.h>
  38 #include "intel_drv.h"
  39 #include "intel_ringbuffer.h"
  40 #include <drm/i915_drm.h>
  41 #include "i915_drv.h"
  42
  43 enum {
  44         ACTIVE_LIST,
  45         INACTIVE_LIST,
  46         PINNED_LIST,
  47 };
  48
  49 static const char *yesno(int v)
  50 {
  51         return v ? "yes" : "no";
  52 }
  53
  54 /* As the drm_debugfs_init() routines are called before dev->dev_private is
  55  * allocated we need to hook into the minor for release. */
  56 static int
  57 drm_add_fake_info_node(struct drm_minor *minor,
  58                        struct dentry *ent,
  59                        const void *key)
  60 {
  61         struct drm_info_node *node;
  62
  63         node = kmalloc(sizeof(*node), GFP_KERNEL);
  64         if (node == NULL) {
  65                 debugfs_remove(ent);
  66                 return -ENOMEM;
  67         }
  68
  69         node->minor = minor;
  70         node->dent = ent;
  71         node->info_ent = (void *) key;
  72
  73         mutex_lock(&minor->debugfs_lock);
  74         list_add(&node->list, &minor->debugfs_list);
  75         mutex_unlock(&minor->debugfs_lock);
  76
  77         return 0;
  78 }
  79
  80 static int i915_capabilities(struct seq_file *m, void *data)
  81 {
  82         struct drm_info_node *node = m->private;
  83         struct drm_device *dev = node->minor->dev;
  84         const struct intel_device_info *info = INTEL_INFO(dev);
  85
  86         seq_printf(m, "gen: %d\n", info->gen);
  87         seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
  88 #define PRINT_FLAG(x)  seq_printf(m, #x ": %s\n", yesno(info->x))
  89 #define SEP_SEMICOLON ;
  90         DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
  91 #undef PRINT_FLAG
  92 #undef SEP_SEMICOLON
  93
  94         return 0;
  95 }
  96
  97 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
  98 {
  99         if (obj->pin_display)
 100                 return "p";
 101         else
 102                 return " ";
 103 }
 104
 105 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
 106 {
 107         switch (obj->tiling_mode) {
 108         default:
 109         case I915_TILING_NONE: return " ";
 110         case I915_TILING_X: return "X";
 111         case I915_TILING_Y: return "Y";
 112         }
 113 }
 114
 115 static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
 116 {
 117         return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
 118 }
 119
 120 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
 121 {
 122         u64 size = 0;
 123         struct i915_vma *vma;
 124
 125         list_for_each_entry(vma, &obj->vma_list, vma_link) {
 126                 if (i915_is_ggtt(vma->vm) &&
 127                     drm_mm_node_allocated(&vma->node))
 128                         size += vma->node.size;
 129         }
 130
 131         return size;
 132 }
 133
 134 static void
 135 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
 136 {
 137         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
 138         struct intel_engine_cs *ring;
 139         struct i915_vma *vma;
 140         int pin_count = 0;
 141         int i;
 142
 143         seq_printf(m, "%pK: %s%s%s%s %8zdKiB %02x %02x [ ",
 144                    &obj->base,
 145                    obj->active ? "*" : " ",
 146                    get_pin_flag(obj),
 147                    get_tiling_flag(obj),
 148                    get_global_flag(obj),
 149                    obj->base.size / 1024,
 150                    obj->base.read_domains,
 151                    obj->base.write_domain);
 152         for_each_ring(ring, dev_priv, i)
 153                 seq_printf(m, "%x ",
 154                                 i915_gem_request_get_seqno(obj->last_read_req[i]));
 155         seq_printf(m, "] %x %x%s%s%s",
 156                    i915_gem_request_get_seqno(obj->last_write_req),
 157                    i915_gem_request_get_seqno(obj->last_fenced_req),
 158                    i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
 159                    obj->dirty ? " dirty" : "",
 160                    obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
 161         if (obj->base.name)
 162                 seq_printf(m, " (name: %d)", obj->base.name);
 163         list_for_each_entry(vma, &obj->vma_list, vma_link) {
 164                 if (vma->pin_count > 0)
 165                         pin_count++;
 166         }
 167         seq_printf(m, " (pinned x %d)", pin_count);
 168         if (obj->pin_display)
 169                 seq_printf(m, " (display)");
 170         if (obj->fence_reg != I915_FENCE_REG_NONE)
 171                 seq_printf(m, " (fence: %d)", obj->fence_reg);
 172         list_for_each_entry(vma, &obj->vma_list, vma_link) {
 173                 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
 174                            i915_is_ggtt(vma->vm) ? "g" : "pp",
 175                            vma->node.start, vma->node.size);
 176                 if (i915_is_ggtt(vma->vm))
 177                         seq_printf(m, ", type: %u)", vma->ggtt_view.type);
 178                 else
 179                         seq_puts(m, ")");
 180         }
 181         if (obj->stolen)
 182                 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
 183         if (obj->pin_display || obj->fault_mappable) {
 184                 char s[3], *t = s;
 185                 if (obj->pin_display)
 186                         *t++ = 'p';
 187                 if (obj->fault_mappable)
 188                         *t++ = 'f';
 189                 *t = '\0';
 190                 seq_printf(m, " (%s mappable)", s);
 191         }
 192         if (obj->last_write_req != NULL)
 193                 seq_printf(m, " (%s)",
 194                            i915_gem_request_get_ring(obj->last_write_req)->name);
 195         if (obj->frontbuffer_bits)
 196                 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
 197 }
 198
 199 static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
 200 {
 201         seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
 202         seq_putc(m, ctx->remap_slice ? 'R' : 'r');
 203         seq_putc(m, ' ');
 204 }
 205
 206 static int i915_gem_object_list_info(struct seq_file *m, void *data)
 207 {
 208         struct drm_info_node *node = m->private;
 209         uintptr_t list = (uintptr_t) node->info_ent->data;
 210         struct list_head *head;
 211         struct drm_device *dev = node->minor->dev;
 212         struct drm_i915_private *dev_priv = dev->dev_private;
 213         struct i915_address_space *vm = &dev_priv->gtt.base;
 214         struct i915_vma *vma;
 215         u64 total_obj_size, total_gtt_size;
 216         int count, ret;
 217
 218         ret = mutex_lock_interruptible(&dev->struct_mutex);
 219         if (ret)
 220                 return ret;
 221
 222         /* FIXME: the user of this interface might want more than just GGTT */
 223         switch (list) {
 224         case ACTIVE_LIST:
 225                 seq_puts(m, "Active:\n");
 226                 head = &vm->active_list;
 227                 break;
 228         case INACTIVE_LIST:
 229                 seq_puts(m, "Inactive:\n");
 230                 head = &vm->inactive_list;
 231                 break;
 232         default:
 233                 mutex_unlock(&dev->struct_mutex);
 234                 return -EINVAL;
 235         }
 236
 237         total_obj_size = total_gtt_size = count = 0;
 238         list_for_each_entry(vma, head, mm_list) {
 239                 seq_printf(m, "   ");
 240                 describe_obj(m, vma->obj);
 241                 seq_printf(m, "\n");
 242                 total_obj_size += vma->obj->base.size;
 243                 total_gtt_size += vma->node.size;
 244                 count++;
 245         }
 246         mutex_unlock(&dev->struct_mutex);
 247
 248         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 249                    count, total_obj_size, total_gtt_size);
 250         return 0;
 251 }
 252
 253 static int obj_rank_by_stolen(void *priv,
 254                               struct list_head *A, struct list_head *B)
 255 {
 256         struct drm_i915_gem_object *a =
 257                 container_of(A, struct drm_i915_gem_object, obj_exec_link);
 258         struct drm_i915_gem_object *b =
 259                 container_of(B, struct drm_i915_gem_object, obj_exec_link);
 260
 261         return a->stolen->start - b->stolen->start;
 262 }
 263
 264 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
 265 {
 266         struct drm_info_node *node = m->private;
 267         struct drm_device *dev = node->minor->dev;
 268         struct drm_i915_private *dev_priv = dev->dev_private;
 269         struct drm_i915_gem_object *obj;
 270         u64 total_obj_size, total_gtt_size;
 271         LIST_HEAD(stolen);
 272         int count, ret;
 273
 274         ret = mutex_lock_interruptible(&dev->struct_mutex);
 275         if (ret)
 276                 return ret;
 277
 278         total_obj_size = total_gtt_size = count = 0;
 279         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 280                 if (obj->stolen == NULL)
 281                         continue;
 282
 283                 list_add(&obj->obj_exec_link, &stolen);
 284
 285                 total_obj_size += obj->base.size;
 286                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 287                 count++;
 288         }
 289         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 290                 if (obj->stolen == NULL)
 291                         continue;
 292
 293                 list_add(&obj->obj_exec_link, &stolen);
 294
 295                 total_obj_size += obj->base.size;
 296                 count++;
 297         }
 298         list_sort(NULL, &stolen, obj_rank_by_stolen);
 299         seq_puts(m, "Stolen:\n");
 300         while (!list_empty(&stolen)) {
 301                 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
 302                 seq_puts(m, "   ");
 303                 describe_obj(m, obj);
 304                 seq_putc(m, '\n');
 305                 list_del_init(&obj->obj_exec_link);
 306         }
 307         mutex_unlock(&dev->struct_mutex);
 308
 309         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 310                    count, total_obj_size, total_gtt_size);
 311         return 0;
 312 }
 313
 314 #define count_objects(list, member) do { \
 315         list_for_each_entry(obj, list, member) { \
 316                 size += i915_gem_obj_total_ggtt_size(obj); \
 317                 ++count; \
 318                 if (obj->map_and_fenceable) { \
 319                         mappable_size += i915_gem_obj_ggtt_size(obj); \
 320                         ++mappable_count; \
 321                 } \
 322         } \
 323 } while (0)
 324
 325 struct file_stats {
 326         struct drm_i915_file_private *file_priv;
 327         unsigned long count;
 328         u64 total, unbound;
 329         u64 global, shared;
 330         u64 active, inactive;
 331 };
 332
 333 static int per_file_stats(int id, void *ptr, void *data)
 334 {
 335         struct drm_i915_gem_object *obj = ptr;
 336         struct file_stats *stats = data;
 337         struct i915_vma *vma;
 338
 339         stats->count++;
 340         stats->total += obj->base.size;
 341
 342         if (obj->base.name || obj->base.dma_buf)
 343                 stats->shared += obj->base.size;
 344
 345         if (USES_FULL_PPGTT(obj->base.dev)) {
 346                 list_for_each_entry(vma, &obj->vma_list, vma_link) {
 347                         struct i915_hw_ppgtt *ppgtt;
 348
 349                         if (!drm_mm_node_allocated(&vma->node))
 350                                 continue;
 351
 352                         if (i915_is_ggtt(vma->vm)) {
 353                                 stats->global += obj->base.size;
 354                                 continue;
 355                         }
 356
 357                         ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
 358                         if (ppgtt->file_priv != stats->file_priv)
 359                                 continue;
 360
 361                         if (obj->active) /* XXX per-vma statistic */
 362                                 stats->active += obj->base.size;
 363                         else
 364                                 stats->inactive += obj->base.size;
 365
 366                         return 0;
 367                 }
 368         } else {
 369                 if (i915_gem_obj_ggtt_bound(obj)) {
 370                         stats->global += obj->base.size;
 371                         if (obj->active)
 372                                 stats->active += obj->base.size;
 373                         else
 374                                 stats->inactive += obj->base.size;
 375                         return 0;
 376                 }
 377         }
 378
 379         if (!list_empty(&obj->global_list))
 380                 stats->unbound += obj->base.size;
 381
 382         return 0;
 383 }
 384
 385 #define print_file_stats(m, name, stats) do { \
 386         if (stats.count) \
 387                 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
 388                            name, \
 389                            stats.count, \
 390                            stats.total, \
 391                            stats.active, \
 392                            stats.inactive, \
 393                            stats.global, \
 394                            stats.shared, \
 395                            stats.unbound); \
 396 } while (0)
 397
 398 static void print_batch_pool_stats(struct seq_file *m,
 399                                    struct drm_i915_private *dev_priv)
 400 {
 401         struct drm_i915_gem_object *obj;
 402         struct file_stats stats;
 403         struct intel_engine_cs *ring;
 404         int i, j;
 405
 406         memset(&stats, 0, sizeof(stats));
 407
 408         for_each_ring(ring, dev_priv, i) {
 409                 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
 410                         list_for_each_entry(obj,
 411                                             &ring->batch_pool.cache_list[j],
 412                                             batch_pool_link)
 413                                 per_file_stats(0, obj, &stats);
 414                 }
 415         }
 416
 417         print_file_stats(m, "[k]batch pool", stats);
 418 }
 419
 420 #define count_vmas(list, member) do { \
 421         list_for_each_entry(vma, list, member) { \
 422                 size += i915_gem_obj_total_ggtt_size(vma->obj); \
 423                 ++count; \
 424                 if (vma->obj->map_and_fenceable) { \
 425                         mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
 426                         ++mappable_count; \
 427                 } \
 428         } \
 429 } while (0)
 430
 431 static int i915_gem_object_info(struct seq_file *m, void* data)
 432 {
 433         struct drm_info_node *node = m->private;
 434         struct drm_device *dev = node->minor->dev;
 435         struct drm_i915_private *dev_priv = dev->dev_private;
 436         u32 count, mappable_count, purgeable_count;
 437         u64 size, mappable_size, purgeable_size;
 438         struct drm_i915_gem_object *obj;
 439         struct i915_address_space *vm = &dev_priv->gtt.base;
 440         struct drm_file *file;
 441         struct i915_vma *vma;
 442         int ret;
 443
 444         ret = mutex_lock_interruptible(&dev->struct_mutex);
 445         if (ret)
 446                 return ret;
 447
 448         seq_printf(m, "%u objects, %zu bytes\n",
 449                    dev_priv->mm.object_count,
 450                    dev_priv->mm.object_memory);
 451
 452         size = count = mappable_size = mappable_count = 0;
 453         count_objects(&dev_priv->mm.bound_list, global_list);
 454         seq_printf(m, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
 455                    count, mappable_count, size, mappable_size);
 456
 457         size = count = mappable_size = mappable_count = 0;
 458         count_vmas(&vm->active_list, mm_list);
 459         seq_printf(m, "  %u [%u] active objects, %llu [%llu] bytes\n",
 460                    count, mappable_count, size, mappable_size);
 461
 462         size = count = mappable_size = mappable_count = 0;
 463         count_vmas(&vm->inactive_list, mm_list);
 464         seq_printf(m, "  %u [%u] inactive objects, %llu [%llu] bytes\n",
 465                    count, mappable_count, size, mappable_size);
 466
 467         size = count = purgeable_size = purgeable_count = 0;
 468         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 469                 size += obj->base.size, ++count;
 470                 if (obj->madv == I915_MADV_DONTNEED)
 471                         purgeable_size += obj->base.size, ++purgeable_count;
 472         }
 473         seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
 474
 475         size = count = mappable_size = mappable_count = 0;
 476         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 477                 if (obj->fault_mappable) {
 478                         size += i915_gem_obj_ggtt_size(obj);
 479                         ++count;
 480                 }
 481                 if (obj->pin_display) {
 482                         mappable_size += i915_gem_obj_ggtt_size(obj);
 483                         ++mappable_count;
 484                 }
 485                 if (obj->madv == I915_MADV_DONTNEED) {
 486                         purgeable_size += obj->base.size;
 487                         ++purgeable_count;
 488                 }
 489         }
 490         seq_printf(m, "%u purgeable objects, %llu bytes\n",
 491                    purgeable_count, purgeable_size);
 492         seq_printf(m, "%u pinned mappable objects, %llu bytes\n",
 493                    mappable_count, mappable_size);
 494         seq_printf(m, "%u fault mappable objects, %llu bytes\n",
 495                    count, size);
 496
 497         seq_printf(m, "%llu [%llu] gtt total\n",
 498                    dev_priv->gtt.base.total,
 499                    (u64)dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
 500
 501         seq_putc(m, '\n');
 502         print_batch_pool_stats(m, dev_priv);
 503         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
 504                 struct file_stats stats;
 505                 struct task_struct *task;
 506
 507                 memset(&stats, 0, sizeof(stats));
 508                 stats.file_priv = file->driver_priv;
 509                 spin_lock(&file->table_lock);
 510                 idr_for_each(&file->object_idr, per_file_stats, &stats);
 511                 spin_unlock(&file->table_lock);
 512                 /*
 513                  * Although we have a valid reference on file->pid, that does
 514                  * not guarantee that the task_struct who called get_pid() is
 515                  * still alive (e.g. get_pid(current) => fork() => exit()).
 516                  * Therefore, we need to protect this ->comm access using RCU.
 517                  */
 518                 rcu_read_lock();
 519                 task = pid_task(file->pid, PIDTYPE_PID);
 520                 print_file_stats(m, task ? task->comm : "<unknown>", stats);
 521                 rcu_read_unlock();
 522         }
 523
 524         mutex_unlock(&dev->struct_mutex);
 525
 526         return 0;
 527 }
 528
 529 static int i915_gem_gtt_info(struct seq_file *m, void *data)
 530 {
 531         struct drm_info_node *node = m->private;
 532         struct drm_device *dev = node->minor->dev;
 533         uintptr_t list = (uintptr_t) node->info_ent->data;
 534         struct drm_i915_private *dev_priv = dev->dev_private;
 535         struct drm_i915_gem_object *obj;
 536         u64 total_obj_size, total_gtt_size;
 537         int count, ret;
 538
 539         ret = mutex_lock_interruptible(&dev->struct_mutex);
 540         if (ret)
 541                 return ret;
 542
 543         total_obj_size = total_gtt_size = count = 0;
 544         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 545                 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
 546                         continue;
 547
 548                 seq_puts(m, "   ");
 549                 describe_obj(m, obj);
 550                 seq_putc(m, '\n');
 551                 total_obj_size += obj->base.size;
 552                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 553                 count++;
 554         }
 555
 556         mutex_unlock(&dev->struct_mutex);
 557
 558         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 559                    count, total_obj_size, total_gtt_size);
 560
 561         return 0;
 562 }
 563
 564 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
 565 {
 566         struct drm_info_node *node = m->private;
 567         struct drm_device *dev = node->minor->dev;
 568         struct drm_i915_private *dev_priv = dev->dev_private;
 569         struct intel_crtc *crtc;
 570         int ret;
 571
 572         ret = mutex_lock_interruptible(&dev->struct_mutex);
 573         if (ret)
 574                 return ret;
 575
 576         for_each_intel_crtc(dev, crtc) {
 577                 const char pipe = pipe_name(crtc->pipe);
 578                 const char plane = plane_name(crtc->plane);
 579                 struct intel_unpin_work *work;
 580
 581                 spin_lock_irq(&dev->event_lock);
 582                 work = crtc->unpin_work;
 583                 if (work == NULL) {
 584                         seq_printf(m, "No flip due on pipe %c (plane %c)\n",
 585                                    pipe, plane);
 586                 } else {
 587                         u32 addr;
 588
 589                         if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
 590                                 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
 591                                            pipe, plane);
 592                         } else {
 593                                 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
 594                                            pipe, plane);
 595                         }
 596                         if (work->flip_queued_req) {
 597                                 struct intel_engine_cs *ring =
 598                                         i915_gem_request_get_ring(work->flip_queued_req);
 599
 600                                 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
 601                                            ring->name,
 602                                            i915_gem_request_get_seqno(work->flip_queued_req),
 603                                            dev_priv->next_seqno,
 604                                            ring->get_seqno(ring, true),
 605                                            i915_gem_request_completed(work->flip_queued_req, true));
 606                         } else
 607                                 seq_printf(m, "Flip not associated with any ring\n");
 608                         seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
 609                                    work->flip_queued_vblank,
 610                                    work->flip_ready_vblank,
 611                                    drm_crtc_vblank_count(&crtc->base));
 612                         if (work->enable_stall_check)
 613                                 seq_puts(m, "Stall check enabled, ");
 614                         else
 615                                 seq_puts(m, "Stall check waiting for page flip ioctl, ");
 616                         seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
 617
 618                         if (INTEL_INFO(dev)->gen >= 4)
 619                                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
 620                         else
 621                                 addr = I915_READ(DSPADDR(crtc->plane));
 622                         seq_printf(m, "Current scanout address 0x%08x\n", addr);
 623
 624                         if (work->pending_flip_obj) {
 625                                 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
 626                                 seq_printf(m, "MMIO update completed? %d\n",  addr == work->gtt_offset);
 627                         }
 628                 }
 629                 spin_unlock_irq(&dev->event_lock);
 630         }
 631
 632         mutex_unlock(&dev->struct_mutex);
 633
 634         return 0;
 635 }
 636
 637 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
 638 {
 639         struct drm_info_node *node = m->private;
 640         struct drm_device *dev = node->minor->dev;
 641         struct drm_i915_private *dev_priv = dev->dev_private;
 642         struct drm_i915_gem_object *obj;
 643         struct intel_engine_cs *ring;
 644         int total = 0;
 645         int ret, i, j;
 646
 647         ret = mutex_lock_interruptible(&dev->struct_mutex);
 648         if (ret)
 649                 return ret;
 650
 651         for_each_ring(ring, dev_priv, i) {
 652                 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
 653                         int count;
 654
 655                         count = 0;
 656                         list_for_each_entry(obj,
 657                                             &ring->batch_pool.cache_list[j],
 658                                             batch_pool_link)
 659                                 count++;
 660                         seq_printf(m, "%s cache[%d]: %d objects\n",
 661                                    ring->name, j, count);
 662
 663                         list_for_each_entry(obj,
 664                                             &ring->batch_pool.cache_list[j],
 665                                             batch_pool_link) {
 666                                 seq_puts(m, "   ");
 667                                 describe_obj(m, obj);
 668                                 seq_putc(m, '\n');
 669                         }
 670
 671                         total += count;
 672                 }
 673         }
 674
 675         seq_printf(m, "total: %d\n", total);
 676
 677         mutex_unlock(&dev->struct_mutex);
 678
 679         return 0;
 680 }
 681
 682 static int i915_gem_request_info(struct seq_file *m, void *data)
 683 {
 684         struct drm_info_node *node = m->private;
 685         struct drm_device *dev = node->minor->dev;
 686         struct drm_i915_private *dev_priv = dev->dev_private;
 687         struct intel_engine_cs *ring;
 688         struct drm_i915_gem_request *req;
 689         int ret, any, i;
 690
 691         ret = mutex_lock_interruptible(&dev->struct_mutex);
 692         if (ret)
 693                 return ret;
 694
 695         any = 0;
 696         for_each_ring(ring, dev_priv, i) {
 697                 int count;
 698
 699                 count = 0;
 700                 list_for_each_entry(req, &ring->request_list, list)
 701                         count++;
 702                 if (count == 0)
 703                         continue;
 704
 705                 seq_printf(m, "%s requests: %d\n", ring->name, count);
 706                 list_for_each_entry(req, &ring->request_list, list) {
 707                         struct task_struct *task;
 708
 709                         rcu_read_lock();
 710                         task = NULL;
 711                         if (req->pid)
 712                                 task = pid_task(req->pid, PIDTYPE_PID);
 713                         seq_printf(m, "    %x @ %d: %s [%d]\n",
 714                                    req->seqno,
 715                                    (int) (jiffies - req->emitted_jiffies),
 716                                    task ? task->comm : "<unknown>",
 717                                    task ? task->pid : -1);
 718                         rcu_read_unlock();
 719                 }
 720
 721                 any++;
 722         }
 723         mutex_unlock(&dev->struct_mutex);
 724
 725         if (any == 0)
 726                 seq_puts(m, "No requests\n");
 727
 728         return 0;
 729 }
 730
 731 static void i915_ring_seqno_info(struct seq_file *m,
 732                                  struct intel_engine_cs *ring)
 733 {
 734         if (ring->get_seqno) {
 735                 seq_printf(m, "Current sequence (%s): %x\n",
 736                            ring->name, ring->get_seqno(ring, false));
 737         }
 738 }
 739
 740 static int i915_gem_seqno_info(struct seq_file *m, void *data)
 741 {
 742         struct drm_info_node *node = m->private;
 743         struct drm_device *dev = node->minor->dev;
 744         struct drm_i915_private *dev_priv = dev->dev_private;
 745         struct intel_engine_cs *ring;
 746         int ret, i;
 747
 748         ret = mutex_lock_interruptible(&dev->struct_mutex);
 749         if (ret)
 750                 return ret;
 751         intel_runtime_pm_get(dev_priv);
 752
 753         for_each_ring(ring, dev_priv, i)
 754                 i915_ring_seqno_info(m, ring);
 755
 756         intel_runtime_pm_put(dev_priv);
 757         mutex_unlock(&dev->struct_mutex);
 758
 759         return 0;
 760 }
 761
 762
 763 static int i915_interrupt_info(struct seq_file *m, void *data)
 764 {
 765         struct drm_info_node *node = m->private;
 766         struct drm_device *dev = node->minor->dev;
 767         struct drm_i915_private *dev_priv = dev->dev_private;
 768         struct intel_engine_cs *ring;
 769         int ret, i, pipe;
 770
 771         ret = mutex_lock_interruptible(&dev->struct_mutex);
 772         if (ret)
 773                 return ret;
 774         intel_runtime_pm_get(dev_priv);
 775
 776         if (IS_CHERRYVIEW(dev)) {
 777                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 778                            I915_READ(GEN8_MASTER_IRQ));
 779
 780                 seq_printf(m, "Display IER:\t%08x\n",
 781                            I915_READ(VLV_IER));
 782                 seq_printf(m, "Display IIR:\t%08x\n",
 783                            I915_READ(VLV_IIR));
 784                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 785                            I915_READ(VLV_IIR_RW));
 786                 seq_printf(m, "Display IMR:\t%08x\n",
 787                            I915_READ(VLV_IMR));
 788                 for_each_pipe(dev_priv, pipe)
 789                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 790                                    pipe_name(pipe),
 791                                    I915_READ(PIPESTAT(pipe)));
 792
 793                 seq_printf(m, "Port hotplug:\t%08x\n",
 794                            I915_READ(PORT_HOTPLUG_EN));
 795                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 796                            I915_READ(VLV_DPFLIPSTAT));
 797                 seq_printf(m, "DPINVGTT:\t%08x\n",
 798                            I915_READ(DPINVGTT));
 799
 800                 for (i = 0; i < 4; i++) {
 801                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 802                                    i, I915_READ(GEN8_GT_IMR(i)));
 803                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 804                                    i, I915_READ(GEN8_GT_IIR(i)));
 805                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 806                                    i, I915_READ(GEN8_GT_IER(i)));
 807                 }
 808
 809                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 810                            I915_READ(GEN8_PCU_IMR));
 811                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 812                            I915_READ(GEN8_PCU_IIR));
 813                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 814                            I915_READ(GEN8_PCU_IER));
 815         } else if (INTEL_INFO(dev)->gen >= 8) {
 816                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 817                            I915_READ(GEN8_MASTER_IRQ));
 818
 819                 for (i = 0; i < 4; i++) {
 820                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 821                                    i, I915_READ(GEN8_GT_IMR(i)));
 822                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 823                                    i, I915_READ(GEN8_GT_IIR(i)));
 824                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 825                                    i, I915_READ(GEN8_GT_IER(i)));
 826                 }
 827
 828                 for_each_pipe(dev_priv, pipe) {
 829                         if (!intel_display_power_is_enabled(dev_priv,
 830                                                 POWER_DOMAIN_PIPE(pipe))) {
 831                                 seq_printf(m, "Pipe %c power disabled\n",
 832                                            pipe_name(pipe));
 833                                 continue;
 834                         }
 835                         seq_printf(m, "Pipe %c IMR:\t%08x\n",
 836                                    pipe_name(pipe),
 837                                    I915_READ(GEN8_DE_PIPE_IMR(pipe)));
 838                         seq_printf(m, "Pipe %c IIR:\t%08x\n",
 839                                    pipe_name(pipe),
 840                                    I915_READ(GEN8_DE_PIPE_IIR(pipe)));
 841                         seq_printf(m, "Pipe %c IER:\t%08x\n",
 842                                    pipe_name(pipe),
 843                                    I915_READ(GEN8_DE_PIPE_IER(pipe)));
 844                 }
 845
 846                 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
 847                            I915_READ(GEN8_DE_PORT_IMR));
 848                 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
 849                            I915_READ(GEN8_DE_PORT_IIR));
 850                 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
 851                            I915_READ(GEN8_DE_PORT_IER));
 852
 853                 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
 854                            I915_READ(GEN8_DE_MISC_IMR));
 855                 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
 856                            I915_READ(GEN8_DE_MISC_IIR));
 857                 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
 858                            I915_READ(GEN8_DE_MISC_IER));
 859
 860                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 861                            I915_READ(GEN8_PCU_IMR));
 862                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 863                            I915_READ(GEN8_PCU_IIR));
 864                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 865                            I915_READ(GEN8_PCU_IER));
 866         } else if (IS_VALLEYVIEW(dev)) {
 867                 seq_printf(m, "Display IER:\t%08x\n",
 868                            I915_READ(VLV_IER));
 869                 seq_printf(m, "Display IIR:\t%08x\n",
 870                            I915_READ(VLV_IIR));
 871                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 872                            I915_READ(VLV_IIR_RW));
 873                 seq_printf(m, "Display IMR:\t%08x\n",
 874                            I915_READ(VLV_IMR));
 875                 for_each_pipe(dev_priv, pipe)
 876                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 877                                    pipe_name(pipe),
 878                                    I915_READ(PIPESTAT(pipe)));
 879
 880                 seq_printf(m, "Master IER:\t%08x\n",
 881                            I915_READ(VLV_MASTER_IER));
 882
 883                 seq_printf(m, "Render IER:\t%08x\n",
 884                            I915_READ(GTIER));
 885                 seq_printf(m, "Render IIR:\t%08x\n",
 886                            I915_READ(GTIIR));
 887                 seq_printf(m, "Render IMR:\t%08x\n",
 888                            I915_READ(GTIMR));
 889
 890                 seq_printf(m, "PM IER:\t\t%08x\n",
 891                            I915_READ(GEN6_PMIER));
 892                 seq_printf(m, "PM IIR:\t\t%08x\n",
 893                            I915_READ(GEN6_PMIIR));
 894                 seq_printf(m, "PM IMR:\t\t%08x\n",
 895                            I915_READ(GEN6_PMIMR));
 896
 897                 seq_printf(m, "Port hotplug:\t%08x\n",
 898                            I915_READ(PORT_HOTPLUG_EN));
 899                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 900                            I915_READ(VLV_DPFLIPSTAT));
 901                 seq_printf(m, "DPINVGTT:\t%08x\n",
 902                            I915_READ(DPINVGTT));
 903
 904         } else if (!HAS_PCH_SPLIT(dev)) {
 905                 seq_printf(m, "Interrupt enable:    %08x\n",
 906                            I915_READ(IER));
 907                 seq_printf(m, "Interrupt identity:  %08x\n",
 908                            I915_READ(IIR));
 909                 seq_printf(m, "Interrupt mask:      %08x\n",
 910                            I915_READ(IMR));
 911                 for_each_pipe(dev_priv, pipe)
 912                         seq_printf(m, "Pipe %c stat:         %08x\n",
 913                                    pipe_name(pipe),
 914                                    I915_READ(PIPESTAT(pipe)));
 915         } else {
 916                 seq_printf(m, "North Display Interrupt enable:          %08x\n",
 917                            I915_READ(DEIER));
 918                 seq_printf(m, "North Display Interrupt identity:        %08x\n",
 919                            I915_READ(DEIIR));
 920                 seq_printf(m, "North Display Interrupt mask:            %08x\n",
 921                            I915_READ(DEIMR));
 922                 seq_printf(m, "South Display Interrupt enable:          %08x\n",
 923                            I915_READ(SDEIER));
 924                 seq_printf(m, "South Display Interrupt identity:        %08x\n",
 925                            I915_READ(SDEIIR));
 926                 seq_printf(m, "South Display Interrupt mask:            %08x\n",
 927                            I915_READ(SDEIMR));
 928                 seq_printf(m, "Graphics Interrupt enable:               %08x\n",
 929                            I915_READ(GTIER));
 930                 seq_printf(m, "Graphics Interrupt identity:             %08x\n",
 931                            I915_READ(GTIIR));
 932                 seq_printf(m, "Graphics Interrupt mask:         %08x\n",
 933                            I915_READ(GTIMR));
 934         }
 935         for_each_ring(ring, dev_priv, i) {
 936                 if (INTEL_INFO(dev)->gen >= 6) {
 937                         seq_printf(m,
 938                                    "Graphics Interrupt mask (%s):       %08x\n",
 939                                    ring->name, I915_READ_IMR(ring));
 940                 }
 941                 i915_ring_seqno_info(m, ring);
 942         }
 943         intel_runtime_pm_put(dev_priv);
 944         mutex_unlock(&dev->struct_mutex);
 945
 946         return 0;
 947 }
 948
 949 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
 950 {
 951         struct drm_info_node *node = m->private;
 952         struct drm_device *dev = node->minor->dev;
 953         struct drm_i915_private *dev_priv = dev->dev_private;
 954         int i, ret;
 955
 956         ret = mutex_lock_interruptible(&dev->struct_mutex);
 957         if (ret)
 958                 return ret;
 959
 960         seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
 961         seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
 962         for (i = 0; i < dev_priv->num_fence_regs; i++) {
 963                 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
 964
 965                 seq_printf(m, "Fence %d, pin count = %d, object = ",
 966                            i, dev_priv->fence_regs[i].pin_count);
 967                 if (obj == NULL)
 968                         seq_puts(m, "unused");
 969                 else
 970                         describe_obj(m, obj);
 971                 seq_putc(m, '\n');
 972         }
 973
 974         mutex_unlock(&dev->struct_mutex);
 975         return 0;
 976 }
 977
 978 static int i915_hws_info(struct seq_file *m, void *data)
 979 {
 980         struct drm_info_node *node = m->private;
 981         struct drm_device *dev = node->minor->dev;
 982         struct drm_i915_private *dev_priv = dev->dev_private;
 983         struct intel_engine_cs *ring;
 984         const u32 *hws;
 985         int i;
 986
 987         ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
 988         hws = ring->status_page.page_addr;
 989         if (hws == NULL)
 990                 return 0;
 991
 992         for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
 993                 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
 994                            i * 4,
 995                            hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
 996         }
 997         return 0;
 998 }
 999
1000 static ssize_t
1001 i915_error_state_write(struct file *filp,
1002                        const char __user *ubuf,
1003                        size_t cnt,
1004                        loff_t *ppos)
1005 {
1006         struct i915_error_state_file_priv *error_priv = filp->private_data;
1007         struct drm_device *dev = error_priv->dev;
1008         int ret;
1009
1010         DRM_DEBUG_DRIVER("Resetting error state\n");
1011
1012         ret = mutex_lock_interruptible(&dev->struct_mutex);
1013         if (ret)
1014                 return ret;
1015
1016         i915_destroy_error_state(dev);
1017         mutex_unlock(&dev->struct_mutex);
1018
1019         return cnt;
1020 }
1021
1022 static int i915_error_state_open(struct inode *inode, struct file *file)
1023 {
1024         struct drm_device *dev = inode->i_private;
1025         struct i915_error_state_file_priv *error_priv;
1026
1027         error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
1028         if (!error_priv)
1029                 return -ENOMEM;
1030
1031         error_priv->dev = dev;
1032
1033         i915_error_state_get(dev, error_priv);
1034
1035         file->private_data = error_priv;
1036
1037         return 0;
1038 }
1039
1040 static int i915_error_state_release(struct inode *inode, struct file *file)
1041 {
1042         struct i915_error_state_file_priv *error_priv = file->private_data;
1043
1044         i915_error_state_put(error_priv);
1045         kfree(error_priv);
1046
1047         return 0;
1048 }
1049
1050 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1051                                      size_t count, loff_t *pos)
1052 {
1053         struct i915_error_state_file_priv *error_priv = file->private_data;
1054         struct drm_i915_error_state_buf error_str;
1055         loff_t tmp_pos = 0;
1056         ssize_t ret_count = 0;
1057         int ret;
1058
1059         ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
1060         if (ret)
1061                 return ret;
1062
1063         ret = i915_error_state_to_str(&error_str, error_priv);
1064         if (ret)
1065                 goto out;
1066
1067         ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1068                                             error_str.buf,
1069                                             error_str.bytes);
1070
1071         if (ret_count < 0)
1072                 ret = ret_count;
1073         else
1074                 *pos = error_str.start + ret_count;
1075 out:
1076         i915_error_state_buf_release(&error_str);
1077         return ret ?: ret_count;
1078 }
1079
1080 static const struct file_operations i915_error_state_fops = {
1081         .owner = THIS_MODULE,
1082         .open = i915_error_state_open,
1083         .read = i915_error_state_read,
1084         .write = i915_error_state_write,
1085         .llseek = default_llseek,
1086         .release = i915_error_state_release,
1087 };
1088
1089 static int
1090 i915_next_seqno_get(void *data, u64 *val)
1091 {
1092         struct drm_device *dev = data;
1093         struct drm_i915_private *dev_priv = dev->dev_private;
1094         int ret;
1095
1096         ret = mutex_lock_interruptible(&dev->struct_mutex);
1097         if (ret)
1098                 return ret;
1099
1100         *val = dev_priv->next_seqno;
1101         mutex_unlock(&dev->struct_mutex);
1102
1103         return 0;
1104 }
1105
1106 static int
1107 i915_next_seqno_set(void *data, u64 val)
1108 {
1109         struct drm_device *dev = data;
1110         int ret;
1111
1112         ret = mutex_lock_interruptible(&dev->struct_mutex);
1113         if (ret)
1114                 return ret;
1115
1116         ret = i915_gem_set_seqno(dev, val);
1117         mutex_unlock(&dev->struct_mutex);
1118
1119         return ret;
1120 }
1121
1122 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1123                         i915_next_seqno_get, i915_next_seqno_set,
1124                         "0x%llx\n");
1125
1126 static int i915_frequency_info(struct seq_file *m, void *unused)
1127 {
1128         struct drm_info_node *node = m->private;
1129         struct drm_device *dev = node->minor->dev;
1130         struct drm_i915_private *dev_priv = dev->dev_private;
1131         int ret = 0;
1132
1133         intel_runtime_pm_get(dev_priv);
1134
1135         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1136
1137         if (IS_GEN5(dev)) {
1138                 u16 rgvswctl = I915_READ16(MEMSWCTL);
1139                 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1140
1141                 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1142                 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1143                 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1144                            MEMSTAT_VID_SHIFT);
1145                 seq_printf(m, "Current P-state: %d\n",
1146                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1147         } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
1148                    IS_BROADWELL(dev) || IS_GEN9(dev)) {
1149                 u32 rp_state_limits;
1150                 u32 gt_perf_status;
1151                 u32 rp_state_cap;
1152                 u32 rpmodectl, rpinclimit, rpdeclimit;
1153                 u32 rpstat, cagf, reqf;
1154                 u32 rpupei, rpcurup, rpprevup;
1155                 u32 rpdownei, rpcurdown, rpprevdown;
1156                 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1157                 int max_freq;
1158
1159                 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1160                 if (IS_BROXTON(dev)) {
1161                         rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1162                         gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1163                 } else {
1164                         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1165                         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1166                 }
1167
1168                 /* RPSTAT1 is in the GT power well */
1169                 ret = mutex_lock_interruptible(&dev->struct_mutex);
1170                 if (ret)
1171                         goto out;
1172
1173                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1174
1175                 reqf = I915_READ(GEN6_RPNSWREQ);
1176                 if (IS_GEN9(dev))
1177                         reqf >>= 23;
1178                 else {
1179                         reqf &= ~GEN6_TURBO_DISABLE;
1180                         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1181                                 reqf >>= 24;
1182                         else
1183                                 reqf >>= 25;
1184                 }
1185                 reqf = intel_gpu_freq(dev_priv, reqf);
1186
1187                 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1188                 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1189                 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1190
1191                 rpstat = I915_READ(GEN6_RPSTAT1);
1192                 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1193                 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1194                 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1195                 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1196                 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1197                 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
1198                 if (IS_GEN9(dev))
1199                         cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1200                 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1201                         cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1202                 else
1203                         cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1204                 cagf = intel_gpu_freq(dev_priv, cagf);
1205
1206                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1207                 mutex_unlock(&dev->struct_mutex);
1208
1209                 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1210                         pm_ier = I915_READ(GEN6_PMIER);
1211                         pm_imr = I915_READ(GEN6_PMIMR);
1212                         pm_isr = I915_READ(GEN6_PMISR);
1213                         pm_iir = I915_READ(GEN6_PMIIR);
1214                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1215                 } else {
1216                         pm_ier = I915_READ(GEN8_GT_IER(2));
1217                         pm_imr = I915_READ(GEN8_GT_IMR(2));
1218                         pm_isr = I915_READ(GEN8_GT_ISR(2));
1219                         pm_iir = I915_READ(GEN8_GT_IIR(2));
1220                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1221                 }
1222                 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1223                            pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1224                 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1225                 seq_printf(m, "Render p-state ratio: %d\n",
1226                            (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
1227                 seq_printf(m, "Render p-state VID: %d\n",
1228                            gt_perf_status & 0xff);
1229                 seq_printf(m, "Render p-state limit: %d\n",
1230                            rp_state_limits & 0xff);
1231                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1232                 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1233                 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1234                 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1235                 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1236                 seq_printf(m, "CAGF: %dMHz\n", cagf);
1237                 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1238                            GEN6_CURICONT_MASK);
1239                 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1240                            GEN6_CURBSYTAVG_MASK);
1241                 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1242                            GEN6_CURBSYTAVG_MASK);
1243                 seq_printf(m, "Up threshold: %d%%\n",
1244                            dev_priv->rps.up_threshold);
1245
1246                 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1247                            GEN6_CURIAVG_MASK);
1248                 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1249                            GEN6_CURBSYTAVG_MASK);
1250                 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1251                            GEN6_CURBSYTAVG_MASK);
1252                 seq_printf(m, "Down threshold: %d%%\n",
1253                            dev_priv->rps.down_threshold);
1254
1255                 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 :
1256                             rp_state_cap >> 16) & 0xff;
1257                 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
1258                 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1259                            intel_gpu_freq(dev_priv, max_freq));
1260
1261                 max_freq = (rp_state_cap & 0xff00) >> 8;
1262                 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
1263                 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1264                            intel_gpu_freq(dev_priv, max_freq));
1265
1266                 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 :
1267                             rp_state_cap >> 0) & 0xff;
1268                 max_freq *= (IS_SKYLAKE(dev) ? GEN9_FREQ_SCALER : 1);
1269                 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1270                            intel_gpu_freq(dev_priv, max_freq));
1271                 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1272                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1273
1274                 seq_printf(m, "Current freq: %d MHz\n",
1275                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1276                 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1277                 seq_printf(m, "Idle freq: %d MHz\n",
1278                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1279                 seq_printf(m, "Min freq: %d MHz\n",
1280                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1281                 seq_printf(m, "Max freq: %d MHz\n",
1282                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1283                 seq_printf(m,
1284                            "efficient (RPe) frequency: %d MHz\n",
1285                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1286         } else if (IS_VALLEYVIEW(dev)) {
1287                 u32 freq_sts;
1288
1289                 mutex_lock(&dev_priv->rps.hw_lock);
1290                 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1291                 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1292                 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1293
1294                 seq_printf(m, "actual GPU freq: %d MHz\n",
1295                            intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1296
1297                 seq_printf(m, "current GPU freq: %d MHz\n",
1298                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1299
1300                 seq_printf(m, "max GPU freq: %d MHz\n",
1301                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1302
1303                 seq_printf(m, "min GPU freq: %d MHz\n",
1304                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1305
1306                 seq_printf(m, "idle GPU freq: %d MHz\n",
1307                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1308
1309                 seq_printf(m,
1310                            "efficient (RPe) frequency: %d MHz\n",
1311                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1312                 mutex_unlock(&dev_priv->rps.hw_lock);
1313         } else {
1314                 seq_puts(m, "no P-state info available\n");
1315         }
1316
1317 out:
1318         intel_runtime_pm_put(dev_priv);
1319         return ret;
1320 }
1321
1322 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1323 {
1324         struct drm_info_node *node = m->private;
1325         struct drm_device *dev = node->minor->dev;
1326         struct drm_i915_private *dev_priv = dev->dev_private;
1327         struct intel_engine_cs *ring;
1328         u64 acthd[I915_NUM_RINGS];
1329         u32 seqno[I915_NUM_RINGS];
1330         int i;
1331
1332         if (!i915.enable_hangcheck) {
1333                 seq_printf(m, "Hangcheck disabled\n");
1334                 return 0;
1335         }
1336
1337         intel_runtime_pm_get(dev_priv);
1338
1339         for_each_ring(ring, dev_priv, i) {
1340                 seqno[i] = ring->get_seqno(ring, false);
1341                 acthd[i] = intel_ring_get_active_head(ring);
1342         }
1343
1344         intel_runtime_pm_put(dev_priv);
1345
1346         if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1347                 seq_printf(m, "Hangcheck active, fires in %dms\n",
1348                            jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1349                                             jiffies));
1350         } else
1351                 seq_printf(m, "Hangcheck inactive\n");
1352
1353         for_each_ring(ring, dev_priv, i) {
1354                 seq_printf(m, "%s:\n", ring->name);
1355                 seq_printf(m, "\tseqno = %x [current %x]\n",
1356                            ring->hangcheck.seqno, seqno[i]);
1357                 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1358                            (long long)ring->hangcheck.acthd,
1359                            (long long)acthd[i]);
1360                 seq_printf(m, "\tmax ACTHD = 0x%08llx\n",
1361                            (long long)ring->hangcheck.max_acthd);
1362                 seq_printf(m, "\tscore = %d\n", ring->hangcheck.score);
1363                 seq_printf(m, "\taction = %d\n", ring->hangcheck.action);
1364         }
1365
1366         return 0;
1367 }
1368
1369 static int ironlake_drpc_info(struct seq_file *m)
1370 {
1371         struct drm_info_node *node = m->private;
1372         struct drm_device *dev = node->minor->dev;
1373         struct drm_i915_private *dev_priv = dev->dev_private;
1374         u32 rgvmodectl, rstdbyctl;
1375         u16 crstandvid;
1376         int ret;
1377
1378         ret = mutex_lock_interruptible(&dev->struct_mutex);
1379         if (ret)
1380                 return ret;
1381         intel_runtime_pm_get(dev_priv);
1382
1383         rgvmodectl = I915_READ(MEMMODECTL);
1384         rstdbyctl = I915_READ(RSTDBYCTL);
1385         crstandvid = I915_READ16(CRSTANDVID);
1386
1387         intel_runtime_pm_put(dev_priv);
1388         mutex_unlock(&dev->struct_mutex);
1389
1390         seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1391                    "yes" : "no");
1392         seq_printf(m, "Boost freq: %d\n",
1393                    (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1394                    MEMMODE_BOOST_FREQ_SHIFT);
1395         seq_printf(m, "HW control enabled: %s\n",
1396                    rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1397         seq_printf(m, "SW control enabled: %s\n",
1398                    rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1399         seq_printf(m, "Gated voltage change: %s\n",
1400                    rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1401         seq_printf(m, "Starting frequency: P%d\n",
1402                    (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1403         seq_printf(m, "Max P-state: P%d\n",
1404                    (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1405         seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1406         seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1407         seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1408         seq_printf(m, "Render standby enabled: %s\n",
1409                    (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
1410         seq_puts(m, "Current RS state: ");
1411         switch (rstdbyctl & RSX_STATUS_MASK) {
1412         case RSX_STATUS_ON:
1413                 seq_puts(m, "on\n");
1414                 break;
1415         case RSX_STATUS_RC1:
1416                 seq_puts(m, "RC1\n");
1417                 break;
1418         case RSX_STATUS_RC1E:
1419                 seq_puts(m, "RC1E\n");
1420                 break;
1421         case RSX_STATUS_RS1:
1422                 seq_puts(m, "RS1\n");
1423                 break;
1424         case RSX_STATUS_RS2:
1425                 seq_puts(m, "RS2 (RC6)\n");
1426                 break;
1427         case RSX_STATUS_RS3:
1428                 seq_puts(m, "RC3 (RC6+)\n");
1429                 break;
1430         default:
1431                 seq_puts(m, "unknown\n");
1432                 break;
1433         }
1434
1435         return 0;
1436 }
1437
1438 static int i915_forcewake_domains(struct seq_file *m, void *data)
1439 {
1440         struct drm_info_node *node = m->private;
1441         struct drm_device *dev = node->minor->dev;
1442         struct drm_i915_private *dev_priv = dev->dev_private;
1443         struct intel_uncore_forcewake_domain *fw_domain;
1444         int i;
1445
1446         spin_lock_irq(&dev_priv->uncore.lock);
1447         for_each_fw_domain(fw_domain, dev_priv, i) {
1448                 seq_printf(m, "%s.wake_count = %u\n",
1449                            intel_uncore_forcewake_domain_to_str(i),
1450                            fw_domain->wake_count);
1451         }
1452         spin_unlock_irq(&dev_priv->uncore.lock);
1453
1454         return 0;
1455 }
1456
1457 static int vlv_drpc_info(struct seq_file *m)
1458 {
1459         struct drm_info_node *node = m->private;
1460         struct drm_device *dev = node->minor->dev;
1461         struct drm_i915_private *dev_priv = dev->dev_private;
1462         u32 rpmodectl1, rcctl1, pw_status;
1463
1464         intel_runtime_pm_get(dev_priv);
1465
1466         pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1467         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1468         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1469
1470         intel_runtime_pm_put(dev_priv);
1471
1472         seq_printf(m, "Video Turbo Mode: %s\n",
1473                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1474         seq_printf(m, "Turbo enabled: %s\n",
1475                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1476         seq_printf(m, "HW control enabled: %s\n",
1477                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1478         seq_printf(m, "SW control enabled: %s\n",
1479                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1480                           GEN6_RP_MEDIA_SW_MODE));
1481         seq_printf(m, "RC6 Enabled: %s\n",
1482                    yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1483                                         GEN6_RC_CTL_EI_MODE(1))));
1484         seq_printf(m, "Render Power Well: %s\n",
1485                    (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1486         seq_printf(m, "Media Power Well: %s\n",
1487                    (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1488
1489         seq_printf(m, "Render RC6 residency since boot: %u\n",
1490                    I915_READ(VLV_GT_RENDER_RC6));
1491         seq_printf(m, "Media RC6 residency since boot: %u\n",
1492                    I915_READ(VLV_GT_MEDIA_RC6));
1493
1494         return i915_forcewake_domains(m, NULL);
1495 }
1496
1497 static int gen6_drpc_info(struct seq_file *m)
1498 {
1499         struct drm_info_node *node = m->private;
1500         struct drm_device *dev = node->minor->dev;
1501         struct drm_i915_private *dev_priv = dev->dev_private;
1502         u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1503         unsigned forcewake_count;
1504         int count = 0, ret;
1505
1506         ret = mutex_lock_interruptible(&dev->struct_mutex);
1507         if (ret)
1508                 return ret;
1509         intel_runtime_pm_get(dev_priv);
1510
1511         spin_lock_irq(&dev_priv->uncore.lock);
1512         forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1513         spin_unlock_irq(&dev_priv->uncore.lock);
1514
1515         if (forcewake_count) {
1516                 seq_puts(m, "RC information inaccurate because somebody "
1517                             "holds a forcewake reference \n");
1518         } else {
1519                 /* NB: we cannot use forcewake, else we read the wrong values */
1520                 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1521                         udelay(10);
1522                 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1523         }
1524
1525         gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
1526         trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1527
1528         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1529         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1530         mutex_unlock(&dev->struct_mutex);
1531         mutex_lock(&dev_priv->rps.hw_lock);
1532         sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1533         mutex_unlock(&dev_priv->rps.hw_lock);
1534
1535         intel_runtime_pm_put(dev_priv);
1536
1537         seq_printf(m, "Video Turbo Mode: %s\n",
1538                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1539         seq_printf(m, "HW control enabled: %s\n",
1540                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1541         seq_printf(m, "SW control enabled: %s\n",
1542                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1543                           GEN6_RP_MEDIA_SW_MODE));
1544         seq_printf(m, "RC1e Enabled: %s\n",
1545                    yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1546         seq_printf(m, "RC6 Enabled: %s\n",
1547                    yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1548         seq_printf(m, "Deep RC6 Enabled: %s\n",
1549                    yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1550         seq_printf(m, "Deepest RC6 Enabled: %s\n",
1551                    yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1552         seq_puts(m, "Current RC state: ");
1553         switch (gt_core_status & GEN6_RCn_MASK) {
1554         case GEN6_RC0:
1555                 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1556                         seq_puts(m, "Core Power Down\n");
1557                 else
1558                         seq_puts(m, "on\n");
1559                 break;
1560         case GEN6_RC3:
1561                 seq_puts(m, "RC3\n");
1562                 break;
1563         case GEN6_RC6:
1564                 seq_puts(m, "RC6\n");
1565                 break;
1566         case GEN6_RC7:
1567                 seq_puts(m, "RC7\n");
1568                 break;
1569         default:
1570                 seq_puts(m, "Unknown\n");
1571                 break;
1572         }
1573
1574         seq_printf(m, "Core Power Down: %s\n",
1575                    yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1576
1577         /* Not exactly sure what this is */
1578         seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1579                    I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1580         seq_printf(m, "RC6 residency since boot: %u\n",
1581                    I915_READ(GEN6_GT_GFX_RC6));
1582         seq_printf(m, "RC6+ residency since boot: %u\n",
1583                    I915_READ(GEN6_GT_GFX_RC6p));
1584         seq_printf(m, "RC6++ residency since boot: %u\n",
1585                    I915_READ(GEN6_GT_GFX_RC6pp));
1586
1587         seq_printf(m, "RC6   voltage: %dmV\n",
1588                    GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1589         seq_printf(m, "RC6+  voltage: %dmV\n",
1590                    GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1591         seq_printf(m, "RC6++ voltage: %dmV\n",
1592                    GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1593         return 0;
1594 }
1595
1596 static int i915_drpc_info(struct seq_file *m, void *unused)
1597 {
1598         struct drm_info_node *node = m->private;
1599         struct drm_device *dev = node->minor->dev;
1600
1601         if (IS_VALLEYVIEW(dev))
1602                 return vlv_drpc_info(m);
1603         else if (INTEL_INFO(dev)->gen >= 6)
1604                 return gen6_drpc_info(m);
1605         else
1606                 return ironlake_drpc_info(m);
1607 }
1608
1609 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1610 {
1611         struct drm_info_node *node = m->private;
1612         struct drm_device *dev = node->minor->dev;
1613         struct drm_i915_private *dev_priv = dev->dev_private;
1614
1615         seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1616                    dev_priv->fb_tracking.busy_bits);
1617
1618         seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1619                    dev_priv->fb_tracking.flip_bits);
1620
1621         return 0;
1622 }
1623
1624 static int i915_fbc_status(struct seq_file *m, void *unused)
1625 {
1626         struct drm_info_node *node = m->private;
1627         struct drm_device *dev = node->minor->dev;
1628         struct drm_i915_private *dev_priv = dev->dev_private;
1629
1630         if (!HAS_FBC(dev)) {
1631                 seq_puts(m, "FBC unsupported on this chipset\n");
1632                 return 0;
1633         }
1634
1635         intel_runtime_pm_get(dev_priv);
1636
1637         if (intel_fbc_enabled(dev))
1638                 seq_puts(m, "FBC enabled\n");
1639         else
1640                 seq_printf(m, "FBC disabled: %s\n",
1641                           intel_no_fbc_reason_str(dev_priv->fbc.no_fbc_reason));
1642
1643         if (INTEL_INFO(dev_priv)->gen >= 7)
1644                 seq_printf(m, "Compressing: %s\n",
1645                            yesno(I915_READ(FBC_STATUS2) &
1646                                  FBC_COMPRESSION_MASK));
1647
1648         intel_runtime_pm_put(dev_priv);
1649
1650         return 0;
1651 }
1652
1653 static int i915_fbc_fc_get(void *data, u64 *val)
1654 {
1655         struct drm_device *dev = data;
1656         struct drm_i915_private *dev_priv = dev->dev_private;
1657
1658         if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1659                 return -ENODEV;
1660
1661         drm_modeset_lock_all(dev);
1662         *val = dev_priv->fbc.false_color;
1663         drm_modeset_unlock_all(dev);
1664
1665         return 0;
1666 }
1667
1668 static int i915_fbc_fc_set(void *data, u64 val)
1669 {
1670         struct drm_device *dev = data;
1671         struct drm_i915_private *dev_priv = dev->dev_private;
1672         u32 reg;
1673
1674         if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1675                 return -ENODEV;
1676
1677         drm_modeset_lock_all(dev);
1678
1679         reg = I915_READ(ILK_DPFC_CONTROL);
1680         dev_priv->fbc.false_color = val;
1681
1682         I915_WRITE(ILK_DPFC_CONTROL, val ?
1683                    (reg | FBC_CTL_FALSE_COLOR) :
1684                    (reg & ~FBC_CTL_FALSE_COLOR));
1685
1686         drm_modeset_unlock_all(dev);
1687         return 0;
1688 }
1689
1690 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1691                         i915_fbc_fc_get, i915_fbc_fc_set,
1692                         "%llu\n");
1693
1694 static int i915_ips_status(struct seq_file *m, void *unused)
1695 {
1696         struct drm_info_node *node = m->private;
1697         struct drm_device *dev = node->minor->dev;
1698         struct drm_i915_private *dev_priv = dev->dev_private;
1699
1700         if (!HAS_IPS(dev)) {
1701                 seq_puts(m, "not supported\n");
1702                 return 0;
1703         }
1704
1705         intel_runtime_pm_get(dev_priv);
1706
1707         seq_printf(m, "Enabled by kernel parameter: %s\n",
1708                    yesno(i915.enable_ips));
1709
1710         if (INTEL_INFO(dev)->gen >= 8) {
1711                 seq_puts(m, "Currently: unknown\n");
1712         } else {
1713                 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1714                         seq_puts(m, "Currently: enabled\n");
1715                 else
1716                         seq_puts(m, "Currently: disabled\n");
1717         }
1718
1719         intel_runtime_pm_put(dev_priv);
1720
1721         return 0;
1722 }
1723
1724 static int i915_sr_status(struct seq_file *m, void *unused)
1725 {
1726         struct drm_info_node *node = m->private;
1727         struct drm_device *dev = node->minor->dev;
1728         struct drm_i915_private *dev_priv = dev->dev_private;
1729         bool sr_enabled = false;
1730
1731         intel_runtime_pm_get(dev_priv);
1732
1733         if (HAS_PCH_SPLIT(dev))
1734                 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1735         else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
1736                 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1737         else if (IS_I915GM(dev))
1738                 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1739         else if (IS_PINEVIEW(dev))
1740                 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1741
1742         intel_runtime_pm_put(dev_priv);
1743
1744         seq_printf(m, "self-refresh: %s\n",
1745                    sr_enabled ? "enabled" : "disabled");
1746
1747         return 0;
1748 }
1749
1750 static int i915_emon_status(struct seq_file *m, void *unused)
1751 {
1752         struct drm_info_node *node = m->private;
1753         struct drm_device *dev = node->minor->dev;
1754         struct drm_i915_private *dev_priv = dev->dev_private;
1755         unsigned long temp, chipset, gfx;
1756         int ret;
1757
1758         if (!IS_GEN5(dev))
1759                 return -ENODEV;
1760
1761         ret = mutex_lock_interruptible(&dev->struct_mutex);
1762         if (ret)
1763                 return ret;
1764
1765         temp = i915_mch_val(dev_priv);
1766         chipset = i915_chipset_val(dev_priv);
1767         gfx = i915_gfx_val(dev_priv);
1768         mutex_unlock(&dev->struct_mutex);
1769
1770         seq_printf(m, "GMCH temp: %ld\n", temp);
1771         seq_printf(m, "Chipset power: %ld\n", chipset);
1772         seq_printf(m, "GFX power: %ld\n", gfx);
1773         seq_printf(m, "Total power: %ld\n", chipset + gfx);
1774
1775         return 0;
1776 }
1777
1778 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1779 {
1780         struct drm_info_node *node = m->private;
1781         struct drm_device *dev = node->minor->dev;
1782         struct drm_i915_private *dev_priv = dev->dev_private;
1783         int ret = 0;
1784         int gpu_freq, ia_freq;
1785
1786         if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
1787                 seq_puts(m, "unsupported on this chipset\n");
1788                 return 0;
1789         }
1790
1791         intel_runtime_pm_get(dev_priv);
1792
1793         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1794
1795         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1796         if (ret)
1797                 goto out;
1798
1799         seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1800
1801         for (gpu_freq = dev_priv->rps.min_freq_softlimit;
1802              gpu_freq <= dev_priv->rps.max_freq_softlimit;
1803              gpu_freq++) {
1804                 ia_freq = gpu_freq;
1805                 sandybridge_pcode_read(dev_priv,
1806                                        GEN6_PCODE_READ_MIN_FREQ_TABLE,
1807                                        &ia_freq);
1808                 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1809                            intel_gpu_freq(dev_priv, gpu_freq),
1810                            ((ia_freq >> 0) & 0xff) * 100,
1811                            ((ia_freq >> 8) & 0xff) * 100);
1812         }
1813
1814         mutex_unlock(&dev_priv->rps.hw_lock);
1815
1816 out:
1817         intel_runtime_pm_put(dev_priv);
1818         return ret;
1819 }
1820
1821 static int i915_opregion(struct seq_file *m, void *unused)
1822 {
1823         struct drm_info_node *node = m->private;
1824         struct drm_device *dev = node->minor->dev;
1825         struct drm_i915_private *dev_priv = dev->dev_private;
1826         struct intel_opregion *opregion = &dev_priv->opregion;
1827         void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
1828         int ret;
1829
1830         if (data == NULL)
1831                 return -ENOMEM;
1832
1833         ret = mutex_lock_interruptible(&dev->struct_mutex);
1834         if (ret)
1835                 goto out;
1836
1837         if (opregion->header) {
1838                 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1839                 seq_write(m, data, OPREGION_SIZE);
1840         }
1841
1842         mutex_unlock(&dev->struct_mutex);
1843
1844 out:
1845         kfree(data);
1846         return 0;
1847 }
1848
1849 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1850 {
1851         struct drm_info_node *node = m->private;
1852         struct drm_device *dev = node->minor->dev;
1853         struct intel_fbdev *ifbdev = NULL;
1854         struct intel_framebuffer *fb;
1855
1856 #ifdef CONFIG_DRM_I915_FBDEV
1857         struct drm_i915_private *dev_priv = dev->dev_private;
1858
1859         ifbdev = dev_priv->fbdev;
1860         fb = to_intel_framebuffer(ifbdev->helper.fb);
1861
1862         seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1863                    fb->base.width,
1864                    fb->base.height,
1865                    fb->base.depth,
1866                    fb->base.bits_per_pixel,
1867                    fb->base.modifier[0],
1868                    atomic_read(&fb->base.refcount.refcount));
1869         describe_obj(m, fb->obj);
1870         seq_putc(m, '\n');
1871 #endif
1872
1873         mutex_lock(&dev->mode_config.fb_lock);
1874         list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1875                 if (ifbdev && &fb->base == ifbdev->helper.fb)
1876                         continue;
1877
1878                 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1879                            fb->base.width,
1880                            fb->base.height,
1881                            fb->base.depth,
1882                            fb->base.bits_per_pixel,
1883                            fb->base.modifier[0],
1884                            atomic_read(&fb->base.refcount.refcount));
1885                 describe_obj(m, fb->obj);
1886                 seq_putc(m, '\n');
1887         }
1888         mutex_unlock(&dev->mode_config.fb_lock);
1889
1890         return 0;
1891 }
1892
1893 static void describe_ctx_ringbuf(struct seq_file *m,
1894                                  struct intel_ringbuffer *ringbuf)
1895 {
1896         seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1897                    ringbuf->space, ringbuf->head, ringbuf->tail,
1898                    ringbuf->last_retired_head);
1899 }
1900
1901 static int i915_context_status(struct seq_file *m, void *unused)
1902 {
1903         struct drm_info_node *node = m->private;
1904         struct drm_device *dev = node->minor->dev;
1905         struct drm_i915_private *dev_priv = dev->dev_private;
1906         struct intel_engine_cs *ring;
1907         struct intel_context *ctx;
1908         int ret, i;
1909
1910         ret = mutex_lock_interruptible(&dev->struct_mutex);
1911         if (ret)
1912                 return ret;
1913
1914         list_for_each_entry(ctx, &dev_priv->context_list, link) {
1915                 if (!i915.enable_execlists &&
1916                     ctx->legacy_hw_ctx.rcs_state == NULL)
1917                         continue;
1918
1919                 seq_puts(m, "HW context ");
1920                 describe_ctx(m, ctx);
1921                 for_each_ring(ring, dev_priv, i) {
1922                         if (ring->default_context == ctx)
1923                                 seq_printf(m, "(default context %s) ",
1924                                            ring->name);
1925                 }
1926
1927                 if (i915.enable_execlists) {
1928                         seq_putc(m, '\n');
1929                         for_each_ring(ring, dev_priv, i) {
1930                                 struct drm_i915_gem_object *ctx_obj =
1931                                         ctx->engine[i].state;
1932                                 struct intel_ringbuffer *ringbuf =
1933                                         ctx->engine[i].ringbuf;
1934
1935                                 seq_printf(m, "%s: ", ring->name);
1936                                 if (ctx_obj)
1937                                         describe_obj(m, ctx_obj);
1938                                 if (ringbuf)
1939                                         describe_ctx_ringbuf(m, ringbuf);
1940                                 seq_putc(m, '\n');
1941                         }
1942                 } else {
1943                         describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1944                 }
1945
1946                 seq_putc(m, '\n');
1947         }
1948
1949         mutex_unlock(&dev->struct_mutex);
1950
1951         return 0;
1952 }
1953
1954 static void i915_dump_lrc_obj(struct seq_file *m,
1955                               struct intel_engine_cs *ring,
1956                               struct drm_i915_gem_object *ctx_obj)
1957 {
1958         struct page *page;
1959         uint32_t *reg_state;
1960         int j;
1961         unsigned long ggtt_offset = 0;
1962
1963         if (ctx_obj == NULL) {
1964                 seq_printf(m, "Context on %s with no gem object\n",
1965                            ring->name);
1966                 return;
1967         }
1968
1969         seq_printf(m, "CONTEXT: %s %u\n", ring->name,
1970                    intel_execlists_ctx_id(ctx_obj));
1971
1972         if (!i915_gem_obj_ggtt_bound(ctx_obj))
1973                 seq_puts(m, "\tNot bound in GGTT\n");
1974         else
1975                 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
1976
1977         if (i915_gem_object_get_pages(ctx_obj)) {
1978                 seq_puts(m, "\tFailed to get pages for context object\n");
1979                 return;
1980         }
1981
1982         page = i915_gem_object_get_page(ctx_obj, 1);
1983         if (!WARN_ON(page == NULL)) {
1984                 reg_state = kmap_atomic(page);
1985
1986                 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
1987                         seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
1988                                    ggtt_offset + 4096 + (j * 4),
1989                                    reg_state[j], reg_state[j + 1],
1990                                    reg_state[j + 2], reg_state[j + 3]);
1991                 }
1992                 kunmap_atomic(reg_state);
1993         }
1994
1995         seq_putc(m, '\n');
1996 }
1997
1998 static int i915_dump_lrc(struct seq_file *m, void *unused)
1999 {
2000         struct drm_info_node *node = (struct drm_info_node *) m->private;
2001         struct drm_device *dev = node->minor->dev;
2002         struct drm_i915_private *dev_priv = dev->dev_private;
2003         struct intel_engine_cs *ring;
2004         struct intel_context *ctx;
2005         int ret, i;
2006
2007         if (!i915.enable_execlists) {
2008                 seq_printf(m, "Logical Ring Contexts are disabled\n");
2009                 return 0;
2010         }
2011
2012         ret = mutex_lock_interruptible(&dev->struct_mutex);
2013         if (ret)
2014                 return ret;
2015
2016         list_for_each_entry(ctx, &dev_priv->context_list, link) {
2017                 for_each_ring(ring, dev_priv, i) {
2018                         if (ring->default_context != ctx)
2019                                 i915_dump_lrc_obj(m, ring,
2020                                                   ctx->engine[i].state);
2021                 }
2022         }
2023
2024         mutex_unlock(&dev->struct_mutex);
2025
2026         return 0;
2027 }
2028
2029 static int i915_execlists(struct seq_file *m, void *data)
2030 {
2031         struct drm_info_node *node = (struct drm_info_node *)m->private;
2032         struct drm_device *dev = node->minor->dev;
2033         struct drm_i915_private *dev_priv = dev->dev_private;
2034         struct intel_engine_cs *ring;
2035         u32 status_pointer;
2036         u8 read_pointer;
2037         u8 write_pointer;
2038         u32 status;
2039         u32 ctx_id;
2040         struct list_head *cursor;
2041         int ring_id, i;
2042         int ret;
2043
2044         if (!i915.enable_execlists) {
2045                 seq_puts(m, "Logical Ring Contexts are disabled\n");
2046                 return 0;
2047         }
2048
2049         ret = mutex_lock_interruptible(&dev->struct_mutex);
2050         if (ret)
2051                 return ret;
2052
2053         intel_runtime_pm_get(dev_priv);
2054
2055         for_each_ring(ring, dev_priv, ring_id) {
2056                 struct drm_i915_gem_request *head_req = NULL;
2057                 int count = 0;
2058                 unsigned long flags;
2059
2060                 seq_printf(m, "%s\n", ring->name);
2061
2062                 status = I915_READ(RING_EXECLIST_STATUS(ring));
2063                 ctx_id = I915_READ(RING_EXECLIST_STATUS(ring) + 4);
2064                 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2065                            status, ctx_id);
2066
2067                 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
2068                 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2069
2070                 read_pointer = ring->next_context_status_buffer;
2071                 write_pointer = status_pointer & 0x07;
2072                 if (read_pointer > write_pointer)
2073                         write_pointer += 6;
2074                 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2075                            read_pointer, write_pointer);
2076
2077                 for (i = 0; i < 6; i++) {
2078                         status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i);
2079                         ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + 8*i + 4);
2080
2081                         seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2082                                    i, status, ctx_id);
2083                 }
2084
2085                 spin_lock_irqsave(&ring->execlist_lock, flags);
2086                 list_for_each(cursor, &ring->execlist_queue)
2087                         count++;
2088                 head_req = list_first_entry_or_null(&ring->execlist_queue,
2089                                 struct drm_i915_gem_request, execlist_link);
2090                 spin_unlock_irqrestore(&ring->execlist_lock, flags);
2091
2092                 seq_printf(m, "\t%d requests in queue\n", count);
2093                 if (head_req) {
2094                         struct drm_i915_gem_object *ctx_obj;
2095
2096                         ctx_obj = head_req->ctx->engine[ring_id].state;
2097                         seq_printf(m, "\tHead request id: %u\n",
2098                                    intel_execlists_ctx_id(ctx_obj));
2099                         seq_printf(m, "\tHead request tail: %u\n",
2100                                    head_req->tail);
2101                 }
2102
2103                 seq_putc(m, '\n');
2104         }
2105
2106         intel_runtime_pm_put(dev_priv);
2107         mutex_unlock(&dev->struct_mutex);
2108
2109         return 0;
2110 }
2111
2112 static const char *swizzle_string(unsigned swizzle)
2113 {
2114         switch (swizzle) {
2115         case I915_BIT_6_SWIZZLE_NONE:
2116                 return "none";
2117         case I915_BIT_6_SWIZZLE_9:
2118                 return "bit9";
2119         case I915_BIT_6_SWIZZLE_9_10:
2120                 return "bit9/bit10";
2121         case I915_BIT_6_SWIZZLE_9_11:
2122                 return "bit9/bit11";
2123         case I915_BIT_6_SWIZZLE_9_10_11:
2124                 return "bit9/bit10/bit11";
2125         case I915_BIT_6_SWIZZLE_9_17:
2126                 return "bit9/bit17";
2127         case I915_BIT_6_SWIZZLE_9_10_17:
2128                 return "bit9/bit10/bit17";
2129         case I915_BIT_6_SWIZZLE_UNKNOWN:
2130                 return "unknown";
2131         }
2132
2133         return "bug";
2134 }
2135
2136 static int i915_swizzle_info(struct seq_file *m, void *data)
2137 {
2138         struct drm_info_node *node = m->private;
2139         struct drm_device *dev = node->minor->dev;
2140         struct drm_i915_private *dev_priv = dev->dev_private;
2141         int ret;
2142
2143         ret = mutex_lock_interruptible(&dev->struct_mutex);
2144         if (ret)
2145                 return ret;
2146         intel_runtime_pm_get(dev_priv);
2147
2148         seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2149                    swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2150         seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2151                    swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2152
2153         if (IS_GEN3(dev) || IS_GEN4(dev)) {
2154                 seq_printf(m, "DDC = 0x%08x\n",
2155                            I915_READ(DCC));
2156                 seq_printf(m, "DDC2 = 0x%08x\n",
2157                            I915_READ(DCC2));
2158                 seq_printf(m, "C0DRB3 = 0x%04x\n",
2159                            I915_READ16(C0DRB3));
2160                 seq_printf(m, "C1DRB3 = 0x%04x\n",
2161                            I915_READ16(C1DRB3));
2162         } else if (INTEL_INFO(dev)->gen >= 6) {
2163                 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2164                            I915_READ(MAD_DIMM_C0));
2165                 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2166                            I915_READ(MAD_DIMM_C1));
2167                 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2168                            I915_READ(MAD_DIMM_C2));
2169                 seq_printf(m, "TILECTL = 0x%08x\n",
2170                            I915_READ(TILECTL));
2171                 if (INTEL_INFO(dev)->gen >= 8)
2172                         seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2173                                    I915_READ(GAMTARBMODE));
2174                 else
2175                         seq_printf(m, "ARB_MODE = 0x%08x\n",
2176                                    I915_READ(ARB_MODE));
2177                 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2178                            I915_READ(DISP_ARB_CTL));
2179         }
2180
2181         if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2182                 seq_puts(m, "L-shaped memory detected\n");
2183
2184         intel_runtime_pm_put(dev_priv);
2185         mutex_unlock(&dev->struct_mutex);
2186
2187         return 0;
2188 }
2189
2190 static int per_file_ctx(int id, void *ptr, void *data)
2191 {
2192         struct intel_context *ctx = ptr;
2193         struct seq_file *m = data;
2194         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2195
2196         if (!ppgtt) {
2197                 seq_printf(m, "  no ppgtt for context %d\n",
2198                            ctx->user_handle);
2199                 return 0;
2200         }
2201
2202         if (i915_gem_context_is_default(ctx))
2203                 seq_puts(m, "  default context:\n");
2204         else
2205                 seq_printf(m, "  context %d:\n", ctx->user_handle);
2206         ppgtt->debug_dump(ppgtt, m);
2207
2208         return 0;
2209 }
2210
2211 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2212 {
2213         struct drm_i915_private *dev_priv = dev->dev_private;
2214         struct intel_engine_cs *ring;
2215         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2216         int unused, i;
2217
2218         if (!ppgtt)
2219                 return;
2220
2221         for_each_ring(ring, dev_priv, unused) {
2222                 seq_printf(m, "%s\n", ring->name);
2223                 for (i = 0; i < 4; i++) {
2224                         u32 offset = 0x270 + i * 8;
2225                         u64 pdp = I915_READ(ring->mmio_base + offset + 4);
2226                         pdp <<= 32;
2227                         pdp |= I915_READ(ring->mmio_base + offset);
2228                         seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2229                 }
2230         }
2231 }
2232
2233 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2234 {
2235         struct drm_i915_private *dev_priv = dev->dev_private;
2236         struct intel_engine_cs *ring;
2237         struct drm_file *file;
2238         int i;
2239
2240         if (INTEL_INFO(dev)->gen == 6)
2241                 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2242
2243         for_each_ring(ring, dev_priv, i) {
2244                 seq_printf(m, "%s\n", ring->name);
2245                 if (INTEL_INFO(dev)->gen == 7)
2246                         seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
2247                 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
2248                 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
2249                 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
2250         }
2251         if (dev_priv->mm.aliasing_ppgtt) {
2252                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2253
2254                 seq_puts(m, "aliasing PPGTT:\n");
2255                 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2256
2257                 ppgtt->debug_dump(ppgtt, m);
2258         }
2259
2260         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2261                 struct drm_i915_file_private *file_priv = file->driver_priv;
2262
2263                 seq_printf(m, "proc: %s\n",
2264                            get_pid_task(file->pid, PIDTYPE_PID)->comm);
2265                 idr_for_each(&file_priv->context_idr, per_file_ctx, m);
2266         }
2267         seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2268 }
2269
2270 static int i915_ppgtt_info(struct seq_file *m, void *data)
2271 {
2272         struct drm_info_node *node = m->private;
2273         struct drm_device *dev = node->minor->dev;
2274         struct drm_i915_private *dev_priv = dev->dev_private;
2275
2276         int ret = mutex_lock_interruptible(&dev->struct_mutex);
2277         if (ret)
2278                 return ret;
2279         intel_runtime_pm_get(dev_priv);
2280
2281         if (INTEL_INFO(dev)->gen >= 8)
2282                 gen8_ppgtt_info(m, dev);
2283         else if (INTEL_INFO(dev)->gen >= 6)
2284                 gen6_ppgtt_info(m, dev);
2285
2286         intel_runtime_pm_put(dev_priv);
2287         mutex_unlock(&dev->struct_mutex);
2288
2289         return 0;
2290 }
2291
2292 static int count_irq_waiters(struct drm_i915_private *i915)
2293 {
2294         struct intel_engine_cs *ring;
2295         int count = 0;
2296         int i;
2297
2298         for_each_ring(ring, i915, i)
2299                 count += ring->irq_refcount;
2300
2301         return count;
2302 }
2303
2304 static int i915_rps_boost_info(struct seq_file *m, void *data)
2305 {
2306         struct drm_info_node *node = m->private;
2307         struct drm_device *dev = node->minor->dev;
2308         struct drm_i915_private *dev_priv = dev->dev_private;
2309         struct drm_file *file;
2310
2311         seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2312         seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy);
2313         seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2314         seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2315                    intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2316                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2317                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2318                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2319                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2320         spin_lock(&dev_priv->rps.client_lock);
2321         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2322                 struct drm_i915_file_private *file_priv = file->driver_priv;
2323                 struct task_struct *task;
2324
2325                 rcu_read_lock();
2326                 task = pid_task(file->pid, PIDTYPE_PID);
2327                 seq_printf(m, "%s [%d]: %d boosts%s\n",
2328                            task ? task->comm : "<unknown>",
2329                            task ? task->pid : -1,
2330                            file_priv->rps.boosts,
2331                            list_empty(&file_priv->rps.link) ? "" : ", active");
2332                 rcu_read_unlock();
2333         }
2334         seq_printf(m, "Semaphore boosts: %d%s\n",
2335                    dev_priv->rps.semaphores.boosts,
2336                    list_empty(&dev_priv->rps.semaphores.link) ? "" : ", active");
2337         seq_printf(m, "MMIO flip boosts: %d%s\n",
2338                    dev_priv->rps.mmioflips.boosts,
2339                    list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active");
2340         seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts);
2341         spin_unlock(&dev_priv->rps.client_lock);
2342
2343         return 0;
2344 }
2345
2346 static int i915_llc(struct seq_file *m, void *data)
2347 {
2348         struct drm_info_node *node = m->private;
2349         struct drm_device *dev = node->minor->dev;
2350         struct drm_i915_private *dev_priv = dev->dev_private;
2351
2352         /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2353         seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2354         seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2355
2356         return 0;
2357 }
2358
2359 static int i915_edp_psr_status(struct seq_file *m, void *data)
2360 {
2361         struct drm_info_node *node = m->private;
2362         struct drm_device *dev = node->minor->dev;
2363         struct drm_i915_private *dev_priv = dev->dev_private;
2364         u32 psrperf = 0;
2365         u32 stat[3];
2366         enum pipe pipe;
2367         bool enabled = false;
2368
2369         if (!HAS_PSR(dev)) {
2370                 seq_puts(m, "PSR not supported\n");
2371                 return 0;
2372         }
2373
2374         intel_runtime_pm_get(dev_priv);
2375
2376         mutex_lock(&dev_priv->psr.lock);
2377         seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2378         seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2379         seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2380         seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2381         seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2382                    dev_priv->psr.busy_frontbuffer_bits);
2383         seq_printf(m, "Re-enable work scheduled: %s\n",
2384                    yesno(work_busy(&dev_priv->psr.work.work)));
2385
2386         if (HAS_DDI(dev))
2387                 enabled = I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
2388         else {
2389                 for_each_pipe(dev_priv, pipe) {
2390                         stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2391                                 VLV_EDP_PSR_CURR_STATE_MASK;
2392                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2393                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2394                                 enabled = true;
2395                 }
2396         }
2397         seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2398
2399         if (!HAS_DDI(dev))
2400                 for_each_pipe(dev_priv, pipe) {
2401                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2402                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2403                                 seq_printf(m, " pipe %c", pipe_name(pipe));
2404                 }
2405         seq_puts(m, "\n");
2406
2407         /* CHV PSR has no kind of performance counter */
2408         if (HAS_DDI(dev)) {
2409                 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
2410                         EDP_PSR_PERF_CNT_MASK;
2411
2412                 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2413         }
2414         mutex_unlock(&dev_priv->psr.lock);
2415
2416         intel_runtime_pm_put(dev_priv);
2417         return 0;
2418 }
2419
2420 static int i915_sink_crc(struct seq_file *m, void *data)
2421 {
2422         struct drm_info_node *node = m->private;
2423         struct drm_device *dev = node->minor->dev;
2424         struct intel_encoder *encoder;
2425         struct intel_connector *connector;
2426         struct intel_dp *intel_dp = NULL;
2427         int ret;
2428         u8 crc[6];
2429
2430         drm_modeset_lock_all(dev);
2431         for_each_intel_connector(dev, connector) {
2432
2433                 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2434                         continue;
2435
2436                 if (!connector->base.encoder)
2437                         continue;
2438
2439                 encoder = to_intel_encoder(connector->base.encoder);
2440                 if (encoder->type != INTEL_OUTPUT_EDP)
2441                         continue;
2442
2443                 intel_dp = enc_to_intel_dp(&encoder->base);
2444
2445                 ret = intel_dp_sink_crc(intel_dp, crc);
2446                 if (ret)
2447                         goto out;
2448
2449                 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2450                            crc[0], crc[1], crc[2],
2451                            crc[3], crc[4], crc[5]);
2452                 goto out;
2453         }
2454         ret = -ENODEV;
2455 out:
2456         drm_modeset_unlock_all(dev);
2457         return ret;
2458 }
2459
2460 static int i915_energy_uJ(struct seq_file *m, void *data)
2461 {
2462         struct drm_info_node *node = m->private;
2463         struct drm_device *dev = node->minor->dev;
2464         struct drm_i915_private *dev_priv = dev->dev_private;
2465         u64 power;
2466         u32 units;
2467
2468         if (INTEL_INFO(dev)->gen < 6)
2469                 return -ENODEV;
2470
2471         intel_runtime_pm_get(dev_priv);
2472
2473         rdmsrl(MSR_RAPL_POWER_UNIT, power);
2474         power = (power & 0x1f00) >> 8;
2475         units = 1000000 / (1 << power); /* convert to uJ */
2476         power = I915_READ(MCH_SECP_NRG_STTS);
2477         power *= units;
2478
2479         intel_runtime_pm_put(dev_priv);
2480
2481         seq_printf(m, "%llu", (long long unsigned)power);
2482
2483         return 0;
2484 }
2485
2486 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2487 {
2488         struct drm_info_node *node = m->private;
2489         struct drm_device *dev = node->minor->dev;
2490         struct drm_i915_private *dev_priv = dev->dev_private;
2491
2492         if (!HAS_RUNTIME_PM(dev)) {
2493                 seq_puts(m, "not supported\n");
2494                 return 0;
2495         }
2496
2497         seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
2498         seq_printf(m, "IRQs disabled: %s\n",
2499                    yesno(!intel_irqs_enabled(dev_priv)));
2500 #ifdef CONFIG_PM
2501         seq_printf(m, "Usage count: %d\n",
2502                    atomic_read(&dev->dev->power.usage_count));
2503 #else
2504         seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2505 #endif
2506
2507         return 0;
2508 }
2509
2510 static const char *power_domain_str(enum intel_display_power_domain domain)
2511 {
2512         switch (domain) {
2513         case POWER_DOMAIN_PIPE_A:
2514                 return "PIPE_A";
2515         case POWER_DOMAIN_PIPE_B:
2516                 return "PIPE_B";
2517         case POWER_DOMAIN_PIPE_C:
2518                 return "PIPE_C";
2519         case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2520                 return "PIPE_A_PANEL_FITTER";
2521         case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2522                 return "PIPE_B_PANEL_FITTER";
2523         case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2524                 return "PIPE_C_PANEL_FITTER";
2525         case POWER_DOMAIN_TRANSCODER_A:
2526                 return "TRANSCODER_A";
2527         case POWER_DOMAIN_TRANSCODER_B:
2528                 return "TRANSCODER_B";
2529         case POWER_DOMAIN_TRANSCODER_C:
2530                 return "TRANSCODER_C";
2531         case POWER_DOMAIN_TRANSCODER_EDP:
2532                 return "TRANSCODER_EDP";
2533         case POWER_DOMAIN_PORT_DDI_A_2_LANES:
2534                 return "PORT_DDI_A_2_LANES";
2535         case POWER_DOMAIN_PORT_DDI_A_4_LANES:
2536                 return "PORT_DDI_A_4_LANES";
2537         case POWER_DOMAIN_PORT_DDI_B_2_LANES:
2538                 return "PORT_DDI_B_2_LANES";
2539         case POWER_DOMAIN_PORT_DDI_B_4_LANES:
2540                 return "PORT_DDI_B_4_LANES";
2541         case POWER_DOMAIN_PORT_DDI_C_2_LANES:
2542                 return "PORT_DDI_C_2_LANES";
2543         case POWER_DOMAIN_PORT_DDI_C_4_LANES:
2544                 return "PORT_DDI_C_4_LANES";
2545         case POWER_DOMAIN_PORT_DDI_D_2_LANES:
2546                 return "PORT_DDI_D_2_LANES";
2547         case POWER_DOMAIN_PORT_DDI_D_4_LANES:
2548                 return "PORT_DDI_D_4_LANES";
2549         case POWER_DOMAIN_PORT_DSI:
2550                 return "PORT_DSI";
2551         case POWER_DOMAIN_PORT_CRT:
2552                 return "PORT_CRT";
2553         case POWER_DOMAIN_PORT_OTHER:
2554                 return "PORT_OTHER";
2555         case POWER_DOMAIN_VGA:
2556                 return "VGA";
2557         case POWER_DOMAIN_AUDIO:
2558                 return "AUDIO";
2559         case POWER_DOMAIN_PLLS:
2560                 return "PLLS";
2561         case POWER_DOMAIN_AUX_A:
2562                 return "AUX_A";
2563         case POWER_DOMAIN_AUX_B:
2564                 return "AUX_B";
2565         case POWER_DOMAIN_AUX_C:
2566                 return "AUX_C";
2567         case POWER_DOMAIN_AUX_D:
2568                 return "AUX_D";
2569         case POWER_DOMAIN_INIT:
2570                 return "INIT";
2571         default:
2572                 MISSING_CASE(domain);
2573                 return "?";
2574         }
2575 }
2576
2577 static int i915_power_domain_info(struct seq_file *m, void *unused)
2578 {
2579         struct drm_info_node *node = m->private;
2580         struct drm_device *dev = node->minor->dev;
2581         struct drm_i915_private *dev_priv = dev->dev_private;
2582         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2583         int i;
2584
2585         mutex_lock(&power_domains->lock);
2586
2587         seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2588         for (i = 0; i < power_domains->power_well_count; i++) {
2589                 struct i915_power_well *power_well;
2590                 enum intel_display_power_domain power_domain;
2591
2592                 power_well = &power_domains->power_wells[i];
2593                 seq_printf(m, "%-25s %d\n", power_well->name,
2594                            power_well->count);
2595
2596                 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2597                      power_domain++) {
2598                         if (!(BIT(power_domain) & power_well->domains))
2599                                 continue;
2600
2601                         seq_printf(m, "  %-23s %d\n",
2602                                  power_domain_str(power_domain),
2603                                  power_domains->domain_use_count[power_domain]);
2604                 }
2605         }
2606
2607         mutex_unlock(&power_domains->lock);
2608
2609         return 0;
2610 }
2611
2612 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2613                                  struct drm_display_mode *mode)
2614 {
2615         int i;
2616
2617         for (i = 0; i < tabs; i++)
2618                 seq_putc(m, '\t');
2619
2620         seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2621                    mode->base.id, mode->name,
2622                    mode->vrefresh, mode->clock,
2623                    mode->hdisplay, mode->hsync_start,
2624                    mode->hsync_end, mode->htotal,
2625                    mode->vdisplay, mode->vsync_start,
2626                    mode->vsync_end, mode->vtotal,
2627                    mode->type, mode->flags);
2628 }
2629
2630 static void intel_encoder_info(struct seq_file *m,
2631                                struct intel_crtc *intel_crtc,
2632                                struct intel_encoder *intel_encoder)
2633 {
2634         struct drm_info_node *node = m->private;
2635         struct drm_device *dev = node->minor->dev;
2636         struct drm_crtc *crtc = &intel_crtc->base;
2637         struct intel_connector *intel_connector;
2638         struct drm_encoder *encoder;
2639
2640         encoder = &intel_encoder->base;
2641         seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2642                    encoder->base.id, encoder->name);
2643         for_each_connector_on_encoder(dev, encoder, intel_connector) {
2644                 struct drm_connector *connector = &intel_connector->base;
2645                 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2646                            connector->base.id,
2647                            connector->name,
2648                            drm_get_connector_status_name(connector->status));
2649                 if (connector->status == connector_status_connected) {
2650                         struct drm_display_mode *mode = &crtc->mode;
2651                         seq_printf(m, ", mode:\n");
2652                         intel_seq_print_mode(m, 2, mode);
2653                 } else {
2654                         seq_putc(m, '\n');
2655                 }
2656         }
2657 }
2658
2659 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2660 {
2661         struct drm_info_node *node = m->private;
2662         struct drm_device *dev = node->minor->dev;
2663         struct drm_crtc *crtc = &intel_crtc->base;
2664         struct intel_encoder *intel_encoder;
2665
2666         if (crtc->primary->fb)
2667                 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2668                            crtc->primary->fb->base.id, crtc->x, crtc->y,
2669                            crtc->primary->fb->width, crtc->primary->fb->height);
2670         else
2671                 seq_puts(m, "\tprimary plane disabled\n");
2672         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2673                 intel_encoder_info(m, intel_crtc, intel_encoder);
2674 }
2675
2676 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2677 {
2678         struct drm_display_mode *mode = panel->fixed_mode;
2679
2680         seq_printf(m, "\tfixed mode:\n");
2681         intel_seq_print_mode(m, 2, mode);
2682 }
2683
2684 static void intel_dp_info(struct seq_file *m,
2685                           struct intel_connector *intel_connector)
2686 {
2687         struct intel_encoder *intel_encoder = intel_connector->encoder;
2688         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2689
2690         seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2691         seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2692                    "no");
2693         if (intel_encoder->type == INTEL_OUTPUT_EDP)
2694                 intel_panel_info(m, &intel_connector->panel);
2695 }
2696
2697 static void intel_hdmi_info(struct seq_file *m,
2698                             struct intel_connector *intel_connector)
2699 {
2700         struct intel_encoder *intel_encoder = intel_connector->encoder;
2701         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2702
2703         seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2704                    "no");
2705 }
2706
2707 static void intel_lvds_info(struct seq_file *m,
2708                             struct intel_connector *intel_connector)
2709 {
2710         intel_panel_info(m, &intel_connector->panel);
2711 }
2712
2713 static void intel_connector_info(struct seq_file *m,
2714                                  struct drm_connector *connector)
2715 {
2716         struct intel_connector *intel_connector = to_intel_connector(connector);
2717         struct intel_encoder *intel_encoder = intel_connector->encoder;
2718         struct drm_display_mode *mode;
2719
2720         seq_printf(m, "connector %d: type %s, status: %s\n",
2721                    connector->base.id, connector->name,
2722                    drm_get_connector_status_name(connector->status));
2723         if (connector->status == connector_status_connected) {
2724                 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2725                 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2726                            connector->display_info.width_mm,
2727                            connector->display_info.height_mm);
2728                 seq_printf(m, "\tsubpixel order: %s\n",
2729                            drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2730                 seq_printf(m, "\tCEA rev: %d\n",
2731                            connector->display_info.cea_rev);
2732         }
2733         if (intel_encoder) {
2734                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2735                     intel_encoder->type == INTEL_OUTPUT_EDP)
2736                         intel_dp_info(m, intel_connector);
2737                 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2738                         intel_hdmi_info(m, intel_connector);
2739                 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2740                         intel_lvds_info(m, intel_connector);
2741         }
2742
2743         seq_printf(m, "\tmodes:\n");
2744         list_for_each_entry(mode, &connector->modes, head)
2745                 intel_seq_print_mode(m, 2, mode);
2746 }
2747
2748 static bool cursor_active(struct drm_device *dev, int pipe)
2749 {
2750         struct drm_i915_private *dev_priv = dev->dev_private;
2751         u32 state;
2752
2753         if (IS_845G(dev) || IS_I865G(dev))
2754                 state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
2755         else
2756                 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2757
2758         return state;
2759 }
2760
2761 static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2762 {
2763         struct drm_i915_private *dev_priv = dev->dev_private;
2764         u32 pos;
2765
2766         pos = I915_READ(CURPOS(pipe));
2767
2768         *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2769         if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2770                 *x = -*x;
2771
2772         *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2773         if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2774                 *y = -*y;
2775
2776         return cursor_active(dev, pipe);
2777 }
2778
2779 static int i915_display_info(struct seq_file *m, void *unused)
2780 {
2781         struct drm_info_node *node = m->private;
2782         struct drm_device *dev = node->minor->dev;
2783         struct drm_i915_private *dev_priv = dev->dev_private;
2784         struct intel_crtc *crtc;
2785         struct drm_connector *connector;
2786
2787         intel_runtime_pm_get(dev_priv);
2788         drm_modeset_lock_all(dev);
2789         seq_printf(m, "CRTC info\n");
2790         seq_printf(m, "---------\n");
2791         for_each_intel_crtc(dev, crtc) {
2792                 bool active;
2793                 struct intel_crtc_state *pipe_config;
2794                 int x, y;
2795
2796                 pipe_config = to_intel_crtc_state(crtc->base.state);
2797
2798                 seq_printf(m, "CRTC %d: pipe: %c, active=%s (size=%dx%d)\n",
2799                            crtc->base.base.id, pipe_name(crtc->pipe),
2800                            yesno(pipe_config->base.active),
2801                            pipe_config->pipe_src_w, pipe_config->pipe_src_h);
2802                 if (pipe_config->base.active) {
2803                         intel_crtc_info(m, crtc);
2804
2805                         active = cursor_position(dev, crtc->pipe, &x, &y);
2806                         seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
2807                                    yesno(crtc->cursor_base),
2808                                    x, y, crtc->base.cursor->state->crtc_w,
2809                                    crtc->base.cursor->state->crtc_h,
2810                                    crtc->cursor_addr, yesno(active));
2811                 }
2812
2813                 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
2814                            yesno(!crtc->cpu_fifo_underrun_disabled),
2815                            yesno(!crtc->pch_fifo_underrun_disabled));
2816         }
2817
2818         seq_printf(m, "\n");
2819         seq_printf(m, "Connector info\n");
2820         seq_printf(m, "--------------\n");
2821         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2822                 intel_connector_info(m, connector);
2823         }
2824         drm_modeset_unlock_all(dev);
2825         intel_runtime_pm_put(dev_priv);
2826
2827         return 0;
2828 }
2829
2830 static int i915_semaphore_status(struct seq_file *m, void *unused)
2831 {
2832         struct drm_info_node *node = (struct drm_info_node *) m->private;
2833         struct drm_device *dev = node->minor->dev;
2834         struct drm_i915_private *dev_priv = dev->dev_private;
2835         struct intel_engine_cs *ring;
2836         int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
2837         int i, j, ret;
2838
2839         if (!i915_semaphore_is_enabled(dev)) {
2840                 seq_puts(m, "Semaphores are disabled\n");
2841                 return 0;
2842         }
2843
2844         ret = mutex_lock_interruptible(&dev->struct_mutex);
2845         if (ret)
2846                 return ret;
2847         intel_runtime_pm_get(dev_priv);
2848
2849         if (IS_BROADWELL(dev)) {
2850                 struct page *page;
2851                 uint64_t *seqno;
2852
2853                 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
2854
2855                 seqno = (uint64_t *)kmap_atomic(page);
2856                 for_each_ring(ring, dev_priv, i) {
2857                         uint64_t offset;
2858
2859                         seq_printf(m, "%s\n", ring->name);
2860
2861                         seq_puts(m, "  Last signal:");
2862                         for (j = 0; j < num_rings; j++) {
2863                                 offset = i * I915_NUM_RINGS + j;
2864                                 seq_printf(m, "0x%08llx (0x%02llx) ",
2865                                            seqno[offset], offset * 8);
2866                         }
2867                         seq_putc(m, '\n');
2868
2869                         seq_puts(m, "  Last wait:  ");
2870                         for (j = 0; j < num_rings; j++) {
2871                                 offset = i + (j * I915_NUM_RINGS);
2872                                 seq_printf(m, "0x%08llx (0x%02llx) ",
2873                                            seqno[offset], offset * 8);
2874                         }
2875                         seq_putc(m, '\n');
2876
2877                 }
2878                 kunmap_atomic(seqno);
2879         } else {
2880                 seq_puts(m, "  Last signal:");
2881                 for_each_ring(ring, dev_priv, i)
2882                         for (j = 0; j < num_rings; j++)
2883                                 seq_printf(m, "0x%08x\n",
2884                                            I915_READ(ring->semaphore.mbox.signal[j]));
2885                 seq_putc(m, '\n');
2886         }
2887
2888         seq_puts(m, "\nSync seqno:\n");
2889         for_each_ring(ring, dev_priv, i) {
2890                 for (j = 0; j < num_rings; j++) {
2891                         seq_printf(m, "  0x%08x ", ring->semaphore.sync_seqno[j]);
2892                 }
2893                 seq_putc(m, '\n');
2894         }
2895         seq_putc(m, '\n');
2896
2897         intel_runtime_pm_put(dev_priv);
2898         mutex_unlock(&dev->struct_mutex);
2899         return 0;
2900 }
2901
2902 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
2903 {
2904         struct drm_info_node *node = (struct drm_info_node *) m->private;
2905         struct drm_device *dev = node->minor->dev;
2906         struct drm_i915_private *dev_priv = dev->dev_private;
2907         int i;
2908
2909         drm_modeset_lock_all(dev);
2910         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2911                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
2912
2913                 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
2914                 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",
2915                            pll->config.crtc_mask, pll->active, yesno(pll->on));
2916                 seq_printf(m, " tracked hardware state:\n");
2917                 seq_printf(m, " dpll:    0x%08x\n", pll->config.hw_state.dpll);
2918                 seq_printf(m, " dpll_md: 0x%08x\n",
2919                            pll->config.hw_state.dpll_md);
2920                 seq_printf(m, " fp0:     0x%08x\n", pll->config.hw_state.fp0);
2921                 seq_printf(m, " fp1:     0x%08x\n", pll->config.hw_state.fp1);
2922                 seq_printf(m, " wrpll:   0x%08x\n", pll->config.hw_state.wrpll);
2923         }
2924         drm_modeset_unlock_all(dev);
2925
2926         return 0;
2927 }
2928
2929 static int i915_wa_registers(struct seq_file *m, void *unused)
2930 {
2931         int i;
2932         int ret;
2933         struct drm_info_node *node = (struct drm_info_node *) m->private;
2934         struct drm_device *dev = node->minor->dev;
2935         struct drm_i915_private *dev_priv = dev->dev_private;
2936
2937         ret = mutex_lock_interruptible(&dev->struct_mutex);
2938         if (ret)
2939                 return ret;
2940
2941         intel_runtime_pm_get(dev_priv);
2942
2943         seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
2944         for (i = 0; i < dev_priv->workarounds.count; ++i) {
2945                 u32 addr, mask, value, read;
2946                 bool ok;
2947
2948                 addr = dev_priv->workarounds.reg[i].addr;
2949                 mask = dev_priv->workarounds.reg[i].mask;
2950                 value = dev_priv->workarounds.reg[i].value;
2951                 read = I915_READ(addr);
2952                 ok = (value & mask) == (read & mask);
2953                 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
2954                            addr, value, mask, read, ok ? "OK" : "FAIL");
2955         }
2956
2957         intel_runtime_pm_put(dev_priv);
2958         mutex_unlock(&dev->struct_mutex);
2959
2960         return 0;
2961 }
2962
2963 static int i915_ddb_info(struct seq_file *m, void *unused)
2964 {
2965         struct drm_info_node *node = m->private;
2966         struct drm_device *dev = node->minor->dev;
2967         struct drm_i915_private *dev_priv = dev->dev_private;
2968         struct skl_ddb_allocation *ddb;
2969         struct skl_ddb_entry *entry;
2970         enum pipe pipe;
2971         int plane;
2972
2973         if (INTEL_INFO(dev)->gen < 9)
2974                 return 0;
2975
2976         drm_modeset_lock_all(dev);
2977
2978         ddb = &dev_priv->wm.skl_hw.ddb;
2979
2980         seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
2981
2982         for_each_pipe(dev_priv, pipe) {
2983                 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
2984
2985                 for_each_plane(dev_priv, pipe, plane) {
2986                         entry = &ddb->plane[pipe][plane];
2987                         seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane + 1,
2988                                    entry->start, entry->end,
2989                                    skl_ddb_entry_size(entry));
2990                 }
2991
2992                 entry = &ddb->cursor[pipe];
2993                 seq_printf(m, "  %-13s%8u%8u%8u\n", "Cursor", entry->start,
2994                            entry->end, skl_ddb_entry_size(entry));
2995         }
2996
2997         drm_modeset_unlock_all(dev);
2998
2999         return 0;
3000 }
3001
3002 static void drrs_status_per_crtc(struct seq_file *m,
3003                 struct drm_device *dev, struct intel_crtc *intel_crtc)
3004 {
3005         struct intel_encoder *intel_encoder;
3006         struct drm_i915_private *dev_priv = dev->dev_private;
3007         struct i915_drrs *drrs = &dev_priv->drrs;
3008         int vrefresh = 0;
3009
3010         for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) {
3011                 /* Encoder connected on this CRTC */
3012                 switch (intel_encoder->type) {
3013                 case INTEL_OUTPUT_EDP:
3014                         seq_puts(m, "eDP:\n");
3015                         break;
3016                 case INTEL_OUTPUT_DSI:
3017                         seq_puts(m, "DSI:\n");
3018                         break;
3019                 case INTEL_OUTPUT_HDMI:
3020                         seq_puts(m, "HDMI:\n");
3021                         break;
3022                 case INTEL_OUTPUT_DISPLAYPORT:
3023                         seq_puts(m, "DP:\n");
3024                         break;
3025                 default:
3026                         seq_printf(m, "Other encoder (id=%d).\n",
3027                                                 intel_encoder->type);
3028                         return;
3029                 }
3030         }
3031
3032         if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3033                 seq_puts(m, "\tVBT: DRRS_type: Static");
3034         else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3035                 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3036         else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3037                 seq_puts(m, "\tVBT: DRRS_type: None");
3038         else
3039                 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3040
3041         seq_puts(m, "\n\n");
3042
3043         if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3044                 struct intel_panel *panel;
3045
3046                 mutex_lock(&drrs->mutex);
3047                 /* DRRS Supported */
3048                 seq_puts(m, "\tDRRS Supported: Yes\n");
3049
3050                 /* disable_drrs() will make drrs->dp NULL */
3051                 if (!drrs->dp) {
3052                         seq_puts(m, "Idleness DRRS: Disabled");
3053                         mutex_unlock(&drrs->mutex);
3054                         return;
3055                 }
3056
3057                 panel = &drrs->dp->attached_connector->panel;
3058                 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3059                                         drrs->busy_frontbuffer_bits);
3060
3061                 seq_puts(m, "\n\t\t");
3062                 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3063                         seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3064                         vrefresh = panel->fixed_mode->vrefresh;
3065                 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3066                         seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3067                         vrefresh = panel->downclock_mode->vrefresh;
3068                 } else {
3069                         seq_printf(m, "DRRS_State: Unknown(%d)\n",
3070                                                 drrs->refresh_rate_type);
3071                         mutex_unlock(&drrs->mutex);
3072                         return;
3073                 }
3074                 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3075
3076                 seq_puts(m, "\n\t\t");
3077                 mutex_unlock(&drrs->mutex);
3078         } else {
3079                 /* DRRS not supported. Print the VBT parameter*/
3080                 seq_puts(m, "\tDRRS Supported : No");
3081         }
3082         seq_puts(m, "\n");
3083 }
3084
3085 static int i915_drrs_status(struct seq_file *m, void *unused)
3086 {
3087         struct drm_info_node *node = m->private;
3088         struct drm_device *dev = node->minor->dev;
3089         struct intel_crtc *intel_crtc;
3090         int active_crtc_cnt = 0;
3091
3092         for_each_intel_crtc(dev, intel_crtc) {
3093                 drm_modeset_lock(&intel_crtc->base.mutex, NULL);
3094
3095                 if (intel_crtc->base.state->active) {
3096                         active_crtc_cnt++;
3097                         seq_printf(m, "\nCRTC %d:  ", active_crtc_cnt);
3098
3099                         drrs_status_per_crtc(m, dev, intel_crtc);
3100                 }
3101
3102                 drm_modeset_unlock(&intel_crtc->base.mutex);
3103         }
3104
3105         if (!active_crtc_cnt)
3106                 seq_puts(m, "No active crtc found\n");
3107
3108         return 0;
3109 }
3110
3111 struct pipe_crc_info {
3112         const char *name;
3113         struct drm_device *dev;
3114         enum pipe pipe;
3115 };
3116
3117 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3118 {
3119         struct drm_info_node *node = (struct drm_info_node *) m->private;
3120         struct drm_device *dev = node->minor->dev;
3121         struct drm_encoder *encoder;
3122         struct intel_encoder *intel_encoder;
3123         struct intel_digital_port *intel_dig_port;
3124         drm_modeset_lock_all(dev);
3125         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3126                 intel_encoder = to_intel_encoder(encoder);
3127                 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
3128                         continue;
3129                 intel_dig_port = enc_to_dig_port(encoder);
3130                 if (!intel_dig_port->dp.can_mst)
3131                         continue;
3132
3133                 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3134         }
3135         drm_modeset_unlock_all(dev);
3136         return 0;
3137 }
3138
3139 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3140 {
3141         struct pipe_crc_info *info = inode->i_private;
3142         struct drm_i915_private *dev_priv = info->dev->dev_private;
3143         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3144
3145         if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3146                 return -ENODEV;
3147
3148         spin_lock_irq(&pipe_crc->lock);
3149
3150         if (pipe_crc->opened) {
3151                 spin_unlock_irq(&pipe_crc->lock);
3152                 return -EBUSY; /* already open */
3153         }
3154
3155         pipe_crc->opened = true;
3156         filep->private_data = inode->i_private;
3157
3158         spin_unlock_irq(&pipe_crc->lock);
3159
3160         return 0;
3161 }
3162
3163 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3164 {
3165         struct pipe_crc_info *info = inode->i_private;
3166         struct drm_i915_private *dev_priv = info->dev->dev_private;
3167         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3168
3169         spin_lock_irq(&pipe_crc->lock);
3170         pipe_crc->opened = false;
3171         spin_unlock_irq(&pipe_crc->lock);
3172
3173         return 0;
3174 }
3175
3176 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3177 #define PIPE_CRC_LINE_LEN       (6 * 8 + 5 + 1)
3178 /* account for \'0' */
3179 #define PIPE_CRC_BUFFER_LEN     (PIPE_CRC_LINE_LEN + 1)
3180
3181 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
3182 {
3183         assert_spin_locked(&pipe_crc->lock);
3184         return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3185                         INTEL_PIPE_CRC_ENTRIES_NR);
3186 }
3187
3188 static ssize_t
3189 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3190                    loff_t *pos)
3191 {
3192         struct pipe_crc_info *info = filep->private_data;
3193         struct drm_device *dev = info->dev;
3194         struct drm_i915_private *dev_priv = dev->dev_private;
3195         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3196         char buf[PIPE_CRC_BUFFER_LEN];
3197         int n_entries;
3198         ssize_t bytes_read;
3199
3200         /*
3201          * Don't allow user space to provide buffers not big enough to hold
3202          * a line of data.
3203          */
3204         if (count < PIPE_CRC_LINE_LEN)
3205                 return -EINVAL;
3206
3207         if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
3208                 return 0;
3209
3210         /* nothing to read */
3211         spin_lock_irq(&pipe_crc->lock);
3212         while (pipe_crc_data_count(pipe_crc) == 0) {
3213                 int ret;
3214
3215                 if (filep->f_flags & O_NONBLOCK) {
3216                         spin_unlock_irq(&pipe_crc->lock);
3217                         return -EAGAIN;
3218                 }
3219
3220                 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3221                                 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3222                 if (ret) {
3223                         spin_unlock_irq(&pipe_crc->lock);
3224                         return ret;
3225                 }
3226         }
3227
3228         /* We now have one or more entries to read */
3229         n_entries = count / PIPE_CRC_LINE_LEN;
3230
3231         bytes_read = 0;
3232         while (n_entries > 0) {
3233                 struct intel_pipe_crc_entry *entry =
3234                         &pipe_crc->entries[pipe_crc->tail];
3235                 int ret;
3236
3237                 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3238                              INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3239                         break;
3240
3241                 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3242                 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3243
3244                 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3245                                        "%8u %8x %8x %8x %8x %8x\n",
3246                                        entry->frame, entry->crc[0],
3247                                        entry->crc[1], entry->crc[2],
3248                                        entry->crc[3], entry->crc[4]);
3249
3250                 spin_unlock_irq(&pipe_crc->lock);
3251
3252                 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
3253                 if (ret == PIPE_CRC_LINE_LEN)
3254                         return -EFAULT;
3255
3256                 user_buf += PIPE_CRC_LINE_LEN;
3257                 n_entries--;
3258
3259                 spin_lock_irq(&pipe_crc->lock);
3260         }
3261
3262         spin_unlock_irq(&pipe_crc->lock);
3263
3264         return bytes_read;
3265 }
3266
3267 static const struct file_operations i915_pipe_crc_fops = {
3268         .owner = THIS_MODULE,
3269         .open = i915_pipe_crc_open,
3270         .read = i915_pipe_crc_read,
3271         .release = i915_pipe_crc_release,
3272 };
3273
3274 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3275         {
3276                 .name = "i915_pipe_A_crc",
3277                 .pipe = PIPE_A,
3278         },
3279         {
3280                 .name = "i915_pipe_B_crc",
3281                 .pipe = PIPE_B,
3282         },
3283         {
3284                 .name = "i915_pipe_C_crc",
3285                 .pipe = PIPE_C,
3286         },
3287 };
3288
3289 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3290                                 enum pipe pipe)
3291 {
3292         struct drm_device *dev = minor->dev;
3293         struct dentry *ent;
3294         struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3295
3296         info->dev = dev;
3297         ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3298                                   &i915_pipe_crc_fops);
3299         if (!ent)
3300                 return -ENOMEM;
3301
3302         return drm_add_fake_info_node(minor, ent, info);
3303 }
3304
3305 static const char * const pipe_crc_sources[] = {
3306         "none",
3307         "plane1",
3308         "plane2",
3309         "pf",
3310         "pipe",
3311         "TV",
3312         "DP-B",
3313         "DP-C",
3314         "DP-D",
3315         "auto",
3316 };
3317
3318 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3319 {
3320         BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3321         return pipe_crc_sources[source];
3322 }
3323
3324 static int display_crc_ctl_show(struct seq_file *m, void *data)
3325 {
3326         struct drm_device *dev = m->private;
3327         struct drm_i915_private *dev_priv = dev->dev_private;
3328         int i;
3329
3330         for (i = 0; i < I915_MAX_PIPES; i++)
3331                 seq_printf(m, "%c %s\n", pipe_name(i),
3332                            pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3333
3334         return 0;
3335 }
3336
3337 static int display_crc_ctl_open(struct inode *inode, struct file *file)
3338 {
3339         struct drm_device *dev = inode->i_private;
3340
3341         return single_open(file, display_crc_ctl_show, dev);
3342 }
3343
3344 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3345                                  uint32_t *val)
3346 {
3347         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3348                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3349
3350         switch (*source) {
3351         case INTEL_PIPE_CRC_SOURCE_PIPE:
3352                 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3353                 break;
3354         case INTEL_PIPE_CRC_SOURCE_NONE:
3355                 *val = 0;
3356                 break;
3357         default:
3358                 return -EINVAL;
3359         }
3360
3361         return 0;
3362 }
3363
3364 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3365                                      enum intel_pipe_crc_source *source)
3366 {
3367         struct intel_encoder *encoder;
3368         struct intel_crtc *crtc;
3369         struct intel_digital_port *dig_port;
3370         int ret = 0;
3371
3372         *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3373
3374         drm_modeset_lock_all(dev);
3375         for_each_intel_encoder(dev, encoder) {
3376                 if (!encoder->base.crtc)
3377                         continue;
3378
3379                 crtc = to_intel_crtc(encoder->base.crtc);
3380
3381                 if (crtc->pipe != pipe)
3382                         continue;
3383
3384                 switch (encoder->type) {
3385                 case INTEL_OUTPUT_TVOUT:
3386                         *source = INTEL_PIPE_CRC_SOURCE_TV;
3387                         break;
3388                 case INTEL_OUTPUT_DISPLAYPORT:
3389                 case INTEL_OUTPUT_EDP:
3390                         dig_port = enc_to_dig_port(&encoder->base);
3391                         switch (dig_port->port) {
3392                         case PORT_B:
3393                                 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3394                                 break;
3395                         case PORT_C:
3396                                 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3397                                 break;
3398                         case PORT_D:
3399                                 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3400                                 break;
3401                         default:
3402                                 WARN(1, "nonexisting DP port %c\n",
3403                                      port_name(dig_port->port));
3404                                 break;
3405                         }
3406                         break;
3407                 default:
3408                         break;
3409                 }
3410         }
3411         drm_modeset_unlock_all(dev);
3412
3413         return ret;
3414 }
3415
3416 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3417                                 enum pipe pipe,
3418                                 enum intel_pipe_crc_source *source,
3419                                 uint32_t *val)
3420 {
3421         struct drm_i915_private *dev_priv = dev->dev_private;
3422         bool need_stable_symbols = false;
3423
3424         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3425                 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3426                 if (ret)
3427                         return ret;
3428         }
3429
3430         switch (*source) {
3431         case INTEL_PIPE_CRC_SOURCE_PIPE:
3432                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3433                 break;
3434         case INTEL_PIPE_CRC_SOURCE_DP_B:
3435                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3436                 need_stable_symbols = true;
3437                 break;
3438         case INTEL_PIPE_CRC_SOURCE_DP_C:
3439                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3440                 need_stable_symbols = true;
3441                 break;
3442         case INTEL_PIPE_CRC_SOURCE_DP_D:
3443                 if (!IS_CHERRYVIEW(dev))
3444                         return -EINVAL;
3445                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3446                 need_stable_symbols = true;
3447                 break;
3448         case INTEL_PIPE_CRC_SOURCE_NONE:
3449                 *val = 0;
3450                 break;
3451         default:
3452                 return -EINVAL;
3453         }
3454
3455         /*
3456          * When the pipe CRC tap point is after the transcoders we need
3457          * to tweak symbol-level features to produce a deterministic series of
3458          * symbols for a given frame. We need to reset those features only once
3459          * a frame (instead of every nth symbol):
3460          *   - DC-balance: used to ensure a better clock recovery from the data
3461          *     link (SDVO)
3462          *   - DisplayPort scrambling: used for EMI reduction
3463          */
3464         if (need_stable_symbols) {
3465                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3466
3467                 tmp |= DC_BALANCE_RESET_VLV;
3468                 switch (pipe) {
3469                 case PIPE_A:
3470                         tmp |= PIPE_A_SCRAMBLE_RESET;
3471                         break;
3472                 case PIPE_B:
3473                         tmp |= PIPE_B_SCRAMBLE_RESET;
3474                         break;
3475                 case PIPE_C:
3476                         tmp |= PIPE_C_SCRAMBLE_RESET;
3477                         break;
3478                 default:
3479                         return -EINVAL;
3480                 }
3481                 I915_WRITE(PORT_DFT2_G4X, tmp);
3482         }
3483
3484         return 0;
3485 }
3486
3487 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
3488                                  enum pipe pipe,
3489                                  enum intel_pipe_crc_source *source,
3490                                  uint32_t *val)
3491 {
3492         struct drm_i915_private *dev_priv = dev->dev_private;
3493         bool need_stable_symbols = false;
3494
3495         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3496                 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3497                 if (ret)
3498                         return ret;
3499         }
3500
3501         switch (*source) {
3502         case INTEL_PIPE_CRC_SOURCE_PIPE:
3503                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3504                 break;
3505         case INTEL_PIPE_CRC_SOURCE_TV:
3506                 if (!SUPPORTS_TV(dev))
3507                         return -EINVAL;
3508                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3509                 break;
3510         case INTEL_PIPE_CRC_SOURCE_DP_B:
3511                 if (!IS_G4X(dev))
3512                         return -EINVAL;
3513                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3514                 need_stable_symbols = true;
3515                 break;
3516         case INTEL_PIPE_CRC_SOURCE_DP_C:
3517                 if (!IS_G4X(dev))
3518                         return -EINVAL;
3519                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3520                 need_stable_symbols = true;
3521                 break;
3522         case INTEL_PIPE_CRC_SOURCE_DP_D:
3523                 if (!IS_G4X(dev))
3524                         return -EINVAL;
3525                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3526                 need_stable_symbols = true;
3527                 break;
3528         case INTEL_PIPE_CRC_SOURCE_NONE:
3529                 *val = 0;
3530                 break;
3531         default:
3532                 return -EINVAL;
3533         }
3534
3535         /*
3536          * When the pipe CRC tap point is after the transcoders we need
3537          * to tweak symbol-level features to produce a deterministic series of
3538          * symbols for a given frame. We need to reset those features only once
3539          * a frame (instead of every nth symbol):
3540          *   - DC-balance: used to ensure a better clock recovery from the data
3541          *     link (SDVO)
3542          *   - DisplayPort scrambling: used for EMI reduction
3543          */
3544         if (need_stable_symbols) {
3545                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3546
3547                 WARN_ON(!IS_G4X(dev));
3548
3549                 I915_WRITE(PORT_DFT_I9XX,
3550                            I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3551
3552                 if (pipe == PIPE_A)
3553                         tmp |= PIPE_A_SCRAMBLE_RESET;
3554                 else
3555                         tmp |= PIPE_B_SCRAMBLE_RESET;
3556
3557                 I915_WRITE(PORT_DFT2_G4X, tmp);
3558         }
3559
3560         return 0;
3561 }
3562
3563 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3564                                          enum pipe pipe)
3565 {
3566         struct drm_i915_private *dev_priv = dev->dev_private;
3567         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3568
3569         switch (pipe) {
3570         case PIPE_A:
3571                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3572                 break;
3573         case PIPE_B:
3574                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3575                 break;
3576         case PIPE_C:
3577                 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3578                 break;
3579         default:
3580                 return;
3581         }
3582         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3583                 tmp &= ~DC_BALANCE_RESET_VLV;
3584         I915_WRITE(PORT_DFT2_G4X, tmp);
3585
3586 }
3587
3588 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3589                                          enum pipe pipe)
3590 {
3591         struct drm_i915_private *dev_priv = dev->dev_private;
3592         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3593
3594         if (pipe == PIPE_A)
3595                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3596         else
3597                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3598         I915_WRITE(PORT_DFT2_G4X, tmp);
3599
3600         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3601                 I915_WRITE(PORT_DFT_I9XX,
3602                            I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3603         }
3604 }
3605
3606 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3607                                 uint32_t *val)
3608 {
3609         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3610                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3611
3612         switch (*source) {
3613         case INTEL_PIPE_CRC_SOURCE_PLANE1:
3614                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3615                 break;
3616         case INTEL_PIPE_CRC_SOURCE_PLANE2:
3617                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3618                 break;
3619         case INTEL_PIPE_CRC_SOURCE_PIPE:
3620                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3621                 break;
3622         case INTEL_PIPE_CRC_SOURCE_NONE:
3623                 *val = 0;
3624                 break;
3625         default:
3626                 return -EINVAL;
3627         }
3628
3629         return 0;
3630 }
3631
3632 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3633 {
3634         struct drm_i915_private *dev_priv = dev->dev_private;
3635         struct intel_crtc *crtc =
3636                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3637         struct intel_crtc_state *pipe_config;
3638
3639         drm_modeset_lock_all(dev);
3640         pipe_config = to_intel_crtc_state(crtc->base.state);
3641
3642         /*
3643          * If we use the eDP transcoder we need to make sure that we don't
3644          * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3645          * relevant on hsw with pipe A when using the always-on power well
3646          * routing.
3647          */
3648         if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
3649             !pipe_config->pch_pfit.enabled) {
3650                 bool active = pipe_config->base.active;
3651
3652                 if (active) {
3653                         intel_crtc_control(&crtc->base, false);
3654                         pipe_config = to_intel_crtc_state(crtc->base.state);
3655                 }
3656
3657                 pipe_config->pch_pfit.force_thru = true;
3658
3659                 intel_display_power_get(dev_priv,
3660                                         POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3661
3662                 if (active)
3663                         intel_crtc_control(&crtc->base, true);
3664         }
3665         drm_modeset_unlock_all(dev);
3666 }
3667
3668 static void hsw_undo_trans_edp_pipe_A_crc_wa(struct drm_device *dev)
3669 {
3670         struct drm_i915_private *dev_priv = dev->dev_private;
3671         struct intel_crtc *crtc =
3672                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3673         struct intel_crtc_state *pipe_config;
3674
3675         drm_modeset_lock_all(dev);
3676         /*
3677          * If we use the eDP transcoder we need to make sure that we don't
3678          * bypass the pfit, since otherwise the pipe CRC source won't work. Only
3679          * relevant on hsw with pipe A when using the always-on power well
3680          * routing.
3681          */
3682         pipe_config = to_intel_crtc_state(crtc->base.state);
3683         if (pipe_config->pch_pfit.force_thru) {
3684                 bool active = pipe_config->base.active;
3685
3686                 if (active) {
3687                         intel_crtc_control(&crtc->base, false);
3688                         pipe_config = to_intel_crtc_state(crtc->base.state);
3689                 }
3690
3691                 pipe_config->pch_pfit.force_thru = false;
3692
3693                 intel_display_power_put(dev_priv,
3694                                         POWER_DOMAIN_PIPE_PANEL_FITTER(PIPE_A));
3695
3696                 if (active)
3697                         intel_crtc_control(&crtc->base, true);
3698         }
3699         drm_modeset_unlock_all(dev);
3700 }
3701
3702 static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3703                                 enum pipe pipe,
3704                                 enum intel_pipe_crc_source *source,
3705                                 uint32_t *val)
3706 {
3707         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3708                 *source = INTEL_PIPE_CRC_SOURCE_PF;
3709
3710         switch (*source) {
3711         case INTEL_PIPE_CRC_SOURCE_PLANE1:
3712                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3713                 break;
3714         case INTEL_PIPE_CRC_SOURCE_PLANE2:
3715                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3716                 break;
3717         case INTEL_PIPE_CRC_SOURCE_PF:
3718                 if (IS_HASWELL(dev) && pipe == PIPE_A)
3719                         hsw_trans_edp_pipe_A_crc_wa(dev);
3720
3721                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3722                 break;
3723         case INTEL_PIPE_CRC_SOURCE_NONE:
3724                 *val = 0;
3725                 break;
3726         default:
3727                 return -EINVAL;
3728         }
3729
3730         return 0;
3731 }
3732
3733 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
3734                                enum intel_pipe_crc_source source)
3735 {
3736         struct drm_i915_private *dev_priv = dev->dev_private;
3737         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
3738         struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
3739                                                                         pipe));
3740         u32 val = 0; /* shut up gcc */
3741         int ret;
3742
3743         if (pipe_crc->source == source)
3744                 return 0;
3745
3746         /* forbid changing the source without going back to 'none' */
3747         if (pipe_crc->source && source)
3748                 return -EINVAL;
3749
3750         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) {
3751                 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
3752                 return -EIO;
3753         }
3754
3755         if (IS_GEN2(dev))
3756                 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
3757         else if (INTEL_INFO(dev)->gen < 5)
3758                 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3759         else if (IS_VALLEYVIEW(dev))
3760                 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3761         else if (IS_GEN5(dev) || IS_GEN6(dev))
3762                 ret = ilk_pipe_crc_ctl_reg(&source, &val);
3763         else
3764                 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3765
3766         if (ret != 0)
3767                 return ret;
3768
3769         /* none -> real source transition */
3770         if (source) {
3771                 struct intel_pipe_crc_entry *entries;
3772
3773                 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
3774                                  pipe_name(pipe), pipe_crc_source_name(source));
3775
3776                 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
3777                                   sizeof(pipe_crc->entries[0]),
3778                                   GFP_KERNEL);
3779                 if (!entries)
3780                         return -ENOMEM;
3781
3782                 /*
3783                  * When IPS gets enabled, the pipe CRC changes. Since IPS gets
3784                  * enabled and disabled dynamically based on package C states,
3785                  * user space can't make reliable use of the CRCs, so let's just
3786                  * completely disable it.
3787                  */
3788                 hsw_disable_ips(crtc);
3789
3790                 spin_lock_irq(&pipe_crc->lock);
3791                 kfree(pipe_crc->entries);
3792                 pipe_crc->entries = entries;
3793                 pipe_crc->head = 0;
3794                 pipe_crc->tail = 0;
3795                 spin_unlock_irq(&pipe_crc->lock);
3796         }
3797
3798         pipe_crc->source = source;
3799
3800         I915_WRITE(PIPE_CRC_CTL(pipe), val);
3801         POSTING_READ(PIPE_CRC_CTL(pipe));
3802
3803         /* real source -> none transition */
3804         if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
3805                 struct intel_pipe_crc_entry *entries;
3806                 struct intel_crtc *crtc =
3807                         to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
3808
3809                 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
3810                                  pipe_name(pipe));
3811
3812                 drm_modeset_lock(&crtc->base.mutex, NULL);
3813                 if (crtc->base.state->active)
3814                         intel_wait_for_vblank(dev, pipe);
3815                 drm_modeset_unlock(&crtc->base.mutex);
3816
3817                 spin_lock_irq(&pipe_crc->lock);
3818                 entries = pipe_crc->entries;
3819                 pipe_crc->entries = NULL;
3820                 pipe_crc->head = 0;
3821                 pipe_crc->tail = 0;
3822                 spin_unlock_irq(&pipe_crc->lock);
3823
3824                 kfree(entries);
3825
3826                 if (IS_G4X(dev))
3827                         g4x_undo_pipe_scramble_reset(dev, pipe);
3828                 else if (IS_VALLEYVIEW(dev))
3829                         vlv_undo_pipe_scramble_reset(dev, pipe);
3830                 else if (IS_HASWELL(dev) && pipe == PIPE_A)
3831                         hsw_undo_trans_edp_pipe_A_crc_wa(dev);
3832
3833                 hsw_enable_ips(crtc);
3834         }
3835
3836         return 0;
3837 }
3838
3839 /*
3840  * Parse pipe CRC command strings:
3841  *   command: wsp* object wsp+ name wsp+ source wsp*
3842  *   object: 'pipe'
3843  *   name: (A | B | C)
3844  *   source: (none | plane1 | plane2 | pf)
3845  *   wsp: (#0x20 | #0x9 | #0xA)+
3846  *
3847  * eg.:
3848  *  "pipe A plane1"  ->  Start CRC computations on plane1 of pipe A
3849  *  "pipe A none"    ->  Stop CRC
3850  */
3851 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
3852 {
3853         int n_words = 0;
3854
3855         while (*buf) {
3856                 char *end;
3857
3858                 /* skip leading white space */
3859                 buf = skip_spaces(buf);
3860                 if (!*buf)
3861                         break;  /* end of buffer */
3862
3863                 /* find end of word */
3864                 for (end = buf; *end && !isspace(*end); end++)
3865                         ;
3866
3867                 if (n_words == max_words) {
3868                         DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
3869                                          max_words);
3870                         return -EINVAL; /* ran out of words[] before bytes */
3871                 }
3872
3873                 if (*end)
3874                         *end++ = '\0';
3875                 words[n_words++] = buf;
3876                 buf = end;
3877         }
3878
3879         return n_words;
3880 }
3881
3882 enum intel_pipe_crc_object {
3883         PIPE_CRC_OBJECT_PIPE,
3884 };
3885
3886 static const char * const pipe_crc_objects[] = {
3887         "pipe",
3888 };
3889
3890 static int
3891 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
3892 {
3893         int i;
3894
3895         for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
3896                 if (!strcmp(buf, pipe_crc_objects[i])) {
3897                         *o = i;
3898                         return 0;
3899                     }
3900
3901         return -EINVAL;
3902 }
3903
3904 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
3905 {
3906         const char name = buf[0];
3907
3908         if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
3909                 return -EINVAL;
3910
3911         *pipe = name - 'A';
3912
3913         return 0;
3914 }
3915
3916 static int
3917 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
3918 {
3919         int i;
3920
3921         for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
3922                 if (!strcmp(buf, pipe_crc_sources[i])) {
3923                         *s = i;
3924                         return 0;
3925                     }
3926
3927         return -EINVAL;
3928 }
3929
3930 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
3931 {
3932 #define N_WORDS 3
3933         int n_words;
3934         char *words[N_WORDS];
3935         enum pipe pipe;
3936         enum intel_pipe_crc_object object;
3937         enum intel_pipe_crc_source source;
3938
3939         n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
3940         if (n_words != N_WORDS) {
3941                 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
3942                                  N_WORDS);
3943                 return -EINVAL;
3944         }
3945
3946         if (display_crc_ctl_parse_object(words[0], &object) < 0) {
3947                 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
3948                 return -EINVAL;
3949         }
3950
3951         if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
3952                 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
3953                 return -EINVAL;
3954         }
3955
3956         if (display_crc_ctl_parse_source(words[2], &source) < 0) {
3957                 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
3958                 return -EINVAL;
3959         }
3960
3961         return pipe_crc_set_source(dev, pipe, source);
3962 }
3963
3964 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
3965                                      size_t len, loff_t *offp)
3966 {
3967         struct seq_file *m = file->private_data;
3968         struct drm_device *dev = m->private;
3969         char *tmpbuf;
3970         int ret;
3971
3972         if (len == 0)
3973                 return 0;
3974
3975         if (len > PAGE_SIZE - 1) {
3976                 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
3977                                  PAGE_SIZE);
3978                 return -E2BIG;
3979         }
3980
3981         tmpbuf = kmalloc(len + 1, GFP_KERNEL);
3982         if (!tmpbuf)
3983                 return -ENOMEM;
3984
3985         if (copy_from_user(tmpbuf, ubuf, len)) {
3986                 ret = -EFAULT;
3987                 goto out;
3988         }
3989         tmpbuf[len] = '\0';
3990
3991         ret = display_crc_ctl_parse(dev, tmpbuf, len);
3992
3993 out:
3994         kfree(tmpbuf);
3995         if (ret < 0)
3996                 return ret;
3997
3998         *offp += len;
3999         return len;
4000 }
4001
4002 static const struct file_operations i915_display_crc_ctl_fops = {
4003         .owner = THIS_MODULE,
4004         .open = display_crc_ctl_open,
4005         .read = seq_read,
4006         .llseek = seq_lseek,
4007         .release = single_release,
4008         .write = display_crc_ctl_write
4009 };
4010
4011 static ssize_t i915_displayport_test_active_write(struct file *file,
4012                                             const char __user *ubuf,
4013                                             size_t len, loff_t *offp)
4014 {
4015         char *input_buffer;
4016         int status = 0;
4017         struct seq_file *m;
4018         struct drm_device *dev;
4019         struct drm_connector *connector;
4020         struct list_head *connector_list;
4021         struct intel_dp *intel_dp;
4022         int val = 0;
4023
4024         m = file->private_data;
4025         if (!m) {
4026                 status = -ENODEV;
4027                 return status;
4028         }
4029         dev = m->private;
4030
4031         if (!dev) {
4032                 status = -ENODEV;
4033                 return status;
4034         }
4035         connector_list = &dev->mode_config.connector_list;
4036
4037         if (len == 0)
4038                 return 0;
4039
4040         input_buffer = kmalloc(len + 1, GFP_KERNEL);
4041         if (!input_buffer)
4042                 return -ENOMEM;
4043
4044         if (copy_from_user(input_buffer, ubuf, len)) {
4045                 status = -EFAULT;
4046                 goto out;
4047         }
4048
4049         input_buffer[len] = '\0';
4050         DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4051
4052         list_for_each_entry(connector, connector_list, head) {
4053
4054                 if (connector->connector_type !=
4055                     DRM_MODE_CONNECTOR_DisplayPort)
4056                         continue;
4057
4058                 if (connector->connector_type ==
4059                     DRM_MODE_CONNECTOR_DisplayPort &&
4060                     connector->status == connector_status_connected &&
4061                     connector->encoder != NULL) {
4062                         intel_dp = enc_to_intel_dp(connector->encoder);
4063                         status = kstrtoint(input_buffer, 10, &val);
4064                         if (status < 0)
4065                                 goto out;
4066                         DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4067                         /* To prevent erroneous activation of the compliance
4068                          * testing code, only accept an actual value of 1 here
4069                          */
4070                         if (val == 1)
4071                                 intel_dp->compliance_test_active = 1;
4072                         else
4073                                 intel_dp->compliance_test_active = 0;
4074                 }
4075         }
4076 out:
4077         kfree(input_buffer);
4078         if (status < 0)
4079                 return status;
4080
4081         *offp += len;
4082         return len;
4083 }
4084
4085 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4086 {
4087         struct drm_device *dev = m->private;
4088         struct drm_connector *connector;
4089         struct list_head *connector_list = &dev->mode_config.connector_list;
4090         struct intel_dp *intel_dp;
4091
4092         if (!dev)
4093                 return -ENODEV;
4094
4095         list_for_each_entry(connector, connector_list, head) {
4096
4097                 if (connector->connector_type !=
4098                     DRM_MODE_CONNECTOR_DisplayPort)
4099                         continue;
4100
4101                 if (connector->status == connector_status_connected &&
4102                     connector->encoder != NULL) {
4103                         intel_dp = enc_to_intel_dp(connector->encoder);
4104                         if (intel_dp->compliance_test_active)
4105                                 seq_puts(m, "1");
4106                         else
4107                                 seq_puts(m, "0");
4108                 } else
4109                         seq_puts(m, "0");
4110         }
4111
4112         return 0;
4113 }
4114
4115 static int i915_displayport_test_active_open(struct inode *inode,
4116                                        struct file *file)
4117 {
4118         struct drm_device *dev = inode->i_private;
4119
4120         return single_open(file, i915_displayport_test_active_show, dev);
4121 }
4122
4123 static const struct file_operations i915_displayport_test_active_fops = {
4124         .owner = THIS_MODULE,
4125         .open = i915_displayport_test_active_open,
4126         .read = seq_read,
4127         .llseek = seq_lseek,
4128         .release = single_release,
4129         .write = i915_displayport_test_active_write
4130 };
4131
4132 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4133 {
4134         struct drm_device *dev = m->private;
4135         struct drm_connector *connector;
4136         struct list_head *connector_list = &dev->mode_config.connector_list;
4137         struct intel_dp *intel_dp;
4138
4139         if (!dev)
4140                 return -ENODEV;
4141
4142         list_for_each_entry(connector, connector_list, head) {
4143
4144                 if (connector->connector_type !=
4145                     DRM_MODE_CONNECTOR_DisplayPort)
4146                         continue;
4147
4148                 if (connector->status == connector_status_connected &&
4149                     connector->encoder != NULL) {
4150                         intel_dp = enc_to_intel_dp(connector->encoder);
4151                         seq_printf(m, "%lx", intel_dp->compliance_test_data);
4152                 } else
4153                         seq_puts(m, "0");
4154         }
4155
4156         return 0;
4157 }
4158 static int i915_displayport_test_data_open(struct inode *inode,
4159                                        struct file *file)
4160 {
4161         struct drm_device *dev = inode->i_private;
4162
4163         return single_open(file, i915_displayport_test_data_show, dev);
4164 }
4165
4166 static const struct file_operations i915_displayport_test_data_fops = {
4167         .owner = THIS_MODULE,
4168         .open = i915_displayport_test_data_open,
4169         .read = seq_read,
4170         .llseek = seq_lseek,
4171         .release = single_release
4172 };
4173
4174 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4175 {
4176         struct drm_device *dev = m->private;
4177         struct drm_connector *connector;
4178         struct list_head *connector_list = &dev->mode_config.connector_list;
4179         struct intel_dp *intel_dp;
4180
4181         if (!dev)
4182                 return -ENODEV;
4183
4184         list_for_each_entry(connector, connector_list, head) {
4185
4186                 if (connector->connector_type !=
4187                     DRM_MODE_CONNECTOR_DisplayPort)
4188                         continue;
4189
4190                 if (connector->status == connector_status_connected &&
4191                     connector->encoder != NULL) {
4192                         intel_dp = enc_to_intel_dp(connector->encoder);
4193                         seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4194                 } else
4195                         seq_puts(m, "0");
4196         }
4197
4198         return 0;
4199 }
4200
4201 static int i915_displayport_test_type_open(struct inode *inode,
4202                                        struct file *file)
4203 {
4204         struct drm_device *dev = inode->i_private;
4205
4206         return single_open(file, i915_displayport_test_type_show, dev);
4207 }
4208
4209 static const struct file_operations i915_displayport_test_type_fops = {
4210         .owner = THIS_MODULE,
4211         .open = i915_displayport_test_type_open,
4212         .read = seq_read,
4213         .llseek = seq_lseek,
4214         .release = single_release
4215 };
4216
4217 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
4218 {
4219         struct drm_device *dev = m->private;
4220         int level;
4221         int num_levels;
4222
4223         if (IS_CHERRYVIEW(dev))
4224                 num_levels = 3;
4225         else if (IS_VALLEYVIEW(dev))
4226                 num_levels = 1;
4227         else
4228                 num_levels = ilk_wm_max_level(dev) + 1;
4229
4230         drm_modeset_lock_all(dev);
4231
4232         for (level = 0; level < num_levels; level++) {
4233                 unsigned int latency = wm[level];
4234
4235                 /*
4236                  * - WM1+ latency values in 0.5us units
4237                  * - latencies are in us on gen9/vlv/chv
4238                  */
4239                 if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev))
4240                         latency *= 10;
4241                 else if (level > 0)
4242                         latency *= 5;
4243
4244                 seq_printf(m, "WM%d %u (%u.%u usec)\n",
4245                            level, wm[level], latency / 10, latency % 10);
4246         }
4247
4248         drm_modeset_unlock_all(dev);
4249 }
4250
4251 static int pri_wm_latency_show(struct seq_file *m, void *data)
4252 {
4253         struct drm_device *dev = m->private;
4254         struct drm_i915_private *dev_priv = dev->dev_private;
4255         const uint16_t *latencies;
4256
4257         if (INTEL_INFO(dev)->gen >= 9)
4258                 latencies = dev_priv->wm.skl_latency;
4259         else
4260                 latencies = to_i915(dev)->wm.pri_latency;
4261
4262         wm_latency_show(m, latencies);
4263
4264         return 0;
4265 }
4266
4267 static int spr_wm_latency_show(struct seq_file *m, void *data)
4268 {
4269         struct drm_device *dev = m->private;
4270         struct drm_i915_private *dev_priv = dev->dev_private;
4271         const uint16_t *latencies;
4272
4273         if (INTEL_INFO(dev)->gen >= 9)
4274                 latencies = dev_priv->wm.skl_latency;
4275         else
4276                 latencies = to_i915(dev)->wm.spr_latency;
4277
4278         wm_latency_show(m, latencies);
4279
4280         return 0;
4281 }
4282
4283 static int cur_wm_latency_show(struct seq_file *m, void *data)
4284 {
4285         struct drm_device *dev = m->private;
4286         struct drm_i915_private *dev_priv = dev->dev_private;
4287         const uint16_t *latencies;
4288
4289         if (INTEL_INFO(dev)->gen >= 9)
4290                 latencies = dev_priv->wm.skl_latency;
4291         else
4292                 latencies = to_i915(dev)->wm.cur_latency;
4293
4294         wm_latency_show(m, latencies);
4295
4296         return 0;
4297 }
4298
4299 static int pri_wm_latency_open(struct inode *inode, struct file *file)
4300 {
4301         struct drm_device *dev = inode->i_private;
4302
4303         if (INTEL_INFO(dev)->gen < 5)
4304                 return -ENODEV;
4305
4306         return single_open(file, pri_wm_latency_show, dev);
4307 }
4308
4309 static int spr_wm_latency_open(struct inode *inode, struct file *file)
4310 {
4311         struct drm_device *dev = inode->i_private;
4312
4313         if (HAS_GMCH_DISPLAY(dev))
4314                 return -ENODEV;
4315
4316         return single_open(file, spr_wm_latency_show, dev);
4317 }
4318
4319 static int cur_wm_latency_open(struct inode *inode, struct file *file)
4320 {
4321         struct drm_device *dev = inode->i_private;
4322
4323         if (HAS_GMCH_DISPLAY(dev))
4324                 return -ENODEV;
4325
4326         return single_open(file, cur_wm_latency_show, dev);
4327 }
4328
4329 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
4330                                 size_t len, loff_t *offp, uint16_t wm[8])
4331 {
4332         struct seq_file *m = file->private_data;
4333         struct drm_device *dev = m->private;
4334         uint16_t new[8] = { 0 };
4335         int num_levels;
4336         int level;
4337         int ret;
4338         char tmp[32];
4339
4340         if (IS_CHERRYVIEW(dev))
4341                 num_levels = 3;
4342         else if (IS_VALLEYVIEW(dev))
4343                 num_levels = 1;
4344         else
4345                 num_levels = ilk_wm_max_level(dev) + 1;
4346
4347         if (len >= sizeof(tmp))
4348                 return -EINVAL;
4349
4350         if (copy_from_user(tmp, ubuf, len))
4351                 return -EFAULT;
4352
4353         tmp[len] = '\0';
4354
4355         ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4356                      &new[0], &new[1], &new[2], &new[3],
4357                      &new[4], &new[5], &new[6], &new[7]);
4358         if (ret != num_levels)
4359                 return -EINVAL;
4360
4361         drm_modeset_lock_all(dev);
4362
4363         for (level = 0; level < num_levels; level++)
4364                 wm[level] = new[level];
4365
4366         drm_modeset_unlock_all(dev);
4367
4368         return len;
4369 }
4370
4371
4372 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4373                                     size_t len, loff_t *offp)
4374 {
4375         struct seq_file *m = file->private_data;
4376         struct drm_device *dev = m->private;
4377         struct drm_i915_private *dev_priv = dev->dev_private;
4378         uint16_t *latencies;
4379
4380         if (INTEL_INFO(dev)->gen >= 9)
4381                 latencies = dev_priv->wm.skl_latency;
4382         else
4383                 latencies = to_i915(dev)->wm.pri_latency;
4384
4385         return wm_latency_write(file, ubuf, len, offp, latencies);
4386 }
4387
4388 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4389                                     size_t len, loff_t *offp)
4390 {
4391         struct seq_file *m = file->private_data;
4392         struct drm_device *dev = m->private;
4393         struct drm_i915_private *dev_priv = dev->dev_private;
4394         uint16_t *latencies;
4395
4396         if (INTEL_INFO(dev)->gen >= 9)
4397                 latencies = dev_priv->wm.skl_latency;
4398         else
4399                 latencies = to_i915(dev)->wm.spr_latency;
4400
4401         return wm_latency_write(file, ubuf, len, offp, latencies);
4402 }
4403
4404 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4405                                     size_t len, loff_t *offp)
4406 {
4407         struct seq_file *m = file->private_data;
4408         struct drm_device *dev = m->private;
4409         struct drm_i915_private *dev_priv = dev->dev_private;
4410         uint16_t *latencies;
4411
4412         if (INTEL_INFO(dev)->gen >= 9)
4413                 latencies = dev_priv->wm.skl_latency;
4414         else
4415                 latencies = to_i915(dev)->wm.cur_latency;
4416
4417         return wm_latency_write(file, ubuf, len, offp, latencies);
4418 }
4419
4420 static const struct file_operations i915_pri_wm_latency_fops = {
4421         .owner = THIS_MODULE,
4422         .open = pri_wm_latency_open,
4423         .read = seq_read,
4424         .llseek = seq_lseek,
4425         .release = single_release,
4426         .write = pri_wm_latency_write
4427 };
4428
4429 static const struct file_operations i915_spr_wm_latency_fops = {
4430         .owner = THIS_MODULE,
4431         .open = spr_wm_latency_open,
4432         .read = seq_read,
4433         .llseek = seq_lseek,
4434         .release = single_release,
4435         .write = spr_wm_latency_write
4436 };
4437
4438 static const struct file_operations i915_cur_wm_latency_fops = {
4439         .owner = THIS_MODULE,
4440         .open = cur_wm_latency_open,
4441         .read = seq_read,
4442         .llseek = seq_lseek,
4443         .release = single_release,
4444         .write = cur_wm_latency_write
4445 };
4446
4447 static int
4448 i915_wedged_get(void *data, u64 *val)
4449 {
4450         struct drm_device *dev = data;
4451         struct drm_i915_private *dev_priv = dev->dev_private;
4452
4453         *val = atomic_read(&dev_priv->gpu_error.reset_counter);
4454
4455         return 0;
4456 }
4457
4458 static int
4459 i915_wedged_set(void *data, u64 val)
4460 {
4461         struct drm_device *dev = data;
4462         struct drm_i915_private *dev_priv = dev->dev_private;
4463
4464         /*
4465          * There is no safeguard against this debugfs entry colliding
4466          * with the hangcheck calling same i915_handle_error() in
4467          * parallel, causing an explosion. For now we assume that the
4468          * test harness is responsible enough not to inject gpu hangs
4469          * while it is writing to 'i915_wedged'
4470          */
4471
4472         if (i915_reset_in_progress(&dev_priv->gpu_error))
4473                 return -EAGAIN;
4474
4475         intel_runtime_pm_get(dev_priv);
4476
4477         i915_handle_error(dev, val,
4478                           "Manually setting wedged to %llu", val);
4479
4480         intel_runtime_pm_put(dev_priv);
4481
4482         return 0;
4483 }
4484
4485 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4486                         i915_wedged_get, i915_wedged_set,
4487                         "%llu\n");
4488
4489 static int
4490 i915_ring_stop_get(void *data, u64 *val)
4491 {
4492         struct drm_device *dev = data;
4493         struct drm_i915_private *dev_priv = dev->dev_private;
4494
4495         *val = dev_priv->gpu_error.stop_rings;
4496
4497         return 0;
4498 }
4499
4500 static int
4501 i915_ring_stop_set(void *data, u64 val)
4502 {
4503         struct drm_device *dev = data;
4504         struct drm_i915_private *dev_priv = dev->dev_private;
4505         int ret;
4506
4507         DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
4508
4509         ret = mutex_lock_interruptible(&dev->struct_mutex);
4510         if (ret)
4511                 return ret;
4512
4513         dev_priv->gpu_error.stop_rings = val;
4514         mutex_unlock(&dev->struct_mutex);
4515
4516         return 0;
4517 }
4518
4519 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
4520                         i915_ring_stop_get, i915_ring_stop_set,
4521                         "0x%08llx\n");
4522
4523 static int
4524 i915_ring_missed_irq_get(void *data, u64 *val)
4525 {
4526         struct drm_device *dev = data;
4527         struct drm_i915_private *dev_priv = dev->dev_private;
4528
4529         *val = dev_priv->gpu_error.missed_irq_rings;
4530         return 0;
4531 }
4532
4533 static int
4534 i915_ring_missed_irq_set(void *data, u64 val)
4535 {
4536         struct drm_device *dev = data;
4537         struct drm_i915_private *dev_priv = dev->dev_private;
4538         int ret;
4539
4540         /* Lock against concurrent debugfs callers */
4541         ret = mutex_lock_interruptible(&dev->struct_mutex);
4542         if (ret)
4543                 return ret;
4544         dev_priv->gpu_error.missed_irq_rings = val;
4545         mutex_unlock(&dev->struct_mutex);
4546
4547         return 0;
4548 }
4549
4550 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4551                         i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4552                         "0x%08llx\n");
4553
4554 static int
4555 i915_ring_test_irq_get(void *data, u64 *val)
4556 {
4557         struct drm_device *dev = data;
4558         struct drm_i915_private *dev_priv = dev->dev_private;
4559
4560         *val = dev_priv->gpu_error.test_irq_rings;
4561
4562         return 0;
4563 }
4564
4565 static int
4566 i915_ring_test_irq_set(void *data, u64 val)
4567 {
4568         struct drm_device *dev = data;
4569         struct drm_i915_private *dev_priv = dev->dev_private;
4570         int ret;
4571
4572         DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4573
4574         /* Lock against concurrent debugfs callers */
4575         ret = mutex_lock_interruptible(&dev->struct_mutex);
4576         if (ret)
4577                 return ret;
4578
4579         dev_priv->gpu_error.test_irq_rings = val;
4580         mutex_unlock(&dev->struct_mutex);
4581
4582         return 0;
4583 }
4584
4585 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4586                         i915_ring_test_irq_get, i915_ring_test_irq_set,
4587                         "0x%08llx\n");
4588
4589 #define DROP_UNBOUND 0x1
4590 #define DROP_BOUND 0x2
4591 #define DROP_RETIRE 0x4
4592 #define DROP_ACTIVE 0x8
4593 #define DROP_ALL (DROP_UNBOUND | \
4594                   DROP_BOUND | \
4595                   DROP_RETIRE | \
4596                   DROP_ACTIVE)
4597 static int
4598 i915_drop_caches_get(void *data, u64 *val)
4599 {
4600         *val = DROP_ALL;
4601
4602         return 0;
4603 }
4604
4605 static int
4606 i915_drop_caches_set(void *data, u64 val)
4607 {
4608         struct drm_device *dev = data;
4609         struct drm_i915_private *dev_priv = dev->dev_private;
4610         int ret;
4611
4612         DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4613
4614         /* No need to check and wait for gpu resets, only libdrm auto-restarts
4615          * on ioctls on -EAGAIN. */
4616         ret = mutex_lock_interruptible(&dev->struct_mutex);
4617         if (ret)
4618                 return ret;
4619
4620         if (val & DROP_ACTIVE) {
4621                 ret = i915_gpu_idle(dev);
4622                 if (ret)
4623                         goto unlock;
4624         }
4625
4626         if (val & (DROP_RETIRE | DROP_ACTIVE))
4627                 i915_gem_retire_requests(dev);
4628
4629         if (val & DROP_BOUND)
4630                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4631
4632         if (val & DROP_UNBOUND)
4633                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4634
4635 unlock:
4636         mutex_unlock(&dev->struct_mutex);
4637
4638         return ret;
4639 }
4640
4641 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4642                         i915_drop_caches_get, i915_drop_caches_set,
4643                         "0x%08llx\n");
4644
4645 static int
4646 i915_max_freq_get(void *data, u64 *val)
4647 {
4648         struct drm_device *dev = data;
4649         struct drm_i915_private *dev_priv = dev->dev_private;
4650         int ret;
4651
4652         if (INTEL_INFO(dev)->gen < 6)
4653                 return -ENODEV;
4654
4655         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4656
4657         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4658         if (ret)
4659                 return ret;
4660
4661         *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4662         mutex_unlock(&dev_priv->rps.hw_lock);
4663
4664         return 0;
4665 }
4666
4667 static int
4668 i915_max_freq_set(void *data, u64 val)
4669 {
4670         struct drm_device *dev = data;
4671         struct drm_i915_private *dev_priv = dev->dev_private;
4672         u32 hw_max, hw_min;
4673         int ret;
4674
4675         if (INTEL_INFO(dev)->gen < 6)
4676                 return -ENODEV;
4677
4678         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4679
4680         DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4681
4682         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4683         if (ret)
4684                 return ret;
4685
4686         /*
4687          * Turbo will still be enabled, but won't go above the set value.
4688          */
4689         val = intel_freq_opcode(dev_priv, val);
4690
4691         hw_max = dev_priv->rps.max_freq;
4692         hw_min = dev_priv->rps.min_freq;
4693
4694         if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4695                 mutex_unlock(&dev_priv->rps.hw_lock);
4696                 return -EINVAL;
4697         }
4698
4699         dev_priv->rps.max_freq_softlimit = val;
4700
4701         intel_set_rps(dev, val);
4702
4703         mutex_unlock(&dev_priv->rps.hw_lock);
4704
4705         return 0;
4706 }
4707
4708 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4709                         i915_max_freq_get, i915_max_freq_set,
4710                         "%llu\n");
4711
4712 static int
4713 i915_min_freq_get(void *data, u64 *val)
4714 {
4715         struct drm_device *dev = data;
4716         struct drm_i915_private *dev_priv = dev->dev_private;
4717         int ret;
4718
4719         if (INTEL_INFO(dev)->gen < 6)
4720                 return -ENODEV;
4721
4722         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4723
4724         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4725         if (ret)
4726                 return ret;
4727
4728         *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4729         mutex_unlock(&dev_priv->rps.hw_lock);
4730
4731         return 0;
4732 }
4733
4734 static int
4735 i915_min_freq_set(void *data, u64 val)
4736 {
4737         struct drm_device *dev = data;
4738         struct drm_i915_private *dev_priv = dev->dev_private;
4739         u32 hw_max, hw_min;
4740         int ret;
4741
4742         if (INTEL_INFO(dev)->gen < 6)
4743                 return -ENODEV;
4744
4745         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4746
4747         DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
4748
4749         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4750         if (ret)
4751                 return ret;
4752
4753         /*
4754          * Turbo will still be enabled, but won't go below the set value.
4755          */
4756         val = intel_freq_opcode(dev_priv, val);
4757
4758         hw_max = dev_priv->rps.max_freq;
4759         hw_min = dev_priv->rps.min_freq;
4760
4761         if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
4762                 mutex_unlock(&dev_priv->rps.hw_lock);
4763                 return -EINVAL;
4764         }
4765
4766         dev_priv->rps.min_freq_softlimit = val;
4767
4768         intel_set_rps(dev, val);
4769
4770         mutex_unlock(&dev_priv->rps.hw_lock);
4771
4772         return 0;
4773 }
4774
4775 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4776                         i915_min_freq_get, i915_min_freq_set,
4777                         "%llu\n");
4778
4779 static int
4780 i915_cache_sharing_get(void *data, u64 *val)
4781 {
4782         struct drm_device *dev = data;
4783         struct drm_i915_private *dev_priv = dev->dev_private;
4784         u32 snpcr;
4785         int ret;
4786
4787         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4788                 return -ENODEV;
4789
4790         ret = mutex_lock_interruptible(&dev->struct_mutex);
4791         if (ret)
4792                 return ret;
4793         intel_runtime_pm_get(dev_priv);
4794
4795         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4796
4797         intel_runtime_pm_put(dev_priv);
4798         mutex_unlock(&dev_priv->dev->struct_mutex);
4799
4800         *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
4801
4802         return 0;
4803 }
4804
4805 static int
4806 i915_cache_sharing_set(void *data, u64 val)
4807 {
4808         struct drm_device *dev = data;
4809         struct drm_i915_private *dev_priv = dev->dev_private;
4810         u32 snpcr;
4811
4812         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4813                 return -ENODEV;
4814
4815         if (val > 3)
4816                 return -EINVAL;
4817
4818         intel_runtime_pm_get(dev_priv);
4819         DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
4820
4821         /* Update the cache sharing policy here as well */
4822         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4823         snpcr &= ~GEN6_MBC_SNPCR_MASK;
4824         snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
4825         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4826
4827         intel_runtime_pm_put(dev_priv);
4828         return 0;
4829 }
4830
4831 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
4832                         i915_cache_sharing_get, i915_cache_sharing_set,
4833                         "%llu\n");
4834
4835 struct sseu_dev_status {
4836         unsigned int slice_total;
4837         unsigned int subslice_total;
4838         unsigned int subslice_per_slice;
4839         unsigned int eu_total;
4840         unsigned int eu_per_subslice;
4841 };
4842
4843 static void cherryview_sseu_device_status(struct drm_device *dev,
4844                                           struct sseu_dev_status *stat)
4845 {
4846         struct drm_i915_private *dev_priv = dev->dev_private;
4847         const int ss_max = 2;
4848         int ss;
4849         u32 sig1[ss_max], sig2[ss_max];
4850
4851         sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
4852         sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
4853         sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
4854         sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
4855
4856         for (ss = 0; ss < ss_max; ss++) {
4857                 unsigned int eu_cnt;
4858
4859                 if (sig1[ss] & CHV_SS_PG_ENABLE)
4860                         /* skip disabled subslice */
4861                         continue;
4862
4863                 stat->slice_total = 1;
4864                 stat->subslice_per_slice++;
4865                 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
4866                          ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
4867                          ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
4868                          ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
4869                 stat->eu_total += eu_cnt;
4870                 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
4871         }
4872         stat->subslice_total = stat->subslice_per_slice;
4873 }
4874
4875 static void gen9_sseu_device_status(struct drm_device *dev,
4876                                     struct sseu_dev_status *stat)
4877 {
4878         struct drm_i915_private *dev_priv = dev->dev_private;
4879         int s_max = 3, ss_max = 4;
4880         int s, ss;
4881         u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
4882
4883         /* BXT has a single slice and at most 3 subslices. */
4884         if (IS_BROXTON(dev)) {
4885                 s_max = 1;
4886                 ss_max = 3;
4887         }
4888
4889         for (s = 0; s < s_max; s++) {
4890                 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
4891                 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
4892                 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
4893         }
4894
4895         eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
4896                      GEN9_PGCTL_SSA_EU19_ACK |
4897                      GEN9_PGCTL_SSA_EU210_ACK |
4898                      GEN9_PGCTL_SSA_EU311_ACK;
4899         eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
4900                      GEN9_PGCTL_SSB_EU19_ACK |
4901                      GEN9_PGCTL_SSB_EU210_ACK |
4902                      GEN9_PGCTL_SSB_EU311_ACK;
4903
4904         for (s = 0; s < s_max; s++) {
4905                 unsigned int ss_cnt = 0;
4906
4907                 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
4908                         /* skip disabled slice */
4909                         continue;
4910
4911                 stat->slice_total++;
4912
4913                 if (IS_SKYLAKE(dev))
4914                         ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
4915
4916                 for (ss = 0; ss < ss_max; ss++) {
4917                         unsigned int eu_cnt;
4918
4919                         if (IS_BROXTON(dev) &&
4920                             !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
4921                                 /* skip disabled subslice */
4922                                 continue;
4923
4924                         if (IS_BROXTON(dev))
4925                                 ss_cnt++;
4926
4927                         eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
4928                                                eu_mask[ss%2]);
4929                         stat->eu_total += eu_cnt;
4930                         stat->eu_per_subslice = max(stat->eu_per_subslice,
4931                                                     eu_cnt);
4932                 }
4933
4934                 stat->subslice_total += ss_cnt;
4935                 stat->subslice_per_slice = max(stat->subslice_per_slice,
4936                                                ss_cnt);
4937         }
4938 }
4939
4940 static int i915_sseu_status(struct seq_file *m, void *unused)
4941 {
4942         struct drm_info_node *node = (struct drm_info_node *) m->private;
4943         struct drm_device *dev = node->minor->dev;
4944         struct sseu_dev_status stat;
4945
4946         if ((INTEL_INFO(dev)->gen < 8) || IS_BROADWELL(dev))
4947                 return -ENODEV;
4948
4949         seq_puts(m, "SSEU Device Info\n");
4950         seq_printf(m, "  Available Slice Total: %u\n",
4951                    INTEL_INFO(dev)->slice_total);
4952         seq_printf(m, "  Available Subslice Total: %u\n",
4953                    INTEL_INFO(dev)->subslice_total);
4954         seq_printf(m, "  Available Subslice Per Slice: %u\n",
4955                    INTEL_INFO(dev)->subslice_per_slice);
4956         seq_printf(m, "  Available EU Total: %u\n",
4957                    INTEL_INFO(dev)->eu_total);
4958         seq_printf(m, "  Available EU Per Subslice: %u\n",
4959                    INTEL_INFO(dev)->eu_per_subslice);
4960         seq_printf(m, "  Has Slice Power Gating: %s\n",
4961                    yesno(INTEL_INFO(dev)->has_slice_pg));
4962         seq_printf(m, "  Has Subslice Power Gating: %s\n",
4963                    yesno(INTEL_INFO(dev)->has_subslice_pg));
4964         seq_printf(m, "  Has EU Power Gating: %s\n",
4965                    yesno(INTEL_INFO(dev)->has_eu_pg));
4966
4967         seq_puts(m, "SSEU Device Status\n");
4968         memset(&stat, 0, sizeof(stat));
4969         if (IS_CHERRYVIEW(dev)) {
4970                 cherryview_sseu_device_status(dev, &stat);
4971         } else if (INTEL_INFO(dev)->gen >= 9) {
4972                 gen9_sseu_device_status(dev, &stat);
4973         }
4974         seq_printf(m, "  Enabled Slice Total: %u\n",
4975                    stat.slice_total);
4976         seq_printf(m, "  Enabled Subslice Total: %u\n",
4977                    stat.subslice_total);
4978         seq_printf(m, "  Enabled Subslice Per Slice: %u\n",
4979                    stat.subslice_per_slice);
4980         seq_printf(m, "  Enabled EU Total: %u\n",
4981                    stat.eu_total);
4982         seq_printf(m, "  Enabled EU Per Subslice: %u\n",
4983                    stat.eu_per_subslice);
4984
4985         return 0;
4986 }
4987
4988 static int i915_forcewake_open(struct inode *inode, struct file *file)
4989 {
4990         struct drm_device *dev = inode->i_private;
4991         struct drm_i915_private *dev_priv = dev->dev_private;
4992
4993         if (INTEL_INFO(dev)->gen < 6)
4994                 return 0;
4995
4996         intel_runtime_pm_get(dev_priv);
4997         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4998
4999         return 0;
5000 }
5001
5002 static int i915_forcewake_release(struct inode *inode, struct file *file)
5003 {
5004         struct drm_device *dev = inode->i_private;
5005         struct drm_i915_private *dev_priv = dev->dev_private;
5006
5007         if (INTEL_INFO(dev)->gen < 6)
5008                 return 0;
5009
5010         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5011         intel_runtime_pm_put(dev_priv);
5012
5013         return 0;
5014 }
5015
5016 static const struct file_operations i915_forcewake_fops = {
5017         .owner = THIS_MODULE,
5018         .open = i915_forcewake_open,
5019         .release = i915_forcewake_release,
5020 };
5021
5022 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5023 {
5024         struct drm_device *dev = minor->dev;
5025         struct dentry *ent;
5026
5027         ent = debugfs_create_file("i915_forcewake_user",
5028                                   S_IRUSR,
5029                                   root, dev,
5030                                   &i915_forcewake_fops);
5031         if (!ent)
5032                 return -ENOMEM;
5033
5034         return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
5035 }
5036
5037 static int i915_debugfs_create(struct dentry *root,
5038                                struct drm_minor *minor,
5039                                const char *name,
5040                                const struct file_operations *fops)
5041 {
5042         struct drm_device *dev = minor->dev;
5043         struct dentry *ent;
5044
5045         ent = debugfs_create_file(name,
5046                                   S_IRUGO | S_IWUSR,
5047                                   root, dev,
5048                                   fops);
5049         if (!ent)
5050                 return -ENOMEM;
5051
5052         return drm_add_fake_info_node(minor, ent, fops);
5053 }
5054
5055 static const struct drm_info_list i915_debugfs_list[] = {
5056         {"i915_capabilities", i915_capabilities, 0},
5057         {"i915_gem_objects", i915_gem_object_info, 0},
5058         {"i915_gem_gtt", i915_gem_gtt_info, 0},
5059         {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
5060         {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
5061         {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
5062         {"i915_gem_stolen", i915_gem_stolen_list_info },
5063         {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
5064         {"i915_gem_request", i915_gem_request_info, 0},
5065         {"i915_gem_seqno", i915_gem_seqno_info, 0},
5066         {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
5067         {"i915_gem_interrupt", i915_interrupt_info, 0},
5068         {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5069         {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5070         {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
5071         {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
5072         {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
5073         {"i915_frequency_info", i915_frequency_info, 0},
5074         {"i915_hangcheck_info", i915_hangcheck_info, 0},
5075         {"i915_drpc_info", i915_drpc_info, 0},
5076         {"i915_emon_status", i915_emon_status, 0},
5077         {"i915_ring_freq_table", i915_ring_freq_table, 0},
5078         {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
5079         {"i915_fbc_status", i915_fbc_status, 0},
5080         {"i915_ips_status", i915_ips_status, 0},
5081         {"i915_sr_status", i915_sr_status, 0},
5082         {"i915_opregion", i915_opregion, 0},
5083         {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
5084         {"i915_context_status", i915_context_status, 0},
5085         {"i915_dump_lrc", i915_dump_lrc, 0},
5086         {"i915_execlists", i915_execlists, 0},
5087         {"i915_forcewake_domains", i915_forcewake_domains, 0},
5088         {"i915_swizzle_info", i915_swizzle_info, 0},
5089         {"i915_ppgtt_info", i915_ppgtt_info, 0},
5090         {"i915_llc", i915_llc, 0},
5091         {"i915_edp_psr_status", i915_edp_psr_status, 0},
5092         {"i915_sink_crc_eDP1", i915_sink_crc, 0},
5093         {"i915_energy_uJ", i915_energy_uJ, 0},
5094         {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
5095         {"i915_power_domain_info", i915_power_domain_info, 0},
5096         {"i915_display_info", i915_display_info, 0},
5097         {"i915_semaphore_status", i915_semaphore_status, 0},
5098         {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
5099         {"i915_dp_mst_info", i915_dp_mst_info, 0},
5100         {"i915_wa_registers", i915_wa_registers, 0},
5101         {"i915_ddb_info", i915_ddb_info, 0},
5102         {"i915_sseu_status", i915_sseu_status, 0},
5103         {"i915_drrs_status", i915_drrs_status, 0},
5104         {"i915_rps_boost_info", i915_rps_boost_info, 0},
5105 };
5106 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5107
5108 static const struct i915_debugfs_files {
5109         const char *name;
5110         const struct file_operations *fops;
5111 } i915_debugfs_files[] = {
5112         {"i915_wedged", &i915_wedged_fops},
5113         {"i915_max_freq", &i915_max_freq_fops},
5114         {"i915_min_freq", &i915_min_freq_fops},
5115         {"i915_cache_sharing", &i915_cache_sharing_fops},
5116         {"i915_ring_stop", &i915_ring_stop_fops},
5117         {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5118         {"i915_ring_test_irq", &i915_ring_test_irq_fops},
5119         {"i915_gem_drop_caches", &i915_drop_caches_fops},
5120         {"i915_error_state", &i915_error_state_fops},
5121         {"i915_next_seqno", &i915_next_seqno_fops},
5122         {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
5123         {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5124         {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5125         {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
5126         {"i915_fbc_false_color", &i915_fbc_fc_fops},
5127         {"i915_dp_test_data", &i915_displayport_test_data_fops},
5128         {"i915_dp_test_type", &i915_displayport_test_type_fops},
5129         {"i915_dp_test_active", &i915_displayport_test_active_fops}
5130 };
5131
5132 void intel_display_crc_init(struct drm_device *dev)
5133 {
5134         struct drm_i915_private *dev_priv = dev->dev_private;
5135         enum pipe pipe;
5136
5137         for_each_pipe(dev_priv, pipe) {
5138                 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
5139
5140                 pipe_crc->opened = false;
5141                 spin_lock_init(&pipe_crc->lock);
5142                 init_waitqueue_head(&pipe_crc->wq);
5143         }
5144 }
5145
5146 int i915_debugfs_init(struct drm_minor *minor)
5147 {
5148         int ret, i;
5149
5150         ret = i915_forcewake_create(minor->debugfs_root, minor);
5151         if (ret)
5152                 return ret;
5153
5154         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5155                 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5156                 if (ret)
5157                         return ret;
5158         }
5159
5160         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5161                 ret = i915_debugfs_create(minor->debugfs_root, minor,
5162                                           i915_debugfs_files[i].name,
5163                                           i915_debugfs_files[i].fops);
5164                 if (ret)
5165                         return ret;
5166         }
5167
5168         return drm_debugfs_create_files(i915_debugfs_list,
5169                                         I915_DEBUGFS_ENTRIES,
5170                                         minor->debugfs_root, minor);
5171 }
5172
5173 void i915_debugfs_cleanup(struct drm_minor *minor)
5174 {
5175         int i;
5176
5177         drm_debugfs_remove_files(i915_debugfs_list,
5178                                  I915_DEBUGFS_ENTRIES, minor);
5179
5180         drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
5181                                  1, minor);
5182
5183         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5184                 struct drm_info_list *info_list =
5185                         (struct drm_info_list *)&i915_pipe_crc_data[i];
5186
5187                 drm_debugfs_remove_files(info_list, 1, minor);
5188         }
5189
5190         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5191                 struct drm_info_list *info_list =
5192                         (struct drm_info_list *) i915_debugfs_files[i].fops;
5193
5194                 drm_debugfs_remove_files(info_list, 1, minor);
5195         }
5196 }
5197
5198 struct dpcd_block {
5199         /* DPCD dump start address. */
5200         unsigned int offset;
5201         /* DPCD dump end address, inclusive. If unset, .size will be used. */
5202         unsigned int end;
5203         /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5204         size_t size;
5205         /* Only valid for eDP. */
5206         bool edp;
5207 };
5208
5209 static const struct dpcd_block i915_dpcd_debug[] = {
5210         { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5211         { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5212         { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5213         { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5214         { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5215         { .offset = DP_SET_POWER },
5216         { .offset = DP_EDP_DPCD_REV },
5217         { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5218         { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5219         { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5220 };
5221
5222 static int i915_dpcd_show(struct seq_file *m, void *data)
5223 {
5224         struct drm_connector *connector = m->private;
5225         struct intel_dp *intel_dp =
5226                 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5227         uint8_t buf[16];
5228         ssize_t err;
5229         int i;
5230
5231         if (connector->status != connector_status_connected)
5232                 return -ENODEV;
5233
5234         for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5235                 const struct dpcd_block *b = &i915_dpcd_debug[i];
5236                 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5237
5238                 if (b->edp &&
5239                     connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5240                         continue;
5241
5242                 /* low tech for now */
5243                 if (WARN_ON(size > sizeof(buf)))
5244                         continue;
5245
5246                 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5247                 if (err <= 0) {
5248                         DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5249                                   size, b->offset, err);
5250                         continue;
5251                 }
5252
5253                 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
5254         }
5255
5256         return 0;
5257 }
5258
5259 static int i915_dpcd_open(struct inode *inode, struct file *file)
5260 {
5261         return single_open(file, i915_dpcd_show, inode->i_private);
5262 }
5263
5264 static const struct file_operations i915_dpcd_fops = {
5265         .owner = THIS_MODULE,
5266         .open = i915_dpcd_open,
5267         .read = seq_read,
5268         .llseek = seq_lseek,
5269         .release = single_release,
5270 };
5271
5272 /**
5273  * i915_debugfs_connector_add - add i915 specific connector debugfs files
5274  * @connector: pointer to a registered drm_connector
5275  *
5276  * Cleanup will be done by drm_connector_unregister() through a call to
5277  * drm_debugfs_connector_remove().
5278  *
5279  * Returns 0 on success, negative error codes on error.
5280  */
5281 int i915_debugfs_connector_add(struct drm_connector *connector)
5282 {
5283         struct dentry *root = connector->debugfs_entry;
5284
5285         /* The connector must have been registered beforehands. */
5286         if (!root)
5287                 return -ENODEV;
5288
5289         if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5290             connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5291                 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,
5292                                     &i915_dpcd_fops);
5293
5294         return 0;
5295 }