2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
43 static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
45 return to_i915(node->minor->dev);
48 /* As the drm_debugfs_init() routines are called before dev->dev_private is
49 * allocated we need to hook into the minor for release. */
51 drm_add_fake_info_node(struct drm_minor *minor,
55 struct drm_info_node *node;
57 node = kmalloc(sizeof(*node), GFP_KERNEL);
65 node->info_ent = (void *)key;
67 mutex_lock(&minor->debugfs_lock);
68 list_add(&node->list, &minor->debugfs_list);
69 mutex_unlock(&minor->debugfs_lock);
74 static int i915_capabilities(struct seq_file *m, void *data)
76 struct drm_i915_private *dev_priv = node_to_i915(m->private);
77 const struct intel_device_info *info = INTEL_INFO(dev_priv);
79 seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv));
80 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv));
81 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
82 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
88 static char get_active_flag(struct drm_i915_gem_object *obj)
90 return i915_gem_object_is_active(obj) ? '*' : ' ';
93 static char get_pin_flag(struct drm_i915_gem_object *obj)
95 return obj->pin_display ? 'p' : ' ';
98 static char get_tiling_flag(struct drm_i915_gem_object *obj)
100 switch (i915_gem_object_get_tiling(obj)) {
102 case I915_TILING_NONE: return ' ';
103 case I915_TILING_X: return 'X';
104 case I915_TILING_Y: return 'Y';
108 static char get_global_flag(struct drm_i915_gem_object *obj)
110 return !list_empty(&obj->userfault_link) ? 'g' : ' ';
113 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
115 return obj->mm.mapping ? 'M' : ' ';
118 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
121 struct i915_vma *vma;
123 list_for_each_entry(vma, &obj->vma_list, obj_link) {
124 if (i915_vma_is_ggtt(vma) && drm_mm_node_allocated(&vma->node))
125 size += vma->node.size;
132 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
134 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
135 struct intel_engine_cs *engine;
136 struct i915_vma *vma;
137 unsigned int frontbuffer_bits;
140 lockdep_assert_held(&obj->base.dev->struct_mutex);
142 seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x %s%s%s",
144 get_active_flag(obj),
146 get_tiling_flag(obj),
147 get_global_flag(obj),
148 get_pin_mapped_flag(obj),
149 obj->base.size / 1024,
150 obj->base.read_domains,
151 obj->base.write_domain,
152 i915_cache_level_str(dev_priv, obj->cache_level),
153 obj->mm.dirty ? " dirty" : "",
154 obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : "");
156 seq_printf(m, " (name: %d)", obj->base.name);
157 list_for_each_entry(vma, &obj->vma_list, obj_link) {
158 if (i915_vma_is_pinned(vma))
161 seq_printf(m, " (pinned x %d)", pin_count);
162 if (obj->pin_display)
163 seq_printf(m, " (display)");
164 list_for_each_entry(vma, &obj->vma_list, obj_link) {
165 if (!drm_mm_node_allocated(&vma->node))
168 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
169 i915_vma_is_ggtt(vma) ? "g" : "pp",
170 vma->node.start, vma->node.size);
171 if (i915_vma_is_ggtt(vma))
172 seq_printf(m, ", type: %u", vma->ggtt_view.type);
174 seq_printf(m, " , fence: %d%s",
176 i915_gem_active_isset(&vma->last_fence) ? "*" : "");
180 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
182 engine = i915_gem_object_last_write_engine(obj);
184 seq_printf(m, " (%s)", engine->name);
186 frontbuffer_bits = atomic_read(&obj->frontbuffer_bits);
187 if (frontbuffer_bits)
188 seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits);
191 static int obj_rank_by_stolen(void *priv,
192 struct list_head *A, struct list_head *B)
194 struct drm_i915_gem_object *a =
195 container_of(A, struct drm_i915_gem_object, obj_exec_link);
196 struct drm_i915_gem_object *b =
197 container_of(B, struct drm_i915_gem_object, obj_exec_link);
199 if (a->stolen->start < b->stolen->start)
201 if (a->stolen->start > b->stolen->start)
206 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
208 struct drm_i915_private *dev_priv = node_to_i915(m->private);
209 struct drm_device *dev = &dev_priv->drm;
210 struct drm_i915_gem_object *obj;
211 u64 total_obj_size, total_gtt_size;
215 ret = mutex_lock_interruptible(&dev->struct_mutex);
219 total_obj_size = total_gtt_size = count = 0;
220 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) {
221 if (obj->stolen == NULL)
224 list_add(&obj->obj_exec_link, &stolen);
226 total_obj_size += obj->base.size;
227 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
230 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_link) {
231 if (obj->stolen == NULL)
234 list_add(&obj->obj_exec_link, &stolen);
236 total_obj_size += obj->base.size;
239 list_sort(NULL, &stolen, obj_rank_by_stolen);
240 seq_puts(m, "Stolen:\n");
241 while (!list_empty(&stolen)) {
242 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
244 describe_obj(m, obj);
246 list_del_init(&obj->obj_exec_link);
248 mutex_unlock(&dev->struct_mutex);
250 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
251 count, total_obj_size, total_gtt_size);
256 struct drm_i915_file_private *file_priv;
260 u64 active, inactive;
263 static int per_file_stats(int id, void *ptr, void *data)
265 struct drm_i915_gem_object *obj = ptr;
266 struct file_stats *stats = data;
267 struct i915_vma *vma;
270 stats->total += obj->base.size;
271 if (!obj->bind_count)
272 stats->unbound += obj->base.size;
273 if (obj->base.name || obj->base.dma_buf)
274 stats->shared += obj->base.size;
276 list_for_each_entry(vma, &obj->vma_list, obj_link) {
277 if (!drm_mm_node_allocated(&vma->node))
280 if (i915_vma_is_ggtt(vma)) {
281 stats->global += vma->node.size;
283 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm);
285 if (ppgtt->base.file != stats->file_priv)
289 if (i915_vma_is_active(vma))
290 stats->active += vma->node.size;
292 stats->inactive += vma->node.size;
298 #define print_file_stats(m, name, stats) do { \
300 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
311 static void print_batch_pool_stats(struct seq_file *m,
312 struct drm_i915_private *dev_priv)
314 struct drm_i915_gem_object *obj;
315 struct file_stats stats;
316 struct intel_engine_cs *engine;
317 enum intel_engine_id id;
320 memset(&stats, 0, sizeof(stats));
322 for_each_engine(engine, dev_priv, id) {
323 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
324 list_for_each_entry(obj,
325 &engine->batch_pool.cache_list[j],
327 per_file_stats(0, obj, &stats);
331 print_file_stats(m, "[k]batch pool", stats);
334 static int per_file_ctx_stats(int id, void *ptr, void *data)
336 struct i915_gem_context *ctx = ptr;
339 for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) {
340 if (ctx->engine[n].state)
341 per_file_stats(0, ctx->engine[n].state->obj, data);
342 if (ctx->engine[n].ring)
343 per_file_stats(0, ctx->engine[n].ring->vma->obj, data);
349 static void print_context_stats(struct seq_file *m,
350 struct drm_i915_private *dev_priv)
352 struct drm_device *dev = &dev_priv->drm;
353 struct file_stats stats;
354 struct drm_file *file;
356 memset(&stats, 0, sizeof(stats));
358 mutex_lock(&dev->struct_mutex);
359 if (dev_priv->kernel_context)
360 per_file_ctx_stats(0, dev_priv->kernel_context, &stats);
362 list_for_each_entry(file, &dev->filelist, lhead) {
363 struct drm_i915_file_private *fpriv = file->driver_priv;
364 idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats);
366 mutex_unlock(&dev->struct_mutex);
368 print_file_stats(m, "[k]contexts", stats);
371 static int i915_gem_object_info(struct seq_file *m, void *data)
373 struct drm_i915_private *dev_priv = node_to_i915(m->private);
374 struct drm_device *dev = &dev_priv->drm;
375 struct i915_ggtt *ggtt = &dev_priv->ggtt;
376 u32 count, mapped_count, purgeable_count, dpy_count;
377 u64 size, mapped_size, purgeable_size, dpy_size;
378 struct drm_i915_gem_object *obj;
379 struct drm_file *file;
382 ret = mutex_lock_interruptible(&dev->struct_mutex);
386 seq_printf(m, "%u objects, %llu bytes\n",
387 dev_priv->mm.object_count,
388 dev_priv->mm.object_memory);
391 mapped_size = mapped_count = 0;
392 purgeable_size = purgeable_count = 0;
393 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_link) {
394 size += obj->base.size;
397 if (obj->mm.madv == I915_MADV_DONTNEED) {
398 purgeable_size += obj->base.size;
402 if (obj->mm.mapping) {
404 mapped_size += obj->base.size;
407 seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
409 size = count = dpy_size = dpy_count = 0;
410 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) {
411 size += obj->base.size;
414 if (obj->pin_display) {
415 dpy_size += obj->base.size;
419 if (obj->mm.madv == I915_MADV_DONTNEED) {
420 purgeable_size += obj->base.size;
424 if (obj->mm.mapping) {
426 mapped_size += obj->base.size;
429 seq_printf(m, "%u bound objects, %llu bytes\n",
431 seq_printf(m, "%u purgeable objects, %llu bytes\n",
432 purgeable_count, purgeable_size);
433 seq_printf(m, "%u mapped objects, %llu bytes\n",
434 mapped_count, mapped_size);
435 seq_printf(m, "%u display objects (pinned), %llu bytes\n",
436 dpy_count, dpy_size);
438 seq_printf(m, "%llu [%llu] gtt total\n",
439 ggtt->base.total, ggtt->mappable_end - ggtt->base.start);
442 print_batch_pool_stats(m, dev_priv);
443 mutex_unlock(&dev->struct_mutex);
445 mutex_lock(&dev->filelist_mutex);
446 print_context_stats(m, dev_priv);
447 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
448 struct file_stats stats;
449 struct drm_i915_file_private *file_priv = file->driver_priv;
450 struct drm_i915_gem_request *request;
451 struct task_struct *task;
453 memset(&stats, 0, sizeof(stats));
454 stats.file_priv = file->driver_priv;
455 spin_lock(&file->table_lock);
456 idr_for_each(&file->object_idr, per_file_stats, &stats);
457 spin_unlock(&file->table_lock);
459 * Although we have a valid reference on file->pid, that does
460 * not guarantee that the task_struct who called get_pid() is
461 * still alive (e.g. get_pid(current) => fork() => exit()).
462 * Therefore, we need to protect this ->comm access using RCU.
464 mutex_lock(&dev->struct_mutex);
465 request = list_first_entry_or_null(&file_priv->mm.request_list,
466 struct drm_i915_gem_request,
469 task = pid_task(request && request->ctx->pid ?
470 request->ctx->pid : file->pid,
472 print_file_stats(m, task ? task->comm : "<unknown>", stats);
474 mutex_unlock(&dev->struct_mutex);
476 mutex_unlock(&dev->filelist_mutex);
481 static int i915_gem_gtt_info(struct seq_file *m, void *data)
483 struct drm_info_node *node = m->private;
484 struct drm_i915_private *dev_priv = node_to_i915(node);
485 struct drm_device *dev = &dev_priv->drm;
486 bool show_pin_display_only = !!node->info_ent->data;
487 struct drm_i915_gem_object *obj;
488 u64 total_obj_size, total_gtt_size;
491 ret = mutex_lock_interruptible(&dev->struct_mutex);
495 total_obj_size = total_gtt_size = count = 0;
496 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) {
497 if (show_pin_display_only && !obj->pin_display)
501 describe_obj(m, obj);
503 total_obj_size += obj->base.size;
504 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
508 mutex_unlock(&dev->struct_mutex);
510 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
511 count, total_obj_size, total_gtt_size);
516 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
518 struct drm_i915_private *dev_priv = node_to_i915(m->private);
519 struct drm_device *dev = &dev_priv->drm;
520 struct intel_crtc *crtc;
523 ret = mutex_lock_interruptible(&dev->struct_mutex);
527 for_each_intel_crtc(dev, crtc) {
528 const char pipe = pipe_name(crtc->pipe);
529 const char plane = plane_name(crtc->plane);
530 struct intel_flip_work *work;
532 spin_lock_irq(&dev->event_lock);
533 work = crtc->flip_work;
535 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
541 pending = atomic_read(&work->pending);
543 seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n",
546 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
549 if (work->flip_queued_req) {
550 struct intel_engine_cs *engine = work->flip_queued_req->engine;
552 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
554 work->flip_queued_req->global_seqno,
555 atomic_read(&dev_priv->gt.global_timeline.next_seqno),
556 intel_engine_get_seqno(engine),
557 i915_gem_request_completed(work->flip_queued_req));
559 seq_printf(m, "Flip not associated with any ring\n");
560 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
561 work->flip_queued_vblank,
562 work->flip_ready_vblank,
563 intel_crtc_get_vblank_counter(crtc));
564 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
566 if (INTEL_GEN(dev_priv) >= 4)
567 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
569 addr = I915_READ(DSPADDR(crtc->plane));
570 seq_printf(m, "Current scanout address 0x%08x\n", addr);
572 if (work->pending_flip_obj) {
573 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
574 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
577 spin_unlock_irq(&dev->event_lock);
580 mutex_unlock(&dev->struct_mutex);
585 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
587 struct drm_i915_private *dev_priv = node_to_i915(m->private);
588 struct drm_device *dev = &dev_priv->drm;
589 struct drm_i915_gem_object *obj;
590 struct intel_engine_cs *engine;
591 enum intel_engine_id id;
595 ret = mutex_lock_interruptible(&dev->struct_mutex);
599 for_each_engine(engine, dev_priv, id) {
600 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
604 list_for_each_entry(obj,
605 &engine->batch_pool.cache_list[j],
608 seq_printf(m, "%s cache[%d]: %d objects\n",
609 engine->name, j, count);
611 list_for_each_entry(obj,
612 &engine->batch_pool.cache_list[j],
615 describe_obj(m, obj);
623 seq_printf(m, "total: %d\n", total);
625 mutex_unlock(&dev->struct_mutex);
630 static void print_request(struct seq_file *m,
631 struct drm_i915_gem_request *rq,
634 seq_printf(m, "%s%x [%x:%x] prio=%d @ %dms: %s\n", prefix,
635 rq->global_seqno, rq->ctx->hw_id, rq->fence.seqno,
636 rq->priotree.priority,
637 jiffies_to_msecs(jiffies - rq->emitted_jiffies),
638 rq->timeline->common->name);
641 static int i915_gem_request_info(struct seq_file *m, void *data)
643 struct drm_i915_private *dev_priv = node_to_i915(m->private);
644 struct drm_device *dev = &dev_priv->drm;
645 struct drm_i915_gem_request *req;
646 struct intel_engine_cs *engine;
647 enum intel_engine_id id;
650 ret = mutex_lock_interruptible(&dev->struct_mutex);
655 for_each_engine(engine, dev_priv, id) {
659 list_for_each_entry(req, &engine->timeline->requests, link)
664 seq_printf(m, "%s requests: %d\n", engine->name, count);
665 list_for_each_entry(req, &engine->timeline->requests, link)
666 print_request(m, req, " ");
670 mutex_unlock(&dev->struct_mutex);
673 seq_puts(m, "No requests\n");
678 static void i915_ring_seqno_info(struct seq_file *m,
679 struct intel_engine_cs *engine)
681 struct intel_breadcrumbs *b = &engine->breadcrumbs;
684 seq_printf(m, "Current sequence (%s): %x\n",
685 engine->name, intel_engine_get_seqno(engine));
687 spin_lock_irq(&b->lock);
688 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
689 struct intel_wait *w = container_of(rb, typeof(*w), node);
691 seq_printf(m, "Waiting (%s): %s [%d] on %x\n",
692 engine->name, w->tsk->comm, w->tsk->pid, w->seqno);
694 spin_unlock_irq(&b->lock);
697 static int i915_gem_seqno_info(struct seq_file *m, void *data)
699 struct drm_i915_private *dev_priv = node_to_i915(m->private);
700 struct intel_engine_cs *engine;
701 enum intel_engine_id id;
703 for_each_engine(engine, dev_priv, id)
704 i915_ring_seqno_info(m, engine);
710 static int i915_interrupt_info(struct seq_file *m, void *data)
712 struct drm_i915_private *dev_priv = node_to_i915(m->private);
713 struct intel_engine_cs *engine;
714 enum intel_engine_id id;
717 intel_runtime_pm_get(dev_priv);
719 if (IS_CHERRYVIEW(dev_priv)) {
720 seq_printf(m, "Master Interrupt Control:\t%08x\n",
721 I915_READ(GEN8_MASTER_IRQ));
723 seq_printf(m, "Display IER:\t%08x\n",
725 seq_printf(m, "Display IIR:\t%08x\n",
727 seq_printf(m, "Display IIR_RW:\t%08x\n",
728 I915_READ(VLV_IIR_RW));
729 seq_printf(m, "Display IMR:\t%08x\n",
731 for_each_pipe(dev_priv, pipe) {
732 enum intel_display_power_domain power_domain;
734 power_domain = POWER_DOMAIN_PIPE(pipe);
735 if (!intel_display_power_get_if_enabled(dev_priv,
737 seq_printf(m, "Pipe %c power disabled\n",
742 seq_printf(m, "Pipe %c stat:\t%08x\n",
744 I915_READ(PIPESTAT(pipe)));
746 intel_display_power_put(dev_priv, power_domain);
749 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
750 seq_printf(m, "Port hotplug:\t%08x\n",
751 I915_READ(PORT_HOTPLUG_EN));
752 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
753 I915_READ(VLV_DPFLIPSTAT));
754 seq_printf(m, "DPINVGTT:\t%08x\n",
755 I915_READ(DPINVGTT));
756 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
758 for (i = 0; i < 4; i++) {
759 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
760 i, I915_READ(GEN8_GT_IMR(i)));
761 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
762 i, I915_READ(GEN8_GT_IIR(i)));
763 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
764 i, I915_READ(GEN8_GT_IER(i)));
767 seq_printf(m, "PCU interrupt mask:\t%08x\n",
768 I915_READ(GEN8_PCU_IMR));
769 seq_printf(m, "PCU interrupt identity:\t%08x\n",
770 I915_READ(GEN8_PCU_IIR));
771 seq_printf(m, "PCU interrupt enable:\t%08x\n",
772 I915_READ(GEN8_PCU_IER));
773 } else if (INTEL_GEN(dev_priv) >= 8) {
774 seq_printf(m, "Master Interrupt Control:\t%08x\n",
775 I915_READ(GEN8_MASTER_IRQ));
777 for (i = 0; i < 4; i++) {
778 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
779 i, I915_READ(GEN8_GT_IMR(i)));
780 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
781 i, I915_READ(GEN8_GT_IIR(i)));
782 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
783 i, I915_READ(GEN8_GT_IER(i)));
786 for_each_pipe(dev_priv, pipe) {
787 enum intel_display_power_domain power_domain;
789 power_domain = POWER_DOMAIN_PIPE(pipe);
790 if (!intel_display_power_get_if_enabled(dev_priv,
792 seq_printf(m, "Pipe %c power disabled\n",
796 seq_printf(m, "Pipe %c IMR:\t%08x\n",
798 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
799 seq_printf(m, "Pipe %c IIR:\t%08x\n",
801 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
802 seq_printf(m, "Pipe %c IER:\t%08x\n",
804 I915_READ(GEN8_DE_PIPE_IER(pipe)));
806 intel_display_power_put(dev_priv, power_domain);
809 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
810 I915_READ(GEN8_DE_PORT_IMR));
811 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
812 I915_READ(GEN8_DE_PORT_IIR));
813 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
814 I915_READ(GEN8_DE_PORT_IER));
816 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
817 I915_READ(GEN8_DE_MISC_IMR));
818 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
819 I915_READ(GEN8_DE_MISC_IIR));
820 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
821 I915_READ(GEN8_DE_MISC_IER));
823 seq_printf(m, "PCU interrupt mask:\t%08x\n",
824 I915_READ(GEN8_PCU_IMR));
825 seq_printf(m, "PCU interrupt identity:\t%08x\n",
826 I915_READ(GEN8_PCU_IIR));
827 seq_printf(m, "PCU interrupt enable:\t%08x\n",
828 I915_READ(GEN8_PCU_IER));
829 } else if (IS_VALLEYVIEW(dev_priv)) {
830 seq_printf(m, "Display IER:\t%08x\n",
832 seq_printf(m, "Display IIR:\t%08x\n",
834 seq_printf(m, "Display IIR_RW:\t%08x\n",
835 I915_READ(VLV_IIR_RW));
836 seq_printf(m, "Display IMR:\t%08x\n",
838 for_each_pipe(dev_priv, pipe)
839 seq_printf(m, "Pipe %c stat:\t%08x\n",
841 I915_READ(PIPESTAT(pipe)));
843 seq_printf(m, "Master IER:\t%08x\n",
844 I915_READ(VLV_MASTER_IER));
846 seq_printf(m, "Render IER:\t%08x\n",
848 seq_printf(m, "Render IIR:\t%08x\n",
850 seq_printf(m, "Render IMR:\t%08x\n",
853 seq_printf(m, "PM IER:\t\t%08x\n",
854 I915_READ(GEN6_PMIER));
855 seq_printf(m, "PM IIR:\t\t%08x\n",
856 I915_READ(GEN6_PMIIR));
857 seq_printf(m, "PM IMR:\t\t%08x\n",
858 I915_READ(GEN6_PMIMR));
860 seq_printf(m, "Port hotplug:\t%08x\n",
861 I915_READ(PORT_HOTPLUG_EN));
862 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
863 I915_READ(VLV_DPFLIPSTAT));
864 seq_printf(m, "DPINVGTT:\t%08x\n",
865 I915_READ(DPINVGTT));
867 } else if (!HAS_PCH_SPLIT(dev_priv)) {
868 seq_printf(m, "Interrupt enable: %08x\n",
870 seq_printf(m, "Interrupt identity: %08x\n",
872 seq_printf(m, "Interrupt mask: %08x\n",
874 for_each_pipe(dev_priv, pipe)
875 seq_printf(m, "Pipe %c stat: %08x\n",
877 I915_READ(PIPESTAT(pipe)));
879 seq_printf(m, "North Display Interrupt enable: %08x\n",
881 seq_printf(m, "North Display Interrupt identity: %08x\n",
883 seq_printf(m, "North Display Interrupt mask: %08x\n",
885 seq_printf(m, "South Display Interrupt enable: %08x\n",
887 seq_printf(m, "South Display Interrupt identity: %08x\n",
889 seq_printf(m, "South Display Interrupt mask: %08x\n",
891 seq_printf(m, "Graphics Interrupt enable: %08x\n",
893 seq_printf(m, "Graphics Interrupt identity: %08x\n",
895 seq_printf(m, "Graphics Interrupt mask: %08x\n",
898 for_each_engine(engine, dev_priv, id) {
899 if (INTEL_GEN(dev_priv) >= 6) {
901 "Graphics Interrupt mask (%s): %08x\n",
902 engine->name, I915_READ_IMR(engine));
904 i915_ring_seqno_info(m, engine);
906 intel_runtime_pm_put(dev_priv);
911 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
913 struct drm_i915_private *dev_priv = node_to_i915(m->private);
914 struct drm_device *dev = &dev_priv->drm;
917 ret = mutex_lock_interruptible(&dev->struct_mutex);
921 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
922 for (i = 0; i < dev_priv->num_fence_regs; i++) {
923 struct i915_vma *vma = dev_priv->fence_regs[i].vma;
925 seq_printf(m, "Fence %d, pin count = %d, object = ",
926 i, dev_priv->fence_regs[i].pin_count);
928 seq_puts(m, "unused");
930 describe_obj(m, vma->obj);
934 mutex_unlock(&dev->struct_mutex);
938 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
941 i915_error_state_write(struct file *filp,
942 const char __user *ubuf,
946 struct i915_error_state_file_priv *error_priv = filp->private_data;
948 DRM_DEBUG_DRIVER("Resetting error state\n");
949 i915_destroy_error_state(error_priv->dev);
954 static int i915_error_state_open(struct inode *inode, struct file *file)
956 struct drm_i915_private *dev_priv = inode->i_private;
957 struct i915_error_state_file_priv *error_priv;
959 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
963 error_priv->dev = &dev_priv->drm;
965 i915_error_state_get(&dev_priv->drm, error_priv);
967 file->private_data = error_priv;
972 static int i915_error_state_release(struct inode *inode, struct file *file)
974 struct i915_error_state_file_priv *error_priv = file->private_data;
976 i915_error_state_put(error_priv);
982 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
983 size_t count, loff_t *pos)
985 struct i915_error_state_file_priv *error_priv = file->private_data;
986 struct drm_i915_error_state_buf error_str;
988 ssize_t ret_count = 0;
991 ret = i915_error_state_buf_init(&error_str,
992 to_i915(error_priv->dev), count, *pos);
996 ret = i915_error_state_to_str(&error_str, error_priv);
1000 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1007 *pos = error_str.start + ret_count;
1009 i915_error_state_buf_release(&error_str);
1010 return ret ?: ret_count;
1013 static const struct file_operations i915_error_state_fops = {
1014 .owner = THIS_MODULE,
1015 .open = i915_error_state_open,
1016 .read = i915_error_state_read,
1017 .write = i915_error_state_write,
1018 .llseek = default_llseek,
1019 .release = i915_error_state_release,
1025 i915_next_seqno_get(void *data, u64 *val)
1027 struct drm_i915_private *dev_priv = data;
1029 *val = atomic_read(&dev_priv->gt.global_timeline.next_seqno);
1034 i915_next_seqno_set(void *data, u64 val)
1036 struct drm_i915_private *dev_priv = data;
1037 struct drm_device *dev = &dev_priv->drm;
1040 ret = mutex_lock_interruptible(&dev->struct_mutex);
1044 ret = i915_gem_set_global_seqno(dev, val);
1045 mutex_unlock(&dev->struct_mutex);
1050 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1051 i915_next_seqno_get, i915_next_seqno_set,
1054 static int i915_frequency_info(struct seq_file *m, void *unused)
1056 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1057 struct drm_device *dev = &dev_priv->drm;
1060 intel_runtime_pm_get(dev_priv);
1062 if (IS_GEN5(dev_priv)) {
1063 u16 rgvswctl = I915_READ16(MEMSWCTL);
1064 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1066 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1067 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1068 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1070 seq_printf(m, "Current P-state: %d\n",
1071 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1072 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1075 mutex_lock(&dev_priv->rps.hw_lock);
1076 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1077 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1078 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1080 seq_printf(m, "actual GPU freq: %d MHz\n",
1081 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1083 seq_printf(m, "current GPU freq: %d MHz\n",
1084 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1086 seq_printf(m, "max GPU freq: %d MHz\n",
1087 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1089 seq_printf(m, "min GPU freq: %d MHz\n",
1090 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1092 seq_printf(m, "idle GPU freq: %d MHz\n",
1093 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1096 "efficient (RPe) frequency: %d MHz\n",
1097 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1098 mutex_unlock(&dev_priv->rps.hw_lock);
1099 } else if (INTEL_GEN(dev_priv) >= 6) {
1100 u32 rp_state_limits;
1103 u32 rpmodectl, rpinclimit, rpdeclimit;
1104 u32 rpstat, cagf, reqf;
1105 u32 rpupei, rpcurup, rpprevup;
1106 u32 rpdownei, rpcurdown, rpprevdown;
1107 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1110 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1111 if (IS_BROXTON(dev_priv)) {
1112 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1113 gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1115 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1116 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1119 /* RPSTAT1 is in the GT power well */
1120 ret = mutex_lock_interruptible(&dev->struct_mutex);
1124 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1126 reqf = I915_READ(GEN6_RPNSWREQ);
1127 if (IS_GEN9(dev_priv))
1130 reqf &= ~GEN6_TURBO_DISABLE;
1131 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1136 reqf = intel_gpu_freq(dev_priv, reqf);
1138 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1139 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1140 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1142 rpstat = I915_READ(GEN6_RPSTAT1);
1143 rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
1144 rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
1145 rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
1146 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
1147 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
1148 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
1149 if (IS_GEN9(dev_priv))
1150 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1151 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1152 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1154 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1155 cagf = intel_gpu_freq(dev_priv, cagf);
1157 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1158 mutex_unlock(&dev->struct_mutex);
1160 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
1161 pm_ier = I915_READ(GEN6_PMIER);
1162 pm_imr = I915_READ(GEN6_PMIMR);
1163 pm_isr = I915_READ(GEN6_PMISR);
1164 pm_iir = I915_READ(GEN6_PMIIR);
1165 pm_mask = I915_READ(GEN6_PMINTRMSK);
1167 pm_ier = I915_READ(GEN8_GT_IER(2));
1168 pm_imr = I915_READ(GEN8_GT_IMR(2));
1169 pm_isr = I915_READ(GEN8_GT_ISR(2));
1170 pm_iir = I915_READ(GEN8_GT_IIR(2));
1171 pm_mask = I915_READ(GEN6_PMINTRMSK);
1173 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1174 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1175 seq_printf(m, "pm_intr_keep: 0x%08x\n", dev_priv->rps.pm_intr_keep);
1176 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1177 seq_printf(m, "Render p-state ratio: %d\n",
1178 (gt_perf_status & (IS_GEN9(dev_priv) ? 0x1ff00 : 0xff00)) >> 8);
1179 seq_printf(m, "Render p-state VID: %d\n",
1180 gt_perf_status & 0xff);
1181 seq_printf(m, "Render p-state limit: %d\n",
1182 rp_state_limits & 0xff);
1183 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1184 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1185 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1186 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1187 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1188 seq_printf(m, "CAGF: %dMHz\n", cagf);
1189 seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
1190 rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei));
1191 seq_printf(m, "RP CUR UP: %d (%dus)\n",
1192 rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
1193 seq_printf(m, "RP PREV UP: %d (%dus)\n",
1194 rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
1195 seq_printf(m, "Up threshold: %d%%\n",
1196 dev_priv->rps.up_threshold);
1198 seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
1199 rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
1200 seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
1201 rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown));
1202 seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
1203 rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown));
1204 seq_printf(m, "Down threshold: %d%%\n",
1205 dev_priv->rps.down_threshold);
1207 max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 0 :
1208 rp_state_cap >> 16) & 0xff;
1209 max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1210 GEN9_FREQ_SCALER : 1);
1211 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1212 intel_gpu_freq(dev_priv, max_freq));
1214 max_freq = (rp_state_cap & 0xff00) >> 8;
1215 max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1216 GEN9_FREQ_SCALER : 1);
1217 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1218 intel_gpu_freq(dev_priv, max_freq));
1220 max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 16 :
1221 rp_state_cap >> 0) & 0xff;
1222 max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1223 GEN9_FREQ_SCALER : 1);
1224 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1225 intel_gpu_freq(dev_priv, max_freq));
1226 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1227 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1229 seq_printf(m, "Current freq: %d MHz\n",
1230 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1231 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1232 seq_printf(m, "Idle freq: %d MHz\n",
1233 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1234 seq_printf(m, "Min freq: %d MHz\n",
1235 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1236 seq_printf(m, "Boost freq: %d MHz\n",
1237 intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
1238 seq_printf(m, "Max freq: %d MHz\n",
1239 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1241 "efficient (RPe) frequency: %d MHz\n",
1242 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1244 seq_puts(m, "no P-state info available\n");
1247 seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
1248 seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1249 seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1252 intel_runtime_pm_put(dev_priv);
1256 static void i915_instdone_info(struct drm_i915_private *dev_priv,
1258 struct intel_instdone *instdone)
1263 seq_printf(m, "\t\tINSTDONE: 0x%08x\n",
1264 instdone->instdone);
1266 if (INTEL_GEN(dev_priv) <= 3)
1269 seq_printf(m, "\t\tSC_INSTDONE: 0x%08x\n",
1270 instdone->slice_common);
1272 if (INTEL_GEN(dev_priv) <= 6)
1275 for_each_instdone_slice_subslice(dev_priv, slice, subslice)
1276 seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
1277 slice, subslice, instdone->sampler[slice][subslice]);
1279 for_each_instdone_slice_subslice(dev_priv, slice, subslice)
1280 seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n",
1281 slice, subslice, instdone->row[slice][subslice]);
1284 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1286 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1287 struct intel_engine_cs *engine;
1288 u64 acthd[I915_NUM_ENGINES];
1289 u32 seqno[I915_NUM_ENGINES];
1290 struct intel_instdone instdone;
1291 enum intel_engine_id id;
1293 if (test_bit(I915_WEDGED, &dev_priv->gpu_error.flags))
1294 seq_printf(m, "Wedged\n");
1295 if (test_bit(I915_RESET_IN_PROGRESS, &dev_priv->gpu_error.flags))
1296 seq_printf(m, "Reset in progress\n");
1297 if (waitqueue_active(&dev_priv->gpu_error.wait_queue))
1298 seq_printf(m, "Waiter holding struct mutex\n");
1299 if (waitqueue_active(&dev_priv->gpu_error.reset_queue))
1300 seq_printf(m, "struct_mutex blocked for reset\n");
1302 if (!i915.enable_hangcheck) {
1303 seq_printf(m, "Hangcheck disabled\n");
1307 intel_runtime_pm_get(dev_priv);
1309 for_each_engine(engine, dev_priv, id) {
1310 acthd[id] = intel_engine_get_active_head(engine);
1311 seqno[id] = intel_engine_get_seqno(engine);
1314 intel_engine_get_instdone(dev_priv->engine[RCS], &instdone);
1316 intel_runtime_pm_put(dev_priv);
1318 if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1319 seq_printf(m, "Hangcheck active, fires in %dms\n",
1320 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1323 seq_printf(m, "Hangcheck inactive\n");
1325 for_each_engine(engine, dev_priv, id) {
1326 struct intel_breadcrumbs *b = &engine->breadcrumbs;
1329 seq_printf(m, "%s:\n", engine->name);
1330 seq_printf(m, "\tseqno = %x [current %x, last %x]\n",
1331 engine->hangcheck.seqno, seqno[id],
1332 intel_engine_last_submit(engine));
1333 seq_printf(m, "\twaiters? %s, fake irq active? %s, stalled? %s\n",
1334 yesno(intel_engine_has_waiter(engine)),
1335 yesno(test_bit(engine->id,
1336 &dev_priv->gpu_error.missed_irq_rings)),
1337 yesno(engine->hangcheck.stalled));
1339 spin_lock_irq(&b->lock);
1340 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
1341 struct intel_wait *w = container_of(rb, typeof(*w), node);
1343 seq_printf(m, "\t%s [%d] waiting for %x\n",
1344 w->tsk->comm, w->tsk->pid, w->seqno);
1346 spin_unlock_irq(&b->lock);
1348 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1349 (long long)engine->hangcheck.acthd,
1350 (long long)acthd[id]);
1351 seq_printf(m, "\taction = %s(%d) %d ms ago\n",
1352 hangcheck_action_to_str(engine->hangcheck.action),
1353 engine->hangcheck.action,
1354 jiffies_to_msecs(jiffies -
1355 engine->hangcheck.action_timestamp));
1357 if (engine->id == RCS) {
1358 seq_puts(m, "\tinstdone read =\n");
1360 i915_instdone_info(dev_priv, m, &instdone);
1362 seq_puts(m, "\tinstdone accu =\n");
1364 i915_instdone_info(dev_priv, m,
1365 &engine->hangcheck.instdone);
1372 static int ironlake_drpc_info(struct seq_file *m)
1374 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1375 u32 rgvmodectl, rstdbyctl;
1378 intel_runtime_pm_get(dev_priv);
1380 rgvmodectl = I915_READ(MEMMODECTL);
1381 rstdbyctl = I915_READ(RSTDBYCTL);
1382 crstandvid = I915_READ16(CRSTANDVID);
1384 intel_runtime_pm_put(dev_priv);
1386 seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1387 seq_printf(m, "Boost freq: %d\n",
1388 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1389 MEMMODE_BOOST_FREQ_SHIFT);
1390 seq_printf(m, "HW control enabled: %s\n",
1391 yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1392 seq_printf(m, "SW control enabled: %s\n",
1393 yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1394 seq_printf(m, "Gated voltage change: %s\n",
1395 yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1396 seq_printf(m, "Starting frequency: P%d\n",
1397 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1398 seq_printf(m, "Max P-state: P%d\n",
1399 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1400 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1401 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1402 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1403 seq_printf(m, "Render standby enabled: %s\n",
1404 yesno(!(rstdbyctl & RCX_SW_EXIT)));
1405 seq_puts(m, "Current RS state: ");
1406 switch (rstdbyctl & RSX_STATUS_MASK) {
1408 seq_puts(m, "on\n");
1410 case RSX_STATUS_RC1:
1411 seq_puts(m, "RC1\n");
1413 case RSX_STATUS_RC1E:
1414 seq_puts(m, "RC1E\n");
1416 case RSX_STATUS_RS1:
1417 seq_puts(m, "RS1\n");
1419 case RSX_STATUS_RS2:
1420 seq_puts(m, "RS2 (RC6)\n");
1422 case RSX_STATUS_RS3:
1423 seq_puts(m, "RC3 (RC6+)\n");
1426 seq_puts(m, "unknown\n");
1433 static int i915_forcewake_domains(struct seq_file *m, void *data)
1435 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1436 struct intel_uncore_forcewake_domain *fw_domain;
1438 spin_lock_irq(&dev_priv->uncore.lock);
1439 for_each_fw_domain(fw_domain, dev_priv) {
1440 seq_printf(m, "%s.wake_count = %u\n",
1441 intel_uncore_forcewake_domain_to_str(fw_domain->id),
1442 fw_domain->wake_count);
1444 spin_unlock_irq(&dev_priv->uncore.lock);
1449 static int vlv_drpc_info(struct seq_file *m)
1451 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1452 u32 rpmodectl1, rcctl1, pw_status;
1454 intel_runtime_pm_get(dev_priv);
1456 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1457 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1458 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1460 intel_runtime_pm_put(dev_priv);
1462 seq_printf(m, "Video Turbo Mode: %s\n",
1463 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1464 seq_printf(m, "Turbo enabled: %s\n",
1465 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1466 seq_printf(m, "HW control enabled: %s\n",
1467 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1468 seq_printf(m, "SW control enabled: %s\n",
1469 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1470 GEN6_RP_MEDIA_SW_MODE));
1471 seq_printf(m, "RC6 Enabled: %s\n",
1472 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1473 GEN6_RC_CTL_EI_MODE(1))));
1474 seq_printf(m, "Render Power Well: %s\n",
1475 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1476 seq_printf(m, "Media Power Well: %s\n",
1477 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1479 seq_printf(m, "Render RC6 residency since boot: %u\n",
1480 I915_READ(VLV_GT_RENDER_RC6));
1481 seq_printf(m, "Media RC6 residency since boot: %u\n",
1482 I915_READ(VLV_GT_MEDIA_RC6));
1484 return i915_forcewake_domains(m, NULL);
1487 static int gen6_drpc_info(struct seq_file *m)
1489 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1490 struct drm_device *dev = &dev_priv->drm;
1491 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1492 u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
1493 unsigned forcewake_count;
1496 ret = mutex_lock_interruptible(&dev->struct_mutex);
1499 intel_runtime_pm_get(dev_priv);
1501 spin_lock_irq(&dev_priv->uncore.lock);
1502 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1503 spin_unlock_irq(&dev_priv->uncore.lock);
1505 if (forcewake_count) {
1506 seq_puts(m, "RC information inaccurate because somebody "
1507 "holds a forcewake reference \n");
1509 /* NB: we cannot use forcewake, else we read the wrong values */
1510 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1512 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1515 gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1516 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1518 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1519 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1520 if (INTEL_GEN(dev_priv) >= 9) {
1521 gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE);
1522 gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
1524 mutex_unlock(&dev->struct_mutex);
1525 mutex_lock(&dev_priv->rps.hw_lock);
1526 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1527 mutex_unlock(&dev_priv->rps.hw_lock);
1529 intel_runtime_pm_put(dev_priv);
1531 seq_printf(m, "Video Turbo Mode: %s\n",
1532 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1533 seq_printf(m, "HW control enabled: %s\n",
1534 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1535 seq_printf(m, "SW control enabled: %s\n",
1536 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1537 GEN6_RP_MEDIA_SW_MODE));
1538 seq_printf(m, "RC1e Enabled: %s\n",
1539 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1540 seq_printf(m, "RC6 Enabled: %s\n",
1541 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1542 if (INTEL_GEN(dev_priv) >= 9) {
1543 seq_printf(m, "Render Well Gating Enabled: %s\n",
1544 yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
1545 seq_printf(m, "Media Well Gating Enabled: %s\n",
1546 yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE));
1548 seq_printf(m, "Deep RC6 Enabled: %s\n",
1549 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1550 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1551 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1552 seq_puts(m, "Current RC state: ");
1553 switch (gt_core_status & GEN6_RCn_MASK) {
1555 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1556 seq_puts(m, "Core Power Down\n");
1558 seq_puts(m, "on\n");
1561 seq_puts(m, "RC3\n");
1564 seq_puts(m, "RC6\n");
1567 seq_puts(m, "RC7\n");
1570 seq_puts(m, "Unknown\n");
1574 seq_printf(m, "Core Power Down: %s\n",
1575 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1576 if (INTEL_GEN(dev_priv) >= 9) {
1577 seq_printf(m, "Render Power Well: %s\n",
1578 (gen9_powergate_status &
1579 GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
1580 seq_printf(m, "Media Power Well: %s\n",
1581 (gen9_powergate_status &
1582 GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
1585 /* Not exactly sure what this is */
1586 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1587 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1588 seq_printf(m, "RC6 residency since boot: %u\n",
1589 I915_READ(GEN6_GT_GFX_RC6));
1590 seq_printf(m, "RC6+ residency since boot: %u\n",
1591 I915_READ(GEN6_GT_GFX_RC6p));
1592 seq_printf(m, "RC6++ residency since boot: %u\n",
1593 I915_READ(GEN6_GT_GFX_RC6pp));
1595 seq_printf(m, "RC6 voltage: %dmV\n",
1596 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1597 seq_printf(m, "RC6+ voltage: %dmV\n",
1598 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1599 seq_printf(m, "RC6++ voltage: %dmV\n",
1600 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1601 return i915_forcewake_domains(m, NULL);
1604 static int i915_drpc_info(struct seq_file *m, void *unused)
1606 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1608 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1609 return vlv_drpc_info(m);
1610 else if (INTEL_GEN(dev_priv) >= 6)
1611 return gen6_drpc_info(m);
1613 return ironlake_drpc_info(m);
1616 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1618 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1620 seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1621 dev_priv->fb_tracking.busy_bits);
1623 seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1624 dev_priv->fb_tracking.flip_bits);
1629 static int i915_fbc_status(struct seq_file *m, void *unused)
1631 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1633 if (!HAS_FBC(dev_priv)) {
1634 seq_puts(m, "FBC unsupported on this chipset\n");
1638 intel_runtime_pm_get(dev_priv);
1639 mutex_lock(&dev_priv->fbc.lock);
1641 if (intel_fbc_is_active(dev_priv))
1642 seq_puts(m, "FBC enabled\n");
1644 seq_printf(m, "FBC disabled: %s\n",
1645 dev_priv->fbc.no_fbc_reason);
1647 if (intel_fbc_is_active(dev_priv) && INTEL_GEN(dev_priv) >= 7) {
1648 uint32_t mask = INTEL_GEN(dev_priv) >= 8 ?
1649 BDW_FBC_COMPRESSION_MASK :
1650 IVB_FBC_COMPRESSION_MASK;
1651 seq_printf(m, "Compressing: %s\n",
1652 yesno(I915_READ(FBC_STATUS2) & mask));
1655 mutex_unlock(&dev_priv->fbc.lock);
1656 intel_runtime_pm_put(dev_priv);
1661 static int i915_fbc_fc_get(void *data, u64 *val)
1663 struct drm_i915_private *dev_priv = data;
1665 if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1668 *val = dev_priv->fbc.false_color;
1673 static int i915_fbc_fc_set(void *data, u64 val)
1675 struct drm_i915_private *dev_priv = data;
1678 if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1681 mutex_lock(&dev_priv->fbc.lock);
1683 reg = I915_READ(ILK_DPFC_CONTROL);
1684 dev_priv->fbc.false_color = val;
1686 I915_WRITE(ILK_DPFC_CONTROL, val ?
1687 (reg | FBC_CTL_FALSE_COLOR) :
1688 (reg & ~FBC_CTL_FALSE_COLOR));
1690 mutex_unlock(&dev_priv->fbc.lock);
1694 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1695 i915_fbc_fc_get, i915_fbc_fc_set,
1698 static int i915_ips_status(struct seq_file *m, void *unused)
1700 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1702 if (!HAS_IPS(dev_priv)) {
1703 seq_puts(m, "not supported\n");
1707 intel_runtime_pm_get(dev_priv);
1709 seq_printf(m, "Enabled by kernel parameter: %s\n",
1710 yesno(i915.enable_ips));
1712 if (INTEL_GEN(dev_priv) >= 8) {
1713 seq_puts(m, "Currently: unknown\n");
1715 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1716 seq_puts(m, "Currently: enabled\n");
1718 seq_puts(m, "Currently: disabled\n");
1721 intel_runtime_pm_put(dev_priv);
1726 static int i915_sr_status(struct seq_file *m, void *unused)
1728 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1729 bool sr_enabled = false;
1731 intel_runtime_pm_get(dev_priv);
1732 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1734 if (HAS_PCH_SPLIT(dev_priv))
1735 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1736 else if (IS_CRESTLINE(dev_priv) || IS_G4X(dev_priv) ||
1737 IS_I945G(dev_priv) || IS_I945GM(dev_priv))
1738 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1739 else if (IS_I915GM(dev_priv))
1740 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1741 else if (IS_PINEVIEW(dev_priv))
1742 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1743 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1744 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1746 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1747 intel_runtime_pm_put(dev_priv);
1749 seq_printf(m, "self-refresh: %s\n", enableddisabled(sr_enabled));
1754 static int i915_emon_status(struct seq_file *m, void *unused)
1756 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1757 struct drm_device *dev = &dev_priv->drm;
1758 unsigned long temp, chipset, gfx;
1761 if (!IS_GEN5(dev_priv))
1764 ret = mutex_lock_interruptible(&dev->struct_mutex);
1768 temp = i915_mch_val(dev_priv);
1769 chipset = i915_chipset_val(dev_priv);
1770 gfx = i915_gfx_val(dev_priv);
1771 mutex_unlock(&dev->struct_mutex);
1773 seq_printf(m, "GMCH temp: %ld\n", temp);
1774 seq_printf(m, "Chipset power: %ld\n", chipset);
1775 seq_printf(m, "GFX power: %ld\n", gfx);
1776 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1781 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1783 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1785 int gpu_freq, ia_freq;
1786 unsigned int max_gpu_freq, min_gpu_freq;
1788 if (!HAS_LLC(dev_priv)) {
1789 seq_puts(m, "unsupported on this chipset\n");
1793 intel_runtime_pm_get(dev_priv);
1795 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1799 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
1800 /* Convert GT frequency to 50 HZ units */
1802 dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1804 dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1806 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1807 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1810 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1812 for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1814 sandybridge_pcode_read(dev_priv,
1815 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1817 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1818 intel_gpu_freq(dev_priv, (gpu_freq *
1819 (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1820 GEN9_FREQ_SCALER : 1))),
1821 ((ia_freq >> 0) & 0xff) * 100,
1822 ((ia_freq >> 8) & 0xff) * 100);
1825 mutex_unlock(&dev_priv->rps.hw_lock);
1828 intel_runtime_pm_put(dev_priv);
1832 static int i915_opregion(struct seq_file *m, void *unused)
1834 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1835 struct drm_device *dev = &dev_priv->drm;
1836 struct intel_opregion *opregion = &dev_priv->opregion;
1839 ret = mutex_lock_interruptible(&dev->struct_mutex);
1843 if (opregion->header)
1844 seq_write(m, opregion->header, OPREGION_SIZE);
1846 mutex_unlock(&dev->struct_mutex);
1852 static int i915_vbt(struct seq_file *m, void *unused)
1854 struct intel_opregion *opregion = &node_to_i915(m->private)->opregion;
1857 seq_write(m, opregion->vbt, opregion->vbt_size);
1862 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1864 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1865 struct drm_device *dev = &dev_priv->drm;
1866 struct intel_framebuffer *fbdev_fb = NULL;
1867 struct drm_framebuffer *drm_fb;
1870 ret = mutex_lock_interruptible(&dev->struct_mutex);
1874 #ifdef CONFIG_DRM_FBDEV_EMULATION
1875 if (dev_priv->fbdev) {
1876 fbdev_fb = to_intel_framebuffer(dev_priv->fbdev->helper.fb);
1878 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1879 fbdev_fb->base.width,
1880 fbdev_fb->base.height,
1881 fbdev_fb->base.depth,
1882 fbdev_fb->base.bits_per_pixel,
1883 fbdev_fb->base.modifier[0],
1884 drm_framebuffer_read_refcount(&fbdev_fb->base));
1885 describe_obj(m, fbdev_fb->obj);
1890 mutex_lock(&dev->mode_config.fb_lock);
1891 drm_for_each_fb(drm_fb, dev) {
1892 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
1896 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1900 fb->base.bits_per_pixel,
1901 fb->base.modifier[0],
1902 drm_framebuffer_read_refcount(&fb->base));
1903 describe_obj(m, fb->obj);
1906 mutex_unlock(&dev->mode_config.fb_lock);
1907 mutex_unlock(&dev->struct_mutex);
1912 static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring)
1914 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1915 ring->space, ring->head, ring->tail,
1916 ring->last_retired_head);
1919 static int i915_context_status(struct seq_file *m, void *unused)
1921 struct drm_i915_private *dev_priv = node_to_i915(m->private);
1922 struct drm_device *dev = &dev_priv->drm;
1923 struct intel_engine_cs *engine;
1924 struct i915_gem_context *ctx;
1925 enum intel_engine_id id;
1928 ret = mutex_lock_interruptible(&dev->struct_mutex);
1932 list_for_each_entry(ctx, &dev_priv->context_list, link) {
1933 seq_printf(m, "HW context %u ", ctx->hw_id);
1935 struct task_struct *task;
1937 task = get_pid_task(ctx->pid, PIDTYPE_PID);
1939 seq_printf(m, "(%s [%d]) ",
1940 task->comm, task->pid);
1941 put_task_struct(task);
1943 } else if (IS_ERR(ctx->file_priv)) {
1944 seq_puts(m, "(deleted) ");
1946 seq_puts(m, "(kernel) ");
1949 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
1952 for_each_engine(engine, dev_priv, id) {
1953 struct intel_context *ce = &ctx->engine[engine->id];
1955 seq_printf(m, "%s: ", engine->name);
1956 seq_putc(m, ce->initialised ? 'I' : 'i');
1958 describe_obj(m, ce->state->obj);
1960 describe_ctx_ring(m, ce->ring);
1967 mutex_unlock(&dev->struct_mutex);
1972 static void i915_dump_lrc_obj(struct seq_file *m,
1973 struct i915_gem_context *ctx,
1974 struct intel_engine_cs *engine)
1976 struct i915_vma *vma = ctx->engine[engine->id].state;
1980 seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id);
1983 seq_puts(m, "\tFake context\n");
1987 if (vma->flags & I915_VMA_GLOBAL_BIND)
1988 seq_printf(m, "\tBound in GGTT at 0x%08x\n",
1989 i915_ggtt_offset(vma));
1991 if (i915_gem_object_pin_pages(vma->obj)) {
1992 seq_puts(m, "\tFailed to get pages for context object\n\n");
1996 page = i915_gem_object_get_page(vma->obj, LRC_STATE_PN);
1998 u32 *reg_state = kmap_atomic(page);
2000 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2002 "\t[0x%04x] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2004 reg_state[j], reg_state[j + 1],
2005 reg_state[j + 2], reg_state[j + 3]);
2007 kunmap_atomic(reg_state);
2010 i915_gem_object_unpin_pages(vma->obj);
2014 static int i915_dump_lrc(struct seq_file *m, void *unused)
2016 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2017 struct drm_device *dev = &dev_priv->drm;
2018 struct intel_engine_cs *engine;
2019 struct i915_gem_context *ctx;
2020 enum intel_engine_id id;
2023 if (!i915.enable_execlists) {
2024 seq_printf(m, "Logical Ring Contexts are disabled\n");
2028 ret = mutex_lock_interruptible(&dev->struct_mutex);
2032 list_for_each_entry(ctx, &dev_priv->context_list, link)
2033 for_each_engine(engine, dev_priv, id)
2034 i915_dump_lrc_obj(m, ctx, engine);
2036 mutex_unlock(&dev->struct_mutex);
2041 static const char *swizzle_string(unsigned swizzle)
2044 case I915_BIT_6_SWIZZLE_NONE:
2046 case I915_BIT_6_SWIZZLE_9:
2048 case I915_BIT_6_SWIZZLE_9_10:
2049 return "bit9/bit10";
2050 case I915_BIT_6_SWIZZLE_9_11:
2051 return "bit9/bit11";
2052 case I915_BIT_6_SWIZZLE_9_10_11:
2053 return "bit9/bit10/bit11";
2054 case I915_BIT_6_SWIZZLE_9_17:
2055 return "bit9/bit17";
2056 case I915_BIT_6_SWIZZLE_9_10_17:
2057 return "bit9/bit10/bit17";
2058 case I915_BIT_6_SWIZZLE_UNKNOWN:
2065 static int i915_swizzle_info(struct seq_file *m, void *data)
2067 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2069 intel_runtime_pm_get(dev_priv);
2071 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2072 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2073 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2074 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2076 if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) {
2077 seq_printf(m, "DDC = 0x%08x\n",
2079 seq_printf(m, "DDC2 = 0x%08x\n",
2081 seq_printf(m, "C0DRB3 = 0x%04x\n",
2082 I915_READ16(C0DRB3));
2083 seq_printf(m, "C1DRB3 = 0x%04x\n",
2084 I915_READ16(C1DRB3));
2085 } else if (INTEL_GEN(dev_priv) >= 6) {
2086 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2087 I915_READ(MAD_DIMM_C0));
2088 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2089 I915_READ(MAD_DIMM_C1));
2090 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2091 I915_READ(MAD_DIMM_C2));
2092 seq_printf(m, "TILECTL = 0x%08x\n",
2093 I915_READ(TILECTL));
2094 if (INTEL_GEN(dev_priv) >= 8)
2095 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2096 I915_READ(GAMTARBMODE));
2098 seq_printf(m, "ARB_MODE = 0x%08x\n",
2099 I915_READ(ARB_MODE));
2100 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2101 I915_READ(DISP_ARB_CTL));
2104 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2105 seq_puts(m, "L-shaped memory detected\n");
2107 intel_runtime_pm_put(dev_priv);
2112 static int per_file_ctx(int id, void *ptr, void *data)
2114 struct i915_gem_context *ctx = ptr;
2115 struct seq_file *m = data;
2116 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2119 seq_printf(m, " no ppgtt for context %d\n",
2124 if (i915_gem_context_is_default(ctx))
2125 seq_puts(m, " default context:\n");
2127 seq_printf(m, " context %d:\n", ctx->user_handle);
2128 ppgtt->debug_dump(ppgtt, m);
2133 static void gen8_ppgtt_info(struct seq_file *m,
2134 struct drm_i915_private *dev_priv)
2136 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2137 struct intel_engine_cs *engine;
2138 enum intel_engine_id id;
2144 for_each_engine(engine, dev_priv, id) {
2145 seq_printf(m, "%s\n", engine->name);
2146 for (i = 0; i < 4; i++) {
2147 u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
2149 pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
2150 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2155 static void gen6_ppgtt_info(struct seq_file *m,
2156 struct drm_i915_private *dev_priv)
2158 struct intel_engine_cs *engine;
2159 enum intel_engine_id id;
2161 if (IS_GEN6(dev_priv))
2162 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2164 for_each_engine(engine, dev_priv, id) {
2165 seq_printf(m, "%s\n", engine->name);
2166 if (IS_GEN7(dev_priv))
2167 seq_printf(m, "GFX_MODE: 0x%08x\n",
2168 I915_READ(RING_MODE_GEN7(engine)));
2169 seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
2170 I915_READ(RING_PP_DIR_BASE(engine)));
2171 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
2172 I915_READ(RING_PP_DIR_BASE_READ(engine)));
2173 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
2174 I915_READ(RING_PP_DIR_DCLV(engine)));
2176 if (dev_priv->mm.aliasing_ppgtt) {
2177 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2179 seq_puts(m, "aliasing PPGTT:\n");
2180 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2182 ppgtt->debug_dump(ppgtt, m);
2185 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2188 static int i915_ppgtt_info(struct seq_file *m, void *data)
2190 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2191 struct drm_device *dev = &dev_priv->drm;
2192 struct drm_file *file;
2195 mutex_lock(&dev->filelist_mutex);
2196 ret = mutex_lock_interruptible(&dev->struct_mutex);
2200 intel_runtime_pm_get(dev_priv);
2202 if (INTEL_GEN(dev_priv) >= 8)
2203 gen8_ppgtt_info(m, dev_priv);
2204 else if (INTEL_GEN(dev_priv) >= 6)
2205 gen6_ppgtt_info(m, dev_priv);
2207 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2208 struct drm_i915_file_private *file_priv = file->driver_priv;
2209 struct task_struct *task;
2211 task = get_pid_task(file->pid, PIDTYPE_PID);
2216 seq_printf(m, "\nproc: %s\n", task->comm);
2217 put_task_struct(task);
2218 idr_for_each(&file_priv->context_idr, per_file_ctx,
2219 (void *)(unsigned long)m);
2223 intel_runtime_pm_put(dev_priv);
2224 mutex_unlock(&dev->struct_mutex);
2226 mutex_unlock(&dev->filelist_mutex);
2230 static int count_irq_waiters(struct drm_i915_private *i915)
2232 struct intel_engine_cs *engine;
2233 enum intel_engine_id id;
2236 for_each_engine(engine, i915, id)
2237 count += intel_engine_has_waiter(engine);
2242 static const char *rps_power_to_str(unsigned int power)
2244 static const char * const strings[] = {
2245 [LOW_POWER] = "low power",
2246 [BETWEEN] = "mixed",
2247 [HIGH_POWER] = "high power",
2250 if (power >= ARRAY_SIZE(strings) || !strings[power])
2253 return strings[power];
2256 static int i915_rps_boost_info(struct seq_file *m, void *data)
2258 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2259 struct drm_device *dev = &dev_priv->drm;
2260 struct drm_file *file;
2262 seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2263 seq_printf(m, "GPU busy? %s [%d requests]\n",
2264 yesno(dev_priv->gt.awake), dev_priv->gt.active_requests);
2265 seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2266 seq_printf(m, "Frequency requested %d\n",
2267 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
2268 seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2269 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2270 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2271 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2272 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2273 seq_printf(m, " idle:%d, efficient:%d, boost:%d\n",
2274 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
2275 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2276 intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
2278 mutex_lock(&dev->filelist_mutex);
2279 spin_lock(&dev_priv->rps.client_lock);
2280 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2281 struct drm_i915_file_private *file_priv = file->driver_priv;
2282 struct task_struct *task;
2285 task = pid_task(file->pid, PIDTYPE_PID);
2286 seq_printf(m, "%s [%d]: %d boosts%s\n",
2287 task ? task->comm : "<unknown>",
2288 task ? task->pid : -1,
2289 file_priv->rps.boosts,
2290 list_empty(&file_priv->rps.link) ? "" : ", active");
2293 seq_printf(m, "Kernel (anonymous) boosts: %d\n", dev_priv->rps.boosts);
2294 spin_unlock(&dev_priv->rps.client_lock);
2295 mutex_unlock(&dev->filelist_mutex);
2297 if (INTEL_GEN(dev_priv) >= 6 &&
2298 dev_priv->rps.enabled &&
2299 dev_priv->gt.active_requests) {
2301 u32 rpdown, rpdownei;
2303 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2304 rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK;
2305 rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK;
2306 rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK;
2307 rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK;
2308 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2310 seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n",
2311 rps_power_to_str(dev_priv->rps.power));
2312 seq_printf(m, " Avg. up: %d%% [above threshold? %d%%]\n",
2313 100 * rpup / rpupei,
2314 dev_priv->rps.up_threshold);
2315 seq_printf(m, " Avg. down: %d%% [below threshold? %d%%]\n",
2316 100 * rpdown / rpdownei,
2317 dev_priv->rps.down_threshold);
2319 seq_puts(m, "\nRPS Autotuning inactive\n");
2325 static int i915_llc(struct seq_file *m, void *data)
2327 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2328 const bool edram = INTEL_GEN(dev_priv) > 8;
2330 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv)));
2331 seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
2332 intel_uncore_edram_size(dev_priv)/1024/1024);
2337 static int i915_guc_load_status_info(struct seq_file *m, void *data)
2339 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2340 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
2343 if (!HAS_GUC_UCODE(dev_priv))
2346 seq_printf(m, "GuC firmware status:\n");
2347 seq_printf(m, "\tpath: %s\n",
2348 guc_fw->guc_fw_path);
2349 seq_printf(m, "\tfetch: %s\n",
2350 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
2351 seq_printf(m, "\tload: %s\n",
2352 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
2353 seq_printf(m, "\tversion wanted: %d.%d\n",
2354 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2355 seq_printf(m, "\tversion found: %d.%d\n",
2356 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
2357 seq_printf(m, "\theader: offset is %d; size = %d\n",
2358 guc_fw->header_offset, guc_fw->header_size);
2359 seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2360 guc_fw->ucode_offset, guc_fw->ucode_size);
2361 seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2362 guc_fw->rsa_offset, guc_fw->rsa_size);
2364 tmp = I915_READ(GUC_STATUS);
2366 seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2367 seq_printf(m, "\tBootrom status = 0x%x\n",
2368 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2369 seq_printf(m, "\tuKernel status = 0x%x\n",
2370 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2371 seq_printf(m, "\tMIA Core status = 0x%x\n",
2372 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2373 seq_puts(m, "\nScratch registers:\n");
2374 for (i = 0; i < 16; i++)
2375 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2380 static void i915_guc_log_info(struct seq_file *m,
2381 struct drm_i915_private *dev_priv)
2383 struct intel_guc *guc = &dev_priv->guc;
2385 seq_puts(m, "\nGuC logging stats:\n");
2387 seq_printf(m, "\tISR: flush count %10u, overflow count %10u\n",
2388 guc->log.flush_count[GUC_ISR_LOG_BUFFER],
2389 guc->log.total_overflow_count[GUC_ISR_LOG_BUFFER]);
2391 seq_printf(m, "\tDPC: flush count %10u, overflow count %10u\n",
2392 guc->log.flush_count[GUC_DPC_LOG_BUFFER],
2393 guc->log.total_overflow_count[GUC_DPC_LOG_BUFFER]);
2395 seq_printf(m, "\tCRASH: flush count %10u, overflow count %10u\n",
2396 guc->log.flush_count[GUC_CRASH_DUMP_LOG_BUFFER],
2397 guc->log.total_overflow_count[GUC_CRASH_DUMP_LOG_BUFFER]);
2399 seq_printf(m, "\tTotal flush interrupt count: %u\n",
2400 guc->log.flush_interrupt_count);
2402 seq_printf(m, "\tCapture miss count: %u\n",
2403 guc->log.capture_miss_count);
2406 static void i915_guc_client_info(struct seq_file *m,
2407 struct drm_i915_private *dev_priv,
2408 struct i915_guc_client *client)
2410 struct intel_engine_cs *engine;
2411 enum intel_engine_id id;
2414 seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2415 client->priority, client->ctx_index, client->proc_desc_offset);
2416 seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2417 client->doorbell_id, client->doorbell_offset, client->cookie);
2418 seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2419 client->wq_size, client->wq_offset, client->wq_tail);
2421 seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space);
2422 seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2423 seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2425 for_each_engine(engine, dev_priv, id) {
2426 u64 submissions = client->submissions[id];
2428 seq_printf(m, "\tSubmissions: %llu %s\n",
2429 submissions, engine->name);
2431 seq_printf(m, "\tTotal: %llu\n", tot);
2434 static int i915_guc_info(struct seq_file *m, void *data)
2436 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2437 struct drm_device *dev = &dev_priv->drm;
2438 struct intel_guc guc;
2439 struct i915_guc_client client = {};
2440 struct intel_engine_cs *engine;
2441 enum intel_engine_id id;
2444 if (!HAS_GUC_SCHED(dev_priv))
2447 if (mutex_lock_interruptible(&dev->struct_mutex))
2450 /* Take a local copy of the GuC data, so we can dump it at leisure */
2451 guc = dev_priv->guc;
2452 if (guc.execbuf_client)
2453 client = *guc.execbuf_client;
2455 mutex_unlock(&dev->struct_mutex);
2457 seq_printf(m, "Doorbell map:\n");
2458 seq_printf(m, "\t%*pb\n", GUC_MAX_DOORBELLS, guc.doorbell_bitmap);
2459 seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc.db_cacheline);
2461 seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
2462 seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
2463 seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
2464 seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
2465 seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
2467 seq_printf(m, "\nGuC submissions:\n");
2468 for_each_engine(engine, dev_priv, id) {
2469 u64 submissions = guc.submissions[id];
2470 total += submissions;
2471 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",
2472 engine->name, submissions, guc.last_seqno[id]);
2474 seq_printf(m, "\t%s: %llu\n", "Total", total);
2476 seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
2477 i915_guc_client_info(m, dev_priv, &client);
2479 i915_guc_log_info(m, dev_priv);
2481 /* Add more as required ... */
2486 static int i915_guc_log_dump(struct seq_file *m, void *data)
2488 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2489 struct drm_i915_gem_object *obj;
2492 if (!dev_priv->guc.log.vma)
2495 obj = dev_priv->guc.log.vma->obj;
2496 for (pg = 0; pg < obj->base.size / PAGE_SIZE; pg++) {
2497 u32 *log = kmap_atomic(i915_gem_object_get_page(obj, pg));
2499 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2500 seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2501 *(log + i), *(log + i + 1),
2502 *(log + i + 2), *(log + i + 3));
2512 static int i915_guc_log_control_get(void *data, u64 *val)
2514 struct drm_device *dev = data;
2515 struct drm_i915_private *dev_priv = to_i915(dev);
2517 if (!dev_priv->guc.log.vma)
2520 *val = i915.guc_log_level;
2525 static int i915_guc_log_control_set(void *data, u64 val)
2527 struct drm_device *dev = data;
2528 struct drm_i915_private *dev_priv = to_i915(dev);
2531 if (!dev_priv->guc.log.vma)
2534 ret = mutex_lock_interruptible(&dev->struct_mutex);
2538 intel_runtime_pm_get(dev_priv);
2539 ret = i915_guc_log_control(dev_priv, val);
2540 intel_runtime_pm_put(dev_priv);
2542 mutex_unlock(&dev->struct_mutex);
2546 DEFINE_SIMPLE_ATTRIBUTE(i915_guc_log_control_fops,
2547 i915_guc_log_control_get, i915_guc_log_control_set,
2550 static int i915_edp_psr_status(struct seq_file *m, void *data)
2552 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2556 bool enabled = false;
2558 if (!HAS_PSR(dev_priv)) {
2559 seq_puts(m, "PSR not supported\n");
2563 intel_runtime_pm_get(dev_priv);
2565 mutex_lock(&dev_priv->psr.lock);
2566 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2567 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2568 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2569 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2570 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2571 dev_priv->psr.busy_frontbuffer_bits);
2572 seq_printf(m, "Re-enable work scheduled: %s\n",
2573 yesno(work_busy(&dev_priv->psr.work.work)));
2575 if (HAS_DDI(dev_priv))
2576 enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2578 for_each_pipe(dev_priv, pipe) {
2579 enum transcoder cpu_transcoder =
2580 intel_pipe_to_cpu_transcoder(dev_priv, pipe);
2581 enum intel_display_power_domain power_domain;
2583 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
2584 if (!intel_display_power_get_if_enabled(dev_priv,
2588 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2589 VLV_EDP_PSR_CURR_STATE_MASK;
2590 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2591 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2594 intel_display_power_put(dev_priv, power_domain);
2598 seq_printf(m, "Main link in standby mode: %s\n",
2599 yesno(dev_priv->psr.link_standby));
2601 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2603 if (!HAS_DDI(dev_priv))
2604 for_each_pipe(dev_priv, pipe) {
2605 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2606 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2607 seq_printf(m, " pipe %c", pipe_name(pipe));
2612 * VLV/CHV PSR has no kind of performance counter
2613 * SKL+ Perf counter is reset to 0 everytime DC state is entered
2615 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2616 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
2617 EDP_PSR_PERF_CNT_MASK;
2619 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2621 mutex_unlock(&dev_priv->psr.lock);
2623 intel_runtime_pm_put(dev_priv);
2627 static int i915_sink_crc(struct seq_file *m, void *data)
2629 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2630 struct drm_device *dev = &dev_priv->drm;
2631 struct intel_connector *connector;
2632 struct intel_dp *intel_dp = NULL;
2636 drm_modeset_lock_all(dev);
2637 for_each_intel_connector(dev, connector) {
2638 struct drm_crtc *crtc;
2640 if (!connector->base.state->best_encoder)
2643 crtc = connector->base.state->crtc;
2644 if (!crtc->state->active)
2647 if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
2650 intel_dp = enc_to_intel_dp(connector->base.state->best_encoder);
2652 ret = intel_dp_sink_crc(intel_dp, crc);
2656 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2657 crc[0], crc[1], crc[2],
2658 crc[3], crc[4], crc[5]);
2663 drm_modeset_unlock_all(dev);
2667 static int i915_energy_uJ(struct seq_file *m, void *data)
2669 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2673 if (INTEL_GEN(dev_priv) < 6)
2676 intel_runtime_pm_get(dev_priv);
2678 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2679 power = (power & 0x1f00) >> 8;
2680 units = 1000000 / (1 << power); /* convert to uJ */
2681 power = I915_READ(MCH_SECP_NRG_STTS);
2684 intel_runtime_pm_put(dev_priv);
2686 seq_printf(m, "%llu", (long long unsigned)power);
2691 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2693 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2694 struct pci_dev *pdev = dev_priv->drm.pdev;
2696 if (!HAS_RUNTIME_PM(dev_priv))
2697 seq_puts(m, "Runtime power management not supported\n");
2699 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
2700 seq_printf(m, "IRQs disabled: %s\n",
2701 yesno(!intel_irqs_enabled(dev_priv)));
2703 seq_printf(m, "Usage count: %d\n",
2704 atomic_read(&dev_priv->drm.dev->power.usage_count));
2706 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2708 seq_printf(m, "PCI device power state: %s [%d]\n",
2709 pci_power_name(pdev->current_state),
2710 pdev->current_state);
2715 static int i915_power_domain_info(struct seq_file *m, void *unused)
2717 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2718 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2721 mutex_lock(&power_domains->lock);
2723 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2724 for (i = 0; i < power_domains->power_well_count; i++) {
2725 struct i915_power_well *power_well;
2726 enum intel_display_power_domain power_domain;
2728 power_well = &power_domains->power_wells[i];
2729 seq_printf(m, "%-25s %d\n", power_well->name,
2732 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2734 if (!(BIT(power_domain) & power_well->domains))
2737 seq_printf(m, " %-23s %d\n",
2738 intel_display_power_domain_str(power_domain),
2739 power_domains->domain_use_count[power_domain]);
2743 mutex_unlock(&power_domains->lock);
2748 static int i915_dmc_info(struct seq_file *m, void *unused)
2750 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2751 struct intel_csr *csr;
2753 if (!HAS_CSR(dev_priv)) {
2754 seq_puts(m, "not supported\n");
2758 csr = &dev_priv->csr;
2760 intel_runtime_pm_get(dev_priv);
2762 seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2763 seq_printf(m, "path: %s\n", csr->fw_path);
2765 if (!csr->dmc_payload)
2768 seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2769 CSR_VERSION_MINOR(csr->version));
2771 if (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6)) {
2772 seq_printf(m, "DC3 -> DC5 count: %d\n",
2773 I915_READ(SKL_CSR_DC3_DC5_COUNT));
2774 seq_printf(m, "DC5 -> DC6 count: %d\n",
2775 I915_READ(SKL_CSR_DC5_DC6_COUNT));
2776 } else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) {
2777 seq_printf(m, "DC3 -> DC5 count: %d\n",
2778 I915_READ(BXT_CSR_DC3_DC5_COUNT));
2782 seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2783 seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2784 seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2786 intel_runtime_pm_put(dev_priv);
2791 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2792 struct drm_display_mode *mode)
2796 for (i = 0; i < tabs; i++)
2799 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2800 mode->base.id, mode->name,
2801 mode->vrefresh, mode->clock,
2802 mode->hdisplay, mode->hsync_start,
2803 mode->hsync_end, mode->htotal,
2804 mode->vdisplay, mode->vsync_start,
2805 mode->vsync_end, mode->vtotal,
2806 mode->type, mode->flags);
2809 static void intel_encoder_info(struct seq_file *m,
2810 struct intel_crtc *intel_crtc,
2811 struct intel_encoder *intel_encoder)
2813 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2814 struct drm_device *dev = &dev_priv->drm;
2815 struct drm_crtc *crtc = &intel_crtc->base;
2816 struct intel_connector *intel_connector;
2817 struct drm_encoder *encoder;
2819 encoder = &intel_encoder->base;
2820 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2821 encoder->base.id, encoder->name);
2822 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2823 struct drm_connector *connector = &intel_connector->base;
2824 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2827 drm_get_connector_status_name(connector->status));
2828 if (connector->status == connector_status_connected) {
2829 struct drm_display_mode *mode = &crtc->mode;
2830 seq_printf(m, ", mode:\n");
2831 intel_seq_print_mode(m, 2, mode);
2838 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2840 struct drm_i915_private *dev_priv = node_to_i915(m->private);
2841 struct drm_device *dev = &dev_priv->drm;
2842 struct drm_crtc *crtc = &intel_crtc->base;
2843 struct intel_encoder *intel_encoder;
2844 struct drm_plane_state *plane_state = crtc->primary->state;
2845 struct drm_framebuffer *fb = plane_state->fb;
2848 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2849 fb->base.id, plane_state->src_x >> 16,
2850 plane_state->src_y >> 16, fb->width, fb->height);
2852 seq_puts(m, "\tprimary plane disabled\n");
2853 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2854 intel_encoder_info(m, intel_crtc, intel_encoder);
2857 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2859 struct drm_display_mode *mode = panel->fixed_mode;
2861 seq_printf(m, "\tfixed mode:\n");
2862 intel_seq_print_mode(m, 2, mode);
2865 static void intel_dp_info(struct seq_file *m,
2866 struct intel_connector *intel_connector)
2868 struct intel_encoder *intel_encoder = intel_connector->encoder;
2869 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2871 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2872 seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2873 if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
2874 intel_panel_info(m, &intel_connector->panel);
2876 drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports,
2880 static void intel_hdmi_info(struct seq_file *m,
2881 struct intel_connector *intel_connector)
2883 struct intel_encoder *intel_encoder = intel_connector->encoder;
2884 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2886 seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
2889 static void intel_lvds_info(struct seq_file *m,
2890 struct intel_connector *intel_connector)
2892 intel_panel_info(m, &intel_connector->panel);
2895 static void intel_connector_info(struct seq_file *m,
2896 struct drm_connector *connector)
2898 struct intel_connector *intel_connector = to_intel_connector(connector);
2899 struct intel_encoder *intel_encoder = intel_connector->encoder;
2900 struct drm_display_mode *mode;
2902 seq_printf(m, "connector %d: type %s, status: %s\n",
2903 connector->base.id, connector->name,
2904 drm_get_connector_status_name(connector->status));
2905 if (connector->status == connector_status_connected) {
2906 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2907 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2908 connector->display_info.width_mm,
2909 connector->display_info.height_mm);
2910 seq_printf(m, "\tsubpixel order: %s\n",
2911 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2912 seq_printf(m, "\tCEA rev: %d\n",
2913 connector->display_info.cea_rev);
2916 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
2919 switch (connector->connector_type) {
2920 case DRM_MODE_CONNECTOR_DisplayPort:
2921 case DRM_MODE_CONNECTOR_eDP:
2922 intel_dp_info(m, intel_connector);
2924 case DRM_MODE_CONNECTOR_LVDS:
2925 if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2926 intel_lvds_info(m, intel_connector);
2928 case DRM_MODE_CONNECTOR_HDMIA:
2929 if (intel_encoder->type == INTEL_OUTPUT_HDMI ||
2930 intel_encoder->type == INTEL_OUTPUT_UNKNOWN)
2931 intel_hdmi_info(m, intel_connector);
2937 seq_printf(m, "\tmodes:\n");
2938 list_for_each_entry(mode, &connector->modes, head)
2939 intel_seq_print_mode(m, 2, mode);
2942 static bool cursor_active(struct drm_i915_private *dev_priv, int pipe)
2946 if (IS_845G(dev_priv) || IS_I865G(dev_priv))
2947 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
2949 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2954 static bool cursor_position(struct drm_i915_private *dev_priv,
2955 int pipe, int *x, int *y)
2959 pos = I915_READ(CURPOS(pipe));
2961 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2962 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2965 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2966 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2969 return cursor_active(dev_priv, pipe);
2972 static const char *plane_type(enum drm_plane_type type)
2975 case DRM_PLANE_TYPE_OVERLAY:
2977 case DRM_PLANE_TYPE_PRIMARY:
2979 case DRM_PLANE_TYPE_CURSOR:
2982 * Deliberately omitting default: to generate compiler warnings
2983 * when a new drm_plane_type gets added.
2990 static const char *plane_rotation(unsigned int rotation)
2992 static char buf[48];
2994 * According to doc only one DRM_ROTATE_ is allowed but this
2995 * will print them all to visualize if the values are misused
2997 snprintf(buf, sizeof(buf),
2998 "%s%s%s%s%s%s(0x%08x)",
2999 (rotation & DRM_ROTATE_0) ? "0 " : "",
3000 (rotation & DRM_ROTATE_90) ? "90 " : "",
3001 (rotation & DRM_ROTATE_180) ? "180 " : "",
3002 (rotation & DRM_ROTATE_270) ? "270 " : "",
3003 (rotation & DRM_REFLECT_X) ? "FLIPX " : "",
3004 (rotation & DRM_REFLECT_Y) ? "FLIPY " : "",
3010 static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3012 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3013 struct drm_device *dev = &dev_priv->drm;
3014 struct intel_plane *intel_plane;
3016 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3017 struct drm_plane_state *state;
3018 struct drm_plane *plane = &intel_plane->base;
3019 struct drm_format_name_buf format_name;
3021 if (!plane->state) {
3022 seq_puts(m, "plane->state is NULL!\n");
3026 state = plane->state;
3029 drm_get_format_name(state->fb->pixel_format, &format_name);
3031 sprintf(format_name.str, "N/A");
3034 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3036 plane_type(intel_plane->base.type),
3037 state->crtc_x, state->crtc_y,
3038 state->crtc_w, state->crtc_h,
3039 (state->src_x >> 16),
3040 ((state->src_x & 0xffff) * 15625) >> 10,
3041 (state->src_y >> 16),
3042 ((state->src_y & 0xffff) * 15625) >> 10,
3043 (state->src_w >> 16),
3044 ((state->src_w & 0xffff) * 15625) >> 10,
3045 (state->src_h >> 16),
3046 ((state->src_h & 0xffff) * 15625) >> 10,
3048 plane_rotation(state->rotation));
3052 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3054 struct intel_crtc_state *pipe_config;
3055 int num_scalers = intel_crtc->num_scalers;
3058 pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3060 /* Not all platformas have a scaler */
3062 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3064 pipe_config->scaler_state.scaler_users,
3065 pipe_config->scaler_state.scaler_id);
3067 for (i = 0; i < num_scalers; i++) {
3068 struct intel_scaler *sc =
3069 &pipe_config->scaler_state.scalers[i];
3071 seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3072 i, yesno(sc->in_use), sc->mode);
3076 seq_puts(m, "\tNo scalers available on this platform\n");
3080 static int i915_display_info(struct seq_file *m, void *unused)
3082 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3083 struct drm_device *dev = &dev_priv->drm;
3084 struct intel_crtc *crtc;
3085 struct drm_connector *connector;
3087 intel_runtime_pm_get(dev_priv);
3088 drm_modeset_lock_all(dev);
3089 seq_printf(m, "CRTC info\n");
3090 seq_printf(m, "---------\n");
3091 for_each_intel_crtc(dev, crtc) {
3093 struct intel_crtc_state *pipe_config;
3096 pipe_config = to_intel_crtc_state(crtc->base.state);
3098 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3099 crtc->base.base.id, pipe_name(crtc->pipe),
3100 yesno(pipe_config->base.active),
3101 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3102 yesno(pipe_config->dither), pipe_config->pipe_bpp);
3104 if (pipe_config->base.active) {
3105 intel_crtc_info(m, crtc);
3107 active = cursor_position(dev_priv, crtc->pipe, &x, &y);
3108 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
3109 yesno(crtc->cursor_base),
3110 x, y, crtc->base.cursor->state->crtc_w,
3111 crtc->base.cursor->state->crtc_h,
3112 crtc->cursor_addr, yesno(active));
3113 intel_scaler_info(m, crtc);
3114 intel_plane_info(m, crtc);
3117 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3118 yesno(!crtc->cpu_fifo_underrun_disabled),
3119 yesno(!crtc->pch_fifo_underrun_disabled));
3122 seq_printf(m, "\n");
3123 seq_printf(m, "Connector info\n");
3124 seq_printf(m, "--------------\n");
3125 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3126 intel_connector_info(m, connector);
3128 drm_modeset_unlock_all(dev);
3129 intel_runtime_pm_put(dev_priv);
3134 static int i915_engine_info(struct seq_file *m, void *unused)
3136 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3137 struct intel_engine_cs *engine;
3138 enum intel_engine_id id;
3140 intel_runtime_pm_get(dev_priv);
3142 for_each_engine(engine, dev_priv, id) {
3143 struct intel_breadcrumbs *b = &engine->breadcrumbs;
3144 struct drm_i915_gem_request *rq;
3148 seq_printf(m, "%s\n", engine->name);
3149 seq_printf(m, "\tcurrent seqno %x, last %x, hangcheck %x [%d ms]\n",
3150 intel_engine_get_seqno(engine),
3151 intel_engine_last_submit(engine),
3152 engine->hangcheck.seqno,
3153 jiffies_to_msecs(jiffies - engine->hangcheck.action_timestamp));
3157 seq_printf(m, "\tRequests:\n");
3159 rq = list_first_entry(&engine->timeline->requests,
3160 struct drm_i915_gem_request, link);
3161 if (&rq->link != &engine->timeline->requests)
3162 print_request(m, rq, "\t\tfirst ");
3164 rq = list_last_entry(&engine->timeline->requests,
3165 struct drm_i915_gem_request, link);
3166 if (&rq->link != &engine->timeline->requests)
3167 print_request(m, rq, "\t\tlast ");
3169 rq = i915_gem_find_active_request(engine);
3171 print_request(m, rq, "\t\tactive ");
3173 "\t\t[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]\n",
3174 rq->head, rq->postfix, rq->tail,
3175 rq->batch ? upper_32_bits(rq->batch->node.start) : ~0u,
3176 rq->batch ? lower_32_bits(rq->batch->node.start) : ~0u);
3179 seq_printf(m, "\tRING_START: 0x%08x [0x%08x]\n",
3180 I915_READ(RING_START(engine->mmio_base)),
3181 rq ? i915_ggtt_offset(rq->ring->vma) : 0);
3182 seq_printf(m, "\tRING_HEAD: 0x%08x [0x%08x]\n",
3183 I915_READ(RING_HEAD(engine->mmio_base)) & HEAD_ADDR,
3184 rq ? rq->ring->head : 0);
3185 seq_printf(m, "\tRING_TAIL: 0x%08x [0x%08x]\n",
3186 I915_READ(RING_TAIL(engine->mmio_base)) & TAIL_ADDR,
3187 rq ? rq->ring->tail : 0);
3188 seq_printf(m, "\tRING_CTL: 0x%08x [%s]\n",
3189 I915_READ(RING_CTL(engine->mmio_base)),
3190 I915_READ(RING_CTL(engine->mmio_base)) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? "waiting" : "");
3194 addr = intel_engine_get_active_head(engine);
3195 seq_printf(m, "\tACTHD: 0x%08x_%08x\n",
3196 upper_32_bits(addr), lower_32_bits(addr));
3197 addr = intel_engine_get_last_batch_head(engine);
3198 seq_printf(m, "\tBBADDR: 0x%08x_%08x\n",
3199 upper_32_bits(addr), lower_32_bits(addr));
3201 if (i915.enable_execlists) {
3202 u32 ptr, read, write;
3205 seq_printf(m, "\tExeclist status: 0x%08x %08x\n",
3206 I915_READ(RING_EXECLIST_STATUS_LO(engine)),
3207 I915_READ(RING_EXECLIST_STATUS_HI(engine)));
3209 ptr = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
3210 read = GEN8_CSB_READ_PTR(ptr);
3211 write = GEN8_CSB_WRITE_PTR(ptr);
3212 seq_printf(m, "\tExeclist CSB read %d, write %d\n",
3214 if (read >= GEN8_CSB_ENTRIES)
3216 if (write >= GEN8_CSB_ENTRIES)
3219 write += GEN8_CSB_ENTRIES;
3220 while (read < write) {
3221 unsigned int idx = ++read % GEN8_CSB_ENTRIES;
3223 seq_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n",
3225 I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, idx)),
3226 I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, idx)));
3230 rq = READ_ONCE(engine->execlist_port[0].request);
3232 print_request(m, rq, "\t\tELSP[0] ");
3234 seq_printf(m, "\t\tELSP[0] idle\n");
3235 rq = READ_ONCE(engine->execlist_port[1].request);
3237 print_request(m, rq, "\t\tELSP[1] ");
3239 seq_printf(m, "\t\tELSP[1] idle\n");
3242 spin_lock_irq(&engine->timeline->lock);
3243 for (rb = engine->execlist_first; rb; rb = rb_next(rb)) {
3244 rq = rb_entry(rb, typeof(*rq), priotree.node);
3245 print_request(m, rq, "\t\tQ ");
3247 spin_unlock_irq(&engine->timeline->lock);
3248 } else if (INTEL_GEN(dev_priv) > 6) {
3249 seq_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
3250 I915_READ(RING_PP_DIR_BASE(engine)));
3251 seq_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n",
3252 I915_READ(RING_PP_DIR_BASE_READ(engine)));
3253 seq_printf(m, "\tPP_DIR_DCLV: 0x%08x\n",
3254 I915_READ(RING_PP_DIR_DCLV(engine)));
3257 spin_lock_irq(&b->lock);
3258 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
3259 struct intel_wait *w = container_of(rb, typeof(*w), node);
3261 seq_printf(m, "\t%s [%d] waiting for %x\n",
3262 w->tsk->comm, w->tsk->pid, w->seqno);
3264 spin_unlock_irq(&b->lock);
3269 intel_runtime_pm_put(dev_priv);
3274 static int i915_semaphore_status(struct seq_file *m, void *unused)
3276 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3277 struct drm_device *dev = &dev_priv->drm;
3278 struct intel_engine_cs *engine;
3279 int num_rings = INTEL_INFO(dev_priv)->num_rings;
3280 enum intel_engine_id id;
3283 if (!i915.semaphores) {
3284 seq_puts(m, "Semaphores are disabled\n");
3288 ret = mutex_lock_interruptible(&dev->struct_mutex);
3291 intel_runtime_pm_get(dev_priv);
3293 if (IS_BROADWELL(dev_priv)) {
3297 page = i915_gem_object_get_page(dev_priv->semaphore->obj, 0);
3299 seqno = (uint64_t *)kmap_atomic(page);
3300 for_each_engine(engine, dev_priv, id) {
3303 seq_printf(m, "%s\n", engine->name);
3305 seq_puts(m, " Last signal:");
3306 for (j = 0; j < num_rings; j++) {
3307 offset = id * I915_NUM_ENGINES + j;
3308 seq_printf(m, "0x%08llx (0x%02llx) ",
3309 seqno[offset], offset * 8);
3313 seq_puts(m, " Last wait: ");
3314 for (j = 0; j < num_rings; j++) {
3315 offset = id + (j * I915_NUM_ENGINES);
3316 seq_printf(m, "0x%08llx (0x%02llx) ",
3317 seqno[offset], offset * 8);
3322 kunmap_atomic(seqno);
3324 seq_puts(m, " Last signal:");
3325 for_each_engine(engine, dev_priv, id)
3326 for (j = 0; j < num_rings; j++)
3327 seq_printf(m, "0x%08x\n",
3328 I915_READ(engine->semaphore.mbox.signal[j]));
3332 intel_runtime_pm_put(dev_priv);
3333 mutex_unlock(&dev->struct_mutex);
3337 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3339 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3340 struct drm_device *dev = &dev_priv->drm;
3343 drm_modeset_lock_all(dev);
3344 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3345 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3347 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3348 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3349 pll->config.crtc_mask, pll->active_mask, yesno(pll->on));
3350 seq_printf(m, " tracked hardware state:\n");
3351 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
3352 seq_printf(m, " dpll_md: 0x%08x\n",
3353 pll->config.hw_state.dpll_md);
3354 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
3355 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
3356 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
3358 drm_modeset_unlock_all(dev);
3363 static int i915_wa_registers(struct seq_file *m, void *unused)
3367 struct intel_engine_cs *engine;
3368 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3369 struct drm_device *dev = &dev_priv->drm;
3370 struct i915_workarounds *workarounds = &dev_priv->workarounds;
3371 enum intel_engine_id id;
3373 ret = mutex_lock_interruptible(&dev->struct_mutex);
3377 intel_runtime_pm_get(dev_priv);
3379 seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
3380 for_each_engine(engine, dev_priv, id)
3381 seq_printf(m, "HW whitelist count for %s: %d\n",
3382 engine->name, workarounds->hw_whitelist_count[id]);
3383 for (i = 0; i < workarounds->count; ++i) {
3385 u32 mask, value, read;
3388 addr = workarounds->reg[i].addr;
3389 mask = workarounds->reg[i].mask;
3390 value = workarounds->reg[i].value;
3391 read = I915_READ(addr);
3392 ok = (value & mask) == (read & mask);
3393 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3394 i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
3397 intel_runtime_pm_put(dev_priv);
3398 mutex_unlock(&dev->struct_mutex);
3403 static int i915_ddb_info(struct seq_file *m, void *unused)
3405 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3406 struct drm_device *dev = &dev_priv->drm;
3407 struct skl_ddb_allocation *ddb;
3408 struct skl_ddb_entry *entry;
3412 if (INTEL_GEN(dev_priv) < 9)
3415 drm_modeset_lock_all(dev);
3417 ddb = &dev_priv->wm.skl_hw.ddb;
3419 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3421 for_each_pipe(dev_priv, pipe) {
3422 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3424 for_each_universal_plane(dev_priv, pipe, plane) {
3425 entry = &ddb->plane[pipe][plane];
3426 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
3427 entry->start, entry->end,
3428 skl_ddb_entry_size(entry));
3431 entry = &ddb->plane[pipe][PLANE_CURSOR];
3432 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
3433 entry->end, skl_ddb_entry_size(entry));
3436 drm_modeset_unlock_all(dev);
3441 static void drrs_status_per_crtc(struct seq_file *m,
3442 struct drm_device *dev,
3443 struct intel_crtc *intel_crtc)
3445 struct drm_i915_private *dev_priv = to_i915(dev);
3446 struct i915_drrs *drrs = &dev_priv->drrs;
3448 struct drm_connector *connector;
3450 drm_for_each_connector(connector, dev) {
3451 if (connector->state->crtc != &intel_crtc->base)
3454 seq_printf(m, "%s:\n", connector->name);
3457 if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3458 seq_puts(m, "\tVBT: DRRS_type: Static");
3459 else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3460 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3461 else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3462 seq_puts(m, "\tVBT: DRRS_type: None");
3464 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3466 seq_puts(m, "\n\n");
3468 if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3469 struct intel_panel *panel;
3471 mutex_lock(&drrs->mutex);
3472 /* DRRS Supported */
3473 seq_puts(m, "\tDRRS Supported: Yes\n");
3475 /* disable_drrs() will make drrs->dp NULL */
3477 seq_puts(m, "Idleness DRRS: Disabled");
3478 mutex_unlock(&drrs->mutex);
3482 panel = &drrs->dp->attached_connector->panel;
3483 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3484 drrs->busy_frontbuffer_bits);
3486 seq_puts(m, "\n\t\t");
3487 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3488 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3489 vrefresh = panel->fixed_mode->vrefresh;
3490 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3491 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3492 vrefresh = panel->downclock_mode->vrefresh;
3494 seq_printf(m, "DRRS_State: Unknown(%d)\n",
3495 drrs->refresh_rate_type);
3496 mutex_unlock(&drrs->mutex);
3499 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3501 seq_puts(m, "\n\t\t");
3502 mutex_unlock(&drrs->mutex);
3504 /* DRRS not supported. Print the VBT parameter*/
3505 seq_puts(m, "\tDRRS Supported : No");
3510 static int i915_drrs_status(struct seq_file *m, void *unused)
3512 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3513 struct drm_device *dev = &dev_priv->drm;
3514 struct intel_crtc *intel_crtc;
3515 int active_crtc_cnt = 0;
3517 drm_modeset_lock_all(dev);
3518 for_each_intel_crtc(dev, intel_crtc) {
3519 if (intel_crtc->base.state->active) {
3521 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt);
3523 drrs_status_per_crtc(m, dev, intel_crtc);
3526 drm_modeset_unlock_all(dev);
3528 if (!active_crtc_cnt)
3529 seq_puts(m, "No active crtc found\n");
3534 struct pipe_crc_info {
3536 struct drm_i915_private *dev_priv;
3540 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3542 struct drm_i915_private *dev_priv = node_to_i915(m->private);
3543 struct drm_device *dev = &dev_priv->drm;
3544 struct intel_encoder *intel_encoder;
3545 struct intel_digital_port *intel_dig_port;
3546 struct drm_connector *connector;
3548 drm_modeset_lock_all(dev);
3549 drm_for_each_connector(connector, dev) {
3550 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
3553 intel_encoder = intel_attached_encoder(connector);
3554 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
3557 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
3558 if (!intel_dig_port->dp.can_mst)
3561 seq_printf(m, "MST Source Port %c\n",
3562 port_name(intel_dig_port->port));
3563 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3565 drm_modeset_unlock_all(dev);
3569 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3571 struct pipe_crc_info *info = inode->i_private;
3572 struct drm_i915_private *dev_priv = info->dev_priv;
3573 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3575 if (info->pipe >= INTEL_INFO(dev_priv)->num_pipes)
3578 spin_lock_irq(&pipe_crc->lock);
3580 if (pipe_crc->opened) {
3581 spin_unlock_irq(&pipe_crc->lock);
3582 return -EBUSY; /* already open */
3585 pipe_crc->opened = true;
3586 filep->private_data = inode->i_private;
3588 spin_unlock_irq(&pipe_crc->lock);
3593 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3595 struct pipe_crc_info *info = inode->i_private;
3596 struct drm_i915_private *dev_priv = info->dev_priv;
3597 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3599 spin_lock_irq(&pipe_crc->lock);
3600 pipe_crc->opened = false;
3601 spin_unlock_irq(&pipe_crc->lock);
3606 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3607 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3608 /* account for \'0' */
3609 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3611 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
3613 assert_spin_locked(&pipe_crc->lock);
3614 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3615 INTEL_PIPE_CRC_ENTRIES_NR);
3619 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3622 struct pipe_crc_info *info = filep->private_data;
3623 struct drm_i915_private *dev_priv = info->dev_priv;
3624 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3625 char buf[PIPE_CRC_BUFFER_LEN];
3630 * Don't allow user space to provide buffers not big enough to hold
3633 if (count < PIPE_CRC_LINE_LEN)
3636 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
3639 /* nothing to read */
3640 spin_lock_irq(&pipe_crc->lock);
3641 while (pipe_crc_data_count(pipe_crc) == 0) {
3644 if (filep->f_flags & O_NONBLOCK) {
3645 spin_unlock_irq(&pipe_crc->lock);
3649 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3650 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3652 spin_unlock_irq(&pipe_crc->lock);
3657 /* We now have one or more entries to read */
3658 n_entries = count / PIPE_CRC_LINE_LEN;
3661 while (n_entries > 0) {
3662 struct intel_pipe_crc_entry *entry =
3663 &pipe_crc->entries[pipe_crc->tail];
3665 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3666 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3669 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3670 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3672 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3673 "%8u %8x %8x %8x %8x %8x\n",
3674 entry->frame, entry->crc[0],
3675 entry->crc[1], entry->crc[2],
3676 entry->crc[3], entry->crc[4]);
3678 spin_unlock_irq(&pipe_crc->lock);
3680 if (copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN))
3683 user_buf += PIPE_CRC_LINE_LEN;
3686 spin_lock_irq(&pipe_crc->lock);
3689 spin_unlock_irq(&pipe_crc->lock);
3694 static const struct file_operations i915_pipe_crc_fops = {
3695 .owner = THIS_MODULE,
3696 .open = i915_pipe_crc_open,
3697 .read = i915_pipe_crc_read,
3698 .release = i915_pipe_crc_release,
3701 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3703 .name = "i915_pipe_A_crc",
3707 .name = "i915_pipe_B_crc",
3711 .name = "i915_pipe_C_crc",
3716 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3719 struct drm_i915_private *dev_priv = to_i915(minor->dev);
3721 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3723 info->dev_priv = dev_priv;
3724 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3725 &i915_pipe_crc_fops);
3729 return drm_add_fake_info_node(minor, ent, info);
3732 static const char * const pipe_crc_sources[] = {
3745 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3747 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3748 return pipe_crc_sources[source];
3751 static int display_crc_ctl_show(struct seq_file *m, void *data)
3753 struct drm_i915_private *dev_priv = m->private;
3756 for (i = 0; i < I915_MAX_PIPES; i++)
3757 seq_printf(m, "%c %s\n", pipe_name(i),
3758 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3763 static int display_crc_ctl_open(struct inode *inode, struct file *file)
3765 return single_open(file, display_crc_ctl_show, inode->i_private);
3768 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3771 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3772 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3775 case INTEL_PIPE_CRC_SOURCE_PIPE:
3776 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3778 case INTEL_PIPE_CRC_SOURCE_NONE:
3788 static int i9xx_pipe_crc_auto_source(struct drm_i915_private *dev_priv,
3790 enum intel_pipe_crc_source *source)
3792 struct drm_device *dev = &dev_priv->drm;
3793 struct intel_encoder *encoder;
3794 struct intel_crtc *crtc;
3795 struct intel_digital_port *dig_port;
3798 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3800 drm_modeset_lock_all(dev);
3801 for_each_intel_encoder(dev, encoder) {
3802 if (!encoder->base.crtc)
3805 crtc = to_intel_crtc(encoder->base.crtc);
3807 if (crtc->pipe != pipe)
3810 switch (encoder->type) {
3811 case INTEL_OUTPUT_TVOUT:
3812 *source = INTEL_PIPE_CRC_SOURCE_TV;
3814 case INTEL_OUTPUT_DP:
3815 case INTEL_OUTPUT_EDP:
3816 dig_port = enc_to_dig_port(&encoder->base);
3817 switch (dig_port->port) {
3819 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3822 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3825 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3828 WARN(1, "nonexisting DP port %c\n",
3829 port_name(dig_port->port));
3837 drm_modeset_unlock_all(dev);
3842 static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
3844 enum intel_pipe_crc_source *source,
3847 bool need_stable_symbols = false;
3849 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3850 int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
3856 case INTEL_PIPE_CRC_SOURCE_PIPE:
3857 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3859 case INTEL_PIPE_CRC_SOURCE_DP_B:
3860 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3861 need_stable_symbols = true;
3863 case INTEL_PIPE_CRC_SOURCE_DP_C:
3864 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3865 need_stable_symbols = true;
3867 case INTEL_PIPE_CRC_SOURCE_DP_D:
3868 if (!IS_CHERRYVIEW(dev_priv))
3870 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3871 need_stable_symbols = true;
3873 case INTEL_PIPE_CRC_SOURCE_NONE:
3881 * When the pipe CRC tap point is after the transcoders we need
3882 * to tweak symbol-level features to produce a deterministic series of
3883 * symbols for a given frame. We need to reset those features only once
3884 * a frame (instead of every nth symbol):
3885 * - DC-balance: used to ensure a better clock recovery from the data
3887 * - DisplayPort scrambling: used for EMI reduction
3889 if (need_stable_symbols) {
3890 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3892 tmp |= DC_BALANCE_RESET_VLV;
3895 tmp |= PIPE_A_SCRAMBLE_RESET;
3898 tmp |= PIPE_B_SCRAMBLE_RESET;
3901 tmp |= PIPE_C_SCRAMBLE_RESET;
3906 I915_WRITE(PORT_DFT2_G4X, tmp);
3912 static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
3914 enum intel_pipe_crc_source *source,
3917 bool need_stable_symbols = false;
3919 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3920 int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
3926 case INTEL_PIPE_CRC_SOURCE_PIPE:
3927 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3929 case INTEL_PIPE_CRC_SOURCE_TV:
3930 if (!SUPPORTS_TV(dev_priv))
3932 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3934 case INTEL_PIPE_CRC_SOURCE_DP_B:
3935 if (!IS_G4X(dev_priv))
3937 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3938 need_stable_symbols = true;
3940 case INTEL_PIPE_CRC_SOURCE_DP_C:
3941 if (!IS_G4X(dev_priv))
3943 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3944 need_stable_symbols = true;
3946 case INTEL_PIPE_CRC_SOURCE_DP_D:
3947 if (!IS_G4X(dev_priv))
3949 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3950 need_stable_symbols = true;
3952 case INTEL_PIPE_CRC_SOURCE_NONE:
3960 * When the pipe CRC tap point is after the transcoders we need
3961 * to tweak symbol-level features to produce a deterministic series of
3962 * symbols for a given frame. We need to reset those features only once
3963 * a frame (instead of every nth symbol):
3964 * - DC-balance: used to ensure a better clock recovery from the data
3966 * - DisplayPort scrambling: used for EMI reduction
3968 if (need_stable_symbols) {
3969 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3971 WARN_ON(!IS_G4X(dev_priv));
3973 I915_WRITE(PORT_DFT_I9XX,
3974 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3977 tmp |= PIPE_A_SCRAMBLE_RESET;
3979 tmp |= PIPE_B_SCRAMBLE_RESET;
3981 I915_WRITE(PORT_DFT2_G4X, tmp);
3987 static void vlv_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
3990 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3994 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3997 tmp &= ~PIPE_B_SCRAMBLE_RESET;
4000 tmp &= ~PIPE_C_SCRAMBLE_RESET;
4005 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
4006 tmp &= ~DC_BALANCE_RESET_VLV;
4007 I915_WRITE(PORT_DFT2_G4X, tmp);
4011 static void g4x_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
4014 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
4017 tmp &= ~PIPE_A_SCRAMBLE_RESET;
4019 tmp &= ~PIPE_B_SCRAMBLE_RESET;
4020 I915_WRITE(PORT_DFT2_G4X, tmp);
4022 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
4023 I915_WRITE(PORT_DFT_I9XX,
4024 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
4028 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
4031 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
4032 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
4035 case INTEL_PIPE_CRC_SOURCE_PLANE1:
4036 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
4038 case INTEL_PIPE_CRC_SOURCE_PLANE2:
4039 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
4041 case INTEL_PIPE_CRC_SOURCE_PIPE:
4042 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
4044 case INTEL_PIPE_CRC_SOURCE_NONE:
4054 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_i915_private *dev_priv,
4057 struct drm_device *dev = &dev_priv->drm;
4058 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
4059 struct intel_crtc_state *pipe_config;
4060 struct drm_atomic_state *state;
4063 drm_modeset_lock_all(dev);
4064 state = drm_atomic_state_alloc(dev);
4070 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
4071 pipe_config = intel_atomic_get_crtc_state(state, crtc);
4072 if (IS_ERR(pipe_config)) {
4073 ret = PTR_ERR(pipe_config);
4077 pipe_config->pch_pfit.force_thru = enable;
4078 if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
4079 pipe_config->pch_pfit.enabled != enable)
4080 pipe_config->base.connectors_changed = true;
4082 ret = drm_atomic_commit(state);
4084 WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
4085 drm_modeset_unlock_all(dev);
4086 drm_atomic_state_put(state);
4089 static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
4091 enum intel_pipe_crc_source *source,
4094 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
4095 *source = INTEL_PIPE_CRC_SOURCE_PF;
4098 case INTEL_PIPE_CRC_SOURCE_PLANE1:
4099 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
4101 case INTEL_PIPE_CRC_SOURCE_PLANE2:
4102 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
4104 case INTEL_PIPE_CRC_SOURCE_PF:
4105 if (IS_HASWELL(dev_priv) && pipe == PIPE_A)
4106 hsw_trans_edp_pipe_A_crc_wa(dev_priv, true);
4108 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
4110 case INTEL_PIPE_CRC_SOURCE_NONE:
4120 static int pipe_crc_set_source(struct drm_i915_private *dev_priv,
4122 enum intel_pipe_crc_source source)
4124 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
4125 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
4126 enum intel_display_power_domain power_domain;
4127 u32 val = 0; /* shut up gcc */
4130 if (pipe_crc->source == source)
4133 /* forbid changing the source without going back to 'none' */
4134 if (pipe_crc->source && source)
4137 power_domain = POWER_DOMAIN_PIPE(pipe);
4138 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
4139 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
4143 if (IS_GEN2(dev_priv))
4144 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
4145 else if (INTEL_GEN(dev_priv) < 5)
4146 ret = i9xx_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val);
4147 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4148 ret = vlv_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val);
4149 else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv))
4150 ret = ilk_pipe_crc_ctl_reg(&source, &val);
4152 ret = ivb_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val);
4157 /* none -> real source transition */
4159 struct intel_pipe_crc_entry *entries;
4161 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4162 pipe_name(pipe), pipe_crc_source_name(source));
4164 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
4165 sizeof(pipe_crc->entries[0]),
4173 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4174 * enabled and disabled dynamically based on package C states,
4175 * user space can't make reliable use of the CRCs, so let's just
4176 * completely disable it.
4178 hsw_disable_ips(crtc);
4180 spin_lock_irq(&pipe_crc->lock);
4181 kfree(pipe_crc->entries);
4182 pipe_crc->entries = entries;
4185 spin_unlock_irq(&pipe_crc->lock);
4188 pipe_crc->source = source;
4190 I915_WRITE(PIPE_CRC_CTL(pipe), val);
4191 POSTING_READ(PIPE_CRC_CTL(pipe));
4193 /* real source -> none transition */
4194 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
4195 struct intel_pipe_crc_entry *entries;
4196 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
4199 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4202 drm_modeset_lock(&crtc->base.mutex, NULL);
4203 if (crtc->base.state->active)
4204 intel_wait_for_vblank(dev_priv, pipe);
4205 drm_modeset_unlock(&crtc->base.mutex);
4207 spin_lock_irq(&pipe_crc->lock);
4208 entries = pipe_crc->entries;
4209 pipe_crc->entries = NULL;
4212 spin_unlock_irq(&pipe_crc->lock);
4216 if (IS_G4X(dev_priv))
4217 g4x_undo_pipe_scramble_reset(dev_priv, pipe);
4218 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4219 vlv_undo_pipe_scramble_reset(dev_priv, pipe);
4220 else if (IS_HASWELL(dev_priv) && pipe == PIPE_A)
4221 hsw_trans_edp_pipe_A_crc_wa(dev_priv, false);
4223 hsw_enable_ips(crtc);
4229 intel_display_power_put(dev_priv, power_domain);
4235 * Parse pipe CRC command strings:
4236 * command: wsp* object wsp+ name wsp+ source wsp*
4239 * source: (none | plane1 | plane2 | pf)
4240 * wsp: (#0x20 | #0x9 | #0xA)+
4243 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
4244 * "pipe A none" -> Stop CRC
4246 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
4253 /* skip leading white space */
4254 buf = skip_spaces(buf);
4256 break; /* end of buffer */
4258 /* find end of word */
4259 for (end = buf; *end && !isspace(*end); end++)
4262 if (n_words == max_words) {
4263 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4265 return -EINVAL; /* ran out of words[] before bytes */
4270 words[n_words++] = buf;
4277 enum intel_pipe_crc_object {
4278 PIPE_CRC_OBJECT_PIPE,
4281 static const char * const pipe_crc_objects[] = {
4286 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
4290 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
4291 if (!strcmp(buf, pipe_crc_objects[i])) {
4299 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
4301 const char name = buf[0];
4303 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
4312 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
4316 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
4317 if (!strcmp(buf, pipe_crc_sources[i])) {
4325 static int display_crc_ctl_parse(struct drm_i915_private *dev_priv,
4326 char *buf, size_t len)
4330 char *words[N_WORDS];
4332 enum intel_pipe_crc_object object;
4333 enum intel_pipe_crc_source source;
4335 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
4336 if (n_words != N_WORDS) {
4337 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4342 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
4343 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
4347 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
4348 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
4352 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
4353 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
4357 return pipe_crc_set_source(dev_priv, pipe, source);
4360 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
4361 size_t len, loff_t *offp)
4363 struct seq_file *m = file->private_data;
4364 struct drm_i915_private *dev_priv = m->private;
4371 if (len > PAGE_SIZE - 1) {
4372 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4377 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
4381 if (copy_from_user(tmpbuf, ubuf, len)) {
4387 ret = display_crc_ctl_parse(dev_priv, tmpbuf, len);
4398 static const struct file_operations i915_display_crc_ctl_fops = {
4399 .owner = THIS_MODULE,
4400 .open = display_crc_ctl_open,
4402 .llseek = seq_lseek,
4403 .release = single_release,
4404 .write = display_crc_ctl_write
4407 static ssize_t i915_displayport_test_active_write(struct file *file,
4408 const char __user *ubuf,
4409 size_t len, loff_t *offp)
4413 struct drm_device *dev;
4414 struct drm_connector *connector;
4415 struct list_head *connector_list;
4416 struct intel_dp *intel_dp;
4419 dev = ((struct seq_file *)file->private_data)->private;
4421 connector_list = &dev->mode_config.connector_list;
4426 input_buffer = kmalloc(len + 1, GFP_KERNEL);
4430 if (copy_from_user(input_buffer, ubuf, len)) {
4435 input_buffer[len] = '\0';
4436 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4438 list_for_each_entry(connector, connector_list, head) {
4439 if (connector->connector_type !=
4440 DRM_MODE_CONNECTOR_DisplayPort)
4443 if (connector->status == connector_status_connected &&
4444 connector->encoder != NULL) {
4445 intel_dp = enc_to_intel_dp(connector->encoder);
4446 status = kstrtoint(input_buffer, 10, &val);
4449 DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4450 /* To prevent erroneous activation of the compliance
4451 * testing code, only accept an actual value of 1 here
4454 intel_dp->compliance_test_active = 1;
4456 intel_dp->compliance_test_active = 0;
4460 kfree(input_buffer);
4468 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4470 struct drm_device *dev = m->private;
4471 struct drm_connector *connector;
4472 struct list_head *connector_list = &dev->mode_config.connector_list;
4473 struct intel_dp *intel_dp;
4475 list_for_each_entry(connector, connector_list, head) {
4476 if (connector->connector_type !=
4477 DRM_MODE_CONNECTOR_DisplayPort)
4480 if (connector->status == connector_status_connected &&
4481 connector->encoder != NULL) {
4482 intel_dp = enc_to_intel_dp(connector->encoder);
4483 if (intel_dp->compliance_test_active)
4494 static int i915_displayport_test_active_open(struct inode *inode,
4497 struct drm_i915_private *dev_priv = inode->i_private;
4499 return single_open(file, i915_displayport_test_active_show,
4503 static const struct file_operations i915_displayport_test_active_fops = {
4504 .owner = THIS_MODULE,
4505 .open = i915_displayport_test_active_open,
4507 .llseek = seq_lseek,
4508 .release = single_release,
4509 .write = i915_displayport_test_active_write
4512 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4514 struct drm_device *dev = m->private;
4515 struct drm_connector *connector;
4516 struct list_head *connector_list = &dev->mode_config.connector_list;
4517 struct intel_dp *intel_dp;
4519 list_for_each_entry(connector, connector_list, head) {
4520 if (connector->connector_type !=
4521 DRM_MODE_CONNECTOR_DisplayPort)
4524 if (connector->status == connector_status_connected &&
4525 connector->encoder != NULL) {
4526 intel_dp = enc_to_intel_dp(connector->encoder);
4527 seq_printf(m, "%lx", intel_dp->compliance_test_data);
4534 static int i915_displayport_test_data_open(struct inode *inode,
4537 struct drm_i915_private *dev_priv = inode->i_private;
4539 return single_open(file, i915_displayport_test_data_show,
4543 static const struct file_operations i915_displayport_test_data_fops = {
4544 .owner = THIS_MODULE,
4545 .open = i915_displayport_test_data_open,
4547 .llseek = seq_lseek,
4548 .release = single_release
4551 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4553 struct drm_device *dev = m->private;
4554 struct drm_connector *connector;
4555 struct list_head *connector_list = &dev->mode_config.connector_list;
4556 struct intel_dp *intel_dp;
4558 list_for_each_entry(connector, connector_list, head) {
4559 if (connector->connector_type !=
4560 DRM_MODE_CONNECTOR_DisplayPort)
4563 if (connector->status == connector_status_connected &&
4564 connector->encoder != NULL) {
4565 intel_dp = enc_to_intel_dp(connector->encoder);
4566 seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4574 static int i915_displayport_test_type_open(struct inode *inode,
4577 struct drm_i915_private *dev_priv = inode->i_private;
4579 return single_open(file, i915_displayport_test_type_show,
4583 static const struct file_operations i915_displayport_test_type_fops = {
4584 .owner = THIS_MODULE,
4585 .open = i915_displayport_test_type_open,
4587 .llseek = seq_lseek,
4588 .release = single_release
4591 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
4593 struct drm_i915_private *dev_priv = m->private;
4594 struct drm_device *dev = &dev_priv->drm;
4598 if (IS_CHERRYVIEW(dev_priv))
4600 else if (IS_VALLEYVIEW(dev_priv))
4603 num_levels = ilk_wm_max_level(dev_priv) + 1;
4605 drm_modeset_lock_all(dev);
4607 for (level = 0; level < num_levels; level++) {
4608 unsigned int latency = wm[level];
4611 * - WM1+ latency values in 0.5us units
4612 * - latencies are in us on gen9/vlv/chv
4614 if (INTEL_GEN(dev_priv) >= 9 || IS_VALLEYVIEW(dev_priv) ||
4615 IS_CHERRYVIEW(dev_priv))
4620 seq_printf(m, "WM%d %u (%u.%u usec)\n",
4621 level, wm[level], latency / 10, latency % 10);
4624 drm_modeset_unlock_all(dev);
4627 static int pri_wm_latency_show(struct seq_file *m, void *data)
4629 struct drm_i915_private *dev_priv = m->private;
4630 const uint16_t *latencies;
4632 if (INTEL_GEN(dev_priv) >= 9)
4633 latencies = dev_priv->wm.skl_latency;
4635 latencies = dev_priv->wm.pri_latency;
4637 wm_latency_show(m, latencies);
4642 static int spr_wm_latency_show(struct seq_file *m, void *data)
4644 struct drm_i915_private *dev_priv = m->private;
4645 const uint16_t *latencies;
4647 if (INTEL_GEN(dev_priv) >= 9)
4648 latencies = dev_priv->wm.skl_latency;
4650 latencies = dev_priv->wm.spr_latency;
4652 wm_latency_show(m, latencies);
4657 static int cur_wm_latency_show(struct seq_file *m, void *data)
4659 struct drm_i915_private *dev_priv = m->private;
4660 const uint16_t *latencies;
4662 if (INTEL_GEN(dev_priv) >= 9)
4663 latencies = dev_priv->wm.skl_latency;
4665 latencies = dev_priv->wm.cur_latency;
4667 wm_latency_show(m, latencies);
4672 static int pri_wm_latency_open(struct inode *inode, struct file *file)
4674 struct drm_i915_private *dev_priv = inode->i_private;
4676 if (INTEL_GEN(dev_priv) < 5)
4679 return single_open(file, pri_wm_latency_show, dev_priv);
4682 static int spr_wm_latency_open(struct inode *inode, struct file *file)
4684 struct drm_i915_private *dev_priv = inode->i_private;
4686 if (HAS_GMCH_DISPLAY(dev_priv))
4689 return single_open(file, spr_wm_latency_show, dev_priv);
4692 static int cur_wm_latency_open(struct inode *inode, struct file *file)
4694 struct drm_i915_private *dev_priv = inode->i_private;
4696 if (HAS_GMCH_DISPLAY(dev_priv))
4699 return single_open(file, cur_wm_latency_show, dev_priv);
4702 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
4703 size_t len, loff_t *offp, uint16_t wm[8])
4705 struct seq_file *m = file->private_data;
4706 struct drm_i915_private *dev_priv = m->private;
4707 struct drm_device *dev = &dev_priv->drm;
4708 uint16_t new[8] = { 0 };
4714 if (IS_CHERRYVIEW(dev_priv))
4716 else if (IS_VALLEYVIEW(dev_priv))
4719 num_levels = ilk_wm_max_level(dev_priv) + 1;
4721 if (len >= sizeof(tmp))
4724 if (copy_from_user(tmp, ubuf, len))
4729 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4730 &new[0], &new[1], &new[2], &new[3],
4731 &new[4], &new[5], &new[6], &new[7]);
4732 if (ret != num_levels)
4735 drm_modeset_lock_all(dev);
4737 for (level = 0; level < num_levels; level++)
4738 wm[level] = new[level];
4740 drm_modeset_unlock_all(dev);
4746 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4747 size_t len, loff_t *offp)
4749 struct seq_file *m = file->private_data;
4750 struct drm_i915_private *dev_priv = m->private;
4751 uint16_t *latencies;
4753 if (INTEL_GEN(dev_priv) >= 9)
4754 latencies = dev_priv->wm.skl_latency;
4756 latencies = dev_priv->wm.pri_latency;
4758 return wm_latency_write(file, ubuf, len, offp, latencies);
4761 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4762 size_t len, loff_t *offp)
4764 struct seq_file *m = file->private_data;
4765 struct drm_i915_private *dev_priv = m->private;
4766 uint16_t *latencies;
4768 if (INTEL_GEN(dev_priv) >= 9)
4769 latencies = dev_priv->wm.skl_latency;
4771 latencies = dev_priv->wm.spr_latency;
4773 return wm_latency_write(file, ubuf, len, offp, latencies);
4776 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4777 size_t len, loff_t *offp)
4779 struct seq_file *m = file->private_data;
4780 struct drm_i915_private *dev_priv = m->private;
4781 uint16_t *latencies;
4783 if (INTEL_GEN(dev_priv) >= 9)
4784 latencies = dev_priv->wm.skl_latency;
4786 latencies = dev_priv->wm.cur_latency;
4788 return wm_latency_write(file, ubuf, len, offp, latencies);
4791 static const struct file_operations i915_pri_wm_latency_fops = {
4792 .owner = THIS_MODULE,
4793 .open = pri_wm_latency_open,
4795 .llseek = seq_lseek,
4796 .release = single_release,
4797 .write = pri_wm_latency_write
4800 static const struct file_operations i915_spr_wm_latency_fops = {
4801 .owner = THIS_MODULE,
4802 .open = spr_wm_latency_open,
4804 .llseek = seq_lseek,
4805 .release = single_release,
4806 .write = spr_wm_latency_write
4809 static const struct file_operations i915_cur_wm_latency_fops = {
4810 .owner = THIS_MODULE,
4811 .open = cur_wm_latency_open,
4813 .llseek = seq_lseek,
4814 .release = single_release,
4815 .write = cur_wm_latency_write
4819 i915_wedged_get(void *data, u64 *val)
4821 struct drm_i915_private *dev_priv = data;
4823 *val = i915_terminally_wedged(&dev_priv->gpu_error);
4829 i915_wedged_set(void *data, u64 val)
4831 struct drm_i915_private *dev_priv = data;
4834 * There is no safeguard against this debugfs entry colliding
4835 * with the hangcheck calling same i915_handle_error() in
4836 * parallel, causing an explosion. For now we assume that the
4837 * test harness is responsible enough not to inject gpu hangs
4838 * while it is writing to 'i915_wedged'
4841 if (i915_reset_in_progress(&dev_priv->gpu_error))
4844 i915_handle_error(dev_priv, val,
4845 "Manually setting wedged to %llu", val);
4850 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4851 i915_wedged_get, i915_wedged_set,
4855 i915_ring_missed_irq_get(void *data, u64 *val)
4857 struct drm_i915_private *dev_priv = data;
4859 *val = dev_priv->gpu_error.missed_irq_rings;
4864 i915_ring_missed_irq_set(void *data, u64 val)
4866 struct drm_i915_private *dev_priv = data;
4867 struct drm_device *dev = &dev_priv->drm;
4870 /* Lock against concurrent debugfs callers */
4871 ret = mutex_lock_interruptible(&dev->struct_mutex);
4874 dev_priv->gpu_error.missed_irq_rings = val;
4875 mutex_unlock(&dev->struct_mutex);
4880 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4881 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4885 i915_ring_test_irq_get(void *data, u64 *val)
4887 struct drm_i915_private *dev_priv = data;
4889 *val = dev_priv->gpu_error.test_irq_rings;
4895 i915_ring_test_irq_set(void *data, u64 val)
4897 struct drm_i915_private *dev_priv = data;
4899 val &= INTEL_INFO(dev_priv)->ring_mask;
4900 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4901 dev_priv->gpu_error.test_irq_rings = val;
4906 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4907 i915_ring_test_irq_get, i915_ring_test_irq_set,
4910 #define DROP_UNBOUND 0x1
4911 #define DROP_BOUND 0x2
4912 #define DROP_RETIRE 0x4
4913 #define DROP_ACTIVE 0x8
4914 #define DROP_FREED 0x10
4915 #define DROP_ALL (DROP_UNBOUND | \
4921 i915_drop_caches_get(void *data, u64 *val)
4929 i915_drop_caches_set(void *data, u64 val)
4931 struct drm_i915_private *dev_priv = data;
4932 struct drm_device *dev = &dev_priv->drm;
4935 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4937 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4938 * on ioctls on -EAGAIN. */
4939 ret = mutex_lock_interruptible(&dev->struct_mutex);
4943 if (val & DROP_ACTIVE) {
4944 ret = i915_gem_wait_for_idle(dev_priv,
4945 I915_WAIT_INTERRUPTIBLE |
4951 if (val & (DROP_RETIRE | DROP_ACTIVE))
4952 i915_gem_retire_requests(dev_priv);
4954 if (val & DROP_BOUND)
4955 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4957 if (val & DROP_UNBOUND)
4958 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4961 mutex_unlock(&dev->struct_mutex);
4963 if (val & DROP_FREED) {
4965 flush_work(&dev_priv->mm.free_work);
4971 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4972 i915_drop_caches_get, i915_drop_caches_set,
4976 i915_max_freq_get(void *data, u64 *val)
4978 struct drm_i915_private *dev_priv = data;
4980 if (INTEL_GEN(dev_priv) < 6)
4983 *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4988 i915_max_freq_set(void *data, u64 val)
4990 struct drm_i915_private *dev_priv = data;
4994 if (INTEL_GEN(dev_priv) < 6)
4997 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4999 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
5004 * Turbo will still be enabled, but won't go above the set value.
5006 val = intel_freq_opcode(dev_priv, val);
5008 hw_max = dev_priv->rps.max_freq;
5009 hw_min = dev_priv->rps.min_freq;
5011 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
5012 mutex_unlock(&dev_priv->rps.hw_lock);
5016 dev_priv->rps.max_freq_softlimit = val;
5018 intel_set_rps(dev_priv, val);
5020 mutex_unlock(&dev_priv->rps.hw_lock);
5025 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
5026 i915_max_freq_get, i915_max_freq_set,
5030 i915_min_freq_get(void *data, u64 *val)
5032 struct drm_i915_private *dev_priv = data;
5034 if (INTEL_GEN(dev_priv) < 6)
5037 *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
5042 i915_min_freq_set(void *data, u64 val)
5044 struct drm_i915_private *dev_priv = data;
5048 if (INTEL_GEN(dev_priv) < 6)
5051 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
5053 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
5058 * Turbo will still be enabled, but won't go below the set value.
5060 val = intel_freq_opcode(dev_priv, val);
5062 hw_max = dev_priv->rps.max_freq;
5063 hw_min = dev_priv->rps.min_freq;
5066 val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
5067 mutex_unlock(&dev_priv->rps.hw_lock);
5071 dev_priv->rps.min_freq_softlimit = val;
5073 intel_set_rps(dev_priv, val);
5075 mutex_unlock(&dev_priv->rps.hw_lock);
5080 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
5081 i915_min_freq_get, i915_min_freq_set,
5085 i915_cache_sharing_get(void *data, u64 *val)
5087 struct drm_i915_private *dev_priv = data;
5090 if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
5093 intel_runtime_pm_get(dev_priv);
5095 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5097 intel_runtime_pm_put(dev_priv);
5099 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
5105 i915_cache_sharing_set(void *data, u64 val)
5107 struct drm_i915_private *dev_priv = data;
5110 if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
5116 intel_runtime_pm_get(dev_priv);
5117 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
5119 /* Update the cache sharing policy here as well */
5120 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5121 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5122 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
5123 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5125 intel_runtime_pm_put(dev_priv);
5129 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
5130 i915_cache_sharing_get, i915_cache_sharing_set,
5133 static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
5134 struct sseu_dev_info *sseu)
5138 u32 sig1[ss_max], sig2[ss_max];
5140 sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
5141 sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
5142 sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
5143 sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
5145 for (ss = 0; ss < ss_max; ss++) {
5146 unsigned int eu_cnt;
5148 if (sig1[ss] & CHV_SS_PG_ENABLE)
5149 /* skip disabled subslice */
5152 sseu->slice_mask = BIT(0);
5153 sseu->subslice_mask |= BIT(ss);
5154 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
5155 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
5156 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
5157 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
5158 sseu->eu_total += eu_cnt;
5159 sseu->eu_per_subslice = max_t(unsigned int,
5160 sseu->eu_per_subslice, eu_cnt);
5164 static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
5165 struct sseu_dev_info *sseu)
5167 int s_max = 3, ss_max = 4;
5169 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
5171 /* BXT has a single slice and at most 3 subslices. */
5172 if (IS_BROXTON(dev_priv)) {
5177 for (s = 0; s < s_max; s++) {
5178 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
5179 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
5180 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
5183 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
5184 GEN9_PGCTL_SSA_EU19_ACK |
5185 GEN9_PGCTL_SSA_EU210_ACK |
5186 GEN9_PGCTL_SSA_EU311_ACK;
5187 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
5188 GEN9_PGCTL_SSB_EU19_ACK |
5189 GEN9_PGCTL_SSB_EU210_ACK |
5190 GEN9_PGCTL_SSB_EU311_ACK;
5192 for (s = 0; s < s_max; s++) {
5193 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
5194 /* skip disabled slice */
5197 sseu->slice_mask |= BIT(s);
5199 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
5200 sseu->subslice_mask =
5201 INTEL_INFO(dev_priv)->sseu.subslice_mask;
5203 for (ss = 0; ss < ss_max; ss++) {
5204 unsigned int eu_cnt;
5206 if (IS_BROXTON(dev_priv)) {
5207 if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
5208 /* skip disabled subslice */
5211 sseu->subslice_mask |= BIT(ss);
5214 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
5216 sseu->eu_total += eu_cnt;
5217 sseu->eu_per_subslice = max_t(unsigned int,
5218 sseu->eu_per_subslice,
5224 static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
5225 struct sseu_dev_info *sseu)
5227 u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
5230 sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK;
5232 if (sseu->slice_mask) {
5233 sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask;
5234 sseu->eu_per_subslice =
5235 INTEL_INFO(dev_priv)->sseu.eu_per_subslice;
5236 sseu->eu_total = sseu->eu_per_subslice *
5237 sseu_subslice_total(sseu);
5239 /* subtract fused off EU(s) from enabled slice(s) */
5240 for (s = 0; s < fls(sseu->slice_mask); s++) {
5242 INTEL_INFO(dev_priv)->sseu.subslice_7eu[s];
5244 sseu->eu_total -= hweight8(subslice_7eu);
5249 static void i915_print_sseu_info(struct seq_file *m, bool is_available_info,
5250 const struct sseu_dev_info *sseu)
5252 struct drm_i915_private *dev_priv = node_to_i915(m->private);
5253 const char *type = is_available_info ? "Available" : "Enabled";
5255 seq_printf(m, " %s Slice Mask: %04x\n", type,
5257 seq_printf(m, " %s Slice Total: %u\n", type,
5258 hweight8(sseu->slice_mask));
5259 seq_printf(m, " %s Subslice Total: %u\n", type,
5260 sseu_subslice_total(sseu));
5261 seq_printf(m, " %s Subslice Mask: %04x\n", type,
5262 sseu->subslice_mask);
5263 seq_printf(m, " %s Subslice Per Slice: %u\n", type,
5264 hweight8(sseu->subslice_mask));
5265 seq_printf(m, " %s EU Total: %u\n", type,
5267 seq_printf(m, " %s EU Per Subslice: %u\n", type,
5268 sseu->eu_per_subslice);
5270 if (!is_available_info)
5273 seq_printf(m, " Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv)));
5274 if (HAS_POOLED_EU(dev_priv))
5275 seq_printf(m, " Min EU in pool: %u\n", sseu->min_eu_in_pool);
5277 seq_printf(m, " Has Slice Power Gating: %s\n",
5278 yesno(sseu->has_slice_pg));
5279 seq_printf(m, " Has Subslice Power Gating: %s\n",
5280 yesno(sseu->has_subslice_pg));
5281 seq_printf(m, " Has EU Power Gating: %s\n",
5282 yesno(sseu->has_eu_pg));
5285 static int i915_sseu_status(struct seq_file *m, void *unused)
5287 struct drm_i915_private *dev_priv = node_to_i915(m->private);
5288 struct sseu_dev_info sseu;
5290 if (INTEL_GEN(dev_priv) < 8)
5293 seq_puts(m, "SSEU Device Info\n");
5294 i915_print_sseu_info(m, true, &INTEL_INFO(dev_priv)->sseu);
5296 seq_puts(m, "SSEU Device Status\n");
5297 memset(&sseu, 0, sizeof(sseu));
5299 intel_runtime_pm_get(dev_priv);
5301 if (IS_CHERRYVIEW(dev_priv)) {
5302 cherryview_sseu_device_status(dev_priv, &sseu);
5303 } else if (IS_BROADWELL(dev_priv)) {
5304 broadwell_sseu_device_status(dev_priv, &sseu);
5305 } else if (INTEL_GEN(dev_priv) >= 9) {
5306 gen9_sseu_device_status(dev_priv, &sseu);
5309 intel_runtime_pm_put(dev_priv);
5311 i915_print_sseu_info(m, false, &sseu);
5316 static int i915_forcewake_open(struct inode *inode, struct file *file)
5318 struct drm_i915_private *dev_priv = inode->i_private;
5320 if (INTEL_GEN(dev_priv) < 6)
5323 intel_runtime_pm_get(dev_priv);
5324 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5329 static int i915_forcewake_release(struct inode *inode, struct file *file)
5331 struct drm_i915_private *dev_priv = inode->i_private;
5333 if (INTEL_GEN(dev_priv) < 6)
5336 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5337 intel_runtime_pm_put(dev_priv);
5342 static const struct file_operations i915_forcewake_fops = {
5343 .owner = THIS_MODULE,
5344 .open = i915_forcewake_open,
5345 .release = i915_forcewake_release,
5348 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5352 ent = debugfs_create_file("i915_forcewake_user",
5354 root, to_i915(minor->dev),
5355 &i915_forcewake_fops);
5359 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
5362 static int i915_debugfs_create(struct dentry *root,
5363 struct drm_minor *minor,
5365 const struct file_operations *fops)
5369 ent = debugfs_create_file(name,
5371 root, to_i915(minor->dev),
5376 return drm_add_fake_info_node(minor, ent, fops);
5379 static const struct drm_info_list i915_debugfs_list[] = {
5380 {"i915_capabilities", i915_capabilities, 0},
5381 {"i915_gem_objects", i915_gem_object_info, 0},
5382 {"i915_gem_gtt", i915_gem_gtt_info, 0},
5383 {"i915_gem_pin_display", i915_gem_gtt_info, 0, (void *)1},
5384 {"i915_gem_stolen", i915_gem_stolen_list_info },
5385 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
5386 {"i915_gem_request", i915_gem_request_info, 0},
5387 {"i915_gem_seqno", i915_gem_seqno_info, 0},
5388 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
5389 {"i915_gem_interrupt", i915_interrupt_info, 0},
5390 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
5391 {"i915_guc_info", i915_guc_info, 0},
5392 {"i915_guc_load_status", i915_guc_load_status_info, 0},
5393 {"i915_guc_log_dump", i915_guc_log_dump, 0},
5394 {"i915_frequency_info", i915_frequency_info, 0},
5395 {"i915_hangcheck_info", i915_hangcheck_info, 0},
5396 {"i915_drpc_info", i915_drpc_info, 0},
5397 {"i915_emon_status", i915_emon_status, 0},
5398 {"i915_ring_freq_table", i915_ring_freq_table, 0},
5399 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
5400 {"i915_fbc_status", i915_fbc_status, 0},
5401 {"i915_ips_status", i915_ips_status, 0},
5402 {"i915_sr_status", i915_sr_status, 0},
5403 {"i915_opregion", i915_opregion, 0},
5404 {"i915_vbt", i915_vbt, 0},
5405 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
5406 {"i915_context_status", i915_context_status, 0},
5407 {"i915_dump_lrc", i915_dump_lrc, 0},
5408 {"i915_forcewake_domains", i915_forcewake_domains, 0},
5409 {"i915_swizzle_info", i915_swizzle_info, 0},
5410 {"i915_ppgtt_info", i915_ppgtt_info, 0},
5411 {"i915_llc", i915_llc, 0},
5412 {"i915_edp_psr_status", i915_edp_psr_status, 0},
5413 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
5414 {"i915_energy_uJ", i915_energy_uJ, 0},
5415 {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
5416 {"i915_power_domain_info", i915_power_domain_info, 0},
5417 {"i915_dmc_info", i915_dmc_info, 0},
5418 {"i915_display_info", i915_display_info, 0},
5419 {"i915_engine_info", i915_engine_info, 0},
5420 {"i915_semaphore_status", i915_semaphore_status, 0},
5421 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
5422 {"i915_dp_mst_info", i915_dp_mst_info, 0},
5423 {"i915_wa_registers", i915_wa_registers, 0},
5424 {"i915_ddb_info", i915_ddb_info, 0},
5425 {"i915_sseu_status", i915_sseu_status, 0},
5426 {"i915_drrs_status", i915_drrs_status, 0},
5427 {"i915_rps_boost_info", i915_rps_boost_info, 0},
5429 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5431 static const struct i915_debugfs_files {
5433 const struct file_operations *fops;
5434 } i915_debugfs_files[] = {
5435 {"i915_wedged", &i915_wedged_fops},
5436 {"i915_max_freq", &i915_max_freq_fops},
5437 {"i915_min_freq", &i915_min_freq_fops},
5438 {"i915_cache_sharing", &i915_cache_sharing_fops},
5439 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5440 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
5441 {"i915_gem_drop_caches", &i915_drop_caches_fops},
5442 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
5443 {"i915_error_state", &i915_error_state_fops},
5445 {"i915_next_seqno", &i915_next_seqno_fops},
5446 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
5447 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5448 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5449 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
5450 {"i915_fbc_false_color", &i915_fbc_fc_fops},
5451 {"i915_dp_test_data", &i915_displayport_test_data_fops},
5452 {"i915_dp_test_type", &i915_displayport_test_type_fops},
5453 {"i915_dp_test_active", &i915_displayport_test_active_fops},
5454 {"i915_guc_log_control", &i915_guc_log_control_fops}
5457 void intel_display_crc_init(struct drm_i915_private *dev_priv)
5461 for_each_pipe(dev_priv, pipe) {
5462 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
5464 pipe_crc->opened = false;
5465 spin_lock_init(&pipe_crc->lock);
5466 init_waitqueue_head(&pipe_crc->wq);
5470 int i915_debugfs_register(struct drm_i915_private *dev_priv)
5472 struct drm_minor *minor = dev_priv->drm.primary;
5475 ret = i915_forcewake_create(minor->debugfs_root, minor);
5479 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5480 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5485 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5486 ret = i915_debugfs_create(minor->debugfs_root, minor,
5487 i915_debugfs_files[i].name,
5488 i915_debugfs_files[i].fops);
5493 return drm_debugfs_create_files(i915_debugfs_list,
5494 I915_DEBUGFS_ENTRIES,
5495 minor->debugfs_root, minor);
5498 void i915_debugfs_unregister(struct drm_i915_private *dev_priv)
5500 struct drm_minor *minor = dev_priv->drm.primary;
5503 drm_debugfs_remove_files(i915_debugfs_list,
5504 I915_DEBUGFS_ENTRIES, minor);
5506 drm_debugfs_remove_files((struct drm_info_list *)&i915_forcewake_fops,
5509 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5510 struct drm_info_list *info_list =
5511 (struct drm_info_list *)&i915_pipe_crc_data[i];
5513 drm_debugfs_remove_files(info_list, 1, minor);
5516 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5517 struct drm_info_list *info_list =
5518 (struct drm_info_list *)i915_debugfs_files[i].fops;
5520 drm_debugfs_remove_files(info_list, 1, minor);
5525 /* DPCD dump start address. */
5526 unsigned int offset;
5527 /* DPCD dump end address, inclusive. If unset, .size will be used. */
5529 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5531 /* Only valid for eDP. */
5535 static const struct dpcd_block i915_dpcd_debug[] = {
5536 { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5537 { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5538 { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5539 { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5540 { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5541 { .offset = DP_SET_POWER },
5542 { .offset = DP_EDP_DPCD_REV },
5543 { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5544 { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5545 { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5548 static int i915_dpcd_show(struct seq_file *m, void *data)
5550 struct drm_connector *connector = m->private;
5551 struct intel_dp *intel_dp =
5552 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5557 if (connector->status != connector_status_connected)
5560 for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5561 const struct dpcd_block *b = &i915_dpcd_debug[i];
5562 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5565 connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5568 /* low tech for now */
5569 if (WARN_ON(size > sizeof(buf)))
5572 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5574 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5575 size, b->offset, err);
5579 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
5585 static int i915_dpcd_open(struct inode *inode, struct file *file)
5587 return single_open(file, i915_dpcd_show, inode->i_private);
5590 static const struct file_operations i915_dpcd_fops = {
5591 .owner = THIS_MODULE,
5592 .open = i915_dpcd_open,
5594 .llseek = seq_lseek,
5595 .release = single_release,
5598 static int i915_panel_show(struct seq_file *m, void *data)
5600 struct drm_connector *connector = m->private;
5601 struct intel_dp *intel_dp =
5602 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5604 if (connector->status != connector_status_connected)
5607 seq_printf(m, "Panel power up delay: %d\n",
5608 intel_dp->panel_power_up_delay);
5609 seq_printf(m, "Panel power down delay: %d\n",
5610 intel_dp->panel_power_down_delay);
5611 seq_printf(m, "Backlight on delay: %d\n",
5612 intel_dp->backlight_on_delay);
5613 seq_printf(m, "Backlight off delay: %d\n",
5614 intel_dp->backlight_off_delay);
5619 static int i915_panel_open(struct inode *inode, struct file *file)
5621 return single_open(file, i915_panel_show, inode->i_private);
5624 static const struct file_operations i915_panel_fops = {
5625 .owner = THIS_MODULE,
5626 .open = i915_panel_open,
5628 .llseek = seq_lseek,
5629 .release = single_release,
5633 * i915_debugfs_connector_add - add i915 specific connector debugfs files
5634 * @connector: pointer to a registered drm_connector
5636 * Cleanup will be done by drm_connector_unregister() through a call to
5637 * drm_debugfs_connector_remove().
5639 * Returns 0 on success, negative error codes on error.
5641 int i915_debugfs_connector_add(struct drm_connector *connector)
5643 struct dentry *root = connector->debugfs_entry;
5645 /* The connector must have been registered beforehands. */
5649 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5650 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5651 debugfs_create_file("i915_dpcd", S_IRUGO, root,
5652 connector, &i915_dpcd_fops);
5654 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5655 debugfs_create_file("i915_panel_timings", S_IRUGO, root,
5656 connector, &i915_panel_fops);