drivers/gpu/drm/i915/i915_debugfs.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *
  27  */
  28
  29 #include <linux/seq_file.h>
  30 #include <linux/circ_buf.h>
  31 #include <linux/ctype.h>
  32 #include <linux/debugfs.h>
  33 #include <linux/slab.h>
  34 #include <linux/export.h>
  35 #include <linux/list_sort.h>
  36 #include <asm/msr-index.h>
  37 #include <drm/drmP.h>
  38 #include "intel_drv.h"
  39 #include "intel_ringbuffer.h"
  40 #include <drm/i915_drm.h>
  41 #include "i915_drv.h"
  42
  43 static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
  44 {
  45         return to_i915(node->minor->dev);
  46 }
  47
  48 /* As the drm_debugfs_init() routines are called before dev->dev_private is
  49  * allocated we need to hook into the minor for release. */
  50 static int
  51 drm_add_fake_info_node(struct drm_minor *minor,
  52                        struct dentry *ent,
  53                        const void *key)
  54 {
  55         struct drm_info_node *node;
  56
  57         node = kmalloc(sizeof(*node), GFP_KERNEL);
  58         if (node == NULL) {
  59                 debugfs_remove(ent);
  60                 return -ENOMEM;
  61         }
  62
  63         node->minor = minor;
  64         node->dent = ent;
  65         node->info_ent = (void *)key;
  66
  67         mutex_lock(&minor->debugfs_lock);
  68         list_add(&node->list, &minor->debugfs_list);
  69         mutex_unlock(&minor->debugfs_lock);
  70
  71         return 0;
  72 }
  73
  74 static int i915_capabilities(struct seq_file *m, void *data)
  75 {
  76         struct drm_i915_private *dev_priv = node_to_i915(m->private);
  77         const struct intel_device_info *info = INTEL_INFO(dev_priv);
  78
  79         seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv));
  80         seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv));
  81 #define PRINT_FLAG(x)  seq_printf(m, #x ": %s\n", yesno(info->x))
  82         DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
  83 #undef PRINT_FLAG
  84
  85         return 0;
  86 }
  87
  88 static char get_active_flag(struct drm_i915_gem_object *obj)
  89 {
  90         return i915_gem_object_is_active(obj) ? '*' : ' ';
  91 }
  92
  93 static char get_pin_flag(struct drm_i915_gem_object *obj)
  94 {
  95         return obj->pin_display ? 'p' : ' ';
  96 }
  97
  98 static char get_tiling_flag(struct drm_i915_gem_object *obj)
  99 {
 100         switch (i915_gem_object_get_tiling(obj)) {
 101         default:
 102         case I915_TILING_NONE: return ' ';
 103         case I915_TILING_X: return 'X';
 104         case I915_TILING_Y: return 'Y';
 105         }
 106 }
 107
 108 static char get_global_flag(struct drm_i915_gem_object *obj)
 109 {
 110         return !list_empty(&obj->userfault_link) ? 'g' : ' ';
 111 }
 112
 113 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
 114 {
 115         return obj->mm.mapping ? 'M' : ' ';
 116 }
 117
 118 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
 119 {
 120         u64 size = 0;
 121         struct i915_vma *vma;
 122
 123         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 124                 if (i915_vma_is_ggtt(vma) && drm_mm_node_allocated(&vma->node))
 125                         size += vma->node.size;
 126         }
 127
 128         return size;
 129 }
 130
 131 static void
 132 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
 133 {
 134         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
 135         struct intel_engine_cs *engine;
 136         struct i915_vma *vma;
 137         unsigned int frontbuffer_bits;
 138         int pin_count = 0;
 139
 140         lockdep_assert_held(&obj->base.dev->struct_mutex);
 141
 142         seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x %s%s%s",
 143                    &obj->base,
 144                    get_active_flag(obj),
 145                    get_pin_flag(obj),
 146                    get_tiling_flag(obj),
 147                    get_global_flag(obj),
 148                    get_pin_mapped_flag(obj),
 149                    obj->base.size / 1024,
 150                    obj->base.read_domains,
 151                    obj->base.write_domain,
 152                    i915_cache_level_str(dev_priv, obj->cache_level),
 153                    obj->mm.dirty ? " dirty" : "",
 154                    obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : "");
 155         if (obj->base.name)
 156                 seq_printf(m, " (name: %d)", obj->base.name);
 157         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 158                 if (i915_vma_is_pinned(vma))
 159                         pin_count++;
 160         }
 161         seq_printf(m, " (pinned x %d)", pin_count);
 162         if (obj->pin_display)
 163                 seq_printf(m, " (display)");
 164         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 165                 if (!drm_mm_node_allocated(&vma->node))
 166                         continue;
 167
 168                 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
 169                            i915_vma_is_ggtt(vma) ? "g" : "pp",
 170                            vma->node.start, vma->node.size);
 171                 if (i915_vma_is_ggtt(vma))
 172                         seq_printf(m, ", type: %u", vma->ggtt_view.type);
 173                 if (vma->fence)
 174                         seq_printf(m, " , fence: %d%s",
 175                                    vma->fence->id,
 176                                    i915_gem_active_isset(&vma->last_fence) ? "*" : "");
 177                 seq_puts(m, ")");
 178         }
 179         if (obj->stolen)
 180                 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
 181
 182         engine = i915_gem_object_last_write_engine(obj);
 183         if (engine)
 184                 seq_printf(m, " (%s)", engine->name);
 185
 186         frontbuffer_bits = atomic_read(&obj->frontbuffer_bits);
 187         if (frontbuffer_bits)
 188                 seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits);
 189 }
 190
 191 static int obj_rank_by_stolen(void *priv,
 192                               struct list_head *A, struct list_head *B)
 193 {
 194         struct drm_i915_gem_object *a =
 195                 container_of(A, struct drm_i915_gem_object, obj_exec_link);
 196         struct drm_i915_gem_object *b =
 197                 container_of(B, struct drm_i915_gem_object, obj_exec_link);
 198
 199         if (a->stolen->start < b->stolen->start)
 200                 return -1;
 201         if (a->stolen->start > b->stolen->start)
 202                 return 1;
 203         return 0;
 204 }
 205
 206 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
 207 {
 208         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 209         struct drm_device *dev = &dev_priv->drm;
 210         struct drm_i915_gem_object *obj;
 211         u64 total_obj_size, total_gtt_size;
 212         LIST_HEAD(stolen);
 213         int count, ret;
 214
 215         ret = mutex_lock_interruptible(&dev->struct_mutex);
 216         if (ret)
 217                 return ret;
 218
 219         total_obj_size = total_gtt_size = count = 0;
 220         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) {
 221                 if (obj->stolen == NULL)
 222                         continue;
 223
 224                 list_add(&obj->obj_exec_link, &stolen);
 225
 226                 total_obj_size += obj->base.size;
 227                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 228                 count++;
 229         }
 230         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_link) {
 231                 if (obj->stolen == NULL)
 232                         continue;
 233
 234                 list_add(&obj->obj_exec_link, &stolen);
 235
 236                 total_obj_size += obj->base.size;
 237                 count++;
 238         }
 239         list_sort(NULL, &stolen, obj_rank_by_stolen);
 240         seq_puts(m, "Stolen:\n");
 241         while (!list_empty(&stolen)) {
 242                 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
 243                 seq_puts(m, "   ");
 244                 describe_obj(m, obj);
 245                 seq_putc(m, '\n');
 246                 list_del_init(&obj->obj_exec_link);
 247         }
 248         mutex_unlock(&dev->struct_mutex);
 249
 250         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 251                    count, total_obj_size, total_gtt_size);
 252         return 0;
 253 }
 254
 255 struct file_stats {
 256         struct drm_i915_file_private *file_priv;
 257         unsigned long count;
 258         u64 total, unbound;
 259         u64 global, shared;
 260         u64 active, inactive;
 261 };
 262
 263 static int per_file_stats(int id, void *ptr, void *data)
 264 {
 265         struct drm_i915_gem_object *obj = ptr;
 266         struct file_stats *stats = data;
 267         struct i915_vma *vma;
 268
 269         stats->count++;
 270         stats->total += obj->base.size;
 271         if (!obj->bind_count)
 272                 stats->unbound += obj->base.size;
 273         if (obj->base.name || obj->base.dma_buf)
 274                 stats->shared += obj->base.size;
 275
 276         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 277                 if (!drm_mm_node_allocated(&vma->node))
 278                         continue;
 279
 280                 if (i915_vma_is_ggtt(vma)) {
 281                         stats->global += vma->node.size;
 282                 } else {
 283                         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm);
 284
 285                         if (ppgtt->base.file != stats->file_priv)
 286                                 continue;
 287                 }
 288
 289                 if (i915_vma_is_active(vma))
 290                         stats->active += vma->node.size;
 291                 else
 292                         stats->inactive += vma->node.size;
 293         }
 294
 295         return 0;
 296 }
 297
 298 #define print_file_stats(m, name, stats) do { \
 299         if (stats.count) \
 300                 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
 301                            name, \
 302                            stats.count, \
 303                            stats.total, \
 304                            stats.active, \
 305                            stats.inactive, \
 306                            stats.global, \
 307                            stats.shared, \
 308                            stats.unbound); \
 309 } while (0)
 310
 311 static void print_batch_pool_stats(struct seq_file *m,
 312                                    struct drm_i915_private *dev_priv)
 313 {
 314         struct drm_i915_gem_object *obj;
 315         struct file_stats stats;
 316         struct intel_engine_cs *engine;
 317         enum intel_engine_id id;
 318         int j;
 319
 320         memset(&stats, 0, sizeof(stats));
 321
 322         for_each_engine(engine, dev_priv, id) {
 323                 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
 324                         list_for_each_entry(obj,
 325                                             &engine->batch_pool.cache_list[j],
 326                                             batch_pool_link)
 327                                 per_file_stats(0, obj, &stats);
 328                 }
 329         }
 330
 331         print_file_stats(m, "[k]batch pool", stats);
 332 }
 333
 334 static int per_file_ctx_stats(int id, void *ptr, void *data)
 335 {
 336         struct i915_gem_context *ctx = ptr;
 337         int n;
 338
 339         for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) {
 340                 if (ctx->engine[n].state)
 341                         per_file_stats(0, ctx->engine[n].state->obj, data);
 342                 if (ctx->engine[n].ring)
 343                         per_file_stats(0, ctx->engine[n].ring->vma->obj, data);
 344         }
 345
 346         return 0;
 347 }
 348
 349 static void print_context_stats(struct seq_file *m,
 350                                 struct drm_i915_private *dev_priv)
 351 {
 352         struct drm_device *dev = &dev_priv->drm;
 353         struct file_stats stats;
 354         struct drm_file *file;
 355
 356         memset(&stats, 0, sizeof(stats));
 357
 358         mutex_lock(&dev->struct_mutex);
 359         if (dev_priv->kernel_context)
 360                 per_file_ctx_stats(0, dev_priv->kernel_context, &stats);
 361
 362         list_for_each_entry(file, &dev->filelist, lhead) {
 363                 struct drm_i915_file_private *fpriv = file->driver_priv;
 364                 idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats);
 365         }
 366         mutex_unlock(&dev->struct_mutex);
 367
 368         print_file_stats(m, "[k]contexts", stats);
 369 }
 370
 371 static int i915_gem_object_info(struct seq_file *m, void *data)
 372 {
 373         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 374         struct drm_device *dev = &dev_priv->drm;
 375         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 376         u32 count, mapped_count, purgeable_count, dpy_count;
 377         u64 size, mapped_size, purgeable_size, dpy_size;
 378         struct drm_i915_gem_object *obj;
 379         struct drm_file *file;
 380         int ret;
 381
 382         ret = mutex_lock_interruptible(&dev->struct_mutex);
 383         if (ret)
 384                 return ret;
 385
 386         seq_printf(m, "%u objects, %llu bytes\n",
 387                    dev_priv->mm.object_count,
 388                    dev_priv->mm.object_memory);
 389
 390         size = count = 0;
 391         mapped_size = mapped_count = 0;
 392         purgeable_size = purgeable_count = 0;
 393         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_link) {
 394                 size += obj->base.size;
 395                 ++count;
 396
 397                 if (obj->mm.madv == I915_MADV_DONTNEED) {
 398                         purgeable_size += obj->base.size;
 399                         ++purgeable_count;
 400                 }
 401
 402                 if (obj->mm.mapping) {
 403                         mapped_count++;
 404                         mapped_size += obj->base.size;
 405                 }
 406         }
 407         seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
 408
 409         size = count = dpy_size = dpy_count = 0;
 410         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) {
 411                 size += obj->base.size;
 412                 ++count;
 413
 414                 if (obj->pin_display) {
 415                         dpy_size += obj->base.size;
 416                         ++dpy_count;
 417                 }
 418
 419                 if (obj->mm.madv == I915_MADV_DONTNEED) {
 420                         purgeable_size += obj->base.size;
 421                         ++purgeable_count;
 422                 }
 423
 424                 if (obj->mm.mapping) {
 425                         mapped_count++;
 426                         mapped_size += obj->base.size;
 427                 }
 428         }
 429         seq_printf(m, "%u bound objects, %llu bytes\n",
 430                    count, size);
 431         seq_printf(m, "%u purgeable objects, %llu bytes\n",
 432                    purgeable_count, purgeable_size);
 433         seq_printf(m, "%u mapped objects, %llu bytes\n",
 434                    mapped_count, mapped_size);
 435         seq_printf(m, "%u display objects (pinned), %llu bytes\n",
 436                    dpy_count, dpy_size);
 437
 438         seq_printf(m, "%llu [%llu] gtt total\n",
 439                    ggtt->base.total, ggtt->mappable_end - ggtt->base.start);
 440
 441         seq_putc(m, '\n');
 442         print_batch_pool_stats(m, dev_priv);
 443         mutex_unlock(&dev->struct_mutex);
 444
 445         mutex_lock(&dev->filelist_mutex);
 446         print_context_stats(m, dev_priv);
 447         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
 448                 struct file_stats stats;
 449                 struct drm_i915_file_private *file_priv = file->driver_priv;
 450                 struct drm_i915_gem_request *request;
 451                 struct task_struct *task;
 452
 453                 memset(&stats, 0, sizeof(stats));
 454                 stats.file_priv = file->driver_priv;
 455                 spin_lock(&file->table_lock);
 456                 idr_for_each(&file->object_idr, per_file_stats, &stats);
 457                 spin_unlock(&file->table_lock);
 458                 /*
 459                  * Although we have a valid reference on file->pid, that does
 460                  * not guarantee that the task_struct who called get_pid() is
 461                  * still alive (e.g. get_pid(current) => fork() => exit()).
 462                  * Therefore, we need to protect this ->comm access using RCU.
 463                  */
 464                 mutex_lock(&dev->struct_mutex);
 465                 request = list_first_entry_or_null(&file_priv->mm.request_list,
 466                                                    struct drm_i915_gem_request,
 467                                                    client_list);
 468                 rcu_read_lock();
 469                 task = pid_task(request && request->ctx->pid ?
 470                                 request->ctx->pid : file->pid,
 471                                 PIDTYPE_PID);
 472                 print_file_stats(m, task ? task->comm : "<unknown>", stats);
 473                 rcu_read_unlock();
 474                 mutex_unlock(&dev->struct_mutex);
 475         }
 476         mutex_unlock(&dev->filelist_mutex);
 477
 478         return 0;
 479 }
 480
 481 static int i915_gem_gtt_info(struct seq_file *m, void *data)
 482 {
 483         struct drm_info_node *node = m->private;
 484         struct drm_i915_private *dev_priv = node_to_i915(node);
 485         struct drm_device *dev = &dev_priv->drm;
 486         bool show_pin_display_only = !!node->info_ent->data;
 487         struct drm_i915_gem_object *obj;
 488         u64 total_obj_size, total_gtt_size;
 489         int count, ret;
 490
 491         ret = mutex_lock_interruptible(&dev->struct_mutex);
 492         if (ret)
 493                 return ret;
 494
 495         total_obj_size = total_gtt_size = count = 0;
 496         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_link) {
 497                 if (show_pin_display_only && !obj->pin_display)
 498                         continue;
 499
 500                 seq_puts(m, "   ");
 501                 describe_obj(m, obj);
 502                 seq_putc(m, '\n');
 503                 total_obj_size += obj->base.size;
 504                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 505                 count++;
 506         }
 507
 508         mutex_unlock(&dev->struct_mutex);
 509
 510         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 511                    count, total_obj_size, total_gtt_size);
 512
 513         return 0;
 514 }
 515
 516 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
 517 {
 518         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 519         struct drm_device *dev = &dev_priv->drm;
 520         struct intel_crtc *crtc;
 521         int ret;
 522
 523         ret = mutex_lock_interruptible(&dev->struct_mutex);
 524         if (ret)
 525                 return ret;
 526
 527         for_each_intel_crtc(dev, crtc) {
 528                 const char pipe = pipe_name(crtc->pipe);
 529                 const char plane = plane_name(crtc->plane);
 530                 struct intel_flip_work *work;
 531
 532                 spin_lock_irq(&dev->event_lock);
 533                 work = crtc->flip_work;
 534                 if (work == NULL) {
 535                         seq_printf(m, "No flip due on pipe %c (plane %c)\n",
 536                                    pipe, plane);
 537                 } else {
 538                         u32 pending;
 539                         u32 addr;
 540
 541                         pending = atomic_read(&work->pending);
 542                         if (pending) {
 543                                 seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n",
 544                                            pipe, plane);
 545                         } else {
 546                                 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
 547                                            pipe, plane);
 548                         }
 549                         if (work->flip_queued_req) {
 550                                 struct intel_engine_cs *engine = work->flip_queued_req->engine;
 551
 552                                 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
 553                                            engine->name,
 554                                            work->flip_queued_req->global_seqno,
 555                                            atomic_read(&dev_priv->gt.global_timeline.next_seqno),
 556                                            intel_engine_get_seqno(engine),
 557                                            i915_gem_request_completed(work->flip_queued_req));
 558                         } else
 559                                 seq_printf(m, "Flip not associated with any ring\n");
 560                         seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
 561                                    work->flip_queued_vblank,
 562                                    work->flip_ready_vblank,
 563                                    intel_crtc_get_vblank_counter(crtc));
 564                         seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
 565
 566                         if (INTEL_GEN(dev_priv) >= 4)
 567                                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
 568                         else
 569                                 addr = I915_READ(DSPADDR(crtc->plane));
 570                         seq_printf(m, "Current scanout address 0x%08x\n", addr);
 571
 572                         if (work->pending_flip_obj) {
 573                                 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
 574                                 seq_printf(m, "MMIO update completed? %d\n",  addr == work->gtt_offset);
 575                         }
 576                 }
 577                 spin_unlock_irq(&dev->event_lock);
 578         }
 579
 580         mutex_unlock(&dev->struct_mutex);
 581
 582         return 0;
 583 }
 584
 585 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
 586 {
 587         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 588         struct drm_device *dev = &dev_priv->drm;
 589         struct drm_i915_gem_object *obj;
 590         struct intel_engine_cs *engine;
 591         enum intel_engine_id id;
 592         int total = 0;
 593         int ret, j;
 594
 595         ret = mutex_lock_interruptible(&dev->struct_mutex);
 596         if (ret)
 597                 return ret;
 598
 599         for_each_engine(engine, dev_priv, id) {
 600                 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
 601                         int count;
 602
 603                         count = 0;
 604                         list_for_each_entry(obj,
 605                                             &engine->batch_pool.cache_list[j],
 606                                             batch_pool_link)
 607                                 count++;
 608                         seq_printf(m, "%s cache[%d]: %d objects\n",
 609                                    engine->name, j, count);
 610
 611                         list_for_each_entry(obj,
 612                                             &engine->batch_pool.cache_list[j],
 613                                             batch_pool_link) {
 614                                 seq_puts(m, "   ");
 615                                 describe_obj(m, obj);
 616                                 seq_putc(m, '\n');
 617                         }
 618
 619                         total += count;
 620                 }
 621         }
 622
 623         seq_printf(m, "total: %d\n", total);
 624
 625         mutex_unlock(&dev->struct_mutex);
 626
 627         return 0;
 628 }
 629
 630 static void print_request(struct seq_file *m,
 631                           struct drm_i915_gem_request *rq,
 632                           const char *prefix)
 633 {
 634         seq_printf(m, "%s%x [%x:%x] prio=%d @ %dms: %s\n", prefix,
 635                    rq->global_seqno, rq->ctx->hw_id, rq->fence.seqno,
 636                    rq->priotree.priority,
 637                    jiffies_to_msecs(jiffies - rq->emitted_jiffies),
 638                    rq->timeline->common->name);
 639 }
 640
 641 static int i915_gem_request_info(struct seq_file *m, void *data)
 642 {
 643         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 644         struct drm_device *dev = &dev_priv->drm;
 645         struct drm_i915_gem_request *req;
 646         struct intel_engine_cs *engine;
 647         enum intel_engine_id id;
 648         int ret, any;
 649
 650         ret = mutex_lock_interruptible(&dev->struct_mutex);
 651         if (ret)
 652                 return ret;
 653
 654         any = 0;
 655         for_each_engine(engine, dev_priv, id) {
 656                 int count;
 657
 658                 count = 0;
 659                 list_for_each_entry(req, &engine->timeline->requests, link)
 660                         count++;
 661                 if (count == 0)
 662                         continue;
 663
 664                 seq_printf(m, "%s requests: %d\n", engine->name, count);
 665                 list_for_each_entry(req, &engine->timeline->requests, link)
 666                         print_request(m, req, "    ");
 667
 668                 any++;
 669         }
 670         mutex_unlock(&dev->struct_mutex);
 671
 672         if (any == 0)
 673                 seq_puts(m, "No requests\n");
 674
 675         return 0;
 676 }
 677
 678 static void i915_ring_seqno_info(struct seq_file *m,
 679                                  struct intel_engine_cs *engine)
 680 {
 681         struct intel_breadcrumbs *b = &engine->breadcrumbs;
 682         struct rb_node *rb;
 683
 684         seq_printf(m, "Current sequence (%s): %x\n",
 685                    engine->name, intel_engine_get_seqno(engine));
 686
 687         spin_lock_irq(&b->lock);
 688         for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
 689                 struct intel_wait *w = container_of(rb, typeof(*w), node);
 690
 691                 seq_printf(m, "Waiting (%s): %s [%d] on %x\n",
 692                            engine->name, w->tsk->comm, w->tsk->pid, w->seqno);
 693         }
 694         spin_unlock_irq(&b->lock);
 695 }
 696
 697 static int i915_gem_seqno_info(struct seq_file *m, void *data)
 698 {
 699         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 700         struct intel_engine_cs *engine;
 701         enum intel_engine_id id;
 702
 703         for_each_engine(engine, dev_priv, id)
 704                 i915_ring_seqno_info(m, engine);
 705
 706         return 0;
 707 }
 708
 709
 710 static int i915_interrupt_info(struct seq_file *m, void *data)
 711 {
 712         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 713         struct intel_engine_cs *engine;
 714         enum intel_engine_id id;
 715         int i, pipe;
 716
 717         intel_runtime_pm_get(dev_priv);
 718
 719         if (IS_CHERRYVIEW(dev_priv)) {
 720                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 721                            I915_READ(GEN8_MASTER_IRQ));
 722
 723                 seq_printf(m, "Display IER:\t%08x\n",
 724                            I915_READ(VLV_IER));
 725                 seq_printf(m, "Display IIR:\t%08x\n",
 726                            I915_READ(VLV_IIR));
 727                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 728                            I915_READ(VLV_IIR_RW));
 729                 seq_printf(m, "Display IMR:\t%08x\n",
 730                            I915_READ(VLV_IMR));
 731                 for_each_pipe(dev_priv, pipe) {
 732                         enum intel_display_power_domain power_domain;
 733
 734                         power_domain = POWER_DOMAIN_PIPE(pipe);
 735                         if (!intel_display_power_get_if_enabled(dev_priv,
 736                                                                 power_domain)) {
 737                                 seq_printf(m, "Pipe %c power disabled\n",
 738                                            pipe_name(pipe));
 739                                 continue;
 740                         }
 741
 742                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 743                                    pipe_name(pipe),
 744                                    I915_READ(PIPESTAT(pipe)));
 745
 746                         intel_display_power_put(dev_priv, power_domain);
 747                 }
 748
 749                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 750                 seq_printf(m, "Port hotplug:\t%08x\n",
 751                            I915_READ(PORT_HOTPLUG_EN));
 752                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 753                            I915_READ(VLV_DPFLIPSTAT));
 754                 seq_printf(m, "DPINVGTT:\t%08x\n",
 755                            I915_READ(DPINVGTT));
 756                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 757
 758                 for (i = 0; i < 4; i++) {
 759                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 760                                    i, I915_READ(GEN8_GT_IMR(i)));
 761                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 762                                    i, I915_READ(GEN8_GT_IIR(i)));
 763                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 764                                    i, I915_READ(GEN8_GT_IER(i)));
 765                 }
 766
 767                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 768                            I915_READ(GEN8_PCU_IMR));
 769                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 770                            I915_READ(GEN8_PCU_IIR));
 771                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 772                            I915_READ(GEN8_PCU_IER));
 773         } else if (INTEL_GEN(dev_priv) >= 8) {
 774                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 775                            I915_READ(GEN8_MASTER_IRQ));
 776
 777                 for (i = 0; i < 4; i++) {
 778                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 779                                    i, I915_READ(GEN8_GT_IMR(i)));
 780                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 781                                    i, I915_READ(GEN8_GT_IIR(i)));
 782                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 783                                    i, I915_READ(GEN8_GT_IER(i)));
 784                 }
 785
 786                 for_each_pipe(dev_priv, pipe) {
 787                         enum intel_display_power_domain power_domain;
 788
 789                         power_domain = POWER_DOMAIN_PIPE(pipe);
 790                         if (!intel_display_power_get_if_enabled(dev_priv,
 791                                                                 power_domain)) {
 792                                 seq_printf(m, "Pipe %c power disabled\n",
 793                                            pipe_name(pipe));
 794                                 continue;
 795                         }
 796                         seq_printf(m, "Pipe %c IMR:\t%08x\n",
 797                                    pipe_name(pipe),
 798                                    I915_READ(GEN8_DE_PIPE_IMR(pipe)));
 799                         seq_printf(m, "Pipe %c IIR:\t%08x\n",
 800                                    pipe_name(pipe),
 801                                    I915_READ(GEN8_DE_PIPE_IIR(pipe)));
 802                         seq_printf(m, "Pipe %c IER:\t%08x\n",
 803                                    pipe_name(pipe),
 804                                    I915_READ(GEN8_DE_PIPE_IER(pipe)));
 805
 806                         intel_display_power_put(dev_priv, power_domain);
 807                 }
 808
 809                 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
 810                            I915_READ(GEN8_DE_PORT_IMR));
 811                 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
 812                            I915_READ(GEN8_DE_PORT_IIR));
 813                 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
 814                            I915_READ(GEN8_DE_PORT_IER));
 815
 816                 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
 817                            I915_READ(GEN8_DE_MISC_IMR));
 818                 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
 819                            I915_READ(GEN8_DE_MISC_IIR));
 820                 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
 821                            I915_READ(GEN8_DE_MISC_IER));
 822
 823                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 824                            I915_READ(GEN8_PCU_IMR));
 825                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 826                            I915_READ(GEN8_PCU_IIR));
 827                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 828                            I915_READ(GEN8_PCU_IER));
 829         } else if (IS_VALLEYVIEW(dev_priv)) {
 830                 seq_printf(m, "Display IER:\t%08x\n",
 831                            I915_READ(VLV_IER));
 832                 seq_printf(m, "Display IIR:\t%08x\n",
 833                            I915_READ(VLV_IIR));
 834                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 835                            I915_READ(VLV_IIR_RW));
 836                 seq_printf(m, "Display IMR:\t%08x\n",
 837                            I915_READ(VLV_IMR));
 838                 for_each_pipe(dev_priv, pipe)
 839                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 840                                    pipe_name(pipe),
 841                                    I915_READ(PIPESTAT(pipe)));
 842
 843                 seq_printf(m, "Master IER:\t%08x\n",
 844                            I915_READ(VLV_MASTER_IER));
 845
 846                 seq_printf(m, "Render IER:\t%08x\n",
 847                            I915_READ(GTIER));
 848                 seq_printf(m, "Render IIR:\t%08x\n",
 849                            I915_READ(GTIIR));
 850                 seq_printf(m, "Render IMR:\t%08x\n",
 851                            I915_READ(GTIMR));
 852
 853                 seq_printf(m, "PM IER:\t\t%08x\n",
 854                            I915_READ(GEN6_PMIER));
 855                 seq_printf(m, "PM IIR:\t\t%08x\n",
 856                            I915_READ(GEN6_PMIIR));
 857                 seq_printf(m, "PM IMR:\t\t%08x\n",
 858                            I915_READ(GEN6_PMIMR));
 859
 860                 seq_printf(m, "Port hotplug:\t%08x\n",
 861                            I915_READ(PORT_HOTPLUG_EN));
 862                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 863                            I915_READ(VLV_DPFLIPSTAT));
 864                 seq_printf(m, "DPINVGTT:\t%08x\n",
 865                            I915_READ(DPINVGTT));
 866
 867         } else if (!HAS_PCH_SPLIT(dev_priv)) {
 868                 seq_printf(m, "Interrupt enable:    %08x\n",
 869                            I915_READ(IER));
 870                 seq_printf(m, "Interrupt identity:  %08x\n",
 871                            I915_READ(IIR));
 872                 seq_printf(m, "Interrupt mask:      %08x\n",
 873                            I915_READ(IMR));
 874                 for_each_pipe(dev_priv, pipe)
 875                         seq_printf(m, "Pipe %c stat:         %08x\n",
 876                                    pipe_name(pipe),
 877                                    I915_READ(PIPESTAT(pipe)));
 878         } else {
 879                 seq_printf(m, "North Display Interrupt enable:          %08x\n",
 880                            I915_READ(DEIER));
 881                 seq_printf(m, "North Display Interrupt identity:        %08x\n",
 882                            I915_READ(DEIIR));
 883                 seq_printf(m, "North Display Interrupt mask:            %08x\n",
 884                            I915_READ(DEIMR));
 885                 seq_printf(m, "South Display Interrupt enable:          %08x\n",
 886                            I915_READ(SDEIER));
 887                 seq_printf(m, "South Display Interrupt identity:        %08x\n",
 888                            I915_READ(SDEIIR));
 889                 seq_printf(m, "South Display Interrupt mask:            %08x\n",
 890                            I915_READ(SDEIMR));
 891                 seq_printf(m, "Graphics Interrupt enable:               %08x\n",
 892                            I915_READ(GTIER));
 893                 seq_printf(m, "Graphics Interrupt identity:             %08x\n",
 894                            I915_READ(GTIIR));
 895                 seq_printf(m, "Graphics Interrupt mask:         %08x\n",
 896                            I915_READ(GTIMR));
 897         }
 898         for_each_engine(engine, dev_priv, id) {
 899                 if (INTEL_GEN(dev_priv) >= 6) {
 900                         seq_printf(m,
 901                                    "Graphics Interrupt mask (%s):       %08x\n",
 902                                    engine->name, I915_READ_IMR(engine));
 903                 }
 904                 i915_ring_seqno_info(m, engine);
 905         }
 906         intel_runtime_pm_put(dev_priv);
 907
 908         return 0;
 909 }
 910
 911 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
 912 {
 913         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 914         struct drm_device *dev = &dev_priv->drm;
 915         int i, ret;
 916
 917         ret = mutex_lock_interruptible(&dev->struct_mutex);
 918         if (ret)
 919                 return ret;
 920
 921         seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
 922         for (i = 0; i < dev_priv->num_fence_regs; i++) {
 923                 struct i915_vma *vma = dev_priv->fence_regs[i].vma;
 924
 925                 seq_printf(m, "Fence %d, pin count = %d, object = ",
 926                            i, dev_priv->fence_regs[i].pin_count);
 927                 if (!vma)
 928                         seq_puts(m, "unused");
 929                 else
 930                         describe_obj(m, vma->obj);
 931                 seq_putc(m, '\n');
 932         }
 933
 934         mutex_unlock(&dev->struct_mutex);
 935         return 0;
 936 }
 937
 938 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
 939
 940 static ssize_t
 941 i915_error_state_write(struct file *filp,
 942                        const char __user *ubuf,
 943                        size_t cnt,
 944                        loff_t *ppos)
 945 {
 946         struct i915_error_state_file_priv *error_priv = filp->private_data;
 947
 948         DRM_DEBUG_DRIVER("Resetting error state\n");
 949         i915_destroy_error_state(error_priv->dev);
 950
 951         return cnt;
 952 }
 953
 954 static int i915_error_state_open(struct inode *inode, struct file *file)
 955 {
 956         struct drm_i915_private *dev_priv = inode->i_private;
 957         struct i915_error_state_file_priv *error_priv;
 958
 959         error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
 960         if (!error_priv)
 961                 return -ENOMEM;
 962
 963         error_priv->dev = &dev_priv->drm;
 964
 965         i915_error_state_get(&dev_priv->drm, error_priv);
 966
 967         file->private_data = error_priv;
 968
 969         return 0;
 970 }
 971
 972 static int i915_error_state_release(struct inode *inode, struct file *file)
 973 {
 974         struct i915_error_state_file_priv *error_priv = file->private_data;
 975
 976         i915_error_state_put(error_priv);
 977         kfree(error_priv);
 978
 979         return 0;
 980 }
 981
 982 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
 983                                      size_t count, loff_t *pos)
 984 {
 985         struct i915_error_state_file_priv *error_priv = file->private_data;
 986         struct drm_i915_error_state_buf error_str;
 987         loff_t tmp_pos = 0;
 988         ssize_t ret_count = 0;
 989         int ret;
 990
 991         ret = i915_error_state_buf_init(&error_str,
 992                                         to_i915(error_priv->dev), count, *pos);
 993         if (ret)
 994                 return ret;
 995
 996         ret = i915_error_state_to_str(&error_str, error_priv);
 997         if (ret)
 998                 goto out;
 999
1000         ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1001                                             error_str.buf,
1002                                             error_str.bytes);
1003
1004         if (ret_count < 0)
1005                 ret = ret_count;
1006         else
1007                 *pos = error_str.start + ret_count;
1008 out:
1009         i915_error_state_buf_release(&error_str);
1010         return ret ?: ret_count;
1011 }
1012
1013 static const struct file_operations i915_error_state_fops = {
1014         .owner = THIS_MODULE,
1015         .open = i915_error_state_open,
1016         .read = i915_error_state_read,
1017         .write = i915_error_state_write,
1018         .llseek = default_llseek,
1019         .release = i915_error_state_release,
1020 };
1021
1022 #endif
1023
1024 static int
1025 i915_next_seqno_get(void *data, u64 *val)
1026 {
1027         struct drm_i915_private *dev_priv = data;
1028
1029         *val = atomic_read(&dev_priv->gt.global_timeline.next_seqno);
1030         return 0;
1031 }
1032
1033 static int
1034 i915_next_seqno_set(void *data, u64 val)
1035 {
1036         struct drm_i915_private *dev_priv = data;
1037         struct drm_device *dev = &dev_priv->drm;
1038         int ret;
1039
1040         ret = mutex_lock_interruptible(&dev->struct_mutex);
1041         if (ret)
1042                 return ret;
1043
1044         ret = i915_gem_set_global_seqno(dev, val);
1045         mutex_unlock(&dev->struct_mutex);
1046
1047         return ret;
1048 }
1049
1050 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1051                         i915_next_seqno_get, i915_next_seqno_set,
1052                         "0x%llx\n");
1053
1054 static int i915_frequency_info(struct seq_file *m, void *unused)
1055 {
1056         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1057         struct drm_device *dev = &dev_priv->drm;
1058         int ret = 0;
1059
1060         intel_runtime_pm_get(dev_priv);
1061
1062         if (IS_GEN5(dev_priv)) {
1063                 u16 rgvswctl = I915_READ16(MEMSWCTL);
1064                 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1065
1066                 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1067                 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1068                 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1069                            MEMSTAT_VID_SHIFT);
1070                 seq_printf(m, "Current P-state: %d\n",
1071                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1072         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1073                 u32 freq_sts;
1074
1075                 mutex_lock(&dev_priv->rps.hw_lock);
1076                 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1077                 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1078                 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1079
1080                 seq_printf(m, "actual GPU freq: %d MHz\n",
1081                            intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1082
1083                 seq_printf(m, "current GPU freq: %d MHz\n",
1084                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1085
1086                 seq_printf(m, "max GPU freq: %d MHz\n",
1087                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1088
1089                 seq_printf(m, "min GPU freq: %d MHz\n",
1090                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1091
1092                 seq_printf(m, "idle GPU freq: %d MHz\n",
1093                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1094
1095                 seq_printf(m,
1096                            "efficient (RPe) frequency: %d MHz\n",
1097                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1098                 mutex_unlock(&dev_priv->rps.hw_lock);
1099         } else if (INTEL_GEN(dev_priv) >= 6) {
1100                 u32 rp_state_limits;
1101                 u32 gt_perf_status;
1102                 u32 rp_state_cap;
1103                 u32 rpmodectl, rpinclimit, rpdeclimit;
1104                 u32 rpstat, cagf, reqf;
1105                 u32 rpupei, rpcurup, rpprevup;
1106                 u32 rpdownei, rpcurdown, rpprevdown;
1107                 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1108                 int max_freq;
1109
1110                 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1111                 if (IS_BROXTON(dev_priv)) {
1112                         rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1113                         gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1114                 } else {
1115                         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1116                         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1117                 }
1118
1119                 /* RPSTAT1 is in the GT power well */
1120                 ret = mutex_lock_interruptible(&dev->struct_mutex);
1121                 if (ret)
1122                         goto out;
1123
1124                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1125
1126                 reqf = I915_READ(GEN6_RPNSWREQ);
1127                 if (IS_GEN9(dev_priv))
1128                         reqf >>= 23;
1129                 else {
1130                         reqf &= ~GEN6_TURBO_DISABLE;
1131                         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1132                                 reqf >>= 24;
1133                         else
1134                                 reqf >>= 25;
1135                 }
1136                 reqf = intel_gpu_freq(dev_priv, reqf);
1137
1138                 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1139                 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1140                 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1141
1142                 rpstat = I915_READ(GEN6_RPSTAT1);
1143                 rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
1144                 rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
1145                 rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
1146                 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
1147                 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
1148                 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
1149                 if (IS_GEN9(dev_priv))
1150                         cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1151                 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1152                         cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1153                 else
1154                         cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1155                 cagf = intel_gpu_freq(dev_priv, cagf);
1156
1157                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1158                 mutex_unlock(&dev->struct_mutex);
1159
1160                 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
1161                         pm_ier = I915_READ(GEN6_PMIER);
1162                         pm_imr = I915_READ(GEN6_PMIMR);
1163                         pm_isr = I915_READ(GEN6_PMISR);
1164                         pm_iir = I915_READ(GEN6_PMIIR);
1165                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1166                 } else {
1167                         pm_ier = I915_READ(GEN8_GT_IER(2));
1168                         pm_imr = I915_READ(GEN8_GT_IMR(2));
1169                         pm_isr = I915_READ(GEN8_GT_ISR(2));
1170                         pm_iir = I915_READ(GEN8_GT_IIR(2));
1171                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1172                 }
1173                 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1174                            pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1175                 seq_printf(m, "pm_intr_keep: 0x%08x\n", dev_priv->rps.pm_intr_keep);
1176                 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1177                 seq_printf(m, "Render p-state ratio: %d\n",
1178                            (gt_perf_status & (IS_GEN9(dev_priv) ? 0x1ff00 : 0xff00)) >> 8);
1179                 seq_printf(m, "Render p-state VID: %d\n",
1180                            gt_perf_status & 0xff);
1181                 seq_printf(m, "Render p-state limit: %d\n",
1182                            rp_state_limits & 0xff);
1183                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1184                 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1185                 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1186                 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1187                 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1188                 seq_printf(m, "CAGF: %dMHz\n", cagf);
1189                 seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
1190                            rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei));
1191                 seq_printf(m, "RP CUR UP: %d (%dus)\n",
1192                            rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
1193                 seq_printf(m, "RP PREV UP: %d (%dus)\n",
1194                            rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
1195                 seq_printf(m, "Up threshold: %d%%\n",
1196                            dev_priv->rps.up_threshold);
1197
1198                 seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
1199                            rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
1200                 seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
1201                            rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown));
1202                 seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
1203                            rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown));
1204                 seq_printf(m, "Down threshold: %d%%\n",
1205                            dev_priv->rps.down_threshold);
1206
1207                 max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 0 :
1208                             rp_state_cap >> 16) & 0xff;
1209                 max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1210                              GEN9_FREQ_SCALER : 1);
1211                 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1212                            intel_gpu_freq(dev_priv, max_freq));
1213
1214                 max_freq = (rp_state_cap & 0xff00) >> 8;
1215                 max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1216                              GEN9_FREQ_SCALER : 1);
1217                 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1218                            intel_gpu_freq(dev_priv, max_freq));
1219
1220                 max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 16 :
1221                             rp_state_cap >> 0) & 0xff;
1222                 max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1223                              GEN9_FREQ_SCALER : 1);
1224                 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1225                            intel_gpu_freq(dev_priv, max_freq));
1226                 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1227                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1228
1229                 seq_printf(m, "Current freq: %d MHz\n",
1230                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1231                 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1232                 seq_printf(m, "Idle freq: %d MHz\n",
1233                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1234                 seq_printf(m, "Min freq: %d MHz\n",
1235                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1236                 seq_printf(m, "Boost freq: %d MHz\n",
1237                            intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
1238                 seq_printf(m, "Max freq: %d MHz\n",
1239                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1240                 seq_printf(m,
1241                            "efficient (RPe) frequency: %d MHz\n",
1242                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1243         } else {
1244                 seq_puts(m, "no P-state info available\n");
1245         }
1246
1247         seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
1248         seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1249         seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1250
1251 out:
1252         intel_runtime_pm_put(dev_priv);
1253         return ret;
1254 }
1255
1256 static void i915_instdone_info(struct drm_i915_private *dev_priv,
1257                                struct seq_file *m,
1258                                struct intel_instdone *instdone)
1259 {
1260         int slice;
1261         int subslice;
1262
1263         seq_printf(m, "\t\tINSTDONE: 0x%08x\n",
1264                    instdone->instdone);
1265
1266         if (INTEL_GEN(dev_priv) <= 3)
1267                 return;
1268
1269         seq_printf(m, "\t\tSC_INSTDONE: 0x%08x\n",
1270                    instdone->slice_common);
1271
1272         if (INTEL_GEN(dev_priv) <= 6)
1273                 return;
1274
1275         for_each_instdone_slice_subslice(dev_priv, slice, subslice)
1276                 seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
1277                            slice, subslice, instdone->sampler[slice][subslice]);
1278
1279         for_each_instdone_slice_subslice(dev_priv, slice, subslice)
1280                 seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n",
1281                            slice, subslice, instdone->row[slice][subslice]);
1282 }
1283
1284 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1285 {
1286         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1287         struct intel_engine_cs *engine;
1288         u64 acthd[I915_NUM_ENGINES];
1289         u32 seqno[I915_NUM_ENGINES];
1290         struct intel_instdone instdone;
1291         enum intel_engine_id id;
1292
1293         if (test_bit(I915_WEDGED, &dev_priv->gpu_error.flags))
1294                 seq_printf(m, "Wedged\n");
1295         if (test_bit(I915_RESET_IN_PROGRESS, &dev_priv->gpu_error.flags))
1296                 seq_printf(m, "Reset in progress\n");
1297         if (waitqueue_active(&dev_priv->gpu_error.wait_queue))
1298                 seq_printf(m, "Waiter holding struct mutex\n");
1299         if (waitqueue_active(&dev_priv->gpu_error.reset_queue))
1300                 seq_printf(m, "struct_mutex blocked for reset\n");
1301
1302         if (!i915.enable_hangcheck) {
1303                 seq_printf(m, "Hangcheck disabled\n");
1304                 return 0;
1305         }
1306
1307         intel_runtime_pm_get(dev_priv);
1308
1309         for_each_engine(engine, dev_priv, id) {
1310                 acthd[id] = intel_engine_get_active_head(engine);
1311                 seqno[id] = intel_engine_get_seqno(engine);
1312         }
1313
1314         intel_engine_get_instdone(dev_priv->engine[RCS], &instdone);
1315
1316         intel_runtime_pm_put(dev_priv);
1317
1318         if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1319                 seq_printf(m, "Hangcheck active, fires in %dms\n",
1320                            jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1321                                             jiffies));
1322         } else
1323                 seq_printf(m, "Hangcheck inactive\n");
1324
1325         for_each_engine(engine, dev_priv, id) {
1326                 struct intel_breadcrumbs *b = &engine->breadcrumbs;
1327                 struct rb_node *rb;
1328
1329                 seq_printf(m, "%s:\n", engine->name);
1330                 seq_printf(m, "\tseqno = %x [current %x, last %x]\n",
1331                            engine->hangcheck.seqno, seqno[id],
1332                            intel_engine_last_submit(engine));
1333                 seq_printf(m, "\twaiters? %s, fake irq active? %s, stalled? %s\n",
1334                            yesno(intel_engine_has_waiter(engine)),
1335                            yesno(test_bit(engine->id,
1336                                           &dev_priv->gpu_error.missed_irq_rings)),
1337                            yesno(engine->hangcheck.stalled));
1338
1339                 spin_lock_irq(&b->lock);
1340                 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
1341                         struct intel_wait *w = container_of(rb, typeof(*w), node);
1342
1343                         seq_printf(m, "\t%s [%d] waiting for %x\n",
1344                                    w->tsk->comm, w->tsk->pid, w->seqno);
1345                 }
1346                 spin_unlock_irq(&b->lock);
1347
1348                 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1349                            (long long)engine->hangcheck.acthd,
1350                            (long long)acthd[id]);
1351                 seq_printf(m, "\taction = %s(%d) %d ms ago\n",
1352                            hangcheck_action_to_str(engine->hangcheck.action),
1353                            engine->hangcheck.action,
1354                            jiffies_to_msecs(jiffies -
1355                                             engine->hangcheck.action_timestamp));
1356
1357                 if (engine->id == RCS) {
1358                         seq_puts(m, "\tinstdone read =\n");
1359
1360                         i915_instdone_info(dev_priv, m, &instdone);
1361
1362                         seq_puts(m, "\tinstdone accu =\n");
1363
1364                         i915_instdone_info(dev_priv, m,
1365                                            &engine->hangcheck.instdone);
1366                 }
1367         }
1368
1369         return 0;
1370 }
1371
1372 static int ironlake_drpc_info(struct seq_file *m)
1373 {
1374         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1375         u32 rgvmodectl, rstdbyctl;
1376         u16 crstandvid;
1377
1378         intel_runtime_pm_get(dev_priv);
1379
1380         rgvmodectl = I915_READ(MEMMODECTL);
1381         rstdbyctl = I915_READ(RSTDBYCTL);
1382         crstandvid = I915_READ16(CRSTANDVID);
1383
1384         intel_runtime_pm_put(dev_priv);
1385
1386         seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1387         seq_printf(m, "Boost freq: %d\n",
1388                    (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1389                    MEMMODE_BOOST_FREQ_SHIFT);
1390         seq_printf(m, "HW control enabled: %s\n",
1391                    yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1392         seq_printf(m, "SW control enabled: %s\n",
1393                    yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1394         seq_printf(m, "Gated voltage change: %s\n",
1395                    yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1396         seq_printf(m, "Starting frequency: P%d\n",
1397                    (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1398         seq_printf(m, "Max P-state: P%d\n",
1399                    (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1400         seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1401         seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1402         seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1403         seq_printf(m, "Render standby enabled: %s\n",
1404                    yesno(!(rstdbyctl & RCX_SW_EXIT)));
1405         seq_puts(m, "Current RS state: ");
1406         switch (rstdbyctl & RSX_STATUS_MASK) {
1407         case RSX_STATUS_ON:
1408                 seq_puts(m, "on\n");
1409                 break;
1410         case RSX_STATUS_RC1:
1411                 seq_puts(m, "RC1\n");
1412                 break;
1413         case RSX_STATUS_RC1E:
1414                 seq_puts(m, "RC1E\n");
1415                 break;
1416         case RSX_STATUS_RS1:
1417                 seq_puts(m, "RS1\n");
1418                 break;
1419         case RSX_STATUS_RS2:
1420                 seq_puts(m, "RS2 (RC6)\n");
1421                 break;
1422         case RSX_STATUS_RS3:
1423                 seq_puts(m, "RC3 (RC6+)\n");
1424                 break;
1425         default:
1426                 seq_puts(m, "unknown\n");
1427                 break;
1428         }
1429
1430         return 0;
1431 }
1432
1433 static int i915_forcewake_domains(struct seq_file *m, void *data)
1434 {
1435         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1436         struct intel_uncore_forcewake_domain *fw_domain;
1437
1438         spin_lock_irq(&dev_priv->uncore.lock);
1439         for_each_fw_domain(fw_domain, dev_priv) {
1440                 seq_printf(m, "%s.wake_count = %u\n",
1441                            intel_uncore_forcewake_domain_to_str(fw_domain->id),
1442                            fw_domain->wake_count);
1443         }
1444         spin_unlock_irq(&dev_priv->uncore.lock);
1445
1446         return 0;
1447 }
1448
1449 static int vlv_drpc_info(struct seq_file *m)
1450 {
1451         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1452         u32 rpmodectl1, rcctl1, pw_status;
1453
1454         intel_runtime_pm_get(dev_priv);
1455
1456         pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1457         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1458         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1459
1460         intel_runtime_pm_put(dev_priv);
1461
1462         seq_printf(m, "Video Turbo Mode: %s\n",
1463                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1464         seq_printf(m, "Turbo enabled: %s\n",
1465                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1466         seq_printf(m, "HW control enabled: %s\n",
1467                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1468         seq_printf(m, "SW control enabled: %s\n",
1469                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1470                           GEN6_RP_MEDIA_SW_MODE));
1471         seq_printf(m, "RC6 Enabled: %s\n",
1472                    yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1473                                         GEN6_RC_CTL_EI_MODE(1))));
1474         seq_printf(m, "Render Power Well: %s\n",
1475                    (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1476         seq_printf(m, "Media Power Well: %s\n",
1477                    (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1478
1479         seq_printf(m, "Render RC6 residency since boot: %u\n",
1480                    I915_READ(VLV_GT_RENDER_RC6));
1481         seq_printf(m, "Media RC6 residency since boot: %u\n",
1482                    I915_READ(VLV_GT_MEDIA_RC6));
1483
1484         return i915_forcewake_domains(m, NULL);
1485 }
1486
1487 static int gen6_drpc_info(struct seq_file *m)
1488 {
1489         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1490         struct drm_device *dev = &dev_priv->drm;
1491         u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1492         u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
1493         unsigned forcewake_count;
1494         int count = 0, ret;
1495
1496         ret = mutex_lock_interruptible(&dev->struct_mutex);
1497         if (ret)
1498                 return ret;
1499         intel_runtime_pm_get(dev_priv);
1500
1501         spin_lock_irq(&dev_priv->uncore.lock);
1502         forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1503         spin_unlock_irq(&dev_priv->uncore.lock);
1504
1505         if (forcewake_count) {
1506                 seq_puts(m, "RC information inaccurate because somebody "
1507                             "holds a forcewake reference \n");
1508         } else {
1509                 /* NB: we cannot use forcewake, else we read the wrong values */
1510                 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1511                         udelay(10);
1512                 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1513         }
1514
1515         gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1516         trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1517
1518         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1519         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1520         if (INTEL_GEN(dev_priv) >= 9) {
1521                 gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE);
1522                 gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
1523         }
1524         mutex_unlock(&dev->struct_mutex);
1525         mutex_lock(&dev_priv->rps.hw_lock);
1526         sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1527         mutex_unlock(&dev_priv->rps.hw_lock);
1528
1529         intel_runtime_pm_put(dev_priv);
1530
1531         seq_printf(m, "Video Turbo Mode: %s\n",
1532                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1533         seq_printf(m, "HW control enabled: %s\n",
1534                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1535         seq_printf(m, "SW control enabled: %s\n",
1536                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1537                           GEN6_RP_MEDIA_SW_MODE));
1538         seq_printf(m, "RC1e Enabled: %s\n",
1539                    yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1540         seq_printf(m, "RC6 Enabled: %s\n",
1541                    yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1542         if (INTEL_GEN(dev_priv) >= 9) {
1543                 seq_printf(m, "Render Well Gating Enabled: %s\n",
1544                         yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
1545                 seq_printf(m, "Media Well Gating Enabled: %s\n",
1546                         yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE));
1547         }
1548         seq_printf(m, "Deep RC6 Enabled: %s\n",
1549                    yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1550         seq_printf(m, "Deepest RC6 Enabled: %s\n",
1551                    yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1552         seq_puts(m, "Current RC state: ");
1553         switch (gt_core_status & GEN6_RCn_MASK) {
1554         case GEN6_RC0:
1555                 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1556                         seq_puts(m, "Core Power Down\n");
1557                 else
1558                         seq_puts(m, "on\n");
1559                 break;
1560         case GEN6_RC3:
1561                 seq_puts(m, "RC3\n");
1562                 break;
1563         case GEN6_RC6:
1564                 seq_puts(m, "RC6\n");
1565                 break;
1566         case GEN6_RC7:
1567                 seq_puts(m, "RC7\n");
1568                 break;
1569         default:
1570                 seq_puts(m, "Unknown\n");
1571                 break;
1572         }
1573
1574         seq_printf(m, "Core Power Down: %s\n",
1575                    yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1576         if (INTEL_GEN(dev_priv) >= 9) {
1577                 seq_printf(m, "Render Power Well: %s\n",
1578                         (gen9_powergate_status &
1579                          GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
1580                 seq_printf(m, "Media Power Well: %s\n",
1581                         (gen9_powergate_status &
1582                          GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
1583         }
1584
1585         /* Not exactly sure what this is */
1586         seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1587                    I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1588         seq_printf(m, "RC6 residency since boot: %u\n",
1589                    I915_READ(GEN6_GT_GFX_RC6));
1590         seq_printf(m, "RC6+ residency since boot: %u\n",
1591                    I915_READ(GEN6_GT_GFX_RC6p));
1592         seq_printf(m, "RC6++ residency since boot: %u\n",
1593                    I915_READ(GEN6_GT_GFX_RC6pp));
1594
1595         seq_printf(m, "RC6   voltage: %dmV\n",
1596                    GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1597         seq_printf(m, "RC6+  voltage: %dmV\n",
1598                    GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1599         seq_printf(m, "RC6++ voltage: %dmV\n",
1600                    GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1601         return i915_forcewake_domains(m, NULL);
1602 }
1603
1604 static int i915_drpc_info(struct seq_file *m, void *unused)
1605 {
1606         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1607
1608         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1609                 return vlv_drpc_info(m);
1610         else if (INTEL_GEN(dev_priv) >= 6)
1611                 return gen6_drpc_info(m);
1612         else
1613                 return ironlake_drpc_info(m);
1614 }
1615
1616 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1617 {
1618         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1619
1620         seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1621                    dev_priv->fb_tracking.busy_bits);
1622
1623         seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1624                    dev_priv->fb_tracking.flip_bits);
1625
1626         return 0;
1627 }
1628
1629 static int i915_fbc_status(struct seq_file *m, void *unused)
1630 {
1631         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1632
1633         if (!HAS_FBC(dev_priv)) {
1634                 seq_puts(m, "FBC unsupported on this chipset\n");
1635                 return 0;
1636         }
1637
1638         intel_runtime_pm_get(dev_priv);
1639         mutex_lock(&dev_priv->fbc.lock);
1640
1641         if (intel_fbc_is_active(dev_priv))
1642                 seq_puts(m, "FBC enabled\n");
1643         else
1644                 seq_printf(m, "FBC disabled: %s\n",
1645                            dev_priv->fbc.no_fbc_reason);
1646
1647         if (intel_fbc_is_active(dev_priv) && INTEL_GEN(dev_priv) >= 7) {
1648                 uint32_t mask = INTEL_GEN(dev_priv) >= 8 ?
1649                                 BDW_FBC_COMPRESSION_MASK :
1650                                 IVB_FBC_COMPRESSION_MASK;
1651                 seq_printf(m, "Compressing: %s\n",
1652                            yesno(I915_READ(FBC_STATUS2) & mask));
1653         }
1654
1655         mutex_unlock(&dev_priv->fbc.lock);
1656         intel_runtime_pm_put(dev_priv);
1657
1658         return 0;
1659 }
1660
1661 static int i915_fbc_fc_get(void *data, u64 *val)
1662 {
1663         struct drm_i915_private *dev_priv = data;
1664
1665         if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1666                 return -ENODEV;
1667
1668         *val = dev_priv->fbc.false_color;
1669
1670         return 0;
1671 }
1672
1673 static int i915_fbc_fc_set(void *data, u64 val)
1674 {
1675         struct drm_i915_private *dev_priv = data;
1676         u32 reg;
1677
1678         if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1679                 return -ENODEV;
1680
1681         mutex_lock(&dev_priv->fbc.lock);
1682
1683         reg = I915_READ(ILK_DPFC_CONTROL);
1684         dev_priv->fbc.false_color = val;
1685
1686         I915_WRITE(ILK_DPFC_CONTROL, val ?
1687                    (reg | FBC_CTL_FALSE_COLOR) :
1688                    (reg & ~FBC_CTL_FALSE_COLOR));
1689
1690         mutex_unlock(&dev_priv->fbc.lock);
1691         return 0;
1692 }
1693
1694 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1695                         i915_fbc_fc_get, i915_fbc_fc_set,
1696                         "%llu\n");
1697
1698 static int i915_ips_status(struct seq_file *m, void *unused)
1699 {
1700         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1701
1702         if (!HAS_IPS(dev_priv)) {
1703                 seq_puts(m, "not supported\n");
1704                 return 0;
1705         }
1706
1707         intel_runtime_pm_get(dev_priv);
1708
1709         seq_printf(m, "Enabled by kernel parameter: %s\n",
1710                    yesno(i915.enable_ips));
1711
1712         if (INTEL_GEN(dev_priv) >= 8) {
1713                 seq_puts(m, "Currently: unknown\n");
1714         } else {
1715                 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1716                         seq_puts(m, "Currently: enabled\n");
1717                 else
1718                         seq_puts(m, "Currently: disabled\n");
1719         }
1720
1721         intel_runtime_pm_put(dev_priv);
1722
1723         return 0;
1724 }
1725
1726 static int i915_sr_status(struct seq_file *m, void *unused)
1727 {
1728         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1729         bool sr_enabled = false;
1730
1731         intel_runtime_pm_get(dev_priv);
1732         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1733
1734         if (HAS_PCH_SPLIT(dev_priv))
1735                 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1736         else if (IS_CRESTLINE(dev_priv) || IS_G4X(dev_priv) ||
1737                  IS_I945G(dev_priv) || IS_I945GM(dev_priv))
1738                 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1739         else if (IS_I915GM(dev_priv))
1740                 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1741         else if (IS_PINEVIEW(dev_priv))
1742                 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1743         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1744                 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1745
1746         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1747         intel_runtime_pm_put(dev_priv);
1748
1749         seq_printf(m, "self-refresh: %s\n", enableddisabled(sr_enabled));
1750
1751         return 0;
1752 }
1753
1754 static int i915_emon_status(struct seq_file *m, void *unused)
1755 {
1756         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1757         struct drm_device *dev = &dev_priv->drm;
1758         unsigned long temp, chipset, gfx;
1759         int ret;
1760
1761         if (!IS_GEN5(dev_priv))
1762                 return -ENODEV;
1763
1764         ret = mutex_lock_interruptible(&dev->struct_mutex);
1765         if (ret)
1766                 return ret;
1767
1768         temp = i915_mch_val(dev_priv);
1769         chipset = i915_chipset_val(dev_priv);
1770         gfx = i915_gfx_val(dev_priv);
1771         mutex_unlock(&dev->struct_mutex);
1772
1773         seq_printf(m, "GMCH temp: %ld\n", temp);
1774         seq_printf(m, "Chipset power: %ld\n", chipset);
1775         seq_printf(m, "GFX power: %ld\n", gfx);
1776         seq_printf(m, "Total power: %ld\n", chipset + gfx);
1777
1778         return 0;
1779 }
1780
1781 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1782 {
1783         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1784         int ret = 0;
1785         int gpu_freq, ia_freq;
1786         unsigned int max_gpu_freq, min_gpu_freq;
1787
1788         if (!HAS_LLC(dev_priv)) {
1789                 seq_puts(m, "unsupported on this chipset\n");
1790                 return 0;
1791         }
1792
1793         intel_runtime_pm_get(dev_priv);
1794
1795         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1796         if (ret)
1797                 goto out;
1798
1799         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
1800                 /* Convert GT frequency to 50 HZ units */
1801                 min_gpu_freq =
1802                         dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1803                 max_gpu_freq =
1804                         dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1805         } else {
1806                 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1807                 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1808         }
1809
1810         seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1811
1812         for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1813                 ia_freq = gpu_freq;
1814                 sandybridge_pcode_read(dev_priv,
1815                                        GEN6_PCODE_READ_MIN_FREQ_TABLE,
1816                                        &ia_freq);
1817                 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1818                            intel_gpu_freq(dev_priv, (gpu_freq *
1819                                 (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1820                                  GEN9_FREQ_SCALER : 1))),
1821                            ((ia_freq >> 0) & 0xff) * 100,
1822                            ((ia_freq >> 8) & 0xff) * 100);
1823         }
1824
1825         mutex_unlock(&dev_priv->rps.hw_lock);
1826
1827 out:
1828         intel_runtime_pm_put(dev_priv);
1829         return ret;
1830 }
1831
1832 static int i915_opregion(struct seq_file *m, void *unused)
1833 {
1834         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1835         struct drm_device *dev = &dev_priv->drm;
1836         struct intel_opregion *opregion = &dev_priv->opregion;
1837         int ret;
1838
1839         ret = mutex_lock_interruptible(&dev->struct_mutex);
1840         if (ret)
1841                 goto out;
1842
1843         if (opregion->header)
1844                 seq_write(m, opregion->header, OPREGION_SIZE);
1845
1846         mutex_unlock(&dev->struct_mutex);
1847
1848 out:
1849         return 0;
1850 }
1851
1852 static int i915_vbt(struct seq_file *m, void *unused)
1853 {
1854         struct intel_opregion *opregion = &node_to_i915(m->private)->opregion;
1855
1856         if (opregion->vbt)
1857                 seq_write(m, opregion->vbt, opregion->vbt_size);
1858
1859         return 0;
1860 }
1861
1862 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1863 {
1864         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1865         struct drm_device *dev = &dev_priv->drm;
1866         struct intel_framebuffer *fbdev_fb = NULL;
1867         struct drm_framebuffer *drm_fb;
1868         int ret;
1869
1870         ret = mutex_lock_interruptible(&dev->struct_mutex);
1871         if (ret)
1872                 return ret;
1873
1874 #ifdef CONFIG_DRM_FBDEV_EMULATION
1875         if (dev_priv->fbdev) {
1876                 fbdev_fb = to_intel_framebuffer(dev_priv->fbdev->helper.fb);
1877
1878                 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1879                            fbdev_fb->base.width,
1880                            fbdev_fb->base.height,
1881                            fbdev_fb->base.depth,
1882                            fbdev_fb->base.bits_per_pixel,
1883                            fbdev_fb->base.modifier[0],
1884                            drm_framebuffer_read_refcount(&fbdev_fb->base));
1885                 describe_obj(m, fbdev_fb->obj);
1886                 seq_putc(m, '\n');
1887         }
1888 #endif
1889
1890         mutex_lock(&dev->mode_config.fb_lock);
1891         drm_for_each_fb(drm_fb, dev) {
1892                 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
1893                 if (fb == fbdev_fb)
1894                         continue;
1895
1896                 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1897                            fb->base.width,
1898                            fb->base.height,
1899                            fb->base.depth,
1900                            fb->base.bits_per_pixel,
1901                            fb->base.modifier[0],
1902                            drm_framebuffer_read_refcount(&fb->base));
1903                 describe_obj(m, fb->obj);
1904                 seq_putc(m, '\n');
1905         }
1906         mutex_unlock(&dev->mode_config.fb_lock);
1907         mutex_unlock(&dev->struct_mutex);
1908
1909         return 0;
1910 }
1911
1912 static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring)
1913 {
1914         seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1915                    ring->space, ring->head, ring->tail,
1916                    ring->last_retired_head);
1917 }
1918
1919 static int i915_context_status(struct seq_file *m, void *unused)
1920 {
1921         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1922         struct drm_device *dev = &dev_priv->drm;
1923         struct intel_engine_cs *engine;
1924         struct i915_gem_context *ctx;
1925         enum intel_engine_id id;
1926         int ret;
1927
1928         ret = mutex_lock_interruptible(&dev->struct_mutex);
1929         if (ret)
1930                 return ret;
1931
1932         list_for_each_entry(ctx, &dev_priv->context_list, link) {
1933                 seq_printf(m, "HW context %u ", ctx->hw_id);
1934                 if (ctx->pid) {
1935                         struct task_struct *task;
1936
1937                         task = get_pid_task(ctx->pid, PIDTYPE_PID);
1938                         if (task) {
1939                                 seq_printf(m, "(%s [%d]) ",
1940                                            task->comm, task->pid);
1941                                 put_task_struct(task);
1942                         }
1943                 } else if (IS_ERR(ctx->file_priv)) {
1944                         seq_puts(m, "(deleted) ");
1945                 } else {
1946                         seq_puts(m, "(kernel) ");
1947                 }
1948
1949                 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
1950                 seq_putc(m, '\n');
1951
1952                 for_each_engine(engine, dev_priv, id) {
1953                         struct intel_context *ce = &ctx->engine[engine->id];
1954
1955                         seq_printf(m, "%s: ", engine->name);
1956                         seq_putc(m, ce->initialised ? 'I' : 'i');
1957                         if (ce->state)
1958                                 describe_obj(m, ce->state->obj);
1959                         if (ce->ring)
1960                                 describe_ctx_ring(m, ce->ring);
1961                         seq_putc(m, '\n');
1962                 }
1963
1964                 seq_putc(m, '\n');
1965         }
1966
1967         mutex_unlock(&dev->struct_mutex);
1968
1969         return 0;
1970 }
1971
1972 static void i915_dump_lrc_obj(struct seq_file *m,
1973                               struct i915_gem_context *ctx,
1974                               struct intel_engine_cs *engine)
1975 {
1976         struct i915_vma *vma = ctx->engine[engine->id].state;
1977         struct page *page;
1978         int j;
1979
1980         seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id);
1981
1982         if (!vma) {
1983                 seq_puts(m, "\tFake context\n");
1984                 return;
1985         }
1986
1987         if (vma->flags & I915_VMA_GLOBAL_BIND)
1988                 seq_printf(m, "\tBound in GGTT at 0x%08x\n",
1989                            i915_ggtt_offset(vma));
1990
1991         if (i915_gem_object_pin_pages(vma->obj)) {
1992                 seq_puts(m, "\tFailed to get pages for context object\n\n");
1993                 return;
1994         }
1995
1996         page = i915_gem_object_get_page(vma->obj, LRC_STATE_PN);
1997         if (page) {
1998                 u32 *reg_state = kmap_atomic(page);
1999
2000                 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2001                         seq_printf(m,
2002                                    "\t[0x%04x] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2003                                    j * 4,
2004                                    reg_state[j], reg_state[j + 1],
2005                                    reg_state[j + 2], reg_state[j + 3]);
2006                 }
2007                 kunmap_atomic(reg_state);
2008         }
2009
2010         i915_gem_object_unpin_pages(vma->obj);
2011         seq_putc(m, '\n');
2012 }
2013
2014 static int i915_dump_lrc(struct seq_file *m, void *unused)
2015 {
2016         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2017         struct drm_device *dev = &dev_priv->drm;
2018         struct intel_engine_cs *engine;
2019         struct i915_gem_context *ctx;
2020         enum intel_engine_id id;
2021         int ret;
2022
2023         if (!i915.enable_execlists) {
2024                 seq_printf(m, "Logical Ring Contexts are disabled\n");
2025                 return 0;
2026         }
2027
2028         ret = mutex_lock_interruptible(&dev->struct_mutex);
2029         if (ret)
2030                 return ret;
2031
2032         list_for_each_entry(ctx, &dev_priv->context_list, link)
2033                 for_each_engine(engine, dev_priv, id)
2034                         i915_dump_lrc_obj(m, ctx, engine);
2035
2036         mutex_unlock(&dev->struct_mutex);
2037
2038         return 0;
2039 }
2040
2041 static const char *swizzle_string(unsigned swizzle)
2042 {
2043         switch (swizzle) {
2044         case I915_BIT_6_SWIZZLE_NONE:
2045                 return "none";
2046         case I915_BIT_6_SWIZZLE_9:
2047                 return "bit9";
2048         case I915_BIT_6_SWIZZLE_9_10:
2049                 return "bit9/bit10";
2050         case I915_BIT_6_SWIZZLE_9_11:
2051                 return "bit9/bit11";
2052         case I915_BIT_6_SWIZZLE_9_10_11:
2053                 return "bit9/bit10/bit11";
2054         case I915_BIT_6_SWIZZLE_9_17:
2055                 return "bit9/bit17";
2056         case I915_BIT_6_SWIZZLE_9_10_17:
2057                 return "bit9/bit10/bit17";
2058         case I915_BIT_6_SWIZZLE_UNKNOWN:
2059                 return "unknown";
2060         }
2061
2062         return "bug";
2063 }
2064
2065 static int i915_swizzle_info(struct seq_file *m, void *data)
2066 {
2067         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2068
2069         intel_runtime_pm_get(dev_priv);
2070
2071         seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2072                    swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2073         seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2074                    swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2075
2076         if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) {
2077                 seq_printf(m, "DDC = 0x%08x\n",
2078                            I915_READ(DCC));
2079                 seq_printf(m, "DDC2 = 0x%08x\n",
2080                            I915_READ(DCC2));
2081                 seq_printf(m, "C0DRB3 = 0x%04x\n",
2082                            I915_READ16(C0DRB3));
2083                 seq_printf(m, "C1DRB3 = 0x%04x\n",
2084                            I915_READ16(C1DRB3));
2085         } else if (INTEL_GEN(dev_priv) >= 6) {
2086                 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2087                            I915_READ(MAD_DIMM_C0));
2088                 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2089                            I915_READ(MAD_DIMM_C1));
2090                 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2091                            I915_READ(MAD_DIMM_C2));
2092                 seq_printf(m, "TILECTL = 0x%08x\n",
2093                            I915_READ(TILECTL));
2094                 if (INTEL_GEN(dev_priv) >= 8)
2095                         seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2096                                    I915_READ(GAMTARBMODE));
2097                 else
2098                         seq_printf(m, "ARB_MODE = 0x%08x\n",
2099                                    I915_READ(ARB_MODE));
2100                 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2101                            I915_READ(DISP_ARB_CTL));
2102         }
2103
2104         if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2105                 seq_puts(m, "L-shaped memory detected\n");
2106
2107         intel_runtime_pm_put(dev_priv);
2108
2109         return 0;
2110 }
2111
2112 static int per_file_ctx(int id, void *ptr, void *data)
2113 {
2114         struct i915_gem_context *ctx = ptr;
2115         struct seq_file *m = data;
2116         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2117
2118         if (!ppgtt) {
2119                 seq_printf(m, "  no ppgtt for context %d\n",
2120                            ctx->user_handle);
2121                 return 0;
2122         }
2123
2124         if (i915_gem_context_is_default(ctx))
2125                 seq_puts(m, "  default context:\n");
2126         else
2127                 seq_printf(m, "  context %d:\n", ctx->user_handle);
2128         ppgtt->debug_dump(ppgtt, m);
2129
2130         return 0;
2131 }
2132
2133 static void gen8_ppgtt_info(struct seq_file *m,
2134                             struct drm_i915_private *dev_priv)
2135 {
2136         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2137         struct intel_engine_cs *engine;
2138         enum intel_engine_id id;
2139         int i;
2140
2141         if (!ppgtt)
2142                 return;
2143
2144         for_each_engine(engine, dev_priv, id) {
2145                 seq_printf(m, "%s\n", engine->name);
2146                 for (i = 0; i < 4; i++) {
2147                         u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
2148                         pdp <<= 32;
2149                         pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
2150                         seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2151                 }
2152         }
2153 }
2154
2155 static void gen6_ppgtt_info(struct seq_file *m,
2156                             struct drm_i915_private *dev_priv)
2157 {
2158         struct intel_engine_cs *engine;
2159         enum intel_engine_id id;
2160
2161         if (IS_GEN6(dev_priv))
2162                 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2163
2164         for_each_engine(engine, dev_priv, id) {
2165                 seq_printf(m, "%s\n", engine->name);
2166                 if (IS_GEN7(dev_priv))
2167                         seq_printf(m, "GFX_MODE: 0x%08x\n",
2168                                    I915_READ(RING_MODE_GEN7(engine)));
2169                 seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
2170                            I915_READ(RING_PP_DIR_BASE(engine)));
2171                 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
2172                            I915_READ(RING_PP_DIR_BASE_READ(engine)));
2173                 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
2174                            I915_READ(RING_PP_DIR_DCLV(engine)));
2175         }
2176         if (dev_priv->mm.aliasing_ppgtt) {
2177                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2178
2179                 seq_puts(m, "aliasing PPGTT:\n");
2180                 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2181
2182                 ppgtt->debug_dump(ppgtt, m);
2183         }
2184
2185         seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2186 }
2187
2188 static int i915_ppgtt_info(struct seq_file *m, void *data)
2189 {
2190         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2191         struct drm_device *dev = &dev_priv->drm;
2192         struct drm_file *file;
2193         int ret;
2194
2195         mutex_lock(&dev->filelist_mutex);
2196         ret = mutex_lock_interruptible(&dev->struct_mutex);
2197         if (ret)
2198                 goto out_unlock;
2199
2200         intel_runtime_pm_get(dev_priv);
2201
2202         if (INTEL_GEN(dev_priv) >= 8)
2203                 gen8_ppgtt_info(m, dev_priv);
2204         else if (INTEL_GEN(dev_priv) >= 6)
2205                 gen6_ppgtt_info(m, dev_priv);
2206
2207         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2208                 struct drm_i915_file_private *file_priv = file->driver_priv;
2209                 struct task_struct *task;
2210
2211                 task = get_pid_task(file->pid, PIDTYPE_PID);
2212                 if (!task) {
2213                         ret = -ESRCH;
2214                         goto out_rpm;
2215                 }
2216                 seq_printf(m, "\nproc: %s\n", task->comm);
2217                 put_task_struct(task);
2218                 idr_for_each(&file_priv->context_idr, per_file_ctx,
2219                              (void *)(unsigned long)m);
2220         }
2221
2222 out_rpm:
2223         intel_runtime_pm_put(dev_priv);
2224         mutex_unlock(&dev->struct_mutex);
2225 out_unlock:
2226         mutex_unlock(&dev->filelist_mutex);
2227         return ret;
2228 }
2229
2230 static int count_irq_waiters(struct drm_i915_private *i915)
2231 {
2232         struct intel_engine_cs *engine;
2233         enum intel_engine_id id;
2234         int count = 0;
2235
2236         for_each_engine(engine, i915, id)
2237                 count += intel_engine_has_waiter(engine);
2238
2239         return count;
2240 }
2241
2242 static const char *rps_power_to_str(unsigned int power)
2243 {
2244         static const char * const strings[] = {
2245                 [LOW_POWER] = "low power",
2246                 [BETWEEN] = "mixed",
2247                 [HIGH_POWER] = "high power",
2248         };
2249
2250         if (power >= ARRAY_SIZE(strings) || !strings[power])
2251                 return "unknown";
2252
2253         return strings[power];
2254 }
2255
2256 static int i915_rps_boost_info(struct seq_file *m, void *data)
2257 {
2258         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2259         struct drm_device *dev = &dev_priv->drm;
2260         struct drm_file *file;
2261
2262         seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2263         seq_printf(m, "GPU busy? %s [%d requests]\n",
2264                    yesno(dev_priv->gt.awake), dev_priv->gt.active_requests);
2265         seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2266         seq_printf(m, "Frequency requested %d\n",
2267                    intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
2268         seq_printf(m, "  min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2269                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2270                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2271                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2272                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2273         seq_printf(m, "  idle:%d, efficient:%d, boost:%d\n",
2274                    intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
2275                    intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2276                    intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
2277
2278         mutex_lock(&dev->filelist_mutex);
2279         spin_lock(&dev_priv->rps.client_lock);
2280         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2281                 struct drm_i915_file_private *file_priv = file->driver_priv;
2282                 struct task_struct *task;
2283
2284                 rcu_read_lock();
2285                 task = pid_task(file->pid, PIDTYPE_PID);
2286                 seq_printf(m, "%s [%d]: %d boosts%s\n",
2287                            task ? task->comm : "<unknown>",
2288                            task ? task->pid : -1,
2289                            file_priv->rps.boosts,
2290                            list_empty(&file_priv->rps.link) ? "" : ", active");
2291                 rcu_read_unlock();
2292         }
2293         seq_printf(m, "Kernel (anonymous) boosts: %d\n", dev_priv->rps.boosts);
2294         spin_unlock(&dev_priv->rps.client_lock);
2295         mutex_unlock(&dev->filelist_mutex);
2296
2297         if (INTEL_GEN(dev_priv) >= 6 &&
2298             dev_priv->rps.enabled &&
2299             dev_priv->gt.active_requests) {
2300                 u32 rpup, rpupei;
2301                 u32 rpdown, rpdownei;
2302
2303                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2304                 rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK;
2305                 rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK;
2306                 rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK;
2307                 rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK;
2308                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2309
2310                 seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n",
2311                            rps_power_to_str(dev_priv->rps.power));
2312                 seq_printf(m, "  Avg. up: %d%% [above threshold? %d%%]\n",
2313                            100 * rpup / rpupei,
2314                            dev_priv->rps.up_threshold);
2315                 seq_printf(m, "  Avg. down: %d%% [below threshold? %d%%]\n",
2316                            100 * rpdown / rpdownei,
2317                            dev_priv->rps.down_threshold);
2318         } else {
2319                 seq_puts(m, "\nRPS Autotuning inactive\n");
2320         }
2321
2322         return 0;
2323 }
2324
2325 static int i915_llc(struct seq_file *m, void *data)
2326 {
2327         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2328         const bool edram = INTEL_GEN(dev_priv) > 8;
2329
2330         seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv)));
2331         seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
2332                    intel_uncore_edram_size(dev_priv)/1024/1024);
2333
2334         return 0;
2335 }
2336
2337 static int i915_guc_load_status_info(struct seq_file *m, void *data)
2338 {
2339         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2340         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
2341         u32 tmp, i;
2342
2343         if (!HAS_GUC_UCODE(dev_priv))
2344                 return 0;
2345
2346         seq_printf(m, "GuC firmware status:\n");
2347         seq_printf(m, "\tpath: %s\n",
2348                 guc_fw->guc_fw_path);
2349         seq_printf(m, "\tfetch: %s\n",
2350                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
2351         seq_printf(m, "\tload: %s\n",
2352                 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
2353         seq_printf(m, "\tversion wanted: %d.%d\n",
2354                 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2355         seq_printf(m, "\tversion found: %d.%d\n",
2356                 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
2357         seq_printf(m, "\theader: offset is %d; size = %d\n",
2358                 guc_fw->header_offset, guc_fw->header_size);
2359         seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2360                 guc_fw->ucode_offset, guc_fw->ucode_size);
2361         seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2362                 guc_fw->rsa_offset, guc_fw->rsa_size);
2363
2364         tmp = I915_READ(GUC_STATUS);
2365
2366         seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2367         seq_printf(m, "\tBootrom status = 0x%x\n",
2368                 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2369         seq_printf(m, "\tuKernel status = 0x%x\n",
2370                 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2371         seq_printf(m, "\tMIA Core status = 0x%x\n",
2372                 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2373         seq_puts(m, "\nScratch registers:\n");
2374         for (i = 0; i < 16; i++)
2375                 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2376
2377         return 0;
2378 }
2379
2380 static void i915_guc_log_info(struct seq_file *m,
2381                               struct drm_i915_private *dev_priv)
2382 {
2383         struct intel_guc *guc = &dev_priv->guc;
2384
2385         seq_puts(m, "\nGuC logging stats:\n");
2386
2387         seq_printf(m, "\tISR:   flush count %10u, overflow count %10u\n",
2388                    guc->log.flush_count[GUC_ISR_LOG_BUFFER],
2389                    guc->log.total_overflow_count[GUC_ISR_LOG_BUFFER]);
2390
2391         seq_printf(m, "\tDPC:   flush count %10u, overflow count %10u\n",
2392                    guc->log.flush_count[GUC_DPC_LOG_BUFFER],
2393                    guc->log.total_overflow_count[GUC_DPC_LOG_BUFFER]);
2394
2395         seq_printf(m, "\tCRASH: flush count %10u, overflow count %10u\n",
2396                    guc->log.flush_count[GUC_CRASH_DUMP_LOG_BUFFER],
2397                    guc->log.total_overflow_count[GUC_CRASH_DUMP_LOG_BUFFER]);
2398
2399         seq_printf(m, "\tTotal flush interrupt count: %u\n",
2400                    guc->log.flush_interrupt_count);
2401
2402         seq_printf(m, "\tCapture miss count: %u\n",
2403                    guc->log.capture_miss_count);
2404 }
2405
2406 static void i915_guc_client_info(struct seq_file *m,
2407                                  struct drm_i915_private *dev_priv,
2408                                  struct i915_guc_client *client)
2409 {
2410         struct intel_engine_cs *engine;
2411         enum intel_engine_id id;
2412         uint64_t tot = 0;
2413
2414         seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2415                 client->priority, client->ctx_index, client->proc_desc_offset);
2416         seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2417                 client->doorbell_id, client->doorbell_offset, client->cookie);
2418         seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2419                 client->wq_size, client->wq_offset, client->wq_tail);
2420
2421         seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space);
2422         seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2423         seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2424
2425         for_each_engine(engine, dev_priv, id) {
2426                 u64 submissions = client->submissions[id];
2427                 tot += submissions;
2428                 seq_printf(m, "\tSubmissions: %llu %s\n",
2429                                 submissions, engine->name);
2430         }
2431         seq_printf(m, "\tTotal: %llu\n", tot);
2432 }
2433
2434 static int i915_guc_info(struct seq_file *m, void *data)
2435 {
2436         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2437         struct drm_device *dev = &dev_priv->drm;
2438         struct intel_guc guc;
2439         struct i915_guc_client client = {};
2440         struct intel_engine_cs *engine;
2441         enum intel_engine_id id;
2442         u64 total = 0;
2443
2444         if (!HAS_GUC_SCHED(dev_priv))
2445                 return 0;
2446
2447         if (mutex_lock_interruptible(&dev->struct_mutex))
2448                 return 0;
2449
2450         /* Take a local copy of the GuC data, so we can dump it at leisure */
2451         guc = dev_priv->guc;
2452         if (guc.execbuf_client)
2453                 client = *guc.execbuf_client;
2454
2455         mutex_unlock(&dev->struct_mutex);
2456
2457         seq_printf(m, "Doorbell map:\n");
2458         seq_printf(m, "\t%*pb\n", GUC_MAX_DOORBELLS, guc.doorbell_bitmap);
2459         seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc.db_cacheline);
2460
2461         seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
2462         seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
2463         seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
2464         seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
2465         seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
2466
2467         seq_printf(m, "\nGuC submissions:\n");
2468         for_each_engine(engine, dev_priv, id) {
2469                 u64 submissions = guc.submissions[id];
2470                 total += submissions;
2471                 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",
2472                         engine->name, submissions, guc.last_seqno[id]);
2473         }
2474         seq_printf(m, "\t%s: %llu\n", "Total", total);
2475
2476         seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
2477         i915_guc_client_info(m, dev_priv, &client);
2478
2479         i915_guc_log_info(m, dev_priv);
2480
2481         /* Add more as required ... */
2482
2483         return 0;
2484 }
2485
2486 static int i915_guc_log_dump(struct seq_file *m, void *data)
2487 {
2488         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2489         struct drm_i915_gem_object *obj;
2490         int i = 0, pg;
2491
2492         if (!dev_priv->guc.log.vma)
2493                 return 0;
2494
2495         obj = dev_priv->guc.log.vma->obj;
2496         for (pg = 0; pg < obj->base.size / PAGE_SIZE; pg++) {
2497                 u32 *log = kmap_atomic(i915_gem_object_get_page(obj, pg));
2498
2499                 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2500                         seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2501                                    *(log + i), *(log + i + 1),
2502                                    *(log + i + 2), *(log + i + 3));
2503
2504                 kunmap_atomic(log);
2505         }
2506
2507         seq_putc(m, '\n');
2508
2509         return 0;
2510 }
2511
2512 static int i915_guc_log_control_get(void *data, u64 *val)
2513 {
2514         struct drm_device *dev = data;
2515         struct drm_i915_private *dev_priv = to_i915(dev);
2516
2517         if (!dev_priv->guc.log.vma)
2518                 return -EINVAL;
2519
2520         *val = i915.guc_log_level;
2521
2522         return 0;
2523 }
2524
2525 static int i915_guc_log_control_set(void *data, u64 val)
2526 {
2527         struct drm_device *dev = data;
2528         struct drm_i915_private *dev_priv = to_i915(dev);
2529         int ret;
2530
2531         if (!dev_priv->guc.log.vma)
2532                 return -EINVAL;
2533
2534         ret = mutex_lock_interruptible(&dev->struct_mutex);
2535         if (ret)
2536                 return ret;
2537
2538         intel_runtime_pm_get(dev_priv);
2539         ret = i915_guc_log_control(dev_priv, val);
2540         intel_runtime_pm_put(dev_priv);
2541
2542         mutex_unlock(&dev->struct_mutex);
2543         return ret;
2544 }
2545
2546 DEFINE_SIMPLE_ATTRIBUTE(i915_guc_log_control_fops,
2547                         i915_guc_log_control_get, i915_guc_log_control_set,
2548                         "%lld\n");
2549
2550 static int i915_edp_psr_status(struct seq_file *m, void *data)
2551 {
2552         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2553         u32 psrperf = 0;
2554         u32 stat[3];
2555         enum pipe pipe;
2556         bool enabled = false;
2557
2558         if (!HAS_PSR(dev_priv)) {
2559                 seq_puts(m, "PSR not supported\n");
2560                 return 0;
2561         }
2562
2563         intel_runtime_pm_get(dev_priv);
2564
2565         mutex_lock(&dev_priv->psr.lock);
2566         seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2567         seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2568         seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2569         seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2570         seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2571                    dev_priv->psr.busy_frontbuffer_bits);
2572         seq_printf(m, "Re-enable work scheduled: %s\n",
2573                    yesno(work_busy(&dev_priv->psr.work.work)));
2574
2575         if (HAS_DDI(dev_priv))
2576                 enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2577         else {
2578                 for_each_pipe(dev_priv, pipe) {
2579                         enum transcoder cpu_transcoder =
2580                                 intel_pipe_to_cpu_transcoder(dev_priv, pipe);
2581                         enum intel_display_power_domain power_domain;
2582
2583                         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
2584                         if (!intel_display_power_get_if_enabled(dev_priv,
2585                                                                 power_domain))
2586                                 continue;
2587
2588                         stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2589                                 VLV_EDP_PSR_CURR_STATE_MASK;
2590                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2591                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2592                                 enabled = true;
2593
2594                         intel_display_power_put(dev_priv, power_domain);
2595                 }
2596         }
2597
2598         seq_printf(m, "Main link in standby mode: %s\n",
2599                    yesno(dev_priv->psr.link_standby));
2600
2601         seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2602
2603         if (!HAS_DDI(dev_priv))
2604                 for_each_pipe(dev_priv, pipe) {
2605                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2606                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2607                                 seq_printf(m, " pipe %c", pipe_name(pipe));
2608                 }
2609         seq_puts(m, "\n");
2610
2611         /*
2612          * VLV/CHV PSR has no kind of performance counter
2613          * SKL+ Perf counter is reset to 0 everytime DC state is entered
2614          */
2615         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2616                 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
2617                         EDP_PSR_PERF_CNT_MASK;
2618
2619                 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2620         }
2621         mutex_unlock(&dev_priv->psr.lock);
2622
2623         intel_runtime_pm_put(dev_priv);
2624         return 0;
2625 }
2626
2627 static int i915_sink_crc(struct seq_file *m, void *data)
2628 {
2629         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2630         struct drm_device *dev = &dev_priv->drm;
2631         struct intel_connector *connector;
2632         struct intel_dp *intel_dp = NULL;
2633         int ret;
2634         u8 crc[6];
2635
2636         drm_modeset_lock_all(dev);
2637         for_each_intel_connector(dev, connector) {
2638                 struct drm_crtc *crtc;
2639
2640                 if (!connector->base.state->best_encoder)
2641                         continue;
2642
2643                 crtc = connector->base.state->crtc;
2644                 if (!crtc->state->active)
2645                         continue;
2646
2647                 if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
2648                         continue;
2649
2650                 intel_dp = enc_to_intel_dp(connector->base.state->best_encoder);
2651
2652                 ret = intel_dp_sink_crc(intel_dp, crc);
2653                 if (ret)
2654                         goto out;
2655
2656                 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2657                            crc[0], crc[1], crc[2],
2658                            crc[3], crc[4], crc[5]);
2659                 goto out;
2660         }
2661         ret = -ENODEV;
2662 out:
2663         drm_modeset_unlock_all(dev);
2664         return ret;
2665 }
2666
2667 static int i915_energy_uJ(struct seq_file *m, void *data)
2668 {
2669         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2670         u64 power;
2671         u32 units;
2672
2673         if (INTEL_GEN(dev_priv) < 6)
2674                 return -ENODEV;
2675
2676         intel_runtime_pm_get(dev_priv);
2677
2678         rdmsrl(MSR_RAPL_POWER_UNIT, power);
2679         power = (power & 0x1f00) >> 8;
2680         units = 1000000 / (1 << power); /* convert to uJ */
2681         power = I915_READ(MCH_SECP_NRG_STTS);
2682         power *= units;
2683
2684         intel_runtime_pm_put(dev_priv);
2685
2686         seq_printf(m, "%llu", (long long unsigned)power);
2687
2688         return 0;
2689 }
2690
2691 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2692 {
2693         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2694         struct pci_dev *pdev = dev_priv->drm.pdev;
2695
2696         if (!HAS_RUNTIME_PM(dev_priv))
2697                 seq_puts(m, "Runtime power management not supported\n");
2698
2699         seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
2700         seq_printf(m, "IRQs disabled: %s\n",
2701                    yesno(!intel_irqs_enabled(dev_priv)));
2702 #ifdef CONFIG_PM
2703         seq_printf(m, "Usage count: %d\n",
2704                    atomic_read(&dev_priv->drm.dev->power.usage_count));
2705 #else
2706         seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2707 #endif
2708         seq_printf(m, "PCI device power state: %s [%d]\n",
2709                    pci_power_name(pdev->current_state),
2710                    pdev->current_state);
2711
2712         return 0;
2713 }
2714
2715 static int i915_power_domain_info(struct seq_file *m, void *unused)
2716 {
2717         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2718         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2719         int i;
2720
2721         mutex_lock(&power_domains->lock);
2722
2723         seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2724         for (i = 0; i < power_domains->power_well_count; i++) {
2725                 struct i915_power_well *power_well;
2726                 enum intel_display_power_domain power_domain;
2727
2728                 power_well = &power_domains->power_wells[i];
2729                 seq_printf(m, "%-25s %d\n", power_well->name,
2730                            power_well->count);
2731
2732                 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2733                      power_domain++) {
2734                         if (!(BIT(power_domain) & power_well->domains))
2735                                 continue;
2736
2737                         seq_printf(m, "  %-23s %d\n",
2738                                  intel_display_power_domain_str(power_domain),
2739                                  power_domains->domain_use_count[power_domain]);
2740                 }
2741         }
2742
2743         mutex_unlock(&power_domains->lock);
2744
2745         return 0;
2746 }
2747
2748 static int i915_dmc_info(struct seq_file *m, void *unused)
2749 {
2750         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2751         struct intel_csr *csr;
2752
2753         if (!HAS_CSR(dev_priv)) {
2754                 seq_puts(m, "not supported\n");
2755                 return 0;
2756         }
2757
2758         csr = &dev_priv->csr;
2759
2760         intel_runtime_pm_get(dev_priv);
2761
2762         seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2763         seq_printf(m, "path: %s\n", csr->fw_path);
2764
2765         if (!csr->dmc_payload)
2766                 goto out;
2767
2768         seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2769                    CSR_VERSION_MINOR(csr->version));
2770
2771         if (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6)) {
2772                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2773                            I915_READ(SKL_CSR_DC3_DC5_COUNT));
2774                 seq_printf(m, "DC5 -> DC6 count: %d\n",
2775                            I915_READ(SKL_CSR_DC5_DC6_COUNT));
2776         } else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) {
2777                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2778                            I915_READ(BXT_CSR_DC3_DC5_COUNT));
2779         }
2780
2781 out:
2782         seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2783         seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2784         seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2785
2786         intel_runtime_pm_put(dev_priv);
2787
2788         return 0;
2789 }
2790
2791 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2792                                  struct drm_display_mode *mode)
2793 {
2794         int i;
2795
2796         for (i = 0; i < tabs; i++)
2797                 seq_putc(m, '\t');
2798
2799         seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2800                    mode->base.id, mode->name,
2801                    mode->vrefresh, mode->clock,
2802                    mode->hdisplay, mode->hsync_start,
2803                    mode->hsync_end, mode->htotal,
2804                    mode->vdisplay, mode->vsync_start,
2805                    mode->vsync_end, mode->vtotal,
2806                    mode->type, mode->flags);
2807 }
2808
2809 static void intel_encoder_info(struct seq_file *m,
2810                                struct intel_crtc *intel_crtc,
2811                                struct intel_encoder *intel_encoder)
2812 {
2813         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2814         struct drm_device *dev = &dev_priv->drm;
2815         struct drm_crtc *crtc = &intel_crtc->base;
2816         struct intel_connector *intel_connector;
2817         struct drm_encoder *encoder;
2818
2819         encoder = &intel_encoder->base;
2820         seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2821                    encoder->base.id, encoder->name);
2822         for_each_connector_on_encoder(dev, encoder, intel_connector) {
2823                 struct drm_connector *connector = &intel_connector->base;
2824                 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2825                            connector->base.id,
2826                            connector->name,
2827                            drm_get_connector_status_name(connector->status));
2828                 if (connector->status == connector_status_connected) {
2829                         struct drm_display_mode *mode = &crtc->mode;
2830                         seq_printf(m, ", mode:\n");
2831                         intel_seq_print_mode(m, 2, mode);
2832                 } else {
2833                         seq_putc(m, '\n');
2834                 }
2835         }
2836 }
2837
2838 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2839 {
2840         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2841         struct drm_device *dev = &dev_priv->drm;
2842         struct drm_crtc *crtc = &intel_crtc->base;
2843         struct intel_encoder *intel_encoder;
2844         struct drm_plane_state *plane_state = crtc->primary->state;
2845         struct drm_framebuffer *fb = plane_state->fb;
2846
2847         if (fb)
2848                 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2849                            fb->base.id, plane_state->src_x >> 16,
2850                            plane_state->src_y >> 16, fb->width, fb->height);
2851         else
2852                 seq_puts(m, "\tprimary plane disabled\n");
2853         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2854                 intel_encoder_info(m, intel_crtc, intel_encoder);
2855 }
2856
2857 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2858 {
2859         struct drm_display_mode *mode = panel->fixed_mode;
2860
2861         seq_printf(m, "\tfixed mode:\n");
2862         intel_seq_print_mode(m, 2, mode);
2863 }
2864
2865 static void intel_dp_info(struct seq_file *m,
2866                           struct intel_connector *intel_connector)
2867 {
2868         struct intel_encoder *intel_encoder = intel_connector->encoder;
2869         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2870
2871         seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2872         seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2873         if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
2874                 intel_panel_info(m, &intel_connector->panel);
2875
2876         drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports,
2877                                 &intel_dp->aux);
2878 }
2879
2880 static void intel_hdmi_info(struct seq_file *m,
2881                             struct intel_connector *intel_connector)
2882 {
2883         struct intel_encoder *intel_encoder = intel_connector->encoder;
2884         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2885
2886         seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
2887 }
2888
2889 static void intel_lvds_info(struct seq_file *m,
2890                             struct intel_connector *intel_connector)
2891 {
2892         intel_panel_info(m, &intel_connector->panel);
2893 }
2894
2895 static void intel_connector_info(struct seq_file *m,
2896                                  struct drm_connector *connector)
2897 {
2898         struct intel_connector *intel_connector = to_intel_connector(connector);
2899         struct intel_encoder *intel_encoder = intel_connector->encoder;
2900         struct drm_display_mode *mode;
2901
2902         seq_printf(m, "connector %d: type %s, status: %s\n",
2903                    connector->base.id, connector->name,
2904                    drm_get_connector_status_name(connector->status));
2905         if (connector->status == connector_status_connected) {
2906                 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2907                 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2908                            connector->display_info.width_mm,
2909                            connector->display_info.height_mm);
2910                 seq_printf(m, "\tsubpixel order: %s\n",
2911                            drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2912                 seq_printf(m, "\tCEA rev: %d\n",
2913                            connector->display_info.cea_rev);
2914         }
2915
2916         if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
2917                 return;
2918
2919         switch (connector->connector_type) {
2920         case DRM_MODE_CONNECTOR_DisplayPort:
2921         case DRM_MODE_CONNECTOR_eDP:
2922                 intel_dp_info(m, intel_connector);
2923                 break;
2924         case DRM_MODE_CONNECTOR_LVDS:
2925                 if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2926                         intel_lvds_info(m, intel_connector);
2927                 break;
2928         case DRM_MODE_CONNECTOR_HDMIA:
2929                 if (intel_encoder->type == INTEL_OUTPUT_HDMI ||
2930                     intel_encoder->type == INTEL_OUTPUT_UNKNOWN)
2931                         intel_hdmi_info(m, intel_connector);
2932                 break;
2933         default:
2934                 break;
2935         }
2936
2937         seq_printf(m, "\tmodes:\n");
2938         list_for_each_entry(mode, &connector->modes, head)
2939                 intel_seq_print_mode(m, 2, mode);
2940 }
2941
2942 static bool cursor_active(struct drm_i915_private *dev_priv, int pipe)
2943 {
2944         u32 state;
2945
2946         if (IS_845G(dev_priv) || IS_I865G(dev_priv))
2947                 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
2948         else
2949                 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2950
2951         return state;
2952 }
2953
2954 static bool cursor_position(struct drm_i915_private *dev_priv,
2955                             int pipe, int *x, int *y)
2956 {
2957         u32 pos;
2958
2959         pos = I915_READ(CURPOS(pipe));
2960
2961         *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2962         if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2963                 *x = -*x;
2964
2965         *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2966         if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2967                 *y = -*y;
2968
2969         return cursor_active(dev_priv, pipe);
2970 }
2971
2972 static const char *plane_type(enum drm_plane_type type)
2973 {
2974         switch (type) {
2975         case DRM_PLANE_TYPE_OVERLAY:
2976                 return "OVL";
2977         case DRM_PLANE_TYPE_PRIMARY:
2978                 return "PRI";
2979         case DRM_PLANE_TYPE_CURSOR:
2980                 return "CUR";
2981         /*
2982          * Deliberately omitting default: to generate compiler warnings
2983          * when a new drm_plane_type gets added.
2984          */
2985         }
2986
2987         return "unknown";
2988 }
2989
2990 static const char *plane_rotation(unsigned int rotation)
2991 {
2992         static char buf[48];
2993         /*
2994          * According to doc only one DRM_ROTATE_ is allowed but this
2995          * will print them all to visualize if the values are misused
2996          */
2997         snprintf(buf, sizeof(buf),
2998                  "%s%s%s%s%s%s(0x%08x)",
2999                  (rotation & DRM_ROTATE_0) ? "0 " : "",
3000                  (rotation & DRM_ROTATE_90) ? "90 " : "",
3001                  (rotation & DRM_ROTATE_180) ? "180 " : "",
3002                  (rotation & DRM_ROTATE_270) ? "270 " : "",
3003                  (rotation & DRM_REFLECT_X) ? "FLIPX " : "",
3004                  (rotation & DRM_REFLECT_Y) ? "FLIPY " : "",
3005                  rotation);
3006
3007         return buf;
3008 }
3009
3010 static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3011 {
3012         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3013         struct drm_device *dev = &dev_priv->drm;
3014         struct intel_plane *intel_plane;
3015
3016         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3017                 struct drm_plane_state *state;
3018                 struct drm_plane *plane = &intel_plane->base;
3019                 struct drm_format_name_buf format_name;
3020
3021                 if (!plane->state) {
3022                         seq_puts(m, "plane->state is NULL!\n");
3023                         continue;
3024                 }
3025
3026                 state = plane->state;
3027
3028                 if (state->fb) {
3029                         drm_get_format_name(state->fb->pixel_format, &format_name);
3030                 } else {
3031                         sprintf(format_name.str, "N/A");
3032                 }
3033
3034                 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3035                            plane->base.id,
3036                            plane_type(intel_plane->base.type),
3037                            state->crtc_x, state->crtc_y,
3038                            state->crtc_w, state->crtc_h,
3039                            (state->src_x >> 16),
3040                            ((state->src_x & 0xffff) * 15625) >> 10,
3041                            (state->src_y >> 16),
3042                            ((state->src_y & 0xffff) * 15625) >> 10,
3043                            (state->src_w >> 16),
3044                            ((state->src_w & 0xffff) * 15625) >> 10,
3045                            (state->src_h >> 16),
3046                            ((state->src_h & 0xffff) * 15625) >> 10,
3047                            format_name.str,
3048                            plane_rotation(state->rotation));
3049         }
3050 }
3051
3052 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3053 {
3054         struct intel_crtc_state *pipe_config;
3055         int num_scalers = intel_crtc->num_scalers;
3056         int i;
3057
3058         pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3059
3060         /* Not all platformas have a scaler */
3061         if (num_scalers) {
3062                 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3063                            num_scalers,
3064                            pipe_config->scaler_state.scaler_users,
3065                            pipe_config->scaler_state.scaler_id);
3066
3067                 for (i = 0; i < num_scalers; i++) {
3068                         struct intel_scaler *sc =
3069                                         &pipe_config->scaler_state.scalers[i];
3070
3071                         seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3072                                    i, yesno(sc->in_use), sc->mode);
3073                 }
3074                 seq_puts(m, "\n");
3075         } else {
3076                 seq_puts(m, "\tNo scalers available on this platform\n");
3077         }
3078 }
3079
3080 static int i915_display_info(struct seq_file *m, void *unused)
3081 {
3082         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3083         struct drm_device *dev = &dev_priv->drm;
3084         struct intel_crtc *crtc;
3085         struct drm_connector *connector;
3086
3087         intel_runtime_pm_get(dev_priv);
3088         drm_modeset_lock_all(dev);
3089         seq_printf(m, "CRTC info\n");
3090         seq_printf(m, "---------\n");
3091         for_each_intel_crtc(dev, crtc) {
3092                 bool active;
3093                 struct intel_crtc_state *pipe_config;
3094                 int x, y;
3095
3096                 pipe_config = to_intel_crtc_state(crtc->base.state);
3097
3098                 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3099                            crtc->base.base.id, pipe_name(crtc->pipe),
3100                            yesno(pipe_config->base.active),
3101                            pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3102                            yesno(pipe_config->dither), pipe_config->pipe_bpp);
3103
3104                 if (pipe_config->base.active) {
3105                         intel_crtc_info(m, crtc);
3106
3107                         active = cursor_position(dev_priv, crtc->pipe, &x, &y);
3108                         seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
3109                                    yesno(crtc->cursor_base),
3110                                    x, y, crtc->base.cursor->state->crtc_w,
3111                                    crtc->base.cursor->state->crtc_h,
3112                                    crtc->cursor_addr, yesno(active));
3113                         intel_scaler_info(m, crtc);
3114                         intel_plane_info(m, crtc);
3115                 }
3116
3117                 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3118                            yesno(!crtc->cpu_fifo_underrun_disabled),
3119                            yesno(!crtc->pch_fifo_underrun_disabled));
3120         }
3121
3122         seq_printf(m, "\n");
3123         seq_printf(m, "Connector info\n");
3124         seq_printf(m, "--------------\n");
3125         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3126                 intel_connector_info(m, connector);
3127         }
3128         drm_modeset_unlock_all(dev);
3129         intel_runtime_pm_put(dev_priv);
3130
3131         return 0;
3132 }
3133
3134 static int i915_engine_info(struct seq_file *m, void *unused)
3135 {
3136         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3137         struct intel_engine_cs *engine;
3138         enum intel_engine_id id;
3139
3140         intel_runtime_pm_get(dev_priv);
3141
3142         for_each_engine(engine, dev_priv, id) {
3143                 struct intel_breadcrumbs *b = &engine->breadcrumbs;
3144                 struct drm_i915_gem_request *rq;
3145                 struct rb_node *rb;
3146                 u64 addr;
3147
3148                 seq_printf(m, "%s\n", engine->name);
3149                 seq_printf(m, "\tcurrent seqno %x, last %x, hangcheck %x [%d ms]\n",
3150                            intel_engine_get_seqno(engine),
3151                            intel_engine_last_submit(engine),
3152                            engine->hangcheck.seqno,
3153                            jiffies_to_msecs(jiffies - engine->hangcheck.action_timestamp));
3154
3155                 rcu_read_lock();
3156
3157                 seq_printf(m, "\tRequests:\n");
3158
3159                 rq = list_first_entry(&engine->timeline->requests,
3160                                       struct drm_i915_gem_request, link);
3161                 if (&rq->link != &engine->timeline->requests)
3162                         print_request(m, rq, "\t\tfirst  ");
3163
3164                 rq = list_last_entry(&engine->timeline->requests,
3165                                      struct drm_i915_gem_request, link);
3166                 if (&rq->link != &engine->timeline->requests)
3167                         print_request(m, rq, "\t\tlast   ");
3168
3169                 rq = i915_gem_find_active_request(engine);
3170                 if (rq) {
3171                         print_request(m, rq, "\t\tactive ");
3172                         seq_printf(m,
3173                                    "\t\t[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]\n",
3174                                    rq->head, rq->postfix, rq->tail,
3175                                    rq->batch ? upper_32_bits(rq->batch->node.start) : ~0u,
3176                                    rq->batch ? lower_32_bits(rq->batch->node.start) : ~0u);
3177                 }
3178
3179                 seq_printf(m, "\tRING_START: 0x%08x [0x%08x]\n",
3180                            I915_READ(RING_START(engine->mmio_base)),
3181                            rq ? i915_ggtt_offset(rq->ring->vma) : 0);
3182                 seq_printf(m, "\tRING_HEAD:  0x%08x [0x%08x]\n",
3183                            I915_READ(RING_HEAD(engine->mmio_base)) & HEAD_ADDR,
3184                            rq ? rq->ring->head : 0);
3185                 seq_printf(m, "\tRING_TAIL:  0x%08x [0x%08x]\n",
3186                            I915_READ(RING_TAIL(engine->mmio_base)) & TAIL_ADDR,
3187                            rq ? rq->ring->tail : 0);
3188                 seq_printf(m, "\tRING_CTL:   0x%08x [%s]\n",
3189                            I915_READ(RING_CTL(engine->mmio_base)),
3190                            I915_READ(RING_CTL(engine->mmio_base)) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? "waiting" : "");
3191
3192                 rcu_read_unlock();
3193
3194                 addr = intel_engine_get_active_head(engine);
3195                 seq_printf(m, "\tACTHD:  0x%08x_%08x\n",
3196                            upper_32_bits(addr), lower_32_bits(addr));
3197                 addr = intel_engine_get_last_batch_head(engine);
3198                 seq_printf(m, "\tBBADDR: 0x%08x_%08x\n",
3199                            upper_32_bits(addr), lower_32_bits(addr));
3200
3201                 if (i915.enable_execlists) {
3202                         u32 ptr, read, write;
3203                         struct rb_node *rb;
3204
3205                         seq_printf(m, "\tExeclist status: 0x%08x %08x\n",
3206                                    I915_READ(RING_EXECLIST_STATUS_LO(engine)),
3207                                    I915_READ(RING_EXECLIST_STATUS_HI(engine)));
3208
3209                         ptr = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
3210                         read = GEN8_CSB_READ_PTR(ptr);
3211                         write = GEN8_CSB_WRITE_PTR(ptr);
3212                         seq_printf(m, "\tExeclist CSB read %d, write %d\n",
3213                                    read, write);
3214                         if (read >= GEN8_CSB_ENTRIES)
3215                                 read = 0;
3216                         if (write >= GEN8_CSB_ENTRIES)
3217                                 write = 0;
3218                         if (read > write)
3219                                 write += GEN8_CSB_ENTRIES;
3220                         while (read < write) {
3221                                 unsigned int idx = ++read % GEN8_CSB_ENTRIES;
3222
3223                                 seq_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n",
3224                                            idx,
3225                                            I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, idx)),
3226                                            I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, idx)));
3227                         }
3228
3229                         rcu_read_lock();
3230                         rq = READ_ONCE(engine->execlist_port[0].request);
3231                         if (rq)
3232                                 print_request(m, rq, "\t\tELSP[0] ");
3233                         else
3234                                 seq_printf(m, "\t\tELSP[0] idle\n");
3235                         rq = READ_ONCE(engine->execlist_port[1].request);
3236                         if (rq)
3237                                 print_request(m, rq, "\t\tELSP[1] ");
3238                         else
3239                                 seq_printf(m, "\t\tELSP[1] idle\n");
3240                         rcu_read_unlock();
3241
3242                         spin_lock_irq(&engine->timeline->lock);
3243                         for (rb = engine->execlist_first; rb; rb = rb_next(rb)) {
3244                                 rq = rb_entry(rb, typeof(*rq), priotree.node);
3245                                 print_request(m, rq, "\t\tQ ");
3246                         }
3247                         spin_unlock_irq(&engine->timeline->lock);
3248                 } else if (INTEL_GEN(dev_priv) > 6) {
3249                         seq_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
3250                                    I915_READ(RING_PP_DIR_BASE(engine)));
3251                         seq_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n",
3252                                    I915_READ(RING_PP_DIR_BASE_READ(engine)));
3253                         seq_printf(m, "\tPP_DIR_DCLV: 0x%08x\n",
3254                                    I915_READ(RING_PP_DIR_DCLV(engine)));
3255                 }
3256
3257                 spin_lock_irq(&b->lock);
3258                 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
3259                         struct intel_wait *w = container_of(rb, typeof(*w), node);
3260
3261                         seq_printf(m, "\t%s [%d] waiting for %x\n",
3262                                    w->tsk->comm, w->tsk->pid, w->seqno);
3263                 }
3264                 spin_unlock_irq(&b->lock);
3265
3266                 seq_puts(m, "\n");
3267         }
3268
3269         intel_runtime_pm_put(dev_priv);
3270
3271         return 0;
3272 }
3273
3274 static int i915_semaphore_status(struct seq_file *m, void *unused)
3275 {
3276         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3277         struct drm_device *dev = &dev_priv->drm;
3278         struct intel_engine_cs *engine;
3279         int num_rings = INTEL_INFO(dev_priv)->num_rings;
3280         enum intel_engine_id id;
3281         int j, ret;
3282
3283         if (!i915.semaphores) {
3284                 seq_puts(m, "Semaphores are disabled\n");
3285                 return 0;
3286         }
3287
3288         ret = mutex_lock_interruptible(&dev->struct_mutex);
3289         if (ret)
3290                 return ret;
3291         intel_runtime_pm_get(dev_priv);
3292
3293         if (IS_BROADWELL(dev_priv)) {
3294                 struct page *page;
3295                 uint64_t *seqno;
3296
3297                 page = i915_gem_object_get_page(dev_priv->semaphore->obj, 0);
3298
3299                 seqno = (uint64_t *)kmap_atomic(page);
3300                 for_each_engine(engine, dev_priv, id) {
3301                         uint64_t offset;
3302
3303                         seq_printf(m, "%s\n", engine->name);
3304
3305                         seq_puts(m, "  Last signal:");
3306                         for (j = 0; j < num_rings; j++) {
3307                                 offset = id * I915_NUM_ENGINES + j;
3308                                 seq_printf(m, "0x%08llx (0x%02llx) ",
3309                                            seqno[offset], offset * 8);
3310                         }
3311                         seq_putc(m, '\n');
3312
3313                         seq_puts(m, "  Last wait:  ");
3314                         for (j = 0; j < num_rings; j++) {
3315                                 offset = id + (j * I915_NUM_ENGINES);
3316                                 seq_printf(m, "0x%08llx (0x%02llx) ",
3317                                            seqno[offset], offset * 8);
3318                         }
3319                         seq_putc(m, '\n');
3320
3321                 }
3322                 kunmap_atomic(seqno);
3323         } else {
3324                 seq_puts(m, "  Last signal:");
3325                 for_each_engine(engine, dev_priv, id)
3326                         for (j = 0; j < num_rings; j++)
3327                                 seq_printf(m, "0x%08x\n",
3328                                            I915_READ(engine->semaphore.mbox.signal[j]));
3329                 seq_putc(m, '\n');
3330         }
3331
3332         intel_runtime_pm_put(dev_priv);
3333         mutex_unlock(&dev->struct_mutex);
3334         return 0;
3335 }
3336
3337 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3338 {
3339         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3340         struct drm_device *dev = &dev_priv->drm;
3341         int i;
3342
3343         drm_modeset_lock_all(dev);
3344         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3345                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3346
3347                 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3348                 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3349                            pll->config.crtc_mask, pll->active_mask, yesno(pll->on));
3350                 seq_printf(m, " tracked hardware state:\n");
3351                 seq_printf(m, " dpll:    0x%08x\n", pll->config.hw_state.dpll);
3352                 seq_printf(m, " dpll_md: 0x%08x\n",
3353                            pll->config.hw_state.dpll_md);
3354                 seq_printf(m, " fp0:     0x%08x\n", pll->config.hw_state.fp0);
3355                 seq_printf(m, " fp1:     0x%08x\n", pll->config.hw_state.fp1);
3356                 seq_printf(m, " wrpll:   0x%08x\n", pll->config.hw_state.wrpll);
3357         }
3358         drm_modeset_unlock_all(dev);
3359
3360         return 0;
3361 }
3362
3363 static int i915_wa_registers(struct seq_file *m, void *unused)
3364 {
3365         int i;
3366         int ret;
3367         struct intel_engine_cs *engine;
3368         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3369         struct drm_device *dev = &dev_priv->drm;
3370         struct i915_workarounds *workarounds = &dev_priv->workarounds;
3371         enum intel_engine_id id;
3372
3373         ret = mutex_lock_interruptible(&dev->struct_mutex);
3374         if (ret)
3375                 return ret;
3376
3377         intel_runtime_pm_get(dev_priv);
3378
3379         seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
3380         for_each_engine(engine, dev_priv, id)
3381                 seq_printf(m, "HW whitelist count for %s: %d\n",
3382                            engine->name, workarounds->hw_whitelist_count[id]);
3383         for (i = 0; i < workarounds->count; ++i) {
3384                 i915_reg_t addr;
3385                 u32 mask, value, read;
3386                 bool ok;
3387
3388                 addr = workarounds->reg[i].addr;
3389                 mask = workarounds->reg[i].mask;
3390                 value = workarounds->reg[i].value;
3391                 read = I915_READ(addr);
3392                 ok = (value & mask) == (read & mask);
3393                 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3394                            i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
3395         }
3396
3397         intel_runtime_pm_put(dev_priv);
3398         mutex_unlock(&dev->struct_mutex);
3399
3400         return 0;
3401 }
3402
3403 static int i915_ddb_info(struct seq_file *m, void *unused)
3404 {
3405         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3406         struct drm_device *dev = &dev_priv->drm;
3407         struct skl_ddb_allocation *ddb;
3408         struct skl_ddb_entry *entry;
3409         enum pipe pipe;
3410         int plane;
3411
3412         if (INTEL_GEN(dev_priv) < 9)
3413                 return 0;
3414
3415         drm_modeset_lock_all(dev);
3416
3417         ddb = &dev_priv->wm.skl_hw.ddb;
3418
3419         seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3420
3421         for_each_pipe(dev_priv, pipe) {
3422                 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3423
3424                 for_each_universal_plane(dev_priv, pipe, plane) {
3425                         entry = &ddb->plane[pipe][plane];
3426                         seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane + 1,
3427                                    entry->start, entry->end,
3428                                    skl_ddb_entry_size(entry));
3429                 }
3430
3431                 entry = &ddb->plane[pipe][PLANE_CURSOR];
3432                 seq_printf(m, "  %-13s%8u%8u%8u\n", "Cursor", entry->start,
3433                            entry->end, skl_ddb_entry_size(entry));
3434         }
3435
3436         drm_modeset_unlock_all(dev);
3437
3438         return 0;
3439 }
3440
3441 static void drrs_status_per_crtc(struct seq_file *m,
3442                                  struct drm_device *dev,
3443                                  struct intel_crtc *intel_crtc)
3444 {
3445         struct drm_i915_private *dev_priv = to_i915(dev);
3446         struct i915_drrs *drrs = &dev_priv->drrs;
3447         int vrefresh = 0;
3448         struct drm_connector *connector;
3449
3450         drm_for_each_connector(connector, dev) {
3451                 if (connector->state->crtc != &intel_crtc->base)
3452                         continue;
3453
3454                 seq_printf(m, "%s:\n", connector->name);
3455         }
3456
3457         if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3458                 seq_puts(m, "\tVBT: DRRS_type: Static");
3459         else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3460                 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3461         else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3462                 seq_puts(m, "\tVBT: DRRS_type: None");
3463         else
3464                 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3465
3466         seq_puts(m, "\n\n");
3467
3468         if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3469                 struct intel_panel *panel;
3470
3471                 mutex_lock(&drrs->mutex);
3472                 /* DRRS Supported */
3473                 seq_puts(m, "\tDRRS Supported: Yes\n");
3474
3475                 /* disable_drrs() will make drrs->dp NULL */
3476                 if (!drrs->dp) {
3477                         seq_puts(m, "Idleness DRRS: Disabled");
3478                         mutex_unlock(&drrs->mutex);
3479                         return;
3480                 }
3481
3482                 panel = &drrs->dp->attached_connector->panel;
3483                 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3484                                         drrs->busy_frontbuffer_bits);
3485
3486                 seq_puts(m, "\n\t\t");
3487                 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3488                         seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3489                         vrefresh = panel->fixed_mode->vrefresh;
3490                 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3491                         seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3492                         vrefresh = panel->downclock_mode->vrefresh;
3493                 } else {
3494                         seq_printf(m, "DRRS_State: Unknown(%d)\n",
3495                                                 drrs->refresh_rate_type);
3496                         mutex_unlock(&drrs->mutex);
3497                         return;
3498                 }
3499                 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3500
3501                 seq_puts(m, "\n\t\t");
3502                 mutex_unlock(&drrs->mutex);
3503         } else {
3504                 /* DRRS not supported. Print the VBT parameter*/
3505                 seq_puts(m, "\tDRRS Supported : No");
3506         }
3507         seq_puts(m, "\n");
3508 }
3509
3510 static int i915_drrs_status(struct seq_file *m, void *unused)
3511 {
3512         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3513         struct drm_device *dev = &dev_priv->drm;
3514         struct intel_crtc *intel_crtc;
3515         int active_crtc_cnt = 0;
3516
3517         drm_modeset_lock_all(dev);
3518         for_each_intel_crtc(dev, intel_crtc) {
3519                 if (intel_crtc->base.state->active) {
3520                         active_crtc_cnt++;
3521                         seq_printf(m, "\nCRTC %d:  ", active_crtc_cnt);
3522
3523                         drrs_status_per_crtc(m, dev, intel_crtc);
3524                 }
3525         }
3526         drm_modeset_unlock_all(dev);
3527
3528         if (!active_crtc_cnt)
3529                 seq_puts(m, "No active crtc found\n");
3530
3531         return 0;
3532 }
3533
3534 struct pipe_crc_info {
3535         const char *name;
3536         struct drm_i915_private *dev_priv;
3537         enum pipe pipe;
3538 };
3539
3540 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3541 {
3542         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3543         struct drm_device *dev = &dev_priv->drm;
3544         struct intel_encoder *intel_encoder;
3545         struct intel_digital_port *intel_dig_port;
3546         struct drm_connector *connector;
3547
3548         drm_modeset_lock_all(dev);
3549         drm_for_each_connector(connector, dev) {
3550                 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
3551                         continue;
3552
3553                 intel_encoder = intel_attached_encoder(connector);
3554                 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
3555                         continue;
3556
3557                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
3558                 if (!intel_dig_port->dp.can_mst)
3559                         continue;
3560
3561                 seq_printf(m, "MST Source Port %c\n",
3562                            port_name(intel_dig_port->port));
3563                 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3564         }
3565         drm_modeset_unlock_all(dev);
3566         return 0;
3567 }
3568
3569 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3570 {
3571         struct pipe_crc_info *info = inode->i_private;
3572         struct drm_i915_private *dev_priv = info->dev_priv;
3573         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3574
3575         if (info->pipe >= INTEL_INFO(dev_priv)->num_pipes)
3576                 return -ENODEV;
3577
3578         spin_lock_irq(&pipe_crc->lock);
3579
3580         if (pipe_crc->opened) {
3581                 spin_unlock_irq(&pipe_crc->lock);
3582                 return -EBUSY; /* already open */
3583         }
3584
3585         pipe_crc->opened = true;
3586         filep->private_data = inode->i_private;
3587
3588         spin_unlock_irq(&pipe_crc->lock);
3589
3590         return 0;
3591 }
3592
3593 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3594 {
3595         struct pipe_crc_info *info = inode->i_private;
3596         struct drm_i915_private *dev_priv = info->dev_priv;
3597         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3598
3599         spin_lock_irq(&pipe_crc->lock);
3600         pipe_crc->opened = false;
3601         spin_unlock_irq(&pipe_crc->lock);
3602
3603         return 0;
3604 }
3605
3606 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3607 #define PIPE_CRC_LINE_LEN       (6 * 8 + 5 + 1)
3608 /* account for \'0' */
3609 #define PIPE_CRC_BUFFER_LEN     (PIPE_CRC_LINE_LEN + 1)
3610
3611 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
3612 {
3613         assert_spin_locked(&pipe_crc->lock);
3614         return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3615                         INTEL_PIPE_CRC_ENTRIES_NR);
3616 }
3617
3618 static ssize_t
3619 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3620                    loff_t *pos)
3621 {
3622         struct pipe_crc_info *info = filep->private_data;
3623         struct drm_i915_private *dev_priv = info->dev_priv;
3624         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3625         char buf[PIPE_CRC_BUFFER_LEN];
3626         int n_entries;
3627         ssize_t bytes_read;
3628
3629         /*
3630          * Don't allow user space to provide buffers not big enough to hold
3631          * a line of data.
3632          */
3633         if (count < PIPE_CRC_LINE_LEN)
3634                 return -EINVAL;
3635
3636         if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
3637                 return 0;
3638
3639         /* nothing to read */
3640         spin_lock_irq(&pipe_crc->lock);
3641         while (pipe_crc_data_count(pipe_crc) == 0) {
3642                 int ret;
3643
3644                 if (filep->f_flags & O_NONBLOCK) {
3645                         spin_unlock_irq(&pipe_crc->lock);
3646                         return -EAGAIN;
3647                 }
3648
3649                 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3650                                 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3651                 if (ret) {
3652                         spin_unlock_irq(&pipe_crc->lock);
3653                         return ret;
3654                 }
3655         }
3656
3657         /* We now have one or more entries to read */
3658         n_entries = count / PIPE_CRC_LINE_LEN;
3659
3660         bytes_read = 0;
3661         while (n_entries > 0) {
3662                 struct intel_pipe_crc_entry *entry =
3663                         &pipe_crc->entries[pipe_crc->tail];
3664
3665                 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3666                              INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3667                         break;
3668
3669                 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3670                 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3671
3672                 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3673                                        "%8u %8x %8x %8x %8x %8x\n",
3674                                        entry->frame, entry->crc[0],
3675                                        entry->crc[1], entry->crc[2],
3676                                        entry->crc[3], entry->crc[4]);
3677
3678                 spin_unlock_irq(&pipe_crc->lock);
3679
3680                 if (copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN))
3681                         return -EFAULT;
3682
3683                 user_buf += PIPE_CRC_LINE_LEN;
3684                 n_entries--;
3685
3686                 spin_lock_irq(&pipe_crc->lock);
3687         }
3688
3689         spin_unlock_irq(&pipe_crc->lock);
3690
3691         return bytes_read;
3692 }
3693
3694 static const struct file_operations i915_pipe_crc_fops = {
3695         .owner = THIS_MODULE,
3696         .open = i915_pipe_crc_open,
3697         .read = i915_pipe_crc_read,
3698         .release = i915_pipe_crc_release,
3699 };
3700
3701 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3702         {
3703                 .name = "i915_pipe_A_crc",
3704                 .pipe = PIPE_A,
3705         },
3706         {
3707                 .name = "i915_pipe_B_crc",
3708                 .pipe = PIPE_B,
3709         },
3710         {
3711                 .name = "i915_pipe_C_crc",
3712                 .pipe = PIPE_C,
3713         },
3714 };
3715
3716 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3717                                 enum pipe pipe)
3718 {
3719         struct drm_i915_private *dev_priv = to_i915(minor->dev);
3720         struct dentry *ent;
3721         struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3722
3723         info->dev_priv = dev_priv;
3724         ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3725                                   &i915_pipe_crc_fops);
3726         if (!ent)
3727                 return -ENOMEM;
3728
3729         return drm_add_fake_info_node(minor, ent, info);
3730 }
3731
3732 static const char * const pipe_crc_sources[] = {
3733         "none",
3734         "plane1",
3735         "plane2",
3736         "pf",
3737         "pipe",
3738         "TV",
3739         "DP-B",
3740         "DP-C",
3741         "DP-D",
3742         "auto",
3743 };
3744
3745 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3746 {
3747         BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3748         return pipe_crc_sources[source];
3749 }
3750
3751 static int display_crc_ctl_show(struct seq_file *m, void *data)
3752 {
3753         struct drm_i915_private *dev_priv = m->private;
3754         int i;
3755
3756         for (i = 0; i < I915_MAX_PIPES; i++)
3757                 seq_printf(m, "%c %s\n", pipe_name(i),
3758                            pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3759
3760         return 0;
3761 }
3762
3763 static int display_crc_ctl_open(struct inode *inode, struct file *file)
3764 {
3765         return single_open(file, display_crc_ctl_show, inode->i_private);
3766 }
3767
3768 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3769                                  uint32_t *val)
3770 {
3771         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3772                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3773
3774         switch (*source) {
3775         case INTEL_PIPE_CRC_SOURCE_PIPE:
3776                 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3777                 break;
3778         case INTEL_PIPE_CRC_SOURCE_NONE:
3779                 *val = 0;
3780                 break;
3781         default:
3782                 return -EINVAL;
3783         }
3784
3785         return 0;
3786 }
3787
3788 static int i9xx_pipe_crc_auto_source(struct drm_i915_private *dev_priv,
3789                                      enum pipe pipe,
3790                                      enum intel_pipe_crc_source *source)
3791 {
3792         struct drm_device *dev = &dev_priv->drm;
3793         struct intel_encoder *encoder;
3794         struct intel_crtc *crtc;
3795         struct intel_digital_port *dig_port;
3796         int ret = 0;
3797
3798         *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3799
3800         drm_modeset_lock_all(dev);
3801         for_each_intel_encoder(dev, encoder) {
3802                 if (!encoder->base.crtc)
3803                         continue;
3804
3805                 crtc = to_intel_crtc(encoder->base.crtc);
3806
3807                 if (crtc->pipe != pipe)
3808                         continue;
3809
3810                 switch (encoder->type) {
3811                 case INTEL_OUTPUT_TVOUT:
3812                         *source = INTEL_PIPE_CRC_SOURCE_TV;
3813                         break;
3814                 case INTEL_OUTPUT_DP:
3815                 case INTEL_OUTPUT_EDP:
3816                         dig_port = enc_to_dig_port(&encoder->base);
3817                         switch (dig_port->port) {
3818                         case PORT_B:
3819                                 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3820                                 break;
3821                         case PORT_C:
3822                                 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3823                                 break;
3824                         case PORT_D:
3825                                 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3826                                 break;
3827                         default:
3828                                 WARN(1, "nonexisting DP port %c\n",
3829                                      port_name(dig_port->port));
3830                                 break;
3831                         }
3832                         break;
3833                 default:
3834                         break;
3835                 }
3836         }
3837         drm_modeset_unlock_all(dev);
3838
3839         return ret;
3840 }
3841
3842 static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
3843                                 enum pipe pipe,
3844                                 enum intel_pipe_crc_source *source,
3845                                 uint32_t *val)
3846 {
3847         bool need_stable_symbols = false;
3848
3849         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3850                 int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
3851                 if (ret)
3852                         return ret;
3853         }
3854
3855         switch (*source) {
3856         case INTEL_PIPE_CRC_SOURCE_PIPE:
3857                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3858                 break;
3859         case INTEL_PIPE_CRC_SOURCE_DP_B:
3860                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3861                 need_stable_symbols = true;
3862                 break;
3863         case INTEL_PIPE_CRC_SOURCE_DP_C:
3864                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3865                 need_stable_symbols = true;
3866                 break;
3867         case INTEL_PIPE_CRC_SOURCE_DP_D:
3868                 if (!IS_CHERRYVIEW(dev_priv))
3869                         return -EINVAL;
3870                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3871                 need_stable_symbols = true;
3872                 break;
3873         case INTEL_PIPE_CRC_SOURCE_NONE:
3874                 *val = 0;
3875                 break;
3876         default:
3877                 return -EINVAL;
3878         }
3879
3880         /*
3881          * When the pipe CRC tap point is after the transcoders we need
3882          * to tweak symbol-level features to produce a deterministic series of
3883          * symbols for a given frame. We need to reset those features only once
3884          * a frame (instead of every nth symbol):
3885          *   - DC-balance: used to ensure a better clock recovery from the data
3886          *     link (SDVO)
3887          *   - DisplayPort scrambling: used for EMI reduction
3888          */
3889         if (need_stable_symbols) {
3890                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3891
3892                 tmp |= DC_BALANCE_RESET_VLV;
3893                 switch (pipe) {
3894                 case PIPE_A:
3895                         tmp |= PIPE_A_SCRAMBLE_RESET;
3896                         break;
3897                 case PIPE_B:
3898                         tmp |= PIPE_B_SCRAMBLE_RESET;
3899                         break;
3900                 case PIPE_C:
3901                         tmp |= PIPE_C_SCRAMBLE_RESET;
3902                         break;
3903                 default:
3904                         return -EINVAL;
3905                 }
3906                 I915_WRITE(PORT_DFT2_G4X, tmp);
3907         }
3908
3909         return 0;
3910 }
3911
3912 static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
3913                                  enum pipe pipe,
3914                                  enum intel_pipe_crc_source *source,
3915                                  uint32_t *val)
3916 {
3917         bool need_stable_symbols = false;
3918
3919         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3920                 int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
3921                 if (ret)
3922                         return ret;
3923         }
3924
3925         switch (*source) {
3926         case INTEL_PIPE_CRC_SOURCE_PIPE:
3927                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3928                 break;
3929         case INTEL_PIPE_CRC_SOURCE_TV:
3930                 if (!SUPPORTS_TV(dev_priv))
3931                         return -EINVAL;
3932                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3933                 break;
3934         case INTEL_PIPE_CRC_SOURCE_DP_B:
3935                 if (!IS_G4X(dev_priv))
3936                         return -EINVAL;
3937                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3938                 need_stable_symbols = true;
3939                 break;
3940         case INTEL_PIPE_CRC_SOURCE_DP_C:
3941                 if (!IS_G4X(dev_priv))
3942                         return -EINVAL;
3943                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3944                 need_stable_symbols = true;
3945                 break;
3946         case INTEL_PIPE_CRC_SOURCE_DP_D:
3947                 if (!IS_G4X(dev_priv))
3948                         return -EINVAL;
3949                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3950                 need_stable_symbols = true;
3951                 break;
3952         case INTEL_PIPE_CRC_SOURCE_NONE:
3953                 *val = 0;
3954                 break;
3955         default:
3956                 return -EINVAL;
3957         }
3958
3959         /*
3960          * When the pipe CRC tap point is after the transcoders we need
3961          * to tweak symbol-level features to produce a deterministic series of
3962          * symbols for a given frame. We need to reset those features only once
3963          * a frame (instead of every nth symbol):
3964          *   - DC-balance: used to ensure a better clock recovery from the data
3965          *     link (SDVO)
3966          *   - DisplayPort scrambling: used for EMI reduction
3967          */
3968         if (need_stable_symbols) {
3969                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3970
3971                 WARN_ON(!IS_G4X(dev_priv));
3972
3973                 I915_WRITE(PORT_DFT_I9XX,
3974                            I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3975
3976                 if (pipe == PIPE_A)
3977                         tmp |= PIPE_A_SCRAMBLE_RESET;
3978                 else
3979                         tmp |= PIPE_B_SCRAMBLE_RESET;
3980
3981                 I915_WRITE(PORT_DFT2_G4X, tmp);
3982         }
3983
3984         return 0;
3985 }
3986
3987 static void vlv_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
3988                                          enum pipe pipe)
3989 {
3990         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3991
3992         switch (pipe) {
3993         case PIPE_A:
3994                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3995                 break;
3996         case PIPE_B:
3997                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3998                 break;
3999         case PIPE_C:
4000                 tmp &= ~PIPE_C_SCRAMBLE_RESET;
4001                 break;
4002         default:
4003                 return;
4004         }
4005         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
4006                 tmp &= ~DC_BALANCE_RESET_VLV;
4007         I915_WRITE(PORT_DFT2_G4X, tmp);
4008
4009 }
4010
4011 static void g4x_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
4012                                          enum pipe pipe)
4013 {
4014         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
4015
4016         if (pipe == PIPE_A)
4017                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
4018         else
4019                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
4020         I915_WRITE(PORT_DFT2_G4X, tmp);
4021
4022         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
4023                 I915_WRITE(PORT_DFT_I9XX,
4024                            I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
4025         }
4026 }
4027
4028 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
4029                                 uint32_t *val)
4030 {
4031         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
4032                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
4033
4034         switch (*source) {
4035         case INTEL_PIPE_CRC_SOURCE_PLANE1:
4036                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
4037                 break;
4038         case INTEL_PIPE_CRC_SOURCE_PLANE2:
4039                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
4040                 break;
4041         case INTEL_PIPE_CRC_SOURCE_PIPE:
4042                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
4043                 break;
4044         case INTEL_PIPE_CRC_SOURCE_NONE:
4045                 *val = 0;
4046                 break;
4047         default:
4048                 return -EINVAL;
4049         }
4050
4051         return 0;
4052 }
4053
4054 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_i915_private *dev_priv,
4055                                         bool enable)
4056 {
4057         struct drm_device *dev = &dev_priv->drm;
4058         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
4059         struct intel_crtc_state *pipe_config;
4060         struct drm_atomic_state *state;
4061         int ret = 0;
4062
4063         drm_modeset_lock_all(dev);
4064         state = drm_atomic_state_alloc(dev);
4065         if (!state) {
4066                 ret = -ENOMEM;
4067                 goto out;
4068         }
4069
4070         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
4071         pipe_config = intel_atomic_get_crtc_state(state, crtc);
4072         if (IS_ERR(pipe_config)) {
4073                 ret = PTR_ERR(pipe_config);
4074                 goto out;
4075         }
4076
4077         pipe_config->pch_pfit.force_thru = enable;
4078         if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
4079             pipe_config->pch_pfit.enabled != enable)
4080                 pipe_config->base.connectors_changed = true;
4081
4082         ret = drm_atomic_commit(state);
4083 out:
4084         WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
4085         drm_modeset_unlock_all(dev);
4086         drm_atomic_state_put(state);
4087 }
4088
4089 static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
4090                                 enum pipe pipe,
4091                                 enum intel_pipe_crc_source *source,
4092                                 uint32_t *val)
4093 {
4094         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
4095                 *source = INTEL_PIPE_CRC_SOURCE_PF;
4096
4097         switch (*source) {
4098         case INTEL_PIPE_CRC_SOURCE_PLANE1:
4099                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
4100                 break;
4101         case INTEL_PIPE_CRC_SOURCE_PLANE2:
4102                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
4103                 break;
4104         case INTEL_PIPE_CRC_SOURCE_PF:
4105                 if (IS_HASWELL(dev_priv) && pipe == PIPE_A)
4106                         hsw_trans_edp_pipe_A_crc_wa(dev_priv, true);
4107
4108                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
4109                 break;
4110         case INTEL_PIPE_CRC_SOURCE_NONE:
4111                 *val = 0;
4112                 break;
4113         default:
4114                 return -EINVAL;
4115         }
4116
4117         return 0;
4118 }
4119
4120 static int pipe_crc_set_source(struct drm_i915_private *dev_priv,
4121                                enum pipe pipe,
4122                                enum intel_pipe_crc_source source)
4123 {
4124         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
4125         struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
4126         enum intel_display_power_domain power_domain;
4127         u32 val = 0; /* shut up gcc */
4128         int ret;
4129
4130         if (pipe_crc->source == source)
4131                 return 0;
4132
4133         /* forbid changing the source without going back to 'none' */
4134         if (pipe_crc->source && source)
4135                 return -EINVAL;
4136
4137         power_domain = POWER_DOMAIN_PIPE(pipe);
4138         if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
4139                 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
4140                 return -EIO;
4141         }
4142
4143         if (IS_GEN2(dev_priv))
4144                 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
4145         else if (INTEL_GEN(dev_priv) < 5)
4146                 ret = i9xx_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val);
4147         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4148                 ret = vlv_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val);
4149         else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv))
4150                 ret = ilk_pipe_crc_ctl_reg(&source, &val);
4151         else
4152                 ret = ivb_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val);
4153
4154         if (ret != 0)
4155                 goto out;
4156
4157         /* none -> real source transition */
4158         if (source) {
4159                 struct intel_pipe_crc_entry *entries;
4160
4161                 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4162                                  pipe_name(pipe), pipe_crc_source_name(source));
4163
4164                 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
4165                                   sizeof(pipe_crc->entries[0]),
4166                                   GFP_KERNEL);
4167                 if (!entries) {
4168                         ret = -ENOMEM;
4169                         goto out;
4170                 }
4171
4172                 /*
4173                  * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4174                  * enabled and disabled dynamically based on package C states,
4175                  * user space can't make reliable use of the CRCs, so let's just
4176                  * completely disable it.
4177                  */
4178                 hsw_disable_ips(crtc);
4179
4180                 spin_lock_irq(&pipe_crc->lock);
4181                 kfree(pipe_crc->entries);
4182                 pipe_crc->entries = entries;
4183                 pipe_crc->head = 0;
4184                 pipe_crc->tail = 0;
4185                 spin_unlock_irq(&pipe_crc->lock);
4186         }
4187
4188         pipe_crc->source = source;
4189
4190         I915_WRITE(PIPE_CRC_CTL(pipe), val);
4191         POSTING_READ(PIPE_CRC_CTL(pipe));
4192
4193         /* real source -> none transition */
4194         if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
4195                 struct intel_pipe_crc_entry *entries;
4196                 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv,
4197                                                                   pipe);
4198
4199                 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4200                                  pipe_name(pipe));
4201
4202                 drm_modeset_lock(&crtc->base.mutex, NULL);
4203                 if (crtc->base.state->active)
4204                         intel_wait_for_vblank(dev_priv, pipe);
4205                 drm_modeset_unlock(&crtc->base.mutex);
4206
4207                 spin_lock_irq(&pipe_crc->lock);
4208                 entries = pipe_crc->entries;
4209                 pipe_crc->entries = NULL;
4210                 pipe_crc->head = 0;
4211                 pipe_crc->tail = 0;
4212                 spin_unlock_irq(&pipe_crc->lock);
4213
4214                 kfree(entries);
4215
4216                 if (IS_G4X(dev_priv))
4217                         g4x_undo_pipe_scramble_reset(dev_priv, pipe);
4218                 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4219                         vlv_undo_pipe_scramble_reset(dev_priv, pipe);
4220                 else if (IS_HASWELL(dev_priv) && pipe == PIPE_A)
4221                         hsw_trans_edp_pipe_A_crc_wa(dev_priv, false);
4222
4223                 hsw_enable_ips(crtc);
4224         }
4225
4226         ret = 0;
4227
4228 out:
4229         intel_display_power_put(dev_priv, power_domain);
4230
4231         return ret;
4232 }
4233
4234 /*
4235  * Parse pipe CRC command strings:
4236  *   command: wsp* object wsp+ name wsp+ source wsp*
4237  *   object: 'pipe'
4238  *   name: (A | B | C)
4239  *   source: (none | plane1 | plane2 | pf)
4240  *   wsp: (#0x20 | #0x9 | #0xA)+
4241  *
4242  * eg.:
4243  *  "pipe A plane1"  ->  Start CRC computations on plane1 of pipe A
4244  *  "pipe A none"    ->  Stop CRC
4245  */
4246 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
4247 {
4248         int n_words = 0;
4249
4250         while (*buf) {
4251                 char *end;
4252
4253                 /* skip leading white space */
4254                 buf = skip_spaces(buf);
4255                 if (!*buf)
4256                         break;  /* end of buffer */
4257
4258                 /* find end of word */
4259                 for (end = buf; *end && !isspace(*end); end++)
4260                         ;
4261
4262                 if (n_words == max_words) {
4263                         DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4264                                          max_words);
4265                         return -EINVAL; /* ran out of words[] before bytes */
4266                 }
4267
4268                 if (*end)
4269                         *end++ = '\0';
4270                 words[n_words++] = buf;
4271                 buf = end;
4272         }
4273
4274         return n_words;
4275 }
4276
4277 enum intel_pipe_crc_object {
4278         PIPE_CRC_OBJECT_PIPE,
4279 };
4280
4281 static const char * const pipe_crc_objects[] = {
4282         "pipe",
4283 };
4284
4285 static int
4286 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
4287 {
4288         int i;
4289
4290         for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
4291                 if (!strcmp(buf, pipe_crc_objects[i])) {
4292                         *o = i;
4293                         return 0;
4294                     }
4295
4296         return -EINVAL;
4297 }
4298
4299 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
4300 {
4301         const char name = buf[0];
4302
4303         if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
4304                 return -EINVAL;
4305
4306         *pipe = name - 'A';
4307
4308         return 0;
4309 }
4310
4311 static int
4312 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
4313 {
4314         int i;
4315
4316         for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
4317                 if (!strcmp(buf, pipe_crc_sources[i])) {
4318                         *s = i;
4319                         return 0;
4320                     }
4321
4322         return -EINVAL;
4323 }
4324
4325 static int display_crc_ctl_parse(struct drm_i915_private *dev_priv,
4326                                  char *buf, size_t len)
4327 {
4328 #define N_WORDS 3
4329         int n_words;
4330         char *words[N_WORDS];
4331         enum pipe pipe;
4332         enum intel_pipe_crc_object object;
4333         enum intel_pipe_crc_source source;
4334
4335         n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
4336         if (n_words != N_WORDS) {
4337                 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4338                                  N_WORDS);
4339                 return -EINVAL;
4340         }
4341
4342         if (display_crc_ctl_parse_object(words[0], &object) < 0) {
4343                 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
4344                 return -EINVAL;
4345         }
4346
4347         if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
4348                 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
4349                 return -EINVAL;
4350         }
4351
4352         if (display_crc_ctl_parse_source(words[2], &source) < 0) {
4353                 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
4354                 return -EINVAL;
4355         }
4356
4357         return pipe_crc_set_source(dev_priv, pipe, source);
4358 }
4359
4360 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
4361                                      size_t len, loff_t *offp)
4362 {
4363         struct seq_file *m = file->private_data;
4364         struct drm_i915_private *dev_priv = m->private;
4365         char *tmpbuf;
4366         int ret;
4367
4368         if (len == 0)
4369                 return 0;
4370
4371         if (len > PAGE_SIZE - 1) {
4372                 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4373                                  PAGE_SIZE);
4374                 return -E2BIG;
4375         }
4376
4377         tmpbuf = kmalloc(len + 1, GFP_KERNEL);
4378         if (!tmpbuf)
4379                 return -ENOMEM;
4380
4381         if (copy_from_user(tmpbuf, ubuf, len)) {
4382                 ret = -EFAULT;
4383                 goto out;
4384         }
4385         tmpbuf[len] = '\0';
4386
4387         ret = display_crc_ctl_parse(dev_priv, tmpbuf, len);
4388
4389 out:
4390         kfree(tmpbuf);
4391         if (ret < 0)
4392                 return ret;
4393
4394         *offp += len;
4395         return len;
4396 }
4397
4398 static const struct file_operations i915_display_crc_ctl_fops = {
4399         .owner = THIS_MODULE,
4400         .open = display_crc_ctl_open,
4401         .read = seq_read,
4402         .llseek = seq_lseek,
4403         .release = single_release,
4404         .write = display_crc_ctl_write
4405 };
4406
4407 static ssize_t i915_displayport_test_active_write(struct file *file,
4408                                                   const char __user *ubuf,
4409                                                   size_t len, loff_t *offp)
4410 {
4411         char *input_buffer;
4412         int status = 0;
4413         struct drm_device *dev;
4414         struct drm_connector *connector;
4415         struct list_head *connector_list;
4416         struct intel_dp *intel_dp;
4417         int val = 0;
4418
4419         dev = ((struct seq_file *)file->private_data)->private;
4420
4421         connector_list = &dev->mode_config.connector_list;
4422
4423         if (len == 0)
4424                 return 0;
4425
4426         input_buffer = kmalloc(len + 1, GFP_KERNEL);
4427         if (!input_buffer)
4428                 return -ENOMEM;
4429
4430         if (copy_from_user(input_buffer, ubuf, len)) {
4431                 status = -EFAULT;
4432                 goto out;
4433         }
4434
4435         input_buffer[len] = '\0';
4436         DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4437
4438         list_for_each_entry(connector, connector_list, head) {
4439                 if (connector->connector_type !=
4440                     DRM_MODE_CONNECTOR_DisplayPort)
4441                         continue;
4442
4443                 if (connector->status == connector_status_connected &&
4444                     connector->encoder != NULL) {
4445                         intel_dp = enc_to_intel_dp(connector->encoder);
4446                         status = kstrtoint(input_buffer, 10, &val);
4447                         if (status < 0)
4448                                 goto out;
4449                         DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4450                         /* To prevent erroneous activation of the compliance
4451                          * testing code, only accept an actual value of 1 here
4452                          */
4453                         if (val == 1)
4454                                 intel_dp->compliance_test_active = 1;
4455                         else
4456                                 intel_dp->compliance_test_active = 0;
4457                 }
4458         }
4459 out:
4460         kfree(input_buffer);
4461         if (status < 0)
4462                 return status;
4463
4464         *offp += len;
4465         return len;
4466 }
4467
4468 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4469 {
4470         struct drm_device *dev = m->private;
4471         struct drm_connector *connector;
4472         struct list_head *connector_list = &dev->mode_config.connector_list;
4473         struct intel_dp *intel_dp;
4474
4475         list_for_each_entry(connector, connector_list, head) {
4476                 if (connector->connector_type !=
4477                     DRM_MODE_CONNECTOR_DisplayPort)
4478                         continue;
4479
4480                 if (connector->status == connector_status_connected &&
4481                     connector->encoder != NULL) {
4482                         intel_dp = enc_to_intel_dp(connector->encoder);
4483                         if (intel_dp->compliance_test_active)
4484                                 seq_puts(m, "1");
4485                         else
4486                                 seq_puts(m, "0");
4487                 } else
4488                         seq_puts(m, "0");
4489         }
4490
4491         return 0;
4492 }
4493
4494 static int i915_displayport_test_active_open(struct inode *inode,
4495                                              struct file *file)
4496 {
4497         struct drm_i915_private *dev_priv = inode->i_private;
4498
4499         return single_open(file, i915_displayport_test_active_show,
4500                            &dev_priv->drm);
4501 }
4502
4503 static const struct file_operations i915_displayport_test_active_fops = {
4504         .owner = THIS_MODULE,
4505         .open = i915_displayport_test_active_open,
4506         .read = seq_read,
4507         .llseek = seq_lseek,
4508         .release = single_release,
4509         .write = i915_displayport_test_active_write
4510 };
4511
4512 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4513 {
4514         struct drm_device *dev = m->private;
4515         struct drm_connector *connector;
4516         struct list_head *connector_list = &dev->mode_config.connector_list;
4517         struct intel_dp *intel_dp;
4518
4519         list_for_each_entry(connector, connector_list, head) {
4520                 if (connector->connector_type !=
4521                     DRM_MODE_CONNECTOR_DisplayPort)
4522                         continue;
4523
4524                 if (connector->status == connector_status_connected &&
4525                     connector->encoder != NULL) {
4526                         intel_dp = enc_to_intel_dp(connector->encoder);
4527                         seq_printf(m, "%lx", intel_dp->compliance_test_data);
4528                 } else
4529                         seq_puts(m, "0");
4530         }
4531
4532         return 0;
4533 }
4534 static int i915_displayport_test_data_open(struct inode *inode,
4535                                            struct file *file)
4536 {
4537         struct drm_i915_private *dev_priv = inode->i_private;
4538
4539         return single_open(file, i915_displayport_test_data_show,
4540                            &dev_priv->drm);
4541 }
4542
4543 static const struct file_operations i915_displayport_test_data_fops = {
4544         .owner = THIS_MODULE,
4545         .open = i915_displayport_test_data_open,
4546         .read = seq_read,
4547         .llseek = seq_lseek,
4548         .release = single_release
4549 };
4550
4551 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4552 {
4553         struct drm_device *dev = m->private;
4554         struct drm_connector *connector;
4555         struct list_head *connector_list = &dev->mode_config.connector_list;
4556         struct intel_dp *intel_dp;
4557
4558         list_for_each_entry(connector, connector_list, head) {
4559                 if (connector->connector_type !=
4560                     DRM_MODE_CONNECTOR_DisplayPort)
4561                         continue;
4562
4563                 if (connector->status == connector_status_connected &&
4564                     connector->encoder != NULL) {
4565                         intel_dp = enc_to_intel_dp(connector->encoder);
4566                         seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4567                 } else
4568                         seq_puts(m, "0");
4569         }
4570
4571         return 0;
4572 }
4573
4574 static int i915_displayport_test_type_open(struct inode *inode,
4575                                        struct file *file)
4576 {
4577         struct drm_i915_private *dev_priv = inode->i_private;
4578
4579         return single_open(file, i915_displayport_test_type_show,
4580                            &dev_priv->drm);
4581 }
4582
4583 static const struct file_operations i915_displayport_test_type_fops = {
4584         .owner = THIS_MODULE,
4585         .open = i915_displayport_test_type_open,
4586         .read = seq_read,
4587         .llseek = seq_lseek,
4588         .release = single_release
4589 };
4590
4591 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
4592 {
4593         struct drm_i915_private *dev_priv = m->private;
4594         struct drm_device *dev = &dev_priv->drm;
4595         int level;
4596         int num_levels;
4597
4598         if (IS_CHERRYVIEW(dev_priv))
4599                 num_levels = 3;
4600         else if (IS_VALLEYVIEW(dev_priv))
4601                 num_levels = 1;
4602         else
4603                 num_levels = ilk_wm_max_level(dev_priv) + 1;
4604
4605         drm_modeset_lock_all(dev);
4606
4607         for (level = 0; level < num_levels; level++) {
4608                 unsigned int latency = wm[level];
4609
4610                 /*
4611                  * - WM1+ latency values in 0.5us units
4612                  * - latencies are in us on gen9/vlv/chv
4613                  */
4614                 if (INTEL_GEN(dev_priv) >= 9 || IS_VALLEYVIEW(dev_priv) ||
4615                     IS_CHERRYVIEW(dev_priv))
4616                         latency *= 10;
4617                 else if (level > 0)
4618                         latency *= 5;
4619
4620                 seq_printf(m, "WM%d %u (%u.%u usec)\n",
4621                            level, wm[level], latency / 10, latency % 10);
4622         }
4623
4624         drm_modeset_unlock_all(dev);
4625 }
4626
4627 static int pri_wm_latency_show(struct seq_file *m, void *data)
4628 {
4629         struct drm_i915_private *dev_priv = m->private;
4630         const uint16_t *latencies;
4631
4632         if (INTEL_GEN(dev_priv) >= 9)
4633                 latencies = dev_priv->wm.skl_latency;
4634         else
4635                 latencies = dev_priv->wm.pri_latency;
4636
4637         wm_latency_show(m, latencies);
4638
4639         return 0;
4640 }
4641
4642 static int spr_wm_latency_show(struct seq_file *m, void *data)
4643 {
4644         struct drm_i915_private *dev_priv = m->private;
4645         const uint16_t *latencies;
4646
4647         if (INTEL_GEN(dev_priv) >= 9)
4648                 latencies = dev_priv->wm.skl_latency;
4649         else
4650                 latencies = dev_priv->wm.spr_latency;
4651
4652         wm_latency_show(m, latencies);
4653
4654         return 0;
4655 }
4656
4657 static int cur_wm_latency_show(struct seq_file *m, void *data)
4658 {
4659         struct drm_i915_private *dev_priv = m->private;
4660         const uint16_t *latencies;
4661
4662         if (INTEL_GEN(dev_priv) >= 9)
4663                 latencies = dev_priv->wm.skl_latency;
4664         else
4665                 latencies = dev_priv->wm.cur_latency;
4666
4667         wm_latency_show(m, latencies);
4668
4669         return 0;
4670 }
4671
4672 static int pri_wm_latency_open(struct inode *inode, struct file *file)
4673 {
4674         struct drm_i915_private *dev_priv = inode->i_private;
4675
4676         if (INTEL_GEN(dev_priv) < 5)
4677                 return -ENODEV;
4678
4679         return single_open(file, pri_wm_latency_show, dev_priv);
4680 }
4681
4682 static int spr_wm_latency_open(struct inode *inode, struct file *file)
4683 {
4684         struct drm_i915_private *dev_priv = inode->i_private;
4685
4686         if (HAS_GMCH_DISPLAY(dev_priv))
4687                 return -ENODEV;
4688
4689         return single_open(file, spr_wm_latency_show, dev_priv);
4690 }
4691
4692 static int cur_wm_latency_open(struct inode *inode, struct file *file)
4693 {
4694         struct drm_i915_private *dev_priv = inode->i_private;
4695
4696         if (HAS_GMCH_DISPLAY(dev_priv))
4697                 return -ENODEV;
4698
4699         return single_open(file, cur_wm_latency_show, dev_priv);
4700 }
4701
4702 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
4703                                 size_t len, loff_t *offp, uint16_t wm[8])
4704 {
4705         struct seq_file *m = file->private_data;
4706         struct drm_i915_private *dev_priv = m->private;
4707         struct drm_device *dev = &dev_priv->drm;
4708         uint16_t new[8] = { 0 };
4709         int num_levels;
4710         int level;
4711         int ret;
4712         char tmp[32];
4713
4714         if (IS_CHERRYVIEW(dev_priv))
4715                 num_levels = 3;
4716         else if (IS_VALLEYVIEW(dev_priv))
4717                 num_levels = 1;
4718         else
4719                 num_levels = ilk_wm_max_level(dev_priv) + 1;
4720
4721         if (len >= sizeof(tmp))
4722                 return -EINVAL;
4723
4724         if (copy_from_user(tmp, ubuf, len))
4725                 return -EFAULT;
4726
4727         tmp[len] = '\0';
4728
4729         ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4730                      &new[0], &new[1], &new[2], &new[3],
4731                      &new[4], &new[5], &new[6], &new[7]);
4732         if (ret != num_levels)
4733                 return -EINVAL;
4734
4735         drm_modeset_lock_all(dev);
4736
4737         for (level = 0; level < num_levels; level++)
4738                 wm[level] = new[level];
4739
4740         drm_modeset_unlock_all(dev);
4741
4742         return len;
4743 }
4744
4745
4746 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4747                                     size_t len, loff_t *offp)
4748 {
4749         struct seq_file *m = file->private_data;
4750         struct drm_i915_private *dev_priv = m->private;
4751         uint16_t *latencies;
4752
4753         if (INTEL_GEN(dev_priv) >= 9)
4754                 latencies = dev_priv->wm.skl_latency;
4755         else
4756                 latencies = dev_priv->wm.pri_latency;
4757
4758         return wm_latency_write(file, ubuf, len, offp, latencies);
4759 }
4760
4761 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4762                                     size_t len, loff_t *offp)
4763 {
4764         struct seq_file *m = file->private_data;
4765         struct drm_i915_private *dev_priv = m->private;
4766         uint16_t *latencies;
4767
4768         if (INTEL_GEN(dev_priv) >= 9)
4769                 latencies = dev_priv->wm.skl_latency;
4770         else
4771                 latencies = dev_priv->wm.spr_latency;
4772
4773         return wm_latency_write(file, ubuf, len, offp, latencies);
4774 }
4775
4776 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4777                                     size_t len, loff_t *offp)
4778 {
4779         struct seq_file *m = file->private_data;
4780         struct drm_i915_private *dev_priv = m->private;
4781         uint16_t *latencies;
4782
4783         if (INTEL_GEN(dev_priv) >= 9)
4784                 latencies = dev_priv->wm.skl_latency;
4785         else
4786                 latencies = dev_priv->wm.cur_latency;
4787
4788         return wm_latency_write(file, ubuf, len, offp, latencies);
4789 }
4790
4791 static const struct file_operations i915_pri_wm_latency_fops = {
4792         .owner = THIS_MODULE,
4793         .open = pri_wm_latency_open,
4794         .read = seq_read,
4795         .llseek = seq_lseek,
4796         .release = single_release,
4797         .write = pri_wm_latency_write
4798 };
4799
4800 static const struct file_operations i915_spr_wm_latency_fops = {
4801         .owner = THIS_MODULE,
4802         .open = spr_wm_latency_open,
4803         .read = seq_read,
4804         .llseek = seq_lseek,
4805         .release = single_release,
4806         .write = spr_wm_latency_write
4807 };
4808
4809 static const struct file_operations i915_cur_wm_latency_fops = {
4810         .owner = THIS_MODULE,
4811         .open = cur_wm_latency_open,
4812         .read = seq_read,
4813         .llseek = seq_lseek,
4814         .release = single_release,
4815         .write = cur_wm_latency_write
4816 };
4817
4818 static int
4819 i915_wedged_get(void *data, u64 *val)
4820 {
4821         struct drm_i915_private *dev_priv = data;
4822
4823         *val = i915_terminally_wedged(&dev_priv->gpu_error);
4824
4825         return 0;
4826 }
4827
4828 static int
4829 i915_wedged_set(void *data, u64 val)
4830 {
4831         struct drm_i915_private *dev_priv = data;
4832
4833         /*
4834          * There is no safeguard against this debugfs entry colliding
4835          * with the hangcheck calling same i915_handle_error() in
4836          * parallel, causing an explosion. For now we assume that the
4837          * test harness is responsible enough not to inject gpu hangs
4838          * while it is writing to 'i915_wedged'
4839          */
4840
4841         if (i915_reset_in_progress(&dev_priv->gpu_error))
4842                 return -EAGAIN;
4843
4844         i915_handle_error(dev_priv, val,
4845                           "Manually setting wedged to %llu", val);
4846
4847         return 0;
4848 }
4849
4850 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4851                         i915_wedged_get, i915_wedged_set,
4852                         "%llu\n");
4853
4854 static int
4855 i915_ring_missed_irq_get(void *data, u64 *val)
4856 {
4857         struct drm_i915_private *dev_priv = data;
4858
4859         *val = dev_priv->gpu_error.missed_irq_rings;
4860         return 0;
4861 }
4862
4863 static int
4864 i915_ring_missed_irq_set(void *data, u64 val)
4865 {
4866         struct drm_i915_private *dev_priv = data;
4867         struct drm_device *dev = &dev_priv->drm;
4868         int ret;
4869
4870         /* Lock against concurrent debugfs callers */
4871         ret = mutex_lock_interruptible(&dev->struct_mutex);
4872         if (ret)
4873                 return ret;
4874         dev_priv->gpu_error.missed_irq_rings = val;
4875         mutex_unlock(&dev->struct_mutex);
4876
4877         return 0;
4878 }
4879
4880 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4881                         i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4882                         "0x%08llx\n");
4883
4884 static int
4885 i915_ring_test_irq_get(void *data, u64 *val)
4886 {
4887         struct drm_i915_private *dev_priv = data;
4888
4889         *val = dev_priv->gpu_error.test_irq_rings;
4890
4891         return 0;
4892 }
4893
4894 static int
4895 i915_ring_test_irq_set(void *data, u64 val)
4896 {
4897         struct drm_i915_private *dev_priv = data;
4898
4899         val &= INTEL_INFO(dev_priv)->ring_mask;
4900         DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4901         dev_priv->gpu_error.test_irq_rings = val;
4902
4903         return 0;
4904 }
4905
4906 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4907                         i915_ring_test_irq_get, i915_ring_test_irq_set,
4908                         "0x%08llx\n");
4909
4910 #define DROP_UNBOUND 0x1
4911 #define DROP_BOUND 0x2
4912 #define DROP_RETIRE 0x4
4913 #define DROP_ACTIVE 0x8
4914 #define DROP_FREED 0x10
4915 #define DROP_ALL (DROP_UNBOUND  | \
4916                   DROP_BOUND    | \
4917                   DROP_RETIRE   | \
4918                   DROP_ACTIVE   | \
4919                   DROP_FREED)
4920 static int
4921 i915_drop_caches_get(void *data, u64 *val)
4922 {
4923         *val = DROP_ALL;
4924
4925         return 0;
4926 }
4927
4928 static int
4929 i915_drop_caches_set(void *data, u64 val)
4930 {
4931         struct drm_i915_private *dev_priv = data;
4932         struct drm_device *dev = &dev_priv->drm;
4933         int ret;
4934
4935         DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4936
4937         /* No need to check and wait for gpu resets, only libdrm auto-restarts
4938          * on ioctls on -EAGAIN. */
4939         ret = mutex_lock_interruptible(&dev->struct_mutex);
4940         if (ret)
4941                 return ret;
4942
4943         if (val & DROP_ACTIVE) {
4944                 ret = i915_gem_wait_for_idle(dev_priv,
4945                                              I915_WAIT_INTERRUPTIBLE |
4946                                              I915_WAIT_LOCKED);
4947                 if (ret)
4948                         goto unlock;
4949         }
4950
4951         if (val & (DROP_RETIRE | DROP_ACTIVE))
4952                 i915_gem_retire_requests(dev_priv);
4953
4954         if (val & DROP_BOUND)
4955                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4956
4957         if (val & DROP_UNBOUND)
4958                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4959
4960 unlock:
4961         mutex_unlock(&dev->struct_mutex);
4962
4963         if (val & DROP_FREED) {
4964                 synchronize_rcu();
4965                 flush_work(&dev_priv->mm.free_work);
4966         }
4967
4968         return ret;
4969 }
4970
4971 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4972                         i915_drop_caches_get, i915_drop_caches_set,
4973                         "0x%08llx\n");
4974
4975 static int
4976 i915_max_freq_get(void *data, u64 *val)
4977 {
4978         struct drm_i915_private *dev_priv = data;
4979
4980         if (INTEL_GEN(dev_priv) < 6)
4981                 return -ENODEV;
4982
4983         *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4984         return 0;
4985 }
4986
4987 static int
4988 i915_max_freq_set(void *data, u64 val)
4989 {
4990         struct drm_i915_private *dev_priv = data;
4991         u32 hw_max, hw_min;
4992         int ret;
4993
4994         if (INTEL_GEN(dev_priv) < 6)
4995                 return -ENODEV;
4996
4997         DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4998
4999         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
5000         if (ret)
5001                 return ret;
5002
5003         /*
5004          * Turbo will still be enabled, but won't go above the set value.
5005          */
5006         val = intel_freq_opcode(dev_priv, val);
5007
5008         hw_max = dev_priv->rps.max_freq;
5009         hw_min = dev_priv->rps.min_freq;
5010
5011         if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
5012                 mutex_unlock(&dev_priv->rps.hw_lock);
5013                 return -EINVAL;
5014         }
5015
5016         dev_priv->rps.max_freq_softlimit = val;
5017
5018         intel_set_rps(dev_priv, val);
5019
5020         mutex_unlock(&dev_priv->rps.hw_lock);
5021
5022         return 0;
5023 }
5024
5025 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
5026                         i915_max_freq_get, i915_max_freq_set,
5027                         "%llu\n");
5028
5029 static int
5030 i915_min_freq_get(void *data, u64 *val)
5031 {
5032         struct drm_i915_private *dev_priv = data;
5033
5034         if (INTEL_GEN(dev_priv) < 6)
5035                 return -ENODEV;
5036
5037         *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
5038         return 0;
5039 }
5040
5041 static int
5042 i915_min_freq_set(void *data, u64 val)
5043 {
5044         struct drm_i915_private *dev_priv = data;
5045         u32 hw_max, hw_min;
5046         int ret;
5047
5048         if (INTEL_GEN(dev_priv) < 6)
5049                 return -ENODEV;
5050
5051         DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
5052
5053         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
5054         if (ret)
5055                 return ret;
5056
5057         /*
5058          * Turbo will still be enabled, but won't go below the set value.
5059          */
5060         val = intel_freq_opcode(dev_priv, val);
5061
5062         hw_max = dev_priv->rps.max_freq;
5063         hw_min = dev_priv->rps.min_freq;
5064
5065         if (val < hw_min ||
5066             val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
5067                 mutex_unlock(&dev_priv->rps.hw_lock);
5068                 return -EINVAL;
5069         }
5070
5071         dev_priv->rps.min_freq_softlimit = val;
5072
5073         intel_set_rps(dev_priv, val);
5074
5075         mutex_unlock(&dev_priv->rps.hw_lock);
5076
5077         return 0;
5078 }
5079
5080 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
5081                         i915_min_freq_get, i915_min_freq_set,
5082                         "%llu\n");
5083
5084 static int
5085 i915_cache_sharing_get(void *data, u64 *val)
5086 {
5087         struct drm_i915_private *dev_priv = data;
5088         u32 snpcr;
5089
5090         if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
5091                 return -ENODEV;
5092
5093         intel_runtime_pm_get(dev_priv);
5094
5095         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5096
5097         intel_runtime_pm_put(dev_priv);
5098
5099         *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
5100
5101         return 0;
5102 }
5103
5104 static int
5105 i915_cache_sharing_set(void *data, u64 val)
5106 {
5107         struct drm_i915_private *dev_priv = data;
5108         u32 snpcr;
5109
5110         if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
5111                 return -ENODEV;
5112
5113         if (val > 3)
5114                 return -EINVAL;
5115
5116         intel_runtime_pm_get(dev_priv);
5117         DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
5118
5119         /* Update the cache sharing policy here as well */
5120         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5121         snpcr &= ~GEN6_MBC_SNPCR_MASK;
5122         snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
5123         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5124
5125         intel_runtime_pm_put(dev_priv);
5126         return 0;
5127 }
5128
5129 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
5130                         i915_cache_sharing_get, i915_cache_sharing_set,
5131                         "%llu\n");
5132
5133 static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
5134                                           struct sseu_dev_info *sseu)
5135 {
5136         int ss_max = 2;
5137         int ss;
5138         u32 sig1[ss_max], sig2[ss_max];
5139
5140         sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
5141         sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
5142         sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
5143         sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
5144
5145         for (ss = 0; ss < ss_max; ss++) {
5146                 unsigned int eu_cnt;
5147
5148                 if (sig1[ss] & CHV_SS_PG_ENABLE)
5149                         /* skip disabled subslice */
5150                         continue;
5151
5152                 sseu->slice_mask = BIT(0);
5153                 sseu->subslice_mask |= BIT(ss);
5154                 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
5155                          ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
5156                          ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
5157                          ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
5158                 sseu->eu_total += eu_cnt;
5159                 sseu->eu_per_subslice = max_t(unsigned int,
5160                                               sseu->eu_per_subslice, eu_cnt);
5161         }
5162 }
5163
5164 static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
5165                                     struct sseu_dev_info *sseu)
5166 {
5167         int s_max = 3, ss_max = 4;
5168         int s, ss;
5169         u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
5170
5171         /* BXT has a single slice and at most 3 subslices. */
5172         if (IS_BROXTON(dev_priv)) {
5173                 s_max = 1;
5174                 ss_max = 3;
5175         }
5176
5177         for (s = 0; s < s_max; s++) {
5178                 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
5179                 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
5180                 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
5181         }
5182
5183         eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
5184                      GEN9_PGCTL_SSA_EU19_ACK |
5185                      GEN9_PGCTL_SSA_EU210_ACK |
5186                      GEN9_PGCTL_SSA_EU311_ACK;
5187         eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
5188                      GEN9_PGCTL_SSB_EU19_ACK |
5189                      GEN9_PGCTL_SSB_EU210_ACK |
5190                      GEN9_PGCTL_SSB_EU311_ACK;
5191
5192         for (s = 0; s < s_max; s++) {
5193                 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
5194                         /* skip disabled slice */
5195                         continue;
5196
5197                 sseu->slice_mask |= BIT(s);
5198
5199                 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
5200                         sseu->subslice_mask =
5201                                 INTEL_INFO(dev_priv)->sseu.subslice_mask;
5202
5203                 for (ss = 0; ss < ss_max; ss++) {
5204                         unsigned int eu_cnt;
5205
5206                         if (IS_BROXTON(dev_priv)) {
5207                                 if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
5208                                         /* skip disabled subslice */
5209                                         continue;
5210
5211                                 sseu->subslice_mask |= BIT(ss);
5212                         }
5213
5214                         eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
5215                                                eu_mask[ss%2]);
5216                         sseu->eu_total += eu_cnt;
5217                         sseu->eu_per_subslice = max_t(unsigned int,
5218                                                       sseu->eu_per_subslice,
5219                                                       eu_cnt);
5220                 }
5221         }
5222 }
5223
5224 static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
5225                                          struct sseu_dev_info *sseu)
5226 {
5227         u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
5228         int s;
5229
5230         sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK;
5231
5232         if (sseu->slice_mask) {
5233                 sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask;
5234                 sseu->eu_per_subslice =
5235                                 INTEL_INFO(dev_priv)->sseu.eu_per_subslice;
5236                 sseu->eu_total = sseu->eu_per_subslice *
5237                                  sseu_subslice_total(sseu);
5238
5239                 /* subtract fused off EU(s) from enabled slice(s) */
5240                 for (s = 0; s < fls(sseu->slice_mask); s++) {
5241                         u8 subslice_7eu =
5242                                 INTEL_INFO(dev_priv)->sseu.subslice_7eu[s];
5243
5244                         sseu->eu_total -= hweight8(subslice_7eu);
5245                 }
5246         }
5247 }
5248
5249 static void i915_print_sseu_info(struct seq_file *m, bool is_available_info,
5250                                  const struct sseu_dev_info *sseu)
5251 {
5252         struct drm_i915_private *dev_priv = node_to_i915(m->private);
5253         const char *type = is_available_info ? "Available" : "Enabled";
5254
5255         seq_printf(m, "  %s Slice Mask: %04x\n", type,
5256                    sseu->slice_mask);
5257         seq_printf(m, "  %s Slice Total: %u\n", type,
5258                    hweight8(sseu->slice_mask));
5259         seq_printf(m, "  %s Subslice Total: %u\n", type,
5260                    sseu_subslice_total(sseu));
5261         seq_printf(m, "  %s Subslice Mask: %04x\n", type,
5262                    sseu->subslice_mask);
5263         seq_printf(m, "  %s Subslice Per Slice: %u\n", type,
5264                    hweight8(sseu->subslice_mask));
5265         seq_printf(m, "  %s EU Total: %u\n", type,
5266                    sseu->eu_total);
5267         seq_printf(m, "  %s EU Per Subslice: %u\n", type,
5268                    sseu->eu_per_subslice);
5269
5270         if (!is_available_info)
5271                 return;
5272
5273         seq_printf(m, "  Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv)));
5274         if (HAS_POOLED_EU(dev_priv))
5275                 seq_printf(m, "  Min EU in pool: %u\n", sseu->min_eu_in_pool);
5276
5277         seq_printf(m, "  Has Slice Power Gating: %s\n",
5278                    yesno(sseu->has_slice_pg));
5279         seq_printf(m, "  Has Subslice Power Gating: %s\n",
5280                    yesno(sseu->has_subslice_pg));
5281         seq_printf(m, "  Has EU Power Gating: %s\n",
5282                    yesno(sseu->has_eu_pg));
5283 }
5284
5285 static int i915_sseu_status(struct seq_file *m, void *unused)
5286 {
5287         struct drm_i915_private *dev_priv = node_to_i915(m->private);
5288         struct sseu_dev_info sseu;
5289
5290         if (INTEL_GEN(dev_priv) < 8)
5291                 return -ENODEV;
5292
5293         seq_puts(m, "SSEU Device Info\n");
5294         i915_print_sseu_info(m, true, &INTEL_INFO(dev_priv)->sseu);
5295
5296         seq_puts(m, "SSEU Device Status\n");
5297         memset(&sseu, 0, sizeof(sseu));
5298
5299         intel_runtime_pm_get(dev_priv);
5300
5301         if (IS_CHERRYVIEW(dev_priv)) {
5302                 cherryview_sseu_device_status(dev_priv, &sseu);
5303         } else if (IS_BROADWELL(dev_priv)) {
5304                 broadwell_sseu_device_status(dev_priv, &sseu);
5305         } else if (INTEL_GEN(dev_priv) >= 9) {
5306                 gen9_sseu_device_status(dev_priv, &sseu);
5307         }
5308
5309         intel_runtime_pm_put(dev_priv);
5310
5311         i915_print_sseu_info(m, false, &sseu);
5312
5313         return 0;
5314 }
5315
5316 static int i915_forcewake_open(struct inode *inode, struct file *file)
5317 {
5318         struct drm_i915_private *dev_priv = inode->i_private;
5319
5320         if (INTEL_GEN(dev_priv) < 6)
5321                 return 0;
5322
5323         intel_runtime_pm_get(dev_priv);
5324         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5325
5326         return 0;
5327 }
5328
5329 static int i915_forcewake_release(struct inode *inode, struct file *file)
5330 {
5331         struct drm_i915_private *dev_priv = inode->i_private;
5332
5333         if (INTEL_GEN(dev_priv) < 6)
5334                 return 0;
5335
5336         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5337         intel_runtime_pm_put(dev_priv);
5338
5339         return 0;
5340 }
5341
5342 static const struct file_operations i915_forcewake_fops = {
5343         .owner = THIS_MODULE,
5344         .open = i915_forcewake_open,
5345         .release = i915_forcewake_release,
5346 };
5347
5348 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5349 {
5350         struct dentry *ent;
5351
5352         ent = debugfs_create_file("i915_forcewake_user",
5353                                   S_IRUSR,
5354                                   root, to_i915(minor->dev),
5355                                   &i915_forcewake_fops);
5356         if (!ent)
5357                 return -ENOMEM;
5358
5359         return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
5360 }
5361
5362 static int i915_debugfs_create(struct dentry *root,
5363                                struct drm_minor *minor,
5364                                const char *name,
5365                                const struct file_operations *fops)
5366 {
5367         struct dentry *ent;
5368
5369         ent = debugfs_create_file(name,
5370                                   S_IRUGO | S_IWUSR,
5371                                   root, to_i915(minor->dev),
5372                                   fops);
5373         if (!ent)
5374                 return -ENOMEM;
5375
5376         return drm_add_fake_info_node(minor, ent, fops);
5377 }
5378
5379 static const struct drm_info_list i915_debugfs_list[] = {
5380         {"i915_capabilities", i915_capabilities, 0},
5381         {"i915_gem_objects", i915_gem_object_info, 0},
5382         {"i915_gem_gtt", i915_gem_gtt_info, 0},
5383         {"i915_gem_pin_display", i915_gem_gtt_info, 0, (void *)1},
5384         {"i915_gem_stolen", i915_gem_stolen_list_info },
5385         {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
5386         {"i915_gem_request", i915_gem_request_info, 0},
5387         {"i915_gem_seqno", i915_gem_seqno_info, 0},
5388         {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
5389         {"i915_gem_interrupt", i915_interrupt_info, 0},
5390         {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
5391         {"i915_guc_info", i915_guc_info, 0},
5392         {"i915_guc_load_status", i915_guc_load_status_info, 0},
5393         {"i915_guc_log_dump", i915_guc_log_dump, 0},
5394         {"i915_frequency_info", i915_frequency_info, 0},
5395         {"i915_hangcheck_info", i915_hangcheck_info, 0},
5396         {"i915_drpc_info", i915_drpc_info, 0},
5397         {"i915_emon_status", i915_emon_status, 0},
5398         {"i915_ring_freq_table", i915_ring_freq_table, 0},
5399         {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
5400         {"i915_fbc_status", i915_fbc_status, 0},
5401         {"i915_ips_status", i915_ips_status, 0},
5402         {"i915_sr_status", i915_sr_status, 0},
5403         {"i915_opregion", i915_opregion, 0},
5404         {"i915_vbt", i915_vbt, 0},
5405         {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
5406         {"i915_context_status", i915_context_status, 0},
5407         {"i915_dump_lrc", i915_dump_lrc, 0},
5408         {"i915_forcewake_domains", i915_forcewake_domains, 0},
5409         {"i915_swizzle_info", i915_swizzle_info, 0},
5410         {"i915_ppgtt_info", i915_ppgtt_info, 0},
5411         {"i915_llc", i915_llc, 0},
5412         {"i915_edp_psr_status", i915_edp_psr_status, 0},
5413         {"i915_sink_crc_eDP1", i915_sink_crc, 0},
5414         {"i915_energy_uJ", i915_energy_uJ, 0},
5415         {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
5416         {"i915_power_domain_info", i915_power_domain_info, 0},
5417         {"i915_dmc_info", i915_dmc_info, 0},
5418         {"i915_display_info", i915_display_info, 0},
5419         {"i915_engine_info", i915_engine_info, 0},
5420         {"i915_semaphore_status", i915_semaphore_status, 0},
5421         {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
5422         {"i915_dp_mst_info", i915_dp_mst_info, 0},
5423         {"i915_wa_registers", i915_wa_registers, 0},
5424         {"i915_ddb_info", i915_ddb_info, 0},
5425         {"i915_sseu_status", i915_sseu_status, 0},
5426         {"i915_drrs_status", i915_drrs_status, 0},
5427         {"i915_rps_boost_info", i915_rps_boost_info, 0},
5428 };
5429 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5430
5431 static const struct i915_debugfs_files {
5432         const char *name;
5433         const struct file_operations *fops;
5434 } i915_debugfs_files[] = {
5435         {"i915_wedged", &i915_wedged_fops},
5436         {"i915_max_freq", &i915_max_freq_fops},
5437         {"i915_min_freq", &i915_min_freq_fops},
5438         {"i915_cache_sharing", &i915_cache_sharing_fops},
5439         {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5440         {"i915_ring_test_irq", &i915_ring_test_irq_fops},
5441         {"i915_gem_drop_caches", &i915_drop_caches_fops},
5442 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
5443         {"i915_error_state", &i915_error_state_fops},
5444 #endif
5445         {"i915_next_seqno", &i915_next_seqno_fops},
5446         {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
5447         {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5448         {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5449         {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
5450         {"i915_fbc_false_color", &i915_fbc_fc_fops},
5451         {"i915_dp_test_data", &i915_displayport_test_data_fops},
5452         {"i915_dp_test_type", &i915_displayport_test_type_fops},
5453         {"i915_dp_test_active", &i915_displayport_test_active_fops},
5454         {"i915_guc_log_control", &i915_guc_log_control_fops}
5455 };
5456
5457 void intel_display_crc_init(struct drm_i915_private *dev_priv)
5458 {
5459         enum pipe pipe;
5460
5461         for_each_pipe(dev_priv, pipe) {
5462                 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
5463
5464                 pipe_crc->opened = false;
5465                 spin_lock_init(&pipe_crc->lock);
5466                 init_waitqueue_head(&pipe_crc->wq);
5467         }
5468 }
5469
5470 int i915_debugfs_register(struct drm_i915_private *dev_priv)
5471 {
5472         struct drm_minor *minor = dev_priv->drm.primary;
5473         int ret, i;
5474
5475         ret = i915_forcewake_create(minor->debugfs_root, minor);
5476         if (ret)
5477                 return ret;
5478
5479         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5480                 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5481                 if (ret)
5482                         return ret;
5483         }
5484
5485         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5486                 ret = i915_debugfs_create(minor->debugfs_root, minor,
5487                                           i915_debugfs_files[i].name,
5488                                           i915_debugfs_files[i].fops);
5489                 if (ret)
5490                         return ret;
5491         }
5492
5493         return drm_debugfs_create_files(i915_debugfs_list,
5494                                         I915_DEBUGFS_ENTRIES,
5495                                         minor->debugfs_root, minor);
5496 }
5497
5498 void i915_debugfs_unregister(struct drm_i915_private *dev_priv)
5499 {
5500         struct drm_minor *minor = dev_priv->drm.primary;
5501         int i;
5502
5503         drm_debugfs_remove_files(i915_debugfs_list,
5504                                  I915_DEBUGFS_ENTRIES, minor);
5505
5506         drm_debugfs_remove_files((struct drm_info_list *)&i915_forcewake_fops,
5507                                  1, minor);
5508
5509         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5510                 struct drm_info_list *info_list =
5511                         (struct drm_info_list *)&i915_pipe_crc_data[i];
5512
5513                 drm_debugfs_remove_files(info_list, 1, minor);
5514         }
5515
5516         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5517                 struct drm_info_list *info_list =
5518                         (struct drm_info_list *)i915_debugfs_files[i].fops;
5519
5520                 drm_debugfs_remove_files(info_list, 1, minor);
5521         }
5522 }
5523
5524 struct dpcd_block {
5525         /* DPCD dump start address. */
5526         unsigned int offset;
5527         /* DPCD dump end address, inclusive. If unset, .size will be used. */
5528         unsigned int end;
5529         /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5530         size_t size;
5531         /* Only valid for eDP. */
5532         bool edp;
5533 };
5534
5535 static const struct dpcd_block i915_dpcd_debug[] = {
5536         { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5537         { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5538         { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5539         { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5540         { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5541         { .offset = DP_SET_POWER },
5542         { .offset = DP_EDP_DPCD_REV },
5543         { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5544         { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5545         { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5546 };
5547
5548 static int i915_dpcd_show(struct seq_file *m, void *data)
5549 {
5550         struct drm_connector *connector = m->private;
5551         struct intel_dp *intel_dp =
5552                 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5553         uint8_t buf[16];
5554         ssize_t err;
5555         int i;
5556
5557         if (connector->status != connector_status_connected)
5558                 return -ENODEV;
5559
5560         for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5561                 const struct dpcd_block *b = &i915_dpcd_debug[i];
5562                 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5563
5564                 if (b->edp &&
5565                     connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5566                         continue;
5567
5568                 /* low tech for now */
5569                 if (WARN_ON(size > sizeof(buf)))
5570                         continue;
5571
5572                 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5573                 if (err <= 0) {
5574                         DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5575                                   size, b->offset, err);
5576                         continue;
5577                 }
5578
5579                 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
5580         }
5581
5582         return 0;
5583 }
5584
5585 static int i915_dpcd_open(struct inode *inode, struct file *file)
5586 {
5587         return single_open(file, i915_dpcd_show, inode->i_private);
5588 }
5589
5590 static const struct file_operations i915_dpcd_fops = {
5591         .owner = THIS_MODULE,
5592         .open = i915_dpcd_open,
5593         .read = seq_read,
5594         .llseek = seq_lseek,
5595         .release = single_release,
5596 };
5597
5598 static int i915_panel_show(struct seq_file *m, void *data)
5599 {
5600         struct drm_connector *connector = m->private;
5601         struct intel_dp *intel_dp =
5602                 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5603
5604         if (connector->status != connector_status_connected)
5605                 return -ENODEV;
5606
5607         seq_printf(m, "Panel power up delay: %d\n",
5608                    intel_dp->panel_power_up_delay);
5609         seq_printf(m, "Panel power down delay: %d\n",
5610                    intel_dp->panel_power_down_delay);
5611         seq_printf(m, "Backlight on delay: %d\n",
5612                    intel_dp->backlight_on_delay);
5613         seq_printf(m, "Backlight off delay: %d\n",
5614                    intel_dp->backlight_off_delay);
5615
5616         return 0;
5617 }
5618
5619 static int i915_panel_open(struct inode *inode, struct file *file)
5620 {
5621         return single_open(file, i915_panel_show, inode->i_private);
5622 }
5623
5624 static const struct file_operations i915_panel_fops = {
5625         .owner = THIS_MODULE,
5626         .open = i915_panel_open,
5627         .read = seq_read,
5628         .llseek = seq_lseek,
5629         .release = single_release,
5630 };
5631
5632 /**
5633  * i915_debugfs_connector_add - add i915 specific connector debugfs files
5634  * @connector: pointer to a registered drm_connector
5635  *
5636  * Cleanup will be done by drm_connector_unregister() through a call to
5637  * drm_debugfs_connector_remove().
5638  *
5639  * Returns 0 on success, negative error codes on error.
5640  */
5641 int i915_debugfs_connector_add(struct drm_connector *connector)
5642 {
5643         struct dentry *root = connector->debugfs_entry;
5644
5645         /* The connector must have been registered beforehands. */
5646         if (!root)
5647                 return -ENODEV;
5648
5649         if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5650             connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5651                 debugfs_create_file("i915_dpcd", S_IRUGO, root,
5652                                     connector, &i915_dpcd_fops);
5653
5654         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5655                 debugfs_create_file("i915_panel_timings", S_IRUGO, root,
5656                                     connector, &i915_panel_fops);
5657
5658         return 0;
5659 }