drivers/gpu/drm/i915/i915_debugfs.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *
  27  */
  28
  29 #include <linux/seq_file.h>
  30 #include <linux/circ_buf.h>
  31 #include <linux/ctype.h>
  32 #include <linux/debugfs.h>
  33 #include <linux/slab.h>
  34 #include <linux/export.h>
  35 #include <linux/list_sort.h>
  36 #include <asm/msr-index.h>
  37 #include <drm/drmP.h>
  38 #include "intel_drv.h"
  39 #include "intel_ringbuffer.h"
  40 #include <drm/i915_drm.h>
  41 #include "i915_drv.h"
  42
  43 enum {
  44         ACTIVE_LIST,
  45         INACTIVE_LIST,
  46         PINNED_LIST,
  47 };
  48
  49 static const char *yesno(int v)
  50 {
  51         return v ? "yes" : "no";
  52 }
  53
  54 /* As the drm_debugfs_init() routines are called before dev->dev_private is
  55  * allocated we need to hook into the minor for release. */
  56 static int
  57 drm_add_fake_info_node(struct drm_minor *minor,
  58                        struct dentry *ent,
  59                        const void *key)
  60 {
  61         struct drm_info_node *node;
  62
  63         node = kmalloc(sizeof(*node), GFP_KERNEL);
  64         if (node == NULL) {
  65                 debugfs_remove(ent);
  66                 return -ENOMEM;
  67         }
  68
  69         node->minor = minor;
  70         node->dent = ent;
  71         node->info_ent = (void *) key;
  72
  73         mutex_lock(&minor->debugfs_lock);
  74         list_add(&node->list, &minor->debugfs_list);
  75         mutex_unlock(&minor->debugfs_lock);
  76
  77         return 0;
  78 }
  79
  80 static int i915_capabilities(struct seq_file *m, void *data)
  81 {
  82         struct drm_info_node *node = (struct drm_info_node *) m->private;
  83         struct drm_device *dev = node->minor->dev;
  84         const struct intel_device_info *info = INTEL_INFO(dev);
  85
  86         seq_printf(m, "gen: %d\n", info->gen);
  87         seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
  88 #define PRINT_FLAG(x)  seq_printf(m, #x ": %s\n", yesno(info->x))
  89 #define SEP_SEMICOLON ;
  90         DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
  91 #undef PRINT_FLAG
  92 #undef SEP_SEMICOLON
  93
  94         return 0;
  95 }
  96
  97 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
  98 {
  99         if (obj->user_pin_count > 0)
 100                 return "P";
 101         else if (i915_gem_obj_is_pinned(obj))
 102                 return "p";
 103         else
 104                 return " ";
 105 }
 106
 107 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
 108 {
 109         switch (obj->tiling_mode) {
 110         default:
 111         case I915_TILING_NONE: return " ";
 112         case I915_TILING_X: return "X";
 113         case I915_TILING_Y: return "Y";
 114         }
 115 }
 116
 117 static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
 118 {
 119         return obj->has_global_gtt_mapping ? "g" : " ";
 120 }
 121
 122 static void
 123 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
 124 {
 125         struct i915_vma *vma;
 126         int pin_count = 0;
 127
 128         seq_printf(m, "%pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%s",
 129                    &obj->base,
 130                    get_pin_flag(obj),
 131                    get_tiling_flag(obj),
 132                    get_global_flag(obj),
 133                    obj->base.size / 1024,
 134                    obj->base.read_domains,
 135                    obj->base.write_domain,
 136                    obj->last_read_seqno,
 137                    obj->last_write_seqno,
 138                    obj->last_fenced_seqno,
 139                    i915_cache_level_str(obj->cache_level),
 140                    obj->dirty ? " dirty" : "",
 141                    obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
 142         if (obj->base.name)
 143                 seq_printf(m, " (name: %d)", obj->base.name);
 144         list_for_each_entry(vma, &obj->vma_list, vma_link)
 145                 if (vma->pin_count > 0)
 146                         pin_count++;
 147                 seq_printf(m, " (pinned x %d)", pin_count);
 148         if (obj->pin_display)
 149                 seq_printf(m, " (display)");
 150         if (obj->fence_reg != I915_FENCE_REG_NONE)
 151                 seq_printf(m, " (fence: %d)", obj->fence_reg);
 152         list_for_each_entry(vma, &obj->vma_list, vma_link) {
 153                 if (!i915_is_ggtt(vma->vm))
 154                         seq_puts(m, " (pp");
 155                 else
 156                         seq_puts(m, " (g");
 157                 seq_printf(m, "gtt offset: %08lx, size: %08lx)",
 158                            vma->node.start, vma->node.size);
 159         }
 160         if (obj->stolen)
 161                 seq_printf(m, " (stolen: %08lx)", obj->stolen->start);
 162         if (obj->pin_mappable || obj->fault_mappable) {
 163                 char s[3], *t = s;
 164                 if (obj->pin_mappable)
 165                         *t++ = 'p';
 166                 if (obj->fault_mappable)
 167                         *t++ = 'f';
 168                 *t = '\0';
 169                 seq_printf(m, " (%s mappable)", s);
 170         }
 171         if (obj->ring != NULL)
 172                 seq_printf(m, " (%s)", obj->ring->name);
 173 }
 174
 175 static void describe_ctx(struct seq_file *m, struct i915_hw_context *ctx)
 176 {
 177         seq_putc(m, ctx->is_initialized ? 'I' : 'i');
 178         seq_putc(m, ctx->remap_slice ? 'R' : 'r');
 179         seq_putc(m, ' ');
 180 }
 181
 182 static int i915_gem_object_list_info(struct seq_file *m, void *data)
 183 {
 184         struct drm_info_node *node = (struct drm_info_node *) m->private;
 185         uintptr_t list = (uintptr_t) node->info_ent->data;
 186         struct list_head *head;
 187         struct drm_device *dev = node->minor->dev;
 188         struct drm_i915_private *dev_priv = dev->dev_private;
 189         struct i915_address_space *vm = &dev_priv->gtt.base;
 190         struct i915_vma *vma;
 191         size_t total_obj_size, total_gtt_size;
 192         int count, ret;
 193
 194         ret = mutex_lock_interruptible(&dev->struct_mutex);
 195         if (ret)
 196                 return ret;
 197
 198         /* FIXME: the user of this interface might want more than just GGTT */
 199         switch (list) {
 200         case ACTIVE_LIST:
 201                 seq_puts(m, "Active:\n");
 202                 head = &vm->active_list;
 203                 break;
 204         case INACTIVE_LIST:
 205                 seq_puts(m, "Inactive:\n");
 206                 head = &vm->inactive_list;
 207                 break;
 208         default:
 209                 mutex_unlock(&dev->struct_mutex);
 210                 return -EINVAL;
 211         }
 212
 213         total_obj_size = total_gtt_size = count = 0;
 214         list_for_each_entry(vma, head, mm_list) {
 215                 seq_printf(m, "   ");
 216                 describe_obj(m, vma->obj);
 217                 seq_printf(m, "\n");
 218                 total_obj_size += vma->obj->base.size;
 219                 total_gtt_size += vma->node.size;
 220                 count++;
 221         }
 222         mutex_unlock(&dev->struct_mutex);
 223
 224         seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
 225                    count, total_obj_size, total_gtt_size);
 226         return 0;
 227 }
 228
 229 static int obj_rank_by_stolen(void *priv,
 230                               struct list_head *A, struct list_head *B)
 231 {
 232         struct drm_i915_gem_object *a =
 233                 container_of(A, struct drm_i915_gem_object, obj_exec_link);
 234         struct drm_i915_gem_object *b =
 235                 container_of(B, struct drm_i915_gem_object, obj_exec_link);
 236
 237         return a->stolen->start - b->stolen->start;
 238 }
 239
 240 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
 241 {
 242         struct drm_info_node *node = (struct drm_info_node *) m->private;
 243         struct drm_device *dev = node->minor->dev;
 244         struct drm_i915_private *dev_priv = dev->dev_private;
 245         struct drm_i915_gem_object *obj;
 246         size_t total_obj_size, total_gtt_size;
 247         LIST_HEAD(stolen);
 248         int count, ret;
 249
 250         ret = mutex_lock_interruptible(&dev->struct_mutex);
 251         if (ret)
 252                 return ret;
 253
 254         total_obj_size = total_gtt_size = count = 0;
 255         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 256                 if (obj->stolen == NULL)
 257                         continue;
 258
 259                 list_add(&obj->obj_exec_link, &stolen);
 260
 261                 total_obj_size += obj->base.size;
 262                 total_gtt_size += i915_gem_obj_ggtt_size(obj);
 263                 count++;
 264         }
 265         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 266                 if (obj->stolen == NULL)
 267                         continue;
 268
 269                 list_add(&obj->obj_exec_link, &stolen);
 270
 271                 total_obj_size += obj->base.size;
 272                 count++;
 273         }
 274         list_sort(NULL, &stolen, obj_rank_by_stolen);
 275         seq_puts(m, "Stolen:\n");
 276         while (!list_empty(&stolen)) {
 277                 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
 278                 seq_puts(m, "   ");
 279                 describe_obj(m, obj);
 280                 seq_putc(m, '\n');
 281                 list_del_init(&obj->obj_exec_link);
 282         }
 283         mutex_unlock(&dev->struct_mutex);
 284
 285         seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
 286                    count, total_obj_size, total_gtt_size);
 287         return 0;
 288 }
 289
 290 #define count_objects(list, member) do { \
 291         list_for_each_entry(obj, list, member) { \
 292                 size += i915_gem_obj_ggtt_size(obj); \
 293                 ++count; \
 294                 if (obj->map_and_fenceable) { \
 295                         mappable_size += i915_gem_obj_ggtt_size(obj); \
 296                         ++mappable_count; \
 297                 } \
 298         } \
 299 } while (0)
 300
 301 struct file_stats {
 302         int count;
 303         size_t total, active, inactive, unbound;
 304 };
 305
 306 static int per_file_stats(int id, void *ptr, void *data)
 307 {
 308         struct drm_i915_gem_object *obj = ptr;
 309         struct file_stats *stats = data;
 310
 311         stats->count++;
 312         stats->total += obj->base.size;
 313
 314         if (i915_gem_obj_ggtt_bound(obj)) {
 315                 if (!list_empty(&obj->ring_list))
 316                         stats->active += obj->base.size;
 317                 else
 318                         stats->inactive += obj->base.size;
 319         } else {
 320                 if (!list_empty(&obj->global_list))
 321                         stats->unbound += obj->base.size;
 322         }
 323
 324         return 0;
 325 }
 326
 327 #define count_vmas(list, member) do { \
 328         list_for_each_entry(vma, list, member) { \
 329                 size += i915_gem_obj_ggtt_size(vma->obj); \
 330                 ++count; \
 331                 if (vma->obj->map_and_fenceable) { \
 332                         mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
 333                         ++mappable_count; \
 334                 } \
 335         } \
 336 } while (0)
 337
 338 static int i915_gem_object_info(struct seq_file *m, void* data)
 339 {
 340         struct drm_info_node *node = (struct drm_info_node *) m->private;
 341         struct drm_device *dev = node->minor->dev;
 342         struct drm_i915_private *dev_priv = dev->dev_private;
 343         u32 count, mappable_count, purgeable_count;
 344         size_t size, mappable_size, purgeable_size;
 345         struct drm_i915_gem_object *obj;
 346         struct i915_address_space *vm = &dev_priv->gtt.base;
 347         struct drm_file *file;
 348         struct i915_vma *vma;
 349         int ret;
 350
 351         ret = mutex_lock_interruptible(&dev->struct_mutex);
 352         if (ret)
 353                 return ret;
 354
 355         seq_printf(m, "%u objects, %zu bytes\n",
 356                    dev_priv->mm.object_count,
 357                    dev_priv->mm.object_memory);
 358
 359         size = count = mappable_size = mappable_count = 0;
 360         count_objects(&dev_priv->mm.bound_list, global_list);
 361         seq_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
 362                    count, mappable_count, size, mappable_size);
 363
 364         size = count = mappable_size = mappable_count = 0;
 365         count_vmas(&vm->active_list, mm_list);
 366         seq_printf(m, "  %u [%u] active objects, %zu [%zu] bytes\n",
 367                    count, mappable_count, size, mappable_size);
 368
 369         size = count = mappable_size = mappable_count = 0;
 370         count_vmas(&vm->inactive_list, mm_list);
 371         seq_printf(m, "  %u [%u] inactive objects, %zu [%zu] bytes\n",
 372                    count, mappable_count, size, mappable_size);
 373
 374         size = count = purgeable_size = purgeable_count = 0;
 375         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 376                 size += obj->base.size, ++count;
 377                 if (obj->madv == I915_MADV_DONTNEED)
 378                         purgeable_size += obj->base.size, ++purgeable_count;
 379         }
 380         seq_printf(m, "%u unbound objects, %zu bytes\n", count, size);
 381
 382         size = count = mappable_size = mappable_count = 0;
 383         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 384                 if (obj->fault_mappable) {
 385                         size += i915_gem_obj_ggtt_size(obj);
 386                         ++count;
 387                 }
 388                 if (obj->pin_mappable) {
 389                         mappable_size += i915_gem_obj_ggtt_size(obj);
 390                         ++mappable_count;
 391                 }
 392                 if (obj->madv == I915_MADV_DONTNEED) {
 393                         purgeable_size += obj->base.size;
 394                         ++purgeable_count;
 395                 }
 396         }
 397         seq_printf(m, "%u purgeable objects, %zu bytes\n",
 398                    purgeable_count, purgeable_size);
 399         seq_printf(m, "%u pinned mappable objects, %zu bytes\n",
 400                    mappable_count, mappable_size);
 401         seq_printf(m, "%u fault mappable objects, %zu bytes\n",
 402                    count, size);
 403
 404         seq_printf(m, "%zu [%lu] gtt total\n",
 405                    dev_priv->gtt.base.total,
 406                    dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
 407
 408         seq_putc(m, '\n');
 409         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
 410                 struct file_stats stats;
 411                 struct task_struct *task;
 412
 413                 memset(&stats, 0, sizeof(stats));
 414                 idr_for_each(&file->object_idr, per_file_stats, &stats);
 415                 /*
 416                  * Although we have a valid reference on file->pid, that does
 417                  * not guarantee that the task_struct who called get_pid() is
 418                  * still alive (e.g. get_pid(current) => fork() => exit()).
 419                  * Therefore, we need to protect this ->comm access using RCU.
 420                  */
 421                 rcu_read_lock();
 422                 task = pid_task(file->pid, PIDTYPE_PID);
 423                 seq_printf(m, "%s: %u objects, %zu bytes (%zu active, %zu inactive, %zu unbound)\n",
 424                            task ? task->comm : "<unknown>",
 425                            stats.count,
 426                            stats.total,
 427                            stats.active,
 428                            stats.inactive,
 429                            stats.unbound);
 430                 rcu_read_unlock();
 431         }
 432
 433         mutex_unlock(&dev->struct_mutex);
 434
 435         return 0;
 436 }
 437
 438 static int i915_gem_gtt_info(struct seq_file *m, void *data)
 439 {
 440         struct drm_info_node *node = (struct drm_info_node *) m->private;
 441         struct drm_device *dev = node->minor->dev;
 442         uintptr_t list = (uintptr_t) node->info_ent->data;
 443         struct drm_i915_private *dev_priv = dev->dev_private;
 444         struct drm_i915_gem_object *obj;
 445         size_t total_obj_size, total_gtt_size;
 446         int count, ret;
 447
 448         ret = mutex_lock_interruptible(&dev->struct_mutex);
 449         if (ret)
 450                 return ret;
 451
 452         total_obj_size = total_gtt_size = count = 0;
 453         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 454                 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
 455                         continue;
 456
 457                 seq_puts(m, "   ");
 458                 describe_obj(m, obj);
 459                 seq_putc(m, '\n');
 460                 total_obj_size += obj->base.size;
 461                 total_gtt_size += i915_gem_obj_ggtt_size(obj);
 462                 count++;
 463         }
 464
 465         mutex_unlock(&dev->struct_mutex);
 466
 467         seq_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
 468                    count, total_obj_size, total_gtt_size);
 469
 470         return 0;
 471 }
 472
 473 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
 474 {
 475         struct drm_info_node *node = (struct drm_info_node *) m->private;
 476         struct drm_device *dev = node->minor->dev;
 477         unsigned long flags;
 478         struct intel_crtc *crtc;
 479
 480         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
 481                 const char pipe = pipe_name(crtc->pipe);
 482                 const char plane = plane_name(crtc->plane);
 483                 struct intel_unpin_work *work;
 484
 485                 spin_lock_irqsave(&dev->event_lock, flags);
 486                 work = crtc->unpin_work;
 487                 if (work == NULL) {
 488                         seq_printf(m, "No flip due on pipe %c (plane %c)\n",
 489                                    pipe, plane);
 490                 } else {
 491                         if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
 492                                 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
 493                                            pipe, plane);
 494                         } else {
 495                                 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
 496                                            pipe, plane);
 497                         }
 498                         if (work->enable_stall_check)
 499                                 seq_puts(m, "Stall check enabled, ");
 500                         else
 501                                 seq_puts(m, "Stall check waiting for page flip ioctl, ");
 502                         seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
 503
 504                         if (work->old_fb_obj) {
 505                                 struct drm_i915_gem_object *obj = work->old_fb_obj;
 506                                 if (obj)
 507                                         seq_printf(m, "Old framebuffer gtt_offset 0x%08lx\n",
 508                                                    i915_gem_obj_ggtt_offset(obj));
 509                         }
 510                         if (work->pending_flip_obj) {
 511                                 struct drm_i915_gem_object *obj = work->pending_flip_obj;
 512                                 if (obj)
 513                                         seq_printf(m, "New framebuffer gtt_offset 0x%08lx\n",
 514                                                    i915_gem_obj_ggtt_offset(obj));
 515                         }
 516                 }
 517                 spin_unlock_irqrestore(&dev->event_lock, flags);
 518         }
 519
 520         return 0;
 521 }
 522
 523 static int i915_gem_request_info(struct seq_file *m, void *data)
 524 {
 525         struct drm_info_node *node = (struct drm_info_node *) m->private;
 526         struct drm_device *dev = node->minor->dev;
 527         drm_i915_private_t *dev_priv = dev->dev_private;
 528         struct intel_ring_buffer *ring;
 529         struct drm_i915_gem_request *gem_request;
 530         int ret, count, i;
 531
 532         ret = mutex_lock_interruptible(&dev->struct_mutex);
 533         if (ret)
 534                 return ret;
 535
 536         count = 0;
 537         for_each_ring(ring, dev_priv, i) {
 538                 if (list_empty(&ring->request_list))
 539                         continue;
 540
 541                 seq_printf(m, "%s requests:\n", ring->name);
 542                 list_for_each_entry(gem_request,
 543                                     &ring->request_list,
 544                                     list) {
 545                         seq_printf(m, "    %d @ %d\n",
 546                                    gem_request->seqno,
 547                                    (int) (jiffies - gem_request->emitted_jiffies));
 548                 }
 549                 count++;
 550         }
 551         mutex_unlock(&dev->struct_mutex);
 552
 553         if (count == 0)
 554                 seq_puts(m, "No requests\n");
 555
 556         return 0;
 557 }
 558
 559 static void i915_ring_seqno_info(struct seq_file *m,
 560                                  struct intel_ring_buffer *ring)
 561 {
 562         if (ring->get_seqno) {
 563                 seq_printf(m, "Current sequence (%s): %u\n",
 564                            ring->name, ring->get_seqno(ring, false));
 565         }
 566 }
 567
 568 static int i915_gem_seqno_info(struct seq_file *m, void *data)
 569 {
 570         struct drm_info_node *node = (struct drm_info_node *) m->private;
 571         struct drm_device *dev = node->minor->dev;
 572         drm_i915_private_t *dev_priv = dev->dev_private;
 573         struct intel_ring_buffer *ring;
 574         int ret, i;
 575
 576         ret = mutex_lock_interruptible(&dev->struct_mutex);
 577         if (ret)
 578                 return ret;
 579         intel_runtime_pm_get(dev_priv);
 580
 581         for_each_ring(ring, dev_priv, i)
 582                 i915_ring_seqno_info(m, ring);
 583
 584         intel_runtime_pm_put(dev_priv);
 585         mutex_unlock(&dev->struct_mutex);
 586
 587         return 0;
 588 }
 589
 590
 591 static int i915_interrupt_info(struct seq_file *m, void *data)
 592 {
 593         struct drm_info_node *node = (struct drm_info_node *) m->private;
 594         struct drm_device *dev = node->minor->dev;
 595         drm_i915_private_t *dev_priv = dev->dev_private;
 596         struct intel_ring_buffer *ring;
 597         int ret, i, pipe;
 598
 599         ret = mutex_lock_interruptible(&dev->struct_mutex);
 600         if (ret)
 601                 return ret;
 602         intel_runtime_pm_get(dev_priv);
 603
 604         if (INTEL_INFO(dev)->gen >= 8) {
 605                 int i;
 606                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 607                            I915_READ(GEN8_MASTER_IRQ));
 608
 609                 for (i = 0; i < 4; i++) {
 610                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 611                                    i, I915_READ(GEN8_GT_IMR(i)));
 612                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 613                                    i, I915_READ(GEN8_GT_IIR(i)));
 614                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 615                                    i, I915_READ(GEN8_GT_IER(i)));
 616                 }
 617
 618                 for_each_pipe(i) {
 619                         seq_printf(m, "Pipe %c IMR:\t%08x\n",
 620                                    pipe_name(i),
 621                                    I915_READ(GEN8_DE_PIPE_IMR(i)));
 622                         seq_printf(m, "Pipe %c IIR:\t%08x\n",
 623                                    pipe_name(i),
 624                                    I915_READ(GEN8_DE_PIPE_IIR(i)));
 625                         seq_printf(m, "Pipe %c IER:\t%08x\n",
 626                                    pipe_name(i),
 627                                    I915_READ(GEN8_DE_PIPE_IER(i)));
 628                 }
 629
 630                 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
 631                            I915_READ(GEN8_DE_PORT_IMR));
 632                 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
 633                            I915_READ(GEN8_DE_PORT_IIR));
 634                 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
 635                            I915_READ(GEN8_DE_PORT_IER));
 636
 637                 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
 638                            I915_READ(GEN8_DE_MISC_IMR));
 639                 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
 640                            I915_READ(GEN8_DE_MISC_IIR));
 641                 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
 642                            I915_READ(GEN8_DE_MISC_IER));
 643
 644                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 645                            I915_READ(GEN8_PCU_IMR));
 646                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 647                            I915_READ(GEN8_PCU_IIR));
 648                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 649                            I915_READ(GEN8_PCU_IER));
 650         } else if (IS_VALLEYVIEW(dev)) {
 651                 seq_printf(m, "Display IER:\t%08x\n",
 652                            I915_READ(VLV_IER));
 653                 seq_printf(m, "Display IIR:\t%08x\n",
 654                            I915_READ(VLV_IIR));
 655                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 656                            I915_READ(VLV_IIR_RW));
 657                 seq_printf(m, "Display IMR:\t%08x\n",
 658                            I915_READ(VLV_IMR));
 659                 for_each_pipe(pipe)
 660                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 661                                    pipe_name(pipe),
 662                                    I915_READ(PIPESTAT(pipe)));
 663
 664                 seq_printf(m, "Master IER:\t%08x\n",
 665                            I915_READ(VLV_MASTER_IER));
 666
 667                 seq_printf(m, "Render IER:\t%08x\n",
 668                            I915_READ(GTIER));
 669                 seq_printf(m, "Render IIR:\t%08x\n",
 670                            I915_READ(GTIIR));
 671                 seq_printf(m, "Render IMR:\t%08x\n",
 672                            I915_READ(GTIMR));
 673
 674                 seq_printf(m, "PM IER:\t\t%08x\n",
 675                            I915_READ(GEN6_PMIER));
 676                 seq_printf(m, "PM IIR:\t\t%08x\n",
 677                            I915_READ(GEN6_PMIIR));
 678                 seq_printf(m, "PM IMR:\t\t%08x\n",
 679                            I915_READ(GEN6_PMIMR));
 680
 681                 seq_printf(m, "Port hotplug:\t%08x\n",
 682                            I915_READ(PORT_HOTPLUG_EN));
 683                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 684                            I915_READ(VLV_DPFLIPSTAT));
 685                 seq_printf(m, "DPINVGTT:\t%08x\n",
 686                            I915_READ(DPINVGTT));
 687
 688         } else if (!HAS_PCH_SPLIT(dev)) {
 689                 seq_printf(m, "Interrupt enable:    %08x\n",
 690                            I915_READ(IER));
 691                 seq_printf(m, "Interrupt identity:  %08x\n",
 692                            I915_READ(IIR));
 693                 seq_printf(m, "Interrupt mask:      %08x\n",
 694                            I915_READ(IMR));
 695                 for_each_pipe(pipe)
 696                         seq_printf(m, "Pipe %c stat:         %08x\n",
 697                                    pipe_name(pipe),
 698                                    I915_READ(PIPESTAT(pipe)));
 699         } else {
 700                 seq_printf(m, "North Display Interrupt enable:          %08x\n",
 701                            I915_READ(DEIER));
 702                 seq_printf(m, "North Display Interrupt identity:        %08x\n",
 703                            I915_READ(DEIIR));
 704                 seq_printf(m, "North Display Interrupt mask:            %08x\n",
 705                            I915_READ(DEIMR));
 706                 seq_printf(m, "South Display Interrupt enable:          %08x\n",
 707                            I915_READ(SDEIER));
 708                 seq_printf(m, "South Display Interrupt identity:        %08x\n",
 709                            I915_READ(SDEIIR));
 710                 seq_printf(m, "South Display Interrupt mask:            %08x\n",
 711                            I915_READ(SDEIMR));
 712                 seq_printf(m, "Graphics Interrupt enable:               %08x\n",
 713                            I915_READ(GTIER));
 714                 seq_printf(m, "Graphics Interrupt identity:             %08x\n",
 715                            I915_READ(GTIIR));
 716                 seq_printf(m, "Graphics Interrupt mask:         %08x\n",
 717                            I915_READ(GTIMR));
 718         }
 719         for_each_ring(ring, dev_priv, i) {
 720                 if (INTEL_INFO(dev)->gen >= 6) {
 721                         seq_printf(m,
 722                                    "Graphics Interrupt mask (%s):       %08x\n",
 723                                    ring->name, I915_READ_IMR(ring));
 724                 }
 725                 i915_ring_seqno_info(m, ring);
 726         }
 727         intel_runtime_pm_put(dev_priv);
 728         mutex_unlock(&dev->struct_mutex);
 729
 730         return 0;
 731 }
 732
 733 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
 734 {
 735         struct drm_info_node *node = (struct drm_info_node *) m->private;
 736         struct drm_device *dev = node->minor->dev;
 737         drm_i915_private_t *dev_priv = dev->dev_private;
 738         int i, ret;
 739
 740         ret = mutex_lock_interruptible(&dev->struct_mutex);
 741         if (ret)
 742                 return ret;
 743
 744         seq_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
 745         seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
 746         for (i = 0; i < dev_priv->num_fence_regs; i++) {
 747                 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
 748
 749                 seq_printf(m, "Fence %d, pin count = %d, object = ",
 750                            i, dev_priv->fence_regs[i].pin_count);
 751                 if (obj == NULL)
 752                         seq_puts(m, "unused");
 753                 else
 754                         describe_obj(m, obj);
 755                 seq_putc(m, '\n');
 756         }
 757
 758         mutex_unlock(&dev->struct_mutex);
 759         return 0;
 760 }
 761
 762 static int i915_hws_info(struct seq_file *m, void *data)
 763 {
 764         struct drm_info_node *node = (struct drm_info_node *) m->private;
 765         struct drm_device *dev = node->minor->dev;
 766         drm_i915_private_t *dev_priv = dev->dev_private;
 767         struct intel_ring_buffer *ring;
 768         const u32 *hws;
 769         int i;
 770
 771         ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
 772         hws = ring->status_page.page_addr;
 773         if (hws == NULL)
 774                 return 0;
 775
 776         for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
 777                 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
 778                            i * 4,
 779                            hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
 780         }
 781         return 0;
 782 }
 783
 784 static ssize_t
 785 i915_error_state_write(struct file *filp,
 786                        const char __user *ubuf,
 787                        size_t cnt,
 788                        loff_t *ppos)
 789 {
 790         struct i915_error_state_file_priv *error_priv = filp->private_data;
 791         struct drm_device *dev = error_priv->dev;
 792         int ret;
 793
 794         DRM_DEBUG_DRIVER("Resetting error state\n");
 795
 796         ret = mutex_lock_interruptible(&dev->struct_mutex);
 797         if (ret)
 798                 return ret;
 799
 800         i915_destroy_error_state(dev);
 801         mutex_unlock(&dev->struct_mutex);
 802
 803         return cnt;
 804 }
 805
 806 static int i915_error_state_open(struct inode *inode, struct file *file)
 807 {
 808         struct drm_device *dev = inode->i_private;
 809         struct i915_error_state_file_priv *error_priv;
 810
 811         error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
 812         if (!error_priv)
 813                 return -ENOMEM;
 814
 815         error_priv->dev = dev;
 816
 817         i915_error_state_get(dev, error_priv);
 818
 819         file->private_data = error_priv;
 820
 821         return 0;
 822 }
 823
 824 static int i915_error_state_release(struct inode *inode, struct file *file)
 825 {
 826         struct i915_error_state_file_priv *error_priv = file->private_data;
 827
 828         i915_error_state_put(error_priv);
 829         kfree(error_priv);
 830
 831         return 0;
 832 }
 833
 834 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
 835                                      size_t count, loff_t *pos)
 836 {
 837         struct i915_error_state_file_priv *error_priv = file->private_data;
 838         struct drm_i915_error_state_buf error_str;
 839         loff_t tmp_pos = 0;
 840         ssize_t ret_count = 0;
 841         int ret;
 842
 843         ret = i915_error_state_buf_init(&error_str, count, *pos);
 844         if (ret)
 845                 return ret;
 846
 847         ret = i915_error_state_to_str(&error_str, error_priv);
 848         if (ret)
 849                 goto out;
 850
 851         ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
 852                                             error_str.buf,
 853                                             error_str.bytes);
 854
 855         if (ret_count < 0)
 856                 ret = ret_count;
 857         else
 858                 *pos = error_str.start + ret_count;
 859 out:
 860         i915_error_state_buf_release(&error_str);
 861         return ret ?: ret_count;
 862 }
 863
 864 static const struct file_operations i915_error_state_fops = {
 865         .owner = THIS_MODULE,
 866         .open = i915_error_state_open,
 867         .read = i915_error_state_read,
 868         .write = i915_error_state_write,
 869         .llseek = default_llseek,
 870         .release = i915_error_state_release,
 871 };
 872
 873 static int
 874 i915_next_seqno_get(void *data, u64 *val)
 875 {
 876         struct drm_device *dev = data;
 877         drm_i915_private_t *dev_priv = dev->dev_private;
 878         int ret;
 879
 880         ret = mutex_lock_interruptible(&dev->struct_mutex);
 881         if (ret)
 882                 return ret;
 883
 884         *val = dev_priv->next_seqno;
 885         mutex_unlock(&dev->struct_mutex);
 886
 887         return 0;
 888 }
 889
 890 static int
 891 i915_next_seqno_set(void *data, u64 val)
 892 {
 893         struct drm_device *dev = data;
 894         int ret;
 895
 896         ret = mutex_lock_interruptible(&dev->struct_mutex);
 897         if (ret)
 898                 return ret;
 899
 900         ret = i915_gem_set_seqno(dev, val);
 901         mutex_unlock(&dev->struct_mutex);
 902
 903         return ret;
 904 }
 905
 906 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
 907                         i915_next_seqno_get, i915_next_seqno_set,
 908                         "0x%llx\n");
 909
 910 static int i915_rstdby_delays(struct seq_file *m, void *unused)
 911 {
 912         struct drm_info_node *node = (struct drm_info_node *) m->private;
 913         struct drm_device *dev = node->minor->dev;
 914         drm_i915_private_t *dev_priv = dev->dev_private;
 915         u16 crstanddelay;
 916         int ret;
 917
 918         ret = mutex_lock_interruptible(&dev->struct_mutex);
 919         if (ret)
 920                 return ret;
 921         intel_runtime_pm_get(dev_priv);
 922
 923         crstanddelay = I915_READ16(CRSTANDVID);
 924
 925         intel_runtime_pm_put(dev_priv);
 926         mutex_unlock(&dev->struct_mutex);
 927
 928         seq_printf(m, "w/ctx: %d, w/o ctx: %d\n", (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
 929
 930         return 0;
 931 }
 932
 933 static int i915_cur_delayinfo(struct seq_file *m, void *unused)
 934 {
 935         struct drm_info_node *node = (struct drm_info_node *) m->private;
 936         struct drm_device *dev = node->minor->dev;
 937         drm_i915_private_t *dev_priv = dev->dev_private;
 938         int ret = 0;
 939
 940         intel_runtime_pm_get(dev_priv);
 941
 942         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
 943
 944         if (IS_GEN5(dev)) {
 945                 u16 rgvswctl = I915_READ16(MEMSWCTL);
 946                 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
 947
 948                 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
 949                 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
 950                 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
 951                            MEMSTAT_VID_SHIFT);
 952                 seq_printf(m, "Current P-state: %d\n",
 953                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
 954         } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
 955                 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
 956                 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
 957                 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
 958                 u32 rpstat, cagf, reqf;
 959                 u32 rpupei, rpcurup, rpprevup;
 960                 u32 rpdownei, rpcurdown, rpprevdown;
 961                 int max_freq;
 962
 963                 /* RPSTAT1 is in the GT power well */
 964                 ret = mutex_lock_interruptible(&dev->struct_mutex);
 965                 if (ret)
 966                         goto out;
 967
 968                 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
 969
 970                 reqf = I915_READ(GEN6_RPNSWREQ);
 971                 reqf &= ~GEN6_TURBO_DISABLE;
 972                 if (IS_HASWELL(dev))
 973                         reqf >>= 24;
 974                 else
 975                         reqf >>= 25;
 976                 reqf *= GT_FREQUENCY_MULTIPLIER;
 977
 978                 rpstat = I915_READ(GEN6_RPSTAT1);
 979                 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
 980                 rpcurup = I915_READ(GEN6_RP_CUR_UP);
 981                 rpprevup = I915_READ(GEN6_RP_PREV_UP);
 982                 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
 983                 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
 984                 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
 985                 if (IS_HASWELL(dev))
 986                         cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
 987                 else
 988                         cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
 989                 cagf *= GT_FREQUENCY_MULTIPLIER;
 990
 991                 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
 992                 mutex_unlock(&dev->struct_mutex);
 993
 994                 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
 995                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
 996                 seq_printf(m, "Render p-state ratio: %d\n",
 997                            (gt_perf_status & 0xff00) >> 8);
 998                 seq_printf(m, "Render p-state VID: %d\n",
 999                            gt_perf_status & 0xff);
1000                 seq_printf(m, "Render p-state limit: %d\n",
1001                            rp_state_limits & 0xff);
1002                 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1003                 seq_printf(m, "CAGF: %dMHz\n", cagf);
1004                 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1005                            GEN6_CURICONT_MASK);
1006                 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1007                            GEN6_CURBSYTAVG_MASK);
1008                 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1009                            GEN6_CURBSYTAVG_MASK);
1010                 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1011                            GEN6_CURIAVG_MASK);
1012                 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1013                            GEN6_CURBSYTAVG_MASK);
1014                 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1015                            GEN6_CURBSYTAVG_MASK);
1016
1017                 max_freq = (rp_state_cap & 0xff0000) >> 16;
1018                 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1019                            max_freq * GT_FREQUENCY_MULTIPLIER);
1020
1021                 max_freq = (rp_state_cap & 0xff00) >> 8;
1022                 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1023                            max_freq * GT_FREQUENCY_MULTIPLIER);
1024
1025                 max_freq = rp_state_cap & 0xff;
1026                 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1027                            max_freq * GT_FREQUENCY_MULTIPLIER);
1028
1029                 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1030                            dev_priv->rps.hw_max * GT_FREQUENCY_MULTIPLIER);
1031         } else if (IS_VALLEYVIEW(dev)) {
1032                 u32 freq_sts, val;
1033
1034                 mutex_lock(&dev_priv->rps.hw_lock);
1035                 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1036                 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1037                 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1038
1039                 val = valleyview_rps_max_freq(dev_priv);
1040                 seq_printf(m, "max GPU freq: %d MHz\n",
1041                            vlv_gpu_freq(dev_priv, val));
1042
1043                 val = valleyview_rps_min_freq(dev_priv);
1044                 seq_printf(m, "min GPU freq: %d MHz\n",
1045                            vlv_gpu_freq(dev_priv, val));
1046
1047                 seq_printf(m, "current GPU freq: %d MHz\n",
1048                            vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1049                 mutex_unlock(&dev_priv->rps.hw_lock);
1050         } else {
1051                 seq_puts(m, "no P-state info available\n");
1052         }
1053
1054 out:
1055         intel_runtime_pm_put(dev_priv);
1056         return ret;
1057 }
1058
1059 static int i915_delayfreq_table(struct seq_file *m, void *unused)
1060 {
1061         struct drm_info_node *node = (struct drm_info_node *) m->private;
1062         struct drm_device *dev = node->minor->dev;
1063         drm_i915_private_t *dev_priv = dev->dev_private;
1064         u32 delayfreq;
1065         int ret, i;
1066
1067         ret = mutex_lock_interruptible(&dev->struct_mutex);
1068         if (ret)
1069                 return ret;
1070         intel_runtime_pm_get(dev_priv);
1071
1072         for (i = 0; i < 16; i++) {
1073                 delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
1074                 seq_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
1075                            (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
1076         }
1077
1078         intel_runtime_pm_put(dev_priv);
1079
1080         mutex_unlock(&dev->struct_mutex);
1081
1082         return 0;
1083 }
1084
1085 static inline int MAP_TO_MV(int map)
1086 {
1087         return 1250 - (map * 25);
1088 }
1089
1090 static int i915_inttoext_table(struct seq_file *m, void *unused)
1091 {
1092         struct drm_info_node *node = (struct drm_info_node *) m->private;
1093         struct drm_device *dev = node->minor->dev;
1094         drm_i915_private_t *dev_priv = dev->dev_private;
1095         u32 inttoext;
1096         int ret, i;
1097
1098         ret = mutex_lock_interruptible(&dev->struct_mutex);
1099         if (ret)
1100                 return ret;
1101         intel_runtime_pm_get(dev_priv);
1102
1103         for (i = 1; i <= 32; i++) {
1104                 inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
1105                 seq_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
1106         }
1107
1108         intel_runtime_pm_put(dev_priv);
1109         mutex_unlock(&dev->struct_mutex);
1110
1111         return 0;
1112 }
1113
1114 static int ironlake_drpc_info(struct seq_file *m)
1115 {
1116         struct drm_info_node *node = (struct drm_info_node *) m->private;
1117         struct drm_device *dev = node->minor->dev;
1118         drm_i915_private_t *dev_priv = dev->dev_private;
1119         u32 rgvmodectl, rstdbyctl;
1120         u16 crstandvid;
1121         int ret;
1122
1123         ret = mutex_lock_interruptible(&dev->struct_mutex);
1124         if (ret)
1125                 return ret;
1126         intel_runtime_pm_get(dev_priv);
1127
1128         rgvmodectl = I915_READ(MEMMODECTL);
1129         rstdbyctl = I915_READ(RSTDBYCTL);
1130         crstandvid = I915_READ16(CRSTANDVID);
1131
1132         intel_runtime_pm_put(dev_priv);
1133         mutex_unlock(&dev->struct_mutex);
1134
1135         seq_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
1136                    "yes" : "no");
1137         seq_printf(m, "Boost freq: %d\n",
1138                    (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1139                    MEMMODE_BOOST_FREQ_SHIFT);
1140         seq_printf(m, "HW control enabled: %s\n",
1141                    rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
1142         seq_printf(m, "SW control enabled: %s\n",
1143                    rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
1144         seq_printf(m, "Gated voltage change: %s\n",
1145                    rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
1146         seq_printf(m, "Starting frequency: P%d\n",
1147                    (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1148         seq_printf(m, "Max P-state: P%d\n",
1149                    (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1150         seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1151         seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1152         seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1153         seq_printf(m, "Render standby enabled: %s\n",
1154                    (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
1155         seq_puts(m, "Current RS state: ");
1156         switch (rstdbyctl & RSX_STATUS_MASK) {
1157         case RSX_STATUS_ON:
1158                 seq_puts(m, "on\n");
1159                 break;
1160         case RSX_STATUS_RC1:
1161                 seq_puts(m, "RC1\n");
1162                 break;
1163         case RSX_STATUS_RC1E:
1164                 seq_puts(m, "RC1E\n");
1165                 break;
1166         case RSX_STATUS_RS1:
1167                 seq_puts(m, "RS1\n");
1168                 break;
1169         case RSX_STATUS_RS2:
1170                 seq_puts(m, "RS2 (RC6)\n");
1171                 break;
1172         case RSX_STATUS_RS3:
1173                 seq_puts(m, "RC3 (RC6+)\n");
1174                 break;
1175         default:
1176                 seq_puts(m, "unknown\n");
1177                 break;
1178         }
1179
1180         return 0;
1181 }
1182
1183 static int vlv_drpc_info(struct seq_file *m)
1184 {
1185
1186         struct drm_info_node *node = (struct drm_info_node *) m->private;
1187         struct drm_device *dev = node->minor->dev;
1188         struct drm_i915_private *dev_priv = dev->dev_private;
1189         u32 rpmodectl1, rcctl1;
1190         unsigned fw_rendercount = 0, fw_mediacount = 0;
1191
1192         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1193         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1194
1195         seq_printf(m, "Video Turbo Mode: %s\n",
1196                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1197         seq_printf(m, "Turbo enabled: %s\n",
1198                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1199         seq_printf(m, "HW control enabled: %s\n",
1200                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1201         seq_printf(m, "SW control enabled: %s\n",
1202                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1203                           GEN6_RP_MEDIA_SW_MODE));
1204         seq_printf(m, "RC6 Enabled: %s\n",
1205                    yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1206                                         GEN6_RC_CTL_EI_MODE(1))));
1207         seq_printf(m, "Render Power Well: %s\n",
1208                         (I915_READ(VLV_GTLC_PW_STATUS) &
1209                                 VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1210         seq_printf(m, "Media Power Well: %s\n",
1211                         (I915_READ(VLV_GTLC_PW_STATUS) &
1212                                 VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1213
1214         spin_lock_irq(&dev_priv->uncore.lock);
1215         fw_rendercount = dev_priv->uncore.fw_rendercount;
1216         fw_mediacount = dev_priv->uncore.fw_mediacount;
1217         spin_unlock_irq(&dev_priv->uncore.lock);
1218
1219         seq_printf(m, "Forcewake Render Count = %u\n", fw_rendercount);
1220         seq_printf(m, "Forcewake Media Count = %u\n", fw_mediacount);
1221
1222
1223         return 0;
1224 }
1225
1226
1227 static int gen6_drpc_info(struct seq_file *m)
1228 {
1229
1230         struct drm_info_node *node = (struct drm_info_node *) m->private;
1231         struct drm_device *dev = node->minor->dev;
1232         struct drm_i915_private *dev_priv = dev->dev_private;
1233         u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1234         unsigned forcewake_count;
1235         int count = 0, ret;
1236
1237         ret = mutex_lock_interruptible(&dev->struct_mutex);
1238         if (ret)
1239                 return ret;
1240         intel_runtime_pm_get(dev_priv);
1241
1242         spin_lock_irq(&dev_priv->uncore.lock);
1243         forcewake_count = dev_priv->uncore.forcewake_count;
1244         spin_unlock_irq(&dev_priv->uncore.lock);
1245
1246         if (forcewake_count) {
1247                 seq_puts(m, "RC information inaccurate because somebody "
1248                             "holds a forcewake reference \n");
1249         } else {
1250                 /* NB: we cannot use forcewake, else we read the wrong values */
1251                 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1252                         udelay(10);
1253                 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1254         }
1255
1256         gt_core_status = readl(dev_priv->regs + GEN6_GT_CORE_STATUS);
1257         trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1258
1259         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1260         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1261         mutex_unlock(&dev->struct_mutex);
1262         mutex_lock(&dev_priv->rps.hw_lock);
1263         sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1264         mutex_unlock(&dev_priv->rps.hw_lock);
1265
1266         intel_runtime_pm_put(dev_priv);
1267
1268         seq_printf(m, "Video Turbo Mode: %s\n",
1269                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1270         seq_printf(m, "HW control enabled: %s\n",
1271                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1272         seq_printf(m, "SW control enabled: %s\n",
1273                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1274                           GEN6_RP_MEDIA_SW_MODE));
1275         seq_printf(m, "RC1e Enabled: %s\n",
1276                    yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1277         seq_printf(m, "RC6 Enabled: %s\n",
1278                    yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1279         seq_printf(m, "Deep RC6 Enabled: %s\n",
1280                    yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1281         seq_printf(m, "Deepest RC6 Enabled: %s\n",
1282                    yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1283         seq_puts(m, "Current RC state: ");
1284         switch (gt_core_status & GEN6_RCn_MASK) {
1285         case GEN6_RC0:
1286                 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1287                         seq_puts(m, "Core Power Down\n");
1288                 else
1289                         seq_puts(m, "on\n");
1290                 break;
1291         case GEN6_RC3:
1292                 seq_puts(m, "RC3\n");
1293                 break;
1294         case GEN6_RC6:
1295                 seq_puts(m, "RC6\n");
1296                 break;
1297         case GEN6_RC7:
1298                 seq_puts(m, "RC7\n");
1299                 break;
1300         default:
1301                 seq_puts(m, "Unknown\n");
1302                 break;
1303         }
1304
1305         seq_printf(m, "Core Power Down: %s\n",
1306                    yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1307
1308         /* Not exactly sure what this is */
1309         seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1310                    I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1311         seq_printf(m, "RC6 residency since boot: %u\n",
1312                    I915_READ(GEN6_GT_GFX_RC6));
1313         seq_printf(m, "RC6+ residency since boot: %u\n",
1314                    I915_READ(GEN6_GT_GFX_RC6p));
1315         seq_printf(m, "RC6++ residency since boot: %u\n",
1316                    I915_READ(GEN6_GT_GFX_RC6pp));
1317
1318         seq_printf(m, "RC6   voltage: %dmV\n",
1319                    GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1320         seq_printf(m, "RC6+  voltage: %dmV\n",
1321                    GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1322         seq_printf(m, "RC6++ voltage: %dmV\n",
1323                    GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1324         return 0;
1325 }
1326
1327 static int i915_drpc_info(struct seq_file *m, void *unused)
1328 {
1329         struct drm_info_node *node = (struct drm_info_node *) m->private;
1330         struct drm_device *dev = node->minor->dev;
1331
1332         if (IS_VALLEYVIEW(dev))
1333                 return vlv_drpc_info(m);
1334         else if (IS_GEN6(dev) || IS_GEN7(dev))
1335                 return gen6_drpc_info(m);
1336         else
1337                 return ironlake_drpc_info(m);
1338 }
1339
1340 static int i915_fbc_status(struct seq_file *m, void *unused)
1341 {
1342         struct drm_info_node *node = (struct drm_info_node *) m->private;
1343         struct drm_device *dev = node->minor->dev;
1344         drm_i915_private_t *dev_priv = dev->dev_private;
1345
1346         if (!HAS_FBC(dev)) {
1347                 seq_puts(m, "FBC unsupported on this chipset\n");
1348                 return 0;
1349         }
1350
1351         if (intel_fbc_enabled(dev)) {
1352                 seq_puts(m, "FBC enabled\n");
1353         } else {
1354                 seq_puts(m, "FBC disabled: ");
1355                 switch (dev_priv->fbc.no_fbc_reason) {
1356                 case FBC_OK:
1357                         seq_puts(m, "FBC actived, but currently disabled in hardware");
1358                         break;
1359                 case FBC_UNSUPPORTED:
1360                         seq_puts(m, "unsupported by this chipset");
1361                         break;
1362                 case FBC_NO_OUTPUT:
1363                         seq_puts(m, "no outputs");
1364                         break;
1365                 case FBC_STOLEN_TOO_SMALL:
1366                         seq_puts(m, "not enough stolen memory");
1367                         break;
1368                 case FBC_UNSUPPORTED_MODE:
1369                         seq_puts(m, "mode not supported");
1370                         break;
1371                 case FBC_MODE_TOO_LARGE:
1372                         seq_puts(m, "mode too large");
1373                         break;
1374                 case FBC_BAD_PLANE:
1375                         seq_puts(m, "FBC unsupported on plane");
1376                         break;
1377                 case FBC_NOT_TILED:
1378                         seq_puts(m, "scanout buffer not tiled");
1379                         break;
1380                 case FBC_MULTIPLE_PIPES:
1381                         seq_puts(m, "multiple pipes are enabled");
1382                         break;
1383                 case FBC_MODULE_PARAM:
1384                         seq_puts(m, "disabled per module param (default off)");
1385                         break;
1386                 case FBC_CHIP_DEFAULT:
1387                         seq_puts(m, "disabled per chip default");
1388                         break;
1389                 default:
1390                         seq_puts(m, "unknown reason");
1391                 }
1392                 seq_putc(m, '\n');
1393         }
1394         return 0;
1395 }
1396
1397 static int i915_ips_status(struct seq_file *m, void *unused)
1398 {
1399         struct drm_info_node *node = (struct drm_info_node *) m->private;
1400         struct drm_device *dev = node->minor->dev;
1401         struct drm_i915_private *dev_priv = dev->dev_private;
1402
1403         if (!HAS_IPS(dev)) {
1404                 seq_puts(m, "not supported\n");
1405                 return 0;
1406         }
1407
1408         if (IS_BROADWELL(dev) || I915_READ(IPS_CTL) & IPS_ENABLE)
1409                 seq_puts(m, "enabled\n");
1410         else
1411                 seq_puts(m, "disabled\n");
1412
1413         return 0;
1414 }
1415
1416 static int i915_sr_status(struct seq_file *m, void *unused)
1417 {
1418         struct drm_info_node *node = (struct drm_info_node *) m->private;
1419         struct drm_device *dev = node->minor->dev;
1420         drm_i915_private_t *dev_priv = dev->dev_private;
1421         bool sr_enabled = false;
1422
1423         if (HAS_PCH_SPLIT(dev))
1424                 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1425         else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
1426                 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1427         else if (IS_I915GM(dev))
1428                 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1429         else if (IS_PINEVIEW(dev))
1430                 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1431
1432         seq_printf(m, "self-refresh: %s\n",
1433                    sr_enabled ? "enabled" : "disabled");
1434
1435         return 0;
1436 }
1437
1438 static int i915_emon_status(struct seq_file *m, void *unused)
1439 {
1440         struct drm_info_node *node = (struct drm_info_node *) m->private;
1441         struct drm_device *dev = node->minor->dev;
1442         drm_i915_private_t *dev_priv = dev->dev_private;
1443         unsigned long temp, chipset, gfx;
1444         int ret;
1445
1446         if (!IS_GEN5(dev))
1447                 return -ENODEV;
1448
1449         ret = mutex_lock_interruptible(&dev->struct_mutex);
1450         if (ret)
1451                 return ret;
1452
1453         temp = i915_mch_val(dev_priv);
1454         chipset = i915_chipset_val(dev_priv);
1455         gfx = i915_gfx_val(dev_priv);
1456         mutex_unlock(&dev->struct_mutex);
1457
1458         seq_printf(m, "GMCH temp: %ld\n", temp);
1459         seq_printf(m, "Chipset power: %ld\n", chipset);
1460         seq_printf(m, "GFX power: %ld\n", gfx);
1461         seq_printf(m, "Total power: %ld\n", chipset + gfx);
1462
1463         return 0;
1464 }
1465
1466 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1467 {
1468         struct drm_info_node *node = (struct drm_info_node *) m->private;
1469         struct drm_device *dev = node->minor->dev;
1470         drm_i915_private_t *dev_priv = dev->dev_private;
1471         int ret = 0;
1472         int gpu_freq, ia_freq;
1473
1474         if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
1475                 seq_puts(m, "unsupported on this chipset\n");
1476                 return 0;
1477         }
1478
1479         intel_runtime_pm_get(dev_priv);
1480
1481         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1482
1483         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1484         if (ret)
1485                 goto out;
1486
1487         seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1488
1489         for (gpu_freq = dev_priv->rps.min_delay;
1490              gpu_freq <= dev_priv->rps.max_delay;
1491              gpu_freq++) {
1492                 ia_freq = gpu_freq;
1493                 sandybridge_pcode_read(dev_priv,
1494                                        GEN6_PCODE_READ_MIN_FREQ_TABLE,
1495                                        &ia_freq);
1496                 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1497                            gpu_freq * GT_FREQUENCY_MULTIPLIER,
1498                            ((ia_freq >> 0) & 0xff) * 100,
1499                            ((ia_freq >> 8) & 0xff) * 100);
1500         }
1501
1502         mutex_unlock(&dev_priv->rps.hw_lock);
1503
1504 out:
1505         intel_runtime_pm_put(dev_priv);
1506         return ret;
1507 }
1508
1509 static int i915_gfxec(struct seq_file *m, void *unused)
1510 {
1511         struct drm_info_node *node = (struct drm_info_node *) m->private;
1512         struct drm_device *dev = node->minor->dev;
1513         drm_i915_private_t *dev_priv = dev->dev_private;
1514         int ret;
1515
1516         ret = mutex_lock_interruptible(&dev->struct_mutex);
1517         if (ret)
1518                 return ret;
1519         intel_runtime_pm_get(dev_priv);
1520
1521         seq_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
1522         intel_runtime_pm_put(dev_priv);
1523
1524         mutex_unlock(&dev->struct_mutex);
1525
1526         return 0;
1527 }
1528
1529 static int i915_opregion(struct seq_file *m, void *unused)
1530 {
1531         struct drm_info_node *node = (struct drm_info_node *) m->private;
1532         struct drm_device *dev = node->minor->dev;
1533         drm_i915_private_t *dev_priv = dev->dev_private;
1534         struct intel_opregion *opregion = &dev_priv->opregion;
1535         void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
1536         int ret;
1537
1538         if (data == NULL)
1539                 return -ENOMEM;
1540
1541         ret = mutex_lock_interruptible(&dev->struct_mutex);
1542         if (ret)
1543                 goto out;
1544
1545         if (opregion->header) {
1546                 memcpy_fromio(data, opregion->header, OPREGION_SIZE);
1547                 seq_write(m, data, OPREGION_SIZE);
1548         }
1549
1550         mutex_unlock(&dev->struct_mutex);
1551
1552 out:
1553         kfree(data);
1554         return 0;
1555 }
1556
1557 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1558 {
1559         struct drm_info_node *node = (struct drm_info_node *) m->private;
1560         struct drm_device *dev = node->minor->dev;
1561         struct intel_fbdev *ifbdev = NULL;
1562         struct intel_framebuffer *fb;
1563
1564 #ifdef CONFIG_DRM_I915_FBDEV
1565         struct drm_i915_private *dev_priv = dev->dev_private;
1566         int ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1567         if (ret)
1568                 return ret;
1569
1570         ifbdev = dev_priv->fbdev;
1571         fb = to_intel_framebuffer(ifbdev->helper.fb);
1572
1573         seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1574                    fb->base.width,
1575                    fb->base.height,
1576                    fb->base.depth,
1577                    fb->base.bits_per_pixel,
1578                    atomic_read(&fb->base.refcount.refcount));
1579         describe_obj(m, fb->obj);
1580         seq_putc(m, '\n');
1581         mutex_unlock(&dev->mode_config.mutex);
1582 #endif
1583
1584         mutex_lock(&dev->mode_config.fb_lock);
1585         list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1586                 if (ifbdev && &fb->base == ifbdev->helper.fb)
1587                         continue;
1588
1589                 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, refcount %d, obj ",
1590                            fb->base.width,
1591                            fb->base.height,
1592                            fb->base.depth,
1593                            fb->base.bits_per_pixel,
1594                            atomic_read(&fb->base.refcount.refcount));
1595                 describe_obj(m, fb->obj);
1596                 seq_putc(m, '\n');
1597         }
1598         mutex_unlock(&dev->mode_config.fb_lock);
1599
1600         return 0;
1601 }
1602
1603 static int i915_context_status(struct seq_file *m, void *unused)
1604 {
1605         struct drm_info_node *node = (struct drm_info_node *) m->private;
1606         struct drm_device *dev = node->minor->dev;
1607         drm_i915_private_t *dev_priv = dev->dev_private;
1608         struct intel_ring_buffer *ring;
1609         struct i915_hw_context *ctx;
1610         int ret, i;
1611
1612         ret = mutex_lock_interruptible(&dev->mode_config.mutex);
1613         if (ret)
1614                 return ret;
1615
1616         if (dev_priv->ips.pwrctx) {
1617                 seq_puts(m, "power context ");
1618                 describe_obj(m, dev_priv->ips.pwrctx);
1619                 seq_putc(m, '\n');
1620         }
1621
1622         if (dev_priv->ips.renderctx) {
1623                 seq_puts(m, "render context ");
1624                 describe_obj(m, dev_priv->ips.renderctx);
1625                 seq_putc(m, '\n');
1626         }
1627
1628         list_for_each_entry(ctx, &dev_priv->context_list, link) {
1629                 seq_puts(m, "HW context ");
1630                 describe_ctx(m, ctx);
1631                 for_each_ring(ring, dev_priv, i)
1632                         if (ring->default_context == ctx)
1633                                 seq_printf(m, "(default context %s) ", ring->name);
1634
1635                 describe_obj(m, ctx->obj);
1636                 seq_putc(m, '\n');
1637         }
1638
1639         mutex_unlock(&dev->mode_config.mutex);
1640
1641         return 0;
1642 }
1643
1644 static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1645 {
1646         struct drm_info_node *node = (struct drm_info_node *) m->private;
1647         struct drm_device *dev = node->minor->dev;
1648         struct drm_i915_private *dev_priv = dev->dev_private;
1649         unsigned forcewake_count = 0, fw_rendercount = 0, fw_mediacount = 0;
1650
1651         spin_lock_irq(&dev_priv->uncore.lock);
1652         if (IS_VALLEYVIEW(dev)) {
1653                 fw_rendercount = dev_priv->uncore.fw_rendercount;
1654                 fw_mediacount = dev_priv->uncore.fw_mediacount;
1655         } else
1656                 forcewake_count = dev_priv->uncore.forcewake_count;
1657         spin_unlock_irq(&dev_priv->uncore.lock);
1658
1659         if (IS_VALLEYVIEW(dev)) {
1660                 seq_printf(m, "fw_rendercount = %u\n", fw_rendercount);
1661                 seq_printf(m, "fw_mediacount = %u\n", fw_mediacount);
1662         } else
1663                 seq_printf(m, "forcewake count = %u\n", forcewake_count);
1664
1665         return 0;
1666 }
1667
1668 static const char *swizzle_string(unsigned swizzle)
1669 {
1670         switch (swizzle) {
1671         case I915_BIT_6_SWIZZLE_NONE:
1672                 return "none";
1673         case I915_BIT_6_SWIZZLE_9:
1674                 return "bit9";
1675         case I915_BIT_6_SWIZZLE_9_10:
1676                 return "bit9/bit10";
1677         case I915_BIT_6_SWIZZLE_9_11:
1678                 return "bit9/bit11";
1679         case I915_BIT_6_SWIZZLE_9_10_11:
1680                 return "bit9/bit10/bit11";
1681         case I915_BIT_6_SWIZZLE_9_17:
1682                 return "bit9/bit17";
1683         case I915_BIT_6_SWIZZLE_9_10_17:
1684                 return "bit9/bit10/bit17";
1685         case I915_BIT_6_SWIZZLE_UNKNOWN:
1686                 return "unknown";
1687         }
1688
1689         return "bug";
1690 }
1691
1692 static int i915_swizzle_info(struct seq_file *m, void *data)
1693 {
1694         struct drm_info_node *node = (struct drm_info_node *) m->private;
1695         struct drm_device *dev = node->minor->dev;
1696         struct drm_i915_private *dev_priv = dev->dev_private;
1697         int ret;
1698
1699         ret = mutex_lock_interruptible(&dev->struct_mutex);
1700         if (ret)
1701                 return ret;
1702         intel_runtime_pm_get(dev_priv);
1703
1704         seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
1705                    swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1706         seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1707                    swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1708
1709         if (IS_GEN3(dev) || IS_GEN4(dev)) {
1710                 seq_printf(m, "DDC = 0x%08x\n",
1711                            I915_READ(DCC));
1712                 seq_printf(m, "C0DRB3 = 0x%04x\n",
1713                            I915_READ16(C0DRB3));
1714                 seq_printf(m, "C1DRB3 = 0x%04x\n",
1715                            I915_READ16(C1DRB3));
1716         } else if (INTEL_INFO(dev)->gen >= 6) {
1717                 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1718                            I915_READ(MAD_DIMM_C0));
1719                 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1720                            I915_READ(MAD_DIMM_C1));
1721                 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1722                            I915_READ(MAD_DIMM_C2));
1723                 seq_printf(m, "TILECTL = 0x%08x\n",
1724                            I915_READ(TILECTL));
1725                 if (IS_GEN8(dev))
1726                         seq_printf(m, "GAMTARBMODE = 0x%08x\n",
1727                                    I915_READ(GAMTARBMODE));
1728                 else
1729                         seq_printf(m, "ARB_MODE = 0x%08x\n",
1730                                    I915_READ(ARB_MODE));
1731                 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1732                            I915_READ(DISP_ARB_CTL));
1733         }
1734         intel_runtime_pm_put(dev_priv);
1735         mutex_unlock(&dev->struct_mutex);
1736
1737         return 0;
1738 }
1739
1740 static int per_file_ctx(int id, void *ptr, void *data)
1741 {
1742         struct i915_hw_context *ctx = ptr;
1743         struct seq_file *m = data;
1744         struct i915_hw_ppgtt *ppgtt = ctx_to_ppgtt(ctx);
1745
1746         ppgtt->debug_dump(ppgtt, m);
1747
1748         return 0;
1749 }
1750
1751 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
1752 {
1753         struct drm_i915_private *dev_priv = dev->dev_private;
1754         struct intel_ring_buffer *ring;
1755         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1756         int unused, i;
1757
1758         if (!ppgtt)
1759                 return;
1760
1761         seq_printf(m, "Page directories: %d\n", ppgtt->num_pd_pages);
1762         seq_printf(m, "Page tables: %d\n", ppgtt->num_pt_pages);
1763         for_each_ring(ring, dev_priv, unused) {
1764                 seq_printf(m, "%s\n", ring->name);
1765                 for (i = 0; i < 4; i++) {
1766                         u32 offset = 0x270 + i * 8;
1767                         u64 pdp = I915_READ(ring->mmio_base + offset + 4);
1768                         pdp <<= 32;
1769                         pdp |= I915_READ(ring->mmio_base + offset);
1770                         for (i = 0; i < 4; i++)
1771                                 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
1772                 }
1773         }
1774 }
1775
1776 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
1777 {
1778         struct drm_i915_private *dev_priv = dev->dev_private;
1779         struct intel_ring_buffer *ring;
1780         struct drm_file *file;
1781         int i;
1782
1783         if (INTEL_INFO(dev)->gen == 6)
1784                 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
1785
1786         for_each_ring(ring, dev_priv, i) {
1787                 seq_printf(m, "%s\n", ring->name);
1788                 if (INTEL_INFO(dev)->gen == 7)
1789                         seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
1790                 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
1791                 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
1792                 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
1793         }
1794         if (dev_priv->mm.aliasing_ppgtt) {
1795                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1796
1797                 seq_puts(m, "aliasing PPGTT:\n");
1798                 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1799
1800                 ppgtt->debug_dump(ppgtt, m);
1801         } else
1802                 return;
1803
1804         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
1805                 struct drm_i915_file_private *file_priv = file->driver_priv;
1806                 struct i915_hw_ppgtt *pvt_ppgtt;
1807
1808                 pvt_ppgtt = ctx_to_ppgtt(file_priv->private_default_ctx);
1809                 seq_printf(m, "proc: %s\n",
1810                            get_pid_task(file->pid, PIDTYPE_PID)->comm);
1811                 seq_puts(m, "  default context:\n");
1812                 idr_for_each(&file_priv->context_idr, per_file_ctx, m);
1813         }
1814         seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
1815 }
1816
1817 static int i915_ppgtt_info(struct seq_file *m, void *data)
1818 {
1819         struct drm_info_node *node = (struct drm_info_node *) m->private;
1820         struct drm_device *dev = node->minor->dev;
1821         struct drm_i915_private *dev_priv = dev->dev_private;
1822
1823         int ret = mutex_lock_interruptible(&dev->struct_mutex);
1824         if (ret)
1825                 return ret;
1826         intel_runtime_pm_get(dev_priv);
1827
1828         if (INTEL_INFO(dev)->gen >= 8)
1829                 gen8_ppgtt_info(m, dev);
1830         else if (INTEL_INFO(dev)->gen >= 6)
1831                 gen6_ppgtt_info(m, dev);
1832
1833         intel_runtime_pm_put(dev_priv);
1834         mutex_unlock(&dev->struct_mutex);
1835
1836         return 0;
1837 }
1838
1839 static int i915_dpio_info(struct seq_file *m, void *data)
1840 {
1841         struct drm_info_node *node = (struct drm_info_node *) m->private;
1842         struct drm_device *dev = node->minor->dev;
1843         struct drm_i915_private *dev_priv = dev->dev_private;
1844         int ret;
1845
1846
1847         if (!IS_VALLEYVIEW(dev)) {
1848                 seq_puts(m, "unsupported\n");
1849                 return 0;
1850         }
1851
1852         ret = mutex_lock_interruptible(&dev_priv->dpio_lock);
1853         if (ret)
1854                 return ret;
1855
1856         seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL));
1857
1858         seq_printf(m, "DPIO PLL DW3 CH0 : 0x%08x\n",
1859                    vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW3(0)));
1860         seq_printf(m, "DPIO PLL DW3 CH1: 0x%08x\n",
1861                    vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW3(1)));
1862
1863         seq_printf(m, "DPIO PLL DW5 CH0: 0x%08x\n",
1864                    vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW5(0)));
1865         seq_printf(m, "DPIO PLL DW5 CH1: 0x%08x\n",
1866                    vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW5(1)));
1867
1868         seq_printf(m, "DPIO PLL DW7 CH0: 0x%08x\n",
1869                    vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW7(0)));
1870         seq_printf(m, "DPIO PLL DW7 CH1: 0x%08x\n",
1871                    vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW7(1)));
1872
1873         seq_printf(m, "DPIO PLL DW10 CH0: 0x%08x\n",
1874                    vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW10(0)));
1875         seq_printf(m, "DPIO PLL DW10 CH1: 0x%08x\n",
1876                    vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW10(1)));
1877
1878         seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n",
1879                    vlv_dpio_read(dev_priv, PIPE_A, VLV_CMN_DW0));
1880
1881         mutex_unlock(&dev_priv->dpio_lock);
1882
1883         return 0;
1884 }
1885
1886 static int i915_llc(struct seq_file *m, void *data)
1887 {
1888         struct drm_info_node *node = (struct drm_info_node *) m->private;
1889         struct drm_device *dev = node->minor->dev;
1890         struct drm_i915_private *dev_priv = dev->dev_private;
1891
1892         /* Size calculation for LLC is a bit of a pain. Ignore for now. */
1893         seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
1894         seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
1895
1896         return 0;
1897 }
1898
1899 static int i915_edp_psr_status(struct seq_file *m, void *data)
1900 {
1901         struct drm_info_node *node = m->private;
1902         struct drm_device *dev = node->minor->dev;
1903         struct drm_i915_private *dev_priv = dev->dev_private;
1904         u32 psrperf = 0;
1905         bool enabled = false;
1906
1907         intel_runtime_pm_get(dev_priv);
1908
1909         seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
1910         seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
1911
1912         enabled = HAS_PSR(dev) &&
1913                 I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE;
1914         seq_printf(m, "Enabled: %s\n", yesno(enabled));
1915
1916         if (HAS_PSR(dev))
1917                 psrperf = I915_READ(EDP_PSR_PERF_CNT(dev)) &
1918                         EDP_PSR_PERF_CNT_MASK;
1919         seq_printf(m, "Performance_Counter: %u\n", psrperf);
1920
1921         intel_runtime_pm_put(dev_priv);
1922         return 0;
1923 }
1924
1925 static int i915_sink_crc(struct seq_file *m, void *data)
1926 {
1927         struct drm_info_node *node = m->private;
1928         struct drm_device *dev = node->minor->dev;
1929         struct intel_encoder *encoder;
1930         struct intel_connector *connector;
1931         struct intel_dp *intel_dp = NULL;
1932         int ret;
1933         u8 crc[6];
1934
1935         drm_modeset_lock_all(dev);
1936         list_for_each_entry(connector, &dev->mode_config.connector_list,
1937                             base.head) {
1938
1939                 if (connector->base.dpms != DRM_MODE_DPMS_ON)
1940                         continue;
1941
1942                 if (!connector->base.encoder)
1943                         continue;
1944
1945                 encoder = to_intel_encoder(connector->base.encoder);
1946                 if (encoder->type != INTEL_OUTPUT_EDP)
1947                         continue;
1948
1949                 intel_dp = enc_to_intel_dp(&encoder->base);
1950
1951                 ret = intel_dp_sink_crc(intel_dp, crc);
1952                 if (ret)
1953                         goto out;
1954
1955                 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
1956                            crc[0], crc[1], crc[2],
1957                            crc[3], crc[4], crc[5]);
1958                 goto out;
1959         }
1960         ret = -ENODEV;
1961 out:
1962         drm_modeset_unlock_all(dev);
1963         return ret;
1964 }
1965
1966 static int i915_energy_uJ(struct seq_file *m, void *data)
1967 {
1968         struct drm_info_node *node = m->private;
1969         struct drm_device *dev = node->minor->dev;
1970         struct drm_i915_private *dev_priv = dev->dev_private;
1971         u64 power;
1972         u32 units;
1973
1974         if (INTEL_INFO(dev)->gen < 6)
1975                 return -ENODEV;
1976
1977         rdmsrl(MSR_RAPL_POWER_UNIT, power);
1978         power = (power & 0x1f00) >> 8;
1979         units = 1000000 / (1 << power); /* convert to uJ */
1980         power = I915_READ(MCH_SECP_NRG_STTS);
1981         power *= units;
1982
1983         seq_printf(m, "%llu", (long long unsigned)power);
1984
1985         return 0;
1986 }
1987
1988 static int i915_pc8_status(struct seq_file *m, void *unused)
1989 {
1990         struct drm_info_node *node = (struct drm_info_node *) m->private;
1991         struct drm_device *dev = node->minor->dev;
1992         struct drm_i915_private *dev_priv = dev->dev_private;
1993
1994         if (!IS_HASWELL(dev)) {
1995                 seq_puts(m, "not supported\n");
1996                 return 0;
1997         }
1998
1999         mutex_lock(&dev_priv->pc8.lock);
2000         seq_printf(m, "Requirements met: %s\n",
2001                    yesno(dev_priv->pc8.requirements_met));
2002         seq_printf(m, "GPU idle: %s\n", yesno(dev_priv->pc8.gpu_idle));
2003         seq_printf(m, "Disable count: %d\n", dev_priv->pc8.disable_count);
2004         seq_printf(m, "IRQs disabled: %s\n",
2005                    yesno(dev_priv->pc8.irqs_disabled));
2006         seq_printf(m, "Enabled: %s\n", yesno(dev_priv->pc8.enabled));
2007         mutex_unlock(&dev_priv->pc8.lock);
2008
2009         return 0;
2010 }
2011
2012 static const char *power_domain_str(enum intel_display_power_domain domain)
2013 {
2014         switch (domain) {
2015         case POWER_DOMAIN_PIPE_A:
2016                 return "PIPE_A";
2017         case POWER_DOMAIN_PIPE_B:
2018                 return "PIPE_B";
2019         case POWER_DOMAIN_PIPE_C:
2020                 return "PIPE_C";
2021         case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
2022                 return "PIPE_A_PANEL_FITTER";
2023         case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
2024                 return "PIPE_B_PANEL_FITTER";
2025         case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
2026                 return "PIPE_C_PANEL_FITTER";
2027         case POWER_DOMAIN_TRANSCODER_A:
2028                 return "TRANSCODER_A";
2029         case POWER_DOMAIN_TRANSCODER_B:
2030                 return "TRANSCODER_B";
2031         case POWER_DOMAIN_TRANSCODER_C:
2032                 return "TRANSCODER_C";
2033         case POWER_DOMAIN_TRANSCODER_EDP:
2034                 return "TRANSCODER_EDP";
2035         case POWER_DOMAIN_VGA:
2036                 return "VGA";
2037         case POWER_DOMAIN_AUDIO:
2038                 return "AUDIO";
2039         case POWER_DOMAIN_INIT:
2040                 return "INIT";
2041         default:
2042                 WARN_ON(1);
2043                 return "?";
2044         }
2045 }
2046
2047 static int i915_power_domain_info(struct seq_file *m, void *unused)
2048 {
2049         struct drm_info_node *node = (struct drm_info_node *) m->private;
2050         struct drm_device *dev = node->minor->dev;
2051         struct drm_i915_private *dev_priv = dev->dev_private;
2052         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2053         int i;
2054
2055         mutex_lock(&power_domains->lock);
2056
2057         seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2058         for (i = 0; i < power_domains->power_well_count; i++) {
2059                 struct i915_power_well *power_well;
2060                 enum intel_display_power_domain power_domain;
2061
2062                 power_well = &power_domains->power_wells[i];
2063                 seq_printf(m, "%-25s %d\n", power_well->name,
2064                            power_well->count);
2065
2066                 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2067                      power_domain++) {
2068                         if (!(BIT(power_domain) & power_well->domains))
2069                                 continue;
2070
2071                         seq_printf(m, "  %-23s %d\n",
2072                                  power_domain_str(power_domain),
2073                                  power_domains->domain_use_count[power_domain]);
2074                 }
2075         }
2076
2077         mutex_unlock(&power_domains->lock);
2078
2079         return 0;
2080 }
2081
2082 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2083                                  struct drm_display_mode *mode)
2084 {
2085         int i;
2086
2087         for (i = 0; i < tabs; i++)
2088                 seq_putc(m, '\t');
2089
2090         seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2091                    mode->base.id, mode->name,
2092                    mode->vrefresh, mode->clock,
2093                    mode->hdisplay, mode->hsync_start,
2094                    mode->hsync_end, mode->htotal,
2095                    mode->vdisplay, mode->vsync_start,
2096                    mode->vsync_end, mode->vtotal,
2097                    mode->type, mode->flags);
2098 }
2099
2100 static void intel_encoder_info(struct seq_file *m,
2101                                struct intel_crtc *intel_crtc,
2102                                struct intel_encoder *intel_encoder)
2103 {
2104         struct drm_info_node *node = (struct drm_info_node *) m->private;
2105         struct drm_device *dev = node->minor->dev;
2106         struct drm_crtc *crtc = &intel_crtc->base;
2107         struct intel_connector *intel_connector;
2108         struct drm_encoder *encoder;
2109
2110         encoder = &intel_encoder->base;
2111         seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2112                    encoder->base.id, drm_get_encoder_name(encoder));
2113         for_each_connector_on_encoder(dev, encoder, intel_connector) {
2114                 struct drm_connector *connector = &intel_connector->base;
2115                 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2116                            connector->base.id,
2117                            drm_get_connector_name(connector),
2118                            drm_get_connector_status_name(connector->status));
2119                 if (connector->status == connector_status_connected) {
2120                         struct drm_display_mode *mode = &crtc->mode;
2121                         seq_printf(m, ", mode:\n");
2122                         intel_seq_print_mode(m, 2, mode);
2123                 } else {
2124                         seq_putc(m, '\n');
2125                 }
2126         }
2127 }
2128
2129 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2130 {
2131         struct drm_info_node *node = (struct drm_info_node *) m->private;
2132         struct drm_device *dev = node->minor->dev;
2133         struct drm_crtc *crtc = &intel_crtc->base;
2134         struct intel_encoder *intel_encoder;
2135
2136         seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2137                    crtc->fb->base.id, crtc->x, crtc->y,
2138                    crtc->fb->width, crtc->fb->height);
2139         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2140                 intel_encoder_info(m, intel_crtc, intel_encoder);
2141 }
2142
2143 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2144 {
2145         struct drm_display_mode *mode = panel->fixed_mode;
2146
2147         seq_printf(m, "\tfixed mode:\n");
2148         intel_seq_print_mode(m, 2, mode);
2149 }
2150
2151 static void intel_dp_info(struct seq_file *m,
2152                           struct intel_connector *intel_connector)
2153 {
2154         struct intel_encoder *intel_encoder = intel_connector->encoder;
2155         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2156
2157         seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2158         seq_printf(m, "\taudio support: %s\n", intel_dp->has_audio ? "yes" :
2159                    "no");
2160         if (intel_encoder->type == INTEL_OUTPUT_EDP)
2161                 intel_panel_info(m, &intel_connector->panel);
2162 }
2163
2164 static void intel_hdmi_info(struct seq_file *m,
2165                             struct intel_connector *intel_connector)
2166 {
2167         struct intel_encoder *intel_encoder = intel_connector->encoder;
2168         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2169
2170         seq_printf(m, "\taudio support: %s\n", intel_hdmi->has_audio ? "yes" :
2171                    "no");
2172 }
2173
2174 static void intel_lvds_info(struct seq_file *m,
2175                             struct intel_connector *intel_connector)
2176 {
2177         intel_panel_info(m, &intel_connector->panel);
2178 }
2179
2180 static void intel_connector_info(struct seq_file *m,
2181                                  struct drm_connector *connector)
2182 {
2183         struct intel_connector *intel_connector = to_intel_connector(connector);
2184         struct intel_encoder *intel_encoder = intel_connector->encoder;
2185
2186         seq_printf(m, "connector %d: type %s, status: %s\n",
2187                    connector->base.id, drm_get_connector_name(connector),
2188                    drm_get_connector_status_name(connector->status));
2189         if (connector->status == connector_status_connected) {
2190                 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2191                 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2192                            connector->display_info.width_mm,
2193                            connector->display_info.height_mm);
2194                 seq_printf(m, "\tsubpixel order: %s\n",
2195                            drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2196                 seq_printf(m, "\tCEA rev: %d\n",
2197                            connector->display_info.cea_rev);
2198         }
2199         if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2200             intel_encoder->type == INTEL_OUTPUT_EDP)
2201                 intel_dp_info(m, intel_connector);
2202         else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2203                 intel_hdmi_info(m, intel_connector);
2204         else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2205                 intel_lvds_info(m, intel_connector);
2206
2207 }
2208
2209 static int i915_display_info(struct seq_file *m, void *unused)
2210 {
2211         struct drm_info_node *node = (struct drm_info_node *) m->private;
2212         struct drm_device *dev = node->minor->dev;
2213         struct drm_crtc *crtc;
2214         struct drm_connector *connector;
2215
2216         drm_modeset_lock_all(dev);
2217         seq_printf(m, "CRTC info\n");
2218         seq_printf(m, "---------\n");
2219         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2220                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2221
2222                 seq_printf(m, "CRTC %d: pipe: %c, active: %s\n",
2223                            crtc->base.id, pipe_name(intel_crtc->pipe),
2224                            intel_crtc->active ? "yes" : "no");
2225                 if (intel_crtc->active)
2226                         intel_crtc_info(m, intel_crtc);
2227         }
2228
2229         seq_printf(m, "\n");
2230         seq_printf(m, "Connector info\n");
2231         seq_printf(m, "--------------\n");
2232         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
2233                 intel_connector_info(m, connector);
2234         }
2235         drm_modeset_unlock_all(dev);
2236
2237         return 0;
2238 }
2239
2240 struct pipe_crc_info {
2241         const char *name;
2242         struct drm_device *dev;
2243         enum pipe pipe;
2244 };
2245
2246 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
2247 {
2248         struct pipe_crc_info *info = inode->i_private;
2249         struct drm_i915_private *dev_priv = info->dev->dev_private;
2250         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2251
2252         if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
2253                 return -ENODEV;
2254
2255         spin_lock_irq(&pipe_crc->lock);
2256
2257         if (pipe_crc->opened) {
2258                 spin_unlock_irq(&pipe_crc->lock);
2259                 return -EBUSY; /* already open */
2260         }
2261
2262         pipe_crc->opened = true;
2263         filep->private_data = inode->i_private;
2264
2265         spin_unlock_irq(&pipe_crc->lock);
2266
2267         return 0;
2268 }
2269
2270 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
2271 {
2272         struct pipe_crc_info *info = inode->i_private;
2273         struct drm_i915_private *dev_priv = info->dev->dev_private;
2274         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2275
2276         spin_lock_irq(&pipe_crc->lock);
2277         pipe_crc->opened = false;
2278         spin_unlock_irq(&pipe_crc->lock);
2279
2280         return 0;
2281 }
2282
2283 /* (6 fields, 8 chars each, space separated (5) + '\n') */
2284 #define PIPE_CRC_LINE_LEN       (6 * 8 + 5 + 1)
2285 /* account for \'0' */
2286 #define PIPE_CRC_BUFFER_LEN     (PIPE_CRC_LINE_LEN + 1)
2287
2288 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
2289 {
2290         assert_spin_locked(&pipe_crc->lock);
2291         return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
2292                         INTEL_PIPE_CRC_ENTRIES_NR);
2293 }
2294
2295 static ssize_t
2296 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
2297                    loff_t *pos)
2298 {
2299         struct pipe_crc_info *info = filep->private_data;
2300         struct drm_device *dev = info->dev;
2301         struct drm_i915_private *dev_priv = dev->dev_private;
2302         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
2303         char buf[PIPE_CRC_BUFFER_LEN];
2304         int head, tail, n_entries, n;
2305         ssize_t bytes_read;
2306
2307         /*
2308          * Don't allow user space to provide buffers not big enough to hold
2309          * a line of data.
2310          */
2311         if (count < PIPE_CRC_LINE_LEN)
2312                 return -EINVAL;
2313
2314         if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
2315                 return 0;
2316
2317         /* nothing to read */
2318         spin_lock_irq(&pipe_crc->lock);
2319         while (pipe_crc_data_count(pipe_crc) == 0) {
2320                 int ret;
2321
2322                 if (filep->f_flags & O_NONBLOCK) {
2323                         spin_unlock_irq(&pipe_crc->lock);
2324                         return -EAGAIN;
2325                 }
2326
2327                 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
2328                                 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
2329                 if (ret) {
2330                         spin_unlock_irq(&pipe_crc->lock);
2331                         return ret;
2332                 }
2333         }
2334
2335         /* We now have one or more entries to read */
2336         head = pipe_crc->head;
2337         tail = pipe_crc->tail;
2338         n_entries = min((size_t)CIRC_CNT(head, tail, INTEL_PIPE_CRC_ENTRIES_NR),
2339                         count / PIPE_CRC_LINE_LEN);
2340         spin_unlock_irq(&pipe_crc->lock);
2341
2342         bytes_read = 0;
2343         n = 0;
2344         do {
2345                 struct intel_pipe_crc_entry *entry = &pipe_crc->entries[tail];
2346                 int ret;
2347
2348                 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
2349                                        "%8u %8x %8x %8x %8x %8x\n",
2350                                        entry->frame, entry->crc[0],
2351                                        entry->crc[1], entry->crc[2],
2352                                        entry->crc[3], entry->crc[4]);
2353
2354                 ret = copy_to_user(user_buf + n * PIPE_CRC_LINE_LEN,
2355                                    buf, PIPE_CRC_LINE_LEN);
2356                 if (ret == PIPE_CRC_LINE_LEN)
2357                         return -EFAULT;
2358
2359                 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
2360                 tail = (tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
2361                 n++;
2362         } while (--n_entries);
2363
2364         spin_lock_irq(&pipe_crc->lock);
2365         pipe_crc->tail = tail;
2366         spin_unlock_irq(&pipe_crc->lock);
2367
2368         return bytes_read;
2369 }
2370
2371 static const struct file_operations i915_pipe_crc_fops = {
2372         .owner = THIS_MODULE,
2373         .open = i915_pipe_crc_open,
2374         .read = i915_pipe_crc_read,
2375         .release = i915_pipe_crc_release,
2376 };
2377
2378 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
2379         {
2380                 .name = "i915_pipe_A_crc",
2381                 .pipe = PIPE_A,
2382         },
2383         {
2384                 .name = "i915_pipe_B_crc",
2385                 .pipe = PIPE_B,
2386         },
2387         {
2388                 .name = "i915_pipe_C_crc",
2389                 .pipe = PIPE_C,
2390         },
2391 };
2392
2393 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
2394                                 enum pipe pipe)
2395 {
2396         struct drm_device *dev = minor->dev;
2397         struct dentry *ent;
2398         struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
2399
2400         info->dev = dev;
2401         ent = debugfs_create_file(info->name, S_IRUGO, root, info,
2402                                   &i915_pipe_crc_fops);
2403         if (!ent)
2404                 return -ENOMEM;
2405
2406         return drm_add_fake_info_node(minor, ent, info);
2407 }
2408
2409 static const char * const pipe_crc_sources[] = {
2410         "none",
2411         "plane1",
2412         "plane2",
2413         "pf",
2414         "pipe",
2415         "TV",
2416         "DP-B",
2417         "DP-C",
2418         "DP-D",
2419         "auto",
2420 };
2421
2422 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
2423 {
2424         BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
2425         return pipe_crc_sources[source];
2426 }
2427
2428 static int display_crc_ctl_show(struct seq_file *m, void *data)
2429 {
2430         struct drm_device *dev = m->private;
2431         struct drm_i915_private *dev_priv = dev->dev_private;
2432         int i;
2433
2434         for (i = 0; i < I915_MAX_PIPES; i++)
2435                 seq_printf(m, "%c %s\n", pipe_name(i),
2436                            pipe_crc_source_name(dev_priv->pipe_crc[i].source));
2437
2438         return 0;
2439 }
2440
2441 static int display_crc_ctl_open(struct inode *inode, struct file *file)
2442 {
2443         struct drm_device *dev = inode->i_private;
2444
2445         return single_open(file, display_crc_ctl_show, dev);
2446 }
2447
2448 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
2449                                  uint32_t *val)
2450 {
2451         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2452                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2453
2454         switch (*source) {
2455         case INTEL_PIPE_CRC_SOURCE_PIPE:
2456                 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
2457                 break;
2458         case INTEL_PIPE_CRC_SOURCE_NONE:
2459                 *val = 0;
2460                 break;
2461         default:
2462                 return -EINVAL;
2463         }
2464
2465         return 0;
2466 }
2467
2468 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
2469                                      enum intel_pipe_crc_source *source)
2470 {
2471         struct intel_encoder *encoder;
2472         struct intel_crtc *crtc;
2473         struct intel_digital_port *dig_port;
2474         int ret = 0;
2475
2476         *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2477
2478         mutex_lock(&dev->mode_config.mutex);
2479         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
2480                             base.head) {
2481                 if (!encoder->base.crtc)
2482                         continue;
2483
2484                 crtc = to_intel_crtc(encoder->base.crtc);
2485
2486                 if (crtc->pipe != pipe)
2487                         continue;
2488
2489                 switch (encoder->type) {
2490                 case INTEL_OUTPUT_TVOUT:
2491                         *source = INTEL_PIPE_CRC_SOURCE_TV;
2492                         break;
2493                 case INTEL_OUTPUT_DISPLAYPORT:
2494                 case INTEL_OUTPUT_EDP:
2495                         dig_port = enc_to_dig_port(&encoder->base);
2496                         switch (dig_port->port) {
2497                         case PORT_B:
2498                                 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
2499                                 break;
2500                         case PORT_C:
2501                                 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
2502                                 break;
2503                         case PORT_D:
2504                                 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
2505                                 break;
2506                         default:
2507                                 WARN(1, "nonexisting DP port %c\n",
2508                                      port_name(dig_port->port));
2509                                 break;
2510                         }
2511                         break;
2512                 }
2513         }
2514         mutex_unlock(&dev->mode_config.mutex);
2515
2516         return ret;
2517 }
2518
2519 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
2520                                 enum pipe pipe,
2521                                 enum intel_pipe_crc_source *source,
2522                                 uint32_t *val)
2523 {
2524         struct drm_i915_private *dev_priv = dev->dev_private;
2525         bool need_stable_symbols = false;
2526
2527         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2528                 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2529                 if (ret)
2530                         return ret;
2531         }
2532
2533         switch (*source) {
2534         case INTEL_PIPE_CRC_SOURCE_PIPE:
2535                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
2536                 break;
2537         case INTEL_PIPE_CRC_SOURCE_DP_B:
2538                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
2539                 need_stable_symbols = true;
2540                 break;
2541         case INTEL_PIPE_CRC_SOURCE_DP_C:
2542                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
2543                 need_stable_symbols = true;
2544                 break;
2545         case INTEL_PIPE_CRC_SOURCE_NONE:
2546                 *val = 0;
2547                 break;
2548         default:
2549                 return -EINVAL;
2550         }
2551
2552         /*
2553          * When the pipe CRC tap point is after the transcoders we need
2554          * to tweak symbol-level features to produce a deterministic series of
2555          * symbols for a given frame. We need to reset those features only once
2556          * a frame (instead of every nth symbol):
2557          *   - DC-balance: used to ensure a better clock recovery from the data
2558          *     link (SDVO)
2559          *   - DisplayPort scrambling: used for EMI reduction
2560          */
2561         if (need_stable_symbols) {
2562                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2563
2564                 WARN_ON(!IS_G4X(dev));
2565
2566                 tmp |= DC_BALANCE_RESET_VLV;
2567                 if (pipe == PIPE_A)
2568                         tmp |= PIPE_A_SCRAMBLE_RESET;
2569                 else
2570                         tmp |= PIPE_B_SCRAMBLE_RESET;
2571
2572                 I915_WRITE(PORT_DFT2_G4X, tmp);
2573         }
2574
2575         return 0;
2576 }
2577
2578 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
2579                                  enum pipe pipe,
2580                                  enum intel_pipe_crc_source *source,
2581                                  uint32_t *val)
2582 {
2583         struct drm_i915_private *dev_priv = dev->dev_private;
2584         bool need_stable_symbols = false;
2585
2586         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
2587                 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
2588                 if (ret)
2589                         return ret;
2590         }
2591
2592         switch (*source) {
2593         case INTEL_PIPE_CRC_SOURCE_PIPE:
2594                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
2595                 break;
2596         case INTEL_PIPE_CRC_SOURCE_TV:
2597                 if (!SUPPORTS_TV(dev))
2598                         return -EINVAL;
2599                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
2600                 break;
2601         case INTEL_PIPE_CRC_SOURCE_DP_B:
2602                 if (!IS_G4X(dev))
2603                         return -EINVAL;
2604                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
2605                 need_stable_symbols = true;
2606                 break;
2607         case INTEL_PIPE_CRC_SOURCE_DP_C:
2608                 if (!IS_G4X(dev))
2609                         return -EINVAL;
2610                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
2611                 need_stable_symbols = true;
2612                 break;
2613         case INTEL_PIPE_CRC_SOURCE_DP_D:
2614                 if (!IS_G4X(dev))
2615                         return -EINVAL;
2616                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
2617                 need_stable_symbols = true;
2618                 break;
2619         case INTEL_PIPE_CRC_SOURCE_NONE:
2620                 *val = 0;
2621                 break;
2622         default:
2623                 return -EINVAL;
2624         }
2625
2626         /*
2627          * When the pipe CRC tap point is after the transcoders we need
2628          * to tweak symbol-level features to produce a deterministic series of
2629          * symbols for a given frame. We need to reset those features only once
2630          * a frame (instead of every nth symbol):
2631          *   - DC-balance: used to ensure a better clock recovery from the data
2632          *     link (SDVO)
2633          *   - DisplayPort scrambling: used for EMI reduction
2634          */
2635         if (need_stable_symbols) {
2636                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2637
2638                 WARN_ON(!IS_G4X(dev));
2639
2640                 I915_WRITE(PORT_DFT_I9XX,
2641                            I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
2642
2643                 if (pipe == PIPE_A)
2644                         tmp |= PIPE_A_SCRAMBLE_RESET;
2645                 else
2646                         tmp |= PIPE_B_SCRAMBLE_RESET;
2647
2648                 I915_WRITE(PORT_DFT2_G4X, tmp);
2649         }
2650
2651         return 0;
2652 }
2653
2654 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
2655                                          enum pipe pipe)
2656 {
2657         struct drm_i915_private *dev_priv = dev->dev_private;
2658         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2659
2660         if (pipe == PIPE_A)
2661                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
2662         else
2663                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
2664         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
2665                 tmp &= ~DC_BALANCE_RESET_VLV;
2666         I915_WRITE(PORT_DFT2_G4X, tmp);
2667
2668 }
2669
2670 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
2671                                          enum pipe pipe)
2672 {
2673         struct drm_i915_private *dev_priv = dev->dev_private;
2674         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
2675
2676         if (pipe == PIPE_A)
2677                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
2678         else
2679                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
2680         I915_WRITE(PORT_DFT2_G4X, tmp);
2681
2682         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
2683                 I915_WRITE(PORT_DFT_I9XX,
2684                            I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
2685         }
2686 }
2687
2688 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
2689                                 uint32_t *val)
2690 {
2691         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2692                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
2693
2694         switch (*source) {
2695         case INTEL_PIPE_CRC_SOURCE_PLANE1:
2696                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
2697                 break;
2698         case INTEL_PIPE_CRC_SOURCE_PLANE2:
2699                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
2700                 break;
2701         case INTEL_PIPE_CRC_SOURCE_PIPE:
2702                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
2703                 break;
2704         case INTEL_PIPE_CRC_SOURCE_NONE:
2705                 *val = 0;
2706                 break;
2707         default:
2708                 return -EINVAL;
2709         }
2710
2711         return 0;
2712 }
2713
2714 static int ivb_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
2715                                 uint32_t *val)
2716 {
2717         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
2718                 *source = INTEL_PIPE_CRC_SOURCE_PF;
2719
2720         switch (*source) {
2721         case INTEL_PIPE_CRC_SOURCE_PLANE1:
2722                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
2723                 break;
2724         case INTEL_PIPE_CRC_SOURCE_PLANE2:
2725                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
2726                 break;
2727         case INTEL_PIPE_CRC_SOURCE_PF:
2728                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
2729                 break;
2730         case INTEL_PIPE_CRC_SOURCE_NONE:
2731                 *val = 0;
2732                 break;
2733         default:
2734                 return -EINVAL;
2735         }
2736
2737         return 0;
2738 }
2739
2740 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
2741                                enum intel_pipe_crc_source source)
2742 {
2743         struct drm_i915_private *dev_priv = dev->dev_private;
2744         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
2745         u32 val = 0; /* shut up gcc */
2746         int ret;
2747
2748         if (pipe_crc->source == source)
2749                 return 0;
2750
2751         /* forbid changing the source without going back to 'none' */
2752         if (pipe_crc->source && source)
2753                 return -EINVAL;
2754
2755         if (IS_GEN2(dev))
2756                 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
2757         else if (INTEL_INFO(dev)->gen < 5)
2758                 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
2759         else if (IS_VALLEYVIEW(dev))
2760                 ret = vlv_pipe_crc_ctl_reg(dev,pipe, &source, &val);
2761         else if (IS_GEN5(dev) || IS_GEN6(dev))
2762                 ret = ilk_pipe_crc_ctl_reg(&source, &val);
2763         else
2764                 ret = ivb_pipe_crc_ctl_reg(&source, &val);
2765
2766         if (ret != 0)
2767                 return ret;
2768
2769         /* none -> real source transition */
2770         if (source) {
2771                 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
2772                                  pipe_name(pipe), pipe_crc_source_name(source));
2773
2774                 pipe_crc->entries = kzalloc(sizeof(*pipe_crc->entries) *
2775                                             INTEL_PIPE_CRC_ENTRIES_NR,
2776                                             GFP_KERNEL);
2777                 if (!pipe_crc->entries)
2778                         return -ENOMEM;
2779
2780                 spin_lock_irq(&pipe_crc->lock);
2781                 pipe_crc->head = 0;
2782                 pipe_crc->tail = 0;
2783                 spin_unlock_irq(&pipe_crc->lock);
2784         }
2785
2786         pipe_crc->source = source;
2787
2788         I915_WRITE(PIPE_CRC_CTL(pipe), val);
2789         POSTING_READ(PIPE_CRC_CTL(pipe));
2790
2791         /* real source -> none transition */
2792         if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
2793                 struct intel_pipe_crc_entry *entries;
2794
2795                 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
2796                                  pipe_name(pipe));
2797
2798                 intel_wait_for_vblank(dev, pipe);
2799
2800                 spin_lock_irq(&pipe_crc->lock);
2801                 entries = pipe_crc->entries;
2802                 pipe_crc->entries = NULL;
2803                 spin_unlock_irq(&pipe_crc->lock);
2804
2805                 kfree(entries);
2806
2807                 if (IS_G4X(dev))
2808                         g4x_undo_pipe_scramble_reset(dev, pipe);
2809                 else if (IS_VALLEYVIEW(dev))
2810                         vlv_undo_pipe_scramble_reset(dev, pipe);
2811         }
2812
2813         return 0;
2814 }
2815
2816 /*
2817  * Parse pipe CRC command strings:
2818  *   command: wsp* object wsp+ name wsp+ source wsp*
2819  *   object: 'pipe'
2820  *   name: (A | B | C)
2821  *   source: (none | plane1 | plane2 | pf)
2822  *   wsp: (#0x20 | #0x9 | #0xA)+
2823  *
2824  * eg.:
2825  *  "pipe A plane1"  ->  Start CRC computations on plane1 of pipe A
2826  *  "pipe A none"    ->  Stop CRC
2827  */
2828 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
2829 {
2830         int n_words = 0;
2831
2832         while (*buf) {
2833                 char *end;
2834
2835                 /* skip leading white space */
2836                 buf = skip_spaces(buf);
2837                 if (!*buf)
2838                         break;  /* end of buffer */
2839
2840                 /* find end of word */
2841                 for (end = buf; *end && !isspace(*end); end++)
2842                         ;
2843
2844                 if (n_words == max_words) {
2845                         DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
2846                                          max_words);
2847                         return -EINVAL; /* ran out of words[] before bytes */
2848                 }
2849
2850                 if (*end)
2851                         *end++ = '\0';
2852                 words[n_words++] = buf;
2853                 buf = end;
2854         }
2855
2856         return n_words;
2857 }
2858
2859 enum intel_pipe_crc_object {
2860         PIPE_CRC_OBJECT_PIPE,
2861 };
2862
2863 static const char * const pipe_crc_objects[] = {
2864         "pipe",
2865 };
2866
2867 static int
2868 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
2869 {
2870         int i;
2871
2872         for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
2873                 if (!strcmp(buf, pipe_crc_objects[i])) {
2874                         *o = i;
2875                         return 0;
2876                     }
2877
2878         return -EINVAL;
2879 }
2880
2881 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
2882 {
2883         const char name = buf[0];
2884
2885         if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
2886                 return -EINVAL;
2887
2888         *pipe = name - 'A';
2889
2890         return 0;
2891 }
2892
2893 static int
2894 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
2895 {
2896         int i;
2897
2898         for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
2899                 if (!strcmp(buf, pipe_crc_sources[i])) {
2900                         *s = i;
2901                         return 0;
2902                     }
2903
2904         return -EINVAL;
2905 }
2906
2907 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
2908 {
2909 #define N_WORDS 3
2910         int n_words;
2911         char *words[N_WORDS];
2912         enum pipe pipe;
2913         enum intel_pipe_crc_object object;
2914         enum intel_pipe_crc_source source;
2915
2916         n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
2917         if (n_words != N_WORDS) {
2918                 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
2919                                  N_WORDS);
2920                 return -EINVAL;
2921         }
2922
2923         if (display_crc_ctl_parse_object(words[0], &object) < 0) {
2924                 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
2925                 return -EINVAL;
2926         }
2927
2928         if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
2929                 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
2930                 return -EINVAL;
2931         }
2932
2933         if (display_crc_ctl_parse_source(words[2], &source) < 0) {
2934                 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
2935                 return -EINVAL;
2936         }
2937
2938         return pipe_crc_set_source(dev, pipe, source);
2939 }
2940
2941 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
2942                                      size_t len, loff_t *offp)
2943 {
2944         struct seq_file *m = file->private_data;
2945         struct drm_device *dev = m->private;
2946         char *tmpbuf;
2947         int ret;
2948
2949         if (len == 0)
2950                 return 0;
2951
2952         if (len > PAGE_SIZE - 1) {
2953                 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
2954                                  PAGE_SIZE);
2955                 return -E2BIG;
2956         }
2957
2958         tmpbuf = kmalloc(len + 1, GFP_KERNEL);
2959         if (!tmpbuf)
2960                 return -ENOMEM;
2961
2962         if (copy_from_user(tmpbuf, ubuf, len)) {
2963                 ret = -EFAULT;
2964                 goto out;
2965         }
2966         tmpbuf[len] = '\0';
2967
2968         ret = display_crc_ctl_parse(dev, tmpbuf, len);
2969
2970 out:
2971         kfree(tmpbuf);
2972         if (ret < 0)
2973                 return ret;
2974
2975         *offp += len;
2976         return len;
2977 }
2978
2979 static const struct file_operations i915_display_crc_ctl_fops = {
2980         .owner = THIS_MODULE,
2981         .open = display_crc_ctl_open,
2982         .read = seq_read,
2983         .llseek = seq_lseek,
2984         .release = single_release,
2985         .write = display_crc_ctl_write
2986 };
2987
2988 static void wm_latency_show(struct seq_file *m, const uint16_t wm[5])
2989 {
2990         struct drm_device *dev = m->private;
2991         int num_levels = IS_HASWELL(dev) || IS_BROADWELL(dev) ? 5 : 4;
2992         int level;
2993
2994         drm_modeset_lock_all(dev);
2995
2996         for (level = 0; level < num_levels; level++) {
2997                 unsigned int latency = wm[level];
2998
2999                 /* WM1+ latency values in 0.5us units */
3000                 if (level > 0)
3001                         latency *= 5;
3002
3003                 seq_printf(m, "WM%d %u (%u.%u usec)\n",
3004                            level, wm[level],
3005                            latency / 10, latency % 10);
3006         }
3007
3008         drm_modeset_unlock_all(dev);
3009 }
3010
3011 static int pri_wm_latency_show(struct seq_file *m, void *data)
3012 {
3013         struct drm_device *dev = m->private;
3014
3015         wm_latency_show(m, to_i915(dev)->wm.pri_latency);
3016
3017         return 0;
3018 }
3019
3020 static int spr_wm_latency_show(struct seq_file *m, void *data)
3021 {
3022         struct drm_device *dev = m->private;
3023
3024         wm_latency_show(m, to_i915(dev)->wm.spr_latency);
3025
3026         return 0;
3027 }
3028
3029 static int cur_wm_latency_show(struct seq_file *m, void *data)
3030 {
3031         struct drm_device *dev = m->private;
3032
3033         wm_latency_show(m, to_i915(dev)->wm.cur_latency);
3034
3035         return 0;
3036 }
3037
3038 static int pri_wm_latency_open(struct inode *inode, struct file *file)
3039 {
3040         struct drm_device *dev = inode->i_private;
3041
3042         if (!HAS_PCH_SPLIT(dev))
3043                 return -ENODEV;
3044
3045         return single_open(file, pri_wm_latency_show, dev);
3046 }
3047
3048 static int spr_wm_latency_open(struct inode *inode, struct file *file)
3049 {
3050         struct drm_device *dev = inode->i_private;
3051
3052         if (!HAS_PCH_SPLIT(dev))
3053                 return -ENODEV;
3054
3055         return single_open(file, spr_wm_latency_show, dev);
3056 }
3057
3058 static int cur_wm_latency_open(struct inode *inode, struct file *file)
3059 {
3060         struct drm_device *dev = inode->i_private;
3061
3062         if (!HAS_PCH_SPLIT(dev))
3063                 return -ENODEV;
3064
3065         return single_open(file, cur_wm_latency_show, dev);
3066 }
3067
3068 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
3069                                 size_t len, loff_t *offp, uint16_t wm[5])
3070 {
3071         struct seq_file *m = file->private_data;
3072         struct drm_device *dev = m->private;
3073         uint16_t new[5] = { 0 };
3074         int num_levels = IS_HASWELL(dev) || IS_BROADWELL(dev) ? 5 : 4;
3075         int level;
3076         int ret;
3077         char tmp[32];
3078
3079         if (len >= sizeof(tmp))
3080                 return -EINVAL;
3081
3082         if (copy_from_user(tmp, ubuf, len))
3083                 return -EFAULT;
3084
3085         tmp[len] = '\0';
3086
3087         ret = sscanf(tmp, "%hu %hu %hu %hu %hu", &new[0], &new[1], &new[2], &new[3], &new[4]);
3088         if (ret != num_levels)
3089                 return -EINVAL;
3090
3091         drm_modeset_lock_all(dev);
3092
3093         for (level = 0; level < num_levels; level++)
3094                 wm[level] = new[level];
3095
3096         drm_modeset_unlock_all(dev);
3097
3098         return len;
3099 }
3100
3101
3102 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
3103                                     size_t len, loff_t *offp)
3104 {
3105         struct seq_file *m = file->private_data;
3106         struct drm_device *dev = m->private;
3107
3108         return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.pri_latency);
3109 }
3110
3111 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
3112                                     size_t len, loff_t *offp)
3113 {
3114         struct seq_file *m = file->private_data;
3115         struct drm_device *dev = m->private;
3116
3117         return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.spr_latency);
3118 }
3119
3120 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
3121                                     size_t len, loff_t *offp)
3122 {
3123         struct seq_file *m = file->private_data;
3124         struct drm_device *dev = m->private;
3125
3126         return wm_latency_write(file, ubuf, len, offp, to_i915(dev)->wm.cur_latency);
3127 }
3128
3129 static const struct file_operations i915_pri_wm_latency_fops = {
3130         .owner = THIS_MODULE,
3131         .open = pri_wm_latency_open,
3132         .read = seq_read,
3133         .llseek = seq_lseek,
3134         .release = single_release,
3135         .write = pri_wm_latency_write
3136 };
3137
3138 static const struct file_operations i915_spr_wm_latency_fops = {
3139         .owner = THIS_MODULE,
3140         .open = spr_wm_latency_open,
3141         .read = seq_read,
3142         .llseek = seq_lseek,
3143         .release = single_release,
3144         .write = spr_wm_latency_write
3145 };
3146
3147 static const struct file_operations i915_cur_wm_latency_fops = {
3148         .owner = THIS_MODULE,
3149         .open = cur_wm_latency_open,
3150         .read = seq_read,
3151         .llseek = seq_lseek,
3152         .release = single_release,
3153         .write = cur_wm_latency_write
3154 };
3155
3156 static int
3157 i915_wedged_get(void *data, u64 *val)
3158 {
3159         struct drm_device *dev = data;
3160         drm_i915_private_t *dev_priv = dev->dev_private;
3161
3162         *val = atomic_read(&dev_priv->gpu_error.reset_counter);
3163
3164         return 0;
3165 }
3166
3167 static int
3168 i915_wedged_set(void *data, u64 val)
3169 {
3170         struct drm_device *dev = data;
3171
3172         DRM_INFO("Manually setting wedged to %llu\n", val);
3173         i915_handle_error(dev, val);
3174
3175         return 0;
3176 }
3177
3178 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
3179                         i915_wedged_get, i915_wedged_set,
3180                         "%llu\n");
3181
3182 static int
3183 i915_ring_stop_get(void *data, u64 *val)
3184 {
3185         struct drm_device *dev = data;
3186         drm_i915_private_t *dev_priv = dev->dev_private;
3187
3188         *val = dev_priv->gpu_error.stop_rings;
3189
3190         return 0;
3191 }
3192
3193 static int
3194 i915_ring_stop_set(void *data, u64 val)
3195 {
3196         struct drm_device *dev = data;
3197         struct drm_i915_private *dev_priv = dev->dev_private;
3198         int ret;
3199
3200         DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
3201
3202         ret = mutex_lock_interruptible(&dev->struct_mutex);
3203         if (ret)
3204                 return ret;
3205
3206         dev_priv->gpu_error.stop_rings = val;
3207         mutex_unlock(&dev->struct_mutex);
3208
3209         return 0;
3210 }
3211
3212 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
3213                         i915_ring_stop_get, i915_ring_stop_set,
3214                         "0x%08llx\n");
3215
3216 static int
3217 i915_ring_missed_irq_get(void *data, u64 *val)
3218 {
3219         struct drm_device *dev = data;
3220         struct drm_i915_private *dev_priv = dev->dev_private;
3221
3222         *val = dev_priv->gpu_error.missed_irq_rings;
3223         return 0;
3224 }
3225
3226 static int
3227 i915_ring_missed_irq_set(void *data, u64 val)
3228 {
3229         struct drm_device *dev = data;
3230         struct drm_i915_private *dev_priv = dev->dev_private;
3231         int ret;
3232
3233         /* Lock against concurrent debugfs callers */
3234         ret = mutex_lock_interruptible(&dev->struct_mutex);
3235         if (ret)
3236                 return ret;
3237         dev_priv->gpu_error.missed_irq_rings = val;
3238         mutex_unlock(&dev->struct_mutex);
3239
3240         return 0;
3241 }
3242
3243 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
3244                         i915_ring_missed_irq_get, i915_ring_missed_irq_set,
3245                         "0x%08llx\n");
3246
3247 static int
3248 i915_ring_test_irq_get(void *data, u64 *val)
3249 {
3250         struct drm_device *dev = data;
3251         struct drm_i915_private *dev_priv = dev->dev_private;
3252
3253         *val = dev_priv->gpu_error.test_irq_rings;
3254
3255         return 0;
3256 }
3257
3258 static int
3259 i915_ring_test_irq_set(void *data, u64 val)
3260 {
3261         struct drm_device *dev = data;
3262         struct drm_i915_private *dev_priv = dev->dev_private;
3263         int ret;
3264
3265         DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
3266
3267         /* Lock against concurrent debugfs callers */
3268         ret = mutex_lock_interruptible(&dev->struct_mutex);
3269         if (ret)
3270                 return ret;
3271
3272         dev_priv->gpu_error.test_irq_rings = val;
3273         mutex_unlock(&dev->struct_mutex);
3274
3275         return 0;
3276 }
3277
3278 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
3279                         i915_ring_test_irq_get, i915_ring_test_irq_set,
3280                         "0x%08llx\n");
3281
3282 #define DROP_UNBOUND 0x1
3283 #define DROP_BOUND 0x2
3284 #define DROP_RETIRE 0x4
3285 #define DROP_ACTIVE 0x8
3286 #define DROP_ALL (DROP_UNBOUND | \
3287                   DROP_BOUND | \
3288                   DROP_RETIRE | \
3289                   DROP_ACTIVE)
3290 static int
3291 i915_drop_caches_get(void *data, u64 *val)
3292 {
3293         *val = DROP_ALL;
3294
3295         return 0;
3296 }
3297
3298 static int
3299 i915_drop_caches_set(void *data, u64 val)
3300 {
3301         struct drm_device *dev = data;
3302         struct drm_i915_private *dev_priv = dev->dev_private;
3303         struct drm_i915_gem_object *obj, *next;
3304         struct i915_address_space *vm;
3305         struct i915_vma *vma, *x;
3306         int ret;
3307
3308         DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
3309
3310         /* No need to check and wait for gpu resets, only libdrm auto-restarts
3311          * on ioctls on -EAGAIN. */
3312         ret = mutex_lock_interruptible(&dev->struct_mutex);
3313         if (ret)
3314                 return ret;
3315
3316         if (val & DROP_ACTIVE) {
3317                 ret = i915_gpu_idle(dev);
3318                 if (ret)
3319                         goto unlock;
3320         }
3321
3322         if (val & (DROP_RETIRE | DROP_ACTIVE))
3323                 i915_gem_retire_requests(dev);
3324
3325         if (val & DROP_BOUND) {
3326                 list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
3327                         list_for_each_entry_safe(vma, x, &vm->inactive_list,
3328                                                  mm_list) {
3329                                 if (vma->pin_count)
3330                                         continue;
3331
3332                                 ret = i915_vma_unbind(vma);
3333                                 if (ret)
3334                                         goto unlock;
3335                         }
3336                 }
3337         }
3338
3339         if (val & DROP_UNBOUND) {
3340                 list_for_each_entry_safe(obj, next, &dev_priv->mm.unbound_list,
3341                                          global_list)
3342                         if (obj->pages_pin_count == 0) {
3343                                 ret = i915_gem_object_put_pages(obj);
3344                                 if (ret)
3345                                         goto unlock;
3346                         }
3347         }
3348
3349 unlock:
3350         mutex_unlock(&dev->struct_mutex);
3351
3352         return ret;
3353 }
3354
3355 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
3356                         i915_drop_caches_get, i915_drop_caches_set,
3357                         "0x%08llx\n");
3358
3359 static int
3360 i915_max_freq_get(void *data, u64 *val)
3361 {
3362         struct drm_device *dev = data;
3363         drm_i915_private_t *dev_priv = dev->dev_private;
3364         int ret;
3365
3366         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3367                 return -ENODEV;
3368
3369         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3370
3371         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
3372         if (ret)
3373                 return ret;
3374
3375         if (IS_VALLEYVIEW(dev))
3376                 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_delay);
3377         else
3378                 *val = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER;
3379         mutex_unlock(&dev_priv->rps.hw_lock);
3380
3381         return 0;
3382 }
3383
3384 static int
3385 i915_max_freq_set(void *data, u64 val)
3386 {
3387         struct drm_device *dev = data;
3388         struct drm_i915_private *dev_priv = dev->dev_private;
3389         u32 rp_state_cap, hw_max, hw_min;
3390         int ret;
3391
3392         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3393                 return -ENODEV;
3394
3395         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3396
3397         DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
3398
3399         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
3400         if (ret)
3401                 return ret;
3402
3403         /*
3404          * Turbo will still be enabled, but won't go above the set value.
3405          */
3406         if (IS_VALLEYVIEW(dev)) {
3407                 val = vlv_freq_opcode(dev_priv, val);
3408
3409                 hw_max = valleyview_rps_max_freq(dev_priv);
3410                 hw_min = valleyview_rps_min_freq(dev_priv);
3411         } else {
3412                 do_div(val, GT_FREQUENCY_MULTIPLIER);
3413
3414                 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3415                 hw_max = dev_priv->rps.hw_max;
3416                 hw_min = (rp_state_cap >> 16) & 0xff;
3417         }
3418
3419         if (val < hw_min || val > hw_max || val < dev_priv->rps.min_delay) {
3420                 mutex_unlock(&dev_priv->rps.hw_lock);
3421                 return -EINVAL;
3422         }
3423
3424         dev_priv->rps.max_delay = val;
3425
3426         if (IS_VALLEYVIEW(dev))
3427                 valleyview_set_rps(dev, val);
3428         else
3429                 gen6_set_rps(dev, val);
3430
3431         mutex_unlock(&dev_priv->rps.hw_lock);
3432
3433         return 0;
3434 }
3435
3436 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
3437                         i915_max_freq_get, i915_max_freq_set,
3438                         "%llu\n");
3439
3440 static int
3441 i915_min_freq_get(void *data, u64 *val)
3442 {
3443         struct drm_device *dev = data;
3444         drm_i915_private_t *dev_priv = dev->dev_private;
3445         int ret;
3446
3447         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3448                 return -ENODEV;
3449
3450         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3451
3452         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
3453         if (ret)
3454                 return ret;
3455
3456         if (IS_VALLEYVIEW(dev))
3457                 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_delay);
3458         else
3459                 *val = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER;
3460         mutex_unlock(&dev_priv->rps.hw_lock);
3461
3462         return 0;
3463 }
3464
3465 static int
3466 i915_min_freq_set(void *data, u64 val)
3467 {
3468         struct drm_device *dev = data;
3469         struct drm_i915_private *dev_priv = dev->dev_private;
3470         u32 rp_state_cap, hw_max, hw_min;
3471         int ret;
3472
3473         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3474                 return -ENODEV;
3475
3476         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
3477
3478         DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
3479
3480         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
3481         if (ret)
3482                 return ret;
3483
3484         /*
3485          * Turbo will still be enabled, but won't go below the set value.
3486          */
3487         if (IS_VALLEYVIEW(dev)) {
3488                 val = vlv_freq_opcode(dev_priv, val);
3489
3490                 hw_max = valleyview_rps_max_freq(dev_priv);
3491                 hw_min = valleyview_rps_min_freq(dev_priv);
3492         } else {
3493                 do_div(val, GT_FREQUENCY_MULTIPLIER);
3494
3495                 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3496                 hw_max = dev_priv->rps.hw_max;
3497                 hw_min = (rp_state_cap >> 16) & 0xff;
3498         }
3499
3500         if (val < hw_min || val > hw_max || val > dev_priv->rps.max_delay) {
3501                 mutex_unlock(&dev_priv->rps.hw_lock);
3502                 return -EINVAL;
3503         }
3504
3505         dev_priv->rps.min_delay = val;
3506
3507         if (IS_VALLEYVIEW(dev))
3508                 valleyview_set_rps(dev, val);
3509         else
3510                 gen6_set_rps(dev, val);
3511
3512         mutex_unlock(&dev_priv->rps.hw_lock);
3513
3514         return 0;
3515 }
3516
3517 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
3518                         i915_min_freq_get, i915_min_freq_set,
3519                         "%llu\n");
3520
3521 static int
3522 i915_cache_sharing_get(void *data, u64 *val)
3523 {
3524         struct drm_device *dev = data;
3525         drm_i915_private_t *dev_priv = dev->dev_private;
3526         u32 snpcr;
3527         int ret;
3528
3529         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3530                 return -ENODEV;
3531
3532         ret = mutex_lock_interruptible(&dev->struct_mutex);
3533         if (ret)
3534                 return ret;
3535         intel_runtime_pm_get(dev_priv);
3536
3537         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
3538
3539         intel_runtime_pm_put(dev_priv);
3540         mutex_unlock(&dev_priv->dev->struct_mutex);
3541
3542         *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
3543
3544         return 0;
3545 }
3546
3547 static int
3548 i915_cache_sharing_set(void *data, u64 val)
3549 {
3550         struct drm_device *dev = data;
3551         struct drm_i915_private *dev_priv = dev->dev_private;
3552         u32 snpcr;
3553
3554         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
3555                 return -ENODEV;
3556
3557         if (val > 3)
3558                 return -EINVAL;
3559
3560         intel_runtime_pm_get(dev_priv);
3561         DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
3562
3563         /* Update the cache sharing policy here as well */
3564         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
3565         snpcr &= ~GEN6_MBC_SNPCR_MASK;
3566         snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
3567         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3568
3569         intel_runtime_pm_put(dev_priv);
3570         return 0;
3571 }
3572
3573 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
3574                         i915_cache_sharing_get, i915_cache_sharing_set,
3575                         "%llu\n");
3576
3577 static int i915_forcewake_open(struct inode *inode, struct file *file)
3578 {
3579         struct drm_device *dev = inode->i_private;
3580         struct drm_i915_private *dev_priv = dev->dev_private;
3581
3582         if (INTEL_INFO(dev)->gen < 6)
3583                 return 0;
3584
3585         intel_runtime_pm_get(dev_priv);
3586         gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3587
3588         return 0;
3589 }
3590
3591 static int i915_forcewake_release(struct inode *inode, struct file *file)
3592 {
3593         struct drm_device *dev = inode->i_private;
3594         struct drm_i915_private *dev_priv = dev->dev_private;
3595
3596         if (INTEL_INFO(dev)->gen < 6)
3597                 return 0;
3598
3599         gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3600         intel_runtime_pm_put(dev_priv);
3601
3602         return 0;
3603 }
3604
3605 static const struct file_operations i915_forcewake_fops = {
3606         .owner = THIS_MODULE,
3607         .open = i915_forcewake_open,
3608         .release = i915_forcewake_release,
3609 };
3610
3611 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
3612 {
3613         struct drm_device *dev = minor->dev;
3614         struct dentry *ent;
3615
3616         ent = debugfs_create_file("i915_forcewake_user",
3617                                   S_IRUSR,
3618                                   root, dev,
3619                                   &i915_forcewake_fops);
3620         if (!ent)
3621                 return -ENOMEM;
3622
3623         return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
3624 }
3625
3626 static int i915_debugfs_create(struct dentry *root,
3627                                struct drm_minor *minor,
3628                                const char *name,
3629                                const struct file_operations *fops)
3630 {
3631         struct drm_device *dev = minor->dev;
3632         struct dentry *ent;
3633
3634         ent = debugfs_create_file(name,
3635                                   S_IRUGO | S_IWUSR,
3636                                   root, dev,
3637                                   fops);
3638         if (!ent)
3639                 return -ENOMEM;
3640
3641         return drm_add_fake_info_node(minor, ent, fops);
3642 }
3643
3644 static const struct drm_info_list i915_debugfs_list[] = {
3645         {"i915_capabilities", i915_capabilities, 0},
3646         {"i915_gem_objects", i915_gem_object_info, 0},
3647         {"i915_gem_gtt", i915_gem_gtt_info, 0},
3648         {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
3649         {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
3650         {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
3651         {"i915_gem_stolen", i915_gem_stolen_list_info },
3652         {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
3653         {"i915_gem_request", i915_gem_request_info, 0},
3654         {"i915_gem_seqno", i915_gem_seqno_info, 0},
3655         {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
3656         {"i915_gem_interrupt", i915_interrupt_info, 0},
3657         {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
3658         {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
3659         {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
3660         {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
3661         {"i915_rstdby_delays", i915_rstdby_delays, 0},
3662         {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
3663         {"i915_delayfreq_table", i915_delayfreq_table, 0},
3664         {"i915_inttoext_table", i915_inttoext_table, 0},
3665         {"i915_drpc_info", i915_drpc_info, 0},
3666         {"i915_emon_status", i915_emon_status, 0},
3667         {"i915_ring_freq_table", i915_ring_freq_table, 0},
3668         {"i915_gfxec", i915_gfxec, 0},
3669         {"i915_fbc_status", i915_fbc_status, 0},
3670         {"i915_ips_status", i915_ips_status, 0},
3671         {"i915_sr_status", i915_sr_status, 0},
3672         {"i915_opregion", i915_opregion, 0},
3673         {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
3674         {"i915_context_status", i915_context_status, 0},
3675         {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
3676         {"i915_swizzle_info", i915_swizzle_info, 0},
3677         {"i915_ppgtt_info", i915_ppgtt_info, 0},
3678         {"i915_dpio", i915_dpio_info, 0},
3679         {"i915_llc", i915_llc, 0},
3680         {"i915_edp_psr_status", i915_edp_psr_status, 0},
3681         {"i915_sink_crc_eDP1", i915_sink_crc, 0},
3682         {"i915_energy_uJ", i915_energy_uJ, 0},
3683         {"i915_pc8_status", i915_pc8_status, 0},
3684         {"i915_power_domain_info", i915_power_domain_info, 0},
3685         {"i915_display_info", i915_display_info, 0},
3686 };
3687 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
3688
3689 static const struct i915_debugfs_files {
3690         const char *name;
3691         const struct file_operations *fops;
3692 } i915_debugfs_files[] = {
3693         {"i915_wedged", &i915_wedged_fops},
3694         {"i915_max_freq", &i915_max_freq_fops},
3695         {"i915_min_freq", &i915_min_freq_fops},
3696         {"i915_cache_sharing", &i915_cache_sharing_fops},
3697         {"i915_ring_stop", &i915_ring_stop_fops},
3698         {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
3699         {"i915_ring_test_irq", &i915_ring_test_irq_fops},
3700         {"i915_gem_drop_caches", &i915_drop_caches_fops},
3701         {"i915_error_state", &i915_error_state_fops},
3702         {"i915_next_seqno", &i915_next_seqno_fops},
3703         {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
3704         {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
3705         {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
3706         {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
3707 };
3708
3709 void intel_display_crc_init(struct drm_device *dev)
3710 {
3711         struct drm_i915_private *dev_priv = dev->dev_private;
3712         enum pipe pipe;
3713
3714         for_each_pipe(pipe) {
3715                 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
3716
3717                 pipe_crc->opened = false;
3718                 spin_lock_init(&pipe_crc->lock);
3719                 init_waitqueue_head(&pipe_crc->wq);
3720         }
3721 }
3722
3723 int i915_debugfs_init(struct drm_minor *minor)
3724 {
3725         int ret, i;
3726
3727         ret = i915_forcewake_create(minor->debugfs_root, minor);
3728         if (ret)
3729                 return ret;
3730
3731         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
3732                 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
3733                 if (ret)
3734                         return ret;
3735         }
3736
3737         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
3738                 ret = i915_debugfs_create(minor->debugfs_root, minor,
3739                                           i915_debugfs_files[i].name,
3740                                           i915_debugfs_files[i].fops);
3741                 if (ret)
3742                         return ret;
3743         }
3744
3745         return drm_debugfs_create_files(i915_debugfs_list,
3746                                         I915_DEBUGFS_ENTRIES,
3747                                         minor->debugfs_root, minor);
3748 }
3749
3750 void i915_debugfs_cleanup(struct drm_minor *minor)
3751 {
3752         int i;
3753
3754         drm_debugfs_remove_files(i915_debugfs_list,
3755                                  I915_DEBUGFS_ENTRIES, minor);
3756
3757         drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
3758                                  1, minor);
3759
3760         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
3761                 struct drm_info_list *info_list =
3762                         (struct drm_info_list *)&i915_pipe_crc_data[i];
3763
3764                 drm_debugfs_remove_files(info_list, 1, minor);
3765         }
3766
3767         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
3768                 struct drm_info_list *info_list =
3769                         (struct drm_info_list *) i915_debugfs_files[i].fops;
3770
3771                 drm_debugfs_remove_files(info_list, 1, minor);
3772         }
3773 }