drivers/gpu/drm/i915/i915_debugfs.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *
  27  */
  28
  29 #include <linux/seq_file.h>
  30 #include <linux/circ_buf.h>
  31 #include <linux/ctype.h>
  32 #include <linux/debugfs.h>
  33 #include <linux/slab.h>
  34 #include <linux/export.h>
  35 #include <linux/list_sort.h>
  36 #include <asm/msr-index.h>
  37 #include <drm/drmP.h>
  38 #include "intel_drv.h"
  39 #include "intel_ringbuffer.h"
  40 #include <drm/i915_drm.h>
  41 #include "i915_drv.h"
  42
  43 enum {
  44         ACTIVE_LIST,
  45         INACTIVE_LIST,
  46         PINNED_LIST,
  47 };
  48
  49 /* As the drm_debugfs_init() routines are called before dev->dev_private is
  50  * allocated we need to hook into the minor for release. */
  51 static int
  52 drm_add_fake_info_node(struct drm_minor *minor,
  53                        struct dentry *ent,
  54                        const void *key)
  55 {
  56         struct drm_info_node *node;
  57
  58         node = kmalloc(sizeof(*node), GFP_KERNEL);
  59         if (node == NULL) {
  60                 debugfs_remove(ent);
  61                 return -ENOMEM;
  62         }
  63
  64         node->minor = minor;
  65         node->dent = ent;
  66         node->info_ent = (void *) key;
  67
  68         mutex_lock(&minor->debugfs_lock);
  69         list_add(&node->list, &minor->debugfs_list);
  70         mutex_unlock(&minor->debugfs_lock);
  71
  72         return 0;
  73 }
  74
  75 static int i915_capabilities(struct seq_file *m, void *data)
  76 {
  77         struct drm_info_node *node = m->private;
  78         struct drm_device *dev = node->minor->dev;
  79         const struct intel_device_info *info = INTEL_INFO(dev);
  80
  81         seq_printf(m, "gen: %d\n", info->gen);
  82         seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
  83 #define PRINT_FLAG(x)  seq_printf(m, #x ": %s\n", yesno(info->x))
  84 #define SEP_SEMICOLON ;
  85         DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
  86 #undef PRINT_FLAG
  87 #undef SEP_SEMICOLON
  88
  89         return 0;
  90 }
  91
  92 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
  93 {
  94         if (obj->pin_display)
  95                 return "p";
  96         else
  97                 return " ";
  98 }
  99
 100 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
 101 {
 102         switch (obj->tiling_mode) {
 103         default:
 104         case I915_TILING_NONE: return " ";
 105         case I915_TILING_X: return "X";
 106         case I915_TILING_Y: return "Y";
 107         }
 108 }
 109
 110 static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
 111 {
 112         return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
 113 }
 114
 115 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
 116 {
 117         u64 size = 0;
 118         struct i915_vma *vma;
 119
 120         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 121                 if (vma->is_ggtt && drm_mm_node_allocated(&vma->node))
 122                         size += vma->node.size;
 123         }
 124
 125         return size;
 126 }
 127
 128 static void
 129 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
 130 {
 131         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
 132         struct intel_engine_cs *engine;
 133         struct i915_vma *vma;
 134         int pin_count = 0;
 135         enum intel_engine_id id;
 136
 137         lockdep_assert_held(&obj->base.dev->struct_mutex);
 138
 139         seq_printf(m, "%pK: %s%s%s%s %8zdKiB %02x %02x [ ",
 140                    &obj->base,
 141                    obj->active ? "*" : " ",
 142                    get_pin_flag(obj),
 143                    get_tiling_flag(obj),
 144                    get_global_flag(obj),
 145                    obj->base.size / 1024,
 146                    obj->base.read_domains,
 147                    obj->base.write_domain);
 148         for_each_engine_id(engine, dev_priv, id)
 149                 seq_printf(m, "%x ",
 150                                 i915_gem_request_get_seqno(obj->last_read_req[id]));
 151         seq_printf(m, "] %x %x%s%s%s",
 152                    i915_gem_request_get_seqno(obj->last_write_req),
 153                    i915_gem_request_get_seqno(obj->last_fenced_req),
 154                    i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
 155                    obj->dirty ? " dirty" : "",
 156                    obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
 157         if (obj->base.name)
 158                 seq_printf(m, " (name: %d)", obj->base.name);
 159         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 160                 if (vma->pin_count > 0)
 161                         pin_count++;
 162         }
 163         seq_printf(m, " (pinned x %d)", pin_count);
 164         if (obj->pin_display)
 165                 seq_printf(m, " (display)");
 166         if (obj->fence_reg != I915_FENCE_REG_NONE)
 167                 seq_printf(m, " (fence: %d)", obj->fence_reg);
 168         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 169                 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
 170                            vma->is_ggtt ? "g" : "pp",
 171                            vma->node.start, vma->node.size);
 172                 if (vma->is_ggtt)
 173                         seq_printf(m, ", type: %u", vma->ggtt_view.type);
 174                 seq_puts(m, ")");
 175         }
 176         if (obj->stolen)
 177                 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
 178         if (obj->pin_display || obj->fault_mappable) {
 179                 char s[3], *t = s;
 180                 if (obj->pin_display)
 181                         *t++ = 'p';
 182                 if (obj->fault_mappable)
 183                         *t++ = 'f';
 184                 *t = '\0';
 185                 seq_printf(m, " (%s mappable)", s);
 186         }
 187         if (obj->last_write_req != NULL)
 188                 seq_printf(m, " (%s)",
 189                            i915_gem_request_get_engine(obj->last_write_req)->name);
 190         if (obj->frontbuffer_bits)
 191                 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
 192 }
 193
 194 static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
 195 {
 196         seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
 197         seq_putc(m, ctx->remap_slice ? 'R' : 'r');
 198         seq_putc(m, ' ');
 199 }
 200
 201 static int i915_gem_object_list_info(struct seq_file *m, void *data)
 202 {
 203         struct drm_info_node *node = m->private;
 204         uintptr_t list = (uintptr_t) node->info_ent->data;
 205         struct list_head *head;
 206         struct drm_device *dev = node->minor->dev;
 207         struct drm_i915_private *dev_priv = to_i915(dev);
 208         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 209         struct i915_vma *vma;
 210         u64 total_obj_size, total_gtt_size;
 211         int count, ret;
 212
 213         ret = mutex_lock_interruptible(&dev->struct_mutex);
 214         if (ret)
 215                 return ret;
 216
 217         /* FIXME: the user of this interface might want more than just GGTT */
 218         switch (list) {
 219         case ACTIVE_LIST:
 220                 seq_puts(m, "Active:\n");
 221                 head = &ggtt->base.active_list;
 222                 break;
 223         case INACTIVE_LIST:
 224                 seq_puts(m, "Inactive:\n");
 225                 head = &ggtt->base.inactive_list;
 226                 break;
 227         default:
 228                 mutex_unlock(&dev->struct_mutex);
 229                 return -EINVAL;
 230         }
 231
 232         total_obj_size = total_gtt_size = count = 0;
 233         list_for_each_entry(vma, head, vm_link) {
 234                 seq_printf(m, "   ");
 235                 describe_obj(m, vma->obj);
 236                 seq_printf(m, "\n");
 237                 total_obj_size += vma->obj->base.size;
 238                 total_gtt_size += vma->node.size;
 239                 count++;
 240         }
 241         mutex_unlock(&dev->struct_mutex);
 242
 243         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 244                    count, total_obj_size, total_gtt_size);
 245         return 0;
 246 }
 247
 248 static int obj_rank_by_stolen(void *priv,
 249                               struct list_head *A, struct list_head *B)
 250 {
 251         struct drm_i915_gem_object *a =
 252                 container_of(A, struct drm_i915_gem_object, obj_exec_link);
 253         struct drm_i915_gem_object *b =
 254                 container_of(B, struct drm_i915_gem_object, obj_exec_link);
 255
 256         if (a->stolen->start < b->stolen->start)
 257                 return -1;
 258         if (a->stolen->start > b->stolen->start)
 259                 return 1;
 260         return 0;
 261 }
 262
 263 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
 264 {
 265         struct drm_info_node *node = m->private;
 266         struct drm_device *dev = node->minor->dev;
 267         struct drm_i915_private *dev_priv = dev->dev_private;
 268         struct drm_i915_gem_object *obj;
 269         u64 total_obj_size, total_gtt_size;
 270         LIST_HEAD(stolen);
 271         int count, ret;
 272
 273         ret = mutex_lock_interruptible(&dev->struct_mutex);
 274         if (ret)
 275                 return ret;
 276
 277         total_obj_size = total_gtt_size = count = 0;
 278         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 279                 if (obj->stolen == NULL)
 280                         continue;
 281
 282                 list_add(&obj->obj_exec_link, &stolen);
 283
 284                 total_obj_size += obj->base.size;
 285                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 286                 count++;
 287         }
 288         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 289                 if (obj->stolen == NULL)
 290                         continue;
 291
 292                 list_add(&obj->obj_exec_link, &stolen);
 293
 294                 total_obj_size += obj->base.size;
 295                 count++;
 296         }
 297         list_sort(NULL, &stolen, obj_rank_by_stolen);
 298         seq_puts(m, "Stolen:\n");
 299         while (!list_empty(&stolen)) {
 300                 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
 301                 seq_puts(m, "   ");
 302                 describe_obj(m, obj);
 303                 seq_putc(m, '\n');
 304                 list_del_init(&obj->obj_exec_link);
 305         }
 306         mutex_unlock(&dev->struct_mutex);
 307
 308         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 309                    count, total_obj_size, total_gtt_size);
 310         return 0;
 311 }
 312
 313 #define count_objects(list, member) do { \
 314         list_for_each_entry(obj, list, member) { \
 315                 size += i915_gem_obj_total_ggtt_size(obj); \
 316                 ++count; \
 317                 if (obj->map_and_fenceable) { \
 318                         mappable_size += i915_gem_obj_ggtt_size(obj); \
 319                         ++mappable_count; \
 320                 } \
 321         } \
 322 } while (0)
 323
 324 struct file_stats {
 325         struct drm_i915_file_private *file_priv;
 326         unsigned long count;
 327         u64 total, unbound;
 328         u64 global, shared;
 329         u64 active, inactive;
 330 };
 331
 332 static int per_file_stats(int id, void *ptr, void *data)
 333 {
 334         struct drm_i915_gem_object *obj = ptr;
 335         struct file_stats *stats = data;
 336         struct i915_vma *vma;
 337
 338         stats->count++;
 339         stats->total += obj->base.size;
 340
 341         if (obj->base.name || obj->base.dma_buf)
 342                 stats->shared += obj->base.size;
 343
 344         if (USES_FULL_PPGTT(obj->base.dev)) {
 345                 list_for_each_entry(vma, &obj->vma_list, obj_link) {
 346                         struct i915_hw_ppgtt *ppgtt;
 347
 348                         if (!drm_mm_node_allocated(&vma->node))
 349                                 continue;
 350
 351                         if (vma->is_ggtt) {
 352                                 stats->global += obj->base.size;
 353                                 continue;
 354                         }
 355
 356                         ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
 357                         if (ppgtt->file_priv != stats->file_priv)
 358                                 continue;
 359
 360                         if (obj->active) /* XXX per-vma statistic */
 361                                 stats->active += obj->base.size;
 362                         else
 363                                 stats->inactive += obj->base.size;
 364
 365                         return 0;
 366                 }
 367         } else {
 368                 if (i915_gem_obj_ggtt_bound(obj)) {
 369                         stats->global += obj->base.size;
 370                         if (obj->active)
 371                                 stats->active += obj->base.size;
 372                         else
 373                                 stats->inactive += obj->base.size;
 374                         return 0;
 375                 }
 376         }
 377
 378         if (!list_empty(&obj->global_list))
 379                 stats->unbound += obj->base.size;
 380
 381         return 0;
 382 }
 383
 384 #define print_file_stats(m, name, stats) do { \
 385         if (stats.count) \
 386                 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
 387                            name, \
 388                            stats.count, \
 389                            stats.total, \
 390                            stats.active, \
 391                            stats.inactive, \
 392                            stats.global, \
 393                            stats.shared, \
 394                            stats.unbound); \
 395 } while (0)
 396
 397 static void print_batch_pool_stats(struct seq_file *m,
 398                                    struct drm_i915_private *dev_priv)
 399 {
 400         struct drm_i915_gem_object *obj;
 401         struct file_stats stats;
 402         struct intel_engine_cs *engine;
 403         int j;
 404
 405         memset(&stats, 0, sizeof(stats));
 406
 407         for_each_engine(engine, dev_priv) {
 408                 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
 409                         list_for_each_entry(obj,
 410                                             &engine->batch_pool.cache_list[j],
 411                                             batch_pool_link)
 412                                 per_file_stats(0, obj, &stats);
 413                 }
 414         }
 415
 416         print_file_stats(m, "[k]batch pool", stats);
 417 }
 418
 419 #define count_vmas(list, member) do { \
 420         list_for_each_entry(vma, list, member) { \
 421                 size += i915_gem_obj_total_ggtt_size(vma->obj); \
 422                 ++count; \
 423                 if (vma->obj->map_and_fenceable) { \
 424                         mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
 425                         ++mappable_count; \
 426                 } \
 427         } \
 428 } while (0)
 429
 430 static int i915_gem_object_info(struct seq_file *m, void* data)
 431 {
 432         struct drm_info_node *node = m->private;
 433         struct drm_device *dev = node->minor->dev;
 434         struct drm_i915_private *dev_priv = to_i915(dev);
 435         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 436         u32 count, mappable_count, purgeable_count;
 437         u64 size, mappable_size, purgeable_size;
 438         struct drm_i915_gem_object *obj;
 439         struct drm_file *file;
 440         struct i915_vma *vma;
 441         int ret;
 442
 443         ret = mutex_lock_interruptible(&dev->struct_mutex);
 444         if (ret)
 445                 return ret;
 446
 447         seq_printf(m, "%u objects, %zu bytes\n",
 448                    dev_priv->mm.object_count,
 449                    dev_priv->mm.object_memory);
 450
 451         size = count = mappable_size = mappable_count = 0;
 452         count_objects(&dev_priv->mm.bound_list, global_list);
 453         seq_printf(m, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
 454                    count, mappable_count, size, mappable_size);
 455
 456         size = count = mappable_size = mappable_count = 0;
 457         count_vmas(&ggtt->base.active_list, vm_link);
 458         seq_printf(m, "  %u [%u] active objects, %llu [%llu] bytes\n",
 459                    count, mappable_count, size, mappable_size);
 460
 461         size = count = mappable_size = mappable_count = 0;
 462         count_vmas(&ggtt->base.inactive_list, vm_link);
 463         seq_printf(m, "  %u [%u] inactive objects, %llu [%llu] bytes\n",
 464                    count, mappable_count, size, mappable_size);
 465
 466         size = count = purgeable_size = purgeable_count = 0;
 467         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 468                 size += obj->base.size, ++count;
 469                 if (obj->madv == I915_MADV_DONTNEED)
 470                         purgeable_size += obj->base.size, ++purgeable_count;
 471         }
 472         seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
 473
 474         size = count = mappable_size = mappable_count = 0;
 475         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 476                 if (obj->fault_mappable) {
 477                         size += i915_gem_obj_ggtt_size(obj);
 478                         ++count;
 479                 }
 480                 if (obj->pin_display) {
 481                         mappable_size += i915_gem_obj_ggtt_size(obj);
 482                         ++mappable_count;
 483                 }
 484                 if (obj->madv == I915_MADV_DONTNEED) {
 485                         purgeable_size += obj->base.size;
 486                         ++purgeable_count;
 487                 }
 488         }
 489         seq_printf(m, "%u purgeable objects, %llu bytes\n",
 490                    purgeable_count, purgeable_size);
 491         seq_printf(m, "%u pinned mappable objects, %llu bytes\n",
 492                    mappable_count, mappable_size);
 493         seq_printf(m, "%u fault mappable objects, %llu bytes\n",
 494                    count, size);
 495
 496         seq_printf(m, "%llu [%llu] gtt total\n",
 497                    ggtt->base.total, ggtt->mappable_end - ggtt->base.start);
 498
 499         seq_putc(m, '\n');
 500         print_batch_pool_stats(m, dev_priv);
 501         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
 502                 struct file_stats stats;
 503                 struct task_struct *task;
 504
 505                 memset(&stats, 0, sizeof(stats));
 506                 stats.file_priv = file->driver_priv;
 507                 spin_lock(&file->table_lock);
 508                 idr_for_each(&file->object_idr, per_file_stats, &stats);
 509                 spin_unlock(&file->table_lock);
 510                 /*
 511                  * Although we have a valid reference on file->pid, that does
 512                  * not guarantee that the task_struct who called get_pid() is
 513                  * still alive (e.g. get_pid(current) => fork() => exit()).
 514                  * Therefore, we need to protect this ->comm access using RCU.
 515                  */
 516                 rcu_read_lock();
 517                 task = pid_task(file->pid, PIDTYPE_PID);
 518                 print_file_stats(m, task ? task->comm : "<unknown>", stats);
 519                 rcu_read_unlock();
 520         }
 521
 522         mutex_unlock(&dev->struct_mutex);
 523
 524         return 0;
 525 }
 526
 527 static int i915_gem_gtt_info(struct seq_file *m, void *data)
 528 {
 529         struct drm_info_node *node = m->private;
 530         struct drm_device *dev = node->minor->dev;
 531         uintptr_t list = (uintptr_t) node->info_ent->data;
 532         struct drm_i915_private *dev_priv = dev->dev_private;
 533         struct drm_i915_gem_object *obj;
 534         u64 total_obj_size, total_gtt_size;
 535         int count, ret;
 536
 537         ret = mutex_lock_interruptible(&dev->struct_mutex);
 538         if (ret)
 539                 return ret;
 540
 541         total_obj_size = total_gtt_size = count = 0;
 542         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 543                 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
 544                         continue;
 545
 546                 seq_puts(m, "   ");
 547                 describe_obj(m, obj);
 548                 seq_putc(m, '\n');
 549                 total_obj_size += obj->base.size;
 550                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 551                 count++;
 552         }
 553
 554         mutex_unlock(&dev->struct_mutex);
 555
 556         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 557                    count, total_obj_size, total_gtt_size);
 558
 559         return 0;
 560 }
 561
 562 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
 563 {
 564         struct drm_info_node *node = m->private;
 565         struct drm_device *dev = node->minor->dev;
 566         struct drm_i915_private *dev_priv = dev->dev_private;
 567         struct intel_crtc *crtc;
 568         int ret;
 569
 570         ret = mutex_lock_interruptible(&dev->struct_mutex);
 571         if (ret)
 572                 return ret;
 573
 574         for_each_intel_crtc(dev, crtc) {
 575                 const char pipe = pipe_name(crtc->pipe);
 576                 const char plane = plane_name(crtc->plane);
 577                 struct intel_unpin_work *work;
 578
 579                 spin_lock_irq(&dev->event_lock);
 580                 work = crtc->unpin_work;
 581                 if (work == NULL) {
 582                         seq_printf(m, "No flip due on pipe %c (plane %c)\n",
 583                                    pipe, plane);
 584                 } else {
 585                         u32 addr;
 586
 587                         if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
 588                                 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
 589                                            pipe, plane);
 590                         } else {
 591                                 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
 592                                            pipe, plane);
 593                         }
 594                         if (work->flip_queued_req) {
 595                                 struct intel_engine_cs *engine = i915_gem_request_get_engine(work->flip_queued_req);
 596
 597                                 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
 598                                            engine->name,
 599                                            i915_gem_request_get_seqno(work->flip_queued_req),
 600                                            dev_priv->next_seqno,
 601                                            engine->get_seqno(engine, true),
 602                                            i915_gem_request_completed(work->flip_queued_req, true));
 603                         } else
 604                                 seq_printf(m, "Flip not associated with any ring\n");
 605                         seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
 606                                    work->flip_queued_vblank,
 607                                    work->flip_ready_vblank,
 608                                    drm_crtc_vblank_count(&crtc->base));
 609                         if (work->enable_stall_check)
 610                                 seq_puts(m, "Stall check enabled, ");
 611                         else
 612                                 seq_puts(m, "Stall check waiting for page flip ioctl, ");
 613                         seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
 614
 615                         if (INTEL_INFO(dev)->gen >= 4)
 616                                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
 617                         else
 618                                 addr = I915_READ(DSPADDR(crtc->plane));
 619                         seq_printf(m, "Current scanout address 0x%08x\n", addr);
 620
 621                         if (work->pending_flip_obj) {
 622                                 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
 623                                 seq_printf(m, "MMIO update completed? %d\n",  addr == work->gtt_offset);
 624                         }
 625                 }
 626                 spin_unlock_irq(&dev->event_lock);
 627         }
 628
 629         mutex_unlock(&dev->struct_mutex);
 630
 631         return 0;
 632 }
 633
 634 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
 635 {
 636         struct drm_info_node *node = m->private;
 637         struct drm_device *dev = node->minor->dev;
 638         struct drm_i915_private *dev_priv = dev->dev_private;
 639         struct drm_i915_gem_object *obj;
 640         struct intel_engine_cs *engine;
 641         int total = 0;
 642         int ret, j;
 643
 644         ret = mutex_lock_interruptible(&dev->struct_mutex);
 645         if (ret)
 646                 return ret;
 647
 648         for_each_engine(engine, dev_priv) {
 649                 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
 650                         int count;
 651
 652                         count = 0;
 653                         list_for_each_entry(obj,
 654                                             &engine->batch_pool.cache_list[j],
 655                                             batch_pool_link)
 656                                 count++;
 657                         seq_printf(m, "%s cache[%d]: %d objects\n",
 658                                    engine->name, j, count);
 659
 660                         list_for_each_entry(obj,
 661                                             &engine->batch_pool.cache_list[j],
 662                                             batch_pool_link) {
 663                                 seq_puts(m, "   ");
 664                                 describe_obj(m, obj);
 665                                 seq_putc(m, '\n');
 666                         }
 667
 668                         total += count;
 669                 }
 670         }
 671
 672         seq_printf(m, "total: %d\n", total);
 673
 674         mutex_unlock(&dev->struct_mutex);
 675
 676         return 0;
 677 }
 678
 679 static int i915_gem_request_info(struct seq_file *m, void *data)
 680 {
 681         struct drm_info_node *node = m->private;
 682         struct drm_device *dev = node->minor->dev;
 683         struct drm_i915_private *dev_priv = dev->dev_private;
 684         struct intel_engine_cs *engine;
 685         struct drm_i915_gem_request *req;
 686         int ret, any;
 687
 688         ret = mutex_lock_interruptible(&dev->struct_mutex);
 689         if (ret)
 690                 return ret;
 691
 692         any = 0;
 693         for_each_engine(engine, dev_priv) {
 694                 int count;
 695
 696                 count = 0;
 697                 list_for_each_entry(req, &engine->request_list, list)
 698                         count++;
 699                 if (count == 0)
 700                         continue;
 701
 702                 seq_printf(m, "%s requests: %d\n", engine->name, count);
 703                 list_for_each_entry(req, &engine->request_list, list) {
 704                         struct task_struct *task;
 705
 706                         rcu_read_lock();
 707                         task = NULL;
 708                         if (req->pid)
 709                                 task = pid_task(req->pid, PIDTYPE_PID);
 710                         seq_printf(m, "    %x @ %d: %s [%d]\n",
 711                                    req->seqno,
 712                                    (int) (jiffies - req->emitted_jiffies),
 713                                    task ? task->comm : "<unknown>",
 714                                    task ? task->pid : -1);
 715                         rcu_read_unlock();
 716                 }
 717
 718                 any++;
 719         }
 720         mutex_unlock(&dev->struct_mutex);
 721
 722         if (any == 0)
 723                 seq_puts(m, "No requests\n");
 724
 725         return 0;
 726 }
 727
 728 static void i915_ring_seqno_info(struct seq_file *m,
 729                                  struct intel_engine_cs *engine)
 730 {
 731         if (engine->get_seqno) {
 732                 seq_printf(m, "Current sequence (%s): %x\n",
 733                            engine->name, engine->get_seqno(engine, false));
 734         }
 735 }
 736
 737 static int i915_gem_seqno_info(struct seq_file *m, void *data)
 738 {
 739         struct drm_info_node *node = m->private;
 740         struct drm_device *dev = node->minor->dev;
 741         struct drm_i915_private *dev_priv = dev->dev_private;
 742         struct intel_engine_cs *engine;
 743         int ret;
 744
 745         ret = mutex_lock_interruptible(&dev->struct_mutex);
 746         if (ret)
 747                 return ret;
 748         intel_runtime_pm_get(dev_priv);
 749
 750         for_each_engine(engine, dev_priv)
 751                 i915_ring_seqno_info(m, engine);
 752
 753         intel_runtime_pm_put(dev_priv);
 754         mutex_unlock(&dev->struct_mutex);
 755
 756         return 0;
 757 }
 758
 759
 760 static int i915_interrupt_info(struct seq_file *m, void *data)
 761 {
 762         struct drm_info_node *node = m->private;
 763         struct drm_device *dev = node->minor->dev;
 764         struct drm_i915_private *dev_priv = dev->dev_private;
 765         struct intel_engine_cs *engine;
 766         int ret, i, pipe;
 767
 768         ret = mutex_lock_interruptible(&dev->struct_mutex);
 769         if (ret)
 770                 return ret;
 771         intel_runtime_pm_get(dev_priv);
 772
 773         if (IS_CHERRYVIEW(dev)) {
 774                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 775                            I915_READ(GEN8_MASTER_IRQ));
 776
 777                 seq_printf(m, "Display IER:\t%08x\n",
 778                            I915_READ(VLV_IER));
 779                 seq_printf(m, "Display IIR:\t%08x\n",
 780                            I915_READ(VLV_IIR));
 781                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 782                            I915_READ(VLV_IIR_RW));
 783                 seq_printf(m, "Display IMR:\t%08x\n",
 784                            I915_READ(VLV_IMR));
 785                 for_each_pipe(dev_priv, pipe)
 786                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 787                                    pipe_name(pipe),
 788                                    I915_READ(PIPESTAT(pipe)));
 789
 790                 seq_printf(m, "Port hotplug:\t%08x\n",
 791                            I915_READ(PORT_HOTPLUG_EN));
 792                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 793                            I915_READ(VLV_DPFLIPSTAT));
 794                 seq_printf(m, "DPINVGTT:\t%08x\n",
 795                            I915_READ(DPINVGTT));
 796
 797                 for (i = 0; i < 4; i++) {
 798                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 799                                    i, I915_READ(GEN8_GT_IMR(i)));
 800                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 801                                    i, I915_READ(GEN8_GT_IIR(i)));
 802                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 803                                    i, I915_READ(GEN8_GT_IER(i)));
 804                 }
 805
 806                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 807                            I915_READ(GEN8_PCU_IMR));
 808                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 809                            I915_READ(GEN8_PCU_IIR));
 810                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 811                            I915_READ(GEN8_PCU_IER));
 812         } else if (INTEL_INFO(dev)->gen >= 8) {
 813                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 814                            I915_READ(GEN8_MASTER_IRQ));
 815
 816                 for (i = 0; i < 4; i++) {
 817                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 818                                    i, I915_READ(GEN8_GT_IMR(i)));
 819                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 820                                    i, I915_READ(GEN8_GT_IIR(i)));
 821                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 822                                    i, I915_READ(GEN8_GT_IER(i)));
 823                 }
 824
 825                 for_each_pipe(dev_priv, pipe) {
 826                         enum intel_display_power_domain power_domain;
 827
 828                         power_domain = POWER_DOMAIN_PIPE(pipe);
 829                         if (!intel_display_power_get_if_enabled(dev_priv,
 830                                                                 power_domain)) {
 831                                 seq_printf(m, "Pipe %c power disabled\n",
 832                                            pipe_name(pipe));
 833                                 continue;
 834                         }
 835                         seq_printf(m, "Pipe %c IMR:\t%08x\n",
 836                                    pipe_name(pipe),
 837                                    I915_READ(GEN8_DE_PIPE_IMR(pipe)));
 838                         seq_printf(m, "Pipe %c IIR:\t%08x\n",
 839                                    pipe_name(pipe),
 840                                    I915_READ(GEN8_DE_PIPE_IIR(pipe)));
 841                         seq_printf(m, "Pipe %c IER:\t%08x\n",
 842                                    pipe_name(pipe),
 843                                    I915_READ(GEN8_DE_PIPE_IER(pipe)));
 844
 845                         intel_display_power_put(dev_priv, power_domain);
 846                 }
 847
 848                 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
 849                            I915_READ(GEN8_DE_PORT_IMR));
 850                 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
 851                            I915_READ(GEN8_DE_PORT_IIR));
 852                 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
 853                            I915_READ(GEN8_DE_PORT_IER));
 854
 855                 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
 856                            I915_READ(GEN8_DE_MISC_IMR));
 857                 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
 858                            I915_READ(GEN8_DE_MISC_IIR));
 859                 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
 860                            I915_READ(GEN8_DE_MISC_IER));
 861
 862                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 863                            I915_READ(GEN8_PCU_IMR));
 864                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 865                            I915_READ(GEN8_PCU_IIR));
 866                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 867                            I915_READ(GEN8_PCU_IER));
 868         } else if (IS_VALLEYVIEW(dev)) {
 869                 seq_printf(m, "Display IER:\t%08x\n",
 870                            I915_READ(VLV_IER));
 871                 seq_printf(m, "Display IIR:\t%08x\n",
 872                            I915_READ(VLV_IIR));
 873                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 874                            I915_READ(VLV_IIR_RW));
 875                 seq_printf(m, "Display IMR:\t%08x\n",
 876                            I915_READ(VLV_IMR));
 877                 for_each_pipe(dev_priv, pipe)
 878                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 879                                    pipe_name(pipe),
 880                                    I915_READ(PIPESTAT(pipe)));
 881
 882                 seq_printf(m, "Master IER:\t%08x\n",
 883                            I915_READ(VLV_MASTER_IER));
 884
 885                 seq_printf(m, "Render IER:\t%08x\n",
 886                            I915_READ(GTIER));
 887                 seq_printf(m, "Render IIR:\t%08x\n",
 888                            I915_READ(GTIIR));
 889                 seq_printf(m, "Render IMR:\t%08x\n",
 890                            I915_READ(GTIMR));
 891
 892                 seq_printf(m, "PM IER:\t\t%08x\n",
 893                            I915_READ(GEN6_PMIER));
 894                 seq_printf(m, "PM IIR:\t\t%08x\n",
 895                            I915_READ(GEN6_PMIIR));
 896                 seq_printf(m, "PM IMR:\t\t%08x\n",
 897                            I915_READ(GEN6_PMIMR));
 898
 899                 seq_printf(m, "Port hotplug:\t%08x\n",
 900                            I915_READ(PORT_HOTPLUG_EN));
 901                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 902                            I915_READ(VLV_DPFLIPSTAT));
 903                 seq_printf(m, "DPINVGTT:\t%08x\n",
 904                            I915_READ(DPINVGTT));
 905
 906         } else if (!HAS_PCH_SPLIT(dev)) {
 907                 seq_printf(m, "Interrupt enable:    %08x\n",
 908                            I915_READ(IER));
 909                 seq_printf(m, "Interrupt identity:  %08x\n",
 910                            I915_READ(IIR));
 911                 seq_printf(m, "Interrupt mask:      %08x\n",
 912                            I915_READ(IMR));
 913                 for_each_pipe(dev_priv, pipe)
 914                         seq_printf(m, "Pipe %c stat:         %08x\n",
 915                                    pipe_name(pipe),
 916                                    I915_READ(PIPESTAT(pipe)));
 917         } else {
 918                 seq_printf(m, "North Display Interrupt enable:          %08x\n",
 919                            I915_READ(DEIER));
 920                 seq_printf(m, "North Display Interrupt identity:        %08x\n",
 921                            I915_READ(DEIIR));
 922                 seq_printf(m, "North Display Interrupt mask:            %08x\n",
 923                            I915_READ(DEIMR));
 924                 seq_printf(m, "South Display Interrupt enable:          %08x\n",
 925                            I915_READ(SDEIER));
 926                 seq_printf(m, "South Display Interrupt identity:        %08x\n",
 927                            I915_READ(SDEIIR));
 928                 seq_printf(m, "South Display Interrupt mask:            %08x\n",
 929                            I915_READ(SDEIMR));
 930                 seq_printf(m, "Graphics Interrupt enable:               %08x\n",
 931                            I915_READ(GTIER));
 932                 seq_printf(m, "Graphics Interrupt identity:             %08x\n",
 933                            I915_READ(GTIIR));
 934                 seq_printf(m, "Graphics Interrupt mask:         %08x\n",
 935                            I915_READ(GTIMR));
 936         }
 937         for_each_engine(engine, dev_priv) {
 938                 if (INTEL_INFO(dev)->gen >= 6) {
 939                         seq_printf(m,
 940                                    "Graphics Interrupt mask (%s):       %08x\n",
 941                                    engine->name, I915_READ_IMR(engine));
 942                 }
 943                 i915_ring_seqno_info(m, engine);
 944         }
 945         intel_runtime_pm_put(dev_priv);
 946         mutex_unlock(&dev->struct_mutex);
 947
 948         return 0;
 949 }
 950
 951 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
 952 {
 953         struct drm_info_node *node = m->private;
 954         struct drm_device *dev = node->minor->dev;
 955         struct drm_i915_private *dev_priv = dev->dev_private;
 956         int i, ret;
 957
 958         ret = mutex_lock_interruptible(&dev->struct_mutex);
 959         if (ret)
 960                 return ret;
 961
 962         seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
 963         for (i = 0; i < dev_priv->num_fence_regs; i++) {
 964                 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
 965
 966                 seq_printf(m, "Fence %d, pin count = %d, object = ",
 967                            i, dev_priv->fence_regs[i].pin_count);
 968                 if (obj == NULL)
 969                         seq_puts(m, "unused");
 970                 else
 971                         describe_obj(m, obj);
 972                 seq_putc(m, '\n');
 973         }
 974
 975         mutex_unlock(&dev->struct_mutex);
 976         return 0;
 977 }
 978
 979 static int i915_hws_info(struct seq_file *m, void *data)
 980 {
 981         struct drm_info_node *node = m->private;
 982         struct drm_device *dev = node->minor->dev;
 983         struct drm_i915_private *dev_priv = dev->dev_private;
 984         struct intel_engine_cs *engine;
 985         const u32 *hws;
 986         int i;
 987
 988         engine = &dev_priv->engine[(uintptr_t)node->info_ent->data];
 989         hws = engine->status_page.page_addr;
 990         if (hws == NULL)
 991                 return 0;
 992
 993         for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
 994                 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
 995                            i * 4,
 996                            hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
 997         }
 998         return 0;
 999 }
1000
1001 static ssize_t
1002 i915_error_state_write(struct file *filp,
1003                        const char __user *ubuf,
1004                        size_t cnt,
1005                        loff_t *ppos)
1006 {
1007         struct i915_error_state_file_priv *error_priv = filp->private_data;
1008         struct drm_device *dev = error_priv->dev;
1009         int ret;
1010
1011         DRM_DEBUG_DRIVER("Resetting error state\n");
1012
1013         ret = mutex_lock_interruptible(&dev->struct_mutex);
1014         if (ret)
1015                 return ret;
1016
1017         i915_destroy_error_state(dev);
1018         mutex_unlock(&dev->struct_mutex);
1019
1020         return cnt;
1021 }
1022
1023 static int i915_error_state_open(struct inode *inode, struct file *file)
1024 {
1025         struct drm_device *dev = inode->i_private;
1026         struct i915_error_state_file_priv *error_priv;
1027
1028         error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
1029         if (!error_priv)
1030                 return -ENOMEM;
1031
1032         error_priv->dev = dev;
1033
1034         i915_error_state_get(dev, error_priv);
1035
1036         file->private_data = error_priv;
1037
1038         return 0;
1039 }
1040
1041 static int i915_error_state_release(struct inode *inode, struct file *file)
1042 {
1043         struct i915_error_state_file_priv *error_priv = file->private_data;
1044
1045         i915_error_state_put(error_priv);
1046         kfree(error_priv);
1047
1048         return 0;
1049 }
1050
1051 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1052                                      size_t count, loff_t *pos)
1053 {
1054         struct i915_error_state_file_priv *error_priv = file->private_data;
1055         struct drm_i915_error_state_buf error_str;
1056         loff_t tmp_pos = 0;
1057         ssize_t ret_count = 0;
1058         int ret;
1059
1060         ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
1061         if (ret)
1062                 return ret;
1063
1064         ret = i915_error_state_to_str(&error_str, error_priv);
1065         if (ret)
1066                 goto out;
1067
1068         ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1069                                             error_str.buf,
1070                                             error_str.bytes);
1071
1072         if (ret_count < 0)
1073                 ret = ret_count;
1074         else
1075                 *pos = error_str.start + ret_count;
1076 out:
1077         i915_error_state_buf_release(&error_str);
1078         return ret ?: ret_count;
1079 }
1080
1081 static const struct file_operations i915_error_state_fops = {
1082         .owner = THIS_MODULE,
1083         .open = i915_error_state_open,
1084         .read = i915_error_state_read,
1085         .write = i915_error_state_write,
1086         .llseek = default_llseek,
1087         .release = i915_error_state_release,
1088 };
1089
1090 static int
1091 i915_next_seqno_get(void *data, u64 *val)
1092 {
1093         struct drm_device *dev = data;
1094         struct drm_i915_private *dev_priv = dev->dev_private;
1095         int ret;
1096
1097         ret = mutex_lock_interruptible(&dev->struct_mutex);
1098         if (ret)
1099                 return ret;
1100
1101         *val = dev_priv->next_seqno;
1102         mutex_unlock(&dev->struct_mutex);
1103
1104         return 0;
1105 }
1106
1107 static int
1108 i915_next_seqno_set(void *data, u64 val)
1109 {
1110         struct drm_device *dev = data;
1111         int ret;
1112
1113         ret = mutex_lock_interruptible(&dev->struct_mutex);
1114         if (ret)
1115                 return ret;
1116
1117         ret = i915_gem_set_seqno(dev, val);
1118         mutex_unlock(&dev->struct_mutex);
1119
1120         return ret;
1121 }
1122
1123 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1124                         i915_next_seqno_get, i915_next_seqno_set,
1125                         "0x%llx\n");
1126
1127 static int i915_frequency_info(struct seq_file *m, void *unused)
1128 {
1129         struct drm_info_node *node = m->private;
1130         struct drm_device *dev = node->minor->dev;
1131         struct drm_i915_private *dev_priv = dev->dev_private;
1132         int ret = 0;
1133
1134         intel_runtime_pm_get(dev_priv);
1135
1136         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1137
1138         if (IS_GEN5(dev)) {
1139                 u16 rgvswctl = I915_READ16(MEMSWCTL);
1140                 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1141
1142                 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1143                 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1144                 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1145                            MEMSTAT_VID_SHIFT);
1146                 seq_printf(m, "Current P-state: %d\n",
1147                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1148         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1149                 u32 freq_sts;
1150
1151                 mutex_lock(&dev_priv->rps.hw_lock);
1152                 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1153                 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1154                 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1155
1156                 seq_printf(m, "actual GPU freq: %d MHz\n",
1157                            intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1158
1159                 seq_printf(m, "current GPU freq: %d MHz\n",
1160                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1161
1162                 seq_printf(m, "max GPU freq: %d MHz\n",
1163                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1164
1165                 seq_printf(m, "min GPU freq: %d MHz\n",
1166                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1167
1168                 seq_printf(m, "idle GPU freq: %d MHz\n",
1169                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1170
1171                 seq_printf(m,
1172                            "efficient (RPe) frequency: %d MHz\n",
1173                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1174                 mutex_unlock(&dev_priv->rps.hw_lock);
1175         } else if (INTEL_INFO(dev)->gen >= 6) {
1176                 u32 rp_state_limits;
1177                 u32 gt_perf_status;
1178                 u32 rp_state_cap;
1179                 u32 rpmodectl, rpinclimit, rpdeclimit;
1180                 u32 rpstat, cagf, reqf;
1181                 u32 rpupei, rpcurup, rpprevup;
1182                 u32 rpdownei, rpcurdown, rpprevdown;
1183                 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1184                 int max_freq;
1185
1186                 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1187                 if (IS_BROXTON(dev)) {
1188                         rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1189                         gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1190                 } else {
1191                         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1192                         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1193                 }
1194
1195                 /* RPSTAT1 is in the GT power well */
1196                 ret = mutex_lock_interruptible(&dev->struct_mutex);
1197                 if (ret)
1198                         goto out;
1199
1200                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1201
1202                 reqf = I915_READ(GEN6_RPNSWREQ);
1203                 if (IS_GEN9(dev))
1204                         reqf >>= 23;
1205                 else {
1206                         reqf &= ~GEN6_TURBO_DISABLE;
1207                         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1208                                 reqf >>= 24;
1209                         else
1210                                 reqf >>= 25;
1211                 }
1212                 reqf = intel_gpu_freq(dev_priv, reqf);
1213
1214                 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1215                 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1216                 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1217
1218                 rpstat = I915_READ(GEN6_RPSTAT1);
1219                 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1220                 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1221                 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1222                 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1223                 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1224                 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
1225                 if (IS_GEN9(dev))
1226                         cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1227                 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1228                         cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1229                 else
1230                         cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1231                 cagf = intel_gpu_freq(dev_priv, cagf);
1232
1233                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1234                 mutex_unlock(&dev->struct_mutex);
1235
1236                 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1237                         pm_ier = I915_READ(GEN6_PMIER);
1238                         pm_imr = I915_READ(GEN6_PMIMR);
1239                         pm_isr = I915_READ(GEN6_PMISR);
1240                         pm_iir = I915_READ(GEN6_PMIIR);
1241                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1242                 } else {
1243                         pm_ier = I915_READ(GEN8_GT_IER(2));
1244                         pm_imr = I915_READ(GEN8_GT_IMR(2));
1245                         pm_isr = I915_READ(GEN8_GT_ISR(2));
1246                         pm_iir = I915_READ(GEN8_GT_IIR(2));
1247                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1248                 }
1249                 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1250                            pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1251                 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1252                 seq_printf(m, "Render p-state ratio: %d\n",
1253                            (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
1254                 seq_printf(m, "Render p-state VID: %d\n",
1255                            gt_perf_status & 0xff);
1256                 seq_printf(m, "Render p-state limit: %d\n",
1257                            rp_state_limits & 0xff);
1258                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1259                 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1260                 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1261                 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1262                 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1263                 seq_printf(m, "CAGF: %dMHz\n", cagf);
1264                 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1265                            GEN6_CURICONT_MASK);
1266                 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1267                            GEN6_CURBSYTAVG_MASK);
1268                 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1269                            GEN6_CURBSYTAVG_MASK);
1270                 seq_printf(m, "Up threshold: %d%%\n",
1271                            dev_priv->rps.up_threshold);
1272
1273                 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1274                            GEN6_CURIAVG_MASK);
1275                 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1276                            GEN6_CURBSYTAVG_MASK);
1277                 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1278                            GEN6_CURBSYTAVG_MASK);
1279                 seq_printf(m, "Down threshold: %d%%\n",
1280                            dev_priv->rps.down_threshold);
1281
1282                 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 :
1283                             rp_state_cap >> 16) & 0xff;
1284                 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1285                              GEN9_FREQ_SCALER : 1);
1286                 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1287                            intel_gpu_freq(dev_priv, max_freq));
1288
1289                 max_freq = (rp_state_cap & 0xff00) >> 8;
1290                 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1291                              GEN9_FREQ_SCALER : 1);
1292                 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1293                            intel_gpu_freq(dev_priv, max_freq));
1294
1295                 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 :
1296                             rp_state_cap >> 0) & 0xff;
1297                 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1298                              GEN9_FREQ_SCALER : 1);
1299                 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1300                            intel_gpu_freq(dev_priv, max_freq));
1301                 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1302                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1303
1304                 seq_printf(m, "Current freq: %d MHz\n",
1305                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1306                 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1307                 seq_printf(m, "Idle freq: %d MHz\n",
1308                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1309                 seq_printf(m, "Min freq: %d MHz\n",
1310                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1311                 seq_printf(m, "Max freq: %d MHz\n",
1312                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1313                 seq_printf(m,
1314                            "efficient (RPe) frequency: %d MHz\n",
1315                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1316         } else {
1317                 seq_puts(m, "no P-state info available\n");
1318         }
1319
1320         seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
1321         seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1322         seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1323
1324 out:
1325         intel_runtime_pm_put(dev_priv);
1326         return ret;
1327 }
1328
1329 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1330 {
1331         struct drm_info_node *node = m->private;
1332         struct drm_device *dev = node->minor->dev;
1333         struct drm_i915_private *dev_priv = dev->dev_private;
1334         struct intel_engine_cs *engine;
1335         u64 acthd[I915_NUM_ENGINES];
1336         u32 seqno[I915_NUM_ENGINES];
1337         u32 instdone[I915_NUM_INSTDONE_REG];
1338         enum intel_engine_id id;
1339         int j;
1340
1341         if (!i915.enable_hangcheck) {
1342                 seq_printf(m, "Hangcheck disabled\n");
1343                 return 0;
1344         }
1345
1346         intel_runtime_pm_get(dev_priv);
1347
1348         for_each_engine_id(engine, dev_priv, id) {
1349                 seqno[id] = engine->get_seqno(engine, false);
1350                 acthd[id] = intel_ring_get_active_head(engine);
1351         }
1352
1353         i915_get_extra_instdone(dev, instdone);
1354
1355         intel_runtime_pm_put(dev_priv);
1356
1357         if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1358                 seq_printf(m, "Hangcheck active, fires in %dms\n",
1359                            jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1360                                             jiffies));
1361         } else
1362                 seq_printf(m, "Hangcheck inactive\n");
1363
1364         for_each_engine_id(engine, dev_priv, id) {
1365                 seq_printf(m, "%s:\n", engine->name);
1366                 seq_printf(m, "\tseqno = %x [current %x]\n",
1367                            engine->hangcheck.seqno, seqno[id]);
1368                 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1369                            (long long)engine->hangcheck.acthd,
1370                            (long long)acthd[id]);
1371                 seq_printf(m, "\tscore = %d\n", engine->hangcheck.score);
1372                 seq_printf(m, "\taction = %d\n", engine->hangcheck.action);
1373
1374                 if (engine->id == RCS) {
1375                         seq_puts(m, "\tinstdone read =");
1376
1377                         for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1378                                 seq_printf(m, " 0x%08x", instdone[j]);
1379
1380                         seq_puts(m, "\n\tinstdone accu =");
1381
1382                         for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1383                                 seq_printf(m, " 0x%08x",
1384                                            engine->hangcheck.instdone[j]);
1385
1386                         seq_puts(m, "\n");
1387                 }
1388         }
1389
1390         return 0;
1391 }
1392
1393 static int ironlake_drpc_info(struct seq_file *m)
1394 {
1395         struct drm_info_node *node = m->private;
1396         struct drm_device *dev = node->minor->dev;
1397         struct drm_i915_private *dev_priv = dev->dev_private;
1398         u32 rgvmodectl, rstdbyctl;
1399         u16 crstandvid;
1400         int ret;
1401
1402         ret = mutex_lock_interruptible(&dev->struct_mutex);
1403         if (ret)
1404                 return ret;
1405         intel_runtime_pm_get(dev_priv);
1406
1407         rgvmodectl = I915_READ(MEMMODECTL);
1408         rstdbyctl = I915_READ(RSTDBYCTL);
1409         crstandvid = I915_READ16(CRSTANDVID);
1410
1411         intel_runtime_pm_put(dev_priv);
1412         mutex_unlock(&dev->struct_mutex);
1413
1414         seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1415         seq_printf(m, "Boost freq: %d\n",
1416                    (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1417                    MEMMODE_BOOST_FREQ_SHIFT);
1418         seq_printf(m, "HW control enabled: %s\n",
1419                    yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1420         seq_printf(m, "SW control enabled: %s\n",
1421                    yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1422         seq_printf(m, "Gated voltage change: %s\n",
1423                    yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1424         seq_printf(m, "Starting frequency: P%d\n",
1425                    (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1426         seq_printf(m, "Max P-state: P%d\n",
1427                    (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1428         seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1429         seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1430         seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1431         seq_printf(m, "Render standby enabled: %s\n",
1432                    yesno(!(rstdbyctl & RCX_SW_EXIT)));
1433         seq_puts(m, "Current RS state: ");
1434         switch (rstdbyctl & RSX_STATUS_MASK) {
1435         case RSX_STATUS_ON:
1436                 seq_puts(m, "on\n");
1437                 break;
1438         case RSX_STATUS_RC1:
1439                 seq_puts(m, "RC1\n");
1440                 break;
1441         case RSX_STATUS_RC1E:
1442                 seq_puts(m, "RC1E\n");
1443                 break;
1444         case RSX_STATUS_RS1:
1445                 seq_puts(m, "RS1\n");
1446                 break;
1447         case RSX_STATUS_RS2:
1448                 seq_puts(m, "RS2 (RC6)\n");
1449                 break;
1450         case RSX_STATUS_RS3:
1451                 seq_puts(m, "RC3 (RC6+)\n");
1452                 break;
1453         default:
1454                 seq_puts(m, "unknown\n");
1455                 break;
1456         }
1457
1458         return 0;
1459 }
1460
1461 static int i915_forcewake_domains(struct seq_file *m, void *data)
1462 {
1463         struct drm_info_node *node = m->private;
1464         struct drm_device *dev = node->minor->dev;
1465         struct drm_i915_private *dev_priv = dev->dev_private;
1466         struct intel_uncore_forcewake_domain *fw_domain;
1467         int i;
1468
1469         spin_lock_irq(&dev_priv->uncore.lock);
1470         for_each_fw_domain(fw_domain, dev_priv, i) {
1471                 seq_printf(m, "%s.wake_count = %u\n",
1472                            intel_uncore_forcewake_domain_to_str(i),
1473                            fw_domain->wake_count);
1474         }
1475         spin_unlock_irq(&dev_priv->uncore.lock);
1476
1477         return 0;
1478 }
1479
1480 static int vlv_drpc_info(struct seq_file *m)
1481 {
1482         struct drm_info_node *node = m->private;
1483         struct drm_device *dev = node->minor->dev;
1484         struct drm_i915_private *dev_priv = dev->dev_private;
1485         u32 rpmodectl1, rcctl1, pw_status;
1486
1487         intel_runtime_pm_get(dev_priv);
1488
1489         pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1490         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1491         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1492
1493         intel_runtime_pm_put(dev_priv);
1494
1495         seq_printf(m, "Video Turbo Mode: %s\n",
1496                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1497         seq_printf(m, "Turbo enabled: %s\n",
1498                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1499         seq_printf(m, "HW control enabled: %s\n",
1500                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1501         seq_printf(m, "SW control enabled: %s\n",
1502                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1503                           GEN6_RP_MEDIA_SW_MODE));
1504         seq_printf(m, "RC6 Enabled: %s\n",
1505                    yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1506                                         GEN6_RC_CTL_EI_MODE(1))));
1507         seq_printf(m, "Render Power Well: %s\n",
1508                    (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1509         seq_printf(m, "Media Power Well: %s\n",
1510                    (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1511
1512         seq_printf(m, "Render RC6 residency since boot: %u\n",
1513                    I915_READ(VLV_GT_RENDER_RC6));
1514         seq_printf(m, "Media RC6 residency since boot: %u\n",
1515                    I915_READ(VLV_GT_MEDIA_RC6));
1516
1517         return i915_forcewake_domains(m, NULL);
1518 }
1519
1520 static int gen6_drpc_info(struct seq_file *m)
1521 {
1522         struct drm_info_node *node = m->private;
1523         struct drm_device *dev = node->minor->dev;
1524         struct drm_i915_private *dev_priv = dev->dev_private;
1525         u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1526         unsigned forcewake_count;
1527         int count = 0, ret;
1528
1529         ret = mutex_lock_interruptible(&dev->struct_mutex);
1530         if (ret)
1531                 return ret;
1532         intel_runtime_pm_get(dev_priv);
1533
1534         spin_lock_irq(&dev_priv->uncore.lock);
1535         forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1536         spin_unlock_irq(&dev_priv->uncore.lock);
1537
1538         if (forcewake_count) {
1539                 seq_puts(m, "RC information inaccurate because somebody "
1540                             "holds a forcewake reference \n");
1541         } else {
1542                 /* NB: we cannot use forcewake, else we read the wrong values */
1543                 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1544                         udelay(10);
1545                 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1546         }
1547
1548         gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1549         trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1550
1551         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1552         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1553         mutex_unlock(&dev->struct_mutex);
1554         mutex_lock(&dev_priv->rps.hw_lock);
1555         sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1556         mutex_unlock(&dev_priv->rps.hw_lock);
1557
1558         intel_runtime_pm_put(dev_priv);
1559
1560         seq_printf(m, "Video Turbo Mode: %s\n",
1561                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1562         seq_printf(m, "HW control enabled: %s\n",
1563                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1564         seq_printf(m, "SW control enabled: %s\n",
1565                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1566                           GEN6_RP_MEDIA_SW_MODE));
1567         seq_printf(m, "RC1e Enabled: %s\n",
1568                    yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1569         seq_printf(m, "RC6 Enabled: %s\n",
1570                    yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1571         seq_printf(m, "Deep RC6 Enabled: %s\n",
1572                    yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1573         seq_printf(m, "Deepest RC6 Enabled: %s\n",
1574                    yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1575         seq_puts(m, "Current RC state: ");
1576         switch (gt_core_status & GEN6_RCn_MASK) {
1577         case GEN6_RC0:
1578                 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1579                         seq_puts(m, "Core Power Down\n");
1580                 else
1581                         seq_puts(m, "on\n");
1582                 break;
1583         case GEN6_RC3:
1584                 seq_puts(m, "RC3\n");
1585                 break;
1586         case GEN6_RC6:
1587                 seq_puts(m, "RC6\n");
1588                 break;
1589         case GEN6_RC7:
1590                 seq_puts(m, "RC7\n");
1591                 break;
1592         default:
1593                 seq_puts(m, "Unknown\n");
1594                 break;
1595         }
1596
1597         seq_printf(m, "Core Power Down: %s\n",
1598                    yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1599
1600         /* Not exactly sure what this is */
1601         seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1602                    I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1603         seq_printf(m, "RC6 residency since boot: %u\n",
1604                    I915_READ(GEN6_GT_GFX_RC6));
1605         seq_printf(m, "RC6+ residency since boot: %u\n",
1606                    I915_READ(GEN6_GT_GFX_RC6p));
1607         seq_printf(m, "RC6++ residency since boot: %u\n",
1608                    I915_READ(GEN6_GT_GFX_RC6pp));
1609
1610         seq_printf(m, "RC6   voltage: %dmV\n",
1611                    GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1612         seq_printf(m, "RC6+  voltage: %dmV\n",
1613                    GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1614         seq_printf(m, "RC6++ voltage: %dmV\n",
1615                    GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1616         return 0;
1617 }
1618
1619 static int i915_drpc_info(struct seq_file *m, void *unused)
1620 {
1621         struct drm_info_node *node = m->private;
1622         struct drm_device *dev = node->minor->dev;
1623
1624         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
1625                 return vlv_drpc_info(m);
1626         else if (INTEL_INFO(dev)->gen >= 6)
1627                 return gen6_drpc_info(m);
1628         else
1629                 return ironlake_drpc_info(m);
1630 }
1631
1632 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1633 {
1634         struct drm_info_node *node = m->private;
1635         struct drm_device *dev = node->minor->dev;
1636         struct drm_i915_private *dev_priv = dev->dev_private;
1637
1638         seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1639                    dev_priv->fb_tracking.busy_bits);
1640
1641         seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1642                    dev_priv->fb_tracking.flip_bits);
1643
1644         return 0;
1645 }
1646
1647 static int i915_fbc_status(struct seq_file *m, void *unused)
1648 {
1649         struct drm_info_node *node = m->private;
1650         struct drm_device *dev = node->minor->dev;
1651         struct drm_i915_private *dev_priv = dev->dev_private;
1652
1653         if (!HAS_FBC(dev)) {
1654                 seq_puts(m, "FBC unsupported on this chipset\n");
1655                 return 0;
1656         }
1657
1658         intel_runtime_pm_get(dev_priv);
1659         mutex_lock(&dev_priv->fbc.lock);
1660
1661         if (intel_fbc_is_active(dev_priv))
1662                 seq_puts(m, "FBC enabled\n");
1663         else
1664                 seq_printf(m, "FBC disabled: %s\n",
1665                            dev_priv->fbc.no_fbc_reason);
1666
1667         if (INTEL_INFO(dev_priv)->gen >= 7)
1668                 seq_printf(m, "Compressing: %s\n",
1669                            yesno(I915_READ(FBC_STATUS2) &
1670                                  FBC_COMPRESSION_MASK));
1671
1672         mutex_unlock(&dev_priv->fbc.lock);
1673         intel_runtime_pm_put(dev_priv);
1674
1675         return 0;
1676 }
1677
1678 static int i915_fbc_fc_get(void *data, u64 *val)
1679 {
1680         struct drm_device *dev = data;
1681         struct drm_i915_private *dev_priv = dev->dev_private;
1682
1683         if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1684                 return -ENODEV;
1685
1686         *val = dev_priv->fbc.false_color;
1687
1688         return 0;
1689 }
1690
1691 static int i915_fbc_fc_set(void *data, u64 val)
1692 {
1693         struct drm_device *dev = data;
1694         struct drm_i915_private *dev_priv = dev->dev_private;
1695         u32 reg;
1696
1697         if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1698                 return -ENODEV;
1699
1700         mutex_lock(&dev_priv->fbc.lock);
1701
1702         reg = I915_READ(ILK_DPFC_CONTROL);
1703         dev_priv->fbc.false_color = val;
1704
1705         I915_WRITE(ILK_DPFC_CONTROL, val ?
1706                    (reg | FBC_CTL_FALSE_COLOR) :
1707                    (reg & ~FBC_CTL_FALSE_COLOR));
1708
1709         mutex_unlock(&dev_priv->fbc.lock);
1710         return 0;
1711 }
1712
1713 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1714                         i915_fbc_fc_get, i915_fbc_fc_set,
1715                         "%llu\n");
1716
1717 static int i915_ips_status(struct seq_file *m, void *unused)
1718 {
1719         struct drm_info_node *node = m->private;
1720         struct drm_device *dev = node->minor->dev;
1721         struct drm_i915_private *dev_priv = dev->dev_private;
1722
1723         if (!HAS_IPS(dev)) {
1724                 seq_puts(m, "not supported\n");
1725                 return 0;
1726         }
1727
1728         intel_runtime_pm_get(dev_priv);
1729
1730         seq_printf(m, "Enabled by kernel parameter: %s\n",
1731                    yesno(i915.enable_ips));
1732
1733         if (INTEL_INFO(dev)->gen >= 8) {
1734                 seq_puts(m, "Currently: unknown\n");
1735         } else {
1736                 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1737                         seq_puts(m, "Currently: enabled\n");
1738                 else
1739                         seq_puts(m, "Currently: disabled\n");
1740         }
1741
1742         intel_runtime_pm_put(dev_priv);
1743
1744         return 0;
1745 }
1746
1747 static int i915_sr_status(struct seq_file *m, void *unused)
1748 {
1749         struct drm_info_node *node = m->private;
1750         struct drm_device *dev = node->minor->dev;
1751         struct drm_i915_private *dev_priv = dev->dev_private;
1752         bool sr_enabled = false;
1753
1754         intel_runtime_pm_get(dev_priv);
1755
1756         if (HAS_PCH_SPLIT(dev))
1757                 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1758         else if (IS_CRESTLINE(dev) || IS_G4X(dev) ||
1759                  IS_I945G(dev) || IS_I945GM(dev))
1760                 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1761         else if (IS_I915GM(dev))
1762                 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1763         else if (IS_PINEVIEW(dev))
1764                 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1765         else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
1766                 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1767
1768         intel_runtime_pm_put(dev_priv);
1769
1770         seq_printf(m, "self-refresh: %s\n",
1771                    sr_enabled ? "enabled" : "disabled");
1772
1773         return 0;
1774 }
1775
1776 static int i915_emon_status(struct seq_file *m, void *unused)
1777 {
1778         struct drm_info_node *node = m->private;
1779         struct drm_device *dev = node->minor->dev;
1780         struct drm_i915_private *dev_priv = dev->dev_private;
1781         unsigned long temp, chipset, gfx;
1782         int ret;
1783
1784         if (!IS_GEN5(dev))
1785                 return -ENODEV;
1786
1787         ret = mutex_lock_interruptible(&dev->struct_mutex);
1788         if (ret)
1789                 return ret;
1790
1791         temp = i915_mch_val(dev_priv);
1792         chipset = i915_chipset_val(dev_priv);
1793         gfx = i915_gfx_val(dev_priv);
1794         mutex_unlock(&dev->struct_mutex);
1795
1796         seq_printf(m, "GMCH temp: %ld\n", temp);
1797         seq_printf(m, "Chipset power: %ld\n", chipset);
1798         seq_printf(m, "GFX power: %ld\n", gfx);
1799         seq_printf(m, "Total power: %ld\n", chipset + gfx);
1800
1801         return 0;
1802 }
1803
1804 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1805 {
1806         struct drm_info_node *node = m->private;
1807         struct drm_device *dev = node->minor->dev;
1808         struct drm_i915_private *dev_priv = dev->dev_private;
1809         int ret = 0;
1810         int gpu_freq, ia_freq;
1811         unsigned int max_gpu_freq, min_gpu_freq;
1812
1813         if (!HAS_CORE_RING_FREQ(dev)) {
1814                 seq_puts(m, "unsupported on this chipset\n");
1815                 return 0;
1816         }
1817
1818         intel_runtime_pm_get(dev_priv);
1819
1820         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1821
1822         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1823         if (ret)
1824                 goto out;
1825
1826         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
1827                 /* Convert GT frequency to 50 HZ units */
1828                 min_gpu_freq =
1829                         dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1830                 max_gpu_freq =
1831                         dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1832         } else {
1833                 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1834                 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1835         }
1836
1837         seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1838
1839         for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1840                 ia_freq = gpu_freq;
1841                 sandybridge_pcode_read(dev_priv,
1842                                        GEN6_PCODE_READ_MIN_FREQ_TABLE,
1843                                        &ia_freq);
1844                 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1845                            intel_gpu_freq(dev_priv, (gpu_freq *
1846                                 (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1847                                  GEN9_FREQ_SCALER : 1))),
1848                            ((ia_freq >> 0) & 0xff) * 100,
1849                            ((ia_freq >> 8) & 0xff) * 100);
1850         }
1851
1852         mutex_unlock(&dev_priv->rps.hw_lock);
1853
1854 out:
1855         intel_runtime_pm_put(dev_priv);
1856         return ret;
1857 }
1858
1859 static int i915_opregion(struct seq_file *m, void *unused)
1860 {
1861         struct drm_info_node *node = m->private;
1862         struct drm_device *dev = node->minor->dev;
1863         struct drm_i915_private *dev_priv = dev->dev_private;
1864         struct intel_opregion *opregion = &dev_priv->opregion;
1865         int ret;
1866
1867         ret = mutex_lock_interruptible(&dev->struct_mutex);
1868         if (ret)
1869                 goto out;
1870
1871         if (opregion->header)
1872                 seq_write(m, opregion->header, OPREGION_SIZE);
1873
1874         mutex_unlock(&dev->struct_mutex);
1875
1876 out:
1877         return 0;
1878 }
1879
1880 static int i915_vbt(struct seq_file *m, void *unused)
1881 {
1882         struct drm_info_node *node = m->private;
1883         struct drm_device *dev = node->minor->dev;
1884         struct drm_i915_private *dev_priv = dev->dev_private;
1885         struct intel_opregion *opregion = &dev_priv->opregion;
1886
1887         if (opregion->vbt)
1888                 seq_write(m, opregion->vbt, opregion->vbt_size);
1889
1890         return 0;
1891 }
1892
1893 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1894 {
1895         struct drm_info_node *node = m->private;
1896         struct drm_device *dev = node->minor->dev;
1897         struct intel_framebuffer *fbdev_fb = NULL;
1898         struct drm_framebuffer *drm_fb;
1899         int ret;
1900
1901         ret = mutex_lock_interruptible(&dev->struct_mutex);
1902         if (ret)
1903                 return ret;
1904
1905 #ifdef CONFIG_DRM_FBDEV_EMULATION
1906        if (to_i915(dev)->fbdev) {
1907                fbdev_fb = to_intel_framebuffer(to_i915(dev)->fbdev->helper.fb);
1908
1909                seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1910                          fbdev_fb->base.width,
1911                          fbdev_fb->base.height,
1912                          fbdev_fb->base.depth,
1913                          fbdev_fb->base.bits_per_pixel,
1914                          fbdev_fb->base.modifier[0],
1915                          atomic_read(&fbdev_fb->base.refcount.refcount));
1916                describe_obj(m, fbdev_fb->obj);
1917                seq_putc(m, '\n');
1918        }
1919 #endif
1920
1921         mutex_lock(&dev->mode_config.fb_lock);
1922         drm_for_each_fb(drm_fb, dev) {
1923                 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
1924                 if (fb == fbdev_fb)
1925                         continue;
1926
1927                 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1928                            fb->base.width,
1929                            fb->base.height,
1930                            fb->base.depth,
1931                            fb->base.bits_per_pixel,
1932                            fb->base.modifier[0],
1933                            atomic_read(&fb->base.refcount.refcount));
1934                 describe_obj(m, fb->obj);
1935                 seq_putc(m, '\n');
1936         }
1937         mutex_unlock(&dev->mode_config.fb_lock);
1938         mutex_unlock(&dev->struct_mutex);
1939
1940         return 0;
1941 }
1942
1943 static void describe_ctx_ringbuf(struct seq_file *m,
1944                                  struct intel_ringbuffer *ringbuf)
1945 {
1946         seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1947                    ringbuf->space, ringbuf->head, ringbuf->tail,
1948                    ringbuf->last_retired_head);
1949 }
1950
1951 static int i915_context_status(struct seq_file *m, void *unused)
1952 {
1953         struct drm_info_node *node = m->private;
1954         struct drm_device *dev = node->minor->dev;
1955         struct drm_i915_private *dev_priv = dev->dev_private;
1956         struct intel_engine_cs *engine;
1957         struct intel_context *ctx;
1958         enum intel_engine_id id;
1959         int ret;
1960
1961         ret = mutex_lock_interruptible(&dev->struct_mutex);
1962         if (ret)
1963                 return ret;
1964
1965         list_for_each_entry(ctx, &dev_priv->context_list, link) {
1966                 if (!i915.enable_execlists &&
1967                     ctx->legacy_hw_ctx.rcs_state == NULL)
1968                         continue;
1969
1970                 seq_puts(m, "HW context ");
1971                 describe_ctx(m, ctx);
1972                 if (ctx == dev_priv->kernel_context)
1973                         seq_printf(m, "(kernel context) ");
1974
1975                 if (i915.enable_execlists) {
1976                         seq_putc(m, '\n');
1977                         for_each_engine_id(engine, dev_priv, id) {
1978                                 struct drm_i915_gem_object *ctx_obj =
1979                                         ctx->engine[id].state;
1980                                 struct intel_ringbuffer *ringbuf =
1981                                         ctx->engine[id].ringbuf;
1982
1983                                 seq_printf(m, "%s: ", engine->name);
1984                                 if (ctx_obj)
1985                                         describe_obj(m, ctx_obj);
1986                                 if (ringbuf)
1987                                         describe_ctx_ringbuf(m, ringbuf);
1988                                 seq_putc(m, '\n');
1989                         }
1990                 } else {
1991                         describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1992                 }
1993
1994                 seq_putc(m, '\n');
1995         }
1996
1997         mutex_unlock(&dev->struct_mutex);
1998
1999         return 0;
2000 }
2001
2002 static void i915_dump_lrc_obj(struct seq_file *m,
2003                               struct intel_context *ctx,
2004                               struct intel_engine_cs *engine)
2005 {
2006         struct page *page;
2007         uint32_t *reg_state;
2008         int j;
2009         struct drm_i915_gem_object *ctx_obj = ctx->engine[engine->id].state;
2010         unsigned long ggtt_offset = 0;
2011
2012         if (ctx_obj == NULL) {
2013                 seq_printf(m, "Context on %s with no gem object\n",
2014                            engine->name);
2015                 return;
2016         }
2017
2018         seq_printf(m, "CONTEXT: %s %u\n", engine->name,
2019                    intel_execlists_ctx_id(ctx, engine));
2020
2021         if (!i915_gem_obj_ggtt_bound(ctx_obj))
2022                 seq_puts(m, "\tNot bound in GGTT\n");
2023         else
2024                 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
2025
2026         if (i915_gem_object_get_pages(ctx_obj)) {
2027                 seq_puts(m, "\tFailed to get pages for context object\n");
2028                 return;
2029         }
2030
2031         page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
2032         if (!WARN_ON(page == NULL)) {
2033                 reg_state = kmap_atomic(page);
2034
2035                 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2036                         seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2037                                    ggtt_offset + 4096 + (j * 4),
2038                                    reg_state[j], reg_state[j + 1],
2039                                    reg_state[j + 2], reg_state[j + 3]);
2040                 }
2041                 kunmap_atomic(reg_state);
2042         }
2043
2044         seq_putc(m, '\n');
2045 }
2046
2047 static int i915_dump_lrc(struct seq_file *m, void *unused)
2048 {
2049         struct drm_info_node *node = (struct drm_info_node *) m->private;
2050         struct drm_device *dev = node->minor->dev;
2051         struct drm_i915_private *dev_priv = dev->dev_private;
2052         struct intel_engine_cs *engine;
2053         struct intel_context *ctx;
2054         int ret;
2055
2056         if (!i915.enable_execlists) {
2057                 seq_printf(m, "Logical Ring Contexts are disabled\n");
2058                 return 0;
2059         }
2060
2061         ret = mutex_lock_interruptible(&dev->struct_mutex);
2062         if (ret)
2063                 return ret;
2064
2065         list_for_each_entry(ctx, &dev_priv->context_list, link)
2066                 if (ctx != dev_priv->kernel_context)
2067                         for_each_engine(engine, dev_priv)
2068                                 i915_dump_lrc_obj(m, ctx, engine);
2069
2070         mutex_unlock(&dev->struct_mutex);
2071
2072         return 0;
2073 }
2074
2075 static int i915_execlists(struct seq_file *m, void *data)
2076 {
2077         struct drm_info_node *node = (struct drm_info_node *)m->private;
2078         struct drm_device *dev = node->minor->dev;
2079         struct drm_i915_private *dev_priv = dev->dev_private;
2080         struct intel_engine_cs *engine;
2081         u32 status_pointer;
2082         u8 read_pointer;
2083         u8 write_pointer;
2084         u32 status;
2085         u32 ctx_id;
2086         struct list_head *cursor;
2087         int i, ret;
2088
2089         if (!i915.enable_execlists) {
2090                 seq_puts(m, "Logical Ring Contexts are disabled\n");
2091                 return 0;
2092         }
2093
2094         ret = mutex_lock_interruptible(&dev->struct_mutex);
2095         if (ret)
2096                 return ret;
2097
2098         intel_runtime_pm_get(dev_priv);
2099
2100         for_each_engine(engine, dev_priv) {
2101                 struct drm_i915_gem_request *head_req = NULL;
2102                 int count = 0;
2103
2104                 seq_printf(m, "%s\n", engine->name);
2105
2106                 status = I915_READ(RING_EXECLIST_STATUS_LO(engine));
2107                 ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(engine));
2108                 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2109                            status, ctx_id);
2110
2111                 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
2112                 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2113
2114                 read_pointer = engine->next_context_status_buffer;
2115                 write_pointer = GEN8_CSB_WRITE_PTR(status_pointer);
2116                 if (read_pointer > write_pointer)
2117                         write_pointer += GEN8_CSB_ENTRIES;
2118                 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2119                            read_pointer, write_pointer);
2120
2121                 for (i = 0; i < GEN8_CSB_ENTRIES; i++) {
2122                         status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, i));
2123                         ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, i));
2124
2125                         seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2126                                    i, status, ctx_id);
2127                 }
2128
2129                 spin_lock_bh(&engine->execlist_lock);
2130                 list_for_each(cursor, &engine->execlist_queue)
2131                         count++;
2132                 head_req = list_first_entry_or_null(&engine->execlist_queue,
2133                                                     struct drm_i915_gem_request,
2134                                                     execlist_link);
2135                 spin_unlock_bh(&engine->execlist_lock);
2136
2137                 seq_printf(m, "\t%d requests in queue\n", count);
2138                 if (head_req) {
2139                         seq_printf(m, "\tHead request id: %u\n",
2140                                    intel_execlists_ctx_id(head_req->ctx, engine));
2141                         seq_printf(m, "\tHead request tail: %u\n",
2142                                    head_req->tail);
2143                 }
2144
2145                 seq_putc(m, '\n');
2146         }
2147
2148         intel_runtime_pm_put(dev_priv);
2149         mutex_unlock(&dev->struct_mutex);
2150
2151         return 0;
2152 }
2153
2154 static const char *swizzle_string(unsigned swizzle)
2155 {
2156         switch (swizzle) {
2157         case I915_BIT_6_SWIZZLE_NONE:
2158                 return "none";
2159         case I915_BIT_6_SWIZZLE_9:
2160                 return "bit9";
2161         case I915_BIT_6_SWIZZLE_9_10:
2162                 return "bit9/bit10";
2163         case I915_BIT_6_SWIZZLE_9_11:
2164                 return "bit9/bit11";
2165         case I915_BIT_6_SWIZZLE_9_10_11:
2166                 return "bit9/bit10/bit11";
2167         case I915_BIT_6_SWIZZLE_9_17:
2168                 return "bit9/bit17";
2169         case I915_BIT_6_SWIZZLE_9_10_17:
2170                 return "bit9/bit10/bit17";
2171         case I915_BIT_6_SWIZZLE_UNKNOWN:
2172                 return "unknown";
2173         }
2174
2175         return "bug";
2176 }
2177
2178 static int i915_swizzle_info(struct seq_file *m, void *data)
2179 {
2180         struct drm_info_node *node = m->private;
2181         struct drm_device *dev = node->minor->dev;
2182         struct drm_i915_private *dev_priv = dev->dev_private;
2183         int ret;
2184
2185         ret = mutex_lock_interruptible(&dev->struct_mutex);
2186         if (ret)
2187                 return ret;
2188         intel_runtime_pm_get(dev_priv);
2189
2190         seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2191                    swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2192         seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2193                    swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2194
2195         if (IS_GEN3(dev) || IS_GEN4(dev)) {
2196                 seq_printf(m, "DDC = 0x%08x\n",
2197                            I915_READ(DCC));
2198                 seq_printf(m, "DDC2 = 0x%08x\n",
2199                            I915_READ(DCC2));
2200                 seq_printf(m, "C0DRB3 = 0x%04x\n",
2201                            I915_READ16(C0DRB3));
2202                 seq_printf(m, "C1DRB3 = 0x%04x\n",
2203                            I915_READ16(C1DRB3));
2204         } else if (INTEL_INFO(dev)->gen >= 6) {
2205                 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2206                            I915_READ(MAD_DIMM_C0));
2207                 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2208                            I915_READ(MAD_DIMM_C1));
2209                 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2210                            I915_READ(MAD_DIMM_C2));
2211                 seq_printf(m, "TILECTL = 0x%08x\n",
2212                            I915_READ(TILECTL));
2213                 if (INTEL_INFO(dev)->gen >= 8)
2214                         seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2215                                    I915_READ(GAMTARBMODE));
2216                 else
2217                         seq_printf(m, "ARB_MODE = 0x%08x\n",
2218                                    I915_READ(ARB_MODE));
2219                 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2220                            I915_READ(DISP_ARB_CTL));
2221         }
2222
2223         if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2224                 seq_puts(m, "L-shaped memory detected\n");
2225
2226         intel_runtime_pm_put(dev_priv);
2227         mutex_unlock(&dev->struct_mutex);
2228
2229         return 0;
2230 }
2231
2232 static int per_file_ctx(int id, void *ptr, void *data)
2233 {
2234         struct intel_context *ctx = ptr;
2235         struct seq_file *m = data;
2236         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2237
2238         if (!ppgtt) {
2239                 seq_printf(m, "  no ppgtt for context %d\n",
2240                            ctx->user_handle);
2241                 return 0;
2242         }
2243
2244         if (i915_gem_context_is_default(ctx))
2245                 seq_puts(m, "  default context:\n");
2246         else
2247                 seq_printf(m, "  context %d:\n", ctx->user_handle);
2248         ppgtt->debug_dump(ppgtt, m);
2249
2250         return 0;
2251 }
2252
2253 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2254 {
2255         struct drm_i915_private *dev_priv = dev->dev_private;
2256         struct intel_engine_cs *engine;
2257         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2258         int i;
2259
2260         if (!ppgtt)
2261                 return;
2262
2263         for_each_engine(engine, dev_priv) {
2264                 seq_printf(m, "%s\n", engine->name);
2265                 for (i = 0; i < 4; i++) {
2266                         u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
2267                         pdp <<= 32;
2268                         pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
2269                         seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2270                 }
2271         }
2272 }
2273
2274 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2275 {
2276         struct drm_i915_private *dev_priv = dev->dev_private;
2277         struct intel_engine_cs *engine;
2278
2279         if (INTEL_INFO(dev)->gen == 6)
2280                 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2281
2282         for_each_engine(engine, dev_priv) {
2283                 seq_printf(m, "%s\n", engine->name);
2284                 if (INTEL_INFO(dev)->gen == 7)
2285                         seq_printf(m, "GFX_MODE: 0x%08x\n",
2286                                    I915_READ(RING_MODE_GEN7(engine)));
2287                 seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
2288                            I915_READ(RING_PP_DIR_BASE(engine)));
2289                 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
2290                            I915_READ(RING_PP_DIR_BASE_READ(engine)));
2291                 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
2292                            I915_READ(RING_PP_DIR_DCLV(engine)));
2293         }
2294         if (dev_priv->mm.aliasing_ppgtt) {
2295                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2296
2297                 seq_puts(m, "aliasing PPGTT:\n");
2298                 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2299
2300                 ppgtt->debug_dump(ppgtt, m);
2301         }
2302
2303         seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2304 }
2305
2306 static int i915_ppgtt_info(struct seq_file *m, void *data)
2307 {
2308         struct drm_info_node *node = m->private;
2309         struct drm_device *dev = node->minor->dev;
2310         struct drm_i915_private *dev_priv = dev->dev_private;
2311         struct drm_file *file;
2312
2313         int ret = mutex_lock_interruptible(&dev->struct_mutex);
2314         if (ret)
2315                 return ret;
2316         intel_runtime_pm_get(dev_priv);
2317
2318         if (INTEL_INFO(dev)->gen >= 8)
2319                 gen8_ppgtt_info(m, dev);
2320         else if (INTEL_INFO(dev)->gen >= 6)
2321                 gen6_ppgtt_info(m, dev);
2322
2323         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2324                 struct drm_i915_file_private *file_priv = file->driver_priv;
2325                 struct task_struct *task;
2326
2327                 task = get_pid_task(file->pid, PIDTYPE_PID);
2328                 if (!task) {
2329                         ret = -ESRCH;
2330                         goto out_put;
2331                 }
2332                 seq_printf(m, "\nproc: %s\n", task->comm);
2333                 put_task_struct(task);
2334                 idr_for_each(&file_priv->context_idr, per_file_ctx,
2335                              (void *)(unsigned long)m);
2336         }
2337
2338 out_put:
2339         intel_runtime_pm_put(dev_priv);
2340         mutex_unlock(&dev->struct_mutex);
2341
2342         return ret;
2343 }
2344
2345 static int count_irq_waiters(struct drm_i915_private *i915)
2346 {
2347         struct intel_engine_cs *engine;
2348         int count = 0;
2349
2350         for_each_engine(engine, i915)
2351                 count += engine->irq_refcount;
2352
2353         return count;
2354 }
2355
2356 static int i915_rps_boost_info(struct seq_file *m, void *data)
2357 {
2358         struct drm_info_node *node = m->private;
2359         struct drm_device *dev = node->minor->dev;
2360         struct drm_i915_private *dev_priv = dev->dev_private;
2361         struct drm_file *file;
2362
2363         seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2364         seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy);
2365         seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2366         seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2367                    intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2368                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2369                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2370                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2371                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2372         spin_lock(&dev_priv->rps.client_lock);
2373         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2374                 struct drm_i915_file_private *file_priv = file->driver_priv;
2375                 struct task_struct *task;
2376
2377                 rcu_read_lock();
2378                 task = pid_task(file->pid, PIDTYPE_PID);
2379                 seq_printf(m, "%s [%d]: %d boosts%s\n",
2380                            task ? task->comm : "<unknown>",
2381                            task ? task->pid : -1,
2382                            file_priv->rps.boosts,
2383                            list_empty(&file_priv->rps.link) ? "" : ", active");
2384                 rcu_read_unlock();
2385         }
2386         seq_printf(m, "Semaphore boosts: %d%s\n",
2387                    dev_priv->rps.semaphores.boosts,
2388                    list_empty(&dev_priv->rps.semaphores.link) ? "" : ", active");
2389         seq_printf(m, "MMIO flip boosts: %d%s\n",
2390                    dev_priv->rps.mmioflips.boosts,
2391                    list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active");
2392         seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts);
2393         spin_unlock(&dev_priv->rps.client_lock);
2394
2395         return 0;
2396 }
2397
2398 static int i915_llc(struct seq_file *m, void *data)
2399 {
2400         struct drm_info_node *node = m->private;
2401         struct drm_device *dev = node->minor->dev;
2402         struct drm_i915_private *dev_priv = dev->dev_private;
2403
2404         /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2405         seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2406         seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2407
2408         return 0;
2409 }
2410
2411 static int i915_guc_load_status_info(struct seq_file *m, void *data)
2412 {
2413         struct drm_info_node *node = m->private;
2414         struct drm_i915_private *dev_priv = node->minor->dev->dev_private;
2415         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
2416         u32 tmp, i;
2417
2418         if (!HAS_GUC_UCODE(dev_priv->dev))
2419                 return 0;
2420
2421         seq_printf(m, "GuC firmware status:\n");
2422         seq_printf(m, "\tpath: %s\n",
2423                 guc_fw->guc_fw_path);
2424         seq_printf(m, "\tfetch: %s\n",
2425                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
2426         seq_printf(m, "\tload: %s\n",
2427                 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
2428         seq_printf(m, "\tversion wanted: %d.%d\n",
2429                 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2430         seq_printf(m, "\tversion found: %d.%d\n",
2431                 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
2432         seq_printf(m, "\theader: offset is %d; size = %d\n",
2433                 guc_fw->header_offset, guc_fw->header_size);
2434         seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2435                 guc_fw->ucode_offset, guc_fw->ucode_size);
2436         seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2437                 guc_fw->rsa_offset, guc_fw->rsa_size);
2438
2439         tmp = I915_READ(GUC_STATUS);
2440
2441         seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2442         seq_printf(m, "\tBootrom status = 0x%x\n",
2443                 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2444         seq_printf(m, "\tuKernel status = 0x%x\n",
2445                 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2446         seq_printf(m, "\tMIA Core status = 0x%x\n",
2447                 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2448         seq_puts(m, "\nScratch registers:\n");
2449         for (i = 0; i < 16; i++)
2450                 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2451
2452         return 0;
2453 }
2454
2455 static void i915_guc_client_info(struct seq_file *m,
2456                                  struct drm_i915_private *dev_priv,
2457                                  struct i915_guc_client *client)
2458 {
2459         struct intel_engine_cs *engine;
2460         uint64_t tot = 0;
2461
2462         seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2463                 client->priority, client->ctx_index, client->proc_desc_offset);
2464         seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2465                 client->doorbell_id, client->doorbell_offset, client->cookie);
2466         seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2467                 client->wq_size, client->wq_offset, client->wq_tail);
2468
2469         seq_printf(m, "\tFailed to queue: %u\n", client->q_fail);
2470         seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2471         seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2472
2473         for_each_engine(engine, dev_priv) {
2474                 seq_printf(m, "\tSubmissions: %llu %s\n",
2475                                 client->submissions[engine->guc_id],
2476                                 engine->name);
2477                 tot += client->submissions[engine->guc_id];
2478         }
2479         seq_printf(m, "\tTotal: %llu\n", tot);
2480 }
2481
2482 static int i915_guc_info(struct seq_file *m, void *data)
2483 {
2484         struct drm_info_node *node = m->private;
2485         struct drm_device *dev = node->minor->dev;
2486         struct drm_i915_private *dev_priv = dev->dev_private;
2487         struct intel_guc guc;
2488         struct i915_guc_client client = {};
2489         struct intel_engine_cs *engine;
2490         u64 total = 0;
2491
2492         if (!HAS_GUC_SCHED(dev_priv->dev))
2493                 return 0;
2494
2495         if (mutex_lock_interruptible(&dev->struct_mutex))
2496                 return 0;
2497
2498         /* Take a local copy of the GuC data, so we can dump it at leisure */
2499         guc = dev_priv->guc;
2500         if (guc.execbuf_client)
2501                 client = *guc.execbuf_client;
2502
2503         mutex_unlock(&dev->struct_mutex);
2504
2505         seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
2506         seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
2507         seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
2508         seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
2509         seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
2510
2511         seq_printf(m, "\nGuC submissions:\n");
2512         for_each_engine(engine, dev_priv) {
2513                 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",
2514                         engine->name, guc.submissions[engine->guc_id],
2515                         guc.last_seqno[engine->guc_id]);
2516                 total += guc.submissions[engine->guc_id];
2517         }
2518         seq_printf(m, "\t%s: %llu\n", "Total", total);
2519
2520         seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
2521         i915_guc_client_info(m, dev_priv, &client);
2522
2523         /* Add more as required ... */
2524
2525         return 0;
2526 }
2527
2528 static int i915_guc_log_dump(struct seq_file *m, void *data)
2529 {
2530         struct drm_info_node *node = m->private;
2531         struct drm_device *dev = node->minor->dev;
2532         struct drm_i915_private *dev_priv = dev->dev_private;
2533         struct drm_i915_gem_object *log_obj = dev_priv->guc.log_obj;
2534         u32 *log;
2535         int i = 0, pg;
2536
2537         if (!log_obj)
2538                 return 0;
2539
2540         for (pg = 0; pg < log_obj->base.size / PAGE_SIZE; pg++) {
2541                 log = kmap_atomic(i915_gem_object_get_page(log_obj, pg));
2542
2543                 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2544                         seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2545                                    *(log + i), *(log + i + 1),
2546                                    *(log + i + 2), *(log + i + 3));
2547
2548                 kunmap_atomic(log);
2549         }
2550
2551         seq_putc(m, '\n');
2552
2553         return 0;
2554 }
2555
2556 static int i915_edp_psr_status(struct seq_file *m, void *data)
2557 {
2558         struct drm_info_node *node = m->private;
2559         struct drm_device *dev = node->minor->dev;
2560         struct drm_i915_private *dev_priv = dev->dev_private;
2561         u32 psrperf = 0;
2562         u32 stat[3];
2563         enum pipe pipe;
2564         bool enabled = false;
2565
2566         if (!HAS_PSR(dev)) {
2567                 seq_puts(m, "PSR not supported\n");
2568                 return 0;
2569         }
2570
2571         intel_runtime_pm_get(dev_priv);
2572
2573         mutex_lock(&dev_priv->psr.lock);
2574         seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2575         seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2576         seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2577         seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2578         seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2579                    dev_priv->psr.busy_frontbuffer_bits);
2580         seq_printf(m, "Re-enable work scheduled: %s\n",
2581                    yesno(work_busy(&dev_priv->psr.work.work)));
2582
2583         if (HAS_DDI(dev))
2584                 enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2585         else {
2586                 for_each_pipe(dev_priv, pipe) {
2587                         stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2588                                 VLV_EDP_PSR_CURR_STATE_MASK;
2589                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2590                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2591                                 enabled = true;
2592                 }
2593         }
2594
2595         seq_printf(m, "Main link in standby mode: %s\n",
2596                    yesno(dev_priv->psr.link_standby));
2597
2598         seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2599
2600         if (!HAS_DDI(dev))
2601                 for_each_pipe(dev_priv, pipe) {
2602                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2603                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2604                                 seq_printf(m, " pipe %c", pipe_name(pipe));
2605                 }
2606         seq_puts(m, "\n");
2607
2608         /*
2609          * VLV/CHV PSR has no kind of performance counter
2610          * SKL+ Perf counter is reset to 0 everytime DC state is entered
2611          */
2612         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2613                 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
2614                         EDP_PSR_PERF_CNT_MASK;
2615
2616                 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2617         }
2618         mutex_unlock(&dev_priv->psr.lock);
2619
2620         intel_runtime_pm_put(dev_priv);
2621         return 0;
2622 }
2623
2624 static int i915_sink_crc(struct seq_file *m, void *data)
2625 {
2626         struct drm_info_node *node = m->private;
2627         struct drm_device *dev = node->minor->dev;
2628         struct intel_encoder *encoder;
2629         struct intel_connector *connector;
2630         struct intel_dp *intel_dp = NULL;
2631         int ret;
2632         u8 crc[6];
2633
2634         drm_modeset_lock_all(dev);
2635         for_each_intel_connector(dev, connector) {
2636
2637                 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2638                         continue;
2639
2640                 if (!connector->base.encoder)
2641                         continue;
2642
2643                 encoder = to_intel_encoder(connector->base.encoder);
2644                 if (encoder->type != INTEL_OUTPUT_EDP)
2645                         continue;
2646
2647                 intel_dp = enc_to_intel_dp(&encoder->base);
2648
2649                 ret = intel_dp_sink_crc(intel_dp, crc);
2650                 if (ret)
2651                         goto out;
2652
2653                 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2654                            crc[0], crc[1], crc[2],
2655                            crc[3], crc[4], crc[5]);
2656                 goto out;
2657         }
2658         ret = -ENODEV;
2659 out:
2660         drm_modeset_unlock_all(dev);
2661         return ret;
2662 }
2663
2664 static int i915_energy_uJ(struct seq_file *m, void *data)
2665 {
2666         struct drm_info_node *node = m->private;
2667         struct drm_device *dev = node->minor->dev;
2668         struct drm_i915_private *dev_priv = dev->dev_private;
2669         u64 power;
2670         u32 units;
2671
2672         if (INTEL_INFO(dev)->gen < 6)
2673                 return -ENODEV;
2674
2675         intel_runtime_pm_get(dev_priv);
2676
2677         rdmsrl(MSR_RAPL_POWER_UNIT, power);
2678         power = (power & 0x1f00) >> 8;
2679         units = 1000000 / (1 << power); /* convert to uJ */
2680         power = I915_READ(MCH_SECP_NRG_STTS);
2681         power *= units;
2682
2683         intel_runtime_pm_put(dev_priv);
2684
2685         seq_printf(m, "%llu", (long long unsigned)power);
2686
2687         return 0;
2688 }
2689
2690 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2691 {
2692         struct drm_info_node *node = m->private;
2693         struct drm_device *dev = node->minor->dev;
2694         struct drm_i915_private *dev_priv = dev->dev_private;
2695
2696         if (!HAS_RUNTIME_PM(dev_priv))
2697                 seq_puts(m, "Runtime power management not supported\n");
2698
2699         seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
2700         seq_printf(m, "IRQs disabled: %s\n",
2701                    yesno(!intel_irqs_enabled(dev_priv)));
2702 #ifdef CONFIG_PM
2703         seq_printf(m, "Usage count: %d\n",
2704                    atomic_read(&dev->dev->power.usage_count));
2705 #else
2706         seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2707 #endif
2708         seq_printf(m, "PCI device power state: %s [%d]\n",
2709                    pci_power_name(dev_priv->dev->pdev->current_state),
2710                    dev_priv->dev->pdev->current_state);
2711
2712         return 0;
2713 }
2714
2715 static int i915_power_domain_info(struct seq_file *m, void *unused)
2716 {
2717         struct drm_info_node *node = m->private;
2718         struct drm_device *dev = node->minor->dev;
2719         struct drm_i915_private *dev_priv = dev->dev_private;
2720         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2721         int i;
2722
2723         mutex_lock(&power_domains->lock);
2724
2725         seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2726         for (i = 0; i < power_domains->power_well_count; i++) {
2727                 struct i915_power_well *power_well;
2728                 enum intel_display_power_domain power_domain;
2729
2730                 power_well = &power_domains->power_wells[i];
2731                 seq_printf(m, "%-25s %d\n", power_well->name,
2732                            power_well->count);
2733
2734                 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2735                      power_domain++) {
2736                         if (!(BIT(power_domain) & power_well->domains))
2737                                 continue;
2738
2739                         seq_printf(m, "  %-23s %d\n",
2740                                  intel_display_power_domain_str(power_domain),
2741                                  power_domains->domain_use_count[power_domain]);
2742                 }
2743         }
2744
2745         mutex_unlock(&power_domains->lock);
2746
2747         return 0;
2748 }
2749
2750 static int i915_dmc_info(struct seq_file *m, void *unused)
2751 {
2752         struct drm_info_node *node = m->private;
2753         struct drm_device *dev = node->minor->dev;
2754         struct drm_i915_private *dev_priv = dev->dev_private;
2755         struct intel_csr *csr;
2756
2757         if (!HAS_CSR(dev)) {
2758                 seq_puts(m, "not supported\n");
2759                 return 0;
2760         }
2761
2762         csr = &dev_priv->csr;
2763
2764         intel_runtime_pm_get(dev_priv);
2765
2766         seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2767         seq_printf(m, "path: %s\n", csr->fw_path);
2768
2769         if (!csr->dmc_payload)
2770                 goto out;
2771
2772         seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2773                    CSR_VERSION_MINOR(csr->version));
2774
2775         if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) {
2776                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2777                            I915_READ(SKL_CSR_DC3_DC5_COUNT));
2778                 seq_printf(m, "DC5 -> DC6 count: %d\n",
2779                            I915_READ(SKL_CSR_DC5_DC6_COUNT));
2780         } else if (IS_BROXTON(dev) && csr->version >= CSR_VERSION(1, 4)) {
2781                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2782                            I915_READ(BXT_CSR_DC3_DC5_COUNT));
2783         }
2784
2785 out:
2786         seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2787         seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2788         seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2789
2790         intel_runtime_pm_put(dev_priv);
2791
2792         return 0;
2793 }
2794
2795 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2796                                  struct drm_display_mode *mode)
2797 {
2798         int i;
2799
2800         for (i = 0; i < tabs; i++)
2801                 seq_putc(m, '\t');
2802
2803         seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2804                    mode->base.id, mode->name,
2805                    mode->vrefresh, mode->clock,
2806                    mode->hdisplay, mode->hsync_start,
2807                    mode->hsync_end, mode->htotal,
2808                    mode->vdisplay, mode->vsync_start,
2809                    mode->vsync_end, mode->vtotal,
2810                    mode->type, mode->flags);
2811 }
2812
2813 static void intel_encoder_info(struct seq_file *m,
2814                                struct intel_crtc *intel_crtc,
2815                                struct intel_encoder *intel_encoder)
2816 {
2817         struct drm_info_node *node = m->private;
2818         struct drm_device *dev = node->minor->dev;
2819         struct drm_crtc *crtc = &intel_crtc->base;
2820         struct intel_connector *intel_connector;
2821         struct drm_encoder *encoder;
2822
2823         encoder = &intel_encoder->base;
2824         seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2825                    encoder->base.id, encoder->name);
2826         for_each_connector_on_encoder(dev, encoder, intel_connector) {
2827                 struct drm_connector *connector = &intel_connector->base;
2828                 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2829                            connector->base.id,
2830                            connector->name,
2831                            drm_get_connector_status_name(connector->status));
2832                 if (connector->status == connector_status_connected) {
2833                         struct drm_display_mode *mode = &crtc->mode;
2834                         seq_printf(m, ", mode:\n");
2835                         intel_seq_print_mode(m, 2, mode);
2836                 } else {
2837                         seq_putc(m, '\n');
2838                 }
2839         }
2840 }
2841
2842 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2843 {
2844         struct drm_info_node *node = m->private;
2845         struct drm_device *dev = node->minor->dev;
2846         struct drm_crtc *crtc = &intel_crtc->base;
2847         struct intel_encoder *intel_encoder;
2848         struct drm_plane_state *plane_state = crtc->primary->state;
2849         struct drm_framebuffer *fb = plane_state->fb;
2850
2851         if (fb)
2852                 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2853                            fb->base.id, plane_state->src_x >> 16,
2854                            plane_state->src_y >> 16, fb->width, fb->height);
2855         else
2856                 seq_puts(m, "\tprimary plane disabled\n");
2857         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2858                 intel_encoder_info(m, intel_crtc, intel_encoder);
2859 }
2860
2861 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2862 {
2863         struct drm_display_mode *mode = panel->fixed_mode;
2864
2865         seq_printf(m, "\tfixed mode:\n");
2866         intel_seq_print_mode(m, 2, mode);
2867 }
2868
2869 static void intel_dp_info(struct seq_file *m,
2870                           struct intel_connector *intel_connector)
2871 {
2872         struct intel_encoder *intel_encoder = intel_connector->encoder;
2873         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2874
2875         seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2876         seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2877         if (intel_encoder->type == INTEL_OUTPUT_EDP)
2878                 intel_panel_info(m, &intel_connector->panel);
2879 }
2880
2881 static void intel_dp_mst_info(struct seq_file *m,
2882                           struct intel_connector *intel_connector)
2883 {
2884         struct intel_encoder *intel_encoder = intel_connector->encoder;
2885         struct intel_dp_mst_encoder *intel_mst =
2886                 enc_to_mst(&intel_encoder->base);
2887         struct intel_digital_port *intel_dig_port = intel_mst->primary;
2888         struct intel_dp *intel_dp = &intel_dig_port->dp;
2889         bool has_audio = drm_dp_mst_port_has_audio(&intel_dp->mst_mgr,
2890                                         intel_connector->port);
2891
2892         seq_printf(m, "\taudio support: %s\n", yesno(has_audio));
2893 }
2894
2895 static void intel_hdmi_info(struct seq_file *m,
2896                             struct intel_connector *intel_connector)
2897 {
2898         struct intel_encoder *intel_encoder = intel_connector->encoder;
2899         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2900
2901         seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
2902 }
2903
2904 static void intel_lvds_info(struct seq_file *m,
2905                             struct intel_connector *intel_connector)
2906 {
2907         intel_panel_info(m, &intel_connector->panel);
2908 }
2909
2910 static void intel_connector_info(struct seq_file *m,
2911                                  struct drm_connector *connector)
2912 {
2913         struct intel_connector *intel_connector = to_intel_connector(connector);
2914         struct intel_encoder *intel_encoder = intel_connector->encoder;
2915         struct drm_display_mode *mode;
2916
2917         seq_printf(m, "connector %d: type %s, status: %s\n",
2918                    connector->base.id, connector->name,
2919                    drm_get_connector_status_name(connector->status));
2920         if (connector->status == connector_status_connected) {
2921                 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2922                 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2923                            connector->display_info.width_mm,
2924                            connector->display_info.height_mm);
2925                 seq_printf(m, "\tsubpixel order: %s\n",
2926                            drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2927                 seq_printf(m, "\tCEA rev: %d\n",
2928                            connector->display_info.cea_rev);
2929         }
2930         if (intel_encoder) {
2931                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2932                     intel_encoder->type == INTEL_OUTPUT_EDP)
2933                         intel_dp_info(m, intel_connector);
2934                 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2935                         intel_hdmi_info(m, intel_connector);
2936                 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2937                         intel_lvds_info(m, intel_connector);
2938                 else if (intel_encoder->type == INTEL_OUTPUT_DP_MST)
2939                         intel_dp_mst_info(m, intel_connector);
2940         }
2941
2942         seq_printf(m, "\tmodes:\n");
2943         list_for_each_entry(mode, &connector->modes, head)
2944                 intel_seq_print_mode(m, 2, mode);
2945 }
2946
2947 static bool cursor_active(struct drm_device *dev, int pipe)
2948 {
2949         struct drm_i915_private *dev_priv = dev->dev_private;
2950         u32 state;
2951
2952         if (IS_845G(dev) || IS_I865G(dev))
2953                 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
2954         else
2955                 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2956
2957         return state;
2958 }
2959
2960 static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2961 {
2962         struct drm_i915_private *dev_priv = dev->dev_private;
2963         u32 pos;
2964
2965         pos = I915_READ(CURPOS(pipe));
2966
2967         *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2968         if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2969                 *x = -*x;
2970
2971         *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2972         if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2973                 *y = -*y;
2974
2975         return cursor_active(dev, pipe);
2976 }
2977
2978 static const char *plane_type(enum drm_plane_type type)
2979 {
2980         switch (type) {
2981         case DRM_PLANE_TYPE_OVERLAY:
2982                 return "OVL";
2983         case DRM_PLANE_TYPE_PRIMARY:
2984                 return "PRI";
2985         case DRM_PLANE_TYPE_CURSOR:
2986                 return "CUR";
2987         /*
2988          * Deliberately omitting default: to generate compiler warnings
2989          * when a new drm_plane_type gets added.
2990          */
2991         }
2992
2993         return "unknown";
2994 }
2995
2996 static const char *plane_rotation(unsigned int rotation)
2997 {
2998         static char buf[48];
2999         /*
3000          * According to doc only one DRM_ROTATE_ is allowed but this
3001          * will print them all to visualize if the values are misused
3002          */
3003         snprintf(buf, sizeof(buf),
3004                  "%s%s%s%s%s%s(0x%08x)",
3005                  (rotation & BIT(DRM_ROTATE_0)) ? "0 " : "",
3006                  (rotation & BIT(DRM_ROTATE_90)) ? "90 " : "",
3007                  (rotation & BIT(DRM_ROTATE_180)) ? "180 " : "",
3008                  (rotation & BIT(DRM_ROTATE_270)) ? "270 " : "",
3009                  (rotation & BIT(DRM_REFLECT_X)) ? "FLIPX " : "",
3010                  (rotation & BIT(DRM_REFLECT_Y)) ? "FLIPY " : "",
3011                  rotation);
3012
3013         return buf;
3014 }
3015
3016 static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3017 {
3018         struct drm_info_node *node = m->private;
3019         struct drm_device *dev = node->minor->dev;
3020         struct intel_plane *intel_plane;
3021
3022         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3023                 struct drm_plane_state *state;
3024                 struct drm_plane *plane = &intel_plane->base;
3025
3026                 if (!plane->state) {
3027                         seq_puts(m, "plane->state is NULL!\n");
3028                         continue;
3029                 }
3030
3031                 state = plane->state;
3032
3033                 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3034                            plane->base.id,
3035                            plane_type(intel_plane->base.type),
3036                            state->crtc_x, state->crtc_y,
3037                            state->crtc_w, state->crtc_h,
3038                            (state->src_x >> 16),
3039                            ((state->src_x & 0xffff) * 15625) >> 10,
3040                            (state->src_y >> 16),
3041                            ((state->src_y & 0xffff) * 15625) >> 10,
3042                            (state->src_w >> 16),
3043                            ((state->src_w & 0xffff) * 15625) >> 10,
3044                            (state->src_h >> 16),
3045                            ((state->src_h & 0xffff) * 15625) >> 10,
3046                            state->fb ? drm_get_format_name(state->fb->pixel_format) : "N/A",
3047                            plane_rotation(state->rotation));
3048         }
3049 }
3050
3051 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3052 {
3053         struct intel_crtc_state *pipe_config;
3054         int num_scalers = intel_crtc->num_scalers;
3055         int i;
3056
3057         pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3058
3059         /* Not all platformas have a scaler */
3060         if (num_scalers) {
3061                 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3062                            num_scalers,
3063                            pipe_config->scaler_state.scaler_users,
3064                            pipe_config->scaler_state.scaler_id);
3065
3066                 for (i = 0; i < SKL_NUM_SCALERS; i++) {
3067                         struct intel_scaler *sc =
3068                                         &pipe_config->scaler_state.scalers[i];
3069
3070                         seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3071                                    i, yesno(sc->in_use), sc->mode);
3072                 }
3073                 seq_puts(m, "\n");
3074         } else {
3075                 seq_puts(m, "\tNo scalers available on this platform\n");
3076         }
3077 }
3078
3079 static int i915_display_info(struct seq_file *m, void *unused)
3080 {
3081         struct drm_info_node *node = m->private;
3082         struct drm_device *dev = node->minor->dev;
3083         struct drm_i915_private *dev_priv = dev->dev_private;
3084         struct intel_crtc *crtc;
3085         struct drm_connector *connector;
3086
3087         intel_runtime_pm_get(dev_priv);
3088         drm_modeset_lock_all(dev);
3089         seq_printf(m, "CRTC info\n");
3090         seq_printf(m, "---------\n");
3091         for_each_intel_crtc(dev, crtc) {
3092                 bool active;
3093                 struct intel_crtc_state *pipe_config;
3094                 int x, y;
3095
3096                 pipe_config = to_intel_crtc_state(crtc->base.state);
3097
3098                 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3099                            crtc->base.base.id, pipe_name(crtc->pipe),
3100                            yesno(pipe_config->base.active),
3101                            pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3102                            yesno(pipe_config->dither), pipe_config->pipe_bpp);
3103
3104                 if (pipe_config->base.active) {
3105                         intel_crtc_info(m, crtc);
3106
3107                         active = cursor_position(dev, crtc->pipe, &x, &y);
3108                         seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
3109                                    yesno(crtc->cursor_base),
3110                                    x, y, crtc->base.cursor->state->crtc_w,
3111                                    crtc->base.cursor->state->crtc_h,
3112                                    crtc->cursor_addr, yesno(active));
3113                         intel_scaler_info(m, crtc);
3114                         intel_plane_info(m, crtc);
3115                 }
3116
3117                 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3118                            yesno(!crtc->cpu_fifo_underrun_disabled),
3119                            yesno(!crtc->pch_fifo_underrun_disabled));
3120         }
3121
3122         seq_printf(m, "\n");
3123         seq_printf(m, "Connector info\n");
3124         seq_printf(m, "--------------\n");
3125         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3126                 intel_connector_info(m, connector);
3127         }
3128         drm_modeset_unlock_all(dev);
3129         intel_runtime_pm_put(dev_priv);
3130
3131         return 0;
3132 }
3133
3134 static int i915_semaphore_status(struct seq_file *m, void *unused)
3135 {
3136         struct drm_info_node *node = (struct drm_info_node *) m->private;
3137         struct drm_device *dev = node->minor->dev;
3138         struct drm_i915_private *dev_priv = dev->dev_private;
3139         struct intel_engine_cs *engine;
3140         int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
3141         enum intel_engine_id id;
3142         int j, ret;
3143
3144         if (!i915_semaphore_is_enabled(dev)) {
3145                 seq_puts(m, "Semaphores are disabled\n");
3146                 return 0;
3147         }
3148
3149         ret = mutex_lock_interruptible(&dev->struct_mutex);
3150         if (ret)
3151                 return ret;
3152         intel_runtime_pm_get(dev_priv);
3153
3154         if (IS_BROADWELL(dev)) {
3155                 struct page *page;
3156                 uint64_t *seqno;
3157
3158                 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
3159
3160                 seqno = (uint64_t *)kmap_atomic(page);
3161                 for_each_engine_id(engine, dev_priv, id) {
3162                         uint64_t offset;
3163
3164                         seq_printf(m, "%s\n", engine->name);
3165
3166                         seq_puts(m, "  Last signal:");
3167                         for (j = 0; j < num_rings; j++) {
3168                                 offset = id * I915_NUM_ENGINES + j;
3169                                 seq_printf(m, "0x%08llx (0x%02llx) ",
3170                                            seqno[offset], offset * 8);
3171                         }
3172                         seq_putc(m, '\n');
3173
3174                         seq_puts(m, "  Last wait:  ");
3175                         for (j = 0; j < num_rings; j++) {
3176                                 offset = id + (j * I915_NUM_ENGINES);
3177                                 seq_printf(m, "0x%08llx (0x%02llx) ",
3178                                            seqno[offset], offset * 8);
3179                         }
3180                         seq_putc(m, '\n');
3181
3182                 }
3183                 kunmap_atomic(seqno);
3184         } else {
3185                 seq_puts(m, "  Last signal:");
3186                 for_each_engine(engine, dev_priv)
3187                         for (j = 0; j < num_rings; j++)
3188                                 seq_printf(m, "0x%08x\n",
3189                                            I915_READ(engine->semaphore.mbox.signal[j]));
3190                 seq_putc(m, '\n');
3191         }
3192
3193         seq_puts(m, "\nSync seqno:\n");
3194         for_each_engine(engine, dev_priv) {
3195                 for (j = 0; j < num_rings; j++)
3196                         seq_printf(m, "  0x%08x ",
3197                                    engine->semaphore.sync_seqno[j]);
3198                 seq_putc(m, '\n');
3199         }
3200         seq_putc(m, '\n');
3201
3202         intel_runtime_pm_put(dev_priv);
3203         mutex_unlock(&dev->struct_mutex);
3204         return 0;
3205 }
3206
3207 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3208 {
3209         struct drm_info_node *node = (struct drm_info_node *) m->private;
3210         struct drm_device *dev = node->minor->dev;
3211         struct drm_i915_private *dev_priv = dev->dev_private;
3212         int i;
3213
3214         drm_modeset_lock_all(dev);
3215         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3216                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3217
3218                 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3219                 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3220                            pll->config.crtc_mask, pll->active_mask, yesno(pll->on));
3221                 seq_printf(m, " tracked hardware state:\n");
3222                 seq_printf(m, " dpll:    0x%08x\n", pll->config.hw_state.dpll);
3223                 seq_printf(m, " dpll_md: 0x%08x\n",
3224                            pll->config.hw_state.dpll_md);
3225                 seq_printf(m, " fp0:     0x%08x\n", pll->config.hw_state.fp0);
3226                 seq_printf(m, " fp1:     0x%08x\n", pll->config.hw_state.fp1);
3227                 seq_printf(m, " wrpll:   0x%08x\n", pll->config.hw_state.wrpll);
3228         }
3229         drm_modeset_unlock_all(dev);
3230
3231         return 0;
3232 }
3233
3234 static int i915_wa_registers(struct seq_file *m, void *unused)
3235 {
3236         int i;
3237         int ret;
3238         struct intel_engine_cs *engine;
3239         struct drm_info_node *node = (struct drm_info_node *) m->private;
3240         struct drm_device *dev = node->minor->dev;
3241         struct drm_i915_private *dev_priv = dev->dev_private;
3242         struct i915_workarounds *workarounds = &dev_priv->workarounds;
3243         enum intel_engine_id id;
3244
3245         ret = mutex_lock_interruptible(&dev->struct_mutex);
3246         if (ret)
3247                 return ret;
3248
3249         intel_runtime_pm_get(dev_priv);
3250
3251         seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
3252         for_each_engine_id(engine, dev_priv, id)
3253                 seq_printf(m, "HW whitelist count for %s: %d\n",
3254                            engine->name, workarounds->hw_whitelist_count[id]);
3255         for (i = 0; i < workarounds->count; ++i) {
3256                 i915_reg_t addr;
3257                 u32 mask, value, read;
3258                 bool ok;
3259
3260                 addr = workarounds->reg[i].addr;
3261                 mask = workarounds->reg[i].mask;
3262                 value = workarounds->reg[i].value;
3263                 read = I915_READ(addr);
3264                 ok = (value & mask) == (read & mask);
3265                 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3266                            i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
3267         }
3268
3269         intel_runtime_pm_put(dev_priv);
3270         mutex_unlock(&dev->struct_mutex);
3271
3272         return 0;
3273 }
3274
3275 static int i915_ddb_info(struct seq_file *m, void *unused)
3276 {
3277         struct drm_info_node *node = m->private;
3278         struct drm_device *dev = node->minor->dev;
3279         struct drm_i915_private *dev_priv = dev->dev_private;
3280         struct skl_ddb_allocation *ddb;
3281         struct skl_ddb_entry *entry;
3282         enum pipe pipe;
3283         int plane;
3284
3285         if (INTEL_INFO(dev)->gen < 9)
3286                 return 0;
3287
3288         drm_modeset_lock_all(dev);
3289
3290         ddb = &dev_priv->wm.skl_hw.ddb;
3291
3292         seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3293
3294         for_each_pipe(dev_priv, pipe) {
3295                 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3296
3297                 for_each_plane(dev_priv, pipe, plane) {
3298                         entry = &ddb->plane[pipe][plane];
3299                         seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane + 1,
3300                                    entry->start, entry->end,
3301                                    skl_ddb_entry_size(entry));
3302                 }
3303
3304                 entry = &ddb->plane[pipe][PLANE_CURSOR];
3305                 seq_printf(m, "  %-13s%8u%8u%8u\n", "Cursor", entry->start,
3306                            entry->end, skl_ddb_entry_size(entry));
3307         }
3308
3309         drm_modeset_unlock_all(dev);
3310
3311         return 0;
3312 }
3313
3314 static void drrs_status_per_crtc(struct seq_file *m,
3315                 struct drm_device *dev, struct intel_crtc *intel_crtc)
3316 {
3317         struct intel_encoder *intel_encoder;
3318         struct drm_i915_private *dev_priv = dev->dev_private;
3319         struct i915_drrs *drrs = &dev_priv->drrs;
3320         int vrefresh = 0;
3321
3322         for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) {
3323                 /* Encoder connected on this CRTC */
3324                 switch (intel_encoder->type) {
3325                 case INTEL_OUTPUT_EDP:
3326                         seq_puts(m, "eDP:\n");
3327                         break;
3328                 case INTEL_OUTPUT_DSI:
3329                         seq_puts(m, "DSI:\n");
3330                         break;
3331                 case INTEL_OUTPUT_HDMI:
3332                         seq_puts(m, "HDMI:\n");
3333                         break;
3334                 case INTEL_OUTPUT_DISPLAYPORT:
3335                         seq_puts(m, "DP:\n");
3336                         break;
3337                 default:
3338                         seq_printf(m, "Other encoder (id=%d).\n",
3339                                                 intel_encoder->type);
3340                         return;
3341                 }
3342         }
3343
3344         if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3345                 seq_puts(m, "\tVBT: DRRS_type: Static");
3346         else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3347                 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3348         else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3349                 seq_puts(m, "\tVBT: DRRS_type: None");
3350         else
3351                 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3352
3353         seq_puts(m, "\n\n");
3354
3355         if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3356                 struct intel_panel *panel;
3357
3358                 mutex_lock(&drrs->mutex);
3359                 /* DRRS Supported */
3360                 seq_puts(m, "\tDRRS Supported: Yes\n");
3361
3362                 /* disable_drrs() will make drrs->dp NULL */
3363                 if (!drrs->dp) {
3364                         seq_puts(m, "Idleness DRRS: Disabled");
3365                         mutex_unlock(&drrs->mutex);
3366                         return;
3367                 }
3368
3369                 panel = &drrs->dp->attached_connector->panel;
3370                 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3371                                         drrs->busy_frontbuffer_bits);
3372
3373                 seq_puts(m, "\n\t\t");
3374                 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3375                         seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3376                         vrefresh = panel->fixed_mode->vrefresh;
3377                 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3378                         seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3379                         vrefresh = panel->downclock_mode->vrefresh;
3380                 } else {
3381                         seq_printf(m, "DRRS_State: Unknown(%d)\n",
3382                                                 drrs->refresh_rate_type);
3383                         mutex_unlock(&drrs->mutex);
3384                         return;
3385                 }
3386                 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3387
3388                 seq_puts(m, "\n\t\t");
3389                 mutex_unlock(&drrs->mutex);
3390         } else {
3391                 /* DRRS not supported. Print the VBT parameter*/
3392                 seq_puts(m, "\tDRRS Supported : No");
3393         }
3394         seq_puts(m, "\n");
3395 }
3396
3397 static int i915_drrs_status(struct seq_file *m, void *unused)
3398 {
3399         struct drm_info_node *node = m->private;
3400         struct drm_device *dev = node->minor->dev;
3401         struct intel_crtc *intel_crtc;
3402         int active_crtc_cnt = 0;
3403
3404         for_each_intel_crtc(dev, intel_crtc) {
3405                 drm_modeset_lock(&intel_crtc->base.mutex, NULL);
3406
3407                 if (intel_crtc->base.state->active) {
3408                         active_crtc_cnt++;
3409                         seq_printf(m, "\nCRTC %d:  ", active_crtc_cnt);
3410
3411                         drrs_status_per_crtc(m, dev, intel_crtc);
3412                 }
3413
3414                 drm_modeset_unlock(&intel_crtc->base.mutex);
3415         }
3416
3417         if (!active_crtc_cnt)
3418                 seq_puts(m, "No active crtc found\n");
3419
3420         return 0;
3421 }
3422
3423 struct pipe_crc_info {
3424         const char *name;
3425         struct drm_device *dev;
3426         enum pipe pipe;
3427 };
3428
3429 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3430 {
3431         struct drm_info_node *node = (struct drm_info_node *) m->private;
3432         struct drm_device *dev = node->minor->dev;
3433         struct drm_encoder *encoder;
3434         struct intel_encoder *intel_encoder;
3435         struct intel_digital_port *intel_dig_port;
3436         drm_modeset_lock_all(dev);
3437         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3438                 intel_encoder = to_intel_encoder(encoder);
3439                 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
3440                         continue;
3441                 intel_dig_port = enc_to_dig_port(encoder);
3442                 if (!intel_dig_port->dp.can_mst)
3443                         continue;
3444
3445                 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3446         }
3447         drm_modeset_unlock_all(dev);
3448         return 0;
3449 }
3450
3451 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3452 {
3453         struct pipe_crc_info *info = inode->i_private;
3454         struct drm_i915_private *dev_priv = info->dev->dev_private;
3455         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3456
3457         if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3458                 return -ENODEV;
3459
3460         spin_lock_irq(&pipe_crc->lock);
3461
3462         if (pipe_crc->opened) {
3463                 spin_unlock_irq(&pipe_crc->lock);
3464                 return -EBUSY; /* already open */
3465         }
3466
3467         pipe_crc->opened = true;
3468         filep->private_data = inode->i_private;
3469
3470         spin_unlock_irq(&pipe_crc->lock);
3471
3472         return 0;
3473 }
3474
3475 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3476 {
3477         struct pipe_crc_info *info = inode->i_private;
3478         struct drm_i915_private *dev_priv = info->dev->dev_private;
3479         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3480
3481         spin_lock_irq(&pipe_crc->lock);
3482         pipe_crc->opened = false;
3483         spin_unlock_irq(&pipe_crc->lock);
3484
3485         return 0;
3486 }
3487
3488 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3489 #define PIPE_CRC_LINE_LEN       (6 * 8 + 5 + 1)
3490 /* account for \'0' */
3491 #define PIPE_CRC_BUFFER_LEN     (PIPE_CRC_LINE_LEN + 1)
3492
3493 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
3494 {
3495         assert_spin_locked(&pipe_crc->lock);
3496         return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3497                         INTEL_PIPE_CRC_ENTRIES_NR);
3498 }
3499
3500 static ssize_t
3501 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3502                    loff_t *pos)
3503 {
3504         struct pipe_crc_info *info = filep->private_data;
3505         struct drm_device *dev = info->dev;
3506         struct drm_i915_private *dev_priv = dev->dev_private;
3507         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3508         char buf[PIPE_CRC_BUFFER_LEN];
3509         int n_entries;
3510         ssize_t bytes_read;
3511
3512         /*
3513          * Don't allow user space to provide buffers not big enough to hold
3514          * a line of data.
3515          */
3516         if (count < PIPE_CRC_LINE_LEN)
3517                 return -EINVAL;
3518
3519         if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
3520                 return 0;
3521
3522         /* nothing to read */
3523         spin_lock_irq(&pipe_crc->lock);
3524         while (pipe_crc_data_count(pipe_crc) == 0) {
3525                 int ret;
3526
3527                 if (filep->f_flags & O_NONBLOCK) {
3528                         spin_unlock_irq(&pipe_crc->lock);
3529                         return -EAGAIN;
3530                 }
3531
3532                 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3533                                 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3534                 if (ret) {
3535                         spin_unlock_irq(&pipe_crc->lock);
3536                         return ret;
3537                 }
3538         }
3539
3540         /* We now have one or more entries to read */
3541         n_entries = count / PIPE_CRC_LINE_LEN;
3542
3543         bytes_read = 0;
3544         while (n_entries > 0) {
3545                 struct intel_pipe_crc_entry *entry =
3546                         &pipe_crc->entries[pipe_crc->tail];
3547                 int ret;
3548
3549                 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3550                              INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3551                         break;
3552
3553                 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3554                 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3555
3556                 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3557                                        "%8u %8x %8x %8x %8x %8x\n",
3558                                        entry->frame, entry->crc[0],
3559                                        entry->crc[1], entry->crc[2],
3560                                        entry->crc[3], entry->crc[4]);
3561
3562                 spin_unlock_irq(&pipe_crc->lock);
3563
3564                 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
3565                 if (ret == PIPE_CRC_LINE_LEN)
3566                         return -EFAULT;
3567
3568                 user_buf += PIPE_CRC_LINE_LEN;
3569                 n_entries--;
3570
3571                 spin_lock_irq(&pipe_crc->lock);
3572         }
3573
3574         spin_unlock_irq(&pipe_crc->lock);
3575
3576         return bytes_read;
3577 }
3578
3579 static const struct file_operations i915_pipe_crc_fops = {
3580         .owner = THIS_MODULE,
3581         .open = i915_pipe_crc_open,
3582         .read = i915_pipe_crc_read,
3583         .release = i915_pipe_crc_release,
3584 };
3585
3586 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3587         {
3588                 .name = "i915_pipe_A_crc",
3589                 .pipe = PIPE_A,
3590         },
3591         {
3592                 .name = "i915_pipe_B_crc",
3593                 .pipe = PIPE_B,
3594         },
3595         {
3596                 .name = "i915_pipe_C_crc",
3597                 .pipe = PIPE_C,
3598         },
3599 };
3600
3601 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3602                                 enum pipe pipe)
3603 {
3604         struct drm_device *dev = minor->dev;
3605         struct dentry *ent;
3606         struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3607
3608         info->dev = dev;
3609         ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3610                                   &i915_pipe_crc_fops);
3611         if (!ent)
3612                 return -ENOMEM;
3613
3614         return drm_add_fake_info_node(minor, ent, info);
3615 }
3616
3617 static const char * const pipe_crc_sources[] = {
3618         "none",
3619         "plane1",
3620         "plane2",
3621         "pf",
3622         "pipe",
3623         "TV",
3624         "DP-B",
3625         "DP-C",
3626         "DP-D",
3627         "auto",
3628 };
3629
3630 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3631 {
3632         BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3633         return pipe_crc_sources[source];
3634 }
3635
3636 static int display_crc_ctl_show(struct seq_file *m, void *data)
3637 {
3638         struct drm_device *dev = m->private;
3639         struct drm_i915_private *dev_priv = dev->dev_private;
3640         int i;
3641
3642         for (i = 0; i < I915_MAX_PIPES; i++)
3643                 seq_printf(m, "%c %s\n", pipe_name(i),
3644                            pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3645
3646         return 0;
3647 }
3648
3649 static int display_crc_ctl_open(struct inode *inode, struct file *file)
3650 {
3651         struct drm_device *dev = inode->i_private;
3652
3653         return single_open(file, display_crc_ctl_show, dev);
3654 }
3655
3656 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3657                                  uint32_t *val)
3658 {
3659         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3660                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3661
3662         switch (*source) {
3663         case INTEL_PIPE_CRC_SOURCE_PIPE:
3664                 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3665                 break;
3666         case INTEL_PIPE_CRC_SOURCE_NONE:
3667                 *val = 0;
3668                 break;
3669         default:
3670                 return -EINVAL;
3671         }
3672
3673         return 0;
3674 }
3675
3676 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3677                                      enum intel_pipe_crc_source *source)
3678 {
3679         struct intel_encoder *encoder;
3680         struct intel_crtc *crtc;
3681         struct intel_digital_port *dig_port;
3682         int ret = 0;
3683
3684         *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3685
3686         drm_modeset_lock_all(dev);
3687         for_each_intel_encoder(dev, encoder) {
3688                 if (!encoder->base.crtc)
3689                         continue;
3690
3691                 crtc = to_intel_crtc(encoder->base.crtc);
3692
3693                 if (crtc->pipe != pipe)
3694                         continue;
3695
3696                 switch (encoder->type) {
3697                 case INTEL_OUTPUT_TVOUT:
3698                         *source = INTEL_PIPE_CRC_SOURCE_TV;
3699                         break;
3700                 case INTEL_OUTPUT_DISPLAYPORT:
3701                 case INTEL_OUTPUT_EDP:
3702                         dig_port = enc_to_dig_port(&encoder->base);
3703                         switch (dig_port->port) {
3704                         case PORT_B:
3705                                 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3706                                 break;
3707                         case PORT_C:
3708                                 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3709                                 break;
3710                         case PORT_D:
3711                                 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3712                                 break;
3713                         default:
3714                                 WARN(1, "nonexisting DP port %c\n",
3715                                      port_name(dig_port->port));
3716                                 break;
3717                         }
3718                         break;
3719                 default:
3720                         break;
3721                 }
3722         }
3723         drm_modeset_unlock_all(dev);
3724
3725         return ret;
3726 }
3727
3728 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3729                                 enum pipe pipe,
3730                                 enum intel_pipe_crc_source *source,
3731                                 uint32_t *val)
3732 {
3733         struct drm_i915_private *dev_priv = dev->dev_private;
3734         bool need_stable_symbols = false;
3735
3736         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3737                 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3738                 if (ret)
3739                         return ret;
3740         }
3741
3742         switch (*source) {
3743         case INTEL_PIPE_CRC_SOURCE_PIPE:
3744                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3745                 break;
3746         case INTEL_PIPE_CRC_SOURCE_DP_B:
3747                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3748                 need_stable_symbols = true;
3749                 break;
3750         case INTEL_PIPE_CRC_SOURCE_DP_C:
3751                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3752                 need_stable_symbols = true;
3753                 break;
3754         case INTEL_PIPE_CRC_SOURCE_DP_D:
3755                 if (!IS_CHERRYVIEW(dev))
3756                         return -EINVAL;
3757                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3758                 need_stable_symbols = true;
3759                 break;
3760         case INTEL_PIPE_CRC_SOURCE_NONE:
3761                 *val = 0;
3762                 break;
3763         default:
3764                 return -EINVAL;
3765         }
3766
3767         /*
3768          * When the pipe CRC tap point is after the transcoders we need
3769          * to tweak symbol-level features to produce a deterministic series of
3770          * symbols for a given frame. We need to reset those features only once
3771          * a frame (instead of every nth symbol):
3772          *   - DC-balance: used to ensure a better clock recovery from the data
3773          *     link (SDVO)
3774          *   - DisplayPort scrambling: used for EMI reduction
3775          */
3776         if (need_stable_symbols) {
3777                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3778
3779                 tmp |= DC_BALANCE_RESET_VLV;
3780                 switch (pipe) {
3781                 case PIPE_A:
3782                         tmp |= PIPE_A_SCRAMBLE_RESET;
3783                         break;
3784                 case PIPE_B:
3785                         tmp |= PIPE_B_SCRAMBLE_RESET;
3786                         break;
3787                 case PIPE_C:
3788                         tmp |= PIPE_C_SCRAMBLE_RESET;
3789                         break;
3790                 default:
3791                         return -EINVAL;
3792                 }
3793                 I915_WRITE(PORT_DFT2_G4X, tmp);
3794         }
3795
3796         return 0;
3797 }
3798
3799 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
3800                                  enum pipe pipe,
3801                                  enum intel_pipe_crc_source *source,
3802                                  uint32_t *val)
3803 {
3804         struct drm_i915_private *dev_priv = dev->dev_private;
3805         bool need_stable_symbols = false;
3806
3807         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3808                 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3809                 if (ret)
3810                         return ret;
3811         }
3812
3813         switch (*source) {
3814         case INTEL_PIPE_CRC_SOURCE_PIPE:
3815                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3816                 break;
3817         case INTEL_PIPE_CRC_SOURCE_TV:
3818                 if (!SUPPORTS_TV(dev))
3819                         return -EINVAL;
3820                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3821                 break;
3822         case INTEL_PIPE_CRC_SOURCE_DP_B:
3823                 if (!IS_G4X(dev))
3824                         return -EINVAL;
3825                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3826                 need_stable_symbols = true;
3827                 break;
3828         case INTEL_PIPE_CRC_SOURCE_DP_C:
3829                 if (!IS_G4X(dev))
3830                         return -EINVAL;
3831                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3832                 need_stable_symbols = true;
3833                 break;
3834         case INTEL_PIPE_CRC_SOURCE_DP_D:
3835                 if (!IS_G4X(dev))
3836                         return -EINVAL;
3837                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3838                 need_stable_symbols = true;
3839                 break;
3840         case INTEL_PIPE_CRC_SOURCE_NONE:
3841                 *val = 0;
3842                 break;
3843         default:
3844                 return -EINVAL;
3845         }
3846
3847         /*
3848          * When the pipe CRC tap point is after the transcoders we need
3849          * to tweak symbol-level features to produce a deterministic series of
3850          * symbols for a given frame. We need to reset those features only once
3851          * a frame (instead of every nth symbol):
3852          *   - DC-balance: used to ensure a better clock recovery from the data
3853          *     link (SDVO)
3854          *   - DisplayPort scrambling: used for EMI reduction
3855          */
3856         if (need_stable_symbols) {
3857                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3858
3859                 WARN_ON(!IS_G4X(dev));
3860
3861                 I915_WRITE(PORT_DFT_I9XX,
3862                            I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3863
3864                 if (pipe == PIPE_A)
3865                         tmp |= PIPE_A_SCRAMBLE_RESET;
3866                 else
3867                         tmp |= PIPE_B_SCRAMBLE_RESET;
3868
3869                 I915_WRITE(PORT_DFT2_G4X, tmp);
3870         }
3871
3872         return 0;
3873 }
3874
3875 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3876                                          enum pipe pipe)
3877 {
3878         struct drm_i915_private *dev_priv = dev->dev_private;
3879         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3880
3881         switch (pipe) {
3882         case PIPE_A:
3883                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3884                 break;
3885         case PIPE_B:
3886                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3887                 break;
3888         case PIPE_C:
3889                 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3890                 break;
3891         default:
3892                 return;
3893         }
3894         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3895                 tmp &= ~DC_BALANCE_RESET_VLV;
3896         I915_WRITE(PORT_DFT2_G4X, tmp);
3897
3898 }
3899
3900 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3901                                          enum pipe pipe)
3902 {
3903         struct drm_i915_private *dev_priv = dev->dev_private;
3904         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3905
3906         if (pipe == PIPE_A)
3907                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3908         else
3909                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3910         I915_WRITE(PORT_DFT2_G4X, tmp);
3911
3912         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3913                 I915_WRITE(PORT_DFT_I9XX,
3914                            I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3915         }
3916 }
3917
3918 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3919                                 uint32_t *val)
3920 {
3921         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3922                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3923
3924         switch (*source) {
3925         case INTEL_PIPE_CRC_SOURCE_PLANE1:
3926                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3927                 break;
3928         case INTEL_PIPE_CRC_SOURCE_PLANE2:
3929                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3930                 break;
3931         case INTEL_PIPE_CRC_SOURCE_PIPE:
3932                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3933                 break;
3934         case INTEL_PIPE_CRC_SOURCE_NONE:
3935                 *val = 0;
3936                 break;
3937         default:
3938                 return -EINVAL;
3939         }
3940
3941         return 0;
3942 }
3943
3944 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev, bool enable)
3945 {
3946         struct drm_i915_private *dev_priv = dev->dev_private;
3947         struct intel_crtc *crtc =
3948                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3949         struct intel_crtc_state *pipe_config;
3950         struct drm_atomic_state *state;
3951         int ret = 0;
3952
3953         drm_modeset_lock_all(dev);
3954         state = drm_atomic_state_alloc(dev);
3955         if (!state) {
3956                 ret = -ENOMEM;
3957                 goto out;
3958         }
3959
3960         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
3961         pipe_config = intel_atomic_get_crtc_state(state, crtc);
3962         if (IS_ERR(pipe_config)) {
3963                 ret = PTR_ERR(pipe_config);
3964                 goto out;
3965         }
3966
3967         pipe_config->pch_pfit.force_thru = enable;
3968         if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
3969             pipe_config->pch_pfit.enabled != enable)
3970                 pipe_config->base.connectors_changed = true;
3971
3972         ret = drm_atomic_commit(state);
3973 out:
3974         drm_modeset_unlock_all(dev);
3975         WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
3976         if (ret)
3977                 drm_atomic_state_free(state);
3978 }
3979
3980 static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3981                                 enum pipe pipe,
3982                                 enum intel_pipe_crc_source *source,
3983                                 uint32_t *val)
3984 {
3985         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3986                 *source = INTEL_PIPE_CRC_SOURCE_PF;
3987
3988         switch (*source) {
3989         case INTEL_PIPE_CRC_SOURCE_PLANE1:
3990                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3991                 break;
3992         case INTEL_PIPE_CRC_SOURCE_PLANE2:
3993                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3994                 break;
3995         case INTEL_PIPE_CRC_SOURCE_PF:
3996                 if (IS_HASWELL(dev) && pipe == PIPE_A)
3997                         hsw_trans_edp_pipe_A_crc_wa(dev, true);
3998
3999                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
4000                 break;
4001         case INTEL_PIPE_CRC_SOURCE_NONE:
4002                 *val = 0;
4003                 break;
4004         default:
4005                 return -EINVAL;
4006         }
4007
4008         return 0;
4009 }
4010
4011 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
4012                                enum intel_pipe_crc_source source)
4013 {
4014         struct drm_i915_private *dev_priv = dev->dev_private;
4015         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
4016         struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
4017                                                                         pipe));
4018         enum intel_display_power_domain power_domain;
4019         u32 val = 0; /* shut up gcc */
4020         int ret;
4021
4022         if (pipe_crc->source == source)
4023                 return 0;
4024
4025         /* forbid changing the source without going back to 'none' */
4026         if (pipe_crc->source && source)
4027                 return -EINVAL;
4028
4029         power_domain = POWER_DOMAIN_PIPE(pipe);
4030         if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
4031                 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
4032                 return -EIO;
4033         }
4034
4035         if (IS_GEN2(dev))
4036                 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
4037         else if (INTEL_INFO(dev)->gen < 5)
4038                 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4039         else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4040                 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4041         else if (IS_GEN5(dev) || IS_GEN6(dev))
4042                 ret = ilk_pipe_crc_ctl_reg(&source, &val);
4043         else
4044                 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4045
4046         if (ret != 0)
4047                 goto out;
4048
4049         /* none -> real source transition */
4050         if (source) {
4051                 struct intel_pipe_crc_entry *entries;
4052
4053                 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4054                                  pipe_name(pipe), pipe_crc_source_name(source));
4055
4056                 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
4057                                   sizeof(pipe_crc->entries[0]),
4058                                   GFP_KERNEL);
4059                 if (!entries) {
4060                         ret = -ENOMEM;
4061                         goto out;
4062                 }
4063
4064                 /*
4065                  * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4066                  * enabled and disabled dynamically based on package C states,
4067                  * user space can't make reliable use of the CRCs, so let's just
4068                  * completely disable it.
4069                  */
4070                 hsw_disable_ips(crtc);
4071
4072                 spin_lock_irq(&pipe_crc->lock);
4073                 kfree(pipe_crc->entries);
4074                 pipe_crc->entries = entries;
4075                 pipe_crc->head = 0;
4076                 pipe_crc->tail = 0;
4077                 spin_unlock_irq(&pipe_crc->lock);
4078         }
4079
4080         pipe_crc->source = source;
4081
4082         I915_WRITE(PIPE_CRC_CTL(pipe), val);
4083         POSTING_READ(PIPE_CRC_CTL(pipe));
4084
4085         /* real source -> none transition */
4086         if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
4087                 struct intel_pipe_crc_entry *entries;
4088                 struct intel_crtc *crtc =
4089                         to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
4090
4091                 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4092                                  pipe_name(pipe));
4093
4094                 drm_modeset_lock(&crtc->base.mutex, NULL);
4095                 if (crtc->base.state->active)
4096                         intel_wait_for_vblank(dev, pipe);
4097                 drm_modeset_unlock(&crtc->base.mutex);
4098
4099                 spin_lock_irq(&pipe_crc->lock);
4100                 entries = pipe_crc->entries;
4101                 pipe_crc->entries = NULL;
4102                 pipe_crc->head = 0;
4103                 pipe_crc->tail = 0;
4104                 spin_unlock_irq(&pipe_crc->lock);
4105
4106                 kfree(entries);
4107
4108                 if (IS_G4X(dev))
4109                         g4x_undo_pipe_scramble_reset(dev, pipe);
4110                 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4111                         vlv_undo_pipe_scramble_reset(dev, pipe);
4112                 else if (IS_HASWELL(dev) && pipe == PIPE_A)
4113                         hsw_trans_edp_pipe_A_crc_wa(dev, false);
4114
4115                 hsw_enable_ips(crtc);
4116         }
4117
4118         ret = 0;
4119
4120 out:
4121         intel_display_power_put(dev_priv, power_domain);
4122
4123         return ret;
4124 }
4125
4126 /*
4127  * Parse pipe CRC command strings:
4128  *   command: wsp* object wsp+ name wsp+ source wsp*
4129  *   object: 'pipe'
4130  *   name: (A | B | C)
4131  *   source: (none | plane1 | plane2 | pf)
4132  *   wsp: (#0x20 | #0x9 | #0xA)+
4133  *
4134  * eg.:
4135  *  "pipe A plane1"  ->  Start CRC computations on plane1 of pipe A
4136  *  "pipe A none"    ->  Stop CRC
4137  */
4138 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
4139 {
4140         int n_words = 0;
4141
4142         while (*buf) {
4143                 char *end;
4144
4145                 /* skip leading white space */
4146                 buf = skip_spaces(buf);
4147                 if (!*buf)
4148                         break;  /* end of buffer */
4149
4150                 /* find end of word */
4151                 for (end = buf; *end && !isspace(*end); end++)
4152                         ;
4153
4154                 if (n_words == max_words) {
4155                         DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4156                                          max_words);
4157                         return -EINVAL; /* ran out of words[] before bytes */
4158                 }
4159
4160                 if (*end)
4161                         *end++ = '\0';
4162                 words[n_words++] = buf;
4163                 buf = end;
4164         }
4165
4166         return n_words;
4167 }
4168
4169 enum intel_pipe_crc_object {
4170         PIPE_CRC_OBJECT_PIPE,
4171 };
4172
4173 static const char * const pipe_crc_objects[] = {
4174         "pipe",
4175 };
4176
4177 static int
4178 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
4179 {
4180         int i;
4181
4182         for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
4183                 if (!strcmp(buf, pipe_crc_objects[i])) {
4184                         *o = i;
4185                         return 0;
4186                     }
4187
4188         return -EINVAL;
4189 }
4190
4191 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
4192 {
4193         const char name = buf[0];
4194
4195         if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
4196                 return -EINVAL;
4197
4198         *pipe = name - 'A';
4199
4200         return 0;
4201 }
4202
4203 static int
4204 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
4205 {
4206         int i;
4207
4208         for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
4209                 if (!strcmp(buf, pipe_crc_sources[i])) {
4210                         *s = i;
4211                         return 0;
4212                     }
4213
4214         return -EINVAL;
4215 }
4216
4217 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
4218 {
4219 #define N_WORDS 3
4220         int n_words;
4221         char *words[N_WORDS];
4222         enum pipe pipe;
4223         enum intel_pipe_crc_object object;
4224         enum intel_pipe_crc_source source;
4225
4226         n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
4227         if (n_words != N_WORDS) {
4228                 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4229                                  N_WORDS);
4230                 return -EINVAL;
4231         }
4232
4233         if (display_crc_ctl_parse_object(words[0], &object) < 0) {
4234                 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
4235                 return -EINVAL;
4236         }
4237
4238         if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
4239                 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
4240                 return -EINVAL;
4241         }
4242
4243         if (display_crc_ctl_parse_source(words[2], &source) < 0) {
4244                 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
4245                 return -EINVAL;
4246         }
4247
4248         return pipe_crc_set_source(dev, pipe, source);
4249 }
4250
4251 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
4252                                      size_t len, loff_t *offp)
4253 {
4254         struct seq_file *m = file->private_data;
4255         struct drm_device *dev = m->private;
4256         char *tmpbuf;
4257         int ret;
4258
4259         if (len == 0)
4260                 return 0;
4261
4262         if (len > PAGE_SIZE - 1) {
4263                 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4264                                  PAGE_SIZE);
4265                 return -E2BIG;
4266         }
4267
4268         tmpbuf = kmalloc(len + 1, GFP_KERNEL);
4269         if (!tmpbuf)
4270                 return -ENOMEM;
4271
4272         if (copy_from_user(tmpbuf, ubuf, len)) {
4273                 ret = -EFAULT;
4274                 goto out;
4275         }
4276         tmpbuf[len] = '\0';
4277
4278         ret = display_crc_ctl_parse(dev, tmpbuf, len);
4279
4280 out:
4281         kfree(tmpbuf);
4282         if (ret < 0)
4283                 return ret;
4284
4285         *offp += len;
4286         return len;
4287 }
4288
4289 static const struct file_operations i915_display_crc_ctl_fops = {
4290         .owner = THIS_MODULE,
4291         .open = display_crc_ctl_open,
4292         .read = seq_read,
4293         .llseek = seq_lseek,
4294         .release = single_release,
4295         .write = display_crc_ctl_write
4296 };
4297
4298 static ssize_t i915_displayport_test_active_write(struct file *file,
4299                                             const char __user *ubuf,
4300                                             size_t len, loff_t *offp)
4301 {
4302         char *input_buffer;
4303         int status = 0;
4304         struct drm_device *dev;
4305         struct drm_connector *connector;
4306         struct list_head *connector_list;
4307         struct intel_dp *intel_dp;
4308         int val = 0;
4309
4310         dev = ((struct seq_file *)file->private_data)->private;
4311
4312         connector_list = &dev->mode_config.connector_list;
4313
4314         if (len == 0)
4315                 return 0;
4316
4317         input_buffer = kmalloc(len + 1, GFP_KERNEL);
4318         if (!input_buffer)
4319                 return -ENOMEM;
4320
4321         if (copy_from_user(input_buffer, ubuf, len)) {
4322                 status = -EFAULT;
4323                 goto out;
4324         }
4325
4326         input_buffer[len] = '\0';
4327         DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4328
4329         list_for_each_entry(connector, connector_list, head) {
4330
4331                 if (connector->connector_type !=
4332                     DRM_MODE_CONNECTOR_DisplayPort)
4333                         continue;
4334
4335                 if (connector->status == connector_status_connected &&
4336                     connector->encoder != NULL) {
4337                         intel_dp = enc_to_intel_dp(connector->encoder);
4338                         status = kstrtoint(input_buffer, 10, &val);
4339                         if (status < 0)
4340                                 goto out;
4341                         DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4342                         /* To prevent erroneous activation of the compliance
4343                          * testing code, only accept an actual value of 1 here
4344                          */
4345                         if (val == 1)
4346                                 intel_dp->compliance_test_active = 1;
4347                         else
4348                                 intel_dp->compliance_test_active = 0;
4349                 }
4350         }
4351 out:
4352         kfree(input_buffer);
4353         if (status < 0)
4354                 return status;
4355
4356         *offp += len;
4357         return len;
4358 }
4359
4360 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4361 {
4362         struct drm_device *dev = m->private;
4363         struct drm_connector *connector;
4364         struct list_head *connector_list = &dev->mode_config.connector_list;
4365         struct intel_dp *intel_dp;
4366
4367         list_for_each_entry(connector, connector_list, head) {
4368
4369                 if (connector->connector_type !=
4370                     DRM_MODE_CONNECTOR_DisplayPort)
4371                         continue;
4372
4373                 if (connector->status == connector_status_connected &&
4374                     connector->encoder != NULL) {
4375                         intel_dp = enc_to_intel_dp(connector->encoder);
4376                         if (intel_dp->compliance_test_active)
4377                                 seq_puts(m, "1");
4378                         else
4379                                 seq_puts(m, "0");
4380                 } else
4381                         seq_puts(m, "0");
4382         }
4383
4384         return 0;
4385 }
4386
4387 static int i915_displayport_test_active_open(struct inode *inode,
4388                                        struct file *file)
4389 {
4390         struct drm_device *dev = inode->i_private;
4391
4392         return single_open(file, i915_displayport_test_active_show, dev);
4393 }
4394
4395 static const struct file_operations i915_displayport_test_active_fops = {
4396         .owner = THIS_MODULE,
4397         .open = i915_displayport_test_active_open,
4398         .read = seq_read,
4399         .llseek = seq_lseek,
4400         .release = single_release,
4401         .write = i915_displayport_test_active_write
4402 };
4403
4404 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4405 {
4406         struct drm_device *dev = m->private;
4407         struct drm_connector *connector;
4408         struct list_head *connector_list = &dev->mode_config.connector_list;
4409         struct intel_dp *intel_dp;
4410
4411         list_for_each_entry(connector, connector_list, head) {
4412
4413                 if (connector->connector_type !=
4414                     DRM_MODE_CONNECTOR_DisplayPort)
4415                         continue;
4416
4417                 if (connector->status == connector_status_connected &&
4418                     connector->encoder != NULL) {
4419                         intel_dp = enc_to_intel_dp(connector->encoder);
4420                         seq_printf(m, "%lx", intel_dp->compliance_test_data);
4421                 } else
4422                         seq_puts(m, "0");
4423         }
4424
4425         return 0;
4426 }
4427 static int i915_displayport_test_data_open(struct inode *inode,
4428                                        struct file *file)
4429 {
4430         struct drm_device *dev = inode->i_private;
4431
4432         return single_open(file, i915_displayport_test_data_show, dev);
4433 }
4434
4435 static const struct file_operations i915_displayport_test_data_fops = {
4436         .owner = THIS_MODULE,
4437         .open = i915_displayport_test_data_open,
4438         .read = seq_read,
4439         .llseek = seq_lseek,
4440         .release = single_release
4441 };
4442
4443 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4444 {
4445         struct drm_device *dev = m->private;
4446         struct drm_connector *connector;
4447         struct list_head *connector_list = &dev->mode_config.connector_list;
4448         struct intel_dp *intel_dp;
4449
4450         list_for_each_entry(connector, connector_list, head) {
4451
4452                 if (connector->connector_type !=
4453                     DRM_MODE_CONNECTOR_DisplayPort)
4454                         continue;
4455
4456                 if (connector->status == connector_status_connected &&
4457                     connector->encoder != NULL) {
4458                         intel_dp = enc_to_intel_dp(connector->encoder);
4459                         seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4460                 } else
4461                         seq_puts(m, "0");
4462         }
4463
4464         return 0;
4465 }
4466
4467 static int i915_displayport_test_type_open(struct inode *inode,
4468                                        struct file *file)
4469 {
4470         struct drm_device *dev = inode->i_private;
4471
4472         return single_open(file, i915_displayport_test_type_show, dev);
4473 }
4474
4475 static const struct file_operations i915_displayport_test_type_fops = {
4476         .owner = THIS_MODULE,
4477         .open = i915_displayport_test_type_open,
4478         .read = seq_read,
4479         .llseek = seq_lseek,
4480         .release = single_release
4481 };
4482
4483 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
4484 {
4485         struct drm_device *dev = m->private;
4486         int level;
4487         int num_levels;
4488
4489         if (IS_CHERRYVIEW(dev))
4490                 num_levels = 3;
4491         else if (IS_VALLEYVIEW(dev))
4492                 num_levels = 1;
4493         else
4494                 num_levels = ilk_wm_max_level(dev) + 1;
4495
4496         drm_modeset_lock_all(dev);
4497
4498         for (level = 0; level < num_levels; level++) {
4499                 unsigned int latency = wm[level];
4500
4501                 /*
4502                  * - WM1+ latency values in 0.5us units
4503                  * - latencies are in us on gen9/vlv/chv
4504                  */
4505                 if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev) ||
4506                     IS_CHERRYVIEW(dev))
4507                         latency *= 10;
4508                 else if (level > 0)
4509                         latency *= 5;
4510
4511                 seq_printf(m, "WM%d %u (%u.%u usec)\n",
4512                            level, wm[level], latency / 10, latency % 10);
4513         }
4514
4515         drm_modeset_unlock_all(dev);
4516 }
4517
4518 static int pri_wm_latency_show(struct seq_file *m, void *data)
4519 {
4520         struct drm_device *dev = m->private;
4521         struct drm_i915_private *dev_priv = dev->dev_private;
4522         const uint16_t *latencies;
4523
4524         if (INTEL_INFO(dev)->gen >= 9)
4525                 latencies = dev_priv->wm.skl_latency;
4526         else
4527                 latencies = to_i915(dev)->wm.pri_latency;
4528
4529         wm_latency_show(m, latencies);
4530
4531         return 0;
4532 }
4533
4534 static int spr_wm_latency_show(struct seq_file *m, void *data)
4535 {
4536         struct drm_device *dev = m->private;
4537         struct drm_i915_private *dev_priv = dev->dev_private;
4538         const uint16_t *latencies;
4539
4540         if (INTEL_INFO(dev)->gen >= 9)
4541                 latencies = dev_priv->wm.skl_latency;
4542         else
4543                 latencies = to_i915(dev)->wm.spr_latency;
4544
4545         wm_latency_show(m, latencies);
4546
4547         return 0;
4548 }
4549
4550 static int cur_wm_latency_show(struct seq_file *m, void *data)
4551 {
4552         struct drm_device *dev = m->private;
4553         struct drm_i915_private *dev_priv = dev->dev_private;
4554         const uint16_t *latencies;
4555
4556         if (INTEL_INFO(dev)->gen >= 9)
4557                 latencies = dev_priv->wm.skl_latency;
4558         else
4559                 latencies = to_i915(dev)->wm.cur_latency;
4560
4561         wm_latency_show(m, latencies);
4562
4563         return 0;
4564 }
4565
4566 static int pri_wm_latency_open(struct inode *inode, struct file *file)
4567 {
4568         struct drm_device *dev = inode->i_private;
4569
4570         if (INTEL_INFO(dev)->gen < 5)
4571                 return -ENODEV;
4572
4573         return single_open(file, pri_wm_latency_show, dev);
4574 }
4575
4576 static int spr_wm_latency_open(struct inode *inode, struct file *file)
4577 {
4578         struct drm_device *dev = inode->i_private;
4579
4580         if (HAS_GMCH_DISPLAY(dev))
4581                 return -ENODEV;
4582
4583         return single_open(file, spr_wm_latency_show, dev);
4584 }
4585
4586 static int cur_wm_latency_open(struct inode *inode, struct file *file)
4587 {
4588         struct drm_device *dev = inode->i_private;
4589
4590         if (HAS_GMCH_DISPLAY(dev))
4591                 return -ENODEV;
4592
4593         return single_open(file, cur_wm_latency_show, dev);
4594 }
4595
4596 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
4597                                 size_t len, loff_t *offp, uint16_t wm[8])
4598 {
4599         struct seq_file *m = file->private_data;
4600         struct drm_device *dev = m->private;
4601         uint16_t new[8] = { 0 };
4602         int num_levels;
4603         int level;
4604         int ret;
4605         char tmp[32];
4606
4607         if (IS_CHERRYVIEW(dev))
4608                 num_levels = 3;
4609         else if (IS_VALLEYVIEW(dev))
4610                 num_levels = 1;
4611         else
4612                 num_levels = ilk_wm_max_level(dev) + 1;
4613
4614         if (len >= sizeof(tmp))
4615                 return -EINVAL;
4616
4617         if (copy_from_user(tmp, ubuf, len))
4618                 return -EFAULT;
4619
4620         tmp[len] = '\0';
4621
4622         ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4623                      &new[0], &new[1], &new[2], &new[3],
4624                      &new[4], &new[5], &new[6], &new[7]);
4625         if (ret != num_levels)
4626                 return -EINVAL;
4627
4628         drm_modeset_lock_all(dev);
4629
4630         for (level = 0; level < num_levels; level++)
4631                 wm[level] = new[level];
4632
4633         drm_modeset_unlock_all(dev);
4634
4635         return len;
4636 }
4637
4638
4639 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4640                                     size_t len, loff_t *offp)
4641 {
4642         struct seq_file *m = file->private_data;
4643         struct drm_device *dev = m->private;
4644         struct drm_i915_private *dev_priv = dev->dev_private;
4645         uint16_t *latencies;
4646
4647         if (INTEL_INFO(dev)->gen >= 9)
4648                 latencies = dev_priv->wm.skl_latency;
4649         else
4650                 latencies = to_i915(dev)->wm.pri_latency;
4651
4652         return wm_latency_write(file, ubuf, len, offp, latencies);
4653 }
4654
4655 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4656                                     size_t len, loff_t *offp)
4657 {
4658         struct seq_file *m = file->private_data;
4659         struct drm_device *dev = m->private;
4660         struct drm_i915_private *dev_priv = dev->dev_private;
4661         uint16_t *latencies;
4662
4663         if (INTEL_INFO(dev)->gen >= 9)
4664                 latencies = dev_priv->wm.skl_latency;
4665         else
4666                 latencies = to_i915(dev)->wm.spr_latency;
4667
4668         return wm_latency_write(file, ubuf, len, offp, latencies);
4669 }
4670
4671 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4672                                     size_t len, loff_t *offp)
4673 {
4674         struct seq_file *m = file->private_data;
4675         struct drm_device *dev = m->private;
4676         struct drm_i915_private *dev_priv = dev->dev_private;
4677         uint16_t *latencies;
4678
4679         if (INTEL_INFO(dev)->gen >= 9)
4680                 latencies = dev_priv->wm.skl_latency;
4681         else
4682                 latencies = to_i915(dev)->wm.cur_latency;
4683
4684         return wm_latency_write(file, ubuf, len, offp, latencies);
4685 }
4686
4687 static const struct file_operations i915_pri_wm_latency_fops = {
4688         .owner = THIS_MODULE,
4689         .open = pri_wm_latency_open,
4690         .read = seq_read,
4691         .llseek = seq_lseek,
4692         .release = single_release,
4693         .write = pri_wm_latency_write
4694 };
4695
4696 static const struct file_operations i915_spr_wm_latency_fops = {
4697         .owner = THIS_MODULE,
4698         .open = spr_wm_latency_open,
4699         .read = seq_read,
4700         .llseek = seq_lseek,
4701         .release = single_release,
4702         .write = spr_wm_latency_write
4703 };
4704
4705 static const struct file_operations i915_cur_wm_latency_fops = {
4706         .owner = THIS_MODULE,
4707         .open = cur_wm_latency_open,
4708         .read = seq_read,
4709         .llseek = seq_lseek,
4710         .release = single_release,
4711         .write = cur_wm_latency_write
4712 };
4713
4714 static int
4715 i915_wedged_get(void *data, u64 *val)
4716 {
4717         struct drm_device *dev = data;
4718         struct drm_i915_private *dev_priv = dev->dev_private;
4719
4720         *val = atomic_read(&dev_priv->gpu_error.reset_counter);
4721
4722         return 0;
4723 }
4724
4725 static int
4726 i915_wedged_set(void *data, u64 val)
4727 {
4728         struct drm_device *dev = data;
4729         struct drm_i915_private *dev_priv = dev->dev_private;
4730
4731         /*
4732          * There is no safeguard against this debugfs entry colliding
4733          * with the hangcheck calling same i915_handle_error() in
4734          * parallel, causing an explosion. For now we assume that the
4735          * test harness is responsible enough not to inject gpu hangs
4736          * while it is writing to 'i915_wedged'
4737          */
4738
4739         if (i915_reset_in_progress(&dev_priv->gpu_error))
4740                 return -EAGAIN;
4741
4742         intel_runtime_pm_get(dev_priv);
4743
4744         i915_handle_error(dev, val,
4745                           "Manually setting wedged to %llu", val);
4746
4747         intel_runtime_pm_put(dev_priv);
4748
4749         return 0;
4750 }
4751
4752 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4753                         i915_wedged_get, i915_wedged_set,
4754                         "%llu\n");
4755
4756 static int
4757 i915_ring_stop_get(void *data, u64 *val)
4758 {
4759         struct drm_device *dev = data;
4760         struct drm_i915_private *dev_priv = dev->dev_private;
4761
4762         *val = dev_priv->gpu_error.stop_rings;
4763
4764         return 0;
4765 }
4766
4767 static int
4768 i915_ring_stop_set(void *data, u64 val)
4769 {
4770         struct drm_device *dev = data;
4771         struct drm_i915_private *dev_priv = dev->dev_private;
4772         int ret;
4773
4774         DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
4775
4776         ret = mutex_lock_interruptible(&dev->struct_mutex);
4777         if (ret)
4778                 return ret;
4779
4780         dev_priv->gpu_error.stop_rings = val;
4781         mutex_unlock(&dev->struct_mutex);
4782
4783         return 0;
4784 }
4785
4786 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
4787                         i915_ring_stop_get, i915_ring_stop_set,
4788                         "0x%08llx\n");
4789
4790 static int
4791 i915_ring_missed_irq_get(void *data, u64 *val)
4792 {
4793         struct drm_device *dev = data;
4794         struct drm_i915_private *dev_priv = dev->dev_private;
4795
4796         *val = dev_priv->gpu_error.missed_irq_rings;
4797         return 0;
4798 }
4799
4800 static int
4801 i915_ring_missed_irq_set(void *data, u64 val)
4802 {
4803         struct drm_device *dev = data;
4804         struct drm_i915_private *dev_priv = dev->dev_private;
4805         int ret;
4806
4807         /* Lock against concurrent debugfs callers */
4808         ret = mutex_lock_interruptible(&dev->struct_mutex);
4809         if (ret)
4810                 return ret;
4811         dev_priv->gpu_error.missed_irq_rings = val;
4812         mutex_unlock(&dev->struct_mutex);
4813
4814         return 0;
4815 }
4816
4817 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4818                         i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4819                         "0x%08llx\n");
4820
4821 static int
4822 i915_ring_test_irq_get(void *data, u64 *val)
4823 {
4824         struct drm_device *dev = data;
4825         struct drm_i915_private *dev_priv = dev->dev_private;
4826
4827         *val = dev_priv->gpu_error.test_irq_rings;
4828
4829         return 0;
4830 }
4831
4832 static int
4833 i915_ring_test_irq_set(void *data, u64 val)
4834 {
4835         struct drm_device *dev = data;
4836         struct drm_i915_private *dev_priv = dev->dev_private;
4837         int ret;
4838
4839         DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4840
4841         /* Lock against concurrent debugfs callers */
4842         ret = mutex_lock_interruptible(&dev->struct_mutex);
4843         if (ret)
4844                 return ret;
4845
4846         dev_priv->gpu_error.test_irq_rings = val;
4847         mutex_unlock(&dev->struct_mutex);
4848
4849         return 0;
4850 }
4851
4852 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4853                         i915_ring_test_irq_get, i915_ring_test_irq_set,
4854                         "0x%08llx\n");
4855
4856 #define DROP_UNBOUND 0x1
4857 #define DROP_BOUND 0x2
4858 #define DROP_RETIRE 0x4
4859 #define DROP_ACTIVE 0x8
4860 #define DROP_ALL (DROP_UNBOUND | \
4861                   DROP_BOUND | \
4862                   DROP_RETIRE | \
4863                   DROP_ACTIVE)
4864 static int
4865 i915_drop_caches_get(void *data, u64 *val)
4866 {
4867         *val = DROP_ALL;
4868
4869         return 0;
4870 }
4871
4872 static int
4873 i915_drop_caches_set(void *data, u64 val)
4874 {
4875         struct drm_device *dev = data;
4876         struct drm_i915_private *dev_priv = dev->dev_private;
4877         int ret;
4878
4879         DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4880
4881         /* No need to check and wait for gpu resets, only libdrm auto-restarts
4882          * on ioctls on -EAGAIN. */
4883         ret = mutex_lock_interruptible(&dev->struct_mutex);
4884         if (ret)
4885                 return ret;
4886
4887         if (val & DROP_ACTIVE) {
4888                 ret = i915_gpu_idle(dev);
4889                 if (ret)
4890                         goto unlock;
4891         }
4892
4893         if (val & (DROP_RETIRE | DROP_ACTIVE))
4894                 i915_gem_retire_requests(dev);
4895
4896         if (val & DROP_BOUND)
4897                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4898
4899         if (val & DROP_UNBOUND)
4900                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4901
4902 unlock:
4903         mutex_unlock(&dev->struct_mutex);
4904
4905         return ret;
4906 }
4907
4908 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4909                         i915_drop_caches_get, i915_drop_caches_set,
4910                         "0x%08llx\n");
4911
4912 static int
4913 i915_max_freq_get(void *data, u64 *val)
4914 {
4915         struct drm_device *dev = data;
4916         struct drm_i915_private *dev_priv = dev->dev_private;
4917         int ret;
4918
4919         if (INTEL_INFO(dev)->gen < 6)
4920                 return -ENODEV;
4921
4922         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4923
4924         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4925         if (ret)
4926                 return ret;
4927
4928         *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4929         mutex_unlock(&dev_priv->rps.hw_lock);
4930
4931         return 0;
4932 }
4933
4934 static int
4935 i915_max_freq_set(void *data, u64 val)
4936 {
4937         struct drm_device *dev = data;
4938         struct drm_i915_private *dev_priv = dev->dev_private;
4939         u32 hw_max, hw_min;
4940         int ret;
4941
4942         if (INTEL_INFO(dev)->gen < 6)
4943                 return -ENODEV;
4944
4945         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4946
4947         DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4948
4949         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4950         if (ret)
4951                 return ret;
4952
4953         /*
4954          * Turbo will still be enabled, but won't go above the set value.
4955          */
4956         val = intel_freq_opcode(dev_priv, val);
4957
4958         hw_max = dev_priv->rps.max_freq;
4959         hw_min = dev_priv->rps.min_freq;
4960
4961         if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4962                 mutex_unlock(&dev_priv->rps.hw_lock);
4963                 return -EINVAL;
4964         }
4965
4966         dev_priv->rps.max_freq_softlimit = val;
4967
4968         intel_set_rps(dev, val);
4969
4970         mutex_unlock(&dev_priv->rps.hw_lock);
4971
4972         return 0;
4973 }
4974
4975 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4976                         i915_max_freq_get, i915_max_freq_set,
4977                         "%llu\n");
4978
4979 static int
4980 i915_min_freq_get(void *data, u64 *val)
4981 {
4982         struct drm_device *dev = data;
4983         struct drm_i915_private *dev_priv = dev->dev_private;
4984         int ret;
4985
4986         if (INTEL_INFO(dev)->gen < 6)
4987                 return -ENODEV;
4988
4989         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4990
4991         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4992         if (ret)
4993                 return ret;
4994
4995         *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4996         mutex_unlock(&dev_priv->rps.hw_lock);
4997
4998         return 0;
4999 }
5000
5001 static int
5002 i915_min_freq_set(void *data, u64 val)
5003 {
5004         struct drm_device *dev = data;
5005         struct drm_i915_private *dev_priv = dev->dev_private;
5006         u32 hw_max, hw_min;
5007         int ret;
5008
5009         if (INTEL_INFO(dev)->gen < 6)
5010                 return -ENODEV;
5011
5012         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5013
5014         DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
5015
5016         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
5017         if (ret)
5018                 return ret;
5019
5020         /*
5021          * Turbo will still be enabled, but won't go below the set value.
5022          */
5023         val = intel_freq_opcode(dev_priv, val);
5024
5025         hw_max = dev_priv->rps.max_freq;
5026         hw_min = dev_priv->rps.min_freq;
5027
5028         if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
5029                 mutex_unlock(&dev_priv->rps.hw_lock);
5030                 return -EINVAL;
5031         }
5032
5033         dev_priv->rps.min_freq_softlimit = val;
5034
5035         intel_set_rps(dev, val);
5036
5037         mutex_unlock(&dev_priv->rps.hw_lock);
5038
5039         return 0;
5040 }
5041
5042 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
5043                         i915_min_freq_get, i915_min_freq_set,
5044                         "%llu\n");
5045
5046 static int
5047 i915_cache_sharing_get(void *data, u64 *val)
5048 {
5049         struct drm_device *dev = data;
5050         struct drm_i915_private *dev_priv = dev->dev_private;
5051         u32 snpcr;
5052         int ret;
5053
5054         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5055                 return -ENODEV;
5056
5057         ret = mutex_lock_interruptible(&dev->struct_mutex);
5058         if (ret)
5059                 return ret;
5060         intel_runtime_pm_get(dev_priv);
5061
5062         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5063
5064         intel_runtime_pm_put(dev_priv);
5065         mutex_unlock(&dev_priv->dev->struct_mutex);
5066
5067         *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
5068
5069         return 0;
5070 }
5071
5072 static int
5073 i915_cache_sharing_set(void *data, u64 val)
5074 {
5075         struct drm_device *dev = data;
5076         struct drm_i915_private *dev_priv = dev->dev_private;
5077         u32 snpcr;
5078
5079         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5080                 return -ENODEV;
5081
5082         if (val > 3)
5083                 return -EINVAL;
5084
5085         intel_runtime_pm_get(dev_priv);
5086         DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
5087
5088         /* Update the cache sharing policy here as well */
5089         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5090         snpcr &= ~GEN6_MBC_SNPCR_MASK;
5091         snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
5092         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5093
5094         intel_runtime_pm_put(dev_priv);
5095         return 0;
5096 }
5097
5098 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
5099                         i915_cache_sharing_get, i915_cache_sharing_set,
5100                         "%llu\n");
5101
5102 struct sseu_dev_status {
5103         unsigned int slice_total;
5104         unsigned int subslice_total;
5105         unsigned int subslice_per_slice;
5106         unsigned int eu_total;
5107         unsigned int eu_per_subslice;
5108 };
5109
5110 static void cherryview_sseu_device_status(struct drm_device *dev,
5111                                           struct sseu_dev_status *stat)
5112 {
5113         struct drm_i915_private *dev_priv = dev->dev_private;
5114         int ss_max = 2;
5115         int ss;
5116         u32 sig1[ss_max], sig2[ss_max];
5117
5118         sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
5119         sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
5120         sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
5121         sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
5122
5123         for (ss = 0; ss < ss_max; ss++) {
5124                 unsigned int eu_cnt;
5125
5126                 if (sig1[ss] & CHV_SS_PG_ENABLE)
5127                         /* skip disabled subslice */
5128                         continue;
5129
5130                 stat->slice_total = 1;
5131                 stat->subslice_per_slice++;
5132                 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
5133                          ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
5134                          ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
5135                          ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
5136                 stat->eu_total += eu_cnt;
5137                 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
5138         }
5139         stat->subslice_total = stat->subslice_per_slice;
5140 }
5141
5142 static void gen9_sseu_device_status(struct drm_device *dev,
5143                                     struct sseu_dev_status *stat)
5144 {
5145         struct drm_i915_private *dev_priv = dev->dev_private;
5146         int s_max = 3, ss_max = 4;
5147         int s, ss;
5148         u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
5149
5150         /* BXT has a single slice and at most 3 subslices. */
5151         if (IS_BROXTON(dev)) {
5152                 s_max = 1;
5153                 ss_max = 3;
5154         }
5155
5156         for (s = 0; s < s_max; s++) {
5157                 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
5158                 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
5159                 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
5160         }
5161
5162         eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
5163                      GEN9_PGCTL_SSA_EU19_ACK |
5164                      GEN9_PGCTL_SSA_EU210_ACK |
5165                      GEN9_PGCTL_SSA_EU311_ACK;
5166         eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
5167                      GEN9_PGCTL_SSB_EU19_ACK |
5168                      GEN9_PGCTL_SSB_EU210_ACK |
5169                      GEN9_PGCTL_SSB_EU311_ACK;
5170
5171         for (s = 0; s < s_max; s++) {
5172                 unsigned int ss_cnt = 0;
5173
5174                 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
5175                         /* skip disabled slice */
5176                         continue;
5177
5178                 stat->slice_total++;
5179
5180                 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
5181                         ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
5182
5183                 for (ss = 0; ss < ss_max; ss++) {
5184                         unsigned int eu_cnt;
5185
5186                         if (IS_BROXTON(dev) &&
5187                             !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
5188                                 /* skip disabled subslice */
5189                                 continue;
5190
5191                         if (IS_BROXTON(dev))
5192                                 ss_cnt++;
5193
5194                         eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
5195                                                eu_mask[ss%2]);
5196                         stat->eu_total += eu_cnt;
5197                         stat->eu_per_subslice = max(stat->eu_per_subslice,
5198                                                     eu_cnt);
5199                 }
5200
5201                 stat->subslice_total += ss_cnt;
5202                 stat->subslice_per_slice = max(stat->subslice_per_slice,
5203                                                ss_cnt);
5204         }
5205 }
5206
5207 static void broadwell_sseu_device_status(struct drm_device *dev,
5208                                          struct sseu_dev_status *stat)
5209 {
5210         struct drm_i915_private *dev_priv = dev->dev_private;
5211         int s;
5212         u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
5213
5214         stat->slice_total = hweight32(slice_info & GEN8_LSLICESTAT_MASK);
5215
5216         if (stat->slice_total) {
5217                 stat->subslice_per_slice = INTEL_INFO(dev)->subslice_per_slice;
5218                 stat->subslice_total = stat->slice_total *
5219                                        stat->subslice_per_slice;
5220                 stat->eu_per_subslice = INTEL_INFO(dev)->eu_per_subslice;
5221                 stat->eu_total = stat->eu_per_subslice * stat->subslice_total;
5222
5223                 /* subtract fused off EU(s) from enabled slice(s) */
5224                 for (s = 0; s < stat->slice_total; s++) {
5225                         u8 subslice_7eu = INTEL_INFO(dev)->subslice_7eu[s];
5226
5227                         stat->eu_total -= hweight8(subslice_7eu);
5228                 }
5229         }
5230 }
5231
5232 static int i915_sseu_status(struct seq_file *m, void *unused)
5233 {
5234         struct drm_info_node *node = (struct drm_info_node *) m->private;
5235         struct drm_device *dev = node->minor->dev;
5236         struct sseu_dev_status stat;
5237
5238         if (INTEL_INFO(dev)->gen < 8)
5239                 return -ENODEV;
5240
5241         seq_puts(m, "SSEU Device Info\n");
5242         seq_printf(m, "  Available Slice Total: %u\n",
5243                    INTEL_INFO(dev)->slice_total);
5244         seq_printf(m, "  Available Subslice Total: %u\n",
5245                    INTEL_INFO(dev)->subslice_total);
5246         seq_printf(m, "  Available Subslice Per Slice: %u\n",
5247                    INTEL_INFO(dev)->subslice_per_slice);
5248         seq_printf(m, "  Available EU Total: %u\n",
5249                    INTEL_INFO(dev)->eu_total);
5250         seq_printf(m, "  Available EU Per Subslice: %u\n",
5251                    INTEL_INFO(dev)->eu_per_subslice);
5252         seq_printf(m, "  Has Slice Power Gating: %s\n",
5253                    yesno(INTEL_INFO(dev)->has_slice_pg));
5254         seq_printf(m, "  Has Subslice Power Gating: %s\n",
5255                    yesno(INTEL_INFO(dev)->has_subslice_pg));
5256         seq_printf(m, "  Has EU Power Gating: %s\n",
5257                    yesno(INTEL_INFO(dev)->has_eu_pg));
5258
5259         seq_puts(m, "SSEU Device Status\n");
5260         memset(&stat, 0, sizeof(stat));
5261         if (IS_CHERRYVIEW(dev)) {
5262                 cherryview_sseu_device_status(dev, &stat);
5263         } else if (IS_BROADWELL(dev)) {
5264                 broadwell_sseu_device_status(dev, &stat);
5265         } else if (INTEL_INFO(dev)->gen >= 9) {
5266                 gen9_sseu_device_status(dev, &stat);
5267         }
5268         seq_printf(m, "  Enabled Slice Total: %u\n",
5269                    stat.slice_total);
5270         seq_printf(m, "  Enabled Subslice Total: %u\n",
5271                    stat.subslice_total);
5272         seq_printf(m, "  Enabled Subslice Per Slice: %u\n",
5273                    stat.subslice_per_slice);
5274         seq_printf(m, "  Enabled EU Total: %u\n",
5275                    stat.eu_total);
5276         seq_printf(m, "  Enabled EU Per Subslice: %u\n",
5277                    stat.eu_per_subslice);
5278
5279         return 0;
5280 }
5281
5282 static int i915_forcewake_open(struct inode *inode, struct file *file)
5283 {
5284         struct drm_device *dev = inode->i_private;
5285         struct drm_i915_private *dev_priv = dev->dev_private;
5286
5287         if (INTEL_INFO(dev)->gen < 6)
5288                 return 0;
5289
5290         intel_runtime_pm_get(dev_priv);
5291         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5292
5293         return 0;
5294 }
5295
5296 static int i915_forcewake_release(struct inode *inode, struct file *file)
5297 {
5298         struct drm_device *dev = inode->i_private;
5299         struct drm_i915_private *dev_priv = dev->dev_private;
5300
5301         if (INTEL_INFO(dev)->gen < 6)
5302                 return 0;
5303
5304         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5305         intel_runtime_pm_put(dev_priv);
5306
5307         return 0;
5308 }
5309
5310 static const struct file_operations i915_forcewake_fops = {
5311         .owner = THIS_MODULE,
5312         .open = i915_forcewake_open,
5313         .release = i915_forcewake_release,
5314 };
5315
5316 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5317 {
5318         struct drm_device *dev = minor->dev;
5319         struct dentry *ent;
5320
5321         ent = debugfs_create_file("i915_forcewake_user",
5322                                   S_IRUSR,
5323                                   root, dev,
5324                                   &i915_forcewake_fops);
5325         if (!ent)
5326                 return -ENOMEM;
5327
5328         return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
5329 }
5330
5331 static int i915_debugfs_create(struct dentry *root,
5332                                struct drm_minor *minor,
5333                                const char *name,
5334                                const struct file_operations *fops)
5335 {
5336         struct drm_device *dev = minor->dev;
5337         struct dentry *ent;
5338
5339         ent = debugfs_create_file(name,
5340                                   S_IRUGO | S_IWUSR,
5341                                   root, dev,
5342                                   fops);
5343         if (!ent)
5344                 return -ENOMEM;
5345
5346         return drm_add_fake_info_node(minor, ent, fops);
5347 }
5348
5349 static const struct drm_info_list i915_debugfs_list[] = {
5350         {"i915_capabilities", i915_capabilities, 0},
5351         {"i915_gem_objects", i915_gem_object_info, 0},
5352         {"i915_gem_gtt", i915_gem_gtt_info, 0},
5353         {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
5354         {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
5355         {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
5356         {"i915_gem_stolen", i915_gem_stolen_list_info },
5357         {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
5358         {"i915_gem_request", i915_gem_request_info, 0},
5359         {"i915_gem_seqno", i915_gem_seqno_info, 0},
5360         {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
5361         {"i915_gem_interrupt", i915_interrupt_info, 0},
5362         {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5363         {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5364         {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
5365         {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
5366         {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
5367         {"i915_guc_info", i915_guc_info, 0},
5368         {"i915_guc_load_status", i915_guc_load_status_info, 0},
5369         {"i915_guc_log_dump", i915_guc_log_dump, 0},
5370         {"i915_frequency_info", i915_frequency_info, 0},
5371         {"i915_hangcheck_info", i915_hangcheck_info, 0},
5372         {"i915_drpc_info", i915_drpc_info, 0},
5373         {"i915_emon_status", i915_emon_status, 0},
5374         {"i915_ring_freq_table", i915_ring_freq_table, 0},
5375         {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
5376         {"i915_fbc_status", i915_fbc_status, 0},
5377         {"i915_ips_status", i915_ips_status, 0},
5378         {"i915_sr_status", i915_sr_status, 0},
5379         {"i915_opregion", i915_opregion, 0},
5380         {"i915_vbt", i915_vbt, 0},
5381         {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
5382         {"i915_context_status", i915_context_status, 0},
5383         {"i915_dump_lrc", i915_dump_lrc, 0},
5384         {"i915_execlists", i915_execlists, 0},
5385         {"i915_forcewake_domains", i915_forcewake_domains, 0},
5386         {"i915_swizzle_info", i915_swizzle_info, 0},
5387         {"i915_ppgtt_info", i915_ppgtt_info, 0},
5388         {"i915_llc", i915_llc, 0},
5389         {"i915_edp_psr_status", i915_edp_psr_status, 0},
5390         {"i915_sink_crc_eDP1", i915_sink_crc, 0},
5391         {"i915_energy_uJ", i915_energy_uJ, 0},
5392         {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
5393         {"i915_power_domain_info", i915_power_domain_info, 0},
5394         {"i915_dmc_info", i915_dmc_info, 0},
5395         {"i915_display_info", i915_display_info, 0},
5396         {"i915_semaphore_status", i915_semaphore_status, 0},
5397         {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
5398         {"i915_dp_mst_info", i915_dp_mst_info, 0},
5399         {"i915_wa_registers", i915_wa_registers, 0},
5400         {"i915_ddb_info", i915_ddb_info, 0},
5401         {"i915_sseu_status", i915_sseu_status, 0},
5402         {"i915_drrs_status", i915_drrs_status, 0},
5403         {"i915_rps_boost_info", i915_rps_boost_info, 0},
5404 };
5405 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5406
5407 static const struct i915_debugfs_files {
5408         const char *name;
5409         const struct file_operations *fops;
5410 } i915_debugfs_files[] = {
5411         {"i915_wedged", &i915_wedged_fops},
5412         {"i915_max_freq", &i915_max_freq_fops},
5413         {"i915_min_freq", &i915_min_freq_fops},
5414         {"i915_cache_sharing", &i915_cache_sharing_fops},
5415         {"i915_ring_stop", &i915_ring_stop_fops},
5416         {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5417         {"i915_ring_test_irq", &i915_ring_test_irq_fops},
5418         {"i915_gem_drop_caches", &i915_drop_caches_fops},
5419         {"i915_error_state", &i915_error_state_fops},
5420         {"i915_next_seqno", &i915_next_seqno_fops},
5421         {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
5422         {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5423         {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5424         {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
5425         {"i915_fbc_false_color", &i915_fbc_fc_fops},
5426         {"i915_dp_test_data", &i915_displayport_test_data_fops},
5427         {"i915_dp_test_type", &i915_displayport_test_type_fops},
5428         {"i915_dp_test_active", &i915_displayport_test_active_fops}
5429 };
5430
5431 void intel_display_crc_init(struct drm_device *dev)
5432 {
5433         struct drm_i915_private *dev_priv = dev->dev_private;
5434         enum pipe pipe;
5435
5436         for_each_pipe(dev_priv, pipe) {
5437                 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
5438
5439                 pipe_crc->opened = false;
5440                 spin_lock_init(&pipe_crc->lock);
5441                 init_waitqueue_head(&pipe_crc->wq);
5442         }
5443 }
5444
5445 int i915_debugfs_init(struct drm_minor *minor)
5446 {
5447         int ret, i;
5448
5449         ret = i915_forcewake_create(minor->debugfs_root, minor);
5450         if (ret)
5451                 return ret;
5452
5453         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5454                 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5455                 if (ret)
5456                         return ret;
5457         }
5458
5459         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5460                 ret = i915_debugfs_create(minor->debugfs_root, minor,
5461                                           i915_debugfs_files[i].name,
5462                                           i915_debugfs_files[i].fops);
5463                 if (ret)
5464                         return ret;
5465         }
5466
5467         return drm_debugfs_create_files(i915_debugfs_list,
5468                                         I915_DEBUGFS_ENTRIES,
5469                                         minor->debugfs_root, minor);
5470 }
5471
5472 void i915_debugfs_cleanup(struct drm_minor *minor)
5473 {
5474         int i;
5475
5476         drm_debugfs_remove_files(i915_debugfs_list,
5477                                  I915_DEBUGFS_ENTRIES, minor);
5478
5479         drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
5480                                  1, minor);
5481
5482         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5483                 struct drm_info_list *info_list =
5484                         (struct drm_info_list *)&i915_pipe_crc_data[i];
5485
5486                 drm_debugfs_remove_files(info_list, 1, minor);
5487         }
5488
5489         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5490                 struct drm_info_list *info_list =
5491                         (struct drm_info_list *) i915_debugfs_files[i].fops;
5492
5493                 drm_debugfs_remove_files(info_list, 1, minor);
5494         }
5495 }
5496
5497 struct dpcd_block {
5498         /* DPCD dump start address. */
5499         unsigned int offset;
5500         /* DPCD dump end address, inclusive. If unset, .size will be used. */
5501         unsigned int end;
5502         /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5503         size_t size;
5504         /* Only valid for eDP. */
5505         bool edp;
5506 };
5507
5508 static const struct dpcd_block i915_dpcd_debug[] = {
5509         { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5510         { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5511         { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5512         { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5513         { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5514         { .offset = DP_SET_POWER },
5515         { .offset = DP_EDP_DPCD_REV },
5516         { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5517         { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5518         { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5519 };
5520
5521 static int i915_dpcd_show(struct seq_file *m, void *data)
5522 {
5523         struct drm_connector *connector = m->private;
5524         struct intel_dp *intel_dp =
5525                 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5526         uint8_t buf[16];
5527         ssize_t err;
5528         int i;
5529
5530         if (connector->status != connector_status_connected)
5531                 return -ENODEV;
5532
5533         for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5534                 const struct dpcd_block *b = &i915_dpcd_debug[i];
5535                 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5536
5537                 if (b->edp &&
5538                     connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5539                         continue;
5540
5541                 /* low tech for now */
5542                 if (WARN_ON(size > sizeof(buf)))
5543                         continue;
5544
5545                 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5546                 if (err <= 0) {
5547                         DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5548                                   size, b->offset, err);
5549                         continue;
5550                 }
5551
5552                 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
5553         }
5554
5555         return 0;
5556 }
5557
5558 static int i915_dpcd_open(struct inode *inode, struct file *file)
5559 {
5560         return single_open(file, i915_dpcd_show, inode->i_private);
5561 }
5562
5563 static const struct file_operations i915_dpcd_fops = {
5564         .owner = THIS_MODULE,
5565         .open = i915_dpcd_open,
5566         .read = seq_read,
5567         .llseek = seq_lseek,
5568         .release = single_release,
5569 };
5570
5571 /**
5572  * i915_debugfs_connector_add - add i915 specific connector debugfs files
5573  * @connector: pointer to a registered drm_connector
5574  *
5575  * Cleanup will be done by drm_connector_unregister() through a call to
5576  * drm_debugfs_connector_remove().
5577  *
5578  * Returns 0 on success, negative error codes on error.
5579  */
5580 int i915_debugfs_connector_add(struct drm_connector *connector)
5581 {
5582         struct dentry *root = connector->debugfs_entry;
5583
5584         /* The connector must have been registered beforehands. */
5585         if (!root)
5586                 return -ENODEV;
5587
5588         if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5589             connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5590                 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,
5591                                     &i915_dpcd_fops);
5592
5593         return 0;
5594 }