drivers/gpu/drm/i915/i915_debugfs.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *
  27  */
  28
  29 #include <linux/seq_file.h>
  30 #include <linux/circ_buf.h>
  31 #include <linux/ctype.h>
  32 #include <linux/debugfs.h>
  33 #include <linux/slab.h>
  34 #include <linux/export.h>
  35 #include <linux/list_sort.h>
  36 #include <asm/msr-index.h>
  37 #include <drm/drmP.h>
  38 #include "intel_drv.h"
  39 #include "intel_ringbuffer.h"
  40 #include <drm/i915_drm.h>
  41 #include "i915_drv.h"
  42
  43 static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
  44 {
  45         return to_i915(node->minor->dev);
  46 }
  47
  48 /* As the drm_debugfs_init() routines are called before dev->dev_private is
  49  * allocated we need to hook into the minor for release. */
  50 static int
  51 drm_add_fake_info_node(struct drm_minor *minor,
  52                        struct dentry *ent,
  53                        const void *key)
  54 {
  55         struct drm_info_node *node;
  56
  57         node = kmalloc(sizeof(*node), GFP_KERNEL);
  58         if (node == NULL) {
  59                 debugfs_remove(ent);
  60                 return -ENOMEM;
  61         }
  62
  63         node->minor = minor;
  64         node->dent = ent;
  65         node->info_ent = (void *)key;
  66
  67         mutex_lock(&minor->debugfs_lock);
  68         list_add(&node->list, &minor->debugfs_list);
  69         mutex_unlock(&minor->debugfs_lock);
  70
  71         return 0;
  72 }
  73
  74 static int i915_capabilities(struct seq_file *m, void *data)
  75 {
  76         struct drm_i915_private *dev_priv = node_to_i915(m->private);
  77         const struct intel_device_info *info = INTEL_INFO(dev_priv);
  78
  79         seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv));
  80         seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv));
  81 #define PRINT_FLAG(x)  seq_printf(m, #x ": %s\n", yesno(info->x))
  82         DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
  83 #undef PRINT_FLAG
  84
  85         return 0;
  86 }
  87
  88 static char get_active_flag(struct drm_i915_gem_object *obj)
  89 {
  90         return i915_gem_object_is_active(obj) ? '*' : ' ';
  91 }
  92
  93 static char get_pin_flag(struct drm_i915_gem_object *obj)
  94 {
  95         return obj->pin_display ? 'p' : ' ';
  96 }
  97
  98 static char get_tiling_flag(struct drm_i915_gem_object *obj)
  99 {
 100         switch (i915_gem_object_get_tiling(obj)) {
 101         default:
 102         case I915_TILING_NONE: return ' ';
 103         case I915_TILING_X: return 'X';
 104         case I915_TILING_Y: return 'Y';
 105         }
 106 }
 107
 108 static char get_global_flag(struct drm_i915_gem_object *obj)
 109 {
 110         return i915_gem_object_to_ggtt(obj, NULL) ?  'g' : ' ';
 111 }
 112
 113 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
 114 {
 115         return obj->mapping ? 'M' : ' ';
 116 }
 117
 118 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
 119 {
 120         u64 size = 0;
 121         struct i915_vma *vma;
 122
 123         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 124                 if (i915_vma_is_ggtt(vma) && drm_mm_node_allocated(&vma->node))
 125                         size += vma->node.size;
 126         }
 127
 128         return size;
 129 }
 130
 131 static void
 132 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
 133 {
 134         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
 135         struct intel_engine_cs *engine;
 136         struct i915_vma *vma;
 137         unsigned int frontbuffer_bits;
 138         int pin_count = 0;
 139         enum intel_engine_id id;
 140
 141         lockdep_assert_held(&obj->base.dev->struct_mutex);
 142
 143         seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x [ ",
 144                    &obj->base,
 145                    get_active_flag(obj),
 146                    get_pin_flag(obj),
 147                    get_tiling_flag(obj),
 148                    get_global_flag(obj),
 149                    get_pin_mapped_flag(obj),
 150                    obj->base.size / 1024,
 151                    obj->base.read_domains,
 152                    obj->base.write_domain);
 153         for_each_engine_id(engine, dev_priv, id)
 154                 seq_printf(m, "%x ",
 155                            i915_gem_active_get_seqno(&obj->last_read[id],
 156                                                      &obj->base.dev->struct_mutex));
 157         seq_printf(m, "] %x %s%s%s",
 158                    i915_gem_active_get_seqno(&obj->last_write,
 159                                              &obj->base.dev->struct_mutex),
 160                    i915_cache_level_str(dev_priv, obj->cache_level),
 161                    obj->dirty ? " dirty" : "",
 162                    obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
 163         if (obj->base.name)
 164                 seq_printf(m, " (name: %d)", obj->base.name);
 165         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 166                 if (i915_vma_is_pinned(vma))
 167                         pin_count++;
 168         }
 169         seq_printf(m, " (pinned x %d)", pin_count);
 170         if (obj->pin_display)
 171                 seq_printf(m, " (display)");
 172         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 173                 if (!drm_mm_node_allocated(&vma->node))
 174                         continue;
 175
 176                 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
 177                            i915_vma_is_ggtt(vma) ? "g" : "pp",
 178                            vma->node.start, vma->node.size);
 179                 if (i915_vma_is_ggtt(vma))
 180                         seq_printf(m, ", type: %u", vma->ggtt_view.type);
 181                 if (vma->fence)
 182                         seq_printf(m, " , fence: %d%s",
 183                                    vma->fence->id,
 184                                    i915_gem_active_isset(&vma->last_fence) ? "*" : "");
 185                 seq_puts(m, ")");
 186         }
 187         if (obj->stolen)
 188                 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
 189         if (obj->pin_display || obj->fault_mappable) {
 190                 char s[3], *t = s;
 191                 if (obj->pin_display)
 192                         *t++ = 'p';
 193                 if (obj->fault_mappable)
 194                         *t++ = 'f';
 195                 *t = '\0';
 196                 seq_printf(m, " (%s mappable)", s);
 197         }
 198
 199         engine = i915_gem_active_get_engine(&obj->last_write,
 200                                             &dev_priv->drm.struct_mutex);
 201         if (engine)
 202                 seq_printf(m, " (%s)", engine->name);
 203
 204         frontbuffer_bits = atomic_read(&obj->frontbuffer_bits);
 205         if (frontbuffer_bits)
 206                 seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits);
 207 }
 208
 209 static int obj_rank_by_stolen(void *priv,
 210                               struct list_head *A, struct list_head *B)
 211 {
 212         struct drm_i915_gem_object *a =
 213                 container_of(A, struct drm_i915_gem_object, obj_exec_link);
 214         struct drm_i915_gem_object *b =
 215                 container_of(B, struct drm_i915_gem_object, obj_exec_link);
 216
 217         if (a->stolen->start < b->stolen->start)
 218                 return -1;
 219         if (a->stolen->start > b->stolen->start)
 220                 return 1;
 221         return 0;
 222 }
 223
 224 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
 225 {
 226         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 227         struct drm_device *dev = &dev_priv->drm;
 228         struct drm_i915_gem_object *obj;
 229         u64 total_obj_size, total_gtt_size;
 230         LIST_HEAD(stolen);
 231         int count, ret;
 232
 233         ret = mutex_lock_interruptible(&dev->struct_mutex);
 234         if (ret)
 235                 return ret;
 236
 237         total_obj_size = total_gtt_size = count = 0;
 238         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 239                 if (obj->stolen == NULL)
 240                         continue;
 241
 242                 list_add(&obj->obj_exec_link, &stolen);
 243
 244                 total_obj_size += obj->base.size;
 245                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 246                 count++;
 247         }
 248         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 249                 if (obj->stolen == NULL)
 250                         continue;
 251
 252                 list_add(&obj->obj_exec_link, &stolen);
 253
 254                 total_obj_size += obj->base.size;
 255                 count++;
 256         }
 257         list_sort(NULL, &stolen, obj_rank_by_stolen);
 258         seq_puts(m, "Stolen:\n");
 259         while (!list_empty(&stolen)) {
 260                 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
 261                 seq_puts(m, "   ");
 262                 describe_obj(m, obj);
 263                 seq_putc(m, '\n');
 264                 list_del_init(&obj->obj_exec_link);
 265         }
 266         mutex_unlock(&dev->struct_mutex);
 267
 268         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 269                    count, total_obj_size, total_gtt_size);
 270         return 0;
 271 }
 272
 273 struct file_stats {
 274         struct drm_i915_file_private *file_priv;
 275         unsigned long count;
 276         u64 total, unbound;
 277         u64 global, shared;
 278         u64 active, inactive;
 279 };
 280
 281 static int per_file_stats(int id, void *ptr, void *data)
 282 {
 283         struct drm_i915_gem_object *obj = ptr;
 284         struct file_stats *stats = data;
 285         struct i915_vma *vma;
 286
 287         stats->count++;
 288         stats->total += obj->base.size;
 289         if (!obj->bind_count)
 290                 stats->unbound += obj->base.size;
 291         if (obj->base.name || obj->base.dma_buf)
 292                 stats->shared += obj->base.size;
 293
 294         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 295                 if (!drm_mm_node_allocated(&vma->node))
 296                         continue;
 297
 298                 if (i915_vma_is_ggtt(vma)) {
 299                         stats->global += vma->node.size;
 300                 } else {
 301                         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm);
 302
 303                         if (ppgtt->base.file != stats->file_priv)
 304                                 continue;
 305                 }
 306
 307                 if (i915_vma_is_active(vma))
 308                         stats->active += vma->node.size;
 309                 else
 310                         stats->inactive += vma->node.size;
 311         }
 312
 313         return 0;
 314 }
 315
 316 #define print_file_stats(m, name, stats) do { \
 317         if (stats.count) \
 318                 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
 319                            name, \
 320                            stats.count, \
 321                            stats.total, \
 322                            stats.active, \
 323                            stats.inactive, \
 324                            stats.global, \
 325                            stats.shared, \
 326                            stats.unbound); \
 327 } while (0)
 328
 329 static void print_batch_pool_stats(struct seq_file *m,
 330                                    struct drm_i915_private *dev_priv)
 331 {
 332         struct drm_i915_gem_object *obj;
 333         struct file_stats stats;
 334         struct intel_engine_cs *engine;
 335         int j;
 336
 337         memset(&stats, 0, sizeof(stats));
 338
 339         for_each_engine(engine, dev_priv) {
 340                 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
 341                         list_for_each_entry(obj,
 342                                             &engine->batch_pool.cache_list[j],
 343                                             batch_pool_link)
 344                                 per_file_stats(0, obj, &stats);
 345                 }
 346         }
 347
 348         print_file_stats(m, "[k]batch pool", stats);
 349 }
 350
 351 static int per_file_ctx_stats(int id, void *ptr, void *data)
 352 {
 353         struct i915_gem_context *ctx = ptr;
 354         int n;
 355
 356         for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) {
 357                 if (ctx->engine[n].state)
 358                         per_file_stats(0, ctx->engine[n].state->obj, data);
 359                 if (ctx->engine[n].ring)
 360                         per_file_stats(0, ctx->engine[n].ring->vma->obj, data);
 361         }
 362
 363         return 0;
 364 }
 365
 366 static void print_context_stats(struct seq_file *m,
 367                                 struct drm_i915_private *dev_priv)
 368 {
 369         struct drm_device *dev = &dev_priv->drm;
 370         struct file_stats stats;
 371         struct drm_file *file;
 372
 373         memset(&stats, 0, sizeof(stats));
 374
 375         mutex_lock(&dev->struct_mutex);
 376         if (dev_priv->kernel_context)
 377                 per_file_ctx_stats(0, dev_priv->kernel_context, &stats);
 378
 379         list_for_each_entry(file, &dev->filelist, lhead) {
 380                 struct drm_i915_file_private *fpriv = file->driver_priv;
 381                 idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats);
 382         }
 383         mutex_unlock(&dev->struct_mutex);
 384
 385         print_file_stats(m, "[k]contexts", stats);
 386 }
 387
 388 static int i915_gem_object_info(struct seq_file *m, void *data)
 389 {
 390         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 391         struct drm_device *dev = &dev_priv->drm;
 392         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 393         u32 count, mapped_count, purgeable_count, dpy_count;
 394         u64 size, mapped_size, purgeable_size, dpy_size;
 395         struct drm_i915_gem_object *obj;
 396         struct drm_file *file;
 397         int ret;
 398
 399         ret = mutex_lock_interruptible(&dev->struct_mutex);
 400         if (ret)
 401                 return ret;
 402
 403         seq_printf(m, "%u objects, %zu bytes\n",
 404                    dev_priv->mm.object_count,
 405                    dev_priv->mm.object_memory);
 406
 407         size = count = 0;
 408         mapped_size = mapped_count = 0;
 409         purgeable_size = purgeable_count = 0;
 410         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 411                 size += obj->base.size;
 412                 ++count;
 413
 414                 if (obj->madv == I915_MADV_DONTNEED) {
 415                         purgeable_size += obj->base.size;
 416                         ++purgeable_count;
 417                 }
 418
 419                 if (obj->mapping) {
 420                         mapped_count++;
 421                         mapped_size += obj->base.size;
 422                 }
 423         }
 424         seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
 425
 426         size = count = dpy_size = dpy_count = 0;
 427         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 428                 size += obj->base.size;
 429                 ++count;
 430
 431                 if (obj->pin_display) {
 432                         dpy_size += obj->base.size;
 433                         ++dpy_count;
 434                 }
 435
 436                 if (obj->madv == I915_MADV_DONTNEED) {
 437                         purgeable_size += obj->base.size;
 438                         ++purgeable_count;
 439                 }
 440
 441                 if (obj->mapping) {
 442                         mapped_count++;
 443                         mapped_size += obj->base.size;
 444                 }
 445         }
 446         seq_printf(m, "%u bound objects, %llu bytes\n",
 447                    count, size);
 448         seq_printf(m, "%u purgeable objects, %llu bytes\n",
 449                    purgeable_count, purgeable_size);
 450         seq_printf(m, "%u mapped objects, %llu bytes\n",
 451                    mapped_count, mapped_size);
 452         seq_printf(m, "%u display objects (pinned), %llu bytes\n",
 453                    dpy_count, dpy_size);
 454
 455         seq_printf(m, "%llu [%llu] gtt total\n",
 456                    ggtt->base.total, ggtt->mappable_end - ggtt->base.start);
 457
 458         seq_putc(m, '\n');
 459         print_batch_pool_stats(m, dev_priv);
 460         mutex_unlock(&dev->struct_mutex);
 461
 462         mutex_lock(&dev->filelist_mutex);
 463         print_context_stats(m, dev_priv);
 464         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
 465                 struct file_stats stats;
 466                 struct drm_i915_file_private *file_priv = file->driver_priv;
 467                 struct drm_i915_gem_request *request;
 468                 struct task_struct *task;
 469
 470                 memset(&stats, 0, sizeof(stats));
 471                 stats.file_priv = file->driver_priv;
 472                 spin_lock(&file->table_lock);
 473                 idr_for_each(&file->object_idr, per_file_stats, &stats);
 474                 spin_unlock(&file->table_lock);
 475                 /*
 476                  * Although we have a valid reference on file->pid, that does
 477                  * not guarantee that the task_struct who called get_pid() is
 478                  * still alive (e.g. get_pid(current) => fork() => exit()).
 479                  * Therefore, we need to protect this ->comm access using RCU.
 480                  */
 481                 mutex_lock(&dev->struct_mutex);
 482                 request = list_first_entry_or_null(&file_priv->mm.request_list,
 483                                                    struct drm_i915_gem_request,
 484                                                    client_list);
 485                 rcu_read_lock();
 486                 task = pid_task(request && request->ctx->pid ?
 487                                 request->ctx->pid : file->pid,
 488                                 PIDTYPE_PID);
 489                 print_file_stats(m, task ? task->comm : "<unknown>", stats);
 490                 rcu_read_unlock();
 491                 mutex_unlock(&dev->struct_mutex);
 492         }
 493         mutex_unlock(&dev->filelist_mutex);
 494
 495         return 0;
 496 }
 497
 498 static int i915_gem_gtt_info(struct seq_file *m, void *data)
 499 {
 500         struct drm_info_node *node = m->private;
 501         struct drm_i915_private *dev_priv = node_to_i915(node);
 502         struct drm_device *dev = &dev_priv->drm;
 503         bool show_pin_display_only = !!node->info_ent->data;
 504         struct drm_i915_gem_object *obj;
 505         u64 total_obj_size, total_gtt_size;
 506         int count, ret;
 507
 508         ret = mutex_lock_interruptible(&dev->struct_mutex);
 509         if (ret)
 510                 return ret;
 511
 512         total_obj_size = total_gtt_size = count = 0;
 513         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 514                 if (show_pin_display_only && !obj->pin_display)
 515                         continue;
 516
 517                 seq_puts(m, "   ");
 518                 describe_obj(m, obj);
 519                 seq_putc(m, '\n');
 520                 total_obj_size += obj->base.size;
 521                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 522                 count++;
 523         }
 524
 525         mutex_unlock(&dev->struct_mutex);
 526
 527         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 528                    count, total_obj_size, total_gtt_size);
 529
 530         return 0;
 531 }
 532
 533 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
 534 {
 535         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 536         struct drm_device *dev = &dev_priv->drm;
 537         struct intel_crtc *crtc;
 538         int ret;
 539
 540         ret = mutex_lock_interruptible(&dev->struct_mutex);
 541         if (ret)
 542                 return ret;
 543
 544         for_each_intel_crtc(dev, crtc) {
 545                 const char pipe = pipe_name(crtc->pipe);
 546                 const char plane = plane_name(crtc->plane);
 547                 struct intel_flip_work *work;
 548
 549                 spin_lock_irq(&dev->event_lock);
 550                 work = crtc->flip_work;
 551                 if (work == NULL) {
 552                         seq_printf(m, "No flip due on pipe %c (plane %c)\n",
 553                                    pipe, plane);
 554                 } else {
 555                         u32 pending;
 556                         u32 addr;
 557
 558                         pending = atomic_read(&work->pending);
 559                         if (pending) {
 560                                 seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n",
 561                                            pipe, plane);
 562                         } else {
 563                                 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
 564                                            pipe, plane);
 565                         }
 566                         if (work->flip_queued_req) {
 567                                 struct intel_engine_cs *engine = i915_gem_request_get_engine(work->flip_queued_req);
 568
 569                                 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
 570                                            engine->name,
 571                                            i915_gem_request_get_seqno(work->flip_queued_req),
 572                                            dev_priv->next_seqno,
 573                                            intel_engine_get_seqno(engine),
 574                                            i915_gem_request_completed(work->flip_queued_req));
 575                         } else
 576                                 seq_printf(m, "Flip not associated with any ring\n");
 577                         seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
 578                                    work->flip_queued_vblank,
 579                                    work->flip_ready_vblank,
 580                                    intel_crtc_get_vblank_counter(crtc));
 581                         seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
 582
 583                         if (INTEL_GEN(dev_priv) >= 4)
 584                                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
 585                         else
 586                                 addr = I915_READ(DSPADDR(crtc->plane));
 587                         seq_printf(m, "Current scanout address 0x%08x\n", addr);
 588
 589                         if (work->pending_flip_obj) {
 590                                 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
 591                                 seq_printf(m, "MMIO update completed? %d\n",  addr == work->gtt_offset);
 592                         }
 593                 }
 594                 spin_unlock_irq(&dev->event_lock);
 595         }
 596
 597         mutex_unlock(&dev->struct_mutex);
 598
 599         return 0;
 600 }
 601
 602 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
 603 {
 604         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 605         struct drm_device *dev = &dev_priv->drm;
 606         struct drm_i915_gem_object *obj;
 607         struct intel_engine_cs *engine;
 608         int total = 0;
 609         int ret, j;
 610
 611         ret = mutex_lock_interruptible(&dev->struct_mutex);
 612         if (ret)
 613                 return ret;
 614
 615         for_each_engine(engine, dev_priv) {
 616                 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
 617                         int count;
 618
 619                         count = 0;
 620                         list_for_each_entry(obj,
 621                                             &engine->batch_pool.cache_list[j],
 622                                             batch_pool_link)
 623                                 count++;
 624                         seq_printf(m, "%s cache[%d]: %d objects\n",
 625                                    engine->name, j, count);
 626
 627                         list_for_each_entry(obj,
 628                                             &engine->batch_pool.cache_list[j],
 629                                             batch_pool_link) {
 630                                 seq_puts(m, "   ");
 631                                 describe_obj(m, obj);
 632                                 seq_putc(m, '\n');
 633                         }
 634
 635                         total += count;
 636                 }
 637         }
 638
 639         seq_printf(m, "total: %d\n", total);
 640
 641         mutex_unlock(&dev->struct_mutex);
 642
 643         return 0;
 644 }
 645
 646 static void print_request(struct seq_file *m,
 647                           struct drm_i915_gem_request *rq,
 648                           const char *prefix)
 649 {
 650         struct pid *pid = rq->ctx->pid;
 651         struct task_struct *task;
 652
 653         rcu_read_lock();
 654         task = pid ? pid_task(pid, PIDTYPE_PID) : NULL;
 655         seq_printf(m, "%s%x [%x:%x] @ %d: %s [%d]\n", prefix,
 656                    rq->fence.seqno, rq->ctx->hw_id, rq->fence.seqno,
 657                    jiffies_to_msecs(jiffies - rq->emitted_jiffies),
 658                    task ? task->comm : "<unknown>",
 659                    task ? task->pid : -1);
 660         rcu_read_unlock();
 661 }
 662
 663 static int i915_gem_request_info(struct seq_file *m, void *data)
 664 {
 665         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 666         struct drm_device *dev = &dev_priv->drm;
 667         struct intel_engine_cs *engine;
 668         struct drm_i915_gem_request *req;
 669         int ret, any;
 670
 671         ret = mutex_lock_interruptible(&dev->struct_mutex);
 672         if (ret)
 673                 return ret;
 674
 675         any = 0;
 676         for_each_engine(engine, dev_priv) {
 677                 int count;
 678
 679                 count = 0;
 680                 list_for_each_entry(req, &engine->request_list, link)
 681                         count++;
 682                 if (count == 0)
 683                         continue;
 684
 685                 seq_printf(m, "%s requests: %d\n", engine->name, count);
 686                 list_for_each_entry(req, &engine->request_list, link)
 687                         print_request(m, req, "    ");
 688
 689                 any++;
 690         }
 691         mutex_unlock(&dev->struct_mutex);
 692
 693         if (any == 0)
 694                 seq_puts(m, "No requests\n");
 695
 696         return 0;
 697 }
 698
 699 static void i915_ring_seqno_info(struct seq_file *m,
 700                                  struct intel_engine_cs *engine)
 701 {
 702         struct intel_breadcrumbs *b = &engine->breadcrumbs;
 703         struct rb_node *rb;
 704
 705         seq_printf(m, "Current sequence (%s): %x\n",
 706                    engine->name, intel_engine_get_seqno(engine));
 707
 708         spin_lock(&b->lock);
 709         for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
 710                 struct intel_wait *w = container_of(rb, typeof(*w), node);
 711
 712                 seq_printf(m, "Waiting (%s): %s [%d] on %x\n",
 713                            engine->name, w->tsk->comm, w->tsk->pid, w->seqno);
 714         }
 715         spin_unlock(&b->lock);
 716 }
 717
 718 static int i915_gem_seqno_info(struct seq_file *m, void *data)
 719 {
 720         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 721         struct intel_engine_cs *engine;
 722
 723         for_each_engine(engine, dev_priv)
 724                 i915_ring_seqno_info(m, engine);
 725
 726         return 0;
 727 }
 728
 729
 730 static int i915_interrupt_info(struct seq_file *m, void *data)
 731 {
 732         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 733         struct intel_engine_cs *engine;
 734         int i, pipe;
 735
 736         intel_runtime_pm_get(dev_priv);
 737
 738         if (IS_CHERRYVIEW(dev_priv)) {
 739                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 740                            I915_READ(GEN8_MASTER_IRQ));
 741
 742                 seq_printf(m, "Display IER:\t%08x\n",
 743                            I915_READ(VLV_IER));
 744                 seq_printf(m, "Display IIR:\t%08x\n",
 745                            I915_READ(VLV_IIR));
 746                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 747                            I915_READ(VLV_IIR_RW));
 748                 seq_printf(m, "Display IMR:\t%08x\n",
 749                            I915_READ(VLV_IMR));
 750                 for_each_pipe(dev_priv, pipe)
 751                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 752                                    pipe_name(pipe),
 753                                    I915_READ(PIPESTAT(pipe)));
 754
 755                 seq_printf(m, "Port hotplug:\t%08x\n",
 756                            I915_READ(PORT_HOTPLUG_EN));
 757                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 758                            I915_READ(VLV_DPFLIPSTAT));
 759                 seq_printf(m, "DPINVGTT:\t%08x\n",
 760                            I915_READ(DPINVGTT));
 761
 762                 for (i = 0; i < 4; i++) {
 763                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 764                                    i, I915_READ(GEN8_GT_IMR(i)));
 765                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 766                                    i, I915_READ(GEN8_GT_IIR(i)));
 767                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 768                                    i, I915_READ(GEN8_GT_IER(i)));
 769                 }
 770
 771                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 772                            I915_READ(GEN8_PCU_IMR));
 773                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 774                            I915_READ(GEN8_PCU_IIR));
 775                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 776                            I915_READ(GEN8_PCU_IER));
 777         } else if (INTEL_GEN(dev_priv) >= 8) {
 778                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 779                            I915_READ(GEN8_MASTER_IRQ));
 780
 781                 for (i = 0; i < 4; i++) {
 782                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 783                                    i, I915_READ(GEN8_GT_IMR(i)));
 784                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 785                                    i, I915_READ(GEN8_GT_IIR(i)));
 786                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 787                                    i, I915_READ(GEN8_GT_IER(i)));
 788                 }
 789
 790                 for_each_pipe(dev_priv, pipe) {
 791                         enum intel_display_power_domain power_domain;
 792
 793                         power_domain = POWER_DOMAIN_PIPE(pipe);
 794                         if (!intel_display_power_get_if_enabled(dev_priv,
 795                                                                 power_domain)) {
 796                                 seq_printf(m, "Pipe %c power disabled\n",
 797                                            pipe_name(pipe));
 798                                 continue;
 799                         }
 800                         seq_printf(m, "Pipe %c IMR:\t%08x\n",
 801                                    pipe_name(pipe),
 802                                    I915_READ(GEN8_DE_PIPE_IMR(pipe)));
 803                         seq_printf(m, "Pipe %c IIR:\t%08x\n",
 804                                    pipe_name(pipe),
 805                                    I915_READ(GEN8_DE_PIPE_IIR(pipe)));
 806                         seq_printf(m, "Pipe %c IER:\t%08x\n",
 807                                    pipe_name(pipe),
 808                                    I915_READ(GEN8_DE_PIPE_IER(pipe)));
 809
 810                         intel_display_power_put(dev_priv, power_domain);
 811                 }
 812
 813                 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
 814                            I915_READ(GEN8_DE_PORT_IMR));
 815                 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
 816                            I915_READ(GEN8_DE_PORT_IIR));
 817                 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
 818                            I915_READ(GEN8_DE_PORT_IER));
 819
 820                 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
 821                            I915_READ(GEN8_DE_MISC_IMR));
 822                 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
 823                            I915_READ(GEN8_DE_MISC_IIR));
 824                 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
 825                            I915_READ(GEN8_DE_MISC_IER));
 826
 827                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 828                            I915_READ(GEN8_PCU_IMR));
 829                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 830                            I915_READ(GEN8_PCU_IIR));
 831                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 832                            I915_READ(GEN8_PCU_IER));
 833         } else if (IS_VALLEYVIEW(dev_priv)) {
 834                 seq_printf(m, "Display IER:\t%08x\n",
 835                            I915_READ(VLV_IER));
 836                 seq_printf(m, "Display IIR:\t%08x\n",
 837                            I915_READ(VLV_IIR));
 838                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 839                            I915_READ(VLV_IIR_RW));
 840                 seq_printf(m, "Display IMR:\t%08x\n",
 841                            I915_READ(VLV_IMR));
 842                 for_each_pipe(dev_priv, pipe)
 843                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 844                                    pipe_name(pipe),
 845                                    I915_READ(PIPESTAT(pipe)));
 846
 847                 seq_printf(m, "Master IER:\t%08x\n",
 848                            I915_READ(VLV_MASTER_IER));
 849
 850                 seq_printf(m, "Render IER:\t%08x\n",
 851                            I915_READ(GTIER));
 852                 seq_printf(m, "Render IIR:\t%08x\n",
 853                            I915_READ(GTIIR));
 854                 seq_printf(m, "Render IMR:\t%08x\n",
 855                            I915_READ(GTIMR));
 856
 857                 seq_printf(m, "PM IER:\t\t%08x\n",
 858                            I915_READ(GEN6_PMIER));
 859                 seq_printf(m, "PM IIR:\t\t%08x\n",
 860                            I915_READ(GEN6_PMIIR));
 861                 seq_printf(m, "PM IMR:\t\t%08x\n",
 862                            I915_READ(GEN6_PMIMR));
 863
 864                 seq_printf(m, "Port hotplug:\t%08x\n",
 865                            I915_READ(PORT_HOTPLUG_EN));
 866                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 867                            I915_READ(VLV_DPFLIPSTAT));
 868                 seq_printf(m, "DPINVGTT:\t%08x\n",
 869                            I915_READ(DPINVGTT));
 870
 871         } else if (!HAS_PCH_SPLIT(dev_priv)) {
 872                 seq_printf(m, "Interrupt enable:    %08x\n",
 873                            I915_READ(IER));
 874                 seq_printf(m, "Interrupt identity:  %08x\n",
 875                            I915_READ(IIR));
 876                 seq_printf(m, "Interrupt mask:      %08x\n",
 877                            I915_READ(IMR));
 878                 for_each_pipe(dev_priv, pipe)
 879                         seq_printf(m, "Pipe %c stat:         %08x\n",
 880                                    pipe_name(pipe),
 881                                    I915_READ(PIPESTAT(pipe)));
 882         } else {
 883                 seq_printf(m, "North Display Interrupt enable:          %08x\n",
 884                            I915_READ(DEIER));
 885                 seq_printf(m, "North Display Interrupt identity:        %08x\n",
 886                            I915_READ(DEIIR));
 887                 seq_printf(m, "North Display Interrupt mask:            %08x\n",
 888                            I915_READ(DEIMR));
 889                 seq_printf(m, "South Display Interrupt enable:          %08x\n",
 890                            I915_READ(SDEIER));
 891                 seq_printf(m, "South Display Interrupt identity:        %08x\n",
 892                            I915_READ(SDEIIR));
 893                 seq_printf(m, "South Display Interrupt mask:            %08x\n",
 894                            I915_READ(SDEIMR));
 895                 seq_printf(m, "Graphics Interrupt enable:               %08x\n",
 896                            I915_READ(GTIER));
 897                 seq_printf(m, "Graphics Interrupt identity:             %08x\n",
 898                            I915_READ(GTIIR));
 899                 seq_printf(m, "Graphics Interrupt mask:         %08x\n",
 900                            I915_READ(GTIMR));
 901         }
 902         for_each_engine(engine, dev_priv) {
 903                 if (INTEL_GEN(dev_priv) >= 6) {
 904                         seq_printf(m,
 905                                    "Graphics Interrupt mask (%s):       %08x\n",
 906                                    engine->name, I915_READ_IMR(engine));
 907                 }
 908                 i915_ring_seqno_info(m, engine);
 909         }
 910         intel_runtime_pm_put(dev_priv);
 911
 912         return 0;
 913 }
 914
 915 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
 916 {
 917         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 918         struct drm_device *dev = &dev_priv->drm;
 919         int i, ret;
 920
 921         ret = mutex_lock_interruptible(&dev->struct_mutex);
 922         if (ret)
 923                 return ret;
 924
 925         seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
 926         for (i = 0; i < dev_priv->num_fence_regs; i++) {
 927                 struct i915_vma *vma = dev_priv->fence_regs[i].vma;
 928
 929                 seq_printf(m, "Fence %d, pin count = %d, object = ",
 930                            i, dev_priv->fence_regs[i].pin_count);
 931                 if (!vma)
 932                         seq_puts(m, "unused");
 933                 else
 934                         describe_obj(m, vma->obj);
 935                 seq_putc(m, '\n');
 936         }
 937
 938         mutex_unlock(&dev->struct_mutex);
 939         return 0;
 940 }
 941
 942 static int i915_hws_info(struct seq_file *m, void *data)
 943 {
 944         struct drm_info_node *node = m->private;
 945         struct drm_i915_private *dev_priv = node_to_i915(node);
 946         struct intel_engine_cs *engine;
 947         const u32 *hws;
 948         int i;
 949
 950         engine = &dev_priv->engine[(uintptr_t)node->info_ent->data];
 951         hws = engine->status_page.page_addr;
 952         if (hws == NULL)
 953                 return 0;
 954
 955         for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
 956                 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
 957                            i * 4,
 958                            hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
 959         }
 960         return 0;
 961 }
 962
 963 static ssize_t
 964 i915_error_state_write(struct file *filp,
 965                        const char __user *ubuf,
 966                        size_t cnt,
 967                        loff_t *ppos)
 968 {
 969         struct i915_error_state_file_priv *error_priv = filp->private_data;
 970
 971         DRM_DEBUG_DRIVER("Resetting error state\n");
 972         i915_destroy_error_state(error_priv->dev);
 973
 974         return cnt;
 975 }
 976
 977 static int i915_error_state_open(struct inode *inode, struct file *file)
 978 {
 979         struct drm_i915_private *dev_priv = inode->i_private;
 980         struct i915_error_state_file_priv *error_priv;
 981
 982         error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
 983         if (!error_priv)
 984                 return -ENOMEM;
 985
 986         error_priv->dev = &dev_priv->drm;
 987
 988         i915_error_state_get(&dev_priv->drm, error_priv);
 989
 990         file->private_data = error_priv;
 991
 992         return 0;
 993 }
 994
 995 static int i915_error_state_release(struct inode *inode, struct file *file)
 996 {
 997         struct i915_error_state_file_priv *error_priv = file->private_data;
 998
 999         i915_error_state_put(error_priv);
1000         kfree(error_priv);
1001
1002         return 0;
1003 }
1004
1005 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1006                                      size_t count, loff_t *pos)
1007 {
1008         struct i915_error_state_file_priv *error_priv = file->private_data;
1009         struct drm_i915_error_state_buf error_str;
1010         loff_t tmp_pos = 0;
1011         ssize_t ret_count = 0;
1012         int ret;
1013
1014         ret = i915_error_state_buf_init(&error_str,
1015                                         to_i915(error_priv->dev), count, *pos);
1016         if (ret)
1017                 return ret;
1018
1019         ret = i915_error_state_to_str(&error_str, error_priv);
1020         if (ret)
1021                 goto out;
1022
1023         ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1024                                             error_str.buf,
1025                                             error_str.bytes);
1026
1027         if (ret_count < 0)
1028                 ret = ret_count;
1029         else
1030                 *pos = error_str.start + ret_count;
1031 out:
1032         i915_error_state_buf_release(&error_str);
1033         return ret ?: ret_count;
1034 }
1035
1036 static const struct file_operations i915_error_state_fops = {
1037         .owner = THIS_MODULE,
1038         .open = i915_error_state_open,
1039         .read = i915_error_state_read,
1040         .write = i915_error_state_write,
1041         .llseek = default_llseek,
1042         .release = i915_error_state_release,
1043 };
1044
1045 static int
1046 i915_next_seqno_get(void *data, u64 *val)
1047 {
1048         struct drm_i915_private *dev_priv = data;
1049         int ret;
1050
1051         ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
1052         if (ret)
1053                 return ret;
1054
1055         *val = dev_priv->next_seqno;
1056         mutex_unlock(&dev_priv->drm.struct_mutex);
1057
1058         return 0;
1059 }
1060
1061 static int
1062 i915_next_seqno_set(void *data, u64 val)
1063 {
1064         struct drm_i915_private *dev_priv = data;
1065         struct drm_device *dev = &dev_priv->drm;
1066         int ret;
1067
1068         ret = mutex_lock_interruptible(&dev->struct_mutex);
1069         if (ret)
1070                 return ret;
1071
1072         ret = i915_gem_set_seqno(dev, val);
1073         mutex_unlock(&dev->struct_mutex);
1074
1075         return ret;
1076 }
1077
1078 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1079                         i915_next_seqno_get, i915_next_seqno_set,
1080                         "0x%llx\n");
1081
1082 static int i915_frequency_info(struct seq_file *m, void *unused)
1083 {
1084         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1085         struct drm_device *dev = &dev_priv->drm;
1086         int ret = 0;
1087
1088         intel_runtime_pm_get(dev_priv);
1089
1090         if (IS_GEN5(dev_priv)) {
1091                 u16 rgvswctl = I915_READ16(MEMSWCTL);
1092                 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1093
1094                 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1095                 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1096                 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1097                            MEMSTAT_VID_SHIFT);
1098                 seq_printf(m, "Current P-state: %d\n",
1099                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1100         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1101                 u32 freq_sts;
1102
1103                 mutex_lock(&dev_priv->rps.hw_lock);
1104                 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1105                 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1106                 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1107
1108                 seq_printf(m, "actual GPU freq: %d MHz\n",
1109                            intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1110
1111                 seq_printf(m, "current GPU freq: %d MHz\n",
1112                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1113
1114                 seq_printf(m, "max GPU freq: %d MHz\n",
1115                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1116
1117                 seq_printf(m, "min GPU freq: %d MHz\n",
1118                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1119
1120                 seq_printf(m, "idle GPU freq: %d MHz\n",
1121                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1122
1123                 seq_printf(m,
1124                            "efficient (RPe) frequency: %d MHz\n",
1125                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1126                 mutex_unlock(&dev_priv->rps.hw_lock);
1127         } else if (INTEL_GEN(dev_priv) >= 6) {
1128                 u32 rp_state_limits;
1129                 u32 gt_perf_status;
1130                 u32 rp_state_cap;
1131                 u32 rpmodectl, rpinclimit, rpdeclimit;
1132                 u32 rpstat, cagf, reqf;
1133                 u32 rpupei, rpcurup, rpprevup;
1134                 u32 rpdownei, rpcurdown, rpprevdown;
1135                 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1136                 int max_freq;
1137
1138                 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1139                 if (IS_BROXTON(dev_priv)) {
1140                         rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1141                         gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1142                 } else {
1143                         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1144                         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1145                 }
1146
1147                 /* RPSTAT1 is in the GT power well */
1148                 ret = mutex_lock_interruptible(&dev->struct_mutex);
1149                 if (ret)
1150                         goto out;
1151
1152                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1153
1154                 reqf = I915_READ(GEN6_RPNSWREQ);
1155                 if (IS_GEN9(dev_priv))
1156                         reqf >>= 23;
1157                 else {
1158                         reqf &= ~GEN6_TURBO_DISABLE;
1159                         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1160                                 reqf >>= 24;
1161                         else
1162                                 reqf >>= 25;
1163                 }
1164                 reqf = intel_gpu_freq(dev_priv, reqf);
1165
1166                 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1167                 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1168                 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1169
1170                 rpstat = I915_READ(GEN6_RPSTAT1);
1171                 rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
1172                 rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
1173                 rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
1174                 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
1175                 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
1176                 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
1177                 if (IS_GEN9(dev_priv))
1178                         cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1179                 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1180                         cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1181                 else
1182                         cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1183                 cagf = intel_gpu_freq(dev_priv, cagf);
1184
1185                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1186                 mutex_unlock(&dev->struct_mutex);
1187
1188                 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
1189                         pm_ier = I915_READ(GEN6_PMIER);
1190                         pm_imr = I915_READ(GEN6_PMIMR);
1191                         pm_isr = I915_READ(GEN6_PMISR);
1192                         pm_iir = I915_READ(GEN6_PMIIR);
1193                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1194                 } else {
1195                         pm_ier = I915_READ(GEN8_GT_IER(2));
1196                         pm_imr = I915_READ(GEN8_GT_IMR(2));
1197                         pm_isr = I915_READ(GEN8_GT_ISR(2));
1198                         pm_iir = I915_READ(GEN8_GT_IIR(2));
1199                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1200                 }
1201                 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1202                            pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1203                 seq_printf(m, "pm_intr_keep: 0x%08x\n", dev_priv->rps.pm_intr_keep);
1204                 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1205                 seq_printf(m, "Render p-state ratio: %d\n",
1206                            (gt_perf_status & (IS_GEN9(dev_priv) ? 0x1ff00 : 0xff00)) >> 8);
1207                 seq_printf(m, "Render p-state VID: %d\n",
1208                            gt_perf_status & 0xff);
1209                 seq_printf(m, "Render p-state limit: %d\n",
1210                            rp_state_limits & 0xff);
1211                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1212                 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1213                 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1214                 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1215                 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1216                 seq_printf(m, "CAGF: %dMHz\n", cagf);
1217                 seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
1218                            rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei));
1219                 seq_printf(m, "RP CUR UP: %d (%dus)\n",
1220                            rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
1221                 seq_printf(m, "RP PREV UP: %d (%dus)\n",
1222                            rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
1223                 seq_printf(m, "Up threshold: %d%%\n",
1224                            dev_priv->rps.up_threshold);
1225
1226                 seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
1227                            rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
1228                 seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
1229                            rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown));
1230                 seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
1231                            rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown));
1232                 seq_printf(m, "Down threshold: %d%%\n",
1233                            dev_priv->rps.down_threshold);
1234
1235                 max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 0 :
1236                             rp_state_cap >> 16) & 0xff;
1237                 max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1238                              GEN9_FREQ_SCALER : 1);
1239                 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1240                            intel_gpu_freq(dev_priv, max_freq));
1241
1242                 max_freq = (rp_state_cap & 0xff00) >> 8;
1243                 max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1244                              GEN9_FREQ_SCALER : 1);
1245                 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1246                            intel_gpu_freq(dev_priv, max_freq));
1247
1248                 max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 16 :
1249                             rp_state_cap >> 0) & 0xff;
1250                 max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1251                              GEN9_FREQ_SCALER : 1);
1252                 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1253                            intel_gpu_freq(dev_priv, max_freq));
1254                 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1255                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1256
1257                 seq_printf(m, "Current freq: %d MHz\n",
1258                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1259                 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1260                 seq_printf(m, "Idle freq: %d MHz\n",
1261                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1262                 seq_printf(m, "Min freq: %d MHz\n",
1263                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1264                 seq_printf(m, "Boost freq: %d MHz\n",
1265                            intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
1266                 seq_printf(m, "Max freq: %d MHz\n",
1267                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1268                 seq_printf(m,
1269                            "efficient (RPe) frequency: %d MHz\n",
1270                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1271         } else {
1272                 seq_puts(m, "no P-state info available\n");
1273         }
1274
1275         seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
1276         seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1277         seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1278
1279 out:
1280         intel_runtime_pm_put(dev_priv);
1281         return ret;
1282 }
1283
1284 static void i915_instdone_info(struct drm_i915_private *dev_priv,
1285                                struct seq_file *m,
1286                                struct intel_instdone *instdone)
1287 {
1288         int slice;
1289         int subslice;
1290
1291         seq_printf(m, "\t\tINSTDONE: 0x%08x\n",
1292                    instdone->instdone);
1293
1294         if (INTEL_GEN(dev_priv) <= 3)
1295                 return;
1296
1297         seq_printf(m, "\t\tSC_INSTDONE: 0x%08x\n",
1298                    instdone->slice_common);
1299
1300         if (INTEL_GEN(dev_priv) <= 6)
1301                 return;
1302
1303         for_each_instdone_slice_subslice(dev_priv, slice, subslice)
1304                 seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
1305                            slice, subslice, instdone->sampler[slice][subslice]);
1306
1307         for_each_instdone_slice_subslice(dev_priv, slice, subslice)
1308                 seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n",
1309                            slice, subslice, instdone->row[slice][subslice]);
1310 }
1311
1312 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1313 {
1314         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1315         struct intel_engine_cs *engine;
1316         u64 acthd[I915_NUM_ENGINES];
1317         u32 seqno[I915_NUM_ENGINES];
1318         struct intel_instdone instdone;
1319         enum intel_engine_id id;
1320
1321         if (test_bit(I915_WEDGED, &dev_priv->gpu_error.flags))
1322                 seq_printf(m, "Wedged\n");
1323         if (test_bit(I915_RESET_IN_PROGRESS, &dev_priv->gpu_error.flags))
1324                 seq_printf(m, "Reset in progress\n");
1325         if (waitqueue_active(&dev_priv->gpu_error.wait_queue))
1326                 seq_printf(m, "Waiter holding struct mutex\n");
1327         if (waitqueue_active(&dev_priv->gpu_error.reset_queue))
1328                 seq_printf(m, "struct_mutex blocked for reset\n");
1329
1330         if (!i915.enable_hangcheck) {
1331                 seq_printf(m, "Hangcheck disabled\n");
1332                 return 0;
1333         }
1334
1335         intel_runtime_pm_get(dev_priv);
1336
1337         for_each_engine_id(engine, dev_priv, id) {
1338                 acthd[id] = intel_engine_get_active_head(engine);
1339                 seqno[id] = intel_engine_get_seqno(engine);
1340         }
1341
1342         intel_engine_get_instdone(&dev_priv->engine[RCS], &instdone);
1343
1344         intel_runtime_pm_put(dev_priv);
1345
1346         if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1347                 seq_printf(m, "Hangcheck active, fires in %dms\n",
1348                            jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1349                                             jiffies));
1350         } else
1351                 seq_printf(m, "Hangcheck inactive\n");
1352
1353         for_each_engine_id(engine, dev_priv, id) {
1354                 struct intel_breadcrumbs *b = &engine->breadcrumbs;
1355                 struct rb_node *rb;
1356
1357                 seq_printf(m, "%s:\n", engine->name);
1358                 seq_printf(m, "\tseqno = %x [current %x, last %x]\n",
1359                            engine->hangcheck.seqno,
1360                            seqno[id],
1361                            engine->last_submitted_seqno);
1362                 seq_printf(m, "\twaiters? %s, fake irq active? %s\n",
1363                            yesno(intel_engine_has_waiter(engine)),
1364                            yesno(test_bit(engine->id,
1365                                           &dev_priv->gpu_error.missed_irq_rings)));
1366                 spin_lock(&b->lock);
1367                 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
1368                         struct intel_wait *w = container_of(rb, typeof(*w), node);
1369
1370                         seq_printf(m, "\t%s [%d] waiting for %x\n",
1371                                    w->tsk->comm, w->tsk->pid, w->seqno);
1372                 }
1373                 spin_unlock(&b->lock);
1374
1375                 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1376                            (long long)engine->hangcheck.acthd,
1377                            (long long)acthd[id]);
1378                 seq_printf(m, "\tscore = %d\n", engine->hangcheck.score);
1379                 seq_printf(m, "\taction = %d\n", engine->hangcheck.action);
1380
1381                 if (engine->id == RCS) {
1382                         seq_puts(m, "\tinstdone read =\n");
1383
1384                         i915_instdone_info(dev_priv, m, &instdone);
1385
1386                         seq_puts(m, "\tinstdone accu =\n");
1387
1388                         i915_instdone_info(dev_priv, m,
1389                                            &engine->hangcheck.instdone);
1390                 }
1391         }
1392
1393         return 0;
1394 }
1395
1396 static int ironlake_drpc_info(struct seq_file *m)
1397 {
1398         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1399         struct drm_device *dev = &dev_priv->drm;
1400         u32 rgvmodectl, rstdbyctl;
1401         u16 crstandvid;
1402         int ret;
1403
1404         ret = mutex_lock_interruptible(&dev->struct_mutex);
1405         if (ret)
1406                 return ret;
1407         intel_runtime_pm_get(dev_priv);
1408
1409         rgvmodectl = I915_READ(MEMMODECTL);
1410         rstdbyctl = I915_READ(RSTDBYCTL);
1411         crstandvid = I915_READ16(CRSTANDVID);
1412
1413         intel_runtime_pm_put(dev_priv);
1414         mutex_unlock(&dev->struct_mutex);
1415
1416         seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1417         seq_printf(m, "Boost freq: %d\n",
1418                    (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1419                    MEMMODE_BOOST_FREQ_SHIFT);
1420         seq_printf(m, "HW control enabled: %s\n",
1421                    yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1422         seq_printf(m, "SW control enabled: %s\n",
1423                    yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1424         seq_printf(m, "Gated voltage change: %s\n",
1425                    yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1426         seq_printf(m, "Starting frequency: P%d\n",
1427                    (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1428         seq_printf(m, "Max P-state: P%d\n",
1429                    (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1430         seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1431         seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1432         seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1433         seq_printf(m, "Render standby enabled: %s\n",
1434                    yesno(!(rstdbyctl & RCX_SW_EXIT)));
1435         seq_puts(m, "Current RS state: ");
1436         switch (rstdbyctl & RSX_STATUS_MASK) {
1437         case RSX_STATUS_ON:
1438                 seq_puts(m, "on\n");
1439                 break;
1440         case RSX_STATUS_RC1:
1441                 seq_puts(m, "RC1\n");
1442                 break;
1443         case RSX_STATUS_RC1E:
1444                 seq_puts(m, "RC1E\n");
1445                 break;
1446         case RSX_STATUS_RS1:
1447                 seq_puts(m, "RS1\n");
1448                 break;
1449         case RSX_STATUS_RS2:
1450                 seq_puts(m, "RS2 (RC6)\n");
1451                 break;
1452         case RSX_STATUS_RS3:
1453                 seq_puts(m, "RC3 (RC6+)\n");
1454                 break;
1455         default:
1456                 seq_puts(m, "unknown\n");
1457                 break;
1458         }
1459
1460         return 0;
1461 }
1462
1463 static int i915_forcewake_domains(struct seq_file *m, void *data)
1464 {
1465         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1466         struct intel_uncore_forcewake_domain *fw_domain;
1467
1468         spin_lock_irq(&dev_priv->uncore.lock);
1469         for_each_fw_domain(fw_domain, dev_priv) {
1470                 seq_printf(m, "%s.wake_count = %u\n",
1471                            intel_uncore_forcewake_domain_to_str(fw_domain->id),
1472                            fw_domain->wake_count);
1473         }
1474         spin_unlock_irq(&dev_priv->uncore.lock);
1475
1476         return 0;
1477 }
1478
1479 static int vlv_drpc_info(struct seq_file *m)
1480 {
1481         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1482         u32 rpmodectl1, rcctl1, pw_status;
1483
1484         intel_runtime_pm_get(dev_priv);
1485
1486         pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1487         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1488         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1489
1490         intel_runtime_pm_put(dev_priv);
1491
1492         seq_printf(m, "Video Turbo Mode: %s\n",
1493                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1494         seq_printf(m, "Turbo enabled: %s\n",
1495                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1496         seq_printf(m, "HW control enabled: %s\n",
1497                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1498         seq_printf(m, "SW control enabled: %s\n",
1499                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1500                           GEN6_RP_MEDIA_SW_MODE));
1501         seq_printf(m, "RC6 Enabled: %s\n",
1502                    yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1503                                         GEN6_RC_CTL_EI_MODE(1))));
1504         seq_printf(m, "Render Power Well: %s\n",
1505                    (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1506         seq_printf(m, "Media Power Well: %s\n",
1507                    (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1508
1509         seq_printf(m, "Render RC6 residency since boot: %u\n",
1510                    I915_READ(VLV_GT_RENDER_RC6));
1511         seq_printf(m, "Media RC6 residency since boot: %u\n",
1512                    I915_READ(VLV_GT_MEDIA_RC6));
1513
1514         return i915_forcewake_domains(m, NULL);
1515 }
1516
1517 static int gen6_drpc_info(struct seq_file *m)
1518 {
1519         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1520         struct drm_device *dev = &dev_priv->drm;
1521         u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1522         u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
1523         unsigned forcewake_count;
1524         int count = 0, ret;
1525
1526         ret = mutex_lock_interruptible(&dev->struct_mutex);
1527         if (ret)
1528                 return ret;
1529         intel_runtime_pm_get(dev_priv);
1530
1531         spin_lock_irq(&dev_priv->uncore.lock);
1532         forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1533         spin_unlock_irq(&dev_priv->uncore.lock);
1534
1535         if (forcewake_count) {
1536                 seq_puts(m, "RC information inaccurate because somebody "
1537                             "holds a forcewake reference \n");
1538         } else {
1539                 /* NB: we cannot use forcewake, else we read the wrong values */
1540                 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1541                         udelay(10);
1542                 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1543         }
1544
1545         gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1546         trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1547
1548         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1549         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1550         if (INTEL_GEN(dev_priv) >= 9) {
1551                 gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE);
1552                 gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
1553         }
1554         mutex_unlock(&dev->struct_mutex);
1555         mutex_lock(&dev_priv->rps.hw_lock);
1556         sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1557         mutex_unlock(&dev_priv->rps.hw_lock);
1558
1559         intel_runtime_pm_put(dev_priv);
1560
1561         seq_printf(m, "Video Turbo Mode: %s\n",
1562                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1563         seq_printf(m, "HW control enabled: %s\n",
1564                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1565         seq_printf(m, "SW control enabled: %s\n",
1566                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1567                           GEN6_RP_MEDIA_SW_MODE));
1568         seq_printf(m, "RC1e Enabled: %s\n",
1569                    yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1570         seq_printf(m, "RC6 Enabled: %s\n",
1571                    yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1572         if (INTEL_GEN(dev_priv) >= 9) {
1573                 seq_printf(m, "Render Well Gating Enabled: %s\n",
1574                         yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
1575                 seq_printf(m, "Media Well Gating Enabled: %s\n",
1576                         yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE));
1577         }
1578         seq_printf(m, "Deep RC6 Enabled: %s\n",
1579                    yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1580         seq_printf(m, "Deepest RC6 Enabled: %s\n",
1581                    yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1582         seq_puts(m, "Current RC state: ");
1583         switch (gt_core_status & GEN6_RCn_MASK) {
1584         case GEN6_RC0:
1585                 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1586                         seq_puts(m, "Core Power Down\n");
1587                 else
1588                         seq_puts(m, "on\n");
1589                 break;
1590         case GEN6_RC3:
1591                 seq_puts(m, "RC3\n");
1592                 break;
1593         case GEN6_RC6:
1594                 seq_puts(m, "RC6\n");
1595                 break;
1596         case GEN6_RC7:
1597                 seq_puts(m, "RC7\n");
1598                 break;
1599         default:
1600                 seq_puts(m, "Unknown\n");
1601                 break;
1602         }
1603
1604         seq_printf(m, "Core Power Down: %s\n",
1605                    yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1606         if (INTEL_GEN(dev_priv) >= 9) {
1607                 seq_printf(m, "Render Power Well: %s\n",
1608                         (gen9_powergate_status &
1609                          GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
1610                 seq_printf(m, "Media Power Well: %s\n",
1611                         (gen9_powergate_status &
1612                          GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
1613         }
1614
1615         /* Not exactly sure what this is */
1616         seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1617                    I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1618         seq_printf(m, "RC6 residency since boot: %u\n",
1619                    I915_READ(GEN6_GT_GFX_RC6));
1620         seq_printf(m, "RC6+ residency since boot: %u\n",
1621                    I915_READ(GEN6_GT_GFX_RC6p));
1622         seq_printf(m, "RC6++ residency since boot: %u\n",
1623                    I915_READ(GEN6_GT_GFX_RC6pp));
1624
1625         seq_printf(m, "RC6   voltage: %dmV\n",
1626                    GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1627         seq_printf(m, "RC6+  voltage: %dmV\n",
1628                    GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1629         seq_printf(m, "RC6++ voltage: %dmV\n",
1630                    GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1631         return i915_forcewake_domains(m, NULL);
1632 }
1633
1634 static int i915_drpc_info(struct seq_file *m, void *unused)
1635 {
1636         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1637
1638         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1639                 return vlv_drpc_info(m);
1640         else if (INTEL_GEN(dev_priv) >= 6)
1641                 return gen6_drpc_info(m);
1642         else
1643                 return ironlake_drpc_info(m);
1644 }
1645
1646 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1647 {
1648         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1649
1650         seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1651                    dev_priv->fb_tracking.busy_bits);
1652
1653         seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1654                    dev_priv->fb_tracking.flip_bits);
1655
1656         return 0;
1657 }
1658
1659 static int i915_fbc_status(struct seq_file *m, void *unused)
1660 {
1661         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1662
1663         if (!HAS_FBC(dev_priv)) {
1664                 seq_puts(m, "FBC unsupported on this chipset\n");
1665                 return 0;
1666         }
1667
1668         intel_runtime_pm_get(dev_priv);
1669         mutex_lock(&dev_priv->fbc.lock);
1670
1671         if (intel_fbc_is_active(dev_priv))
1672                 seq_puts(m, "FBC enabled\n");
1673         else
1674                 seq_printf(m, "FBC disabled: %s\n",
1675                            dev_priv->fbc.no_fbc_reason);
1676
1677         if (intel_fbc_is_active(dev_priv) &&
1678             INTEL_GEN(dev_priv) >= 7)
1679                 seq_printf(m, "Compressing: %s\n",
1680                            yesno(I915_READ(FBC_STATUS2) &
1681                                  FBC_COMPRESSION_MASK));
1682
1683         mutex_unlock(&dev_priv->fbc.lock);
1684         intel_runtime_pm_put(dev_priv);
1685
1686         return 0;
1687 }
1688
1689 static int i915_fbc_fc_get(void *data, u64 *val)
1690 {
1691         struct drm_i915_private *dev_priv = data;
1692
1693         if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1694                 return -ENODEV;
1695
1696         *val = dev_priv->fbc.false_color;
1697
1698         return 0;
1699 }
1700
1701 static int i915_fbc_fc_set(void *data, u64 val)
1702 {
1703         struct drm_i915_private *dev_priv = data;
1704         u32 reg;
1705
1706         if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1707                 return -ENODEV;
1708
1709         mutex_lock(&dev_priv->fbc.lock);
1710
1711         reg = I915_READ(ILK_DPFC_CONTROL);
1712         dev_priv->fbc.false_color = val;
1713
1714         I915_WRITE(ILK_DPFC_CONTROL, val ?
1715                    (reg | FBC_CTL_FALSE_COLOR) :
1716                    (reg & ~FBC_CTL_FALSE_COLOR));
1717
1718         mutex_unlock(&dev_priv->fbc.lock);
1719         return 0;
1720 }
1721
1722 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1723                         i915_fbc_fc_get, i915_fbc_fc_set,
1724                         "%llu\n");
1725
1726 static int i915_ips_status(struct seq_file *m, void *unused)
1727 {
1728         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1729
1730         if (!HAS_IPS(dev_priv)) {
1731                 seq_puts(m, "not supported\n");
1732                 return 0;
1733         }
1734
1735         intel_runtime_pm_get(dev_priv);
1736
1737         seq_printf(m, "Enabled by kernel parameter: %s\n",
1738                    yesno(i915.enable_ips));
1739
1740         if (INTEL_GEN(dev_priv) >= 8) {
1741                 seq_puts(m, "Currently: unknown\n");
1742         } else {
1743                 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1744                         seq_puts(m, "Currently: enabled\n");
1745                 else
1746                         seq_puts(m, "Currently: disabled\n");
1747         }
1748
1749         intel_runtime_pm_put(dev_priv);
1750
1751         return 0;
1752 }
1753
1754 static int i915_sr_status(struct seq_file *m, void *unused)
1755 {
1756         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1757         bool sr_enabled = false;
1758
1759         intel_runtime_pm_get(dev_priv);
1760
1761         if (HAS_PCH_SPLIT(dev_priv))
1762                 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1763         else if (IS_CRESTLINE(dev_priv) || IS_G4X(dev_priv) ||
1764                  IS_I945G(dev_priv) || IS_I945GM(dev_priv))
1765                 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1766         else if (IS_I915GM(dev_priv))
1767                 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1768         else if (IS_PINEVIEW(dev_priv))
1769                 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1770         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1771                 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1772
1773         intel_runtime_pm_put(dev_priv);
1774
1775         seq_printf(m, "self-refresh: %s\n",
1776                    sr_enabled ? "enabled" : "disabled");
1777
1778         return 0;
1779 }
1780
1781 static int i915_emon_status(struct seq_file *m, void *unused)
1782 {
1783         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1784         struct drm_device *dev = &dev_priv->drm;
1785         unsigned long temp, chipset, gfx;
1786         int ret;
1787
1788         if (!IS_GEN5(dev_priv))
1789                 return -ENODEV;
1790
1791         ret = mutex_lock_interruptible(&dev->struct_mutex);
1792         if (ret)
1793                 return ret;
1794
1795         temp = i915_mch_val(dev_priv);
1796         chipset = i915_chipset_val(dev_priv);
1797         gfx = i915_gfx_val(dev_priv);
1798         mutex_unlock(&dev->struct_mutex);
1799
1800         seq_printf(m, "GMCH temp: %ld\n", temp);
1801         seq_printf(m, "Chipset power: %ld\n", chipset);
1802         seq_printf(m, "GFX power: %ld\n", gfx);
1803         seq_printf(m, "Total power: %ld\n", chipset + gfx);
1804
1805         return 0;
1806 }
1807
1808 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1809 {
1810         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1811         int ret = 0;
1812         int gpu_freq, ia_freq;
1813         unsigned int max_gpu_freq, min_gpu_freq;
1814
1815         if (!HAS_LLC(dev_priv)) {
1816                 seq_puts(m, "unsupported on this chipset\n");
1817                 return 0;
1818         }
1819
1820         intel_runtime_pm_get(dev_priv);
1821
1822         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1823         if (ret)
1824                 goto out;
1825
1826         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
1827                 /* Convert GT frequency to 50 HZ units */
1828                 min_gpu_freq =
1829                         dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1830                 max_gpu_freq =
1831                         dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1832         } else {
1833                 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1834                 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1835         }
1836
1837         seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1838
1839         for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1840                 ia_freq = gpu_freq;
1841                 sandybridge_pcode_read(dev_priv,
1842                                        GEN6_PCODE_READ_MIN_FREQ_TABLE,
1843                                        &ia_freq);
1844                 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1845                            intel_gpu_freq(dev_priv, (gpu_freq *
1846                                 (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1847                                  GEN9_FREQ_SCALER : 1))),
1848                            ((ia_freq >> 0) & 0xff) * 100,
1849                            ((ia_freq >> 8) & 0xff) * 100);
1850         }
1851
1852         mutex_unlock(&dev_priv->rps.hw_lock);
1853
1854 out:
1855         intel_runtime_pm_put(dev_priv);
1856         return ret;
1857 }
1858
1859 static int i915_opregion(struct seq_file *m, void *unused)
1860 {
1861         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1862         struct drm_device *dev = &dev_priv->drm;
1863         struct intel_opregion *opregion = &dev_priv->opregion;
1864         int ret;
1865
1866         ret = mutex_lock_interruptible(&dev->struct_mutex);
1867         if (ret)
1868                 goto out;
1869
1870         if (opregion->header)
1871                 seq_write(m, opregion->header, OPREGION_SIZE);
1872
1873         mutex_unlock(&dev->struct_mutex);
1874
1875 out:
1876         return 0;
1877 }
1878
1879 static int i915_vbt(struct seq_file *m, void *unused)
1880 {
1881         struct intel_opregion *opregion = &node_to_i915(m->private)->opregion;
1882
1883         if (opregion->vbt)
1884                 seq_write(m, opregion->vbt, opregion->vbt_size);
1885
1886         return 0;
1887 }
1888
1889 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1890 {
1891         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1892         struct drm_device *dev = &dev_priv->drm;
1893         struct intel_framebuffer *fbdev_fb = NULL;
1894         struct drm_framebuffer *drm_fb;
1895         int ret;
1896
1897         ret = mutex_lock_interruptible(&dev->struct_mutex);
1898         if (ret)
1899                 return ret;
1900
1901 #ifdef CONFIG_DRM_FBDEV_EMULATION
1902         if (dev_priv->fbdev) {
1903                 fbdev_fb = to_intel_framebuffer(dev_priv->fbdev->helper.fb);
1904
1905                 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1906                            fbdev_fb->base.width,
1907                            fbdev_fb->base.height,
1908                            fbdev_fb->base.depth,
1909                            fbdev_fb->base.bits_per_pixel,
1910                            fbdev_fb->base.modifier[0],
1911                            drm_framebuffer_read_refcount(&fbdev_fb->base));
1912                 describe_obj(m, fbdev_fb->obj);
1913                 seq_putc(m, '\n');
1914         }
1915 #endif
1916
1917         mutex_lock(&dev->mode_config.fb_lock);
1918         drm_for_each_fb(drm_fb, dev) {
1919                 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
1920                 if (fb == fbdev_fb)
1921                         continue;
1922
1923                 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1924                            fb->base.width,
1925                            fb->base.height,
1926                            fb->base.depth,
1927                            fb->base.bits_per_pixel,
1928                            fb->base.modifier[0],
1929                            drm_framebuffer_read_refcount(&fb->base));
1930                 describe_obj(m, fb->obj);
1931                 seq_putc(m, '\n');
1932         }
1933         mutex_unlock(&dev->mode_config.fb_lock);
1934         mutex_unlock(&dev->struct_mutex);
1935
1936         return 0;
1937 }
1938
1939 static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring)
1940 {
1941         seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1942                    ring->space, ring->head, ring->tail,
1943                    ring->last_retired_head);
1944 }
1945
1946 static int i915_context_status(struct seq_file *m, void *unused)
1947 {
1948         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1949         struct drm_device *dev = &dev_priv->drm;
1950         struct intel_engine_cs *engine;
1951         struct i915_gem_context *ctx;
1952         int ret;
1953
1954         ret = mutex_lock_interruptible(&dev->struct_mutex);
1955         if (ret)
1956                 return ret;
1957
1958         list_for_each_entry(ctx, &dev_priv->context_list, link) {
1959                 seq_printf(m, "HW context %u ", ctx->hw_id);
1960                 if (ctx->pid) {
1961                         struct task_struct *task;
1962
1963                         task = get_pid_task(ctx->pid, PIDTYPE_PID);
1964                         if (task) {
1965                                 seq_printf(m, "(%s [%d]) ",
1966                                            task->comm, task->pid);
1967                                 put_task_struct(task);
1968                         }
1969                 } else if (IS_ERR(ctx->file_priv)) {
1970                         seq_puts(m, "(deleted) ");
1971                 } else {
1972                         seq_puts(m, "(kernel) ");
1973                 }
1974
1975                 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
1976                 seq_putc(m, '\n');
1977
1978                 for_each_engine(engine, dev_priv) {
1979                         struct intel_context *ce = &ctx->engine[engine->id];
1980
1981                         seq_printf(m, "%s: ", engine->name);
1982                         seq_putc(m, ce->initialised ? 'I' : 'i');
1983                         if (ce->state)
1984                                 describe_obj(m, ce->state->obj);
1985                         if (ce->ring)
1986                                 describe_ctx_ring(m, ce->ring);
1987                         seq_putc(m, '\n');
1988                 }
1989
1990                 seq_putc(m, '\n');
1991         }
1992
1993         mutex_unlock(&dev->struct_mutex);
1994
1995         return 0;
1996 }
1997
1998 static void i915_dump_lrc_obj(struct seq_file *m,
1999                               struct i915_gem_context *ctx,
2000                               struct intel_engine_cs *engine)
2001 {
2002         struct i915_vma *vma = ctx->engine[engine->id].state;
2003         struct page *page;
2004         int j;
2005
2006         seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id);
2007
2008         if (!vma) {
2009                 seq_puts(m, "\tFake context\n");
2010                 return;
2011         }
2012
2013         if (vma->flags & I915_VMA_GLOBAL_BIND)
2014                 seq_printf(m, "\tBound in GGTT at 0x%08x\n",
2015                            i915_ggtt_offset(vma));
2016
2017         if (i915_gem_object_get_pages(vma->obj)) {
2018                 seq_puts(m, "\tFailed to get pages for context object\n\n");
2019                 return;
2020         }
2021
2022         page = i915_gem_object_get_page(vma->obj, LRC_STATE_PN);
2023         if (page) {
2024                 u32 *reg_state = kmap_atomic(page);
2025
2026                 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2027                         seq_printf(m,
2028                                    "\t[0x%04x] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2029                                    j * 4,
2030                                    reg_state[j], reg_state[j + 1],
2031                                    reg_state[j + 2], reg_state[j + 3]);
2032                 }
2033                 kunmap_atomic(reg_state);
2034         }
2035
2036         seq_putc(m, '\n');
2037 }
2038
2039 static int i915_dump_lrc(struct seq_file *m, void *unused)
2040 {
2041         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2042         struct drm_device *dev = &dev_priv->drm;
2043         struct intel_engine_cs *engine;
2044         struct i915_gem_context *ctx;
2045         int ret;
2046
2047         if (!i915.enable_execlists) {
2048                 seq_printf(m, "Logical Ring Contexts are disabled\n");
2049                 return 0;
2050         }
2051
2052         ret = mutex_lock_interruptible(&dev->struct_mutex);
2053         if (ret)
2054                 return ret;
2055
2056         list_for_each_entry(ctx, &dev_priv->context_list, link)
2057                 for_each_engine(engine, dev_priv)
2058                         i915_dump_lrc_obj(m, ctx, engine);
2059
2060         mutex_unlock(&dev->struct_mutex);
2061
2062         return 0;
2063 }
2064
2065 static const char *swizzle_string(unsigned swizzle)
2066 {
2067         switch (swizzle) {
2068         case I915_BIT_6_SWIZZLE_NONE:
2069                 return "none";
2070         case I915_BIT_6_SWIZZLE_9:
2071                 return "bit9";
2072         case I915_BIT_6_SWIZZLE_9_10:
2073                 return "bit9/bit10";
2074         case I915_BIT_6_SWIZZLE_9_11:
2075                 return "bit9/bit11";
2076         case I915_BIT_6_SWIZZLE_9_10_11:
2077                 return "bit9/bit10/bit11";
2078         case I915_BIT_6_SWIZZLE_9_17:
2079                 return "bit9/bit17";
2080         case I915_BIT_6_SWIZZLE_9_10_17:
2081                 return "bit9/bit10/bit17";
2082         case I915_BIT_6_SWIZZLE_UNKNOWN:
2083                 return "unknown";
2084         }
2085
2086         return "bug";
2087 }
2088
2089 static int i915_swizzle_info(struct seq_file *m, void *data)
2090 {
2091         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2092         struct drm_device *dev = &dev_priv->drm;
2093         int ret;
2094
2095         ret = mutex_lock_interruptible(&dev->struct_mutex);
2096         if (ret)
2097                 return ret;
2098         intel_runtime_pm_get(dev_priv);
2099
2100         seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2101                    swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2102         seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2103                    swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2104
2105         if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) {
2106                 seq_printf(m, "DDC = 0x%08x\n",
2107                            I915_READ(DCC));
2108                 seq_printf(m, "DDC2 = 0x%08x\n",
2109                            I915_READ(DCC2));
2110                 seq_printf(m, "C0DRB3 = 0x%04x\n",
2111                            I915_READ16(C0DRB3));
2112                 seq_printf(m, "C1DRB3 = 0x%04x\n",
2113                            I915_READ16(C1DRB3));
2114         } else if (INTEL_GEN(dev_priv) >= 6) {
2115                 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2116                            I915_READ(MAD_DIMM_C0));
2117                 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2118                            I915_READ(MAD_DIMM_C1));
2119                 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2120                            I915_READ(MAD_DIMM_C2));
2121                 seq_printf(m, "TILECTL = 0x%08x\n",
2122                            I915_READ(TILECTL));
2123                 if (INTEL_GEN(dev_priv) >= 8)
2124                         seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2125                                    I915_READ(GAMTARBMODE));
2126                 else
2127                         seq_printf(m, "ARB_MODE = 0x%08x\n",
2128                                    I915_READ(ARB_MODE));
2129                 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2130                            I915_READ(DISP_ARB_CTL));
2131         }
2132
2133         if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2134                 seq_puts(m, "L-shaped memory detected\n");
2135
2136         intel_runtime_pm_put(dev_priv);
2137         mutex_unlock(&dev->struct_mutex);
2138
2139         return 0;
2140 }
2141
2142 static int per_file_ctx(int id, void *ptr, void *data)
2143 {
2144         struct i915_gem_context *ctx = ptr;
2145         struct seq_file *m = data;
2146         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2147
2148         if (!ppgtt) {
2149                 seq_printf(m, "  no ppgtt for context %d\n",
2150                            ctx->user_handle);
2151                 return 0;
2152         }
2153
2154         if (i915_gem_context_is_default(ctx))
2155                 seq_puts(m, "  default context:\n");
2156         else
2157                 seq_printf(m, "  context %d:\n", ctx->user_handle);
2158         ppgtt->debug_dump(ppgtt, m);
2159
2160         return 0;
2161 }
2162
2163 static void gen8_ppgtt_info(struct seq_file *m,
2164                             struct drm_i915_private *dev_priv)
2165 {
2166         struct intel_engine_cs *engine;
2167         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2168         int i;
2169
2170         if (!ppgtt)
2171                 return;
2172
2173         for_each_engine(engine, dev_priv) {
2174                 seq_printf(m, "%s\n", engine->name);
2175                 for (i = 0; i < 4; i++) {
2176                         u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
2177                         pdp <<= 32;
2178                         pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
2179                         seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2180                 }
2181         }
2182 }
2183
2184 static void gen6_ppgtt_info(struct seq_file *m,
2185                             struct drm_i915_private *dev_priv)
2186 {
2187         struct intel_engine_cs *engine;
2188
2189         if (IS_GEN6(dev_priv))
2190                 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2191
2192         for_each_engine(engine, dev_priv) {
2193                 seq_printf(m, "%s\n", engine->name);
2194                 if (IS_GEN7(dev_priv))
2195                         seq_printf(m, "GFX_MODE: 0x%08x\n",
2196                                    I915_READ(RING_MODE_GEN7(engine)));
2197                 seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
2198                            I915_READ(RING_PP_DIR_BASE(engine)));
2199                 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
2200                            I915_READ(RING_PP_DIR_BASE_READ(engine)));
2201                 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
2202                            I915_READ(RING_PP_DIR_DCLV(engine)));
2203         }
2204         if (dev_priv->mm.aliasing_ppgtt) {
2205                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2206
2207                 seq_puts(m, "aliasing PPGTT:\n");
2208                 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2209
2210                 ppgtt->debug_dump(ppgtt, m);
2211         }
2212
2213         seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2214 }
2215
2216 static int i915_ppgtt_info(struct seq_file *m, void *data)
2217 {
2218         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2219         struct drm_device *dev = &dev_priv->drm;
2220         struct drm_file *file;
2221         int ret;
2222
2223         mutex_lock(&dev->filelist_mutex);
2224         ret = mutex_lock_interruptible(&dev->struct_mutex);
2225         if (ret)
2226                 goto out_unlock;
2227
2228         intel_runtime_pm_get(dev_priv);
2229
2230         if (INTEL_GEN(dev_priv) >= 8)
2231                 gen8_ppgtt_info(m, dev_priv);
2232         else if (INTEL_GEN(dev_priv) >= 6)
2233                 gen6_ppgtt_info(m, dev_priv);
2234
2235         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2236                 struct drm_i915_file_private *file_priv = file->driver_priv;
2237                 struct task_struct *task;
2238
2239                 task = get_pid_task(file->pid, PIDTYPE_PID);
2240                 if (!task) {
2241                         ret = -ESRCH;
2242                         goto out_rpm;
2243                 }
2244                 seq_printf(m, "\nproc: %s\n", task->comm);
2245                 put_task_struct(task);
2246                 idr_for_each(&file_priv->context_idr, per_file_ctx,
2247                              (void *)(unsigned long)m);
2248         }
2249
2250 out_rpm:
2251         intel_runtime_pm_put(dev_priv);
2252         mutex_unlock(&dev->struct_mutex);
2253 out_unlock:
2254         mutex_unlock(&dev->filelist_mutex);
2255         return ret;
2256 }
2257
2258 static int count_irq_waiters(struct drm_i915_private *i915)
2259 {
2260         struct intel_engine_cs *engine;
2261         int count = 0;
2262
2263         for_each_engine(engine, i915)
2264                 count += intel_engine_has_waiter(engine);
2265
2266         return count;
2267 }
2268
2269 static const char *rps_power_to_str(unsigned int power)
2270 {
2271         static const char * const strings[] = {
2272                 [LOW_POWER] = "low power",
2273                 [BETWEEN] = "mixed",
2274                 [HIGH_POWER] = "high power",
2275         };
2276
2277         if (power >= ARRAY_SIZE(strings) || !strings[power])
2278                 return "unknown";
2279
2280         return strings[power];
2281 }
2282
2283 static int i915_rps_boost_info(struct seq_file *m, void *data)
2284 {
2285         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2286         struct drm_device *dev = &dev_priv->drm;
2287         struct drm_file *file;
2288
2289         seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2290         seq_printf(m, "GPU busy? %s [%x]\n",
2291                    yesno(dev_priv->gt.awake), dev_priv->gt.active_engines);
2292         seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2293         seq_printf(m, "Frequency requested %d\n",
2294                    intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
2295         seq_printf(m, "  min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2296                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2297                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2298                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2299                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2300         seq_printf(m, "  idle:%d, efficient:%d, boost:%d\n",
2301                    intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
2302                    intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2303                    intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
2304
2305         mutex_lock(&dev->filelist_mutex);
2306         spin_lock(&dev_priv->rps.client_lock);
2307         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2308                 struct drm_i915_file_private *file_priv = file->driver_priv;
2309                 struct task_struct *task;
2310
2311                 rcu_read_lock();
2312                 task = pid_task(file->pid, PIDTYPE_PID);
2313                 seq_printf(m, "%s [%d]: %d boosts%s\n",
2314                            task ? task->comm : "<unknown>",
2315                            task ? task->pid : -1,
2316                            file_priv->rps.boosts,
2317                            list_empty(&file_priv->rps.link) ? "" : ", active");
2318                 rcu_read_unlock();
2319         }
2320         seq_printf(m, "Kernel (anonymous) boosts: %d\n", dev_priv->rps.boosts);
2321         spin_unlock(&dev_priv->rps.client_lock);
2322         mutex_unlock(&dev->filelist_mutex);
2323
2324         if (INTEL_GEN(dev_priv) >= 6 &&
2325             dev_priv->rps.enabled &&
2326             dev_priv->gt.active_engines) {
2327                 u32 rpup, rpupei;
2328                 u32 rpdown, rpdownei;
2329
2330                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2331                 rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK;
2332                 rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK;
2333                 rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK;
2334                 rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK;
2335                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2336
2337                 seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n",
2338                            rps_power_to_str(dev_priv->rps.power));
2339                 seq_printf(m, "  Avg. up: %d%% [above threshold? %d%%]\n",
2340                            100 * rpup / rpupei,
2341                            dev_priv->rps.up_threshold);
2342                 seq_printf(m, "  Avg. down: %d%% [below threshold? %d%%]\n",
2343                            100 * rpdown / rpdownei,
2344                            dev_priv->rps.down_threshold);
2345         } else {
2346                 seq_puts(m, "\nRPS Autotuning inactive\n");
2347         }
2348
2349         return 0;
2350 }
2351
2352 static int i915_llc(struct seq_file *m, void *data)
2353 {
2354         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2355         const bool edram = INTEL_GEN(dev_priv) > 8;
2356
2357         seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv)));
2358         seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
2359                    intel_uncore_edram_size(dev_priv)/1024/1024);
2360
2361         return 0;
2362 }
2363
2364 static int i915_guc_load_status_info(struct seq_file *m, void *data)
2365 {
2366         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2367         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
2368         u32 tmp, i;
2369
2370         if (!HAS_GUC_UCODE(dev_priv))
2371                 return 0;
2372
2373         seq_printf(m, "GuC firmware status:\n");
2374         seq_printf(m, "\tpath: %s\n",
2375                 guc_fw->guc_fw_path);
2376         seq_printf(m, "\tfetch: %s\n",
2377                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
2378         seq_printf(m, "\tload: %s\n",
2379                 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
2380         seq_printf(m, "\tversion wanted: %d.%d\n",
2381                 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2382         seq_printf(m, "\tversion found: %d.%d\n",
2383                 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
2384         seq_printf(m, "\theader: offset is %d; size = %d\n",
2385                 guc_fw->header_offset, guc_fw->header_size);
2386         seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2387                 guc_fw->ucode_offset, guc_fw->ucode_size);
2388         seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2389                 guc_fw->rsa_offset, guc_fw->rsa_size);
2390
2391         tmp = I915_READ(GUC_STATUS);
2392
2393         seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2394         seq_printf(m, "\tBootrom status = 0x%x\n",
2395                 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2396         seq_printf(m, "\tuKernel status = 0x%x\n",
2397                 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2398         seq_printf(m, "\tMIA Core status = 0x%x\n",
2399                 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2400         seq_puts(m, "\nScratch registers:\n");
2401         for (i = 0; i < 16; i++)
2402                 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2403
2404         return 0;
2405 }
2406
2407 static void i915_guc_client_info(struct seq_file *m,
2408                                  struct drm_i915_private *dev_priv,
2409                                  struct i915_guc_client *client)
2410 {
2411         struct intel_engine_cs *engine;
2412         enum intel_engine_id id;
2413         uint64_t tot = 0;
2414
2415         seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2416                 client->priority, client->ctx_index, client->proc_desc_offset);
2417         seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2418                 client->doorbell_id, client->doorbell_offset, client->cookie);
2419         seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2420                 client->wq_size, client->wq_offset, client->wq_tail);
2421
2422         seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space);
2423         seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2424         seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2425
2426         for_each_engine_id(engine, dev_priv, id) {
2427                 u64 submissions = client->submissions[id];
2428                 tot += submissions;
2429                 seq_printf(m, "\tSubmissions: %llu %s\n",
2430                                 submissions, engine->name);
2431         }
2432         seq_printf(m, "\tTotal: %llu\n", tot);
2433 }
2434
2435 static int i915_guc_info(struct seq_file *m, void *data)
2436 {
2437         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2438         struct drm_device *dev = &dev_priv->drm;
2439         struct intel_guc guc;
2440         struct i915_guc_client client = {};
2441         struct intel_engine_cs *engine;
2442         enum intel_engine_id id;
2443         u64 total = 0;
2444
2445         if (!HAS_GUC_SCHED(dev_priv))
2446                 return 0;
2447
2448         if (mutex_lock_interruptible(&dev->struct_mutex))
2449                 return 0;
2450
2451         /* Take a local copy of the GuC data, so we can dump it at leisure */
2452         guc = dev_priv->guc;
2453         if (guc.execbuf_client)
2454                 client = *guc.execbuf_client;
2455
2456         mutex_unlock(&dev->struct_mutex);
2457
2458         seq_printf(m, "Doorbell map:\n");
2459         seq_printf(m, "\t%*pb\n", GUC_MAX_DOORBELLS, guc.doorbell_bitmap);
2460         seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc.db_cacheline);
2461
2462         seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
2463         seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
2464         seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
2465         seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
2466         seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
2467
2468         seq_printf(m, "\nGuC submissions:\n");
2469         for_each_engine_id(engine, dev_priv, id) {
2470                 u64 submissions = guc.submissions[id];
2471                 total += submissions;
2472                 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",
2473                         engine->name, submissions, guc.last_seqno[id]);
2474         }
2475         seq_printf(m, "\t%s: %llu\n", "Total", total);
2476
2477         seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
2478         i915_guc_client_info(m, dev_priv, &client);
2479
2480         /* Add more as required ... */
2481
2482         return 0;
2483 }
2484
2485 static int i915_guc_log_dump(struct seq_file *m, void *data)
2486 {
2487         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2488         struct drm_i915_gem_object *obj;
2489         int i = 0, pg;
2490
2491         if (!dev_priv->guc.log_vma)
2492                 return 0;
2493
2494         obj = dev_priv->guc.log_vma->obj;
2495         for (pg = 0; pg < obj->base.size / PAGE_SIZE; pg++) {
2496                 u32 *log = kmap_atomic(i915_gem_object_get_page(obj, pg));
2497
2498                 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2499                         seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2500                                    *(log + i), *(log + i + 1),
2501                                    *(log + i + 2), *(log + i + 3));
2502
2503                 kunmap_atomic(log);
2504         }
2505
2506         seq_putc(m, '\n');
2507
2508         return 0;
2509 }
2510
2511 static int i915_edp_psr_status(struct seq_file *m, void *data)
2512 {
2513         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2514         u32 psrperf = 0;
2515         u32 stat[3];
2516         enum pipe pipe;
2517         bool enabled = false;
2518
2519         if (!HAS_PSR(dev_priv)) {
2520                 seq_puts(m, "PSR not supported\n");
2521                 return 0;
2522         }
2523
2524         intel_runtime_pm_get(dev_priv);
2525
2526         mutex_lock(&dev_priv->psr.lock);
2527         seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2528         seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2529         seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2530         seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2531         seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2532                    dev_priv->psr.busy_frontbuffer_bits);
2533         seq_printf(m, "Re-enable work scheduled: %s\n",
2534                    yesno(work_busy(&dev_priv->psr.work.work)));
2535
2536         if (HAS_DDI(dev_priv))
2537                 enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2538         else {
2539                 for_each_pipe(dev_priv, pipe) {
2540                         stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2541                                 VLV_EDP_PSR_CURR_STATE_MASK;
2542                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2543                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2544                                 enabled = true;
2545                 }
2546         }
2547
2548         seq_printf(m, "Main link in standby mode: %s\n",
2549                    yesno(dev_priv->psr.link_standby));
2550
2551         seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2552
2553         if (!HAS_DDI(dev_priv))
2554                 for_each_pipe(dev_priv, pipe) {
2555                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2556                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2557                                 seq_printf(m, " pipe %c", pipe_name(pipe));
2558                 }
2559         seq_puts(m, "\n");
2560
2561         /*
2562          * VLV/CHV PSR has no kind of performance counter
2563          * SKL+ Perf counter is reset to 0 everytime DC state is entered
2564          */
2565         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2566                 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
2567                         EDP_PSR_PERF_CNT_MASK;
2568
2569                 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2570         }
2571         mutex_unlock(&dev_priv->psr.lock);
2572
2573         intel_runtime_pm_put(dev_priv);
2574         return 0;
2575 }
2576
2577 static int i915_sink_crc(struct seq_file *m, void *data)
2578 {
2579         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2580         struct drm_device *dev = &dev_priv->drm;
2581         struct intel_connector *connector;
2582         struct intel_dp *intel_dp = NULL;
2583         int ret;
2584         u8 crc[6];
2585
2586         drm_modeset_lock_all(dev);
2587         for_each_intel_connector(dev, connector) {
2588                 struct drm_crtc *crtc;
2589
2590                 if (!connector->base.state->best_encoder)
2591                         continue;
2592
2593                 crtc = connector->base.state->crtc;
2594                 if (!crtc->state->active)
2595                         continue;
2596
2597                 if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
2598                         continue;
2599
2600                 intel_dp = enc_to_intel_dp(connector->base.state->best_encoder);
2601
2602                 ret = intel_dp_sink_crc(intel_dp, crc);
2603                 if (ret)
2604                         goto out;
2605
2606                 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2607                            crc[0], crc[1], crc[2],
2608                            crc[3], crc[4], crc[5]);
2609                 goto out;
2610         }
2611         ret = -ENODEV;
2612 out:
2613         drm_modeset_unlock_all(dev);
2614         return ret;
2615 }
2616
2617 static int i915_energy_uJ(struct seq_file *m, void *data)
2618 {
2619         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2620         u64 power;
2621         u32 units;
2622
2623         if (INTEL_GEN(dev_priv) < 6)
2624                 return -ENODEV;
2625
2626         intel_runtime_pm_get(dev_priv);
2627
2628         rdmsrl(MSR_RAPL_POWER_UNIT, power);
2629         power = (power & 0x1f00) >> 8;
2630         units = 1000000 / (1 << power); /* convert to uJ */
2631         power = I915_READ(MCH_SECP_NRG_STTS);
2632         power *= units;
2633
2634         intel_runtime_pm_put(dev_priv);
2635
2636         seq_printf(m, "%llu", (long long unsigned)power);
2637
2638         return 0;
2639 }
2640
2641 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2642 {
2643         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2644         struct pci_dev *pdev = dev_priv->drm.pdev;
2645
2646         if (!HAS_RUNTIME_PM(dev_priv))
2647                 seq_puts(m, "Runtime power management not supported\n");
2648
2649         seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
2650         seq_printf(m, "IRQs disabled: %s\n",
2651                    yesno(!intel_irqs_enabled(dev_priv)));
2652 #ifdef CONFIG_PM
2653         seq_printf(m, "Usage count: %d\n",
2654                    atomic_read(&dev_priv->drm.dev->power.usage_count));
2655 #else
2656         seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2657 #endif
2658         seq_printf(m, "PCI device power state: %s [%d]\n",
2659                    pci_power_name(pdev->current_state),
2660                    pdev->current_state);
2661
2662         return 0;
2663 }
2664
2665 static int i915_power_domain_info(struct seq_file *m, void *unused)
2666 {
2667         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2668         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2669         int i;
2670
2671         mutex_lock(&power_domains->lock);
2672
2673         seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2674         for (i = 0; i < power_domains->power_well_count; i++) {
2675                 struct i915_power_well *power_well;
2676                 enum intel_display_power_domain power_domain;
2677
2678                 power_well = &power_domains->power_wells[i];
2679                 seq_printf(m, "%-25s %d\n", power_well->name,
2680                            power_well->count);
2681
2682                 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2683                      power_domain++) {
2684                         if (!(BIT(power_domain) & power_well->domains))
2685                                 continue;
2686
2687                         seq_printf(m, "  %-23s %d\n",
2688                                  intel_display_power_domain_str(power_domain),
2689                                  power_domains->domain_use_count[power_domain]);
2690                 }
2691         }
2692
2693         mutex_unlock(&power_domains->lock);
2694
2695         return 0;
2696 }
2697
2698 static int i915_dmc_info(struct seq_file *m, void *unused)
2699 {
2700         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2701         struct intel_csr *csr;
2702
2703         if (!HAS_CSR(dev_priv)) {
2704                 seq_puts(m, "not supported\n");
2705                 return 0;
2706         }
2707
2708         csr = &dev_priv->csr;
2709
2710         intel_runtime_pm_get(dev_priv);
2711
2712         seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2713         seq_printf(m, "path: %s\n", csr->fw_path);
2714
2715         if (!csr->dmc_payload)
2716                 goto out;
2717
2718         seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2719                    CSR_VERSION_MINOR(csr->version));
2720
2721         if (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6)) {
2722                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2723                            I915_READ(SKL_CSR_DC3_DC5_COUNT));
2724                 seq_printf(m, "DC5 -> DC6 count: %d\n",
2725                            I915_READ(SKL_CSR_DC5_DC6_COUNT));
2726         } else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) {
2727                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2728                            I915_READ(BXT_CSR_DC3_DC5_COUNT));
2729         }
2730
2731 out:
2732         seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2733         seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2734         seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2735
2736         intel_runtime_pm_put(dev_priv);
2737
2738         return 0;
2739 }
2740
2741 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2742                                  struct drm_display_mode *mode)
2743 {
2744         int i;
2745
2746         for (i = 0; i < tabs; i++)
2747                 seq_putc(m, '\t');
2748
2749         seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2750                    mode->base.id, mode->name,
2751                    mode->vrefresh, mode->clock,
2752                    mode->hdisplay, mode->hsync_start,
2753                    mode->hsync_end, mode->htotal,
2754                    mode->vdisplay, mode->vsync_start,
2755                    mode->vsync_end, mode->vtotal,
2756                    mode->type, mode->flags);
2757 }
2758
2759 static void intel_encoder_info(struct seq_file *m,
2760                                struct intel_crtc *intel_crtc,
2761                                struct intel_encoder *intel_encoder)
2762 {
2763         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2764         struct drm_device *dev = &dev_priv->drm;
2765         struct drm_crtc *crtc = &intel_crtc->base;
2766         struct intel_connector *intel_connector;
2767         struct drm_encoder *encoder;
2768
2769         encoder = &intel_encoder->base;
2770         seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2771                    encoder->base.id, encoder->name);
2772         for_each_connector_on_encoder(dev, encoder, intel_connector) {
2773                 struct drm_connector *connector = &intel_connector->base;
2774                 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2775                            connector->base.id,
2776                            connector->name,
2777                            drm_get_connector_status_name(connector->status));
2778                 if (connector->status == connector_status_connected) {
2779                         struct drm_display_mode *mode = &crtc->mode;
2780                         seq_printf(m, ", mode:\n");
2781                         intel_seq_print_mode(m, 2, mode);
2782                 } else {
2783                         seq_putc(m, '\n');
2784                 }
2785         }
2786 }
2787
2788 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2789 {
2790         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2791         struct drm_device *dev = &dev_priv->drm;
2792         struct drm_crtc *crtc = &intel_crtc->base;
2793         struct intel_encoder *intel_encoder;
2794         struct drm_plane_state *plane_state = crtc->primary->state;
2795         struct drm_framebuffer *fb = plane_state->fb;
2796
2797         if (fb)
2798                 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2799                            fb->base.id, plane_state->src_x >> 16,
2800                            plane_state->src_y >> 16, fb->width, fb->height);
2801         else
2802                 seq_puts(m, "\tprimary plane disabled\n");
2803         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2804                 intel_encoder_info(m, intel_crtc, intel_encoder);
2805 }
2806
2807 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2808 {
2809         struct drm_display_mode *mode = panel->fixed_mode;
2810
2811         seq_printf(m, "\tfixed mode:\n");
2812         intel_seq_print_mode(m, 2, mode);
2813 }
2814
2815 static void intel_dp_info(struct seq_file *m,
2816                           struct intel_connector *intel_connector)
2817 {
2818         struct intel_encoder *intel_encoder = intel_connector->encoder;
2819         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2820
2821         seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2822         seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2823         if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
2824                 intel_panel_info(m, &intel_connector->panel);
2825
2826         drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports,
2827                                 &intel_dp->aux);
2828 }
2829
2830 static void intel_hdmi_info(struct seq_file *m,
2831                             struct intel_connector *intel_connector)
2832 {
2833         struct intel_encoder *intel_encoder = intel_connector->encoder;
2834         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2835
2836         seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
2837 }
2838
2839 static void intel_lvds_info(struct seq_file *m,
2840                             struct intel_connector *intel_connector)
2841 {
2842         intel_panel_info(m, &intel_connector->panel);
2843 }
2844
2845 static void intel_connector_info(struct seq_file *m,
2846                                  struct drm_connector *connector)
2847 {
2848         struct intel_connector *intel_connector = to_intel_connector(connector);
2849         struct intel_encoder *intel_encoder = intel_connector->encoder;
2850         struct drm_display_mode *mode;
2851
2852         seq_printf(m, "connector %d: type %s, status: %s\n",
2853                    connector->base.id, connector->name,
2854                    drm_get_connector_status_name(connector->status));
2855         if (connector->status == connector_status_connected) {
2856                 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2857                 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2858                            connector->display_info.width_mm,
2859                            connector->display_info.height_mm);
2860                 seq_printf(m, "\tsubpixel order: %s\n",
2861                            drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2862                 seq_printf(m, "\tCEA rev: %d\n",
2863                            connector->display_info.cea_rev);
2864         }
2865
2866         if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
2867                 return;
2868
2869         switch (connector->connector_type) {
2870         case DRM_MODE_CONNECTOR_DisplayPort:
2871         case DRM_MODE_CONNECTOR_eDP:
2872                 intel_dp_info(m, intel_connector);
2873                 break;
2874         case DRM_MODE_CONNECTOR_LVDS:
2875                 if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2876                         intel_lvds_info(m, intel_connector);
2877                 break;
2878         case DRM_MODE_CONNECTOR_HDMIA:
2879                 if (intel_encoder->type == INTEL_OUTPUT_HDMI ||
2880                     intel_encoder->type == INTEL_OUTPUT_UNKNOWN)
2881                         intel_hdmi_info(m, intel_connector);
2882                 break;
2883         default:
2884                 break;
2885         }
2886
2887         seq_printf(m, "\tmodes:\n");
2888         list_for_each_entry(mode, &connector->modes, head)
2889                 intel_seq_print_mode(m, 2, mode);
2890 }
2891
2892 static bool cursor_active(struct drm_i915_private *dev_priv, int pipe)
2893 {
2894         u32 state;
2895
2896         if (IS_845G(dev_priv) || IS_I865G(dev_priv))
2897                 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
2898         else
2899                 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2900
2901         return state;
2902 }
2903
2904 static bool cursor_position(struct drm_i915_private *dev_priv,
2905                             int pipe, int *x, int *y)
2906 {
2907         u32 pos;
2908
2909         pos = I915_READ(CURPOS(pipe));
2910
2911         *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2912         if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2913                 *x = -*x;
2914
2915         *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2916         if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2917                 *y = -*y;
2918
2919         return cursor_active(dev_priv, pipe);
2920 }
2921
2922 static const char *plane_type(enum drm_plane_type type)
2923 {
2924         switch (type) {
2925         case DRM_PLANE_TYPE_OVERLAY:
2926                 return "OVL";
2927         case DRM_PLANE_TYPE_PRIMARY:
2928                 return "PRI";
2929         case DRM_PLANE_TYPE_CURSOR:
2930                 return "CUR";
2931         /*
2932          * Deliberately omitting default: to generate compiler warnings
2933          * when a new drm_plane_type gets added.
2934          */
2935         }
2936
2937         return "unknown";
2938 }
2939
2940 static const char *plane_rotation(unsigned int rotation)
2941 {
2942         static char buf[48];
2943         /*
2944          * According to doc only one DRM_ROTATE_ is allowed but this
2945          * will print them all to visualize if the values are misused
2946          */
2947         snprintf(buf, sizeof(buf),
2948                  "%s%s%s%s%s%s(0x%08x)",
2949                  (rotation & DRM_ROTATE_0) ? "0 " : "",
2950                  (rotation & DRM_ROTATE_90) ? "90 " : "",
2951                  (rotation & DRM_ROTATE_180) ? "180 " : "",
2952                  (rotation & DRM_ROTATE_270) ? "270 " : "",
2953                  (rotation & DRM_REFLECT_X) ? "FLIPX " : "",
2954                  (rotation & DRM_REFLECT_Y) ? "FLIPY " : "",
2955                  rotation);
2956
2957         return buf;
2958 }
2959
2960 static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2961 {
2962         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2963         struct drm_device *dev = &dev_priv->drm;
2964         struct intel_plane *intel_plane;
2965
2966         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2967                 struct drm_plane_state *state;
2968                 struct drm_plane *plane = &intel_plane->base;
2969                 char *format_name;
2970
2971                 if (!plane->state) {
2972                         seq_puts(m, "plane->state is NULL!\n");
2973                         continue;
2974                 }
2975
2976                 state = plane->state;
2977
2978                 if (state->fb) {
2979                         format_name = drm_get_format_name(state->fb->pixel_format);
2980                 } else {
2981                         format_name = kstrdup("N/A", GFP_KERNEL);
2982                 }
2983
2984                 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
2985                            plane->base.id,
2986                            plane_type(intel_plane->base.type),
2987                            state->crtc_x, state->crtc_y,
2988                            state->crtc_w, state->crtc_h,
2989                            (state->src_x >> 16),
2990                            ((state->src_x & 0xffff) * 15625) >> 10,
2991                            (state->src_y >> 16),
2992                            ((state->src_y & 0xffff) * 15625) >> 10,
2993                            (state->src_w >> 16),
2994                            ((state->src_w & 0xffff) * 15625) >> 10,
2995                            (state->src_h >> 16),
2996                            ((state->src_h & 0xffff) * 15625) >> 10,
2997                            format_name,
2998                            plane_rotation(state->rotation));
2999
3000                 kfree(format_name);
3001         }
3002 }
3003
3004 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3005 {
3006         struct intel_crtc_state *pipe_config;
3007         int num_scalers = intel_crtc->num_scalers;
3008         int i;
3009
3010         pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3011
3012         /* Not all platformas have a scaler */
3013         if (num_scalers) {
3014                 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3015                            num_scalers,
3016                            pipe_config->scaler_state.scaler_users,
3017                            pipe_config->scaler_state.scaler_id);
3018
3019                 for (i = 0; i < SKL_NUM_SCALERS; i++) {
3020                         struct intel_scaler *sc =
3021                                         &pipe_config->scaler_state.scalers[i];
3022
3023                         seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3024                                    i, yesno(sc->in_use), sc->mode);
3025                 }
3026                 seq_puts(m, "\n");
3027         } else {
3028                 seq_puts(m, "\tNo scalers available on this platform\n");
3029         }
3030 }
3031
3032 static int i915_display_info(struct seq_file *m, void *unused)
3033 {
3034         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3035         struct drm_device *dev = &dev_priv->drm;
3036         struct intel_crtc *crtc;
3037         struct drm_connector *connector;
3038
3039         intel_runtime_pm_get(dev_priv);
3040         drm_modeset_lock_all(dev);
3041         seq_printf(m, "CRTC info\n");
3042         seq_printf(m, "---------\n");
3043         for_each_intel_crtc(dev, crtc) {
3044                 bool active;
3045                 struct intel_crtc_state *pipe_config;
3046                 int x, y;
3047
3048                 pipe_config = to_intel_crtc_state(crtc->base.state);
3049
3050                 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3051                            crtc->base.base.id, pipe_name(crtc->pipe),
3052                            yesno(pipe_config->base.active),
3053                            pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3054                            yesno(pipe_config->dither), pipe_config->pipe_bpp);
3055
3056                 if (pipe_config->base.active) {
3057                         intel_crtc_info(m, crtc);
3058
3059                         active = cursor_position(dev_priv, crtc->pipe, &x, &y);
3060                         seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
3061                                    yesno(crtc->cursor_base),
3062                                    x, y, crtc->base.cursor->state->crtc_w,
3063                                    crtc->base.cursor->state->crtc_h,
3064                                    crtc->cursor_addr, yesno(active));
3065                         intel_scaler_info(m, crtc);
3066                         intel_plane_info(m, crtc);
3067                 }
3068
3069                 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3070                            yesno(!crtc->cpu_fifo_underrun_disabled),
3071                            yesno(!crtc->pch_fifo_underrun_disabled));
3072         }
3073
3074         seq_printf(m, "\n");
3075         seq_printf(m, "Connector info\n");
3076         seq_printf(m, "--------------\n");
3077         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3078                 intel_connector_info(m, connector);
3079         }
3080         drm_modeset_unlock_all(dev);
3081         intel_runtime_pm_put(dev_priv);
3082
3083         return 0;
3084 }
3085
3086 static int i915_engine_info(struct seq_file *m, void *unused)
3087 {
3088         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3089         struct intel_engine_cs *engine;
3090
3091         for_each_engine(engine, dev_priv) {
3092                 struct intel_breadcrumbs *b = &engine->breadcrumbs;
3093                 struct drm_i915_gem_request *rq;
3094                 struct rb_node *rb;
3095                 u64 addr;
3096
3097                 seq_printf(m, "%s\n", engine->name);
3098                 seq_printf(m, "\tcurrent seqno %x, last %x, hangcheck %x [score %d]\n",
3099                            intel_engine_get_seqno(engine),
3100                            engine->last_submitted_seqno,
3101                            engine->hangcheck.seqno,
3102                            engine->hangcheck.score);
3103
3104                 rcu_read_lock();
3105
3106                 seq_printf(m, "\tRequests:\n");
3107
3108                 rq = list_first_entry(&engine->request_list,
3109                                 struct drm_i915_gem_request, link);
3110                 if (&rq->link != &engine->request_list)
3111                         print_request(m, rq, "\t\tfirst  ");
3112
3113                 rq = list_last_entry(&engine->request_list,
3114                                 struct drm_i915_gem_request, link);
3115                 if (&rq->link != &engine->request_list)
3116                         print_request(m, rq, "\t\tlast   ");
3117
3118                 rq = i915_gem_find_active_request(engine);
3119                 if (rq) {
3120                         print_request(m, rq, "\t\tactive ");
3121                         seq_printf(m,
3122                                    "\t\t[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]\n",
3123                                    rq->head, rq->postfix, rq->tail,
3124                                    rq->batch ? upper_32_bits(rq->batch->node.start) : ~0u,
3125                                    rq->batch ? lower_32_bits(rq->batch->node.start) : ~0u);
3126                 }
3127
3128                 seq_printf(m, "\tRING_START: 0x%08x [0x%08x]\n",
3129                            I915_READ(RING_START(engine->mmio_base)),
3130                            rq ? i915_ggtt_offset(rq->ring->vma) : 0);
3131                 seq_printf(m, "\tRING_HEAD:  0x%08x [0x%08x]\n",
3132                            I915_READ(RING_HEAD(engine->mmio_base)) & HEAD_ADDR,
3133                            rq ? rq->ring->head : 0);
3134                 seq_printf(m, "\tRING_TAIL:  0x%08x [0x%08x]\n",
3135                            I915_READ(RING_TAIL(engine->mmio_base)) & TAIL_ADDR,
3136                            rq ? rq->ring->tail : 0);
3137                 seq_printf(m, "\tRING_CTL:   0x%08x [%s]\n",
3138                            I915_READ(RING_CTL(engine->mmio_base)),
3139                            I915_READ(RING_CTL(engine->mmio_base)) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? "waiting" : "");
3140
3141                 rcu_read_unlock();
3142
3143                 addr = intel_engine_get_active_head(engine);
3144                 seq_printf(m, "\tACTHD:  0x%08x_%08x\n",
3145                            upper_32_bits(addr), lower_32_bits(addr));
3146                 addr = intel_engine_get_last_batch_head(engine);
3147                 seq_printf(m, "\tBBADDR: 0x%08x_%08x\n",
3148                            upper_32_bits(addr), lower_32_bits(addr));
3149
3150                 if (i915.enable_execlists) {
3151                         u32 ptr, read, write;
3152
3153                         seq_printf(m, "\tExeclist status: 0x%08x %08x\n",
3154                                    I915_READ(RING_EXECLIST_STATUS_LO(engine)),
3155                                    I915_READ(RING_EXECLIST_STATUS_HI(engine)));
3156
3157                         ptr = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
3158                         read = GEN8_CSB_READ_PTR(ptr);
3159                         write = GEN8_CSB_WRITE_PTR(ptr);
3160                         seq_printf(m, "\tExeclist CSB read %d, write %d\n",
3161                                    read, write);
3162                         if (read >= GEN8_CSB_ENTRIES)
3163                                 read = 0;
3164                         if (write >= GEN8_CSB_ENTRIES)
3165                                 write = 0;
3166                         if (read > write)
3167                                 write += GEN8_CSB_ENTRIES;
3168                         while (read < write) {
3169                                 unsigned int idx = ++read % GEN8_CSB_ENTRIES;
3170
3171                                 seq_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n",
3172                                            idx,
3173                                            I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, idx)),
3174                                            I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, idx)));
3175                         }
3176
3177                         rcu_read_lock();
3178                         rq = READ_ONCE(engine->execlist_port[0].request);
3179                         if (rq)
3180                                 print_request(m, rq, "\t\tELSP[0] ");
3181                         else
3182                                 seq_printf(m, "\t\tELSP[0] idle\n");
3183                         rq = READ_ONCE(engine->execlist_port[1].request);
3184                         if (rq)
3185                                 print_request(m, rq, "\t\tELSP[1] ");
3186                         else
3187                                 seq_printf(m, "\t\tELSP[1] idle\n");
3188                         rcu_read_unlock();
3189                 } else if (INTEL_GEN(dev_priv) > 6) {
3190                         seq_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
3191                                    I915_READ(RING_PP_DIR_BASE(engine)));
3192                         seq_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n",
3193                                    I915_READ(RING_PP_DIR_BASE_READ(engine)));
3194                         seq_printf(m, "\tPP_DIR_DCLV: 0x%08x\n",
3195                                    I915_READ(RING_PP_DIR_DCLV(engine)));
3196                 }
3197
3198                 spin_lock(&b->lock);
3199                 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
3200                         struct intel_wait *w = container_of(rb, typeof(*w), node);
3201
3202                         seq_printf(m, "\t%s [%d] waiting for %x\n",
3203                                    w->tsk->comm, w->tsk->pid, w->seqno);
3204                 }
3205                 spin_unlock(&b->lock);
3206
3207                 seq_puts(m, "\n");
3208         }
3209
3210         return 0;
3211 }
3212
3213 static int i915_semaphore_status(struct seq_file *m, void *unused)
3214 {
3215         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3216         struct drm_device *dev = &dev_priv->drm;
3217         struct intel_engine_cs *engine;
3218         int num_rings = INTEL_INFO(dev_priv)->num_rings;
3219         enum intel_engine_id id;
3220         int j, ret;
3221
3222         if (!i915.semaphores) {
3223                 seq_puts(m, "Semaphores are disabled\n");
3224                 return 0;
3225         }
3226
3227         ret = mutex_lock_interruptible(&dev->struct_mutex);
3228         if (ret)
3229                 return ret;
3230         intel_runtime_pm_get(dev_priv);
3231
3232         if (IS_BROADWELL(dev_priv)) {
3233                 struct page *page;
3234                 uint64_t *seqno;
3235
3236                 page = i915_gem_object_get_page(dev_priv->semaphore->obj, 0);
3237
3238                 seqno = (uint64_t *)kmap_atomic(page);
3239                 for_each_engine_id(engine, dev_priv, id) {
3240                         uint64_t offset;
3241
3242                         seq_printf(m, "%s\n", engine->name);
3243
3244                         seq_puts(m, "  Last signal:");
3245                         for (j = 0; j < num_rings; j++) {
3246                                 offset = id * I915_NUM_ENGINES + j;
3247                                 seq_printf(m, "0x%08llx (0x%02llx) ",
3248                                            seqno[offset], offset * 8);
3249                         }
3250                         seq_putc(m, '\n');
3251
3252                         seq_puts(m, "  Last wait:  ");
3253                         for (j = 0; j < num_rings; j++) {
3254                                 offset = id + (j * I915_NUM_ENGINES);
3255                                 seq_printf(m, "0x%08llx (0x%02llx) ",
3256                                            seqno[offset], offset * 8);
3257                         }
3258                         seq_putc(m, '\n');
3259
3260                 }
3261                 kunmap_atomic(seqno);
3262         } else {
3263                 seq_puts(m, "  Last signal:");
3264                 for_each_engine(engine, dev_priv)
3265                         for (j = 0; j < num_rings; j++)
3266                                 seq_printf(m, "0x%08x\n",
3267                                            I915_READ(engine->semaphore.mbox.signal[j]));
3268                 seq_putc(m, '\n');
3269         }
3270
3271         seq_puts(m, "\nSync seqno:\n");
3272         for_each_engine(engine, dev_priv) {
3273                 for (j = 0; j < num_rings; j++)
3274                         seq_printf(m, "  0x%08x ",
3275                                    engine->semaphore.sync_seqno[j]);
3276                 seq_putc(m, '\n');
3277         }
3278         seq_putc(m, '\n');
3279
3280         intel_runtime_pm_put(dev_priv);
3281         mutex_unlock(&dev->struct_mutex);
3282         return 0;
3283 }
3284
3285 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3286 {
3287         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3288         struct drm_device *dev = &dev_priv->drm;
3289         int i;
3290
3291         drm_modeset_lock_all(dev);
3292         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3293                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3294
3295                 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3296                 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3297                            pll->config.crtc_mask, pll->active_mask, yesno(pll->on));
3298                 seq_printf(m, " tracked hardware state:\n");
3299                 seq_printf(m, " dpll:    0x%08x\n", pll->config.hw_state.dpll);
3300                 seq_printf(m, " dpll_md: 0x%08x\n",
3301                            pll->config.hw_state.dpll_md);
3302                 seq_printf(m, " fp0:     0x%08x\n", pll->config.hw_state.fp0);
3303                 seq_printf(m, " fp1:     0x%08x\n", pll->config.hw_state.fp1);
3304                 seq_printf(m, " wrpll:   0x%08x\n", pll->config.hw_state.wrpll);
3305         }
3306         drm_modeset_unlock_all(dev);
3307
3308         return 0;
3309 }
3310
3311 static int i915_wa_registers(struct seq_file *m, void *unused)
3312 {
3313         int i;
3314         int ret;
3315         struct intel_engine_cs *engine;
3316         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3317         struct drm_device *dev = &dev_priv->drm;
3318         struct i915_workarounds *workarounds = &dev_priv->workarounds;
3319         enum intel_engine_id id;
3320
3321         ret = mutex_lock_interruptible(&dev->struct_mutex);
3322         if (ret)
3323                 return ret;
3324
3325         intel_runtime_pm_get(dev_priv);
3326
3327         seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
3328         for_each_engine_id(engine, dev_priv, id)
3329                 seq_printf(m, "HW whitelist count for %s: %d\n",
3330                            engine->name, workarounds->hw_whitelist_count[id]);
3331         for (i = 0; i < workarounds->count; ++i) {
3332                 i915_reg_t addr;
3333                 u32 mask, value, read;
3334                 bool ok;
3335
3336                 addr = workarounds->reg[i].addr;
3337                 mask = workarounds->reg[i].mask;
3338                 value = workarounds->reg[i].value;
3339                 read = I915_READ(addr);
3340                 ok = (value & mask) == (read & mask);
3341                 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3342                            i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
3343         }
3344
3345         intel_runtime_pm_put(dev_priv);
3346         mutex_unlock(&dev->struct_mutex);
3347
3348         return 0;
3349 }
3350
3351 static int i915_ddb_info(struct seq_file *m, void *unused)
3352 {
3353         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3354         struct drm_device *dev = &dev_priv->drm;
3355         struct skl_ddb_allocation *ddb;
3356         struct skl_ddb_entry *entry;
3357         enum pipe pipe;
3358         int plane;
3359
3360         if (INTEL_GEN(dev_priv) < 9)
3361                 return 0;
3362
3363         drm_modeset_lock_all(dev);
3364
3365         ddb = &dev_priv->wm.skl_hw.ddb;
3366
3367         seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3368
3369         for_each_pipe(dev_priv, pipe) {
3370                 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3371
3372                 for_each_plane(dev_priv, pipe, plane) {
3373                         entry = &ddb->plane[pipe][plane];
3374                         seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane + 1,
3375                                    entry->start, entry->end,
3376                                    skl_ddb_entry_size(entry));
3377                 }
3378
3379                 entry = &ddb->plane[pipe][PLANE_CURSOR];
3380                 seq_printf(m, "  %-13s%8u%8u%8u\n", "Cursor", entry->start,
3381                            entry->end, skl_ddb_entry_size(entry));
3382         }
3383
3384         drm_modeset_unlock_all(dev);
3385
3386         return 0;
3387 }
3388
3389 static void drrs_status_per_crtc(struct seq_file *m,
3390                                  struct drm_device *dev,
3391                                  struct intel_crtc *intel_crtc)
3392 {
3393         struct drm_i915_private *dev_priv = to_i915(dev);
3394         struct i915_drrs *drrs = &dev_priv->drrs;
3395         int vrefresh = 0;
3396         struct drm_connector *connector;
3397
3398         drm_for_each_connector(connector, dev) {
3399                 if (connector->state->crtc != &intel_crtc->base)
3400                         continue;
3401
3402                 seq_printf(m, "%s:\n", connector->name);
3403         }
3404
3405         if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3406                 seq_puts(m, "\tVBT: DRRS_type: Static");
3407         else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3408                 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3409         else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3410                 seq_puts(m, "\tVBT: DRRS_type: None");
3411         else
3412                 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3413
3414         seq_puts(m, "\n\n");
3415
3416         if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3417                 struct intel_panel *panel;
3418
3419                 mutex_lock(&drrs->mutex);
3420                 /* DRRS Supported */
3421                 seq_puts(m, "\tDRRS Supported: Yes\n");
3422
3423                 /* disable_drrs() will make drrs->dp NULL */
3424                 if (!drrs->dp) {
3425                         seq_puts(m, "Idleness DRRS: Disabled");
3426                         mutex_unlock(&drrs->mutex);
3427                         return;
3428                 }
3429
3430                 panel = &drrs->dp->attached_connector->panel;
3431                 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3432                                         drrs->busy_frontbuffer_bits);
3433
3434                 seq_puts(m, "\n\t\t");
3435                 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3436                         seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3437                         vrefresh = panel->fixed_mode->vrefresh;
3438                 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3439                         seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3440                         vrefresh = panel->downclock_mode->vrefresh;
3441                 } else {
3442                         seq_printf(m, "DRRS_State: Unknown(%d)\n",
3443                                                 drrs->refresh_rate_type);
3444                         mutex_unlock(&drrs->mutex);
3445                         return;
3446                 }
3447                 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3448
3449                 seq_puts(m, "\n\t\t");
3450                 mutex_unlock(&drrs->mutex);
3451         } else {
3452                 /* DRRS not supported. Print the VBT parameter*/
3453                 seq_puts(m, "\tDRRS Supported : No");
3454         }
3455         seq_puts(m, "\n");
3456 }
3457
3458 static int i915_drrs_status(struct seq_file *m, void *unused)
3459 {
3460         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3461         struct drm_device *dev = &dev_priv->drm;
3462         struct intel_crtc *intel_crtc;
3463         int active_crtc_cnt = 0;
3464
3465         drm_modeset_lock_all(dev);
3466         for_each_intel_crtc(dev, intel_crtc) {
3467                 if (intel_crtc->base.state->active) {
3468                         active_crtc_cnt++;
3469                         seq_printf(m, "\nCRTC %d:  ", active_crtc_cnt);
3470
3471                         drrs_status_per_crtc(m, dev, intel_crtc);
3472                 }
3473         }
3474         drm_modeset_unlock_all(dev);
3475
3476         if (!active_crtc_cnt)
3477                 seq_puts(m, "No active crtc found\n");
3478
3479         return 0;
3480 }
3481
3482 struct pipe_crc_info {
3483         const char *name;
3484         struct drm_i915_private *dev_priv;
3485         enum pipe pipe;
3486 };
3487
3488 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3489 {
3490         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3491         struct drm_device *dev = &dev_priv->drm;
3492         struct intel_encoder *intel_encoder;
3493         struct intel_digital_port *intel_dig_port;
3494         struct drm_connector *connector;
3495
3496         drm_modeset_lock_all(dev);
3497         drm_for_each_connector(connector, dev) {
3498                 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
3499                         continue;
3500
3501                 intel_encoder = intel_attached_encoder(connector);
3502                 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
3503                         continue;
3504
3505                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
3506                 if (!intel_dig_port->dp.can_mst)
3507                         continue;
3508
3509                 seq_printf(m, "MST Source Port %c\n",
3510                            port_name(intel_dig_port->port));
3511                 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3512         }
3513         drm_modeset_unlock_all(dev);
3514         return 0;
3515 }
3516
3517 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3518 {
3519         struct pipe_crc_info *info = inode->i_private;
3520         struct drm_i915_private *dev_priv = info->dev_priv;
3521         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3522
3523         if (info->pipe >= INTEL_INFO(dev_priv)->num_pipes)
3524                 return -ENODEV;
3525
3526         spin_lock_irq(&pipe_crc->lock);
3527
3528         if (pipe_crc->opened) {
3529                 spin_unlock_irq(&pipe_crc->lock);
3530                 return -EBUSY; /* already open */
3531         }
3532
3533         pipe_crc->opened = true;
3534         filep->private_data = inode->i_private;
3535
3536         spin_unlock_irq(&pipe_crc->lock);
3537
3538         return 0;
3539 }
3540
3541 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3542 {
3543         struct pipe_crc_info *info = inode->i_private;
3544         struct drm_i915_private *dev_priv = info->dev_priv;
3545         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3546
3547         spin_lock_irq(&pipe_crc->lock);
3548         pipe_crc->opened = false;
3549         spin_unlock_irq(&pipe_crc->lock);
3550
3551         return 0;
3552 }
3553
3554 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3555 #define PIPE_CRC_LINE_LEN       (6 * 8 + 5 + 1)
3556 /* account for \'0' */
3557 #define PIPE_CRC_BUFFER_LEN     (PIPE_CRC_LINE_LEN + 1)
3558
3559 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
3560 {
3561         assert_spin_locked(&pipe_crc->lock);
3562         return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3563                         INTEL_PIPE_CRC_ENTRIES_NR);
3564 }
3565
3566 static ssize_t
3567 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3568                    loff_t *pos)
3569 {
3570         struct pipe_crc_info *info = filep->private_data;
3571         struct drm_i915_private *dev_priv = info->dev_priv;
3572         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3573         char buf[PIPE_CRC_BUFFER_LEN];
3574         int n_entries;
3575         ssize_t bytes_read;
3576
3577         /*
3578          * Don't allow user space to provide buffers not big enough to hold
3579          * a line of data.
3580          */
3581         if (count < PIPE_CRC_LINE_LEN)
3582                 return -EINVAL;
3583
3584         if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
3585                 return 0;
3586
3587         /* nothing to read */
3588         spin_lock_irq(&pipe_crc->lock);
3589         while (pipe_crc_data_count(pipe_crc) == 0) {
3590                 int ret;
3591
3592                 if (filep->f_flags & O_NONBLOCK) {
3593                         spin_unlock_irq(&pipe_crc->lock);
3594                         return -EAGAIN;
3595                 }
3596
3597                 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3598                                 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3599                 if (ret) {
3600                         spin_unlock_irq(&pipe_crc->lock);
3601                         return ret;
3602                 }
3603         }
3604
3605         /* We now have one or more entries to read */
3606         n_entries = count / PIPE_CRC_LINE_LEN;
3607
3608         bytes_read = 0;
3609         while (n_entries > 0) {
3610                 struct intel_pipe_crc_entry *entry =
3611                         &pipe_crc->entries[pipe_crc->tail];
3612
3613                 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3614                              INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3615                         break;
3616
3617                 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3618                 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3619
3620                 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3621                                        "%8u %8x %8x %8x %8x %8x\n",
3622                                        entry->frame, entry->crc[0],
3623                                        entry->crc[1], entry->crc[2],
3624                                        entry->crc[3], entry->crc[4]);
3625
3626                 spin_unlock_irq(&pipe_crc->lock);
3627
3628                 if (copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN))
3629                         return -EFAULT;
3630
3631                 user_buf += PIPE_CRC_LINE_LEN;
3632                 n_entries--;
3633
3634                 spin_lock_irq(&pipe_crc->lock);
3635         }
3636
3637         spin_unlock_irq(&pipe_crc->lock);
3638
3639         return bytes_read;
3640 }
3641
3642 static const struct file_operations i915_pipe_crc_fops = {
3643         .owner = THIS_MODULE,
3644         .open = i915_pipe_crc_open,
3645         .read = i915_pipe_crc_read,
3646         .release = i915_pipe_crc_release,
3647 };
3648
3649 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3650         {
3651                 .name = "i915_pipe_A_crc",
3652                 .pipe = PIPE_A,
3653         },
3654         {
3655                 .name = "i915_pipe_B_crc",
3656                 .pipe = PIPE_B,
3657         },
3658         {
3659                 .name = "i915_pipe_C_crc",
3660                 .pipe = PIPE_C,
3661         },
3662 };
3663
3664 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3665                                 enum pipe pipe)
3666 {
3667         struct drm_i915_private *dev_priv = to_i915(minor->dev);
3668         struct dentry *ent;
3669         struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3670
3671         info->dev_priv = dev_priv;
3672         ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3673                                   &i915_pipe_crc_fops);
3674         if (!ent)
3675                 return -ENOMEM;
3676
3677         return drm_add_fake_info_node(minor, ent, info);
3678 }
3679
3680 static const char * const pipe_crc_sources[] = {
3681         "none",
3682         "plane1",
3683         "plane2",
3684         "pf",
3685         "pipe",
3686         "TV",
3687         "DP-B",
3688         "DP-C",
3689         "DP-D",
3690         "auto",
3691 };
3692
3693 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3694 {
3695         BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3696         return pipe_crc_sources[source];
3697 }
3698
3699 static int display_crc_ctl_show(struct seq_file *m, void *data)
3700 {
3701         struct drm_i915_private *dev_priv = m->private;
3702         int i;
3703
3704         for (i = 0; i < I915_MAX_PIPES; i++)
3705                 seq_printf(m, "%c %s\n", pipe_name(i),
3706                            pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3707
3708         return 0;
3709 }
3710
3711 static int display_crc_ctl_open(struct inode *inode, struct file *file)
3712 {
3713         return single_open(file, display_crc_ctl_show, inode->i_private);
3714 }
3715
3716 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3717                                  uint32_t *val)
3718 {
3719         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3720                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3721
3722         switch (*source) {
3723         case INTEL_PIPE_CRC_SOURCE_PIPE:
3724                 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3725                 break;
3726         case INTEL_PIPE_CRC_SOURCE_NONE:
3727                 *val = 0;
3728                 break;
3729         default:
3730                 return -EINVAL;
3731         }
3732
3733         return 0;
3734 }
3735
3736 static int i9xx_pipe_crc_auto_source(struct drm_i915_private *dev_priv,
3737                                      enum pipe pipe,
3738                                      enum intel_pipe_crc_source *source)
3739 {
3740         struct drm_device *dev = &dev_priv->drm;
3741         struct intel_encoder *encoder;
3742         struct intel_crtc *crtc;
3743         struct intel_digital_port *dig_port;
3744         int ret = 0;
3745
3746         *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3747
3748         drm_modeset_lock_all(dev);
3749         for_each_intel_encoder(dev, encoder) {
3750                 if (!encoder->base.crtc)
3751                         continue;
3752
3753                 crtc = to_intel_crtc(encoder->base.crtc);
3754
3755                 if (crtc->pipe != pipe)
3756                         continue;
3757
3758                 switch (encoder->type) {
3759                 case INTEL_OUTPUT_TVOUT:
3760                         *source = INTEL_PIPE_CRC_SOURCE_TV;
3761                         break;
3762                 case INTEL_OUTPUT_DP:
3763                 case INTEL_OUTPUT_EDP:
3764                         dig_port = enc_to_dig_port(&encoder->base);
3765                         switch (dig_port->port) {
3766                         case PORT_B:
3767                                 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3768                                 break;
3769                         case PORT_C:
3770                                 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3771                                 break;
3772                         case PORT_D:
3773                                 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3774                                 break;
3775                         default:
3776                                 WARN(1, "nonexisting DP port %c\n",
3777                                      port_name(dig_port->port));
3778                                 break;
3779                         }
3780                         break;
3781                 default:
3782                         break;
3783                 }
3784         }
3785         drm_modeset_unlock_all(dev);
3786
3787         return ret;
3788 }
3789
3790 static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
3791                                 enum pipe pipe,
3792                                 enum intel_pipe_crc_source *source,
3793                                 uint32_t *val)
3794 {
3795         bool need_stable_symbols = false;
3796
3797         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3798                 int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
3799                 if (ret)
3800                         return ret;
3801         }
3802
3803         switch (*source) {
3804         case INTEL_PIPE_CRC_SOURCE_PIPE:
3805                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3806                 break;
3807         case INTEL_PIPE_CRC_SOURCE_DP_B:
3808                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3809                 need_stable_symbols = true;
3810                 break;
3811         case INTEL_PIPE_CRC_SOURCE_DP_C:
3812                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3813                 need_stable_symbols = true;
3814                 break;
3815         case INTEL_PIPE_CRC_SOURCE_DP_D:
3816                 if (!IS_CHERRYVIEW(dev_priv))
3817                         return -EINVAL;
3818                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3819                 need_stable_symbols = true;
3820                 break;
3821         case INTEL_PIPE_CRC_SOURCE_NONE:
3822                 *val = 0;
3823                 break;
3824         default:
3825                 return -EINVAL;
3826         }
3827
3828         /*
3829          * When the pipe CRC tap point is after the transcoders we need
3830          * to tweak symbol-level features to produce a deterministic series of
3831          * symbols for a given frame. We need to reset those features only once
3832          * a frame (instead of every nth symbol):
3833          *   - DC-balance: used to ensure a better clock recovery from the data
3834          *     link (SDVO)
3835          *   - DisplayPort scrambling: used for EMI reduction
3836          */
3837         if (need_stable_symbols) {
3838                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3839
3840                 tmp |= DC_BALANCE_RESET_VLV;
3841                 switch (pipe) {
3842                 case PIPE_A:
3843                         tmp |= PIPE_A_SCRAMBLE_RESET;
3844                         break;
3845                 case PIPE_B:
3846                         tmp |= PIPE_B_SCRAMBLE_RESET;
3847                         break;
3848                 case PIPE_C:
3849                         tmp |= PIPE_C_SCRAMBLE_RESET;
3850                         break;
3851                 default:
3852                         return -EINVAL;
3853                 }
3854                 I915_WRITE(PORT_DFT2_G4X, tmp);
3855         }
3856
3857         return 0;
3858 }
3859
3860 static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
3861                                  enum pipe pipe,
3862                                  enum intel_pipe_crc_source *source,
3863                                  uint32_t *val)
3864 {
3865         bool need_stable_symbols = false;
3866
3867         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3868                 int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
3869                 if (ret)
3870                         return ret;
3871         }
3872
3873         switch (*source) {
3874         case INTEL_PIPE_CRC_SOURCE_PIPE:
3875                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3876                 break;
3877         case INTEL_PIPE_CRC_SOURCE_TV:
3878                 if (!SUPPORTS_TV(dev_priv))
3879                         return -EINVAL;
3880                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3881                 break;
3882         case INTEL_PIPE_CRC_SOURCE_DP_B:
3883                 if (!IS_G4X(dev_priv))
3884                         return -EINVAL;
3885                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3886                 need_stable_symbols = true;
3887                 break;
3888         case INTEL_PIPE_CRC_SOURCE_DP_C:
3889                 if (!IS_G4X(dev_priv))
3890                         return -EINVAL;
3891                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3892                 need_stable_symbols = true;
3893                 break;
3894         case INTEL_PIPE_CRC_SOURCE_DP_D:
3895                 if (!IS_G4X(dev_priv))
3896                         return -EINVAL;
3897                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3898                 need_stable_symbols = true;
3899                 break;
3900         case INTEL_PIPE_CRC_SOURCE_NONE:
3901                 *val = 0;
3902                 break;
3903         default:
3904                 return -EINVAL;
3905         }
3906
3907         /*
3908          * When the pipe CRC tap point is after the transcoders we need
3909          * to tweak symbol-level features to produce a deterministic series of
3910          * symbols for a given frame. We need to reset those features only once
3911          * a frame (instead of every nth symbol):
3912          *   - DC-balance: used to ensure a better clock recovery from the data
3913          *     link (SDVO)
3914          *   - DisplayPort scrambling: used for EMI reduction
3915          */
3916         if (need_stable_symbols) {
3917                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3918
3919                 WARN_ON(!IS_G4X(dev_priv));
3920
3921                 I915_WRITE(PORT_DFT_I9XX,
3922                            I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3923
3924                 if (pipe == PIPE_A)
3925                         tmp |= PIPE_A_SCRAMBLE_RESET;
3926                 else
3927                         tmp |= PIPE_B_SCRAMBLE_RESET;
3928
3929                 I915_WRITE(PORT_DFT2_G4X, tmp);
3930         }
3931
3932         return 0;
3933 }
3934
3935 static void vlv_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
3936                                          enum pipe pipe)
3937 {
3938         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3939
3940         switch (pipe) {
3941         case PIPE_A:
3942                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3943                 break;
3944         case PIPE_B:
3945                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3946                 break;
3947         case PIPE_C:
3948                 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3949                 break;
3950         default:
3951                 return;
3952         }
3953         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3954                 tmp &= ~DC_BALANCE_RESET_VLV;
3955         I915_WRITE(PORT_DFT2_G4X, tmp);
3956
3957 }
3958
3959 static void g4x_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
3960                                          enum pipe pipe)
3961 {
3962         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3963
3964         if (pipe == PIPE_A)
3965                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3966         else
3967                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3968         I915_WRITE(PORT_DFT2_G4X, tmp);
3969
3970         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3971                 I915_WRITE(PORT_DFT_I9XX,
3972                            I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3973         }
3974 }
3975
3976 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3977                                 uint32_t *val)
3978 {
3979         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3980                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3981
3982         switch (*source) {
3983         case INTEL_PIPE_CRC_SOURCE_PLANE1:
3984                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3985                 break;
3986         case INTEL_PIPE_CRC_SOURCE_PLANE2:
3987                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3988                 break;
3989         case INTEL_PIPE_CRC_SOURCE_PIPE:
3990                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3991                 break;
3992         case INTEL_PIPE_CRC_SOURCE_NONE:
3993                 *val = 0;
3994                 break;
3995         default:
3996                 return -EINVAL;
3997         }
3998
3999         return 0;
4000 }
4001
4002 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_i915_private *dev_priv,
4003                                         bool enable)
4004 {
4005         struct drm_device *dev = &dev_priv->drm;
4006         struct intel_crtc *crtc =
4007                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
4008         struct intel_crtc_state *pipe_config;
4009         struct drm_atomic_state *state;
4010         int ret = 0;
4011
4012         drm_modeset_lock_all(dev);
4013         state = drm_atomic_state_alloc(dev);
4014         if (!state) {
4015                 ret = -ENOMEM;
4016                 goto out;
4017         }
4018
4019         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
4020         pipe_config = intel_atomic_get_crtc_state(state, crtc);
4021         if (IS_ERR(pipe_config)) {
4022                 ret = PTR_ERR(pipe_config);
4023                 goto out;
4024         }
4025
4026         pipe_config->pch_pfit.force_thru = enable;
4027         if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
4028             pipe_config->pch_pfit.enabled != enable)
4029                 pipe_config->base.connectors_changed = true;
4030
4031         ret = drm_atomic_commit(state);
4032 out:
4033         drm_modeset_unlock_all(dev);
4034         WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
4035         if (ret)
4036                 drm_atomic_state_free(state);
4037 }
4038
4039 static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
4040                                 enum pipe pipe,
4041                                 enum intel_pipe_crc_source *source,
4042                                 uint32_t *val)
4043 {
4044         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
4045                 *source = INTEL_PIPE_CRC_SOURCE_PF;
4046
4047         switch (*source) {
4048         case INTEL_PIPE_CRC_SOURCE_PLANE1:
4049                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
4050                 break;
4051         case INTEL_PIPE_CRC_SOURCE_PLANE2:
4052                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
4053                 break;
4054         case INTEL_PIPE_CRC_SOURCE_PF:
4055                 if (IS_HASWELL(dev_priv) && pipe == PIPE_A)
4056                         hsw_trans_edp_pipe_A_crc_wa(dev_priv, true);
4057
4058                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
4059                 break;
4060         case INTEL_PIPE_CRC_SOURCE_NONE:
4061                 *val = 0;
4062                 break;
4063         default:
4064                 return -EINVAL;
4065         }
4066
4067         return 0;
4068 }
4069
4070 static int pipe_crc_set_source(struct drm_i915_private *dev_priv,
4071                                enum pipe pipe,
4072                                enum intel_pipe_crc_source source)
4073 {
4074         struct drm_device *dev = &dev_priv->drm;
4075         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
4076         struct intel_crtc *crtc =
4077                         to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
4078         enum intel_display_power_domain power_domain;
4079         u32 val = 0; /* shut up gcc */
4080         int ret;
4081
4082         if (pipe_crc->source == source)
4083                 return 0;
4084
4085         /* forbid changing the source without going back to 'none' */
4086         if (pipe_crc->source && source)
4087                 return -EINVAL;
4088
4089         power_domain = POWER_DOMAIN_PIPE(pipe);
4090         if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
4091                 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
4092                 return -EIO;
4093         }
4094
4095         if (IS_GEN2(dev_priv))
4096                 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
4097         else if (INTEL_GEN(dev_priv) < 5)
4098                 ret = i9xx_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val);
4099         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4100                 ret = vlv_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val);
4101         else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv))
4102                 ret = ilk_pipe_crc_ctl_reg(&source, &val);
4103         else
4104                 ret = ivb_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val);
4105
4106         if (ret != 0)
4107                 goto out;
4108
4109         /* none -> real source transition */
4110         if (source) {
4111                 struct intel_pipe_crc_entry *entries;
4112
4113                 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4114                                  pipe_name(pipe), pipe_crc_source_name(source));
4115
4116                 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
4117                                   sizeof(pipe_crc->entries[0]),
4118                                   GFP_KERNEL);
4119                 if (!entries) {
4120                         ret = -ENOMEM;
4121                         goto out;
4122                 }
4123
4124                 /*
4125                  * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4126                  * enabled and disabled dynamically based on package C states,
4127                  * user space can't make reliable use of the CRCs, so let's just
4128                  * completely disable it.
4129                  */
4130                 hsw_disable_ips(crtc);
4131
4132                 spin_lock_irq(&pipe_crc->lock);
4133                 kfree(pipe_crc->entries);
4134                 pipe_crc->entries = entries;
4135                 pipe_crc->head = 0;
4136                 pipe_crc->tail = 0;
4137                 spin_unlock_irq(&pipe_crc->lock);
4138         }
4139
4140         pipe_crc->source = source;
4141
4142         I915_WRITE(PIPE_CRC_CTL(pipe), val);
4143         POSTING_READ(PIPE_CRC_CTL(pipe));
4144
4145         /* real source -> none transition */
4146         if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
4147                 struct intel_pipe_crc_entry *entries;
4148                 struct intel_crtc *crtc =
4149                         to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
4150
4151                 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4152                                  pipe_name(pipe));
4153
4154                 drm_modeset_lock(&crtc->base.mutex, NULL);
4155                 if (crtc->base.state->active)
4156                         intel_wait_for_vblank(dev, pipe);
4157                 drm_modeset_unlock(&crtc->base.mutex);
4158
4159                 spin_lock_irq(&pipe_crc->lock);
4160                 entries = pipe_crc->entries;
4161                 pipe_crc->entries = NULL;
4162                 pipe_crc->head = 0;
4163                 pipe_crc->tail = 0;
4164                 spin_unlock_irq(&pipe_crc->lock);
4165
4166                 kfree(entries);
4167
4168                 if (IS_G4X(dev_priv))
4169                         g4x_undo_pipe_scramble_reset(dev_priv, pipe);
4170                 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4171                         vlv_undo_pipe_scramble_reset(dev_priv, pipe);
4172                 else if (IS_HASWELL(dev_priv) && pipe == PIPE_A)
4173                         hsw_trans_edp_pipe_A_crc_wa(dev_priv, false);
4174
4175                 hsw_enable_ips(crtc);
4176         }
4177
4178         ret = 0;
4179
4180 out:
4181         intel_display_power_put(dev_priv, power_domain);
4182
4183         return ret;
4184 }
4185
4186 /*
4187  * Parse pipe CRC command strings:
4188  *   command: wsp* object wsp+ name wsp+ source wsp*
4189  *   object: 'pipe'
4190  *   name: (A | B | C)
4191  *   source: (none | plane1 | plane2 | pf)
4192  *   wsp: (#0x20 | #0x9 | #0xA)+
4193  *
4194  * eg.:
4195  *  "pipe A plane1"  ->  Start CRC computations on plane1 of pipe A
4196  *  "pipe A none"    ->  Stop CRC
4197  */
4198 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
4199 {
4200         int n_words = 0;
4201
4202         while (*buf) {
4203                 char *end;
4204
4205                 /* skip leading white space */
4206                 buf = skip_spaces(buf);
4207                 if (!*buf)
4208                         break;  /* end of buffer */
4209
4210                 /* find end of word */
4211                 for (end = buf; *end && !isspace(*end); end++)
4212                         ;
4213
4214                 if (n_words == max_words) {
4215                         DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4216                                          max_words);
4217                         return -EINVAL; /* ran out of words[] before bytes */
4218                 }
4219
4220                 if (*end)
4221                         *end++ = '\0';
4222                 words[n_words++] = buf;
4223                 buf = end;
4224         }
4225
4226         return n_words;
4227 }
4228
4229 enum intel_pipe_crc_object {
4230         PIPE_CRC_OBJECT_PIPE,
4231 };
4232
4233 static const char * const pipe_crc_objects[] = {
4234         "pipe",
4235 };
4236
4237 static int
4238 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
4239 {
4240         int i;
4241
4242         for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
4243                 if (!strcmp(buf, pipe_crc_objects[i])) {
4244                         *o = i;
4245                         return 0;
4246                     }
4247
4248         return -EINVAL;
4249 }
4250
4251 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
4252 {
4253         const char name = buf[0];
4254
4255         if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
4256                 return -EINVAL;
4257
4258         *pipe = name - 'A';
4259
4260         return 0;
4261 }
4262
4263 static int
4264 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
4265 {
4266         int i;
4267
4268         for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
4269                 if (!strcmp(buf, pipe_crc_sources[i])) {
4270                         *s = i;
4271                         return 0;
4272                     }
4273
4274         return -EINVAL;
4275 }
4276
4277 static int display_crc_ctl_parse(struct drm_i915_private *dev_priv,
4278                                  char *buf, size_t len)
4279 {
4280 #define N_WORDS 3
4281         int n_words;
4282         char *words[N_WORDS];
4283         enum pipe pipe;
4284         enum intel_pipe_crc_object object;
4285         enum intel_pipe_crc_source source;
4286
4287         n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
4288         if (n_words != N_WORDS) {
4289                 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4290                                  N_WORDS);
4291                 return -EINVAL;
4292         }
4293
4294         if (display_crc_ctl_parse_object(words[0], &object) < 0) {
4295                 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
4296                 return -EINVAL;
4297         }
4298
4299         if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
4300                 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
4301                 return -EINVAL;
4302         }
4303
4304         if (display_crc_ctl_parse_source(words[2], &source) < 0) {
4305                 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
4306                 return -EINVAL;
4307         }
4308
4309         return pipe_crc_set_source(dev_priv, pipe, source);
4310 }
4311
4312 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
4313                                      size_t len, loff_t *offp)
4314 {
4315         struct seq_file *m = file->private_data;
4316         struct drm_i915_private *dev_priv = m->private;
4317         char *tmpbuf;
4318         int ret;
4319
4320         if (len == 0)
4321                 return 0;
4322
4323         if (len > PAGE_SIZE - 1) {
4324                 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4325                                  PAGE_SIZE);
4326                 return -E2BIG;
4327         }
4328
4329         tmpbuf = kmalloc(len + 1, GFP_KERNEL);
4330         if (!tmpbuf)
4331                 return -ENOMEM;
4332
4333         if (copy_from_user(tmpbuf, ubuf, len)) {
4334                 ret = -EFAULT;
4335                 goto out;
4336         }
4337         tmpbuf[len] = '\0';
4338
4339         ret = display_crc_ctl_parse(dev_priv, tmpbuf, len);
4340
4341 out:
4342         kfree(tmpbuf);
4343         if (ret < 0)
4344                 return ret;
4345
4346         *offp += len;
4347         return len;
4348 }
4349
4350 static const struct file_operations i915_display_crc_ctl_fops = {
4351         .owner = THIS_MODULE,
4352         .open = display_crc_ctl_open,
4353         .read = seq_read,
4354         .llseek = seq_lseek,
4355         .release = single_release,
4356         .write = display_crc_ctl_write
4357 };
4358
4359 static ssize_t i915_displayport_test_active_write(struct file *file,
4360                                                   const char __user *ubuf,
4361                                                   size_t len, loff_t *offp)
4362 {
4363         char *input_buffer;
4364         int status = 0;
4365         struct drm_device *dev;
4366         struct drm_connector *connector;
4367         struct list_head *connector_list;
4368         struct intel_dp *intel_dp;
4369         int val = 0;
4370
4371         dev = ((struct seq_file *)file->private_data)->private;
4372
4373         connector_list = &dev->mode_config.connector_list;
4374
4375         if (len == 0)
4376                 return 0;
4377
4378         input_buffer = kmalloc(len + 1, GFP_KERNEL);
4379         if (!input_buffer)
4380                 return -ENOMEM;
4381
4382         if (copy_from_user(input_buffer, ubuf, len)) {
4383                 status = -EFAULT;
4384                 goto out;
4385         }
4386
4387         input_buffer[len] = '\0';
4388         DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4389
4390         list_for_each_entry(connector, connector_list, head) {
4391                 if (connector->connector_type !=
4392                     DRM_MODE_CONNECTOR_DisplayPort)
4393                         continue;
4394
4395                 if (connector->status == connector_status_connected &&
4396                     connector->encoder != NULL) {
4397                         intel_dp = enc_to_intel_dp(connector->encoder);
4398                         status = kstrtoint(input_buffer, 10, &val);
4399                         if (status < 0)
4400                                 goto out;
4401                         DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4402                         /* To prevent erroneous activation of the compliance
4403                          * testing code, only accept an actual value of 1 here
4404                          */
4405                         if (val == 1)
4406                                 intel_dp->compliance_test_active = 1;
4407                         else
4408                                 intel_dp->compliance_test_active = 0;
4409                 }
4410         }
4411 out:
4412         kfree(input_buffer);
4413         if (status < 0)
4414                 return status;
4415
4416         *offp += len;
4417         return len;
4418 }
4419
4420 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4421 {
4422         struct drm_device *dev = m->private;
4423         struct drm_connector *connector;
4424         struct list_head *connector_list = &dev->mode_config.connector_list;
4425         struct intel_dp *intel_dp;
4426
4427         list_for_each_entry(connector, connector_list, head) {
4428                 if (connector->connector_type !=
4429                     DRM_MODE_CONNECTOR_DisplayPort)
4430                         continue;
4431
4432                 if (connector->status == connector_status_connected &&
4433                     connector->encoder != NULL) {
4434                         intel_dp = enc_to_intel_dp(connector->encoder);
4435                         if (intel_dp->compliance_test_active)
4436                                 seq_puts(m, "1");
4437                         else
4438                                 seq_puts(m, "0");
4439                 } else
4440                         seq_puts(m, "0");
4441         }
4442
4443         return 0;
4444 }
4445
4446 static int i915_displayport_test_active_open(struct inode *inode,
4447                                              struct file *file)
4448 {
4449         struct drm_i915_private *dev_priv = inode->i_private;
4450
4451         return single_open(file, i915_displayport_test_active_show,
4452                            &dev_priv->drm);
4453 }
4454
4455 static const struct file_operations i915_displayport_test_active_fops = {
4456         .owner = THIS_MODULE,
4457         .open = i915_displayport_test_active_open,
4458         .read = seq_read,
4459         .llseek = seq_lseek,
4460         .release = single_release,
4461         .write = i915_displayport_test_active_write
4462 };
4463
4464 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4465 {
4466         struct drm_device *dev = m->private;
4467         struct drm_connector *connector;
4468         struct list_head *connector_list = &dev->mode_config.connector_list;
4469         struct intel_dp *intel_dp;
4470
4471         list_for_each_entry(connector, connector_list, head) {
4472                 if (connector->connector_type !=
4473                     DRM_MODE_CONNECTOR_DisplayPort)
4474                         continue;
4475
4476                 if (connector->status == connector_status_connected &&
4477                     connector->encoder != NULL) {
4478                         intel_dp = enc_to_intel_dp(connector->encoder);
4479                         seq_printf(m, "%lx", intel_dp->compliance_test_data);
4480                 } else
4481                         seq_puts(m, "0");
4482         }
4483
4484         return 0;
4485 }
4486 static int i915_displayport_test_data_open(struct inode *inode,
4487                                            struct file *file)
4488 {
4489         struct drm_i915_private *dev_priv = inode->i_private;
4490
4491         return single_open(file, i915_displayport_test_data_show,
4492                            &dev_priv->drm);
4493 }
4494
4495 static const struct file_operations i915_displayport_test_data_fops = {
4496         .owner = THIS_MODULE,
4497         .open = i915_displayport_test_data_open,
4498         .read = seq_read,
4499         .llseek = seq_lseek,
4500         .release = single_release
4501 };
4502
4503 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4504 {
4505         struct drm_device *dev = m->private;
4506         struct drm_connector *connector;
4507         struct list_head *connector_list = &dev->mode_config.connector_list;
4508         struct intel_dp *intel_dp;
4509
4510         list_for_each_entry(connector, connector_list, head) {
4511                 if (connector->connector_type !=
4512                     DRM_MODE_CONNECTOR_DisplayPort)
4513                         continue;
4514
4515                 if (connector->status == connector_status_connected &&
4516                     connector->encoder != NULL) {
4517                         intel_dp = enc_to_intel_dp(connector->encoder);
4518                         seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4519                 } else
4520                         seq_puts(m, "0");
4521         }
4522
4523         return 0;
4524 }
4525
4526 static int i915_displayport_test_type_open(struct inode *inode,
4527                                        struct file *file)
4528 {
4529         struct drm_i915_private *dev_priv = inode->i_private;
4530
4531         return single_open(file, i915_displayport_test_type_show,
4532                            &dev_priv->drm);
4533 }
4534
4535 static const struct file_operations i915_displayport_test_type_fops = {
4536         .owner = THIS_MODULE,
4537         .open = i915_displayport_test_type_open,
4538         .read = seq_read,
4539         .llseek = seq_lseek,
4540         .release = single_release
4541 };
4542
4543 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
4544 {
4545         struct drm_i915_private *dev_priv = m->private;
4546         struct drm_device *dev = &dev_priv->drm;
4547         int level;
4548         int num_levels;
4549
4550         if (IS_CHERRYVIEW(dev_priv))
4551                 num_levels = 3;
4552         else if (IS_VALLEYVIEW(dev_priv))
4553                 num_levels = 1;
4554         else
4555                 num_levels = ilk_wm_max_level(dev) + 1;
4556
4557         drm_modeset_lock_all(dev);
4558
4559         for (level = 0; level < num_levels; level++) {
4560                 unsigned int latency = wm[level];
4561
4562                 /*
4563                  * - WM1+ latency values in 0.5us units
4564                  * - latencies are in us on gen9/vlv/chv
4565                  */
4566                 if (INTEL_GEN(dev_priv) >= 9 || IS_VALLEYVIEW(dev_priv) ||
4567                     IS_CHERRYVIEW(dev_priv))
4568                         latency *= 10;
4569                 else if (level > 0)
4570                         latency *= 5;
4571
4572                 seq_printf(m, "WM%d %u (%u.%u usec)\n",
4573                            level, wm[level], latency / 10, latency % 10);
4574         }
4575
4576         drm_modeset_unlock_all(dev);
4577 }
4578
4579 static int pri_wm_latency_show(struct seq_file *m, void *data)
4580 {
4581         struct drm_i915_private *dev_priv = m->private;
4582         const uint16_t *latencies;
4583
4584         if (INTEL_GEN(dev_priv) >= 9)
4585                 latencies = dev_priv->wm.skl_latency;
4586         else
4587                 latencies = dev_priv->wm.pri_latency;
4588
4589         wm_latency_show(m, latencies);
4590
4591         return 0;
4592 }
4593
4594 static int spr_wm_latency_show(struct seq_file *m, void *data)
4595 {
4596         struct drm_i915_private *dev_priv = m->private;
4597         const uint16_t *latencies;
4598
4599         if (INTEL_GEN(dev_priv) >= 9)
4600                 latencies = dev_priv->wm.skl_latency;
4601         else
4602                 latencies = dev_priv->wm.spr_latency;
4603
4604         wm_latency_show(m, latencies);
4605
4606         return 0;
4607 }
4608
4609 static int cur_wm_latency_show(struct seq_file *m, void *data)
4610 {
4611         struct drm_i915_private *dev_priv = m->private;
4612         const uint16_t *latencies;
4613
4614         if (INTEL_GEN(dev_priv) >= 9)
4615                 latencies = dev_priv->wm.skl_latency;
4616         else
4617                 latencies = dev_priv->wm.cur_latency;
4618
4619         wm_latency_show(m, latencies);
4620
4621         return 0;
4622 }
4623
4624 static int pri_wm_latency_open(struct inode *inode, struct file *file)
4625 {
4626         struct drm_i915_private *dev_priv = inode->i_private;
4627
4628         if (INTEL_GEN(dev_priv) < 5)
4629                 return -ENODEV;
4630
4631         return single_open(file, pri_wm_latency_show, dev_priv);
4632 }
4633
4634 static int spr_wm_latency_open(struct inode *inode, struct file *file)
4635 {
4636         struct drm_i915_private *dev_priv = inode->i_private;
4637
4638         if (HAS_GMCH_DISPLAY(dev_priv))
4639                 return -ENODEV;
4640
4641         return single_open(file, spr_wm_latency_show, dev_priv);
4642 }
4643
4644 static int cur_wm_latency_open(struct inode *inode, struct file *file)
4645 {
4646         struct drm_i915_private *dev_priv = inode->i_private;
4647
4648         if (HAS_GMCH_DISPLAY(dev_priv))
4649                 return -ENODEV;
4650
4651         return single_open(file, cur_wm_latency_show, dev_priv);
4652 }
4653
4654 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
4655                                 size_t len, loff_t *offp, uint16_t wm[8])
4656 {
4657         struct seq_file *m = file->private_data;
4658         struct drm_i915_private *dev_priv = m->private;
4659         struct drm_device *dev = &dev_priv->drm;
4660         uint16_t new[8] = { 0 };
4661         int num_levels;
4662         int level;
4663         int ret;
4664         char tmp[32];
4665
4666         if (IS_CHERRYVIEW(dev_priv))
4667                 num_levels = 3;
4668         else if (IS_VALLEYVIEW(dev_priv))
4669                 num_levels = 1;
4670         else
4671                 num_levels = ilk_wm_max_level(dev) + 1;
4672
4673         if (len >= sizeof(tmp))
4674                 return -EINVAL;
4675
4676         if (copy_from_user(tmp, ubuf, len))
4677                 return -EFAULT;
4678
4679         tmp[len] = '\0';
4680
4681         ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4682                      &new[0], &new[1], &new[2], &new[3],
4683                      &new[4], &new[5], &new[6], &new[7]);
4684         if (ret != num_levels)
4685                 return -EINVAL;
4686
4687         drm_modeset_lock_all(dev);
4688
4689         for (level = 0; level < num_levels; level++)
4690                 wm[level] = new[level];
4691
4692         drm_modeset_unlock_all(dev);
4693
4694         return len;
4695 }
4696
4697
4698 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4699                                     size_t len, loff_t *offp)
4700 {
4701         struct seq_file *m = file->private_data;
4702         struct drm_i915_private *dev_priv = m->private;
4703         uint16_t *latencies;
4704
4705         if (INTEL_GEN(dev_priv) >= 9)
4706                 latencies = dev_priv->wm.skl_latency;
4707         else
4708                 latencies = dev_priv->wm.pri_latency;
4709
4710         return wm_latency_write(file, ubuf, len, offp, latencies);
4711 }
4712
4713 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4714                                     size_t len, loff_t *offp)
4715 {
4716         struct seq_file *m = file->private_data;
4717         struct drm_i915_private *dev_priv = m->private;
4718         uint16_t *latencies;
4719
4720         if (INTEL_GEN(dev_priv) >= 9)
4721                 latencies = dev_priv->wm.skl_latency;
4722         else
4723                 latencies = dev_priv->wm.spr_latency;
4724
4725         return wm_latency_write(file, ubuf, len, offp, latencies);
4726 }
4727
4728 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4729                                     size_t len, loff_t *offp)
4730 {
4731         struct seq_file *m = file->private_data;
4732         struct drm_i915_private *dev_priv = m->private;
4733         uint16_t *latencies;
4734
4735         if (INTEL_GEN(dev_priv) >= 9)
4736                 latencies = dev_priv->wm.skl_latency;
4737         else
4738                 latencies = dev_priv->wm.cur_latency;
4739
4740         return wm_latency_write(file, ubuf, len, offp, latencies);
4741 }
4742
4743 static const struct file_operations i915_pri_wm_latency_fops = {
4744         .owner = THIS_MODULE,
4745         .open = pri_wm_latency_open,
4746         .read = seq_read,
4747         .llseek = seq_lseek,
4748         .release = single_release,
4749         .write = pri_wm_latency_write
4750 };
4751
4752 static const struct file_operations i915_spr_wm_latency_fops = {
4753         .owner = THIS_MODULE,
4754         .open = spr_wm_latency_open,
4755         .read = seq_read,
4756         .llseek = seq_lseek,
4757         .release = single_release,
4758         .write = spr_wm_latency_write
4759 };
4760
4761 static const struct file_operations i915_cur_wm_latency_fops = {
4762         .owner = THIS_MODULE,
4763         .open = cur_wm_latency_open,
4764         .read = seq_read,
4765         .llseek = seq_lseek,
4766         .release = single_release,
4767         .write = cur_wm_latency_write
4768 };
4769
4770 static int
4771 i915_wedged_get(void *data, u64 *val)
4772 {
4773         struct drm_i915_private *dev_priv = data;
4774
4775         *val = i915_terminally_wedged(&dev_priv->gpu_error);
4776
4777         return 0;
4778 }
4779
4780 static int
4781 i915_wedged_set(void *data, u64 val)
4782 {
4783         struct drm_i915_private *dev_priv = data;
4784
4785         /*
4786          * There is no safeguard against this debugfs entry colliding
4787          * with the hangcheck calling same i915_handle_error() in
4788          * parallel, causing an explosion. For now we assume that the
4789          * test harness is responsible enough not to inject gpu hangs
4790          * while it is writing to 'i915_wedged'
4791          */
4792
4793         if (i915_reset_in_progress(&dev_priv->gpu_error))
4794                 return -EAGAIN;
4795
4796         intel_runtime_pm_get(dev_priv);
4797
4798         i915_handle_error(dev_priv, val,
4799                           "Manually setting wedged to %llu", val);
4800
4801         intel_runtime_pm_put(dev_priv);
4802
4803         return 0;
4804 }
4805
4806 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4807                         i915_wedged_get, i915_wedged_set,
4808                         "%llu\n");
4809
4810 static int
4811 i915_ring_missed_irq_get(void *data, u64 *val)
4812 {
4813         struct drm_i915_private *dev_priv = data;
4814
4815         *val = dev_priv->gpu_error.missed_irq_rings;
4816         return 0;
4817 }
4818
4819 static int
4820 i915_ring_missed_irq_set(void *data, u64 val)
4821 {
4822         struct drm_i915_private *dev_priv = data;
4823         struct drm_device *dev = &dev_priv->drm;
4824         int ret;
4825
4826         /* Lock against concurrent debugfs callers */
4827         ret = mutex_lock_interruptible(&dev->struct_mutex);
4828         if (ret)
4829                 return ret;
4830         dev_priv->gpu_error.missed_irq_rings = val;
4831         mutex_unlock(&dev->struct_mutex);
4832
4833         return 0;
4834 }
4835
4836 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4837                         i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4838                         "0x%08llx\n");
4839
4840 static int
4841 i915_ring_test_irq_get(void *data, u64 *val)
4842 {
4843         struct drm_i915_private *dev_priv = data;
4844
4845         *val = dev_priv->gpu_error.test_irq_rings;
4846
4847         return 0;
4848 }
4849
4850 static int
4851 i915_ring_test_irq_set(void *data, u64 val)
4852 {
4853         struct drm_i915_private *dev_priv = data;
4854
4855         val &= INTEL_INFO(dev_priv)->ring_mask;
4856         DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4857         dev_priv->gpu_error.test_irq_rings = val;
4858
4859         return 0;
4860 }
4861
4862 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4863                         i915_ring_test_irq_get, i915_ring_test_irq_set,
4864                         "0x%08llx\n");
4865
4866 #define DROP_UNBOUND 0x1
4867 #define DROP_BOUND 0x2
4868 #define DROP_RETIRE 0x4
4869 #define DROP_ACTIVE 0x8
4870 #define DROP_ALL (DROP_UNBOUND | \
4871                   DROP_BOUND | \
4872                   DROP_RETIRE | \
4873                   DROP_ACTIVE)
4874 static int
4875 i915_drop_caches_get(void *data, u64 *val)
4876 {
4877         *val = DROP_ALL;
4878
4879         return 0;
4880 }
4881
4882 static int
4883 i915_drop_caches_set(void *data, u64 val)
4884 {
4885         struct drm_i915_private *dev_priv = data;
4886         struct drm_device *dev = &dev_priv->drm;
4887         int ret;
4888
4889         DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4890
4891         /* No need to check and wait for gpu resets, only libdrm auto-restarts
4892          * on ioctls on -EAGAIN. */
4893         ret = mutex_lock_interruptible(&dev->struct_mutex);
4894         if (ret)
4895                 return ret;
4896
4897         if (val & DROP_ACTIVE) {
4898                 ret = i915_gem_wait_for_idle(dev_priv,
4899                                              I915_WAIT_INTERRUPTIBLE |
4900                                              I915_WAIT_LOCKED);
4901                 if (ret)
4902                         goto unlock;
4903         }
4904
4905         if (val & (DROP_RETIRE | DROP_ACTIVE))
4906                 i915_gem_retire_requests(dev_priv);
4907
4908         if (val & DROP_BOUND)
4909                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4910
4911         if (val & DROP_UNBOUND)
4912                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4913
4914 unlock:
4915         mutex_unlock(&dev->struct_mutex);
4916
4917         return ret;
4918 }
4919
4920 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4921                         i915_drop_caches_get, i915_drop_caches_set,
4922                         "0x%08llx\n");
4923
4924 static int
4925 i915_max_freq_get(void *data, u64 *val)
4926 {
4927         struct drm_i915_private *dev_priv = data;
4928
4929         if (INTEL_GEN(dev_priv) < 6)
4930                 return -ENODEV;
4931
4932         *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4933         return 0;
4934 }
4935
4936 static int
4937 i915_max_freq_set(void *data, u64 val)
4938 {
4939         struct drm_i915_private *dev_priv = data;
4940         u32 hw_max, hw_min;
4941         int ret;
4942
4943         if (INTEL_GEN(dev_priv) < 6)
4944                 return -ENODEV;
4945
4946         DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4947
4948         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4949         if (ret)
4950                 return ret;
4951
4952         /*
4953          * Turbo will still be enabled, but won't go above the set value.
4954          */
4955         val = intel_freq_opcode(dev_priv, val);
4956
4957         hw_max = dev_priv->rps.max_freq;
4958         hw_min = dev_priv->rps.min_freq;
4959
4960         if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4961                 mutex_unlock(&dev_priv->rps.hw_lock);
4962                 return -EINVAL;
4963         }
4964
4965         dev_priv->rps.max_freq_softlimit = val;
4966
4967         intel_set_rps(dev_priv, val);
4968
4969         mutex_unlock(&dev_priv->rps.hw_lock);
4970
4971         return 0;
4972 }
4973
4974 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4975                         i915_max_freq_get, i915_max_freq_set,
4976                         "%llu\n");
4977
4978 static int
4979 i915_min_freq_get(void *data, u64 *val)
4980 {
4981         struct drm_i915_private *dev_priv = data;
4982
4983         if (INTEL_GEN(dev_priv) < 6)
4984                 return -ENODEV;
4985
4986         *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4987         return 0;
4988 }
4989
4990 static int
4991 i915_min_freq_set(void *data, u64 val)
4992 {
4993         struct drm_i915_private *dev_priv = data;
4994         u32 hw_max, hw_min;
4995         int ret;
4996
4997         if (INTEL_GEN(dev_priv) < 6)
4998                 return -ENODEV;
4999
5000         DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
5001
5002         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
5003         if (ret)
5004                 return ret;
5005
5006         /*
5007          * Turbo will still be enabled, but won't go below the set value.
5008          */
5009         val = intel_freq_opcode(dev_priv, val);
5010
5011         hw_max = dev_priv->rps.max_freq;
5012         hw_min = dev_priv->rps.min_freq;
5013
5014         if (val < hw_min ||
5015             val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
5016                 mutex_unlock(&dev_priv->rps.hw_lock);
5017                 return -EINVAL;
5018         }
5019
5020         dev_priv->rps.min_freq_softlimit = val;
5021
5022         intel_set_rps(dev_priv, val);
5023
5024         mutex_unlock(&dev_priv->rps.hw_lock);
5025
5026         return 0;
5027 }
5028
5029 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
5030                         i915_min_freq_get, i915_min_freq_set,
5031                         "%llu\n");
5032
5033 static int
5034 i915_cache_sharing_get(void *data, u64 *val)
5035 {
5036         struct drm_i915_private *dev_priv = data;
5037         struct drm_device *dev = &dev_priv->drm;
5038         u32 snpcr;
5039         int ret;
5040
5041         if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
5042                 return -ENODEV;
5043
5044         ret = mutex_lock_interruptible(&dev->struct_mutex);
5045         if (ret)
5046                 return ret;
5047         intel_runtime_pm_get(dev_priv);
5048
5049         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5050
5051         intel_runtime_pm_put(dev_priv);
5052         mutex_unlock(&dev->struct_mutex);
5053
5054         *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
5055
5056         return 0;
5057 }
5058
5059 static int
5060 i915_cache_sharing_set(void *data, u64 val)
5061 {
5062         struct drm_i915_private *dev_priv = data;
5063         u32 snpcr;
5064
5065         if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
5066                 return -ENODEV;
5067
5068         if (val > 3)
5069                 return -EINVAL;
5070
5071         intel_runtime_pm_get(dev_priv);
5072         DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
5073
5074         /* Update the cache sharing policy here as well */
5075         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5076         snpcr &= ~GEN6_MBC_SNPCR_MASK;
5077         snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
5078         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5079
5080         intel_runtime_pm_put(dev_priv);
5081         return 0;
5082 }
5083
5084 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
5085                         i915_cache_sharing_get, i915_cache_sharing_set,
5086                         "%llu\n");
5087
5088 static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
5089                                           struct sseu_dev_info *sseu)
5090 {
5091         int ss_max = 2;
5092         int ss;
5093         u32 sig1[ss_max], sig2[ss_max];
5094
5095         sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
5096         sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
5097         sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
5098         sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
5099
5100         for (ss = 0; ss < ss_max; ss++) {
5101                 unsigned int eu_cnt;
5102
5103                 if (sig1[ss] & CHV_SS_PG_ENABLE)
5104                         /* skip disabled subslice */
5105                         continue;
5106
5107                 sseu->slice_mask = BIT(0);
5108                 sseu->subslice_mask |= BIT(ss);
5109                 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
5110                          ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
5111                          ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
5112                          ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
5113                 sseu->eu_total += eu_cnt;
5114                 sseu->eu_per_subslice = max_t(unsigned int,
5115                                               sseu->eu_per_subslice, eu_cnt);
5116         }
5117 }
5118
5119 static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
5120                                     struct sseu_dev_info *sseu)
5121 {
5122         int s_max = 3, ss_max = 4;
5123         int s, ss;
5124         u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
5125
5126         /* BXT has a single slice and at most 3 subslices. */
5127         if (IS_BROXTON(dev_priv)) {
5128                 s_max = 1;
5129                 ss_max = 3;
5130         }
5131
5132         for (s = 0; s < s_max; s++) {
5133                 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
5134                 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
5135                 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
5136         }
5137
5138         eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
5139                      GEN9_PGCTL_SSA_EU19_ACK |
5140                      GEN9_PGCTL_SSA_EU210_ACK |
5141                      GEN9_PGCTL_SSA_EU311_ACK;
5142         eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
5143                      GEN9_PGCTL_SSB_EU19_ACK |
5144                      GEN9_PGCTL_SSB_EU210_ACK |
5145                      GEN9_PGCTL_SSB_EU311_ACK;
5146
5147         for (s = 0; s < s_max; s++) {
5148                 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
5149                         /* skip disabled slice */
5150                         continue;
5151
5152                 sseu->slice_mask |= BIT(s);
5153
5154                 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
5155                         sseu->subslice_mask =
5156                                 INTEL_INFO(dev_priv)->sseu.subslice_mask;
5157
5158                 for (ss = 0; ss < ss_max; ss++) {
5159                         unsigned int eu_cnt;
5160
5161                         if (IS_BROXTON(dev_priv)) {
5162                                 if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
5163                                         /* skip disabled subslice */
5164                                         continue;
5165
5166                                 sseu->subslice_mask |= BIT(ss);
5167                         }
5168
5169                         eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
5170                                                eu_mask[ss%2]);
5171                         sseu->eu_total += eu_cnt;
5172                         sseu->eu_per_subslice = max_t(unsigned int,
5173                                                       sseu->eu_per_subslice,
5174                                                       eu_cnt);
5175                 }
5176         }
5177 }
5178
5179 static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
5180                                          struct sseu_dev_info *sseu)
5181 {
5182         u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
5183         int s;
5184
5185         sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK;
5186
5187         if (sseu->slice_mask) {
5188                 sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask;
5189                 sseu->eu_per_subslice =
5190                                 INTEL_INFO(dev_priv)->sseu.eu_per_subslice;
5191                 sseu->eu_total = sseu->eu_per_subslice *
5192                                  sseu_subslice_total(sseu);
5193
5194                 /* subtract fused off EU(s) from enabled slice(s) */
5195                 for (s = 0; s < fls(sseu->slice_mask); s++) {
5196                         u8 subslice_7eu =
5197                                 INTEL_INFO(dev_priv)->sseu.subslice_7eu[s];
5198
5199                         sseu->eu_total -= hweight8(subslice_7eu);
5200                 }
5201         }
5202 }
5203
5204 static void i915_print_sseu_info(struct seq_file *m, bool is_available_info,
5205                                  const struct sseu_dev_info *sseu)
5206 {
5207         struct drm_i915_private *dev_priv = node_to_i915(m->private);
5208         const char *type = is_available_info ? "Available" : "Enabled";
5209
5210         seq_printf(m, "  %s Slice Mask: %04x\n", type,
5211                    sseu->slice_mask);
5212         seq_printf(m, "  %s Slice Total: %u\n", type,
5213                    hweight8(sseu->slice_mask));
5214         seq_printf(m, "  %s Subslice Total: %u\n", type,
5215                    sseu_subslice_total(sseu));
5216         seq_printf(m, "  %s Subslice Mask: %04x\n", type,
5217                    sseu->subslice_mask);
5218         seq_printf(m, "  %s Subslice Per Slice: %u\n", type,
5219                    hweight8(sseu->subslice_mask));
5220         seq_printf(m, "  %s EU Total: %u\n", type,
5221                    sseu->eu_total);
5222         seq_printf(m, "  %s EU Per Subslice: %u\n", type,
5223                    sseu->eu_per_subslice);
5224
5225         if (!is_available_info)
5226                 return;
5227
5228         seq_printf(m, "  Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv)));
5229         if (HAS_POOLED_EU(dev_priv))
5230                 seq_printf(m, "  Min EU in pool: %u\n", sseu->min_eu_in_pool);
5231
5232         seq_printf(m, "  Has Slice Power Gating: %s\n",
5233                    yesno(sseu->has_slice_pg));
5234         seq_printf(m, "  Has Subslice Power Gating: %s\n",
5235                    yesno(sseu->has_subslice_pg));
5236         seq_printf(m, "  Has EU Power Gating: %s\n",
5237                    yesno(sseu->has_eu_pg));
5238 }
5239
5240 static int i915_sseu_status(struct seq_file *m, void *unused)
5241 {
5242         struct drm_i915_private *dev_priv = node_to_i915(m->private);
5243         struct sseu_dev_info sseu;
5244
5245         if (INTEL_GEN(dev_priv) < 8)
5246                 return -ENODEV;
5247
5248         seq_puts(m, "SSEU Device Info\n");
5249         i915_print_sseu_info(m, true, &INTEL_INFO(dev_priv)->sseu);
5250
5251         seq_puts(m, "SSEU Device Status\n");
5252         memset(&sseu, 0, sizeof(sseu));
5253
5254         intel_runtime_pm_get(dev_priv);
5255
5256         if (IS_CHERRYVIEW(dev_priv)) {
5257                 cherryview_sseu_device_status(dev_priv, &sseu);
5258         } else if (IS_BROADWELL(dev_priv)) {
5259                 broadwell_sseu_device_status(dev_priv, &sseu);
5260         } else if (INTEL_GEN(dev_priv) >= 9) {
5261                 gen9_sseu_device_status(dev_priv, &sseu);
5262         }
5263
5264         intel_runtime_pm_put(dev_priv);
5265
5266         i915_print_sseu_info(m, false, &sseu);
5267
5268         return 0;
5269 }
5270
5271 static int i915_forcewake_open(struct inode *inode, struct file *file)
5272 {
5273         struct drm_i915_private *dev_priv = inode->i_private;
5274
5275         if (INTEL_GEN(dev_priv) < 6)
5276                 return 0;
5277
5278         intel_runtime_pm_get(dev_priv);
5279         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5280
5281         return 0;
5282 }
5283
5284 static int i915_forcewake_release(struct inode *inode, struct file *file)
5285 {
5286         struct drm_i915_private *dev_priv = inode->i_private;
5287
5288         if (INTEL_GEN(dev_priv) < 6)
5289                 return 0;
5290
5291         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5292         intel_runtime_pm_put(dev_priv);
5293
5294         return 0;
5295 }
5296
5297 static const struct file_operations i915_forcewake_fops = {
5298         .owner = THIS_MODULE,
5299         .open = i915_forcewake_open,
5300         .release = i915_forcewake_release,
5301 };
5302
5303 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5304 {
5305         struct dentry *ent;
5306
5307         ent = debugfs_create_file("i915_forcewake_user",
5308                                   S_IRUSR,
5309                                   root, to_i915(minor->dev),
5310                                   &i915_forcewake_fops);
5311         if (!ent)
5312                 return -ENOMEM;
5313
5314         return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
5315 }
5316
5317 static int i915_debugfs_create(struct dentry *root,
5318                                struct drm_minor *minor,
5319                                const char *name,
5320                                const struct file_operations *fops)
5321 {
5322         struct dentry *ent;
5323
5324         ent = debugfs_create_file(name,
5325                                   S_IRUGO | S_IWUSR,
5326                                   root, to_i915(minor->dev),
5327                                   fops);
5328         if (!ent)
5329                 return -ENOMEM;
5330
5331         return drm_add_fake_info_node(minor, ent, fops);
5332 }
5333
5334 static const struct drm_info_list i915_debugfs_list[] = {
5335         {"i915_capabilities", i915_capabilities, 0},
5336         {"i915_gem_objects", i915_gem_object_info, 0},
5337         {"i915_gem_gtt", i915_gem_gtt_info, 0},
5338         {"i915_gem_pin_display", i915_gem_gtt_info, 0, (void *)1},
5339         {"i915_gem_stolen", i915_gem_stolen_list_info },
5340         {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
5341         {"i915_gem_request", i915_gem_request_info, 0},
5342         {"i915_gem_seqno", i915_gem_seqno_info, 0},
5343         {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
5344         {"i915_gem_interrupt", i915_interrupt_info, 0},
5345         {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5346         {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5347         {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
5348         {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
5349         {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
5350         {"i915_guc_info", i915_guc_info, 0},
5351         {"i915_guc_load_status", i915_guc_load_status_info, 0},
5352         {"i915_guc_log_dump", i915_guc_log_dump, 0},
5353         {"i915_frequency_info", i915_frequency_info, 0},
5354         {"i915_hangcheck_info", i915_hangcheck_info, 0},
5355         {"i915_drpc_info", i915_drpc_info, 0},
5356         {"i915_emon_status", i915_emon_status, 0},
5357         {"i915_ring_freq_table", i915_ring_freq_table, 0},
5358         {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
5359         {"i915_fbc_status", i915_fbc_status, 0},
5360         {"i915_ips_status", i915_ips_status, 0},
5361         {"i915_sr_status", i915_sr_status, 0},
5362         {"i915_opregion", i915_opregion, 0},
5363         {"i915_vbt", i915_vbt, 0},
5364         {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
5365         {"i915_context_status", i915_context_status, 0},
5366         {"i915_dump_lrc", i915_dump_lrc, 0},
5367         {"i915_forcewake_domains", i915_forcewake_domains, 0},
5368         {"i915_swizzle_info", i915_swizzle_info, 0},
5369         {"i915_ppgtt_info", i915_ppgtt_info, 0},
5370         {"i915_llc", i915_llc, 0},
5371         {"i915_edp_psr_status", i915_edp_psr_status, 0},
5372         {"i915_sink_crc_eDP1", i915_sink_crc, 0},
5373         {"i915_energy_uJ", i915_energy_uJ, 0},
5374         {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
5375         {"i915_power_domain_info", i915_power_domain_info, 0},
5376         {"i915_dmc_info", i915_dmc_info, 0},
5377         {"i915_display_info", i915_display_info, 0},
5378         {"i915_engine_info", i915_engine_info, 0},
5379         {"i915_semaphore_status", i915_semaphore_status, 0},
5380         {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
5381         {"i915_dp_mst_info", i915_dp_mst_info, 0},
5382         {"i915_wa_registers", i915_wa_registers, 0},
5383         {"i915_ddb_info", i915_ddb_info, 0},
5384         {"i915_sseu_status", i915_sseu_status, 0},
5385         {"i915_drrs_status", i915_drrs_status, 0},
5386         {"i915_rps_boost_info", i915_rps_boost_info, 0},
5387 };
5388 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5389
5390 static const struct i915_debugfs_files {
5391         const char *name;
5392         const struct file_operations *fops;
5393 } i915_debugfs_files[] = {
5394         {"i915_wedged", &i915_wedged_fops},
5395         {"i915_max_freq", &i915_max_freq_fops},
5396         {"i915_min_freq", &i915_min_freq_fops},
5397         {"i915_cache_sharing", &i915_cache_sharing_fops},
5398         {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5399         {"i915_ring_test_irq", &i915_ring_test_irq_fops},
5400         {"i915_gem_drop_caches", &i915_drop_caches_fops},
5401         {"i915_error_state", &i915_error_state_fops},
5402         {"i915_next_seqno", &i915_next_seqno_fops},
5403         {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
5404         {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5405         {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5406         {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
5407         {"i915_fbc_false_color", &i915_fbc_fc_fops},
5408         {"i915_dp_test_data", &i915_displayport_test_data_fops},
5409         {"i915_dp_test_type", &i915_displayport_test_type_fops},
5410         {"i915_dp_test_active", &i915_displayport_test_active_fops}
5411 };
5412
5413 void intel_display_crc_init(struct drm_i915_private *dev_priv)
5414 {
5415         enum pipe pipe;
5416
5417         for_each_pipe(dev_priv, pipe) {
5418                 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
5419
5420                 pipe_crc->opened = false;
5421                 spin_lock_init(&pipe_crc->lock);
5422                 init_waitqueue_head(&pipe_crc->wq);
5423         }
5424 }
5425
5426 int i915_debugfs_register(struct drm_i915_private *dev_priv)
5427 {
5428         struct drm_minor *minor = dev_priv->drm.primary;
5429         int ret, i;
5430
5431         ret = i915_forcewake_create(minor->debugfs_root, minor);
5432         if (ret)
5433                 return ret;
5434
5435         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5436                 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5437                 if (ret)
5438                         return ret;
5439         }
5440
5441         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5442                 ret = i915_debugfs_create(minor->debugfs_root, minor,
5443                                           i915_debugfs_files[i].name,
5444                                           i915_debugfs_files[i].fops);
5445                 if (ret)
5446                         return ret;
5447         }
5448
5449         return drm_debugfs_create_files(i915_debugfs_list,
5450                                         I915_DEBUGFS_ENTRIES,
5451                                         minor->debugfs_root, minor);
5452 }
5453
5454 void i915_debugfs_unregister(struct drm_i915_private *dev_priv)
5455 {
5456         struct drm_minor *minor = dev_priv->drm.primary;
5457         int i;
5458
5459         drm_debugfs_remove_files(i915_debugfs_list,
5460                                  I915_DEBUGFS_ENTRIES, minor);
5461
5462         drm_debugfs_remove_files((struct drm_info_list *)&i915_forcewake_fops,
5463                                  1, minor);
5464
5465         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5466                 struct drm_info_list *info_list =
5467                         (struct drm_info_list *)&i915_pipe_crc_data[i];
5468
5469                 drm_debugfs_remove_files(info_list, 1, minor);
5470         }
5471
5472         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5473                 struct drm_info_list *info_list =
5474                         (struct drm_info_list *)i915_debugfs_files[i].fops;
5475
5476                 drm_debugfs_remove_files(info_list, 1, minor);
5477         }
5478 }
5479
5480 struct dpcd_block {
5481         /* DPCD dump start address. */
5482         unsigned int offset;
5483         /* DPCD dump end address, inclusive. If unset, .size will be used. */
5484         unsigned int end;
5485         /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5486         size_t size;
5487         /* Only valid for eDP. */
5488         bool edp;
5489 };
5490
5491 static const struct dpcd_block i915_dpcd_debug[] = {
5492         { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5493         { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5494         { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5495         { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5496         { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5497         { .offset = DP_SET_POWER },
5498         { .offset = DP_EDP_DPCD_REV },
5499         { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5500         { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5501         { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5502 };
5503
5504 static int i915_dpcd_show(struct seq_file *m, void *data)
5505 {
5506         struct drm_connector *connector = m->private;
5507         struct intel_dp *intel_dp =
5508                 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5509         uint8_t buf[16];
5510         ssize_t err;
5511         int i;
5512
5513         if (connector->status != connector_status_connected)
5514                 return -ENODEV;
5515
5516         for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5517                 const struct dpcd_block *b = &i915_dpcd_debug[i];
5518                 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5519
5520                 if (b->edp &&
5521                     connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5522                         continue;
5523
5524                 /* low tech for now */
5525                 if (WARN_ON(size > sizeof(buf)))
5526                         continue;
5527
5528                 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5529                 if (err <= 0) {
5530                         DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5531                                   size, b->offset, err);
5532                         continue;
5533                 }
5534
5535                 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
5536         }
5537
5538         return 0;
5539 }
5540
5541 static int i915_dpcd_open(struct inode *inode, struct file *file)
5542 {
5543         return single_open(file, i915_dpcd_show, inode->i_private);
5544 }
5545
5546 static const struct file_operations i915_dpcd_fops = {
5547         .owner = THIS_MODULE,
5548         .open = i915_dpcd_open,
5549         .read = seq_read,
5550         .llseek = seq_lseek,
5551         .release = single_release,
5552 };
5553
5554 static int i915_panel_show(struct seq_file *m, void *data)
5555 {
5556         struct drm_connector *connector = m->private;
5557         struct intel_dp *intel_dp =
5558                 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5559
5560         if (connector->status != connector_status_connected)
5561                 return -ENODEV;
5562
5563         seq_printf(m, "Panel power up delay: %d\n",
5564                    intel_dp->panel_power_up_delay);
5565         seq_printf(m, "Panel power down delay: %d\n",
5566                    intel_dp->panel_power_down_delay);
5567         seq_printf(m, "Backlight on delay: %d\n",
5568                    intel_dp->backlight_on_delay);
5569         seq_printf(m, "Backlight off delay: %d\n",
5570                    intel_dp->backlight_off_delay);
5571
5572         return 0;
5573 }
5574
5575 static int i915_panel_open(struct inode *inode, struct file *file)
5576 {
5577         return single_open(file, i915_panel_show, inode->i_private);
5578 }
5579
5580 static const struct file_operations i915_panel_fops = {
5581         .owner = THIS_MODULE,
5582         .open = i915_panel_open,
5583         .read = seq_read,
5584         .llseek = seq_lseek,
5585         .release = single_release,
5586 };
5587
5588 /**
5589  * i915_debugfs_connector_add - add i915 specific connector debugfs files
5590  * @connector: pointer to a registered drm_connector
5591  *
5592  * Cleanup will be done by drm_connector_unregister() through a call to
5593  * drm_debugfs_connector_remove().
5594  *
5595  * Returns 0 on success, negative error codes on error.
5596  */
5597 int i915_debugfs_connector_add(struct drm_connector *connector)
5598 {
5599         struct dentry *root = connector->debugfs_entry;
5600
5601         /* The connector must have been registered beforehands. */
5602         if (!root)
5603                 return -ENODEV;
5604
5605         if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5606             connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5607                 debugfs_create_file("i915_dpcd", S_IRUGO, root,
5608                                     connector, &i915_dpcd_fops);
5609
5610         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5611                 debugfs_create_file("i915_panel_timings", S_IRUGO, root,
5612                                     connector, &i915_panel_fops);
5613
5614         return 0;
5615 }