drivers/gpu/drm/i915/i915_debugfs.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *
  27  */
  28
  29 #include <linux/seq_file.h>
  30 #include <linux/circ_buf.h>
  31 #include <linux/ctype.h>
  32 #include <linux/debugfs.h>
  33 #include <linux/slab.h>
  34 #include <linux/export.h>
  35 #include <linux/list_sort.h>
  36 #include <asm/msr-index.h>
  37 #include <drm/drmP.h>
  38 #include "intel_drv.h"
  39 #include "intel_ringbuffer.h"
  40 #include <drm/i915_drm.h>
  41 #include "i915_drv.h"
  42
  43 static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
  44 {
  45         return to_i915(node->minor->dev);
  46 }
  47
  48 /* As the drm_debugfs_init() routines are called before dev->dev_private is
  49  * allocated we need to hook into the minor for release. */
  50 static int
  51 drm_add_fake_info_node(struct drm_minor *minor,
  52                        struct dentry *ent,
  53                        const void *key)
  54 {
  55         struct drm_info_node *node;
  56
  57         node = kmalloc(sizeof(*node), GFP_KERNEL);
  58         if (node == NULL) {
  59                 debugfs_remove(ent);
  60                 return -ENOMEM;
  61         }
  62
  63         node->minor = minor;
  64         node->dent = ent;
  65         node->info_ent = (void *)key;
  66
  67         mutex_lock(&minor->debugfs_lock);
  68         list_add(&node->list, &minor->debugfs_list);
  69         mutex_unlock(&minor->debugfs_lock);
  70
  71         return 0;
  72 }
  73
  74 static int i915_capabilities(struct seq_file *m, void *data)
  75 {
  76         struct drm_i915_private *dev_priv = node_to_i915(m->private);
  77         const struct intel_device_info *info = INTEL_INFO(dev_priv);
  78
  79         seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv));
  80         seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv));
  81 #define PRINT_FLAG(x)  seq_printf(m, #x ": %s\n", yesno(info->x))
  82         DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
  83 #undef PRINT_FLAG
  84
  85         return 0;
  86 }
  87
  88 static char get_active_flag(struct drm_i915_gem_object *obj)
  89 {
  90         return i915_gem_object_is_active(obj) ? '*' : ' ';
  91 }
  92
  93 static char get_pin_flag(struct drm_i915_gem_object *obj)
  94 {
  95         return obj->pin_display ? 'p' : ' ';
  96 }
  97
  98 static char get_tiling_flag(struct drm_i915_gem_object *obj)
  99 {
 100         switch (i915_gem_object_get_tiling(obj)) {
 101         default:
 102         case I915_TILING_NONE: return ' ';
 103         case I915_TILING_X: return 'X';
 104         case I915_TILING_Y: return 'Y';
 105         }
 106 }
 107
 108 static char get_global_flag(struct drm_i915_gem_object *obj)
 109 {
 110         return !list_empty(&obj->userfault_link) ? 'g' : ' ';
 111 }
 112
 113 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
 114 {
 115         return obj->mapping ? 'M' : ' ';
 116 }
 117
 118 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
 119 {
 120         u64 size = 0;
 121         struct i915_vma *vma;
 122
 123         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 124                 if (i915_vma_is_ggtt(vma) && drm_mm_node_allocated(&vma->node))
 125                         size += vma->node.size;
 126         }
 127
 128         return size;
 129 }
 130
 131 static void
 132 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
 133 {
 134         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
 135         struct intel_engine_cs *engine;
 136         struct i915_vma *vma;
 137         unsigned int frontbuffer_bits;
 138         int pin_count = 0;
 139         enum intel_engine_id id;
 140
 141         lockdep_assert_held(&obj->base.dev->struct_mutex);
 142
 143         seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x [ ",
 144                    &obj->base,
 145                    get_active_flag(obj),
 146                    get_pin_flag(obj),
 147                    get_tiling_flag(obj),
 148                    get_global_flag(obj),
 149                    get_pin_mapped_flag(obj),
 150                    obj->base.size / 1024,
 151                    obj->base.read_domains,
 152                    obj->base.write_domain);
 153         for_each_engine(engine, dev_priv, id)
 154                 seq_printf(m, "%x ",
 155                            i915_gem_active_get_seqno(&obj->last_read[id],
 156                                                      &obj->base.dev->struct_mutex));
 157         seq_printf(m, "] %x %s%s%s",
 158                    i915_gem_active_get_seqno(&obj->last_write,
 159                                              &obj->base.dev->struct_mutex),
 160                    i915_cache_level_str(dev_priv, obj->cache_level),
 161                    obj->dirty ? " dirty" : "",
 162                    obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
 163         if (obj->base.name)
 164                 seq_printf(m, " (name: %d)", obj->base.name);
 165         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 166                 if (i915_vma_is_pinned(vma))
 167                         pin_count++;
 168         }
 169         seq_printf(m, " (pinned x %d)", pin_count);
 170         if (obj->pin_display)
 171                 seq_printf(m, " (display)");
 172         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 173                 if (!drm_mm_node_allocated(&vma->node))
 174                         continue;
 175
 176                 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
 177                            i915_vma_is_ggtt(vma) ? "g" : "pp",
 178                            vma->node.start, vma->node.size);
 179                 if (i915_vma_is_ggtt(vma))
 180                         seq_printf(m, ", type: %u", vma->ggtt_view.type);
 181                 if (vma->fence)
 182                         seq_printf(m, " , fence: %d%s",
 183                                    vma->fence->id,
 184                                    i915_gem_active_isset(&vma->last_fence) ? "*" : "");
 185                 seq_puts(m, ")");
 186         }
 187         if (obj->stolen)
 188                 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
 189
 190         engine = i915_gem_active_get_engine(&obj->last_write,
 191                                             &dev_priv->drm.struct_mutex);
 192         if (engine)
 193                 seq_printf(m, " (%s)", engine->name);
 194
 195         frontbuffer_bits = atomic_read(&obj->frontbuffer_bits);
 196         if (frontbuffer_bits)
 197                 seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits);
 198 }
 199
 200 static int obj_rank_by_stolen(void *priv,
 201                               struct list_head *A, struct list_head *B)
 202 {
 203         struct drm_i915_gem_object *a =
 204                 container_of(A, struct drm_i915_gem_object, obj_exec_link);
 205         struct drm_i915_gem_object *b =
 206                 container_of(B, struct drm_i915_gem_object, obj_exec_link);
 207
 208         if (a->stolen->start < b->stolen->start)
 209                 return -1;
 210         if (a->stolen->start > b->stolen->start)
 211                 return 1;
 212         return 0;
 213 }
 214
 215 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
 216 {
 217         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 218         struct drm_device *dev = &dev_priv->drm;
 219         struct drm_i915_gem_object *obj;
 220         u64 total_obj_size, total_gtt_size;
 221         LIST_HEAD(stolen);
 222         int count, ret;
 223
 224         ret = mutex_lock_interruptible(&dev->struct_mutex);
 225         if (ret)
 226                 return ret;
 227
 228         total_obj_size = total_gtt_size = count = 0;
 229         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 230                 if (obj->stolen == NULL)
 231                         continue;
 232
 233                 list_add(&obj->obj_exec_link, &stolen);
 234
 235                 total_obj_size += obj->base.size;
 236                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 237                 count++;
 238         }
 239         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 240                 if (obj->stolen == NULL)
 241                         continue;
 242
 243                 list_add(&obj->obj_exec_link, &stolen);
 244
 245                 total_obj_size += obj->base.size;
 246                 count++;
 247         }
 248         list_sort(NULL, &stolen, obj_rank_by_stolen);
 249         seq_puts(m, "Stolen:\n");
 250         while (!list_empty(&stolen)) {
 251                 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
 252                 seq_puts(m, "   ");
 253                 describe_obj(m, obj);
 254                 seq_putc(m, '\n');
 255                 list_del_init(&obj->obj_exec_link);
 256         }
 257         mutex_unlock(&dev->struct_mutex);
 258
 259         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 260                    count, total_obj_size, total_gtt_size);
 261         return 0;
 262 }
 263
 264 struct file_stats {
 265         struct drm_i915_file_private *file_priv;
 266         unsigned long count;
 267         u64 total, unbound;
 268         u64 global, shared;
 269         u64 active, inactive;
 270 };
 271
 272 static int per_file_stats(int id, void *ptr, void *data)
 273 {
 274         struct drm_i915_gem_object *obj = ptr;
 275         struct file_stats *stats = data;
 276         struct i915_vma *vma;
 277
 278         stats->count++;
 279         stats->total += obj->base.size;
 280         if (!obj->bind_count)
 281                 stats->unbound += obj->base.size;
 282         if (obj->base.name || obj->base.dma_buf)
 283                 stats->shared += obj->base.size;
 284
 285         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 286                 if (!drm_mm_node_allocated(&vma->node))
 287                         continue;
 288
 289                 if (i915_vma_is_ggtt(vma)) {
 290                         stats->global += vma->node.size;
 291                 } else {
 292                         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm);
 293
 294                         if (ppgtt->base.file != stats->file_priv)
 295                                 continue;
 296                 }
 297
 298                 if (i915_vma_is_active(vma))
 299                         stats->active += vma->node.size;
 300                 else
 301                         stats->inactive += vma->node.size;
 302         }
 303
 304         return 0;
 305 }
 306
 307 #define print_file_stats(m, name, stats) do { \
 308         if (stats.count) \
 309                 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
 310                            name, \
 311                            stats.count, \
 312                            stats.total, \
 313                            stats.active, \
 314                            stats.inactive, \
 315                            stats.global, \
 316                            stats.shared, \
 317                            stats.unbound); \
 318 } while (0)
 319
 320 static void print_batch_pool_stats(struct seq_file *m,
 321                                    struct drm_i915_private *dev_priv)
 322 {
 323         struct drm_i915_gem_object *obj;
 324         struct file_stats stats;
 325         struct intel_engine_cs *engine;
 326         enum intel_engine_id id;
 327         int j;
 328
 329         memset(&stats, 0, sizeof(stats));
 330
 331         for_each_engine(engine, dev_priv, id) {
 332                 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
 333                         list_for_each_entry(obj,
 334                                             &engine->batch_pool.cache_list[j],
 335                                             batch_pool_link)
 336                                 per_file_stats(0, obj, &stats);
 337                 }
 338         }
 339
 340         print_file_stats(m, "[k]batch pool", stats);
 341 }
 342
 343 static int per_file_ctx_stats(int id, void *ptr, void *data)
 344 {
 345         struct i915_gem_context *ctx = ptr;
 346         int n;
 347
 348         for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) {
 349                 if (ctx->engine[n].state)
 350                         per_file_stats(0, ctx->engine[n].state->obj, data);
 351                 if (ctx->engine[n].ring)
 352                         per_file_stats(0, ctx->engine[n].ring->vma->obj, data);
 353         }
 354
 355         return 0;
 356 }
 357
 358 static void print_context_stats(struct seq_file *m,
 359                                 struct drm_i915_private *dev_priv)
 360 {
 361         struct drm_device *dev = &dev_priv->drm;
 362         struct file_stats stats;
 363         struct drm_file *file;
 364
 365         memset(&stats, 0, sizeof(stats));
 366
 367         mutex_lock(&dev->struct_mutex);
 368         if (dev_priv->kernel_context)
 369                 per_file_ctx_stats(0, dev_priv->kernel_context, &stats);
 370
 371         list_for_each_entry(file, &dev->filelist, lhead) {
 372                 struct drm_i915_file_private *fpriv = file->driver_priv;
 373                 idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats);
 374         }
 375         mutex_unlock(&dev->struct_mutex);
 376
 377         print_file_stats(m, "[k]contexts", stats);
 378 }
 379
 380 static int i915_gem_object_info(struct seq_file *m, void *data)
 381 {
 382         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 383         struct drm_device *dev = &dev_priv->drm;
 384         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 385         u32 count, mapped_count, purgeable_count, dpy_count;
 386         u64 size, mapped_size, purgeable_size, dpy_size;
 387         struct drm_i915_gem_object *obj;
 388         struct drm_file *file;
 389         int ret;
 390
 391         ret = mutex_lock_interruptible(&dev->struct_mutex);
 392         if (ret)
 393                 return ret;
 394
 395         seq_printf(m, "%u objects, %llu bytes\n",
 396                    dev_priv->mm.object_count,
 397                    dev_priv->mm.object_memory);
 398
 399         size = count = 0;
 400         mapped_size = mapped_count = 0;
 401         purgeable_size = purgeable_count = 0;
 402         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 403                 size += obj->base.size;
 404                 ++count;
 405
 406                 if (obj->madv == I915_MADV_DONTNEED) {
 407                         purgeable_size += obj->base.size;
 408                         ++purgeable_count;
 409                 }
 410
 411                 if (obj->mapping) {
 412                         mapped_count++;
 413                         mapped_size += obj->base.size;
 414                 }
 415         }
 416         seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
 417
 418         size = count = dpy_size = dpy_count = 0;
 419         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 420                 size += obj->base.size;
 421                 ++count;
 422
 423                 if (obj->pin_display) {
 424                         dpy_size += obj->base.size;
 425                         ++dpy_count;
 426                 }
 427
 428                 if (obj->madv == I915_MADV_DONTNEED) {
 429                         purgeable_size += obj->base.size;
 430                         ++purgeable_count;
 431                 }
 432
 433                 if (obj->mapping) {
 434                         mapped_count++;
 435                         mapped_size += obj->base.size;
 436                 }
 437         }
 438         seq_printf(m, "%u bound objects, %llu bytes\n",
 439                    count, size);
 440         seq_printf(m, "%u purgeable objects, %llu bytes\n",
 441                    purgeable_count, purgeable_size);
 442         seq_printf(m, "%u mapped objects, %llu bytes\n",
 443                    mapped_count, mapped_size);
 444         seq_printf(m, "%u display objects (pinned), %llu bytes\n",
 445                    dpy_count, dpy_size);
 446
 447         seq_printf(m, "%llu [%llu] gtt total\n",
 448                    ggtt->base.total, ggtt->mappable_end - ggtt->base.start);
 449
 450         seq_putc(m, '\n');
 451         print_batch_pool_stats(m, dev_priv);
 452         mutex_unlock(&dev->struct_mutex);
 453
 454         mutex_lock(&dev->filelist_mutex);
 455         print_context_stats(m, dev_priv);
 456         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
 457                 struct file_stats stats;
 458                 struct drm_i915_file_private *file_priv = file->driver_priv;
 459                 struct drm_i915_gem_request *request;
 460                 struct task_struct *task;
 461
 462                 memset(&stats, 0, sizeof(stats));
 463                 stats.file_priv = file->driver_priv;
 464                 spin_lock(&file->table_lock);
 465                 idr_for_each(&file->object_idr, per_file_stats, &stats);
 466                 spin_unlock(&file->table_lock);
 467                 /*
 468                  * Although we have a valid reference on file->pid, that does
 469                  * not guarantee that the task_struct who called get_pid() is
 470                  * still alive (e.g. get_pid(current) => fork() => exit()).
 471                  * Therefore, we need to protect this ->comm access using RCU.
 472                  */
 473                 mutex_lock(&dev->struct_mutex);
 474                 request = list_first_entry_or_null(&file_priv->mm.request_list,
 475                                                    struct drm_i915_gem_request,
 476                                                    client_list);
 477                 rcu_read_lock();
 478                 task = pid_task(request && request->ctx->pid ?
 479                                 request->ctx->pid : file->pid,
 480                                 PIDTYPE_PID);
 481                 print_file_stats(m, task ? task->comm : "<unknown>", stats);
 482                 rcu_read_unlock();
 483                 mutex_unlock(&dev->struct_mutex);
 484         }
 485         mutex_unlock(&dev->filelist_mutex);
 486
 487         return 0;
 488 }
 489
 490 static int i915_gem_gtt_info(struct seq_file *m, void *data)
 491 {
 492         struct drm_info_node *node = m->private;
 493         struct drm_i915_private *dev_priv = node_to_i915(node);
 494         struct drm_device *dev = &dev_priv->drm;
 495         bool show_pin_display_only = !!node->info_ent->data;
 496         struct drm_i915_gem_object *obj;
 497         u64 total_obj_size, total_gtt_size;
 498         int count, ret;
 499
 500         ret = mutex_lock_interruptible(&dev->struct_mutex);
 501         if (ret)
 502                 return ret;
 503
 504         total_obj_size = total_gtt_size = count = 0;
 505         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 506                 if (show_pin_display_only && !obj->pin_display)
 507                         continue;
 508
 509                 seq_puts(m, "   ");
 510                 describe_obj(m, obj);
 511                 seq_putc(m, '\n');
 512                 total_obj_size += obj->base.size;
 513                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 514                 count++;
 515         }
 516
 517         mutex_unlock(&dev->struct_mutex);
 518
 519         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 520                    count, total_obj_size, total_gtt_size);
 521
 522         return 0;
 523 }
 524
 525 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
 526 {
 527         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 528         struct drm_device *dev = &dev_priv->drm;
 529         struct intel_crtc *crtc;
 530         int ret;
 531
 532         ret = mutex_lock_interruptible(&dev->struct_mutex);
 533         if (ret)
 534                 return ret;
 535
 536         for_each_intel_crtc(dev, crtc) {
 537                 const char pipe = pipe_name(crtc->pipe);
 538                 const char plane = plane_name(crtc->plane);
 539                 struct intel_flip_work *work;
 540
 541                 spin_lock_irq(&dev->event_lock);
 542                 work = crtc->flip_work;
 543                 if (work == NULL) {
 544                         seq_printf(m, "No flip due on pipe %c (plane %c)\n",
 545                                    pipe, plane);
 546                 } else {
 547                         u32 pending;
 548                         u32 addr;
 549
 550                         pending = atomic_read(&work->pending);
 551                         if (pending) {
 552                                 seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n",
 553                                            pipe, plane);
 554                         } else {
 555                                 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
 556                                            pipe, plane);
 557                         }
 558                         if (work->flip_queued_req) {
 559                                 struct intel_engine_cs *engine = i915_gem_request_get_engine(work->flip_queued_req);
 560
 561                                 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
 562                                            engine->name,
 563                                            i915_gem_request_get_seqno(work->flip_queued_req),
 564                                            dev_priv->next_seqno,
 565                                            intel_engine_get_seqno(engine),
 566                                            i915_gem_request_completed(work->flip_queued_req));
 567                         } else
 568                                 seq_printf(m, "Flip not associated with any ring\n");
 569                         seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
 570                                    work->flip_queued_vblank,
 571                                    work->flip_ready_vblank,
 572                                    intel_crtc_get_vblank_counter(crtc));
 573                         seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
 574
 575                         if (INTEL_GEN(dev_priv) >= 4)
 576                                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
 577                         else
 578                                 addr = I915_READ(DSPADDR(crtc->plane));
 579                         seq_printf(m, "Current scanout address 0x%08x\n", addr);
 580
 581                         if (work->pending_flip_obj) {
 582                                 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
 583                                 seq_printf(m, "MMIO update completed? %d\n",  addr == work->gtt_offset);
 584                         }
 585                 }
 586                 spin_unlock_irq(&dev->event_lock);
 587         }
 588
 589         mutex_unlock(&dev->struct_mutex);
 590
 591         return 0;
 592 }
 593
 594 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
 595 {
 596         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 597         struct drm_device *dev = &dev_priv->drm;
 598         struct drm_i915_gem_object *obj;
 599         struct intel_engine_cs *engine;
 600         enum intel_engine_id id;
 601         int total = 0;
 602         int ret, j;
 603
 604         ret = mutex_lock_interruptible(&dev->struct_mutex);
 605         if (ret)
 606                 return ret;
 607
 608         for_each_engine(engine, dev_priv, id) {
 609                 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
 610                         int count;
 611
 612                         count = 0;
 613                         list_for_each_entry(obj,
 614                                             &engine->batch_pool.cache_list[j],
 615                                             batch_pool_link)
 616                                 count++;
 617                         seq_printf(m, "%s cache[%d]: %d objects\n",
 618                                    engine->name, j, count);
 619
 620                         list_for_each_entry(obj,
 621                                             &engine->batch_pool.cache_list[j],
 622                                             batch_pool_link) {
 623                                 seq_puts(m, "   ");
 624                                 describe_obj(m, obj);
 625                                 seq_putc(m, '\n');
 626                         }
 627
 628                         total += count;
 629                 }
 630         }
 631
 632         seq_printf(m, "total: %d\n", total);
 633
 634         mutex_unlock(&dev->struct_mutex);
 635
 636         return 0;
 637 }
 638
 639 static void print_request(struct seq_file *m,
 640                           struct drm_i915_gem_request *rq,
 641                           const char *prefix)
 642 {
 643         struct pid *pid = rq->ctx->pid;
 644         struct task_struct *task;
 645
 646         rcu_read_lock();
 647         task = pid ? pid_task(pid, PIDTYPE_PID) : NULL;
 648         seq_printf(m, "%s%x [%x:%x] @ %d: %s [%d]\n", prefix,
 649                    rq->fence.seqno, rq->ctx->hw_id, rq->fence.seqno,
 650                    jiffies_to_msecs(jiffies - rq->emitted_jiffies),
 651                    task ? task->comm : "<unknown>",
 652                    task ? task->pid : -1);
 653         rcu_read_unlock();
 654 }
 655
 656 static int i915_gem_request_info(struct seq_file *m, void *data)
 657 {
 658         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 659         struct drm_device *dev = &dev_priv->drm;
 660         struct drm_i915_gem_request *req;
 661         struct intel_engine_cs *engine;
 662         enum intel_engine_id id;
 663         int ret, any;
 664
 665         ret = mutex_lock_interruptible(&dev->struct_mutex);
 666         if (ret)
 667                 return ret;
 668
 669         any = 0;
 670         for_each_engine(engine, dev_priv, id) {
 671                 int count;
 672
 673                 count = 0;
 674                 list_for_each_entry(req, &engine->request_list, link)
 675                         count++;
 676                 if (count == 0)
 677                         continue;
 678
 679                 seq_printf(m, "%s requests: %d\n", engine->name, count);
 680                 list_for_each_entry(req, &engine->request_list, link)
 681                         print_request(m, req, "    ");
 682
 683                 any++;
 684         }
 685         mutex_unlock(&dev->struct_mutex);
 686
 687         if (any == 0)
 688                 seq_puts(m, "No requests\n");
 689
 690         return 0;
 691 }
 692
 693 static void i915_ring_seqno_info(struct seq_file *m,
 694                                  struct intel_engine_cs *engine)
 695 {
 696         struct intel_breadcrumbs *b = &engine->breadcrumbs;
 697         struct rb_node *rb;
 698
 699         seq_printf(m, "Current sequence (%s): %x\n",
 700                    engine->name, intel_engine_get_seqno(engine));
 701
 702         spin_lock(&b->lock);
 703         for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
 704                 struct intel_wait *w = container_of(rb, typeof(*w), node);
 705
 706                 seq_printf(m, "Waiting (%s): %s [%d] on %x\n",
 707                            engine->name, w->tsk->comm, w->tsk->pid, w->seqno);
 708         }
 709         spin_unlock(&b->lock);
 710 }
 711
 712 static int i915_gem_seqno_info(struct seq_file *m, void *data)
 713 {
 714         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 715         struct intel_engine_cs *engine;
 716         enum intel_engine_id id;
 717
 718         for_each_engine(engine, dev_priv, id)
 719                 i915_ring_seqno_info(m, engine);
 720
 721         return 0;
 722 }
 723
 724
 725 static int i915_interrupt_info(struct seq_file *m, void *data)
 726 {
 727         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 728         struct intel_engine_cs *engine;
 729         enum intel_engine_id id;
 730         int i, pipe;
 731
 732         intel_runtime_pm_get(dev_priv);
 733
 734         if (IS_CHERRYVIEW(dev_priv)) {
 735                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 736                            I915_READ(GEN8_MASTER_IRQ));
 737
 738                 seq_printf(m, "Display IER:\t%08x\n",
 739                            I915_READ(VLV_IER));
 740                 seq_printf(m, "Display IIR:\t%08x\n",
 741                            I915_READ(VLV_IIR));
 742                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 743                            I915_READ(VLV_IIR_RW));
 744                 seq_printf(m, "Display IMR:\t%08x\n",
 745                            I915_READ(VLV_IMR));
 746                 for_each_pipe(dev_priv, pipe) {
 747                         enum intel_display_power_domain power_domain;
 748
 749                         power_domain = POWER_DOMAIN_PIPE(pipe);
 750                         if (!intel_display_power_get_if_enabled(dev_priv,
 751                                                                 power_domain)) {
 752                                 seq_printf(m, "Pipe %c power disabled\n",
 753                                            pipe_name(pipe));
 754                                 continue;
 755                         }
 756
 757                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 758                                    pipe_name(pipe),
 759                                    I915_READ(PIPESTAT(pipe)));
 760
 761                         intel_display_power_put(dev_priv, power_domain);
 762                 }
 763
 764                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 765                 seq_printf(m, "Port hotplug:\t%08x\n",
 766                            I915_READ(PORT_HOTPLUG_EN));
 767                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 768                            I915_READ(VLV_DPFLIPSTAT));
 769                 seq_printf(m, "DPINVGTT:\t%08x\n",
 770                            I915_READ(DPINVGTT));
 771                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 772
 773                 for (i = 0; i < 4; i++) {
 774                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 775                                    i, I915_READ(GEN8_GT_IMR(i)));
 776                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 777                                    i, I915_READ(GEN8_GT_IIR(i)));
 778                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 779                                    i, I915_READ(GEN8_GT_IER(i)));
 780                 }
 781
 782                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 783                            I915_READ(GEN8_PCU_IMR));
 784                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 785                            I915_READ(GEN8_PCU_IIR));
 786                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 787                            I915_READ(GEN8_PCU_IER));
 788         } else if (INTEL_GEN(dev_priv) >= 8) {
 789                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 790                            I915_READ(GEN8_MASTER_IRQ));
 791
 792                 for (i = 0; i < 4; i++) {
 793                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 794                                    i, I915_READ(GEN8_GT_IMR(i)));
 795                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 796                                    i, I915_READ(GEN8_GT_IIR(i)));
 797                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 798                                    i, I915_READ(GEN8_GT_IER(i)));
 799                 }
 800
 801                 for_each_pipe(dev_priv, pipe) {
 802                         enum intel_display_power_domain power_domain;
 803
 804                         power_domain = POWER_DOMAIN_PIPE(pipe);
 805                         if (!intel_display_power_get_if_enabled(dev_priv,
 806                                                                 power_domain)) {
 807                                 seq_printf(m, "Pipe %c power disabled\n",
 808                                            pipe_name(pipe));
 809                                 continue;
 810                         }
 811                         seq_printf(m, "Pipe %c IMR:\t%08x\n",
 812                                    pipe_name(pipe),
 813                                    I915_READ(GEN8_DE_PIPE_IMR(pipe)));
 814                         seq_printf(m, "Pipe %c IIR:\t%08x\n",
 815                                    pipe_name(pipe),
 816                                    I915_READ(GEN8_DE_PIPE_IIR(pipe)));
 817                         seq_printf(m, "Pipe %c IER:\t%08x\n",
 818                                    pipe_name(pipe),
 819                                    I915_READ(GEN8_DE_PIPE_IER(pipe)));
 820
 821                         intel_display_power_put(dev_priv, power_domain);
 822                 }
 823
 824                 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
 825                            I915_READ(GEN8_DE_PORT_IMR));
 826                 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
 827                            I915_READ(GEN8_DE_PORT_IIR));
 828                 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
 829                            I915_READ(GEN8_DE_PORT_IER));
 830
 831                 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
 832                            I915_READ(GEN8_DE_MISC_IMR));
 833                 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
 834                            I915_READ(GEN8_DE_MISC_IIR));
 835                 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
 836                            I915_READ(GEN8_DE_MISC_IER));
 837
 838                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 839                            I915_READ(GEN8_PCU_IMR));
 840                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 841                            I915_READ(GEN8_PCU_IIR));
 842                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 843                            I915_READ(GEN8_PCU_IER));
 844         } else if (IS_VALLEYVIEW(dev_priv)) {
 845                 seq_printf(m, "Display IER:\t%08x\n",
 846                            I915_READ(VLV_IER));
 847                 seq_printf(m, "Display IIR:\t%08x\n",
 848                            I915_READ(VLV_IIR));
 849                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 850                            I915_READ(VLV_IIR_RW));
 851                 seq_printf(m, "Display IMR:\t%08x\n",
 852                            I915_READ(VLV_IMR));
 853                 for_each_pipe(dev_priv, pipe)
 854                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 855                                    pipe_name(pipe),
 856                                    I915_READ(PIPESTAT(pipe)));
 857
 858                 seq_printf(m, "Master IER:\t%08x\n",
 859                            I915_READ(VLV_MASTER_IER));
 860
 861                 seq_printf(m, "Render IER:\t%08x\n",
 862                            I915_READ(GTIER));
 863                 seq_printf(m, "Render IIR:\t%08x\n",
 864                            I915_READ(GTIIR));
 865                 seq_printf(m, "Render IMR:\t%08x\n",
 866                            I915_READ(GTIMR));
 867
 868                 seq_printf(m, "PM IER:\t\t%08x\n",
 869                            I915_READ(GEN6_PMIER));
 870                 seq_printf(m, "PM IIR:\t\t%08x\n",
 871                            I915_READ(GEN6_PMIIR));
 872                 seq_printf(m, "PM IMR:\t\t%08x\n",
 873                            I915_READ(GEN6_PMIMR));
 874
 875                 seq_printf(m, "Port hotplug:\t%08x\n",
 876                            I915_READ(PORT_HOTPLUG_EN));
 877                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 878                            I915_READ(VLV_DPFLIPSTAT));
 879                 seq_printf(m, "DPINVGTT:\t%08x\n",
 880                            I915_READ(DPINVGTT));
 881
 882         } else if (!HAS_PCH_SPLIT(dev_priv)) {
 883                 seq_printf(m, "Interrupt enable:    %08x\n",
 884                            I915_READ(IER));
 885                 seq_printf(m, "Interrupt identity:  %08x\n",
 886                            I915_READ(IIR));
 887                 seq_printf(m, "Interrupt mask:      %08x\n",
 888                            I915_READ(IMR));
 889                 for_each_pipe(dev_priv, pipe)
 890                         seq_printf(m, "Pipe %c stat:         %08x\n",
 891                                    pipe_name(pipe),
 892                                    I915_READ(PIPESTAT(pipe)));
 893         } else {
 894                 seq_printf(m, "North Display Interrupt enable:          %08x\n",
 895                            I915_READ(DEIER));
 896                 seq_printf(m, "North Display Interrupt identity:        %08x\n",
 897                            I915_READ(DEIIR));
 898                 seq_printf(m, "North Display Interrupt mask:            %08x\n",
 899                            I915_READ(DEIMR));
 900                 seq_printf(m, "South Display Interrupt enable:          %08x\n",
 901                            I915_READ(SDEIER));
 902                 seq_printf(m, "South Display Interrupt identity:        %08x\n",
 903                            I915_READ(SDEIIR));
 904                 seq_printf(m, "South Display Interrupt mask:            %08x\n",
 905                            I915_READ(SDEIMR));
 906                 seq_printf(m, "Graphics Interrupt enable:               %08x\n",
 907                            I915_READ(GTIER));
 908                 seq_printf(m, "Graphics Interrupt identity:             %08x\n",
 909                            I915_READ(GTIIR));
 910                 seq_printf(m, "Graphics Interrupt mask:         %08x\n",
 911                            I915_READ(GTIMR));
 912         }
 913         for_each_engine(engine, dev_priv, id) {
 914                 if (INTEL_GEN(dev_priv) >= 6) {
 915                         seq_printf(m,
 916                                    "Graphics Interrupt mask (%s):       %08x\n",
 917                                    engine->name, I915_READ_IMR(engine));
 918                 }
 919                 i915_ring_seqno_info(m, engine);
 920         }
 921         intel_runtime_pm_put(dev_priv);
 922
 923         return 0;
 924 }
 925
 926 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
 927 {
 928         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 929         struct drm_device *dev = &dev_priv->drm;
 930         int i, ret;
 931
 932         ret = mutex_lock_interruptible(&dev->struct_mutex);
 933         if (ret)
 934                 return ret;
 935
 936         seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
 937         for (i = 0; i < dev_priv->num_fence_regs; i++) {
 938                 struct i915_vma *vma = dev_priv->fence_regs[i].vma;
 939
 940                 seq_printf(m, "Fence %d, pin count = %d, object = ",
 941                            i, dev_priv->fence_regs[i].pin_count);
 942                 if (!vma)
 943                         seq_puts(m, "unused");
 944                 else
 945                         describe_obj(m, vma->obj);
 946                 seq_putc(m, '\n');
 947         }
 948
 949         mutex_unlock(&dev->struct_mutex);
 950         return 0;
 951 }
 952
 953 static int i915_hws_info(struct seq_file *m, void *data)
 954 {
 955         struct drm_info_node *node = m->private;
 956         struct drm_i915_private *dev_priv = node_to_i915(node);
 957         struct intel_engine_cs *engine;
 958         const u32 *hws;
 959         int i;
 960
 961         engine = dev_priv->engine[(uintptr_t)node->info_ent->data];
 962         hws = engine->status_page.page_addr;
 963         if (hws == NULL)
 964                 return 0;
 965
 966         for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
 967                 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
 968                            i * 4,
 969                            hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
 970         }
 971         return 0;
 972 }
 973
 974 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
 975
 976 static ssize_t
 977 i915_error_state_write(struct file *filp,
 978                        const char __user *ubuf,
 979                        size_t cnt,
 980                        loff_t *ppos)
 981 {
 982         struct i915_error_state_file_priv *error_priv = filp->private_data;
 983
 984         DRM_DEBUG_DRIVER("Resetting error state\n");
 985         i915_destroy_error_state(error_priv->dev);
 986
 987         return cnt;
 988 }
 989
 990 static int i915_error_state_open(struct inode *inode, struct file *file)
 991 {
 992         struct drm_i915_private *dev_priv = inode->i_private;
 993         struct i915_error_state_file_priv *error_priv;
 994
 995         error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
 996         if (!error_priv)
 997                 return -ENOMEM;
 998
 999         error_priv->dev = &dev_priv->drm;
1000
1001         i915_error_state_get(&dev_priv->drm, error_priv);
1002
1003         file->private_data = error_priv;
1004
1005         return 0;
1006 }
1007
1008 static int i915_error_state_release(struct inode *inode, struct file *file)
1009 {
1010         struct i915_error_state_file_priv *error_priv = file->private_data;
1011
1012         i915_error_state_put(error_priv);
1013         kfree(error_priv);
1014
1015         return 0;
1016 }
1017
1018 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1019                                      size_t count, loff_t *pos)
1020 {
1021         struct i915_error_state_file_priv *error_priv = file->private_data;
1022         struct drm_i915_error_state_buf error_str;
1023         loff_t tmp_pos = 0;
1024         ssize_t ret_count = 0;
1025         int ret;
1026
1027         ret = i915_error_state_buf_init(&error_str,
1028                                         to_i915(error_priv->dev), count, *pos);
1029         if (ret)
1030                 return ret;
1031
1032         ret = i915_error_state_to_str(&error_str, error_priv);
1033         if (ret)
1034                 goto out;
1035
1036         ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1037                                             error_str.buf,
1038                                             error_str.bytes);
1039
1040         if (ret_count < 0)
1041                 ret = ret_count;
1042         else
1043                 *pos = error_str.start + ret_count;
1044 out:
1045         i915_error_state_buf_release(&error_str);
1046         return ret ?: ret_count;
1047 }
1048
1049 static const struct file_operations i915_error_state_fops = {
1050         .owner = THIS_MODULE,
1051         .open = i915_error_state_open,
1052         .read = i915_error_state_read,
1053         .write = i915_error_state_write,
1054         .llseek = default_llseek,
1055         .release = i915_error_state_release,
1056 };
1057
1058 #endif
1059
1060 static int
1061 i915_next_seqno_get(void *data, u64 *val)
1062 {
1063         struct drm_i915_private *dev_priv = data;
1064         int ret;
1065
1066         ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
1067         if (ret)
1068                 return ret;
1069
1070         *val = dev_priv->next_seqno;
1071         mutex_unlock(&dev_priv->drm.struct_mutex);
1072
1073         return 0;
1074 }
1075
1076 static int
1077 i915_next_seqno_set(void *data, u64 val)
1078 {
1079         struct drm_i915_private *dev_priv = data;
1080         struct drm_device *dev = &dev_priv->drm;
1081         int ret;
1082
1083         ret = mutex_lock_interruptible(&dev->struct_mutex);
1084         if (ret)
1085                 return ret;
1086
1087         ret = i915_gem_set_seqno(dev, val);
1088         mutex_unlock(&dev->struct_mutex);
1089
1090         return ret;
1091 }
1092
1093 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1094                         i915_next_seqno_get, i915_next_seqno_set,
1095                         "0x%llx\n");
1096
1097 static int i915_frequency_info(struct seq_file *m, void *unused)
1098 {
1099         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1100         struct drm_device *dev = &dev_priv->drm;
1101         int ret = 0;
1102
1103         intel_runtime_pm_get(dev_priv);
1104
1105         if (IS_GEN5(dev_priv)) {
1106                 u16 rgvswctl = I915_READ16(MEMSWCTL);
1107                 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1108
1109                 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1110                 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1111                 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1112                            MEMSTAT_VID_SHIFT);
1113                 seq_printf(m, "Current P-state: %d\n",
1114                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1115         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1116                 u32 freq_sts;
1117
1118                 mutex_lock(&dev_priv->rps.hw_lock);
1119                 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1120                 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1121                 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1122
1123                 seq_printf(m, "actual GPU freq: %d MHz\n",
1124                            intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1125
1126                 seq_printf(m, "current GPU freq: %d MHz\n",
1127                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1128
1129                 seq_printf(m, "max GPU freq: %d MHz\n",
1130                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1131
1132                 seq_printf(m, "min GPU freq: %d MHz\n",
1133                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1134
1135                 seq_printf(m, "idle GPU freq: %d MHz\n",
1136                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1137
1138                 seq_printf(m,
1139                            "efficient (RPe) frequency: %d MHz\n",
1140                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1141                 mutex_unlock(&dev_priv->rps.hw_lock);
1142         } else if (INTEL_GEN(dev_priv) >= 6) {
1143                 u32 rp_state_limits;
1144                 u32 gt_perf_status;
1145                 u32 rp_state_cap;
1146                 u32 rpmodectl, rpinclimit, rpdeclimit;
1147                 u32 rpstat, cagf, reqf;
1148                 u32 rpupei, rpcurup, rpprevup;
1149                 u32 rpdownei, rpcurdown, rpprevdown;
1150                 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1151                 int max_freq;
1152
1153                 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1154                 if (IS_BROXTON(dev_priv)) {
1155                         rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1156                         gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1157                 } else {
1158                         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1159                         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1160                 }
1161
1162                 /* RPSTAT1 is in the GT power well */
1163                 ret = mutex_lock_interruptible(&dev->struct_mutex);
1164                 if (ret)
1165                         goto out;
1166
1167                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1168
1169                 reqf = I915_READ(GEN6_RPNSWREQ);
1170                 if (IS_GEN9(dev_priv))
1171                         reqf >>= 23;
1172                 else {
1173                         reqf &= ~GEN6_TURBO_DISABLE;
1174                         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1175                                 reqf >>= 24;
1176                         else
1177                                 reqf >>= 25;
1178                 }
1179                 reqf = intel_gpu_freq(dev_priv, reqf);
1180
1181                 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1182                 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1183                 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1184
1185                 rpstat = I915_READ(GEN6_RPSTAT1);
1186                 rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
1187                 rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
1188                 rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
1189                 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
1190                 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
1191                 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
1192                 if (IS_GEN9(dev_priv))
1193                         cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1194                 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1195                         cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1196                 else
1197                         cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1198                 cagf = intel_gpu_freq(dev_priv, cagf);
1199
1200                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1201                 mutex_unlock(&dev->struct_mutex);
1202
1203                 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
1204                         pm_ier = I915_READ(GEN6_PMIER);
1205                         pm_imr = I915_READ(GEN6_PMIMR);
1206                         pm_isr = I915_READ(GEN6_PMISR);
1207                         pm_iir = I915_READ(GEN6_PMIIR);
1208                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1209                 } else {
1210                         pm_ier = I915_READ(GEN8_GT_IER(2));
1211                         pm_imr = I915_READ(GEN8_GT_IMR(2));
1212                         pm_isr = I915_READ(GEN8_GT_ISR(2));
1213                         pm_iir = I915_READ(GEN8_GT_IIR(2));
1214                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1215                 }
1216                 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1217                            pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1218                 seq_printf(m, "pm_intr_keep: 0x%08x\n", dev_priv->rps.pm_intr_keep);
1219                 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1220                 seq_printf(m, "Render p-state ratio: %d\n",
1221                            (gt_perf_status & (IS_GEN9(dev_priv) ? 0x1ff00 : 0xff00)) >> 8);
1222                 seq_printf(m, "Render p-state VID: %d\n",
1223                            gt_perf_status & 0xff);
1224                 seq_printf(m, "Render p-state limit: %d\n",
1225                            rp_state_limits & 0xff);
1226                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1227                 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1228                 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1229                 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1230                 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1231                 seq_printf(m, "CAGF: %dMHz\n", cagf);
1232                 seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
1233                            rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei));
1234                 seq_printf(m, "RP CUR UP: %d (%dus)\n",
1235                            rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
1236                 seq_printf(m, "RP PREV UP: %d (%dus)\n",
1237                            rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
1238                 seq_printf(m, "Up threshold: %d%%\n",
1239                            dev_priv->rps.up_threshold);
1240
1241                 seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
1242                            rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
1243                 seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
1244                            rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown));
1245                 seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
1246                            rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown));
1247                 seq_printf(m, "Down threshold: %d%%\n",
1248                            dev_priv->rps.down_threshold);
1249
1250                 max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 0 :
1251                             rp_state_cap >> 16) & 0xff;
1252                 max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1253                              GEN9_FREQ_SCALER : 1);
1254                 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1255                            intel_gpu_freq(dev_priv, max_freq));
1256
1257                 max_freq = (rp_state_cap & 0xff00) >> 8;
1258                 max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1259                              GEN9_FREQ_SCALER : 1);
1260                 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1261                            intel_gpu_freq(dev_priv, max_freq));
1262
1263                 max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 16 :
1264                             rp_state_cap >> 0) & 0xff;
1265                 max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1266                              GEN9_FREQ_SCALER : 1);
1267                 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1268                            intel_gpu_freq(dev_priv, max_freq));
1269                 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1270                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1271
1272                 seq_printf(m, "Current freq: %d MHz\n",
1273                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1274                 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1275                 seq_printf(m, "Idle freq: %d MHz\n",
1276                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1277                 seq_printf(m, "Min freq: %d MHz\n",
1278                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1279                 seq_printf(m, "Boost freq: %d MHz\n",
1280                            intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
1281                 seq_printf(m, "Max freq: %d MHz\n",
1282                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1283                 seq_printf(m,
1284                            "efficient (RPe) frequency: %d MHz\n",
1285                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1286         } else {
1287                 seq_puts(m, "no P-state info available\n");
1288         }
1289
1290         seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
1291         seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1292         seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1293
1294 out:
1295         intel_runtime_pm_put(dev_priv);
1296         return ret;
1297 }
1298
1299 static void i915_instdone_info(struct drm_i915_private *dev_priv,
1300                                struct seq_file *m,
1301                                struct intel_instdone *instdone)
1302 {
1303         int slice;
1304         int subslice;
1305
1306         seq_printf(m, "\t\tINSTDONE: 0x%08x\n",
1307                    instdone->instdone);
1308
1309         if (INTEL_GEN(dev_priv) <= 3)
1310                 return;
1311
1312         seq_printf(m, "\t\tSC_INSTDONE: 0x%08x\n",
1313                    instdone->slice_common);
1314
1315         if (INTEL_GEN(dev_priv) <= 6)
1316                 return;
1317
1318         for_each_instdone_slice_subslice(dev_priv, slice, subslice)
1319                 seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
1320                            slice, subslice, instdone->sampler[slice][subslice]);
1321
1322         for_each_instdone_slice_subslice(dev_priv, slice, subslice)
1323                 seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n",
1324                            slice, subslice, instdone->row[slice][subslice]);
1325 }
1326
1327 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1328 {
1329         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1330         struct intel_engine_cs *engine;
1331         u64 acthd[I915_NUM_ENGINES];
1332         u32 seqno[I915_NUM_ENGINES];
1333         struct intel_instdone instdone;
1334         enum intel_engine_id id;
1335
1336         if (test_bit(I915_WEDGED, &dev_priv->gpu_error.flags))
1337                 seq_printf(m, "Wedged\n");
1338         if (test_bit(I915_RESET_IN_PROGRESS, &dev_priv->gpu_error.flags))
1339                 seq_printf(m, "Reset in progress\n");
1340         if (waitqueue_active(&dev_priv->gpu_error.wait_queue))
1341                 seq_printf(m, "Waiter holding struct mutex\n");
1342         if (waitqueue_active(&dev_priv->gpu_error.reset_queue))
1343                 seq_printf(m, "struct_mutex blocked for reset\n");
1344
1345         if (!i915.enable_hangcheck) {
1346                 seq_printf(m, "Hangcheck disabled\n");
1347                 return 0;
1348         }
1349
1350         intel_runtime_pm_get(dev_priv);
1351
1352         for_each_engine(engine, dev_priv, id) {
1353                 acthd[id] = intel_engine_get_active_head(engine);
1354                 seqno[id] = intel_engine_get_seqno(engine);
1355         }
1356
1357         intel_engine_get_instdone(dev_priv->engine[RCS], &instdone);
1358
1359         intel_runtime_pm_put(dev_priv);
1360
1361         if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1362                 seq_printf(m, "Hangcheck active, fires in %dms\n",
1363                            jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1364                                             jiffies));
1365         } else
1366                 seq_printf(m, "Hangcheck inactive\n");
1367
1368         for_each_engine(engine, dev_priv, id) {
1369                 struct intel_breadcrumbs *b = &engine->breadcrumbs;
1370                 struct rb_node *rb;
1371
1372                 seq_printf(m, "%s:\n", engine->name);
1373                 seq_printf(m, "\tseqno = %x [current %x, last %x]\n",
1374                            engine->hangcheck.seqno,
1375                            seqno[id],
1376                            engine->last_submitted_seqno);
1377                 seq_printf(m, "\twaiters? %s, fake irq active? %s\n",
1378                            yesno(intel_engine_has_waiter(engine)),
1379                            yesno(test_bit(engine->id,
1380                                           &dev_priv->gpu_error.missed_irq_rings)));
1381                 spin_lock(&b->lock);
1382                 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
1383                         struct intel_wait *w = container_of(rb, typeof(*w), node);
1384
1385                         seq_printf(m, "\t%s [%d] waiting for %x\n",
1386                                    w->tsk->comm, w->tsk->pid, w->seqno);
1387                 }
1388                 spin_unlock(&b->lock);
1389
1390                 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1391                            (long long)engine->hangcheck.acthd,
1392                            (long long)acthd[id]);
1393                 seq_printf(m, "\tscore = %d\n", engine->hangcheck.score);
1394                 seq_printf(m, "\taction = %d\n", engine->hangcheck.action);
1395
1396                 if (engine->id == RCS) {
1397                         seq_puts(m, "\tinstdone read =\n");
1398
1399                         i915_instdone_info(dev_priv, m, &instdone);
1400
1401                         seq_puts(m, "\tinstdone accu =\n");
1402
1403                         i915_instdone_info(dev_priv, m,
1404                                            &engine->hangcheck.instdone);
1405                 }
1406         }
1407
1408         return 0;
1409 }
1410
1411 static int ironlake_drpc_info(struct seq_file *m)
1412 {
1413         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1414         u32 rgvmodectl, rstdbyctl;
1415         u16 crstandvid;
1416
1417         intel_runtime_pm_get(dev_priv);
1418
1419         rgvmodectl = I915_READ(MEMMODECTL);
1420         rstdbyctl = I915_READ(RSTDBYCTL);
1421         crstandvid = I915_READ16(CRSTANDVID);
1422
1423         intel_runtime_pm_put(dev_priv);
1424
1425         seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1426         seq_printf(m, "Boost freq: %d\n",
1427                    (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1428                    MEMMODE_BOOST_FREQ_SHIFT);
1429         seq_printf(m, "HW control enabled: %s\n",
1430                    yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1431         seq_printf(m, "SW control enabled: %s\n",
1432                    yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1433         seq_printf(m, "Gated voltage change: %s\n",
1434                    yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1435         seq_printf(m, "Starting frequency: P%d\n",
1436                    (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1437         seq_printf(m, "Max P-state: P%d\n",
1438                    (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1439         seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1440         seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1441         seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1442         seq_printf(m, "Render standby enabled: %s\n",
1443                    yesno(!(rstdbyctl & RCX_SW_EXIT)));
1444         seq_puts(m, "Current RS state: ");
1445         switch (rstdbyctl & RSX_STATUS_MASK) {
1446         case RSX_STATUS_ON:
1447                 seq_puts(m, "on\n");
1448                 break;
1449         case RSX_STATUS_RC1:
1450                 seq_puts(m, "RC1\n");
1451                 break;
1452         case RSX_STATUS_RC1E:
1453                 seq_puts(m, "RC1E\n");
1454                 break;
1455         case RSX_STATUS_RS1:
1456                 seq_puts(m, "RS1\n");
1457                 break;
1458         case RSX_STATUS_RS2:
1459                 seq_puts(m, "RS2 (RC6)\n");
1460                 break;
1461         case RSX_STATUS_RS3:
1462                 seq_puts(m, "RC3 (RC6+)\n");
1463                 break;
1464         default:
1465                 seq_puts(m, "unknown\n");
1466                 break;
1467         }
1468
1469         return 0;
1470 }
1471
1472 static int i915_forcewake_domains(struct seq_file *m, void *data)
1473 {
1474         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1475         struct intel_uncore_forcewake_domain *fw_domain;
1476
1477         spin_lock_irq(&dev_priv->uncore.lock);
1478         for_each_fw_domain(fw_domain, dev_priv) {
1479                 seq_printf(m, "%s.wake_count = %u\n",
1480                            intel_uncore_forcewake_domain_to_str(fw_domain->id),
1481                            fw_domain->wake_count);
1482         }
1483         spin_unlock_irq(&dev_priv->uncore.lock);
1484
1485         return 0;
1486 }
1487
1488 static int vlv_drpc_info(struct seq_file *m)
1489 {
1490         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1491         u32 rpmodectl1, rcctl1, pw_status;
1492
1493         intel_runtime_pm_get(dev_priv);
1494
1495         pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1496         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1497         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1498
1499         intel_runtime_pm_put(dev_priv);
1500
1501         seq_printf(m, "Video Turbo Mode: %s\n",
1502                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1503         seq_printf(m, "Turbo enabled: %s\n",
1504                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1505         seq_printf(m, "HW control enabled: %s\n",
1506                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1507         seq_printf(m, "SW control enabled: %s\n",
1508                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1509                           GEN6_RP_MEDIA_SW_MODE));
1510         seq_printf(m, "RC6 Enabled: %s\n",
1511                    yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1512                                         GEN6_RC_CTL_EI_MODE(1))));
1513         seq_printf(m, "Render Power Well: %s\n",
1514                    (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1515         seq_printf(m, "Media Power Well: %s\n",
1516                    (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1517
1518         seq_printf(m, "Render RC6 residency since boot: %u\n",
1519                    I915_READ(VLV_GT_RENDER_RC6));
1520         seq_printf(m, "Media RC6 residency since boot: %u\n",
1521                    I915_READ(VLV_GT_MEDIA_RC6));
1522
1523         return i915_forcewake_domains(m, NULL);
1524 }
1525
1526 static int gen6_drpc_info(struct seq_file *m)
1527 {
1528         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1529         struct drm_device *dev = &dev_priv->drm;
1530         u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1531         u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
1532         unsigned forcewake_count;
1533         int count = 0, ret;
1534
1535         ret = mutex_lock_interruptible(&dev->struct_mutex);
1536         if (ret)
1537                 return ret;
1538         intel_runtime_pm_get(dev_priv);
1539
1540         spin_lock_irq(&dev_priv->uncore.lock);
1541         forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1542         spin_unlock_irq(&dev_priv->uncore.lock);
1543
1544         if (forcewake_count) {
1545                 seq_puts(m, "RC information inaccurate because somebody "
1546                             "holds a forcewake reference \n");
1547         } else {
1548                 /* NB: we cannot use forcewake, else we read the wrong values */
1549                 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1550                         udelay(10);
1551                 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1552         }
1553
1554         gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1555         trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1556
1557         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1558         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1559         if (INTEL_GEN(dev_priv) >= 9) {
1560                 gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE);
1561                 gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
1562         }
1563         mutex_unlock(&dev->struct_mutex);
1564         mutex_lock(&dev_priv->rps.hw_lock);
1565         sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1566         mutex_unlock(&dev_priv->rps.hw_lock);
1567
1568         intel_runtime_pm_put(dev_priv);
1569
1570         seq_printf(m, "Video Turbo Mode: %s\n",
1571                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1572         seq_printf(m, "HW control enabled: %s\n",
1573                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1574         seq_printf(m, "SW control enabled: %s\n",
1575                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1576                           GEN6_RP_MEDIA_SW_MODE));
1577         seq_printf(m, "RC1e Enabled: %s\n",
1578                    yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1579         seq_printf(m, "RC6 Enabled: %s\n",
1580                    yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1581         if (INTEL_GEN(dev_priv) >= 9) {
1582                 seq_printf(m, "Render Well Gating Enabled: %s\n",
1583                         yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
1584                 seq_printf(m, "Media Well Gating Enabled: %s\n",
1585                         yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE));
1586         }
1587         seq_printf(m, "Deep RC6 Enabled: %s\n",
1588                    yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1589         seq_printf(m, "Deepest RC6 Enabled: %s\n",
1590                    yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1591         seq_puts(m, "Current RC state: ");
1592         switch (gt_core_status & GEN6_RCn_MASK) {
1593         case GEN6_RC0:
1594                 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1595                         seq_puts(m, "Core Power Down\n");
1596                 else
1597                         seq_puts(m, "on\n");
1598                 break;
1599         case GEN6_RC3:
1600                 seq_puts(m, "RC3\n");
1601                 break;
1602         case GEN6_RC6:
1603                 seq_puts(m, "RC6\n");
1604                 break;
1605         case GEN6_RC7:
1606                 seq_puts(m, "RC7\n");
1607                 break;
1608         default:
1609                 seq_puts(m, "Unknown\n");
1610                 break;
1611         }
1612
1613         seq_printf(m, "Core Power Down: %s\n",
1614                    yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1615         if (INTEL_GEN(dev_priv) >= 9) {
1616                 seq_printf(m, "Render Power Well: %s\n",
1617                         (gen9_powergate_status &
1618                          GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
1619                 seq_printf(m, "Media Power Well: %s\n",
1620                         (gen9_powergate_status &
1621                          GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
1622         }
1623
1624         /* Not exactly sure what this is */
1625         seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1626                    I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1627         seq_printf(m, "RC6 residency since boot: %u\n",
1628                    I915_READ(GEN6_GT_GFX_RC6));
1629         seq_printf(m, "RC6+ residency since boot: %u\n",
1630                    I915_READ(GEN6_GT_GFX_RC6p));
1631         seq_printf(m, "RC6++ residency since boot: %u\n",
1632                    I915_READ(GEN6_GT_GFX_RC6pp));
1633
1634         seq_printf(m, "RC6   voltage: %dmV\n",
1635                    GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1636         seq_printf(m, "RC6+  voltage: %dmV\n",
1637                    GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1638         seq_printf(m, "RC6++ voltage: %dmV\n",
1639                    GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1640         return i915_forcewake_domains(m, NULL);
1641 }
1642
1643 static int i915_drpc_info(struct seq_file *m, void *unused)
1644 {
1645         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1646
1647         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1648                 return vlv_drpc_info(m);
1649         else if (INTEL_GEN(dev_priv) >= 6)
1650                 return gen6_drpc_info(m);
1651         else
1652                 return ironlake_drpc_info(m);
1653 }
1654
1655 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1656 {
1657         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1658
1659         seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1660                    dev_priv->fb_tracking.busy_bits);
1661
1662         seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1663                    dev_priv->fb_tracking.flip_bits);
1664
1665         return 0;
1666 }
1667
1668 static int i915_fbc_status(struct seq_file *m, void *unused)
1669 {
1670         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1671
1672         if (!HAS_FBC(dev_priv)) {
1673                 seq_puts(m, "FBC unsupported on this chipset\n");
1674                 return 0;
1675         }
1676
1677         intel_runtime_pm_get(dev_priv);
1678         mutex_lock(&dev_priv->fbc.lock);
1679
1680         if (intel_fbc_is_active(dev_priv))
1681                 seq_puts(m, "FBC enabled\n");
1682         else
1683                 seq_printf(m, "FBC disabled: %s\n",
1684                            dev_priv->fbc.no_fbc_reason);
1685
1686         if (intel_fbc_is_active(dev_priv) && INTEL_GEN(dev_priv) >= 7) {
1687                 uint32_t mask = INTEL_GEN(dev_priv) >= 8 ?
1688                                 BDW_FBC_COMPRESSION_MASK :
1689                                 IVB_FBC_COMPRESSION_MASK;
1690                 seq_printf(m, "Compressing: %s\n",
1691                            yesno(I915_READ(FBC_STATUS2) & mask));
1692         }
1693
1694         mutex_unlock(&dev_priv->fbc.lock);
1695         intel_runtime_pm_put(dev_priv);
1696
1697         return 0;
1698 }
1699
1700 static int i915_fbc_fc_get(void *data, u64 *val)
1701 {
1702         struct drm_i915_private *dev_priv = data;
1703
1704         if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1705                 return -ENODEV;
1706
1707         *val = dev_priv->fbc.false_color;
1708
1709         return 0;
1710 }
1711
1712 static int i915_fbc_fc_set(void *data, u64 val)
1713 {
1714         struct drm_i915_private *dev_priv = data;
1715         u32 reg;
1716
1717         if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1718                 return -ENODEV;
1719
1720         mutex_lock(&dev_priv->fbc.lock);
1721
1722         reg = I915_READ(ILK_DPFC_CONTROL);
1723         dev_priv->fbc.false_color = val;
1724
1725         I915_WRITE(ILK_DPFC_CONTROL, val ?
1726                    (reg | FBC_CTL_FALSE_COLOR) :
1727                    (reg & ~FBC_CTL_FALSE_COLOR));
1728
1729         mutex_unlock(&dev_priv->fbc.lock);
1730         return 0;
1731 }
1732
1733 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1734                         i915_fbc_fc_get, i915_fbc_fc_set,
1735                         "%llu\n");
1736
1737 static int i915_ips_status(struct seq_file *m, void *unused)
1738 {
1739         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1740
1741         if (!HAS_IPS(dev_priv)) {
1742                 seq_puts(m, "not supported\n");
1743                 return 0;
1744         }
1745
1746         intel_runtime_pm_get(dev_priv);
1747
1748         seq_printf(m, "Enabled by kernel parameter: %s\n",
1749                    yesno(i915.enable_ips));
1750
1751         if (INTEL_GEN(dev_priv) >= 8) {
1752                 seq_puts(m, "Currently: unknown\n");
1753         } else {
1754                 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1755                         seq_puts(m, "Currently: enabled\n");
1756                 else
1757                         seq_puts(m, "Currently: disabled\n");
1758         }
1759
1760         intel_runtime_pm_put(dev_priv);
1761
1762         return 0;
1763 }
1764
1765 static int i915_sr_status(struct seq_file *m, void *unused)
1766 {
1767         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1768         bool sr_enabled = false;
1769
1770         intel_runtime_pm_get(dev_priv);
1771         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1772
1773         if (HAS_PCH_SPLIT(dev_priv))
1774                 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1775         else if (IS_CRESTLINE(dev_priv) || IS_G4X(dev_priv) ||
1776                  IS_I945G(dev_priv) || IS_I945GM(dev_priv))
1777                 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1778         else if (IS_I915GM(dev_priv))
1779                 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1780         else if (IS_PINEVIEW(dev_priv))
1781                 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1782         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1783                 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1784
1785         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1786         intel_runtime_pm_put(dev_priv);
1787
1788         seq_printf(m, "self-refresh: %s\n",
1789                    sr_enabled ? "enabled" : "disabled");
1790
1791         return 0;
1792 }
1793
1794 static int i915_emon_status(struct seq_file *m, void *unused)
1795 {
1796         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1797         struct drm_device *dev = &dev_priv->drm;
1798         unsigned long temp, chipset, gfx;
1799         int ret;
1800
1801         if (!IS_GEN5(dev_priv))
1802                 return -ENODEV;
1803
1804         ret = mutex_lock_interruptible(&dev->struct_mutex);
1805         if (ret)
1806                 return ret;
1807
1808         temp = i915_mch_val(dev_priv);
1809         chipset = i915_chipset_val(dev_priv);
1810         gfx = i915_gfx_val(dev_priv);
1811         mutex_unlock(&dev->struct_mutex);
1812
1813         seq_printf(m, "GMCH temp: %ld\n", temp);
1814         seq_printf(m, "Chipset power: %ld\n", chipset);
1815         seq_printf(m, "GFX power: %ld\n", gfx);
1816         seq_printf(m, "Total power: %ld\n", chipset + gfx);
1817
1818         return 0;
1819 }
1820
1821 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1822 {
1823         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1824         int ret = 0;
1825         int gpu_freq, ia_freq;
1826         unsigned int max_gpu_freq, min_gpu_freq;
1827
1828         if (!HAS_LLC(dev_priv)) {
1829                 seq_puts(m, "unsupported on this chipset\n");
1830                 return 0;
1831         }
1832
1833         intel_runtime_pm_get(dev_priv);
1834
1835         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1836         if (ret)
1837                 goto out;
1838
1839         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
1840                 /* Convert GT frequency to 50 HZ units */
1841                 min_gpu_freq =
1842                         dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1843                 max_gpu_freq =
1844                         dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1845         } else {
1846                 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1847                 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1848         }
1849
1850         seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1851
1852         for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1853                 ia_freq = gpu_freq;
1854                 sandybridge_pcode_read(dev_priv,
1855                                        GEN6_PCODE_READ_MIN_FREQ_TABLE,
1856                                        &ia_freq);
1857                 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1858                            intel_gpu_freq(dev_priv, (gpu_freq *
1859                                 (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1860                                  GEN9_FREQ_SCALER : 1))),
1861                            ((ia_freq >> 0) & 0xff) * 100,
1862                            ((ia_freq >> 8) & 0xff) * 100);
1863         }
1864
1865         mutex_unlock(&dev_priv->rps.hw_lock);
1866
1867 out:
1868         intel_runtime_pm_put(dev_priv);
1869         return ret;
1870 }
1871
1872 static int i915_opregion(struct seq_file *m, void *unused)
1873 {
1874         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1875         struct drm_device *dev = &dev_priv->drm;
1876         struct intel_opregion *opregion = &dev_priv->opregion;
1877         int ret;
1878
1879         ret = mutex_lock_interruptible(&dev->struct_mutex);
1880         if (ret)
1881                 goto out;
1882
1883         if (opregion->header)
1884                 seq_write(m, opregion->header, OPREGION_SIZE);
1885
1886         mutex_unlock(&dev->struct_mutex);
1887
1888 out:
1889         return 0;
1890 }
1891
1892 static int i915_vbt(struct seq_file *m, void *unused)
1893 {
1894         struct intel_opregion *opregion = &node_to_i915(m->private)->opregion;
1895
1896         if (opregion->vbt)
1897                 seq_write(m, opregion->vbt, opregion->vbt_size);
1898
1899         return 0;
1900 }
1901
1902 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1903 {
1904         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1905         struct drm_device *dev = &dev_priv->drm;
1906         struct intel_framebuffer *fbdev_fb = NULL;
1907         struct drm_framebuffer *drm_fb;
1908         int ret;
1909
1910         ret = mutex_lock_interruptible(&dev->struct_mutex);
1911         if (ret)
1912                 return ret;
1913
1914 #ifdef CONFIG_DRM_FBDEV_EMULATION
1915         if (dev_priv->fbdev) {
1916                 fbdev_fb = to_intel_framebuffer(dev_priv->fbdev->helper.fb);
1917
1918                 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1919                            fbdev_fb->base.width,
1920                            fbdev_fb->base.height,
1921                            fbdev_fb->base.depth,
1922                            fbdev_fb->base.bits_per_pixel,
1923                            fbdev_fb->base.modifier[0],
1924                            drm_framebuffer_read_refcount(&fbdev_fb->base));
1925                 describe_obj(m, fbdev_fb->obj);
1926                 seq_putc(m, '\n');
1927         }
1928 #endif
1929
1930         mutex_lock(&dev->mode_config.fb_lock);
1931         drm_for_each_fb(drm_fb, dev) {
1932                 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
1933                 if (fb == fbdev_fb)
1934                         continue;
1935
1936                 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1937                            fb->base.width,
1938                            fb->base.height,
1939                            fb->base.depth,
1940                            fb->base.bits_per_pixel,
1941                            fb->base.modifier[0],
1942                            drm_framebuffer_read_refcount(&fb->base));
1943                 describe_obj(m, fb->obj);
1944                 seq_putc(m, '\n');
1945         }
1946         mutex_unlock(&dev->mode_config.fb_lock);
1947         mutex_unlock(&dev->struct_mutex);
1948
1949         return 0;
1950 }
1951
1952 static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring)
1953 {
1954         seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1955                    ring->space, ring->head, ring->tail,
1956                    ring->last_retired_head);
1957 }
1958
1959 static int i915_context_status(struct seq_file *m, void *unused)
1960 {
1961         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1962         struct drm_device *dev = &dev_priv->drm;
1963         struct intel_engine_cs *engine;
1964         struct i915_gem_context *ctx;
1965         enum intel_engine_id id;
1966         int ret;
1967
1968         ret = mutex_lock_interruptible(&dev->struct_mutex);
1969         if (ret)
1970                 return ret;
1971
1972         list_for_each_entry(ctx, &dev_priv->context_list, link) {
1973                 seq_printf(m, "HW context %u ", ctx->hw_id);
1974                 if (ctx->pid) {
1975                         struct task_struct *task;
1976
1977                         task = get_pid_task(ctx->pid, PIDTYPE_PID);
1978                         if (task) {
1979                                 seq_printf(m, "(%s [%d]) ",
1980                                            task->comm, task->pid);
1981                                 put_task_struct(task);
1982                         }
1983                 } else if (IS_ERR(ctx->file_priv)) {
1984                         seq_puts(m, "(deleted) ");
1985                 } else {
1986                         seq_puts(m, "(kernel) ");
1987                 }
1988
1989                 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
1990                 seq_putc(m, '\n');
1991
1992                 for_each_engine(engine, dev_priv, id) {
1993                         struct intel_context *ce = &ctx->engine[engine->id];
1994
1995                         seq_printf(m, "%s: ", engine->name);
1996                         seq_putc(m, ce->initialised ? 'I' : 'i');
1997                         if (ce->state)
1998                                 describe_obj(m, ce->state->obj);
1999                         if (ce->ring)
2000                                 describe_ctx_ring(m, ce->ring);
2001                         seq_putc(m, '\n');
2002                 }
2003
2004                 seq_putc(m, '\n');
2005         }
2006
2007         mutex_unlock(&dev->struct_mutex);
2008
2009         return 0;
2010 }
2011
2012 static void i915_dump_lrc_obj(struct seq_file *m,
2013                               struct i915_gem_context *ctx,
2014                               struct intel_engine_cs *engine)
2015 {
2016         struct i915_vma *vma = ctx->engine[engine->id].state;
2017         struct page *page;
2018         int j;
2019
2020         seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id);
2021
2022         if (!vma) {
2023                 seq_puts(m, "\tFake context\n");
2024                 return;
2025         }
2026
2027         if (vma->flags & I915_VMA_GLOBAL_BIND)
2028                 seq_printf(m, "\tBound in GGTT at 0x%08x\n",
2029                            i915_ggtt_offset(vma));
2030
2031         if (i915_gem_object_get_pages(vma->obj)) {
2032                 seq_puts(m, "\tFailed to get pages for context object\n\n");
2033                 return;
2034         }
2035
2036         page = i915_gem_object_get_page(vma->obj, LRC_STATE_PN);
2037         if (page) {
2038                 u32 *reg_state = kmap_atomic(page);
2039
2040                 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2041                         seq_printf(m,
2042                                    "\t[0x%04x] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2043                                    j * 4,
2044                                    reg_state[j], reg_state[j + 1],
2045                                    reg_state[j + 2], reg_state[j + 3]);
2046                 }
2047                 kunmap_atomic(reg_state);
2048         }
2049
2050         seq_putc(m, '\n');
2051 }
2052
2053 static int i915_dump_lrc(struct seq_file *m, void *unused)
2054 {
2055         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2056         struct drm_device *dev = &dev_priv->drm;
2057         struct intel_engine_cs *engine;
2058         struct i915_gem_context *ctx;
2059         enum intel_engine_id id;
2060         int ret;
2061
2062         if (!i915.enable_execlists) {
2063                 seq_printf(m, "Logical Ring Contexts are disabled\n");
2064                 return 0;
2065         }
2066
2067         ret = mutex_lock_interruptible(&dev->struct_mutex);
2068         if (ret)
2069                 return ret;
2070
2071         list_for_each_entry(ctx, &dev_priv->context_list, link)
2072                 for_each_engine(engine, dev_priv, id)
2073                         i915_dump_lrc_obj(m, ctx, engine);
2074
2075         mutex_unlock(&dev->struct_mutex);
2076
2077         return 0;
2078 }
2079
2080 static const char *swizzle_string(unsigned swizzle)
2081 {
2082         switch (swizzle) {
2083         case I915_BIT_6_SWIZZLE_NONE:
2084                 return "none";
2085         case I915_BIT_6_SWIZZLE_9:
2086                 return "bit9";
2087         case I915_BIT_6_SWIZZLE_9_10:
2088                 return "bit9/bit10";
2089         case I915_BIT_6_SWIZZLE_9_11:
2090                 return "bit9/bit11";
2091         case I915_BIT_6_SWIZZLE_9_10_11:
2092                 return "bit9/bit10/bit11";
2093         case I915_BIT_6_SWIZZLE_9_17:
2094                 return "bit9/bit17";
2095         case I915_BIT_6_SWIZZLE_9_10_17:
2096                 return "bit9/bit10/bit17";
2097         case I915_BIT_6_SWIZZLE_UNKNOWN:
2098                 return "unknown";
2099         }
2100
2101         return "bug";
2102 }
2103
2104 static int i915_swizzle_info(struct seq_file *m, void *data)
2105 {
2106         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2107
2108         intel_runtime_pm_get(dev_priv);
2109
2110         seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2111                    swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2112         seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2113                    swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2114
2115         if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) {
2116                 seq_printf(m, "DDC = 0x%08x\n",
2117                            I915_READ(DCC));
2118                 seq_printf(m, "DDC2 = 0x%08x\n",
2119                            I915_READ(DCC2));
2120                 seq_printf(m, "C0DRB3 = 0x%04x\n",
2121                            I915_READ16(C0DRB3));
2122                 seq_printf(m, "C1DRB3 = 0x%04x\n",
2123                            I915_READ16(C1DRB3));
2124         } else if (INTEL_GEN(dev_priv) >= 6) {
2125                 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2126                            I915_READ(MAD_DIMM_C0));
2127                 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2128                            I915_READ(MAD_DIMM_C1));
2129                 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2130                            I915_READ(MAD_DIMM_C2));
2131                 seq_printf(m, "TILECTL = 0x%08x\n",
2132                            I915_READ(TILECTL));
2133                 if (INTEL_GEN(dev_priv) >= 8)
2134                         seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2135                                    I915_READ(GAMTARBMODE));
2136                 else
2137                         seq_printf(m, "ARB_MODE = 0x%08x\n",
2138                                    I915_READ(ARB_MODE));
2139                 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2140                            I915_READ(DISP_ARB_CTL));
2141         }
2142
2143         if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2144                 seq_puts(m, "L-shaped memory detected\n");
2145
2146         intel_runtime_pm_put(dev_priv);
2147
2148         return 0;
2149 }
2150
2151 static int per_file_ctx(int id, void *ptr, void *data)
2152 {
2153         struct i915_gem_context *ctx = ptr;
2154         struct seq_file *m = data;
2155         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2156
2157         if (!ppgtt) {
2158                 seq_printf(m, "  no ppgtt for context %d\n",
2159                            ctx->user_handle);
2160                 return 0;
2161         }
2162
2163         if (i915_gem_context_is_default(ctx))
2164                 seq_puts(m, "  default context:\n");
2165         else
2166                 seq_printf(m, "  context %d:\n", ctx->user_handle);
2167         ppgtt->debug_dump(ppgtt, m);
2168
2169         return 0;
2170 }
2171
2172 static void gen8_ppgtt_info(struct seq_file *m,
2173                             struct drm_i915_private *dev_priv)
2174 {
2175         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2176         struct intel_engine_cs *engine;
2177         enum intel_engine_id id;
2178         int i;
2179
2180         if (!ppgtt)
2181                 return;
2182
2183         for_each_engine(engine, dev_priv, id) {
2184                 seq_printf(m, "%s\n", engine->name);
2185                 for (i = 0; i < 4; i++) {
2186                         u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
2187                         pdp <<= 32;
2188                         pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
2189                         seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2190                 }
2191         }
2192 }
2193
2194 static void gen6_ppgtt_info(struct seq_file *m,
2195                             struct drm_i915_private *dev_priv)
2196 {
2197         struct intel_engine_cs *engine;
2198         enum intel_engine_id id;
2199
2200         if (IS_GEN6(dev_priv))
2201                 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2202
2203         for_each_engine(engine, dev_priv, id) {
2204                 seq_printf(m, "%s\n", engine->name);
2205                 if (IS_GEN7(dev_priv))
2206                         seq_printf(m, "GFX_MODE: 0x%08x\n",
2207                                    I915_READ(RING_MODE_GEN7(engine)));
2208                 seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
2209                            I915_READ(RING_PP_DIR_BASE(engine)));
2210                 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
2211                            I915_READ(RING_PP_DIR_BASE_READ(engine)));
2212                 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
2213                            I915_READ(RING_PP_DIR_DCLV(engine)));
2214         }
2215         if (dev_priv->mm.aliasing_ppgtt) {
2216                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2217
2218                 seq_puts(m, "aliasing PPGTT:\n");
2219                 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2220
2221                 ppgtt->debug_dump(ppgtt, m);
2222         }
2223
2224         seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2225 }
2226
2227 static int i915_ppgtt_info(struct seq_file *m, void *data)
2228 {
2229         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2230         struct drm_device *dev = &dev_priv->drm;
2231         struct drm_file *file;
2232         int ret;
2233
2234         mutex_lock(&dev->filelist_mutex);
2235         ret = mutex_lock_interruptible(&dev->struct_mutex);
2236         if (ret)
2237                 goto out_unlock;
2238
2239         intel_runtime_pm_get(dev_priv);
2240
2241         if (INTEL_GEN(dev_priv) >= 8)
2242                 gen8_ppgtt_info(m, dev_priv);
2243         else if (INTEL_GEN(dev_priv) >= 6)
2244                 gen6_ppgtt_info(m, dev_priv);
2245
2246         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2247                 struct drm_i915_file_private *file_priv = file->driver_priv;
2248                 struct task_struct *task;
2249
2250                 task = get_pid_task(file->pid, PIDTYPE_PID);
2251                 if (!task) {
2252                         ret = -ESRCH;
2253                         goto out_rpm;
2254                 }
2255                 seq_printf(m, "\nproc: %s\n", task->comm);
2256                 put_task_struct(task);
2257                 idr_for_each(&file_priv->context_idr, per_file_ctx,
2258                              (void *)(unsigned long)m);
2259         }
2260
2261 out_rpm:
2262         intel_runtime_pm_put(dev_priv);
2263         mutex_unlock(&dev->struct_mutex);
2264 out_unlock:
2265         mutex_unlock(&dev->filelist_mutex);
2266         return ret;
2267 }
2268
2269 static int count_irq_waiters(struct drm_i915_private *i915)
2270 {
2271         struct intel_engine_cs *engine;
2272         enum intel_engine_id id;
2273         int count = 0;
2274
2275         for_each_engine(engine, i915, id)
2276                 count += intel_engine_has_waiter(engine);
2277
2278         return count;
2279 }
2280
2281 static const char *rps_power_to_str(unsigned int power)
2282 {
2283         static const char * const strings[] = {
2284                 [LOW_POWER] = "low power",
2285                 [BETWEEN] = "mixed",
2286                 [HIGH_POWER] = "high power",
2287         };
2288
2289         if (power >= ARRAY_SIZE(strings) || !strings[power])
2290                 return "unknown";
2291
2292         return strings[power];
2293 }
2294
2295 static int i915_rps_boost_info(struct seq_file *m, void *data)
2296 {
2297         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2298         struct drm_device *dev = &dev_priv->drm;
2299         struct drm_file *file;
2300
2301         seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2302         seq_printf(m, "GPU busy? %s [%x]\n",
2303                    yesno(dev_priv->gt.awake), dev_priv->gt.active_engines);
2304         seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2305         seq_printf(m, "Frequency requested %d\n",
2306                    intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
2307         seq_printf(m, "  min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2308                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2309                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2310                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2311                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2312         seq_printf(m, "  idle:%d, efficient:%d, boost:%d\n",
2313                    intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
2314                    intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2315                    intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
2316
2317         mutex_lock(&dev->filelist_mutex);
2318         spin_lock(&dev_priv->rps.client_lock);
2319         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2320                 struct drm_i915_file_private *file_priv = file->driver_priv;
2321                 struct task_struct *task;
2322
2323                 rcu_read_lock();
2324                 task = pid_task(file->pid, PIDTYPE_PID);
2325                 seq_printf(m, "%s [%d]: %d boosts%s\n",
2326                            task ? task->comm : "<unknown>",
2327                            task ? task->pid : -1,
2328                            file_priv->rps.boosts,
2329                            list_empty(&file_priv->rps.link) ? "" : ", active");
2330                 rcu_read_unlock();
2331         }
2332         seq_printf(m, "Kernel (anonymous) boosts: %d\n", dev_priv->rps.boosts);
2333         spin_unlock(&dev_priv->rps.client_lock);
2334         mutex_unlock(&dev->filelist_mutex);
2335
2336         if (INTEL_GEN(dev_priv) >= 6 &&
2337             dev_priv->rps.enabled &&
2338             dev_priv->gt.active_engines) {
2339                 u32 rpup, rpupei;
2340                 u32 rpdown, rpdownei;
2341
2342                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2343                 rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK;
2344                 rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK;
2345                 rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK;
2346                 rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK;
2347                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2348
2349                 seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n",
2350                            rps_power_to_str(dev_priv->rps.power));
2351                 seq_printf(m, "  Avg. up: %d%% [above threshold? %d%%]\n",
2352                            100 * rpup / rpupei,
2353                            dev_priv->rps.up_threshold);
2354                 seq_printf(m, "  Avg. down: %d%% [below threshold? %d%%]\n",
2355                            100 * rpdown / rpdownei,
2356                            dev_priv->rps.down_threshold);
2357         } else {
2358                 seq_puts(m, "\nRPS Autotuning inactive\n");
2359         }
2360
2361         return 0;
2362 }
2363
2364 static int i915_llc(struct seq_file *m, void *data)
2365 {
2366         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2367         const bool edram = INTEL_GEN(dev_priv) > 8;
2368
2369         seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv)));
2370         seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
2371                    intel_uncore_edram_size(dev_priv)/1024/1024);
2372
2373         return 0;
2374 }
2375
2376 static int i915_guc_load_status_info(struct seq_file *m, void *data)
2377 {
2378         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2379         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
2380         u32 tmp, i;
2381
2382         if (!HAS_GUC_UCODE(dev_priv))
2383                 return 0;
2384
2385         seq_printf(m, "GuC firmware status:\n");
2386         seq_printf(m, "\tpath: %s\n",
2387                 guc_fw->guc_fw_path);
2388         seq_printf(m, "\tfetch: %s\n",
2389                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
2390         seq_printf(m, "\tload: %s\n",
2391                 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
2392         seq_printf(m, "\tversion wanted: %d.%d\n",
2393                 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2394         seq_printf(m, "\tversion found: %d.%d\n",
2395                 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
2396         seq_printf(m, "\theader: offset is %d; size = %d\n",
2397                 guc_fw->header_offset, guc_fw->header_size);
2398         seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2399                 guc_fw->ucode_offset, guc_fw->ucode_size);
2400         seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2401                 guc_fw->rsa_offset, guc_fw->rsa_size);
2402
2403         tmp = I915_READ(GUC_STATUS);
2404
2405         seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2406         seq_printf(m, "\tBootrom status = 0x%x\n",
2407                 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2408         seq_printf(m, "\tuKernel status = 0x%x\n",
2409                 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2410         seq_printf(m, "\tMIA Core status = 0x%x\n",
2411                 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2412         seq_puts(m, "\nScratch registers:\n");
2413         for (i = 0; i < 16; i++)
2414                 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2415
2416         return 0;
2417 }
2418
2419 static void i915_guc_log_info(struct seq_file *m,
2420                               struct drm_i915_private *dev_priv)
2421 {
2422         struct intel_guc *guc = &dev_priv->guc;
2423
2424         seq_puts(m, "\nGuC logging stats:\n");
2425
2426         seq_printf(m, "\tISR:   flush count %10u, overflow count %10u\n",
2427                    guc->log.flush_count[GUC_ISR_LOG_BUFFER],
2428                    guc->log.total_overflow_count[GUC_ISR_LOG_BUFFER]);
2429
2430         seq_printf(m, "\tDPC:   flush count %10u, overflow count %10u\n",
2431                    guc->log.flush_count[GUC_DPC_LOG_BUFFER],
2432                    guc->log.total_overflow_count[GUC_DPC_LOG_BUFFER]);
2433
2434         seq_printf(m, "\tCRASH: flush count %10u, overflow count %10u\n",
2435                    guc->log.flush_count[GUC_CRASH_DUMP_LOG_BUFFER],
2436                    guc->log.total_overflow_count[GUC_CRASH_DUMP_LOG_BUFFER]);
2437
2438         seq_printf(m, "\tTotal flush interrupt count: %u\n",
2439                    guc->log.flush_interrupt_count);
2440
2441         seq_printf(m, "\tCapture miss count: %u\n",
2442                    guc->log.capture_miss_count);
2443 }
2444
2445 static void i915_guc_client_info(struct seq_file *m,
2446                                  struct drm_i915_private *dev_priv,
2447                                  struct i915_guc_client *client)
2448 {
2449         struct intel_engine_cs *engine;
2450         enum intel_engine_id id;
2451         uint64_t tot = 0;
2452
2453         seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2454                 client->priority, client->ctx_index, client->proc_desc_offset);
2455         seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2456                 client->doorbell_id, client->doorbell_offset, client->cookie);
2457         seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2458                 client->wq_size, client->wq_offset, client->wq_tail);
2459
2460         seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space);
2461         seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2462         seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2463
2464         for_each_engine(engine, dev_priv, id) {
2465                 u64 submissions = client->submissions[id];
2466                 tot += submissions;
2467                 seq_printf(m, "\tSubmissions: %llu %s\n",
2468                                 submissions, engine->name);
2469         }
2470         seq_printf(m, "\tTotal: %llu\n", tot);
2471 }
2472
2473 static int i915_guc_info(struct seq_file *m, void *data)
2474 {
2475         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2476         struct drm_device *dev = &dev_priv->drm;
2477         struct intel_guc guc;
2478         struct i915_guc_client client = {};
2479         struct intel_engine_cs *engine;
2480         enum intel_engine_id id;
2481         u64 total = 0;
2482
2483         if (!HAS_GUC_SCHED(dev_priv))
2484                 return 0;
2485
2486         if (mutex_lock_interruptible(&dev->struct_mutex))
2487                 return 0;
2488
2489         /* Take a local copy of the GuC data, so we can dump it at leisure */
2490         guc = dev_priv->guc;
2491         if (guc.execbuf_client)
2492                 client = *guc.execbuf_client;
2493
2494         mutex_unlock(&dev->struct_mutex);
2495
2496         seq_printf(m, "Doorbell map:\n");
2497         seq_printf(m, "\t%*pb\n", GUC_MAX_DOORBELLS, guc.doorbell_bitmap);
2498         seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc.db_cacheline);
2499
2500         seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
2501         seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
2502         seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
2503         seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
2504         seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
2505
2506         seq_printf(m, "\nGuC submissions:\n");
2507         for_each_engine(engine, dev_priv, id) {
2508                 u64 submissions = guc.submissions[id];
2509                 total += submissions;
2510                 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",
2511                         engine->name, submissions, guc.last_seqno[id]);
2512         }
2513         seq_printf(m, "\t%s: %llu\n", "Total", total);
2514
2515         seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
2516         i915_guc_client_info(m, dev_priv, &client);
2517
2518         i915_guc_log_info(m, dev_priv);
2519
2520         /* Add more as required ... */
2521
2522         return 0;
2523 }
2524
2525 static int i915_guc_log_dump(struct seq_file *m, void *data)
2526 {
2527         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2528         struct drm_i915_gem_object *obj;
2529         int i = 0, pg;
2530
2531         if (!dev_priv->guc.log.vma)
2532                 return 0;
2533
2534         obj = dev_priv->guc.log.vma->obj;
2535         for (pg = 0; pg < obj->base.size / PAGE_SIZE; pg++) {
2536                 u32 *log = kmap_atomic(i915_gem_object_get_page(obj, pg));
2537
2538                 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2539                         seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2540                                    *(log + i), *(log + i + 1),
2541                                    *(log + i + 2), *(log + i + 3));
2542
2543                 kunmap_atomic(log);
2544         }
2545
2546         seq_putc(m, '\n');
2547
2548         return 0;
2549 }
2550
2551 static int i915_edp_psr_status(struct seq_file *m, void *data)
2552 {
2553         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2554         u32 psrperf = 0;
2555         u32 stat[3];
2556         enum pipe pipe;
2557         bool enabled = false;
2558
2559         if (!HAS_PSR(dev_priv)) {
2560                 seq_puts(m, "PSR not supported\n");
2561                 return 0;
2562         }
2563
2564         intel_runtime_pm_get(dev_priv);
2565
2566         mutex_lock(&dev_priv->psr.lock);
2567         seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2568         seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2569         seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2570         seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2571         seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2572                    dev_priv->psr.busy_frontbuffer_bits);
2573         seq_printf(m, "Re-enable work scheduled: %s\n",
2574                    yesno(work_busy(&dev_priv->psr.work.work)));
2575
2576         if (HAS_DDI(dev_priv))
2577                 enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2578         else {
2579                 for_each_pipe(dev_priv, pipe) {
2580                         enum transcoder cpu_transcoder =
2581                                 intel_pipe_to_cpu_transcoder(dev_priv, pipe);
2582                         enum intel_display_power_domain power_domain;
2583
2584                         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
2585                         if (!intel_display_power_get_if_enabled(dev_priv,
2586                                                                 power_domain))
2587                                 continue;
2588
2589                         stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2590                                 VLV_EDP_PSR_CURR_STATE_MASK;
2591                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2592                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2593                                 enabled = true;
2594
2595                         intel_display_power_put(dev_priv, power_domain);
2596                 }
2597         }
2598
2599         seq_printf(m, "Main link in standby mode: %s\n",
2600                    yesno(dev_priv->psr.link_standby));
2601
2602         seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2603
2604         if (!HAS_DDI(dev_priv))
2605                 for_each_pipe(dev_priv, pipe) {
2606                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2607                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2608                                 seq_printf(m, " pipe %c", pipe_name(pipe));
2609                 }
2610         seq_puts(m, "\n");
2611
2612         /*
2613          * VLV/CHV PSR has no kind of performance counter
2614          * SKL+ Perf counter is reset to 0 everytime DC state is entered
2615          */
2616         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2617                 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
2618                         EDP_PSR_PERF_CNT_MASK;
2619
2620                 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2621         }
2622         mutex_unlock(&dev_priv->psr.lock);
2623
2624         intel_runtime_pm_put(dev_priv);
2625         return 0;
2626 }
2627
2628 static int i915_sink_crc(struct seq_file *m, void *data)
2629 {
2630         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2631         struct drm_device *dev = &dev_priv->drm;
2632         struct intel_connector *connector;
2633         struct intel_dp *intel_dp = NULL;
2634         int ret;
2635         u8 crc[6];
2636
2637         drm_modeset_lock_all(dev);
2638         for_each_intel_connector(dev, connector) {
2639                 struct drm_crtc *crtc;
2640
2641                 if (!connector->base.state->best_encoder)
2642                         continue;
2643
2644                 crtc = connector->base.state->crtc;
2645                 if (!crtc->state->active)
2646                         continue;
2647
2648                 if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
2649                         continue;
2650
2651                 intel_dp = enc_to_intel_dp(connector->base.state->best_encoder);
2652
2653                 ret = intel_dp_sink_crc(intel_dp, crc);
2654                 if (ret)
2655                         goto out;
2656
2657                 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2658                            crc[0], crc[1], crc[2],
2659                            crc[3], crc[4], crc[5]);
2660                 goto out;
2661         }
2662         ret = -ENODEV;
2663 out:
2664         drm_modeset_unlock_all(dev);
2665         return ret;
2666 }
2667
2668 static int i915_energy_uJ(struct seq_file *m, void *data)
2669 {
2670         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2671         u64 power;
2672         u32 units;
2673
2674         if (INTEL_GEN(dev_priv) < 6)
2675                 return -ENODEV;
2676
2677         intel_runtime_pm_get(dev_priv);
2678
2679         rdmsrl(MSR_RAPL_POWER_UNIT, power);
2680         power = (power & 0x1f00) >> 8;
2681         units = 1000000 / (1 << power); /* convert to uJ */
2682         power = I915_READ(MCH_SECP_NRG_STTS);
2683         power *= units;
2684
2685         intel_runtime_pm_put(dev_priv);
2686
2687         seq_printf(m, "%llu", (long long unsigned)power);
2688
2689         return 0;
2690 }
2691
2692 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2693 {
2694         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2695         struct pci_dev *pdev = dev_priv->drm.pdev;
2696
2697         if (!HAS_RUNTIME_PM(dev_priv))
2698                 seq_puts(m, "Runtime power management not supported\n");
2699
2700         seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
2701         seq_printf(m, "IRQs disabled: %s\n",
2702                    yesno(!intel_irqs_enabled(dev_priv)));
2703 #ifdef CONFIG_PM
2704         seq_printf(m, "Usage count: %d\n",
2705                    atomic_read(&dev_priv->drm.dev->power.usage_count));
2706 #else
2707         seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2708 #endif
2709         seq_printf(m, "PCI device power state: %s [%d]\n",
2710                    pci_power_name(pdev->current_state),
2711                    pdev->current_state);
2712
2713         return 0;
2714 }
2715
2716 static int i915_power_domain_info(struct seq_file *m, void *unused)
2717 {
2718         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2719         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2720         int i;
2721
2722         mutex_lock(&power_domains->lock);
2723
2724         seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2725         for (i = 0; i < power_domains->power_well_count; i++) {
2726                 struct i915_power_well *power_well;
2727                 enum intel_display_power_domain power_domain;
2728
2729                 power_well = &power_domains->power_wells[i];
2730                 seq_printf(m, "%-25s %d\n", power_well->name,
2731                            power_well->count);
2732
2733                 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2734                      power_domain++) {
2735                         if (!(BIT(power_domain) & power_well->domains))
2736                                 continue;
2737
2738                         seq_printf(m, "  %-23s %d\n",
2739                                  intel_display_power_domain_str(power_domain),
2740                                  power_domains->domain_use_count[power_domain]);
2741                 }
2742         }
2743
2744         mutex_unlock(&power_domains->lock);
2745
2746         return 0;
2747 }
2748
2749 static int i915_dmc_info(struct seq_file *m, void *unused)
2750 {
2751         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2752         struct intel_csr *csr;
2753
2754         if (!HAS_CSR(dev_priv)) {
2755                 seq_puts(m, "not supported\n");
2756                 return 0;
2757         }
2758
2759         csr = &dev_priv->csr;
2760
2761         intel_runtime_pm_get(dev_priv);
2762
2763         seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2764         seq_printf(m, "path: %s\n", csr->fw_path);
2765
2766         if (!csr->dmc_payload)
2767                 goto out;
2768
2769         seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2770                    CSR_VERSION_MINOR(csr->version));
2771
2772         if (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6)) {
2773                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2774                            I915_READ(SKL_CSR_DC3_DC5_COUNT));
2775                 seq_printf(m, "DC5 -> DC6 count: %d\n",
2776                            I915_READ(SKL_CSR_DC5_DC6_COUNT));
2777         } else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) {
2778                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2779                            I915_READ(BXT_CSR_DC3_DC5_COUNT));
2780         }
2781
2782 out:
2783         seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2784         seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2785         seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2786
2787         intel_runtime_pm_put(dev_priv);
2788
2789         return 0;
2790 }
2791
2792 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2793                                  struct drm_display_mode *mode)
2794 {
2795         int i;
2796
2797         for (i = 0; i < tabs; i++)
2798                 seq_putc(m, '\t');
2799
2800         seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2801                    mode->base.id, mode->name,
2802                    mode->vrefresh, mode->clock,
2803                    mode->hdisplay, mode->hsync_start,
2804                    mode->hsync_end, mode->htotal,
2805                    mode->vdisplay, mode->vsync_start,
2806                    mode->vsync_end, mode->vtotal,
2807                    mode->type, mode->flags);
2808 }
2809
2810 static void intel_encoder_info(struct seq_file *m,
2811                                struct intel_crtc *intel_crtc,
2812                                struct intel_encoder *intel_encoder)
2813 {
2814         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2815         struct drm_device *dev = &dev_priv->drm;
2816         struct drm_crtc *crtc = &intel_crtc->base;
2817         struct intel_connector *intel_connector;
2818         struct drm_encoder *encoder;
2819
2820         encoder = &intel_encoder->base;
2821         seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2822                    encoder->base.id, encoder->name);
2823         for_each_connector_on_encoder(dev, encoder, intel_connector) {
2824                 struct drm_connector *connector = &intel_connector->base;
2825                 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2826                            connector->base.id,
2827                            connector->name,
2828                            drm_get_connector_status_name(connector->status));
2829                 if (connector->status == connector_status_connected) {
2830                         struct drm_display_mode *mode = &crtc->mode;
2831                         seq_printf(m, ", mode:\n");
2832                         intel_seq_print_mode(m, 2, mode);
2833                 } else {
2834                         seq_putc(m, '\n');
2835                 }
2836         }
2837 }
2838
2839 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2840 {
2841         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2842         struct drm_device *dev = &dev_priv->drm;
2843         struct drm_crtc *crtc = &intel_crtc->base;
2844         struct intel_encoder *intel_encoder;
2845         struct drm_plane_state *plane_state = crtc->primary->state;
2846         struct drm_framebuffer *fb = plane_state->fb;
2847
2848         if (fb)
2849                 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2850                            fb->base.id, plane_state->src_x >> 16,
2851                            plane_state->src_y >> 16, fb->width, fb->height);
2852         else
2853                 seq_puts(m, "\tprimary plane disabled\n");
2854         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2855                 intel_encoder_info(m, intel_crtc, intel_encoder);
2856 }
2857
2858 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2859 {
2860         struct drm_display_mode *mode = panel->fixed_mode;
2861
2862         seq_printf(m, "\tfixed mode:\n");
2863         intel_seq_print_mode(m, 2, mode);
2864 }
2865
2866 static void intel_dp_info(struct seq_file *m,
2867                           struct intel_connector *intel_connector)
2868 {
2869         struct intel_encoder *intel_encoder = intel_connector->encoder;
2870         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2871
2872         seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2873         seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2874         if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
2875                 intel_panel_info(m, &intel_connector->panel);
2876
2877         drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports,
2878                                 &intel_dp->aux);
2879 }
2880
2881 static void intel_hdmi_info(struct seq_file *m,
2882                             struct intel_connector *intel_connector)
2883 {
2884         struct intel_encoder *intel_encoder = intel_connector->encoder;
2885         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2886
2887         seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
2888 }
2889
2890 static void intel_lvds_info(struct seq_file *m,
2891                             struct intel_connector *intel_connector)
2892 {
2893         intel_panel_info(m, &intel_connector->panel);
2894 }
2895
2896 static void intel_connector_info(struct seq_file *m,
2897                                  struct drm_connector *connector)
2898 {
2899         struct intel_connector *intel_connector = to_intel_connector(connector);
2900         struct intel_encoder *intel_encoder = intel_connector->encoder;
2901         struct drm_display_mode *mode;
2902
2903         seq_printf(m, "connector %d: type %s, status: %s\n",
2904                    connector->base.id, connector->name,
2905                    drm_get_connector_status_name(connector->status));
2906         if (connector->status == connector_status_connected) {
2907                 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2908                 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2909                            connector->display_info.width_mm,
2910                            connector->display_info.height_mm);
2911                 seq_printf(m, "\tsubpixel order: %s\n",
2912                            drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2913                 seq_printf(m, "\tCEA rev: %d\n",
2914                            connector->display_info.cea_rev);
2915         }
2916
2917         if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
2918                 return;
2919
2920         switch (connector->connector_type) {
2921         case DRM_MODE_CONNECTOR_DisplayPort:
2922         case DRM_MODE_CONNECTOR_eDP:
2923                 intel_dp_info(m, intel_connector);
2924                 break;
2925         case DRM_MODE_CONNECTOR_LVDS:
2926                 if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2927                         intel_lvds_info(m, intel_connector);
2928                 break;
2929         case DRM_MODE_CONNECTOR_HDMIA:
2930                 if (intel_encoder->type == INTEL_OUTPUT_HDMI ||
2931                     intel_encoder->type == INTEL_OUTPUT_UNKNOWN)
2932                         intel_hdmi_info(m, intel_connector);
2933                 break;
2934         default:
2935                 break;
2936         }
2937
2938         seq_printf(m, "\tmodes:\n");
2939         list_for_each_entry(mode, &connector->modes, head)
2940                 intel_seq_print_mode(m, 2, mode);
2941 }
2942
2943 static bool cursor_active(struct drm_i915_private *dev_priv, int pipe)
2944 {
2945         u32 state;
2946
2947         if (IS_845G(dev_priv) || IS_I865G(dev_priv))
2948                 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
2949         else
2950                 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2951
2952         return state;
2953 }
2954
2955 static bool cursor_position(struct drm_i915_private *dev_priv,
2956                             int pipe, int *x, int *y)
2957 {
2958         u32 pos;
2959
2960         pos = I915_READ(CURPOS(pipe));
2961
2962         *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2963         if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2964                 *x = -*x;
2965
2966         *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2967         if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2968                 *y = -*y;
2969
2970         return cursor_active(dev_priv, pipe);
2971 }
2972
2973 static const char *plane_type(enum drm_plane_type type)
2974 {
2975         switch (type) {
2976         case DRM_PLANE_TYPE_OVERLAY:
2977                 return "OVL";
2978         case DRM_PLANE_TYPE_PRIMARY:
2979                 return "PRI";
2980         case DRM_PLANE_TYPE_CURSOR:
2981                 return "CUR";
2982         /*
2983          * Deliberately omitting default: to generate compiler warnings
2984          * when a new drm_plane_type gets added.
2985          */
2986         }
2987
2988         return "unknown";
2989 }
2990
2991 static const char *plane_rotation(unsigned int rotation)
2992 {
2993         static char buf[48];
2994         /*
2995          * According to doc only one DRM_ROTATE_ is allowed but this
2996          * will print them all to visualize if the values are misused
2997          */
2998         snprintf(buf, sizeof(buf),
2999                  "%s%s%s%s%s%s(0x%08x)",
3000                  (rotation & DRM_ROTATE_0) ? "0 " : "",
3001                  (rotation & DRM_ROTATE_90) ? "90 " : "",
3002                  (rotation & DRM_ROTATE_180) ? "180 " : "",
3003                  (rotation & DRM_ROTATE_270) ? "270 " : "",
3004                  (rotation & DRM_REFLECT_X) ? "FLIPX " : "",
3005                  (rotation & DRM_REFLECT_Y) ? "FLIPY " : "",
3006                  rotation);
3007
3008         return buf;
3009 }
3010
3011 static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3012 {
3013         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3014         struct drm_device *dev = &dev_priv->drm;
3015         struct intel_plane *intel_plane;
3016
3017         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3018                 struct drm_plane_state *state;
3019                 struct drm_plane *plane = &intel_plane->base;
3020                 char *format_name;
3021
3022                 if (!plane->state) {
3023                         seq_puts(m, "plane->state is NULL!\n");
3024                         continue;
3025                 }
3026
3027                 state = plane->state;
3028
3029                 if (state->fb) {
3030                         format_name = drm_get_format_name(state->fb->pixel_format);
3031                 } else {
3032                         format_name = kstrdup("N/A", GFP_KERNEL);
3033                 }
3034
3035                 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3036                            plane->base.id,
3037                            plane_type(intel_plane->base.type),
3038                            state->crtc_x, state->crtc_y,
3039                            state->crtc_w, state->crtc_h,
3040                            (state->src_x >> 16),
3041                            ((state->src_x & 0xffff) * 15625) >> 10,
3042                            (state->src_y >> 16),
3043                            ((state->src_y & 0xffff) * 15625) >> 10,
3044                            (state->src_w >> 16),
3045                            ((state->src_w & 0xffff) * 15625) >> 10,
3046                            (state->src_h >> 16),
3047                            ((state->src_h & 0xffff) * 15625) >> 10,
3048                            format_name,
3049                            plane_rotation(state->rotation));
3050
3051                 kfree(format_name);
3052         }
3053 }
3054
3055 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3056 {
3057         struct intel_crtc_state *pipe_config;
3058         int num_scalers = intel_crtc->num_scalers;
3059         int i;
3060
3061         pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3062
3063         /* Not all platformas have a scaler */
3064         if (num_scalers) {
3065                 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3066                            num_scalers,
3067                            pipe_config->scaler_state.scaler_users,
3068                            pipe_config->scaler_state.scaler_id);
3069
3070                 for (i = 0; i < SKL_NUM_SCALERS; i++) {
3071                         struct intel_scaler *sc =
3072                                         &pipe_config->scaler_state.scalers[i];
3073
3074                         seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3075                                    i, yesno(sc->in_use), sc->mode);
3076                 }
3077                 seq_puts(m, "\n");
3078         } else {
3079                 seq_puts(m, "\tNo scalers available on this platform\n");
3080         }
3081 }
3082
3083 static int i915_display_info(struct seq_file *m, void *unused)
3084 {
3085         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3086         struct drm_device *dev = &dev_priv->drm;
3087         struct intel_crtc *crtc;
3088         struct drm_connector *connector;
3089
3090         intel_runtime_pm_get(dev_priv);
3091         drm_modeset_lock_all(dev);
3092         seq_printf(m, "CRTC info\n");
3093         seq_printf(m, "---------\n");
3094         for_each_intel_crtc(dev, crtc) {
3095                 bool active;
3096                 struct intel_crtc_state *pipe_config;
3097                 int x, y;
3098
3099                 pipe_config = to_intel_crtc_state(crtc->base.state);
3100
3101                 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3102                            crtc->base.base.id, pipe_name(crtc->pipe),
3103                            yesno(pipe_config->base.active),
3104                            pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3105                            yesno(pipe_config->dither), pipe_config->pipe_bpp);
3106
3107                 if (pipe_config->base.active) {
3108                         intel_crtc_info(m, crtc);
3109
3110                         active = cursor_position(dev_priv, crtc->pipe, &x, &y);
3111                         seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
3112                                    yesno(crtc->cursor_base),
3113                                    x, y, crtc->base.cursor->state->crtc_w,
3114                                    crtc->base.cursor->state->crtc_h,
3115                                    crtc->cursor_addr, yesno(active));
3116                         intel_scaler_info(m, crtc);
3117                         intel_plane_info(m, crtc);
3118                 }
3119
3120                 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3121                            yesno(!crtc->cpu_fifo_underrun_disabled),
3122                            yesno(!crtc->pch_fifo_underrun_disabled));
3123         }
3124
3125         seq_printf(m, "\n");
3126         seq_printf(m, "Connector info\n");
3127         seq_printf(m, "--------------\n");
3128         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3129                 intel_connector_info(m, connector);
3130         }
3131         drm_modeset_unlock_all(dev);
3132         intel_runtime_pm_put(dev_priv);
3133
3134         return 0;
3135 }
3136
3137 static int i915_engine_info(struct seq_file *m, void *unused)
3138 {
3139         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3140         struct intel_engine_cs *engine;
3141         enum intel_engine_id id;
3142
3143         intel_runtime_pm_get(dev_priv);
3144
3145         for_each_engine(engine, dev_priv, id) {
3146                 struct intel_breadcrumbs *b = &engine->breadcrumbs;
3147                 struct drm_i915_gem_request *rq;
3148                 struct rb_node *rb;
3149                 u64 addr;
3150
3151                 seq_printf(m, "%s\n", engine->name);
3152                 seq_printf(m, "\tcurrent seqno %x, last %x, hangcheck %x [score %d]\n",
3153                            intel_engine_get_seqno(engine),
3154                            engine->last_submitted_seqno,
3155                            engine->hangcheck.seqno,
3156                            engine->hangcheck.score);
3157
3158                 rcu_read_lock();
3159
3160                 seq_printf(m, "\tRequests:\n");
3161
3162                 rq = list_first_entry(&engine->request_list,
3163                                 struct drm_i915_gem_request, link);
3164                 if (&rq->link != &engine->request_list)
3165                         print_request(m, rq, "\t\tfirst  ");
3166
3167                 rq = list_last_entry(&engine->request_list,
3168                                 struct drm_i915_gem_request, link);
3169                 if (&rq->link != &engine->request_list)
3170                         print_request(m, rq, "\t\tlast   ");
3171
3172                 rq = i915_gem_find_active_request(engine);
3173                 if (rq) {
3174                         print_request(m, rq, "\t\tactive ");
3175                         seq_printf(m,
3176                                    "\t\t[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]\n",
3177                                    rq->head, rq->postfix, rq->tail,
3178                                    rq->batch ? upper_32_bits(rq->batch->node.start) : ~0u,
3179                                    rq->batch ? lower_32_bits(rq->batch->node.start) : ~0u);
3180                 }
3181
3182                 seq_printf(m, "\tRING_START: 0x%08x [0x%08x]\n",
3183                            I915_READ(RING_START(engine->mmio_base)),
3184                            rq ? i915_ggtt_offset(rq->ring->vma) : 0);
3185                 seq_printf(m, "\tRING_HEAD:  0x%08x [0x%08x]\n",
3186                            I915_READ(RING_HEAD(engine->mmio_base)) & HEAD_ADDR,
3187                            rq ? rq->ring->head : 0);
3188                 seq_printf(m, "\tRING_TAIL:  0x%08x [0x%08x]\n",
3189                            I915_READ(RING_TAIL(engine->mmio_base)) & TAIL_ADDR,
3190                            rq ? rq->ring->tail : 0);
3191                 seq_printf(m, "\tRING_CTL:   0x%08x [%s]\n",
3192                            I915_READ(RING_CTL(engine->mmio_base)),
3193                            I915_READ(RING_CTL(engine->mmio_base)) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? "waiting" : "");
3194
3195                 rcu_read_unlock();
3196
3197                 addr = intel_engine_get_active_head(engine);
3198                 seq_printf(m, "\tACTHD:  0x%08x_%08x\n",
3199                            upper_32_bits(addr), lower_32_bits(addr));
3200                 addr = intel_engine_get_last_batch_head(engine);
3201                 seq_printf(m, "\tBBADDR: 0x%08x_%08x\n",
3202                            upper_32_bits(addr), lower_32_bits(addr));
3203
3204                 if (i915.enable_execlists) {
3205                         u32 ptr, read, write;
3206
3207                         seq_printf(m, "\tExeclist status: 0x%08x %08x\n",
3208                                    I915_READ(RING_EXECLIST_STATUS_LO(engine)),
3209                                    I915_READ(RING_EXECLIST_STATUS_HI(engine)));
3210
3211                         ptr = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
3212                         read = GEN8_CSB_READ_PTR(ptr);
3213                         write = GEN8_CSB_WRITE_PTR(ptr);
3214                         seq_printf(m, "\tExeclist CSB read %d, write %d\n",
3215                                    read, write);
3216                         if (read >= GEN8_CSB_ENTRIES)
3217                                 read = 0;
3218                         if (write >= GEN8_CSB_ENTRIES)
3219                                 write = 0;
3220                         if (read > write)
3221                                 write += GEN8_CSB_ENTRIES;
3222                         while (read < write) {
3223                                 unsigned int idx = ++read % GEN8_CSB_ENTRIES;
3224
3225                                 seq_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n",
3226                                            idx,
3227                                            I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, idx)),
3228                                            I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, idx)));
3229                         }
3230
3231                         rcu_read_lock();
3232                         rq = READ_ONCE(engine->execlist_port[0].request);
3233                         if (rq)
3234                                 print_request(m, rq, "\t\tELSP[0] ");
3235                         else
3236                                 seq_printf(m, "\t\tELSP[0] idle\n");
3237                         rq = READ_ONCE(engine->execlist_port[1].request);
3238                         if (rq)
3239                                 print_request(m, rq, "\t\tELSP[1] ");
3240                         else
3241                                 seq_printf(m, "\t\tELSP[1] idle\n");
3242                         rcu_read_unlock();
3243                 } else if (INTEL_GEN(dev_priv) > 6) {
3244                         seq_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
3245                                    I915_READ(RING_PP_DIR_BASE(engine)));
3246                         seq_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n",
3247                                    I915_READ(RING_PP_DIR_BASE_READ(engine)));
3248                         seq_printf(m, "\tPP_DIR_DCLV: 0x%08x\n",
3249                                    I915_READ(RING_PP_DIR_DCLV(engine)));
3250                 }
3251
3252                 spin_lock(&b->lock);
3253                 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
3254                         struct intel_wait *w = container_of(rb, typeof(*w), node);
3255
3256                         seq_printf(m, "\t%s [%d] waiting for %x\n",
3257                                    w->tsk->comm, w->tsk->pid, w->seqno);
3258                 }
3259                 spin_unlock(&b->lock);
3260
3261                 seq_puts(m, "\n");
3262         }
3263
3264         intel_runtime_pm_put(dev_priv);
3265
3266         return 0;
3267 }
3268
3269 static int i915_semaphore_status(struct seq_file *m, void *unused)
3270 {
3271         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3272         struct drm_device *dev = &dev_priv->drm;
3273         struct intel_engine_cs *engine;
3274         int num_rings = INTEL_INFO(dev_priv)->num_rings;
3275         enum intel_engine_id id;
3276         int j, ret;
3277
3278         if (!i915.semaphores) {
3279                 seq_puts(m, "Semaphores are disabled\n");
3280                 return 0;
3281         }
3282
3283         ret = mutex_lock_interruptible(&dev->struct_mutex);
3284         if (ret)
3285                 return ret;
3286         intel_runtime_pm_get(dev_priv);
3287
3288         if (IS_BROADWELL(dev_priv)) {
3289                 struct page *page;
3290                 uint64_t *seqno;
3291
3292                 page = i915_gem_object_get_page(dev_priv->semaphore->obj, 0);
3293
3294                 seqno = (uint64_t *)kmap_atomic(page);
3295                 for_each_engine(engine, dev_priv, id) {
3296                         uint64_t offset;
3297
3298                         seq_printf(m, "%s\n", engine->name);
3299
3300                         seq_puts(m, "  Last signal:");
3301                         for (j = 0; j < num_rings; j++) {
3302                                 offset = id * I915_NUM_ENGINES + j;
3303                                 seq_printf(m, "0x%08llx (0x%02llx) ",
3304                                            seqno[offset], offset * 8);
3305                         }
3306                         seq_putc(m, '\n');
3307
3308                         seq_puts(m, "  Last wait:  ");
3309                         for (j = 0; j < num_rings; j++) {
3310                                 offset = id + (j * I915_NUM_ENGINES);
3311                                 seq_printf(m, "0x%08llx (0x%02llx) ",
3312                                            seqno[offset], offset * 8);
3313                         }
3314                         seq_putc(m, '\n');
3315
3316                 }
3317                 kunmap_atomic(seqno);
3318         } else {
3319                 seq_puts(m, "  Last signal:");
3320                 for_each_engine(engine, dev_priv, id)
3321                         for (j = 0; j < num_rings; j++)
3322                                 seq_printf(m, "0x%08x\n",
3323                                            I915_READ(engine->semaphore.mbox.signal[j]));
3324                 seq_putc(m, '\n');
3325         }
3326
3327         seq_puts(m, "\nSync seqno:\n");
3328         for_each_engine(engine, dev_priv, id) {
3329                 for (j = 0; j < num_rings; j++)
3330                         seq_printf(m, "  0x%08x ",
3331                                    engine->semaphore.sync_seqno[j]);
3332                 seq_putc(m, '\n');
3333         }
3334         seq_putc(m, '\n');
3335
3336         intel_runtime_pm_put(dev_priv);
3337         mutex_unlock(&dev->struct_mutex);
3338         return 0;
3339 }
3340
3341 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3342 {
3343         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3344         struct drm_device *dev = &dev_priv->drm;
3345         int i;
3346
3347         drm_modeset_lock_all(dev);
3348         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3349                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3350
3351                 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3352                 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3353                            pll->config.crtc_mask, pll->active_mask, yesno(pll->on));
3354                 seq_printf(m, " tracked hardware state:\n");
3355                 seq_printf(m, " dpll:    0x%08x\n", pll->config.hw_state.dpll);
3356                 seq_printf(m, " dpll_md: 0x%08x\n",
3357                            pll->config.hw_state.dpll_md);
3358                 seq_printf(m, " fp0:     0x%08x\n", pll->config.hw_state.fp0);
3359                 seq_printf(m, " fp1:     0x%08x\n", pll->config.hw_state.fp1);
3360                 seq_printf(m, " wrpll:   0x%08x\n", pll->config.hw_state.wrpll);
3361         }
3362         drm_modeset_unlock_all(dev);
3363
3364         return 0;
3365 }
3366
3367 static int i915_wa_registers(struct seq_file *m, void *unused)
3368 {
3369         int i;
3370         int ret;
3371         struct intel_engine_cs *engine;
3372         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3373         struct drm_device *dev = &dev_priv->drm;
3374         struct i915_workarounds *workarounds = &dev_priv->workarounds;
3375         enum intel_engine_id id;
3376
3377         ret = mutex_lock_interruptible(&dev->struct_mutex);
3378         if (ret)
3379                 return ret;
3380
3381         intel_runtime_pm_get(dev_priv);
3382
3383         seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
3384         for_each_engine(engine, dev_priv, id)
3385                 seq_printf(m, "HW whitelist count for %s: %d\n",
3386                            engine->name, workarounds->hw_whitelist_count[id]);
3387         for (i = 0; i < workarounds->count; ++i) {
3388                 i915_reg_t addr;
3389                 u32 mask, value, read;
3390                 bool ok;
3391
3392                 addr = workarounds->reg[i].addr;
3393                 mask = workarounds->reg[i].mask;
3394                 value = workarounds->reg[i].value;
3395                 read = I915_READ(addr);
3396                 ok = (value & mask) == (read & mask);
3397                 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3398                            i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
3399         }
3400
3401         intel_runtime_pm_put(dev_priv);
3402         mutex_unlock(&dev->struct_mutex);
3403
3404         return 0;
3405 }
3406
3407 static int i915_ddb_info(struct seq_file *m, void *unused)
3408 {
3409         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3410         struct drm_device *dev = &dev_priv->drm;
3411         struct skl_ddb_allocation *ddb;
3412         struct skl_ddb_entry *entry;
3413         enum pipe pipe;
3414         int plane;
3415
3416         if (INTEL_GEN(dev_priv) < 9)
3417                 return 0;
3418
3419         drm_modeset_lock_all(dev);
3420
3421         ddb = &dev_priv->wm.skl_hw.ddb;
3422
3423         seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3424
3425         for_each_pipe(dev_priv, pipe) {
3426                 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3427
3428                 for_each_plane(dev_priv, pipe, plane) {
3429                         entry = &ddb->plane[pipe][plane];
3430                         seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane + 1,
3431                                    entry->start, entry->end,
3432                                    skl_ddb_entry_size(entry));
3433                 }
3434
3435                 entry = &ddb->plane[pipe][PLANE_CURSOR];
3436                 seq_printf(m, "  %-13s%8u%8u%8u\n", "Cursor", entry->start,
3437                            entry->end, skl_ddb_entry_size(entry));
3438         }
3439
3440         drm_modeset_unlock_all(dev);
3441
3442         return 0;
3443 }
3444
3445 static void drrs_status_per_crtc(struct seq_file *m,
3446                                  struct drm_device *dev,
3447                                  struct intel_crtc *intel_crtc)
3448 {
3449         struct drm_i915_private *dev_priv = to_i915(dev);
3450         struct i915_drrs *drrs = &dev_priv->drrs;
3451         int vrefresh = 0;
3452         struct drm_connector *connector;
3453
3454         drm_for_each_connector(connector, dev) {
3455                 if (connector->state->crtc != &intel_crtc->base)
3456                         continue;
3457
3458                 seq_printf(m, "%s:\n", connector->name);
3459         }
3460
3461         if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3462                 seq_puts(m, "\tVBT: DRRS_type: Static");
3463         else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3464                 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3465         else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3466                 seq_puts(m, "\tVBT: DRRS_type: None");
3467         else
3468                 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3469
3470         seq_puts(m, "\n\n");
3471
3472         if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3473                 struct intel_panel *panel;
3474
3475                 mutex_lock(&drrs->mutex);
3476                 /* DRRS Supported */
3477                 seq_puts(m, "\tDRRS Supported: Yes\n");
3478
3479                 /* disable_drrs() will make drrs->dp NULL */
3480                 if (!drrs->dp) {
3481                         seq_puts(m, "Idleness DRRS: Disabled");
3482                         mutex_unlock(&drrs->mutex);
3483                         return;
3484                 }
3485
3486                 panel = &drrs->dp->attached_connector->panel;
3487                 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3488                                         drrs->busy_frontbuffer_bits);
3489
3490                 seq_puts(m, "\n\t\t");
3491                 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3492                         seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3493                         vrefresh = panel->fixed_mode->vrefresh;
3494                 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3495                         seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3496                         vrefresh = panel->downclock_mode->vrefresh;
3497                 } else {
3498                         seq_printf(m, "DRRS_State: Unknown(%d)\n",
3499                                                 drrs->refresh_rate_type);
3500                         mutex_unlock(&drrs->mutex);
3501                         return;
3502                 }
3503                 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3504
3505                 seq_puts(m, "\n\t\t");
3506                 mutex_unlock(&drrs->mutex);
3507         } else {
3508                 /* DRRS not supported. Print the VBT parameter*/
3509                 seq_puts(m, "\tDRRS Supported : No");
3510         }
3511         seq_puts(m, "\n");
3512 }
3513
3514 static int i915_drrs_status(struct seq_file *m, void *unused)
3515 {
3516         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3517         struct drm_device *dev = &dev_priv->drm;
3518         struct intel_crtc *intel_crtc;
3519         int active_crtc_cnt = 0;
3520
3521         drm_modeset_lock_all(dev);
3522         for_each_intel_crtc(dev, intel_crtc) {
3523                 if (intel_crtc->base.state->active) {
3524                         active_crtc_cnt++;
3525                         seq_printf(m, "\nCRTC %d:  ", active_crtc_cnt);
3526
3527                         drrs_status_per_crtc(m, dev, intel_crtc);
3528                 }
3529         }
3530         drm_modeset_unlock_all(dev);
3531
3532         if (!active_crtc_cnt)
3533                 seq_puts(m, "No active crtc found\n");
3534
3535         return 0;
3536 }
3537
3538 struct pipe_crc_info {
3539         const char *name;
3540         struct drm_i915_private *dev_priv;
3541         enum pipe pipe;
3542 };
3543
3544 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3545 {
3546         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3547         struct drm_device *dev = &dev_priv->drm;
3548         struct intel_encoder *intel_encoder;
3549         struct intel_digital_port *intel_dig_port;
3550         struct drm_connector *connector;
3551
3552         drm_modeset_lock_all(dev);
3553         drm_for_each_connector(connector, dev) {
3554                 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
3555                         continue;
3556
3557                 intel_encoder = intel_attached_encoder(connector);
3558                 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
3559                         continue;
3560
3561                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
3562                 if (!intel_dig_port->dp.can_mst)
3563                         continue;
3564
3565                 seq_printf(m, "MST Source Port %c\n",
3566                            port_name(intel_dig_port->port));
3567                 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3568         }
3569         drm_modeset_unlock_all(dev);
3570         return 0;
3571 }
3572
3573 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3574 {
3575         struct pipe_crc_info *info = inode->i_private;
3576         struct drm_i915_private *dev_priv = info->dev_priv;
3577         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3578
3579         if (info->pipe >= INTEL_INFO(dev_priv)->num_pipes)
3580                 return -ENODEV;
3581
3582         spin_lock_irq(&pipe_crc->lock);
3583
3584         if (pipe_crc->opened) {
3585                 spin_unlock_irq(&pipe_crc->lock);
3586                 return -EBUSY; /* already open */
3587         }
3588
3589         pipe_crc->opened = true;
3590         filep->private_data = inode->i_private;
3591
3592         spin_unlock_irq(&pipe_crc->lock);
3593
3594         return 0;
3595 }
3596
3597 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3598 {
3599         struct pipe_crc_info *info = inode->i_private;
3600         struct drm_i915_private *dev_priv = info->dev_priv;
3601         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3602
3603         spin_lock_irq(&pipe_crc->lock);
3604         pipe_crc->opened = false;
3605         spin_unlock_irq(&pipe_crc->lock);
3606
3607         return 0;
3608 }
3609
3610 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3611 #define PIPE_CRC_LINE_LEN       (6 * 8 + 5 + 1)
3612 /* account for \'0' */
3613 #define PIPE_CRC_BUFFER_LEN     (PIPE_CRC_LINE_LEN + 1)
3614
3615 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
3616 {
3617         assert_spin_locked(&pipe_crc->lock);
3618         return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3619                         INTEL_PIPE_CRC_ENTRIES_NR);
3620 }
3621
3622 static ssize_t
3623 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3624                    loff_t *pos)
3625 {
3626         struct pipe_crc_info *info = filep->private_data;
3627         struct drm_i915_private *dev_priv = info->dev_priv;
3628         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3629         char buf[PIPE_CRC_BUFFER_LEN];
3630         int n_entries;
3631         ssize_t bytes_read;
3632
3633         /*
3634          * Don't allow user space to provide buffers not big enough to hold
3635          * a line of data.
3636          */
3637         if (count < PIPE_CRC_LINE_LEN)
3638                 return -EINVAL;
3639
3640         if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
3641                 return 0;
3642
3643         /* nothing to read */
3644         spin_lock_irq(&pipe_crc->lock);
3645         while (pipe_crc_data_count(pipe_crc) == 0) {
3646                 int ret;
3647
3648                 if (filep->f_flags & O_NONBLOCK) {
3649                         spin_unlock_irq(&pipe_crc->lock);
3650                         return -EAGAIN;
3651                 }
3652
3653                 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3654                                 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3655                 if (ret) {
3656                         spin_unlock_irq(&pipe_crc->lock);
3657                         return ret;
3658                 }
3659         }
3660
3661         /* We now have one or more entries to read */
3662         n_entries = count / PIPE_CRC_LINE_LEN;
3663
3664         bytes_read = 0;
3665         while (n_entries > 0) {
3666                 struct intel_pipe_crc_entry *entry =
3667                         &pipe_crc->entries[pipe_crc->tail];
3668
3669                 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3670                              INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3671                         break;
3672
3673                 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3674                 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3675
3676                 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3677                                        "%8u %8x %8x %8x %8x %8x\n",
3678                                        entry->frame, entry->crc[0],
3679                                        entry->crc[1], entry->crc[2],
3680                                        entry->crc[3], entry->crc[4]);
3681
3682                 spin_unlock_irq(&pipe_crc->lock);
3683
3684                 if (copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN))
3685                         return -EFAULT;
3686
3687                 user_buf += PIPE_CRC_LINE_LEN;
3688                 n_entries--;
3689
3690                 spin_lock_irq(&pipe_crc->lock);
3691         }
3692
3693         spin_unlock_irq(&pipe_crc->lock);
3694
3695         return bytes_read;
3696 }
3697
3698 static const struct file_operations i915_pipe_crc_fops = {
3699         .owner = THIS_MODULE,
3700         .open = i915_pipe_crc_open,
3701         .read = i915_pipe_crc_read,
3702         .release = i915_pipe_crc_release,
3703 };
3704
3705 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3706         {
3707                 .name = "i915_pipe_A_crc",
3708                 .pipe = PIPE_A,
3709         },
3710         {
3711                 .name = "i915_pipe_B_crc",
3712                 .pipe = PIPE_B,
3713         },
3714         {
3715                 .name = "i915_pipe_C_crc",
3716                 .pipe = PIPE_C,
3717         },
3718 };
3719
3720 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3721                                 enum pipe pipe)
3722 {
3723         struct drm_i915_private *dev_priv = to_i915(minor->dev);
3724         struct dentry *ent;
3725         struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3726
3727         info->dev_priv = dev_priv;
3728         ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3729                                   &i915_pipe_crc_fops);
3730         if (!ent)
3731                 return -ENOMEM;
3732
3733         return drm_add_fake_info_node(minor, ent, info);
3734 }
3735
3736 static const char * const pipe_crc_sources[] = {
3737         "none",
3738         "plane1",
3739         "plane2",
3740         "pf",
3741         "pipe",
3742         "TV",
3743         "DP-B",
3744         "DP-C",
3745         "DP-D",
3746         "auto",
3747 };
3748
3749 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3750 {
3751         BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3752         return pipe_crc_sources[source];
3753 }
3754
3755 static int display_crc_ctl_show(struct seq_file *m, void *data)
3756 {
3757         struct drm_i915_private *dev_priv = m->private;
3758         int i;
3759
3760         for (i = 0; i < I915_MAX_PIPES; i++)
3761                 seq_printf(m, "%c %s\n", pipe_name(i),
3762                            pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3763
3764         return 0;
3765 }
3766
3767 static int display_crc_ctl_open(struct inode *inode, struct file *file)
3768 {
3769         return single_open(file, display_crc_ctl_show, inode->i_private);
3770 }
3771
3772 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3773                                  uint32_t *val)
3774 {
3775         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3776                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3777
3778         switch (*source) {
3779         case INTEL_PIPE_CRC_SOURCE_PIPE:
3780                 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3781                 break;
3782         case INTEL_PIPE_CRC_SOURCE_NONE:
3783                 *val = 0;
3784                 break;
3785         default:
3786                 return -EINVAL;
3787         }
3788
3789         return 0;
3790 }
3791
3792 static int i9xx_pipe_crc_auto_source(struct drm_i915_private *dev_priv,
3793                                      enum pipe pipe,
3794                                      enum intel_pipe_crc_source *source)
3795 {
3796         struct drm_device *dev = &dev_priv->drm;
3797         struct intel_encoder *encoder;
3798         struct intel_crtc *crtc;
3799         struct intel_digital_port *dig_port;
3800         int ret = 0;
3801
3802         *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3803
3804         drm_modeset_lock_all(dev);
3805         for_each_intel_encoder(dev, encoder) {
3806                 if (!encoder->base.crtc)
3807                         continue;
3808
3809                 crtc = to_intel_crtc(encoder->base.crtc);
3810
3811                 if (crtc->pipe != pipe)
3812                         continue;
3813
3814                 switch (encoder->type) {
3815                 case INTEL_OUTPUT_TVOUT:
3816                         *source = INTEL_PIPE_CRC_SOURCE_TV;
3817                         break;
3818                 case INTEL_OUTPUT_DP:
3819                 case INTEL_OUTPUT_EDP:
3820                         dig_port = enc_to_dig_port(&encoder->base);
3821                         switch (dig_port->port) {
3822                         case PORT_B:
3823                                 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3824                                 break;
3825                         case PORT_C:
3826                                 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3827                                 break;
3828                         case PORT_D:
3829                                 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3830                                 break;
3831                         default:
3832                                 WARN(1, "nonexisting DP port %c\n",
3833                                      port_name(dig_port->port));
3834                                 break;
3835                         }
3836                         break;
3837                 default:
3838                         break;
3839                 }
3840         }
3841         drm_modeset_unlock_all(dev);
3842
3843         return ret;
3844 }
3845
3846 static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
3847                                 enum pipe pipe,
3848                                 enum intel_pipe_crc_source *source,
3849                                 uint32_t *val)
3850 {
3851         bool need_stable_symbols = false;
3852
3853         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3854                 int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
3855                 if (ret)
3856                         return ret;
3857         }
3858
3859         switch (*source) {
3860         case INTEL_PIPE_CRC_SOURCE_PIPE:
3861                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3862                 break;
3863         case INTEL_PIPE_CRC_SOURCE_DP_B:
3864                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3865                 need_stable_symbols = true;
3866                 break;
3867         case INTEL_PIPE_CRC_SOURCE_DP_C:
3868                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3869                 need_stable_symbols = true;
3870                 break;
3871         case INTEL_PIPE_CRC_SOURCE_DP_D:
3872                 if (!IS_CHERRYVIEW(dev_priv))
3873                         return -EINVAL;
3874                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3875                 need_stable_symbols = true;
3876                 break;
3877         case INTEL_PIPE_CRC_SOURCE_NONE:
3878                 *val = 0;
3879                 break;
3880         default:
3881                 return -EINVAL;
3882         }
3883
3884         /*
3885          * When the pipe CRC tap point is after the transcoders we need
3886          * to tweak symbol-level features to produce a deterministic series of
3887          * symbols for a given frame. We need to reset those features only once
3888          * a frame (instead of every nth symbol):
3889          *   - DC-balance: used to ensure a better clock recovery from the data
3890          *     link (SDVO)
3891          *   - DisplayPort scrambling: used for EMI reduction
3892          */
3893         if (need_stable_symbols) {
3894                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3895
3896                 tmp |= DC_BALANCE_RESET_VLV;
3897                 switch (pipe) {
3898                 case PIPE_A:
3899                         tmp |= PIPE_A_SCRAMBLE_RESET;
3900                         break;
3901                 case PIPE_B:
3902                         tmp |= PIPE_B_SCRAMBLE_RESET;
3903                         break;
3904                 case PIPE_C:
3905                         tmp |= PIPE_C_SCRAMBLE_RESET;
3906                         break;
3907                 default:
3908                         return -EINVAL;
3909                 }
3910                 I915_WRITE(PORT_DFT2_G4X, tmp);
3911         }
3912
3913         return 0;
3914 }
3915
3916 static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
3917                                  enum pipe pipe,
3918                                  enum intel_pipe_crc_source *source,
3919                                  uint32_t *val)
3920 {
3921         bool need_stable_symbols = false;
3922
3923         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3924                 int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
3925                 if (ret)
3926                         return ret;
3927         }
3928
3929         switch (*source) {
3930         case INTEL_PIPE_CRC_SOURCE_PIPE:
3931                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3932                 break;
3933         case INTEL_PIPE_CRC_SOURCE_TV:
3934                 if (!SUPPORTS_TV(dev_priv))
3935                         return -EINVAL;
3936                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3937                 break;
3938         case INTEL_PIPE_CRC_SOURCE_DP_B:
3939                 if (!IS_G4X(dev_priv))
3940                         return -EINVAL;
3941                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3942                 need_stable_symbols = true;
3943                 break;
3944         case INTEL_PIPE_CRC_SOURCE_DP_C:
3945                 if (!IS_G4X(dev_priv))
3946                         return -EINVAL;
3947                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3948                 need_stable_symbols = true;
3949                 break;
3950         case INTEL_PIPE_CRC_SOURCE_DP_D:
3951                 if (!IS_G4X(dev_priv))
3952                         return -EINVAL;
3953                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3954                 need_stable_symbols = true;
3955                 break;
3956         case INTEL_PIPE_CRC_SOURCE_NONE:
3957                 *val = 0;
3958                 break;
3959         default:
3960                 return -EINVAL;
3961         }
3962
3963         /*
3964          * When the pipe CRC tap point is after the transcoders we need
3965          * to tweak symbol-level features to produce a deterministic series of
3966          * symbols for a given frame. We need to reset those features only once
3967          * a frame (instead of every nth symbol):
3968          *   - DC-balance: used to ensure a better clock recovery from the data
3969          *     link (SDVO)
3970          *   - DisplayPort scrambling: used for EMI reduction
3971          */
3972         if (need_stable_symbols) {
3973                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3974
3975                 WARN_ON(!IS_G4X(dev_priv));
3976
3977                 I915_WRITE(PORT_DFT_I9XX,
3978                            I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3979
3980                 if (pipe == PIPE_A)
3981                         tmp |= PIPE_A_SCRAMBLE_RESET;
3982                 else
3983                         tmp |= PIPE_B_SCRAMBLE_RESET;
3984
3985                 I915_WRITE(PORT_DFT2_G4X, tmp);
3986         }
3987
3988         return 0;
3989 }
3990
3991 static void vlv_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
3992                                          enum pipe pipe)
3993 {
3994         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3995
3996         switch (pipe) {
3997         case PIPE_A:
3998                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3999                 break;
4000         case PIPE_B:
4001                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
4002                 break;
4003         case PIPE_C:
4004                 tmp &= ~PIPE_C_SCRAMBLE_RESET;
4005                 break;
4006         default:
4007                 return;
4008         }
4009         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
4010                 tmp &= ~DC_BALANCE_RESET_VLV;
4011         I915_WRITE(PORT_DFT2_G4X, tmp);
4012
4013 }
4014
4015 static void g4x_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
4016                                          enum pipe pipe)
4017 {
4018         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
4019
4020         if (pipe == PIPE_A)
4021                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
4022         else
4023                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
4024         I915_WRITE(PORT_DFT2_G4X, tmp);
4025
4026         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
4027                 I915_WRITE(PORT_DFT_I9XX,
4028                            I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
4029         }
4030 }
4031
4032 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
4033                                 uint32_t *val)
4034 {
4035         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
4036                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
4037
4038         switch (*source) {
4039         case INTEL_PIPE_CRC_SOURCE_PLANE1:
4040                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
4041                 break;
4042         case INTEL_PIPE_CRC_SOURCE_PLANE2:
4043                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
4044                 break;
4045         case INTEL_PIPE_CRC_SOURCE_PIPE:
4046                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
4047                 break;
4048         case INTEL_PIPE_CRC_SOURCE_NONE:
4049                 *val = 0;
4050                 break;
4051         default:
4052                 return -EINVAL;
4053         }
4054
4055         return 0;
4056 }
4057
4058 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_i915_private *dev_priv,
4059                                         bool enable)
4060 {
4061         struct drm_device *dev = &dev_priv->drm;
4062         struct intel_crtc *crtc =
4063                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
4064         struct intel_crtc_state *pipe_config;
4065         struct drm_atomic_state *state;
4066         int ret = 0;
4067
4068         drm_modeset_lock_all(dev);
4069         state = drm_atomic_state_alloc(dev);
4070         if (!state) {
4071                 ret = -ENOMEM;
4072                 goto out;
4073         }
4074
4075         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
4076         pipe_config = intel_atomic_get_crtc_state(state, crtc);
4077         if (IS_ERR(pipe_config)) {
4078                 ret = PTR_ERR(pipe_config);
4079                 goto out;
4080         }
4081
4082         pipe_config->pch_pfit.force_thru = enable;
4083         if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
4084             pipe_config->pch_pfit.enabled != enable)
4085                 pipe_config->base.connectors_changed = true;
4086
4087         ret = drm_atomic_commit(state);
4088 out:
4089         WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
4090         drm_modeset_unlock_all(dev);
4091         drm_atomic_state_put(state);
4092 }
4093
4094 static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
4095                                 enum pipe pipe,
4096                                 enum intel_pipe_crc_source *source,
4097                                 uint32_t *val)
4098 {
4099         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
4100                 *source = INTEL_PIPE_CRC_SOURCE_PF;
4101
4102         switch (*source) {
4103         case INTEL_PIPE_CRC_SOURCE_PLANE1:
4104                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
4105                 break;
4106         case INTEL_PIPE_CRC_SOURCE_PLANE2:
4107                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
4108                 break;
4109         case INTEL_PIPE_CRC_SOURCE_PF:
4110                 if (IS_HASWELL(dev_priv) && pipe == PIPE_A)
4111                         hsw_trans_edp_pipe_A_crc_wa(dev_priv, true);
4112
4113                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
4114                 break;
4115         case INTEL_PIPE_CRC_SOURCE_NONE:
4116                 *val = 0;
4117                 break;
4118         default:
4119                 return -EINVAL;
4120         }
4121
4122         return 0;
4123 }
4124
4125 static int pipe_crc_set_source(struct drm_i915_private *dev_priv,
4126                                enum pipe pipe,
4127                                enum intel_pipe_crc_source source)
4128 {
4129         struct drm_device *dev = &dev_priv->drm;
4130         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
4131         struct intel_crtc *crtc =
4132                         to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
4133         enum intel_display_power_domain power_domain;
4134         u32 val = 0; /* shut up gcc */
4135         int ret;
4136
4137         if (pipe_crc->source == source)
4138                 return 0;
4139
4140         /* forbid changing the source without going back to 'none' */
4141         if (pipe_crc->source && source)
4142                 return -EINVAL;
4143
4144         power_domain = POWER_DOMAIN_PIPE(pipe);
4145         if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
4146                 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
4147                 return -EIO;
4148         }
4149
4150         if (IS_GEN2(dev_priv))
4151                 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
4152         else if (INTEL_GEN(dev_priv) < 5)
4153                 ret = i9xx_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val);
4154         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4155                 ret = vlv_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val);
4156         else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv))
4157                 ret = ilk_pipe_crc_ctl_reg(&source, &val);
4158         else
4159                 ret = ivb_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val);
4160
4161         if (ret != 0)
4162                 goto out;
4163
4164         /* none -> real source transition */
4165         if (source) {
4166                 struct intel_pipe_crc_entry *entries;
4167
4168                 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4169                                  pipe_name(pipe), pipe_crc_source_name(source));
4170
4171                 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
4172                                   sizeof(pipe_crc->entries[0]),
4173                                   GFP_KERNEL);
4174                 if (!entries) {
4175                         ret = -ENOMEM;
4176                         goto out;
4177                 }
4178
4179                 /*
4180                  * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4181                  * enabled and disabled dynamically based on package C states,
4182                  * user space can't make reliable use of the CRCs, so let's just
4183                  * completely disable it.
4184                  */
4185                 hsw_disable_ips(crtc);
4186
4187                 spin_lock_irq(&pipe_crc->lock);
4188                 kfree(pipe_crc->entries);
4189                 pipe_crc->entries = entries;
4190                 pipe_crc->head = 0;
4191                 pipe_crc->tail = 0;
4192                 spin_unlock_irq(&pipe_crc->lock);
4193         }
4194
4195         pipe_crc->source = source;
4196
4197         I915_WRITE(PIPE_CRC_CTL(pipe), val);
4198         POSTING_READ(PIPE_CRC_CTL(pipe));
4199
4200         /* real source -> none transition */
4201         if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
4202                 struct intel_pipe_crc_entry *entries;
4203                 struct intel_crtc *crtc =
4204                         to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
4205
4206                 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4207                                  pipe_name(pipe));
4208
4209                 drm_modeset_lock(&crtc->base.mutex, NULL);
4210                 if (crtc->base.state->active)
4211                         intel_wait_for_vblank(dev, pipe);
4212                 drm_modeset_unlock(&crtc->base.mutex);
4213
4214                 spin_lock_irq(&pipe_crc->lock);
4215                 entries = pipe_crc->entries;
4216                 pipe_crc->entries = NULL;
4217                 pipe_crc->head = 0;
4218                 pipe_crc->tail = 0;
4219                 spin_unlock_irq(&pipe_crc->lock);
4220
4221                 kfree(entries);
4222
4223                 if (IS_G4X(dev_priv))
4224                         g4x_undo_pipe_scramble_reset(dev_priv, pipe);
4225                 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4226                         vlv_undo_pipe_scramble_reset(dev_priv, pipe);
4227                 else if (IS_HASWELL(dev_priv) && pipe == PIPE_A)
4228                         hsw_trans_edp_pipe_A_crc_wa(dev_priv, false);
4229
4230                 hsw_enable_ips(crtc);
4231         }
4232
4233         ret = 0;
4234
4235 out:
4236         intel_display_power_put(dev_priv, power_domain);
4237
4238         return ret;
4239 }
4240
4241 /*
4242  * Parse pipe CRC command strings:
4243  *   command: wsp* object wsp+ name wsp+ source wsp*
4244  *   object: 'pipe'
4245  *   name: (A | B | C)
4246  *   source: (none | plane1 | plane2 | pf)
4247  *   wsp: (#0x20 | #0x9 | #0xA)+
4248  *
4249  * eg.:
4250  *  "pipe A plane1"  ->  Start CRC computations on plane1 of pipe A
4251  *  "pipe A none"    ->  Stop CRC
4252  */
4253 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
4254 {
4255         int n_words = 0;
4256
4257         while (*buf) {
4258                 char *end;
4259
4260                 /* skip leading white space */
4261                 buf = skip_spaces(buf);
4262                 if (!*buf)
4263                         break;  /* end of buffer */
4264
4265                 /* find end of word */
4266                 for (end = buf; *end && !isspace(*end); end++)
4267                         ;
4268
4269                 if (n_words == max_words) {
4270                         DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4271                                          max_words);
4272                         return -EINVAL; /* ran out of words[] before bytes */
4273                 }
4274
4275                 if (*end)
4276                         *end++ = '\0';
4277                 words[n_words++] = buf;
4278                 buf = end;
4279         }
4280
4281         return n_words;
4282 }
4283
4284 enum intel_pipe_crc_object {
4285         PIPE_CRC_OBJECT_PIPE,
4286 };
4287
4288 static const char * const pipe_crc_objects[] = {
4289         "pipe",
4290 };
4291
4292 static int
4293 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
4294 {
4295         int i;
4296
4297         for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
4298                 if (!strcmp(buf, pipe_crc_objects[i])) {
4299                         *o = i;
4300                         return 0;
4301                     }
4302
4303         return -EINVAL;
4304 }
4305
4306 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
4307 {
4308         const char name = buf[0];
4309
4310         if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
4311                 return -EINVAL;
4312
4313         *pipe = name - 'A';
4314
4315         return 0;
4316 }
4317
4318 static int
4319 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
4320 {
4321         int i;
4322
4323         for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
4324                 if (!strcmp(buf, pipe_crc_sources[i])) {
4325                         *s = i;
4326                         return 0;
4327                     }
4328
4329         return -EINVAL;
4330 }
4331
4332 static int display_crc_ctl_parse(struct drm_i915_private *dev_priv,
4333                                  char *buf, size_t len)
4334 {
4335 #define N_WORDS 3
4336         int n_words;
4337         char *words[N_WORDS];
4338         enum pipe pipe;
4339         enum intel_pipe_crc_object object;
4340         enum intel_pipe_crc_source source;
4341
4342         n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
4343         if (n_words != N_WORDS) {
4344                 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4345                                  N_WORDS);
4346                 return -EINVAL;
4347         }
4348
4349         if (display_crc_ctl_parse_object(words[0], &object) < 0) {
4350                 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
4351                 return -EINVAL;
4352         }
4353
4354         if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
4355                 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
4356                 return -EINVAL;
4357         }
4358
4359         if (display_crc_ctl_parse_source(words[2], &source) < 0) {
4360                 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
4361                 return -EINVAL;
4362         }
4363
4364         return pipe_crc_set_source(dev_priv, pipe, source);
4365 }
4366
4367 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
4368                                      size_t len, loff_t *offp)
4369 {
4370         struct seq_file *m = file->private_data;
4371         struct drm_i915_private *dev_priv = m->private;
4372         char *tmpbuf;
4373         int ret;
4374
4375         if (len == 0)
4376                 return 0;
4377
4378         if (len > PAGE_SIZE - 1) {
4379                 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4380                                  PAGE_SIZE);
4381                 return -E2BIG;
4382         }
4383
4384         tmpbuf = kmalloc(len + 1, GFP_KERNEL);
4385         if (!tmpbuf)
4386                 return -ENOMEM;
4387
4388         if (copy_from_user(tmpbuf, ubuf, len)) {
4389                 ret = -EFAULT;
4390                 goto out;
4391         }
4392         tmpbuf[len] = '\0';
4393
4394         ret = display_crc_ctl_parse(dev_priv, tmpbuf, len);
4395
4396 out:
4397         kfree(tmpbuf);
4398         if (ret < 0)
4399                 return ret;
4400
4401         *offp += len;
4402         return len;
4403 }
4404
4405 static const struct file_operations i915_display_crc_ctl_fops = {
4406         .owner = THIS_MODULE,
4407         .open = display_crc_ctl_open,
4408         .read = seq_read,
4409         .llseek = seq_lseek,
4410         .release = single_release,
4411         .write = display_crc_ctl_write
4412 };
4413
4414 static ssize_t i915_displayport_test_active_write(struct file *file,
4415                                                   const char __user *ubuf,
4416                                                   size_t len, loff_t *offp)
4417 {
4418         char *input_buffer;
4419         int status = 0;
4420         struct drm_device *dev;
4421         struct drm_connector *connector;
4422         struct list_head *connector_list;
4423         struct intel_dp *intel_dp;
4424         int val = 0;
4425
4426         dev = ((struct seq_file *)file->private_data)->private;
4427
4428         connector_list = &dev->mode_config.connector_list;
4429
4430         if (len == 0)
4431                 return 0;
4432
4433         input_buffer = kmalloc(len + 1, GFP_KERNEL);
4434         if (!input_buffer)
4435                 return -ENOMEM;
4436
4437         if (copy_from_user(input_buffer, ubuf, len)) {
4438                 status = -EFAULT;
4439                 goto out;
4440         }
4441
4442         input_buffer[len] = '\0';
4443         DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4444
4445         list_for_each_entry(connector, connector_list, head) {
4446                 if (connector->connector_type !=
4447                     DRM_MODE_CONNECTOR_DisplayPort)
4448                         continue;
4449
4450                 if (connector->status == connector_status_connected &&
4451                     connector->encoder != NULL) {
4452                         intel_dp = enc_to_intel_dp(connector->encoder);
4453                         status = kstrtoint(input_buffer, 10, &val);
4454                         if (status < 0)
4455                                 goto out;
4456                         DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4457                         /* To prevent erroneous activation of the compliance
4458                          * testing code, only accept an actual value of 1 here
4459                          */
4460                         if (val == 1)
4461                                 intel_dp->compliance_test_active = 1;
4462                         else
4463                                 intel_dp->compliance_test_active = 0;
4464                 }
4465         }
4466 out:
4467         kfree(input_buffer);
4468         if (status < 0)
4469                 return status;
4470
4471         *offp += len;
4472         return len;
4473 }
4474
4475 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4476 {
4477         struct drm_device *dev = m->private;
4478         struct drm_connector *connector;
4479         struct list_head *connector_list = &dev->mode_config.connector_list;
4480         struct intel_dp *intel_dp;
4481
4482         list_for_each_entry(connector, connector_list, head) {
4483                 if (connector->connector_type !=
4484                     DRM_MODE_CONNECTOR_DisplayPort)
4485                         continue;
4486
4487                 if (connector->status == connector_status_connected &&
4488                     connector->encoder != NULL) {
4489                         intel_dp = enc_to_intel_dp(connector->encoder);
4490                         if (intel_dp->compliance_test_active)
4491                                 seq_puts(m, "1");
4492                         else
4493                                 seq_puts(m, "0");
4494                 } else
4495                         seq_puts(m, "0");
4496         }
4497
4498         return 0;
4499 }
4500
4501 static int i915_displayport_test_active_open(struct inode *inode,
4502                                              struct file *file)
4503 {
4504         struct drm_i915_private *dev_priv = inode->i_private;
4505
4506         return single_open(file, i915_displayport_test_active_show,
4507                            &dev_priv->drm);
4508 }
4509
4510 static const struct file_operations i915_displayport_test_active_fops = {
4511         .owner = THIS_MODULE,
4512         .open = i915_displayport_test_active_open,
4513         .read = seq_read,
4514         .llseek = seq_lseek,
4515         .release = single_release,
4516         .write = i915_displayport_test_active_write
4517 };
4518
4519 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4520 {
4521         struct drm_device *dev = m->private;
4522         struct drm_connector *connector;
4523         struct list_head *connector_list = &dev->mode_config.connector_list;
4524         struct intel_dp *intel_dp;
4525
4526         list_for_each_entry(connector, connector_list, head) {
4527                 if (connector->connector_type !=
4528                     DRM_MODE_CONNECTOR_DisplayPort)
4529                         continue;
4530
4531                 if (connector->status == connector_status_connected &&
4532                     connector->encoder != NULL) {
4533                         intel_dp = enc_to_intel_dp(connector->encoder);
4534                         seq_printf(m, "%lx", intel_dp->compliance_test_data);
4535                 } else
4536                         seq_puts(m, "0");
4537         }
4538
4539         return 0;
4540 }
4541 static int i915_displayport_test_data_open(struct inode *inode,
4542                                            struct file *file)
4543 {
4544         struct drm_i915_private *dev_priv = inode->i_private;
4545
4546         return single_open(file, i915_displayport_test_data_show,
4547                            &dev_priv->drm);
4548 }
4549
4550 static const struct file_operations i915_displayport_test_data_fops = {
4551         .owner = THIS_MODULE,
4552         .open = i915_displayport_test_data_open,
4553         .read = seq_read,
4554         .llseek = seq_lseek,
4555         .release = single_release
4556 };
4557
4558 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4559 {
4560         struct drm_device *dev = m->private;
4561         struct drm_connector *connector;
4562         struct list_head *connector_list = &dev->mode_config.connector_list;
4563         struct intel_dp *intel_dp;
4564
4565         list_for_each_entry(connector, connector_list, head) {
4566                 if (connector->connector_type !=
4567                     DRM_MODE_CONNECTOR_DisplayPort)
4568                         continue;
4569
4570                 if (connector->status == connector_status_connected &&
4571                     connector->encoder != NULL) {
4572                         intel_dp = enc_to_intel_dp(connector->encoder);
4573                         seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4574                 } else
4575                         seq_puts(m, "0");
4576         }
4577
4578         return 0;
4579 }
4580
4581 static int i915_displayport_test_type_open(struct inode *inode,
4582                                        struct file *file)
4583 {
4584         struct drm_i915_private *dev_priv = inode->i_private;
4585
4586         return single_open(file, i915_displayport_test_type_show,
4587                            &dev_priv->drm);
4588 }
4589
4590 static const struct file_operations i915_displayport_test_type_fops = {
4591         .owner = THIS_MODULE,
4592         .open = i915_displayport_test_type_open,
4593         .read = seq_read,
4594         .llseek = seq_lseek,
4595         .release = single_release
4596 };
4597
4598 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
4599 {
4600         struct drm_i915_private *dev_priv = m->private;
4601         struct drm_device *dev = &dev_priv->drm;
4602         int level;
4603         int num_levels;
4604
4605         if (IS_CHERRYVIEW(dev_priv))
4606                 num_levels = 3;
4607         else if (IS_VALLEYVIEW(dev_priv))
4608                 num_levels = 1;
4609         else
4610                 num_levels = ilk_wm_max_level(dev_priv) + 1;
4611
4612         drm_modeset_lock_all(dev);
4613
4614         for (level = 0; level < num_levels; level++) {
4615                 unsigned int latency = wm[level];
4616
4617                 /*
4618                  * - WM1+ latency values in 0.5us units
4619                  * - latencies are in us on gen9/vlv/chv
4620                  */
4621                 if (INTEL_GEN(dev_priv) >= 9 || IS_VALLEYVIEW(dev_priv) ||
4622                     IS_CHERRYVIEW(dev_priv))
4623                         latency *= 10;
4624                 else if (level > 0)
4625                         latency *= 5;
4626
4627                 seq_printf(m, "WM%d %u (%u.%u usec)\n",
4628                            level, wm[level], latency / 10, latency % 10);
4629         }
4630
4631         drm_modeset_unlock_all(dev);
4632 }
4633
4634 static int pri_wm_latency_show(struct seq_file *m, void *data)
4635 {
4636         struct drm_i915_private *dev_priv = m->private;
4637         const uint16_t *latencies;
4638
4639         if (INTEL_GEN(dev_priv) >= 9)
4640                 latencies = dev_priv->wm.skl_latency;
4641         else
4642                 latencies = dev_priv->wm.pri_latency;
4643
4644         wm_latency_show(m, latencies);
4645
4646         return 0;
4647 }
4648
4649 static int spr_wm_latency_show(struct seq_file *m, void *data)
4650 {
4651         struct drm_i915_private *dev_priv = m->private;
4652         const uint16_t *latencies;
4653
4654         if (INTEL_GEN(dev_priv) >= 9)
4655                 latencies = dev_priv->wm.skl_latency;
4656         else
4657                 latencies = dev_priv->wm.spr_latency;
4658
4659         wm_latency_show(m, latencies);
4660
4661         return 0;
4662 }
4663
4664 static int cur_wm_latency_show(struct seq_file *m, void *data)
4665 {
4666         struct drm_i915_private *dev_priv = m->private;
4667         const uint16_t *latencies;
4668
4669         if (INTEL_GEN(dev_priv) >= 9)
4670                 latencies = dev_priv->wm.skl_latency;
4671         else
4672                 latencies = dev_priv->wm.cur_latency;
4673
4674         wm_latency_show(m, latencies);
4675
4676         return 0;
4677 }
4678
4679 static int pri_wm_latency_open(struct inode *inode, struct file *file)
4680 {
4681         struct drm_i915_private *dev_priv = inode->i_private;
4682
4683         if (INTEL_GEN(dev_priv) < 5)
4684                 return -ENODEV;
4685
4686         return single_open(file, pri_wm_latency_show, dev_priv);
4687 }
4688
4689 static int spr_wm_latency_open(struct inode *inode, struct file *file)
4690 {
4691         struct drm_i915_private *dev_priv = inode->i_private;
4692
4693         if (HAS_GMCH_DISPLAY(dev_priv))
4694                 return -ENODEV;
4695
4696         return single_open(file, spr_wm_latency_show, dev_priv);
4697 }
4698
4699 static int cur_wm_latency_open(struct inode *inode, struct file *file)
4700 {
4701         struct drm_i915_private *dev_priv = inode->i_private;
4702
4703         if (HAS_GMCH_DISPLAY(dev_priv))
4704                 return -ENODEV;
4705
4706         return single_open(file, cur_wm_latency_show, dev_priv);
4707 }
4708
4709 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
4710                                 size_t len, loff_t *offp, uint16_t wm[8])
4711 {
4712         struct seq_file *m = file->private_data;
4713         struct drm_i915_private *dev_priv = m->private;
4714         struct drm_device *dev = &dev_priv->drm;
4715         uint16_t new[8] = { 0 };
4716         int num_levels;
4717         int level;
4718         int ret;
4719         char tmp[32];
4720
4721         if (IS_CHERRYVIEW(dev_priv))
4722                 num_levels = 3;
4723         else if (IS_VALLEYVIEW(dev_priv))
4724                 num_levels = 1;
4725         else
4726                 num_levels = ilk_wm_max_level(dev_priv) + 1;
4727
4728         if (len >= sizeof(tmp))
4729                 return -EINVAL;
4730
4731         if (copy_from_user(tmp, ubuf, len))
4732                 return -EFAULT;
4733
4734         tmp[len] = '\0';
4735
4736         ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4737                      &new[0], &new[1], &new[2], &new[3],
4738                      &new[4], &new[5], &new[6], &new[7]);
4739         if (ret != num_levels)
4740                 return -EINVAL;
4741
4742         drm_modeset_lock_all(dev);
4743
4744         for (level = 0; level < num_levels; level++)
4745                 wm[level] = new[level];
4746
4747         drm_modeset_unlock_all(dev);
4748
4749         return len;
4750 }
4751
4752
4753 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4754                                     size_t len, loff_t *offp)
4755 {
4756         struct seq_file *m = file->private_data;
4757         struct drm_i915_private *dev_priv = m->private;
4758         uint16_t *latencies;
4759
4760         if (INTEL_GEN(dev_priv) >= 9)
4761                 latencies = dev_priv->wm.skl_latency;
4762         else
4763                 latencies = dev_priv->wm.pri_latency;
4764
4765         return wm_latency_write(file, ubuf, len, offp, latencies);
4766 }
4767
4768 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4769                                     size_t len, loff_t *offp)
4770 {
4771         struct seq_file *m = file->private_data;
4772         struct drm_i915_private *dev_priv = m->private;
4773         uint16_t *latencies;
4774
4775         if (INTEL_GEN(dev_priv) >= 9)
4776                 latencies = dev_priv->wm.skl_latency;
4777         else
4778                 latencies = dev_priv->wm.spr_latency;
4779
4780         return wm_latency_write(file, ubuf, len, offp, latencies);
4781 }
4782
4783 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4784                                     size_t len, loff_t *offp)
4785 {
4786         struct seq_file *m = file->private_data;
4787         struct drm_i915_private *dev_priv = m->private;
4788         uint16_t *latencies;
4789
4790         if (INTEL_GEN(dev_priv) >= 9)
4791                 latencies = dev_priv->wm.skl_latency;
4792         else
4793                 latencies = dev_priv->wm.cur_latency;
4794
4795         return wm_latency_write(file, ubuf, len, offp, latencies);
4796 }
4797
4798 static const struct file_operations i915_pri_wm_latency_fops = {
4799         .owner = THIS_MODULE,
4800         .open = pri_wm_latency_open,
4801         .read = seq_read,
4802         .llseek = seq_lseek,
4803         .release = single_release,
4804         .write = pri_wm_latency_write
4805 };
4806
4807 static const struct file_operations i915_spr_wm_latency_fops = {
4808         .owner = THIS_MODULE,
4809         .open = spr_wm_latency_open,
4810         .read = seq_read,
4811         .llseek = seq_lseek,
4812         .release = single_release,
4813         .write = spr_wm_latency_write
4814 };
4815
4816 static const struct file_operations i915_cur_wm_latency_fops = {
4817         .owner = THIS_MODULE,
4818         .open = cur_wm_latency_open,
4819         .read = seq_read,
4820         .llseek = seq_lseek,
4821         .release = single_release,
4822         .write = cur_wm_latency_write
4823 };
4824
4825 static int
4826 i915_wedged_get(void *data, u64 *val)
4827 {
4828         struct drm_i915_private *dev_priv = data;
4829
4830         *val = i915_terminally_wedged(&dev_priv->gpu_error);
4831
4832         return 0;
4833 }
4834
4835 static int
4836 i915_wedged_set(void *data, u64 val)
4837 {
4838         struct drm_i915_private *dev_priv = data;
4839
4840         /*
4841          * There is no safeguard against this debugfs entry colliding
4842          * with the hangcheck calling same i915_handle_error() in
4843          * parallel, causing an explosion. For now we assume that the
4844          * test harness is responsible enough not to inject gpu hangs
4845          * while it is writing to 'i915_wedged'
4846          */
4847
4848         if (i915_reset_in_progress(&dev_priv->gpu_error))
4849                 return -EAGAIN;
4850
4851         i915_handle_error(dev_priv, val,
4852                           "Manually setting wedged to %llu", val);
4853
4854         return 0;
4855 }
4856
4857 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4858                         i915_wedged_get, i915_wedged_set,
4859                         "%llu\n");
4860
4861 static int
4862 i915_ring_missed_irq_get(void *data, u64 *val)
4863 {
4864         struct drm_i915_private *dev_priv = data;
4865
4866         *val = dev_priv->gpu_error.missed_irq_rings;
4867         return 0;
4868 }
4869
4870 static int
4871 i915_ring_missed_irq_set(void *data, u64 val)
4872 {
4873         struct drm_i915_private *dev_priv = data;
4874         struct drm_device *dev = &dev_priv->drm;
4875         int ret;
4876
4877         /* Lock against concurrent debugfs callers */
4878         ret = mutex_lock_interruptible(&dev->struct_mutex);
4879         if (ret)
4880                 return ret;
4881         dev_priv->gpu_error.missed_irq_rings = val;
4882         mutex_unlock(&dev->struct_mutex);
4883
4884         return 0;
4885 }
4886
4887 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4888                         i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4889                         "0x%08llx\n");
4890
4891 static int
4892 i915_ring_test_irq_get(void *data, u64 *val)
4893 {
4894         struct drm_i915_private *dev_priv = data;
4895
4896         *val = dev_priv->gpu_error.test_irq_rings;
4897
4898         return 0;
4899 }
4900
4901 static int
4902 i915_ring_test_irq_set(void *data, u64 val)
4903 {
4904         struct drm_i915_private *dev_priv = data;
4905
4906         val &= INTEL_INFO(dev_priv)->ring_mask;
4907         DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4908         dev_priv->gpu_error.test_irq_rings = val;
4909
4910         return 0;
4911 }
4912
4913 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4914                         i915_ring_test_irq_get, i915_ring_test_irq_set,
4915                         "0x%08llx\n");
4916
4917 #define DROP_UNBOUND 0x1
4918 #define DROP_BOUND 0x2
4919 #define DROP_RETIRE 0x4
4920 #define DROP_ACTIVE 0x8
4921 #define DROP_ALL (DROP_UNBOUND | \
4922                   DROP_BOUND | \
4923                   DROP_RETIRE | \
4924                   DROP_ACTIVE)
4925 static int
4926 i915_drop_caches_get(void *data, u64 *val)
4927 {
4928         *val = DROP_ALL;
4929
4930         return 0;
4931 }
4932
4933 static int
4934 i915_drop_caches_set(void *data, u64 val)
4935 {
4936         struct drm_i915_private *dev_priv = data;
4937         struct drm_device *dev = &dev_priv->drm;
4938         int ret;
4939
4940         DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4941
4942         /* No need to check and wait for gpu resets, only libdrm auto-restarts
4943          * on ioctls on -EAGAIN. */
4944         ret = mutex_lock_interruptible(&dev->struct_mutex);
4945         if (ret)
4946                 return ret;
4947
4948         if (val & DROP_ACTIVE) {
4949                 ret = i915_gem_wait_for_idle(dev_priv,
4950                                              I915_WAIT_INTERRUPTIBLE |
4951                                              I915_WAIT_LOCKED);
4952                 if (ret)
4953                         goto unlock;
4954         }
4955
4956         if (val & (DROP_RETIRE | DROP_ACTIVE))
4957                 i915_gem_retire_requests(dev_priv);
4958
4959         if (val & DROP_BOUND)
4960                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4961
4962         if (val & DROP_UNBOUND)
4963                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4964
4965 unlock:
4966         mutex_unlock(&dev->struct_mutex);
4967
4968         return ret;
4969 }
4970
4971 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4972                         i915_drop_caches_get, i915_drop_caches_set,
4973                         "0x%08llx\n");
4974
4975 static int
4976 i915_max_freq_get(void *data, u64 *val)
4977 {
4978         struct drm_i915_private *dev_priv = data;
4979
4980         if (INTEL_GEN(dev_priv) < 6)
4981                 return -ENODEV;
4982
4983         *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4984         return 0;
4985 }
4986
4987 static int
4988 i915_max_freq_set(void *data, u64 val)
4989 {
4990         struct drm_i915_private *dev_priv = data;
4991         u32 hw_max, hw_min;
4992         int ret;
4993
4994         if (INTEL_GEN(dev_priv) < 6)
4995                 return -ENODEV;
4996
4997         DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4998
4999         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
5000         if (ret)
5001                 return ret;
5002
5003         /*
5004          * Turbo will still be enabled, but won't go above the set value.
5005          */
5006         val = intel_freq_opcode(dev_priv, val);
5007
5008         hw_max = dev_priv->rps.max_freq;
5009         hw_min = dev_priv->rps.min_freq;
5010
5011         if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
5012                 mutex_unlock(&dev_priv->rps.hw_lock);
5013                 return -EINVAL;
5014         }
5015
5016         dev_priv->rps.max_freq_softlimit = val;
5017
5018         intel_set_rps(dev_priv, val);
5019
5020         mutex_unlock(&dev_priv->rps.hw_lock);
5021
5022         return 0;
5023 }
5024
5025 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
5026                         i915_max_freq_get, i915_max_freq_set,
5027                         "%llu\n");
5028
5029 static int
5030 i915_min_freq_get(void *data, u64 *val)
5031 {
5032         struct drm_i915_private *dev_priv = data;
5033
5034         if (INTEL_GEN(dev_priv) < 6)
5035                 return -ENODEV;
5036
5037         *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
5038         return 0;
5039 }
5040
5041 static int
5042 i915_min_freq_set(void *data, u64 val)
5043 {
5044         struct drm_i915_private *dev_priv = data;
5045         u32 hw_max, hw_min;
5046         int ret;
5047
5048         if (INTEL_GEN(dev_priv) < 6)
5049                 return -ENODEV;
5050
5051         DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
5052
5053         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
5054         if (ret)
5055                 return ret;
5056
5057         /*
5058          * Turbo will still be enabled, but won't go below the set value.
5059          */
5060         val = intel_freq_opcode(dev_priv, val);
5061
5062         hw_max = dev_priv->rps.max_freq;
5063         hw_min = dev_priv->rps.min_freq;
5064
5065         if (val < hw_min ||
5066             val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
5067                 mutex_unlock(&dev_priv->rps.hw_lock);
5068                 return -EINVAL;
5069         }
5070
5071         dev_priv->rps.min_freq_softlimit = val;
5072
5073         intel_set_rps(dev_priv, val);
5074
5075         mutex_unlock(&dev_priv->rps.hw_lock);
5076
5077         return 0;
5078 }
5079
5080 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
5081                         i915_min_freq_get, i915_min_freq_set,
5082                         "%llu\n");
5083
5084 static int
5085 i915_cache_sharing_get(void *data, u64 *val)
5086 {
5087         struct drm_i915_private *dev_priv = data;
5088         u32 snpcr;
5089
5090         if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
5091                 return -ENODEV;
5092
5093         intel_runtime_pm_get(dev_priv);
5094
5095         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5096
5097         intel_runtime_pm_put(dev_priv);
5098
5099         *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
5100
5101         return 0;
5102 }
5103
5104 static int
5105 i915_cache_sharing_set(void *data, u64 val)
5106 {
5107         struct drm_i915_private *dev_priv = data;
5108         u32 snpcr;
5109
5110         if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
5111                 return -ENODEV;
5112
5113         if (val > 3)
5114                 return -EINVAL;
5115
5116         intel_runtime_pm_get(dev_priv);
5117         DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
5118
5119         /* Update the cache sharing policy here as well */
5120         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5121         snpcr &= ~GEN6_MBC_SNPCR_MASK;
5122         snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
5123         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5124
5125         intel_runtime_pm_put(dev_priv);
5126         return 0;
5127 }
5128
5129 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
5130                         i915_cache_sharing_get, i915_cache_sharing_set,
5131                         "%llu\n");
5132
5133 static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
5134                                           struct sseu_dev_info *sseu)
5135 {
5136         int ss_max = 2;
5137         int ss;
5138         u32 sig1[ss_max], sig2[ss_max];
5139
5140         sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
5141         sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
5142         sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
5143         sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
5144
5145         for (ss = 0; ss < ss_max; ss++) {
5146                 unsigned int eu_cnt;
5147
5148                 if (sig1[ss] & CHV_SS_PG_ENABLE)
5149                         /* skip disabled subslice */
5150                         continue;
5151
5152                 sseu->slice_mask = BIT(0);
5153                 sseu->subslice_mask |= BIT(ss);
5154                 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
5155                          ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
5156                          ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
5157                          ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
5158                 sseu->eu_total += eu_cnt;
5159                 sseu->eu_per_subslice = max_t(unsigned int,
5160                                               sseu->eu_per_subslice, eu_cnt);
5161         }
5162 }
5163
5164 static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
5165                                     struct sseu_dev_info *sseu)
5166 {
5167         int s_max = 3, ss_max = 4;
5168         int s, ss;
5169         u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
5170
5171         /* BXT has a single slice and at most 3 subslices. */
5172         if (IS_BROXTON(dev_priv)) {
5173                 s_max = 1;
5174                 ss_max = 3;
5175         }
5176
5177         for (s = 0; s < s_max; s++) {
5178                 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
5179                 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
5180                 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
5181         }
5182
5183         eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
5184                      GEN9_PGCTL_SSA_EU19_ACK |
5185                      GEN9_PGCTL_SSA_EU210_ACK |
5186                      GEN9_PGCTL_SSA_EU311_ACK;
5187         eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
5188                      GEN9_PGCTL_SSB_EU19_ACK |
5189                      GEN9_PGCTL_SSB_EU210_ACK |
5190                      GEN9_PGCTL_SSB_EU311_ACK;
5191
5192         for (s = 0; s < s_max; s++) {
5193                 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
5194                         /* skip disabled slice */
5195                         continue;
5196
5197                 sseu->slice_mask |= BIT(s);
5198
5199                 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
5200                         sseu->subslice_mask =
5201                                 INTEL_INFO(dev_priv)->sseu.subslice_mask;
5202
5203                 for (ss = 0; ss < ss_max; ss++) {
5204                         unsigned int eu_cnt;
5205
5206                         if (IS_BROXTON(dev_priv)) {
5207                                 if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
5208                                         /* skip disabled subslice */
5209                                         continue;
5210
5211                                 sseu->subslice_mask |= BIT(ss);
5212                         }
5213
5214                         eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
5215                                                eu_mask[ss%2]);
5216                         sseu->eu_total += eu_cnt;
5217                         sseu->eu_per_subslice = max_t(unsigned int,
5218                                                       sseu->eu_per_subslice,
5219                                                       eu_cnt);
5220                 }
5221         }
5222 }
5223
5224 static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
5225                                          struct sseu_dev_info *sseu)
5226 {
5227         u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
5228         int s;
5229
5230         sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK;
5231
5232         if (sseu->slice_mask) {
5233                 sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask;
5234                 sseu->eu_per_subslice =
5235                                 INTEL_INFO(dev_priv)->sseu.eu_per_subslice;
5236                 sseu->eu_total = sseu->eu_per_subslice *
5237                                  sseu_subslice_total(sseu);
5238
5239                 /* subtract fused off EU(s) from enabled slice(s) */
5240                 for (s = 0; s < fls(sseu->slice_mask); s++) {
5241                         u8 subslice_7eu =
5242                                 INTEL_INFO(dev_priv)->sseu.subslice_7eu[s];
5243
5244                         sseu->eu_total -= hweight8(subslice_7eu);
5245                 }
5246         }
5247 }
5248
5249 static void i915_print_sseu_info(struct seq_file *m, bool is_available_info,
5250                                  const struct sseu_dev_info *sseu)
5251 {
5252         struct drm_i915_private *dev_priv = node_to_i915(m->private);
5253         const char *type = is_available_info ? "Available" : "Enabled";
5254
5255         seq_printf(m, "  %s Slice Mask: %04x\n", type,
5256                    sseu->slice_mask);
5257         seq_printf(m, "  %s Slice Total: %u\n", type,
5258                    hweight8(sseu->slice_mask));
5259         seq_printf(m, "  %s Subslice Total: %u\n", type,
5260                    sseu_subslice_total(sseu));
5261         seq_printf(m, "  %s Subslice Mask: %04x\n", type,
5262                    sseu->subslice_mask);
5263         seq_printf(m, "  %s Subslice Per Slice: %u\n", type,
5264                    hweight8(sseu->subslice_mask));
5265         seq_printf(m, "  %s EU Total: %u\n", type,
5266                    sseu->eu_total);
5267         seq_printf(m, "  %s EU Per Subslice: %u\n", type,
5268                    sseu->eu_per_subslice);
5269
5270         if (!is_available_info)
5271                 return;
5272
5273         seq_printf(m, "  Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv)));
5274         if (HAS_POOLED_EU(dev_priv))
5275                 seq_printf(m, "  Min EU in pool: %u\n", sseu->min_eu_in_pool);
5276
5277         seq_printf(m, "  Has Slice Power Gating: %s\n",
5278                    yesno(sseu->has_slice_pg));
5279         seq_printf(m, "  Has Subslice Power Gating: %s\n",
5280                    yesno(sseu->has_subslice_pg));
5281         seq_printf(m, "  Has EU Power Gating: %s\n",
5282                    yesno(sseu->has_eu_pg));
5283 }
5284
5285 static int i915_sseu_status(struct seq_file *m, void *unused)
5286 {
5287         struct drm_i915_private *dev_priv = node_to_i915(m->private);
5288         struct sseu_dev_info sseu;
5289
5290         if (INTEL_GEN(dev_priv) < 8)
5291                 return -ENODEV;
5292
5293         seq_puts(m, "SSEU Device Info\n");
5294         i915_print_sseu_info(m, true, &INTEL_INFO(dev_priv)->sseu);
5295
5296         seq_puts(m, "SSEU Device Status\n");
5297         memset(&sseu, 0, sizeof(sseu));
5298
5299         intel_runtime_pm_get(dev_priv);
5300
5301         if (IS_CHERRYVIEW(dev_priv)) {
5302                 cherryview_sseu_device_status(dev_priv, &sseu);
5303         } else if (IS_BROADWELL(dev_priv)) {
5304                 broadwell_sseu_device_status(dev_priv, &sseu);
5305         } else if (INTEL_GEN(dev_priv) >= 9) {
5306                 gen9_sseu_device_status(dev_priv, &sseu);
5307         }
5308
5309         intel_runtime_pm_put(dev_priv);
5310
5311         i915_print_sseu_info(m, false, &sseu);
5312
5313         return 0;
5314 }
5315
5316 static int i915_forcewake_open(struct inode *inode, struct file *file)
5317 {
5318         struct drm_i915_private *dev_priv = inode->i_private;
5319
5320         if (INTEL_GEN(dev_priv) < 6)
5321                 return 0;
5322
5323         intel_runtime_pm_get(dev_priv);
5324         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5325
5326         return 0;
5327 }
5328
5329 static int i915_forcewake_release(struct inode *inode, struct file *file)
5330 {
5331         struct drm_i915_private *dev_priv = inode->i_private;
5332
5333         if (INTEL_GEN(dev_priv) < 6)
5334                 return 0;
5335
5336         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5337         intel_runtime_pm_put(dev_priv);
5338
5339         return 0;
5340 }
5341
5342 static const struct file_operations i915_forcewake_fops = {
5343         .owner = THIS_MODULE,
5344         .open = i915_forcewake_open,
5345         .release = i915_forcewake_release,
5346 };
5347
5348 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5349 {
5350         struct dentry *ent;
5351
5352         ent = debugfs_create_file("i915_forcewake_user",
5353                                   S_IRUSR,
5354                                   root, to_i915(minor->dev),
5355                                   &i915_forcewake_fops);
5356         if (!ent)
5357                 return -ENOMEM;
5358
5359         return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
5360 }
5361
5362 static int i915_debugfs_create(struct dentry *root,
5363                                struct drm_minor *minor,
5364                                const char *name,
5365                                const struct file_operations *fops)
5366 {
5367         struct dentry *ent;
5368
5369         ent = debugfs_create_file(name,
5370                                   S_IRUGO | S_IWUSR,
5371                                   root, to_i915(minor->dev),
5372                                   fops);
5373         if (!ent)
5374                 return -ENOMEM;
5375
5376         return drm_add_fake_info_node(minor, ent, fops);
5377 }
5378
5379 static const struct drm_info_list i915_debugfs_list[] = {
5380         {"i915_capabilities", i915_capabilities, 0},
5381         {"i915_gem_objects", i915_gem_object_info, 0},
5382         {"i915_gem_gtt", i915_gem_gtt_info, 0},
5383         {"i915_gem_pin_display", i915_gem_gtt_info, 0, (void *)1},
5384         {"i915_gem_stolen", i915_gem_stolen_list_info },
5385         {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
5386         {"i915_gem_request", i915_gem_request_info, 0},
5387         {"i915_gem_seqno", i915_gem_seqno_info, 0},
5388         {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
5389         {"i915_gem_interrupt", i915_interrupt_info, 0},
5390         {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5391         {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5392         {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
5393         {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
5394         {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
5395         {"i915_guc_info", i915_guc_info, 0},
5396         {"i915_guc_load_status", i915_guc_load_status_info, 0},
5397         {"i915_guc_log_dump", i915_guc_log_dump, 0},
5398         {"i915_frequency_info", i915_frequency_info, 0},
5399         {"i915_hangcheck_info", i915_hangcheck_info, 0},
5400         {"i915_drpc_info", i915_drpc_info, 0},
5401         {"i915_emon_status", i915_emon_status, 0},
5402         {"i915_ring_freq_table", i915_ring_freq_table, 0},
5403         {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
5404         {"i915_fbc_status", i915_fbc_status, 0},
5405         {"i915_ips_status", i915_ips_status, 0},
5406         {"i915_sr_status", i915_sr_status, 0},
5407         {"i915_opregion", i915_opregion, 0},
5408         {"i915_vbt", i915_vbt, 0},
5409         {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
5410         {"i915_context_status", i915_context_status, 0},
5411         {"i915_dump_lrc", i915_dump_lrc, 0},
5412         {"i915_forcewake_domains", i915_forcewake_domains, 0},
5413         {"i915_swizzle_info", i915_swizzle_info, 0},
5414         {"i915_ppgtt_info", i915_ppgtt_info, 0},
5415         {"i915_llc", i915_llc, 0},
5416         {"i915_edp_psr_status", i915_edp_psr_status, 0},
5417         {"i915_sink_crc_eDP1", i915_sink_crc, 0},
5418         {"i915_energy_uJ", i915_energy_uJ, 0},
5419         {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
5420         {"i915_power_domain_info", i915_power_domain_info, 0},
5421         {"i915_dmc_info", i915_dmc_info, 0},
5422         {"i915_display_info", i915_display_info, 0},
5423         {"i915_engine_info", i915_engine_info, 0},
5424         {"i915_semaphore_status", i915_semaphore_status, 0},
5425         {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
5426         {"i915_dp_mst_info", i915_dp_mst_info, 0},
5427         {"i915_wa_registers", i915_wa_registers, 0},
5428         {"i915_ddb_info", i915_ddb_info, 0},
5429         {"i915_sseu_status", i915_sseu_status, 0},
5430         {"i915_drrs_status", i915_drrs_status, 0},
5431         {"i915_rps_boost_info", i915_rps_boost_info, 0},
5432 };
5433 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5434
5435 static const struct i915_debugfs_files {
5436         const char *name;
5437         const struct file_operations *fops;
5438 } i915_debugfs_files[] = {
5439         {"i915_wedged", &i915_wedged_fops},
5440         {"i915_max_freq", &i915_max_freq_fops},
5441         {"i915_min_freq", &i915_min_freq_fops},
5442         {"i915_cache_sharing", &i915_cache_sharing_fops},
5443         {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5444         {"i915_ring_test_irq", &i915_ring_test_irq_fops},
5445         {"i915_gem_drop_caches", &i915_drop_caches_fops},
5446 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
5447         {"i915_error_state", &i915_error_state_fops},
5448 #endif
5449         {"i915_next_seqno", &i915_next_seqno_fops},
5450         {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
5451         {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5452         {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5453         {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
5454         {"i915_fbc_false_color", &i915_fbc_fc_fops},
5455         {"i915_dp_test_data", &i915_displayport_test_data_fops},
5456         {"i915_dp_test_type", &i915_displayport_test_type_fops},
5457         {"i915_dp_test_active", &i915_displayport_test_active_fops}
5458 };
5459
5460 void intel_display_crc_init(struct drm_i915_private *dev_priv)
5461 {
5462         enum pipe pipe;
5463
5464         for_each_pipe(dev_priv, pipe) {
5465                 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
5466
5467                 pipe_crc->opened = false;
5468                 spin_lock_init(&pipe_crc->lock);
5469                 init_waitqueue_head(&pipe_crc->wq);
5470         }
5471 }
5472
5473 int i915_debugfs_register(struct drm_i915_private *dev_priv)
5474 {
5475         struct drm_minor *minor = dev_priv->drm.primary;
5476         int ret, i;
5477
5478         ret = i915_forcewake_create(minor->debugfs_root, minor);
5479         if (ret)
5480                 return ret;
5481
5482         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5483                 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5484                 if (ret)
5485                         return ret;
5486         }
5487
5488         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5489                 ret = i915_debugfs_create(minor->debugfs_root, minor,
5490                                           i915_debugfs_files[i].name,
5491                                           i915_debugfs_files[i].fops);
5492                 if (ret)
5493                         return ret;
5494         }
5495
5496         return drm_debugfs_create_files(i915_debugfs_list,
5497                                         I915_DEBUGFS_ENTRIES,
5498                                         minor->debugfs_root, minor);
5499 }
5500
5501 void i915_debugfs_unregister(struct drm_i915_private *dev_priv)
5502 {
5503         struct drm_minor *minor = dev_priv->drm.primary;
5504         int i;
5505
5506         drm_debugfs_remove_files(i915_debugfs_list,
5507                                  I915_DEBUGFS_ENTRIES, minor);
5508
5509         drm_debugfs_remove_files((struct drm_info_list *)&i915_forcewake_fops,
5510                                  1, minor);
5511
5512         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5513                 struct drm_info_list *info_list =
5514                         (struct drm_info_list *)&i915_pipe_crc_data[i];
5515
5516                 drm_debugfs_remove_files(info_list, 1, minor);
5517         }
5518
5519         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5520                 struct drm_info_list *info_list =
5521                         (struct drm_info_list *)i915_debugfs_files[i].fops;
5522
5523                 drm_debugfs_remove_files(info_list, 1, minor);
5524         }
5525 }
5526
5527 struct dpcd_block {
5528         /* DPCD dump start address. */
5529         unsigned int offset;
5530         /* DPCD dump end address, inclusive. If unset, .size will be used. */
5531         unsigned int end;
5532         /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5533         size_t size;
5534         /* Only valid for eDP. */
5535         bool edp;
5536 };
5537
5538 static const struct dpcd_block i915_dpcd_debug[] = {
5539         { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5540         { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5541         { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5542         { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5543         { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5544         { .offset = DP_SET_POWER },
5545         { .offset = DP_EDP_DPCD_REV },
5546         { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5547         { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5548         { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5549 };
5550
5551 static int i915_dpcd_show(struct seq_file *m, void *data)
5552 {
5553         struct drm_connector *connector = m->private;
5554         struct intel_dp *intel_dp =
5555                 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5556         uint8_t buf[16];
5557         ssize_t err;
5558         int i;
5559
5560         if (connector->status != connector_status_connected)
5561                 return -ENODEV;
5562
5563         for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5564                 const struct dpcd_block *b = &i915_dpcd_debug[i];
5565                 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5566
5567                 if (b->edp &&
5568                     connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5569                         continue;
5570
5571                 /* low tech for now */
5572                 if (WARN_ON(size > sizeof(buf)))
5573                         continue;
5574
5575                 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5576                 if (err <= 0) {
5577                         DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5578                                   size, b->offset, err);
5579                         continue;
5580                 }
5581
5582                 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
5583         }
5584
5585         return 0;
5586 }
5587
5588 static int i915_dpcd_open(struct inode *inode, struct file *file)
5589 {
5590         return single_open(file, i915_dpcd_show, inode->i_private);
5591 }
5592
5593 static const struct file_operations i915_dpcd_fops = {
5594         .owner = THIS_MODULE,
5595         .open = i915_dpcd_open,
5596         .read = seq_read,
5597         .llseek = seq_lseek,
5598         .release = single_release,
5599 };
5600
5601 static int i915_panel_show(struct seq_file *m, void *data)
5602 {
5603         struct drm_connector *connector = m->private;
5604         struct intel_dp *intel_dp =
5605                 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5606
5607         if (connector->status != connector_status_connected)
5608                 return -ENODEV;
5609
5610         seq_printf(m, "Panel power up delay: %d\n",
5611                    intel_dp->panel_power_up_delay);
5612         seq_printf(m, "Panel power down delay: %d\n",
5613                    intel_dp->panel_power_down_delay);
5614         seq_printf(m, "Backlight on delay: %d\n",
5615                    intel_dp->backlight_on_delay);
5616         seq_printf(m, "Backlight off delay: %d\n",
5617                    intel_dp->backlight_off_delay);
5618
5619         return 0;
5620 }
5621
5622 static int i915_panel_open(struct inode *inode, struct file *file)
5623 {
5624         return single_open(file, i915_panel_show, inode->i_private);
5625 }
5626
5627 static const struct file_operations i915_panel_fops = {
5628         .owner = THIS_MODULE,
5629         .open = i915_panel_open,
5630         .read = seq_read,
5631         .llseek = seq_lseek,
5632         .release = single_release,
5633 };
5634
5635 /**
5636  * i915_debugfs_connector_add - add i915 specific connector debugfs files
5637  * @connector: pointer to a registered drm_connector
5638  *
5639  * Cleanup will be done by drm_connector_unregister() through a call to
5640  * drm_debugfs_connector_remove().
5641  *
5642  * Returns 0 on success, negative error codes on error.
5643  */
5644 int i915_debugfs_connector_add(struct drm_connector *connector)
5645 {
5646         struct dentry *root = connector->debugfs_entry;
5647
5648         /* The connector must have been registered beforehands. */
5649         if (!root)
5650                 return -ENODEV;
5651
5652         if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5653             connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5654                 debugfs_create_file("i915_dpcd", S_IRUGO, root,
5655                                     connector, &i915_dpcd_fops);
5656
5657         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5658                 debugfs_create_file("i915_panel_timings", S_IRUGO, root,
5659                                     connector, &i915_panel_fops);
5660
5661         return 0;
5662 }