drivers/gpu/drm/i915/i915_debugfs.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *
  27  */
  28
  29 #include <linux/seq_file.h>
  30 #include <linux/circ_buf.h>
  31 #include <linux/ctype.h>
  32 #include <linux/debugfs.h>
  33 #include <linux/slab.h>
  34 #include <linux/export.h>
  35 #include <linux/list_sort.h>
  36 #include <asm/msr-index.h>
  37 #include <drm/drmP.h>
  38 #include "intel_drv.h"
  39 #include "intel_ringbuffer.h"
  40 #include <drm/i915_drm.h>
  41 #include "i915_drv.h"
  42
  43 enum {
  44         ACTIVE_LIST,
  45         INACTIVE_LIST,
  46         PINNED_LIST,
  47 };
  48
  49 /* As the drm_debugfs_init() routines are called before dev->dev_private is
  50  * allocated we need to hook into the minor for release. */
  51 static int
  52 drm_add_fake_info_node(struct drm_minor *minor,
  53                        struct dentry *ent,
  54                        const void *key)
  55 {
  56         struct drm_info_node *node;
  57
  58         node = kmalloc(sizeof(*node), GFP_KERNEL);
  59         if (node == NULL) {
  60                 debugfs_remove(ent);
  61                 return -ENOMEM;
  62         }
  63
  64         node->minor = minor;
  65         node->dent = ent;
  66         node->info_ent = (void *) key;
  67
  68         mutex_lock(&minor->debugfs_lock);
  69         list_add(&node->list, &minor->debugfs_list);
  70         mutex_unlock(&minor->debugfs_lock);
  71
  72         return 0;
  73 }
  74
  75 static int i915_capabilities(struct seq_file *m, void *data)
  76 {
  77         struct drm_info_node *node = m->private;
  78         struct drm_device *dev = node->minor->dev;
  79         const struct intel_device_info *info = INTEL_INFO(dev);
  80
  81         seq_printf(m, "gen: %d\n", info->gen);
  82         seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
  83 #define PRINT_FLAG(x)  seq_printf(m, #x ": %s\n", yesno(info->x))
  84 #define SEP_SEMICOLON ;
  85         DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
  86 #undef PRINT_FLAG
  87 #undef SEP_SEMICOLON
  88
  89         return 0;
  90 }
  91
  92 static const char *get_pin_flag(struct drm_i915_gem_object *obj)
  93 {
  94         if (obj->pin_display)
  95                 return "p";
  96         else
  97                 return " ";
  98 }
  99
 100 static const char *get_tiling_flag(struct drm_i915_gem_object *obj)
 101 {
 102         switch (obj->tiling_mode) {
 103         default:
 104         case I915_TILING_NONE: return " ";
 105         case I915_TILING_X: return "X";
 106         case I915_TILING_Y: return "Y";
 107         }
 108 }
 109
 110 static inline const char *get_global_flag(struct drm_i915_gem_object *obj)
 111 {
 112         return i915_gem_obj_to_ggtt(obj) ? "g" : " ";
 113 }
 114
 115 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
 116 {
 117         u64 size = 0;
 118         struct i915_vma *vma;
 119
 120         list_for_each_entry(vma, &obj->vma_list, vma_link) {
 121                 if (i915_is_ggtt(vma->vm) &&
 122                     drm_mm_node_allocated(&vma->node))
 123                         size += vma->node.size;
 124         }
 125
 126         return size;
 127 }
 128
 129 static void
 130 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
 131 {
 132         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
 133         struct intel_engine_cs *ring;
 134         struct i915_vma *vma;
 135         int pin_count = 0;
 136         int i;
 137
 138         seq_printf(m, "%pK: %s%s%s%s %8zdKiB %02x %02x [ ",
 139                    &obj->base,
 140                    obj->active ? "*" : " ",
 141                    get_pin_flag(obj),
 142                    get_tiling_flag(obj),
 143                    get_global_flag(obj),
 144                    obj->base.size / 1024,
 145                    obj->base.read_domains,
 146                    obj->base.write_domain);
 147         for_each_ring(ring, dev_priv, i)
 148                 seq_printf(m, "%x ",
 149                                 i915_gem_request_get_seqno(obj->last_read_req[i]));
 150         seq_printf(m, "] %x %x%s%s%s",
 151                    i915_gem_request_get_seqno(obj->last_write_req),
 152                    i915_gem_request_get_seqno(obj->last_fenced_req),
 153                    i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
 154                    obj->dirty ? " dirty" : "",
 155                    obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
 156         if (obj->base.name)
 157                 seq_printf(m, " (name: %d)", obj->base.name);
 158         list_for_each_entry(vma, &obj->vma_list, vma_link) {
 159                 if (vma->pin_count > 0)
 160                         pin_count++;
 161         }
 162         seq_printf(m, " (pinned x %d)", pin_count);
 163         if (obj->pin_display)
 164                 seq_printf(m, " (display)");
 165         if (obj->fence_reg != I915_FENCE_REG_NONE)
 166                 seq_printf(m, " (fence: %d)", obj->fence_reg);
 167         list_for_each_entry(vma, &obj->vma_list, vma_link) {
 168                 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
 169                            i915_is_ggtt(vma->vm) ? "g" : "pp",
 170                            vma->node.start, vma->node.size);
 171                 if (i915_is_ggtt(vma->vm))
 172                         seq_printf(m, ", type: %u)", vma->ggtt_view.type);
 173                 else
 174                         seq_puts(m, ")");
 175         }
 176         if (obj->stolen)
 177                 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
 178         if (obj->pin_display || obj->fault_mappable) {
 179                 char s[3], *t = s;
 180                 if (obj->pin_display)
 181                         *t++ = 'p';
 182                 if (obj->fault_mappable)
 183                         *t++ = 'f';
 184                 *t = '\0';
 185                 seq_printf(m, " (%s mappable)", s);
 186         }
 187         if (obj->last_write_req != NULL)
 188                 seq_printf(m, " (%s)",
 189                            i915_gem_request_get_ring(obj->last_write_req)->name);
 190         if (obj->frontbuffer_bits)
 191                 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
 192 }
 193
 194 static void describe_ctx(struct seq_file *m, struct intel_context *ctx)
 195 {
 196         seq_putc(m, ctx->legacy_hw_ctx.initialized ? 'I' : 'i');
 197         seq_putc(m, ctx->remap_slice ? 'R' : 'r');
 198         seq_putc(m, ' ');
 199 }
 200
 201 static int i915_gem_object_list_info(struct seq_file *m, void *data)
 202 {
 203         struct drm_info_node *node = m->private;
 204         uintptr_t list = (uintptr_t) node->info_ent->data;
 205         struct list_head *head;
 206         struct drm_device *dev = node->minor->dev;
 207         struct drm_i915_private *dev_priv = dev->dev_private;
 208         struct i915_address_space *vm = &dev_priv->gtt.base;
 209         struct i915_vma *vma;
 210         u64 total_obj_size, total_gtt_size;
 211         int count, ret;
 212
 213         ret = mutex_lock_interruptible(&dev->struct_mutex);
 214         if (ret)
 215                 return ret;
 216
 217         /* FIXME: the user of this interface might want more than just GGTT */
 218         switch (list) {
 219         case ACTIVE_LIST:
 220                 seq_puts(m, "Active:\n");
 221                 head = &vm->active_list;
 222                 break;
 223         case INACTIVE_LIST:
 224                 seq_puts(m, "Inactive:\n");
 225                 head = &vm->inactive_list;
 226                 break;
 227         default:
 228                 mutex_unlock(&dev->struct_mutex);
 229                 return -EINVAL;
 230         }
 231
 232         total_obj_size = total_gtt_size = count = 0;
 233         list_for_each_entry(vma, head, mm_list) {
 234                 seq_printf(m, "   ");
 235                 describe_obj(m, vma->obj);
 236                 seq_printf(m, "\n");
 237                 total_obj_size += vma->obj->base.size;
 238                 total_gtt_size += vma->node.size;
 239                 count++;
 240         }
 241         mutex_unlock(&dev->struct_mutex);
 242
 243         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 244                    count, total_obj_size, total_gtt_size);
 245         return 0;
 246 }
 247
 248 static int obj_rank_by_stolen(void *priv,
 249                               struct list_head *A, struct list_head *B)
 250 {
 251         struct drm_i915_gem_object *a =
 252                 container_of(A, struct drm_i915_gem_object, obj_exec_link);
 253         struct drm_i915_gem_object *b =
 254                 container_of(B, struct drm_i915_gem_object, obj_exec_link);
 255
 256         if (a->stolen->start < b->stolen->start)
 257                 return -1;
 258         if (a->stolen->start > b->stolen->start)
 259                 return 1;
 260         return 0;
 261 }
 262
 263 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
 264 {
 265         struct drm_info_node *node = m->private;
 266         struct drm_device *dev = node->minor->dev;
 267         struct drm_i915_private *dev_priv = dev->dev_private;
 268         struct drm_i915_gem_object *obj;
 269         u64 total_obj_size, total_gtt_size;
 270         LIST_HEAD(stolen);
 271         int count, ret;
 272
 273         ret = mutex_lock_interruptible(&dev->struct_mutex);
 274         if (ret)
 275                 return ret;
 276
 277         total_obj_size = total_gtt_size = count = 0;
 278         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 279                 if (obj->stolen == NULL)
 280                         continue;
 281
 282                 list_add(&obj->obj_exec_link, &stolen);
 283
 284                 total_obj_size += obj->base.size;
 285                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 286                 count++;
 287         }
 288         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 289                 if (obj->stolen == NULL)
 290                         continue;
 291
 292                 list_add(&obj->obj_exec_link, &stolen);
 293
 294                 total_obj_size += obj->base.size;
 295                 count++;
 296         }
 297         list_sort(NULL, &stolen, obj_rank_by_stolen);
 298         seq_puts(m, "Stolen:\n");
 299         while (!list_empty(&stolen)) {
 300                 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
 301                 seq_puts(m, "   ");
 302                 describe_obj(m, obj);
 303                 seq_putc(m, '\n');
 304                 list_del_init(&obj->obj_exec_link);
 305         }
 306         mutex_unlock(&dev->struct_mutex);
 307
 308         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 309                    count, total_obj_size, total_gtt_size);
 310         return 0;
 311 }
 312
 313 #define count_objects(list, member) do { \
 314         list_for_each_entry(obj, list, member) { \
 315                 size += i915_gem_obj_total_ggtt_size(obj); \
 316                 ++count; \
 317                 if (obj->map_and_fenceable) { \
 318                         mappable_size += i915_gem_obj_ggtt_size(obj); \
 319                         ++mappable_count; \
 320                 } \
 321         } \
 322 } while (0)
 323
 324 struct file_stats {
 325         struct drm_i915_file_private *file_priv;
 326         unsigned long count;
 327         u64 total, unbound;
 328         u64 global, shared;
 329         u64 active, inactive;
 330 };
 331
 332 static int per_file_stats(int id, void *ptr, void *data)
 333 {
 334         struct drm_i915_gem_object *obj = ptr;
 335         struct file_stats *stats = data;
 336         struct i915_vma *vma;
 337
 338         stats->count++;
 339         stats->total += obj->base.size;
 340
 341         if (obj->base.name || obj->base.dma_buf)
 342                 stats->shared += obj->base.size;
 343
 344         if (USES_FULL_PPGTT(obj->base.dev)) {
 345                 list_for_each_entry(vma, &obj->vma_list, vma_link) {
 346                         struct i915_hw_ppgtt *ppgtt;
 347
 348                         if (!drm_mm_node_allocated(&vma->node))
 349                                 continue;
 350
 351                         if (i915_is_ggtt(vma->vm)) {
 352                                 stats->global += obj->base.size;
 353                                 continue;
 354                         }
 355
 356                         ppgtt = container_of(vma->vm, struct i915_hw_ppgtt, base);
 357                         if (ppgtt->file_priv != stats->file_priv)
 358                                 continue;
 359
 360                         if (obj->active) /* XXX per-vma statistic */
 361                                 stats->active += obj->base.size;
 362                         else
 363                                 stats->inactive += obj->base.size;
 364
 365                         return 0;
 366                 }
 367         } else {
 368                 if (i915_gem_obj_ggtt_bound(obj)) {
 369                         stats->global += obj->base.size;
 370                         if (obj->active)
 371                                 stats->active += obj->base.size;
 372                         else
 373                                 stats->inactive += obj->base.size;
 374                         return 0;
 375                 }
 376         }
 377
 378         if (!list_empty(&obj->global_list))
 379                 stats->unbound += obj->base.size;
 380
 381         return 0;
 382 }
 383
 384 #define print_file_stats(m, name, stats) do { \
 385         if (stats.count) \
 386                 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
 387                            name, \
 388                            stats.count, \
 389                            stats.total, \
 390                            stats.active, \
 391                            stats.inactive, \
 392                            stats.global, \
 393                            stats.shared, \
 394                            stats.unbound); \
 395 } while (0)
 396
 397 static void print_batch_pool_stats(struct seq_file *m,
 398                                    struct drm_i915_private *dev_priv)
 399 {
 400         struct drm_i915_gem_object *obj;
 401         struct file_stats stats;
 402         struct intel_engine_cs *ring;
 403         int i, j;
 404
 405         memset(&stats, 0, sizeof(stats));
 406
 407         for_each_ring(ring, dev_priv, i) {
 408                 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
 409                         list_for_each_entry(obj,
 410                                             &ring->batch_pool.cache_list[j],
 411                                             batch_pool_link)
 412                                 per_file_stats(0, obj, &stats);
 413                 }
 414         }
 415
 416         print_file_stats(m, "[k]batch pool", stats);
 417 }
 418
 419 #define count_vmas(list, member) do { \
 420         list_for_each_entry(vma, list, member) { \
 421                 size += i915_gem_obj_total_ggtt_size(vma->obj); \
 422                 ++count; \
 423                 if (vma->obj->map_and_fenceable) { \
 424                         mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
 425                         ++mappable_count; \
 426                 } \
 427         } \
 428 } while (0)
 429
 430 static int i915_gem_object_info(struct seq_file *m, void* data)
 431 {
 432         struct drm_info_node *node = m->private;
 433         struct drm_device *dev = node->minor->dev;
 434         struct drm_i915_private *dev_priv = dev->dev_private;
 435         u32 count, mappable_count, purgeable_count;
 436         u64 size, mappable_size, purgeable_size;
 437         struct drm_i915_gem_object *obj;
 438         struct i915_address_space *vm = &dev_priv->gtt.base;
 439         struct drm_file *file;
 440         struct i915_vma *vma;
 441         int ret;
 442
 443         ret = mutex_lock_interruptible(&dev->struct_mutex);
 444         if (ret)
 445                 return ret;
 446
 447         seq_printf(m, "%u objects, %zu bytes\n",
 448                    dev_priv->mm.object_count,
 449                    dev_priv->mm.object_memory);
 450
 451         size = count = mappable_size = mappable_count = 0;
 452         count_objects(&dev_priv->mm.bound_list, global_list);
 453         seq_printf(m, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
 454                    count, mappable_count, size, mappable_size);
 455
 456         size = count = mappable_size = mappable_count = 0;
 457         count_vmas(&vm->active_list, mm_list);
 458         seq_printf(m, "  %u [%u] active objects, %llu [%llu] bytes\n",
 459                    count, mappable_count, size, mappable_size);
 460
 461         size = count = mappable_size = mappable_count = 0;
 462         count_vmas(&vm->inactive_list, mm_list);
 463         seq_printf(m, "  %u [%u] inactive objects, %llu [%llu] bytes\n",
 464                    count, mappable_count, size, mappable_size);
 465
 466         size = count = purgeable_size = purgeable_count = 0;
 467         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 468                 size += obj->base.size, ++count;
 469                 if (obj->madv == I915_MADV_DONTNEED)
 470                         purgeable_size += obj->base.size, ++purgeable_count;
 471         }
 472         seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
 473
 474         size = count = mappable_size = mappable_count = 0;
 475         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 476                 if (obj->fault_mappable) {
 477                         size += i915_gem_obj_ggtt_size(obj);
 478                         ++count;
 479                 }
 480                 if (obj->pin_display) {
 481                         mappable_size += i915_gem_obj_ggtt_size(obj);
 482                         ++mappable_count;
 483                 }
 484                 if (obj->madv == I915_MADV_DONTNEED) {
 485                         purgeable_size += obj->base.size;
 486                         ++purgeable_count;
 487                 }
 488         }
 489         seq_printf(m, "%u purgeable objects, %llu bytes\n",
 490                    purgeable_count, purgeable_size);
 491         seq_printf(m, "%u pinned mappable objects, %llu bytes\n",
 492                    mappable_count, mappable_size);
 493         seq_printf(m, "%u fault mappable objects, %llu bytes\n",
 494                    count, size);
 495
 496         seq_printf(m, "%llu [%llu] gtt total\n",
 497                    dev_priv->gtt.base.total,
 498                    (u64)dev_priv->gtt.mappable_end - dev_priv->gtt.base.start);
 499
 500         seq_putc(m, '\n');
 501         print_batch_pool_stats(m, dev_priv);
 502         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
 503                 struct file_stats stats;
 504                 struct task_struct *task;
 505
 506                 memset(&stats, 0, sizeof(stats));
 507                 stats.file_priv = file->driver_priv;
 508                 spin_lock(&file->table_lock);
 509                 idr_for_each(&file->object_idr, per_file_stats, &stats);
 510                 spin_unlock(&file->table_lock);
 511                 /*
 512                  * Although we have a valid reference on file->pid, that does
 513                  * not guarantee that the task_struct who called get_pid() is
 514                  * still alive (e.g. get_pid(current) => fork() => exit()).
 515                  * Therefore, we need to protect this ->comm access using RCU.
 516                  */
 517                 rcu_read_lock();
 518                 task = pid_task(file->pid, PIDTYPE_PID);
 519                 print_file_stats(m, task ? task->comm : "<unknown>", stats);
 520                 rcu_read_unlock();
 521         }
 522
 523         mutex_unlock(&dev->struct_mutex);
 524
 525         return 0;
 526 }
 527
 528 static int i915_gem_gtt_info(struct seq_file *m, void *data)
 529 {
 530         struct drm_info_node *node = m->private;
 531         struct drm_device *dev = node->minor->dev;
 532         uintptr_t list = (uintptr_t) node->info_ent->data;
 533         struct drm_i915_private *dev_priv = dev->dev_private;
 534         struct drm_i915_gem_object *obj;
 535         u64 total_obj_size, total_gtt_size;
 536         int count, ret;
 537
 538         ret = mutex_lock_interruptible(&dev->struct_mutex);
 539         if (ret)
 540                 return ret;
 541
 542         total_obj_size = total_gtt_size = count = 0;
 543         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 544                 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
 545                         continue;
 546
 547                 seq_puts(m, "   ");
 548                 describe_obj(m, obj);
 549                 seq_putc(m, '\n');
 550                 total_obj_size += obj->base.size;
 551                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 552                 count++;
 553         }
 554
 555         mutex_unlock(&dev->struct_mutex);
 556
 557         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 558                    count, total_obj_size, total_gtt_size);
 559
 560         return 0;
 561 }
 562
 563 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
 564 {
 565         struct drm_info_node *node = m->private;
 566         struct drm_device *dev = node->minor->dev;
 567         struct drm_i915_private *dev_priv = dev->dev_private;
 568         struct intel_crtc *crtc;
 569         int ret;
 570
 571         ret = mutex_lock_interruptible(&dev->struct_mutex);
 572         if (ret)
 573                 return ret;
 574
 575         for_each_intel_crtc(dev, crtc) {
 576                 const char pipe = pipe_name(crtc->pipe);
 577                 const char plane = plane_name(crtc->plane);
 578                 struct intel_unpin_work *work;
 579
 580                 spin_lock_irq(&dev->event_lock);
 581                 work = crtc->unpin_work;
 582                 if (work == NULL) {
 583                         seq_printf(m, "No flip due on pipe %c (plane %c)\n",
 584                                    pipe, plane);
 585                 } else {
 586                         u32 addr;
 587
 588                         if (atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
 589                                 seq_printf(m, "Flip queued on pipe %c (plane %c)\n",
 590                                            pipe, plane);
 591                         } else {
 592                                 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
 593                                            pipe, plane);
 594                         }
 595                         if (work->flip_queued_req) {
 596                                 struct intel_engine_cs *ring =
 597                                         i915_gem_request_get_ring(work->flip_queued_req);
 598
 599                                 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
 600                                            ring->name,
 601                                            i915_gem_request_get_seqno(work->flip_queued_req),
 602                                            dev_priv->next_seqno,
 603                                            ring->get_seqno(ring, true),
 604                                            i915_gem_request_completed(work->flip_queued_req, true));
 605                         } else
 606                                 seq_printf(m, "Flip not associated with any ring\n");
 607                         seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
 608                                    work->flip_queued_vblank,
 609                                    work->flip_ready_vblank,
 610                                    drm_crtc_vblank_count(&crtc->base));
 611                         if (work->enable_stall_check)
 612                                 seq_puts(m, "Stall check enabled, ");
 613                         else
 614                                 seq_puts(m, "Stall check waiting for page flip ioctl, ");
 615                         seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
 616
 617                         if (INTEL_INFO(dev)->gen >= 4)
 618                                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
 619                         else
 620                                 addr = I915_READ(DSPADDR(crtc->plane));
 621                         seq_printf(m, "Current scanout address 0x%08x\n", addr);
 622
 623                         if (work->pending_flip_obj) {
 624                                 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
 625                                 seq_printf(m, "MMIO update completed? %d\n",  addr == work->gtt_offset);
 626                         }
 627                 }
 628                 spin_unlock_irq(&dev->event_lock);
 629         }
 630
 631         mutex_unlock(&dev->struct_mutex);
 632
 633         return 0;
 634 }
 635
 636 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
 637 {
 638         struct drm_info_node *node = m->private;
 639         struct drm_device *dev = node->minor->dev;
 640         struct drm_i915_private *dev_priv = dev->dev_private;
 641         struct drm_i915_gem_object *obj;
 642         struct intel_engine_cs *ring;
 643         int total = 0;
 644         int ret, i, j;
 645
 646         ret = mutex_lock_interruptible(&dev->struct_mutex);
 647         if (ret)
 648                 return ret;
 649
 650         for_each_ring(ring, dev_priv, i) {
 651                 for (j = 0; j < ARRAY_SIZE(ring->batch_pool.cache_list); j++) {
 652                         int count;
 653
 654                         count = 0;
 655                         list_for_each_entry(obj,
 656                                             &ring->batch_pool.cache_list[j],
 657                                             batch_pool_link)
 658                                 count++;
 659                         seq_printf(m, "%s cache[%d]: %d objects\n",
 660                                    ring->name, j, count);
 661
 662                         list_for_each_entry(obj,
 663                                             &ring->batch_pool.cache_list[j],
 664                                             batch_pool_link) {
 665                                 seq_puts(m, "   ");
 666                                 describe_obj(m, obj);
 667                                 seq_putc(m, '\n');
 668                         }
 669
 670                         total += count;
 671                 }
 672         }
 673
 674         seq_printf(m, "total: %d\n", total);
 675
 676         mutex_unlock(&dev->struct_mutex);
 677
 678         return 0;
 679 }
 680
 681 static int i915_gem_request_info(struct seq_file *m, void *data)
 682 {
 683         struct drm_info_node *node = m->private;
 684         struct drm_device *dev = node->minor->dev;
 685         struct drm_i915_private *dev_priv = dev->dev_private;
 686         struct intel_engine_cs *ring;
 687         struct drm_i915_gem_request *req;
 688         int ret, any, i;
 689
 690         ret = mutex_lock_interruptible(&dev->struct_mutex);
 691         if (ret)
 692                 return ret;
 693
 694         any = 0;
 695         for_each_ring(ring, dev_priv, i) {
 696                 int count;
 697
 698                 count = 0;
 699                 list_for_each_entry(req, &ring->request_list, list)
 700                         count++;
 701                 if (count == 0)
 702                         continue;
 703
 704                 seq_printf(m, "%s requests: %d\n", ring->name, count);
 705                 list_for_each_entry(req, &ring->request_list, list) {
 706                         struct task_struct *task;
 707
 708                         rcu_read_lock();
 709                         task = NULL;
 710                         if (req->pid)
 711                                 task = pid_task(req->pid, PIDTYPE_PID);
 712                         seq_printf(m, "    %x @ %d: %s [%d]\n",
 713                                    req->seqno,
 714                                    (int) (jiffies - req->emitted_jiffies),
 715                                    task ? task->comm : "<unknown>",
 716                                    task ? task->pid : -1);
 717                         rcu_read_unlock();
 718                 }
 719
 720                 any++;
 721         }
 722         mutex_unlock(&dev->struct_mutex);
 723
 724         if (any == 0)
 725                 seq_puts(m, "No requests\n");
 726
 727         return 0;
 728 }
 729
 730 static void i915_ring_seqno_info(struct seq_file *m,
 731                                  struct intel_engine_cs *ring)
 732 {
 733         if (ring->get_seqno) {
 734                 seq_printf(m, "Current sequence (%s): %x\n",
 735                            ring->name, ring->get_seqno(ring, false));
 736         }
 737 }
 738
 739 static int i915_gem_seqno_info(struct seq_file *m, void *data)
 740 {
 741         struct drm_info_node *node = m->private;
 742         struct drm_device *dev = node->minor->dev;
 743         struct drm_i915_private *dev_priv = dev->dev_private;
 744         struct intel_engine_cs *ring;
 745         int ret, i;
 746
 747         ret = mutex_lock_interruptible(&dev->struct_mutex);
 748         if (ret)
 749                 return ret;
 750         intel_runtime_pm_get(dev_priv);
 751
 752         for_each_ring(ring, dev_priv, i)
 753                 i915_ring_seqno_info(m, ring);
 754
 755         intel_runtime_pm_put(dev_priv);
 756         mutex_unlock(&dev->struct_mutex);
 757
 758         return 0;
 759 }
 760
 761
 762 static int i915_interrupt_info(struct seq_file *m, void *data)
 763 {
 764         struct drm_info_node *node = m->private;
 765         struct drm_device *dev = node->minor->dev;
 766         struct drm_i915_private *dev_priv = dev->dev_private;
 767         struct intel_engine_cs *ring;
 768         int ret, i, pipe;
 769
 770         ret = mutex_lock_interruptible(&dev->struct_mutex);
 771         if (ret)
 772                 return ret;
 773         intel_runtime_pm_get(dev_priv);
 774
 775         if (IS_CHERRYVIEW(dev)) {
 776                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 777                            I915_READ(GEN8_MASTER_IRQ));
 778
 779                 seq_printf(m, "Display IER:\t%08x\n",
 780                            I915_READ(VLV_IER));
 781                 seq_printf(m, "Display IIR:\t%08x\n",
 782                            I915_READ(VLV_IIR));
 783                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 784                            I915_READ(VLV_IIR_RW));
 785                 seq_printf(m, "Display IMR:\t%08x\n",
 786                            I915_READ(VLV_IMR));
 787                 for_each_pipe(dev_priv, pipe)
 788                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 789                                    pipe_name(pipe),
 790                                    I915_READ(PIPESTAT(pipe)));
 791
 792                 seq_printf(m, "Port hotplug:\t%08x\n",
 793                            I915_READ(PORT_HOTPLUG_EN));
 794                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 795                            I915_READ(VLV_DPFLIPSTAT));
 796                 seq_printf(m, "DPINVGTT:\t%08x\n",
 797                            I915_READ(DPINVGTT));
 798
 799                 for (i = 0; i < 4; i++) {
 800                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 801                                    i, I915_READ(GEN8_GT_IMR(i)));
 802                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 803                                    i, I915_READ(GEN8_GT_IIR(i)));
 804                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 805                                    i, I915_READ(GEN8_GT_IER(i)));
 806                 }
 807
 808                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 809                            I915_READ(GEN8_PCU_IMR));
 810                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 811                            I915_READ(GEN8_PCU_IIR));
 812                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 813                            I915_READ(GEN8_PCU_IER));
 814         } else if (INTEL_INFO(dev)->gen >= 8) {
 815                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 816                            I915_READ(GEN8_MASTER_IRQ));
 817
 818                 for (i = 0; i < 4; i++) {
 819                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 820                                    i, I915_READ(GEN8_GT_IMR(i)));
 821                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 822                                    i, I915_READ(GEN8_GT_IIR(i)));
 823                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 824                                    i, I915_READ(GEN8_GT_IER(i)));
 825                 }
 826
 827                 for_each_pipe(dev_priv, pipe) {
 828                         if (!intel_display_power_is_enabled(dev_priv,
 829                                                 POWER_DOMAIN_PIPE(pipe))) {
 830                                 seq_printf(m, "Pipe %c power disabled\n",
 831                                            pipe_name(pipe));
 832                                 continue;
 833                         }
 834                         seq_printf(m, "Pipe %c IMR:\t%08x\n",
 835                                    pipe_name(pipe),
 836                                    I915_READ(GEN8_DE_PIPE_IMR(pipe)));
 837                         seq_printf(m, "Pipe %c IIR:\t%08x\n",
 838                                    pipe_name(pipe),
 839                                    I915_READ(GEN8_DE_PIPE_IIR(pipe)));
 840                         seq_printf(m, "Pipe %c IER:\t%08x\n",
 841                                    pipe_name(pipe),
 842                                    I915_READ(GEN8_DE_PIPE_IER(pipe)));
 843                 }
 844
 845                 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
 846                            I915_READ(GEN8_DE_PORT_IMR));
 847                 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
 848                            I915_READ(GEN8_DE_PORT_IIR));
 849                 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
 850                            I915_READ(GEN8_DE_PORT_IER));
 851
 852                 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
 853                            I915_READ(GEN8_DE_MISC_IMR));
 854                 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
 855                            I915_READ(GEN8_DE_MISC_IIR));
 856                 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
 857                            I915_READ(GEN8_DE_MISC_IER));
 858
 859                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 860                            I915_READ(GEN8_PCU_IMR));
 861                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 862                            I915_READ(GEN8_PCU_IIR));
 863                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 864                            I915_READ(GEN8_PCU_IER));
 865         } else if (IS_VALLEYVIEW(dev)) {
 866                 seq_printf(m, "Display IER:\t%08x\n",
 867                            I915_READ(VLV_IER));
 868                 seq_printf(m, "Display IIR:\t%08x\n",
 869                            I915_READ(VLV_IIR));
 870                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 871                            I915_READ(VLV_IIR_RW));
 872                 seq_printf(m, "Display IMR:\t%08x\n",
 873                            I915_READ(VLV_IMR));
 874                 for_each_pipe(dev_priv, pipe)
 875                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 876                                    pipe_name(pipe),
 877                                    I915_READ(PIPESTAT(pipe)));
 878
 879                 seq_printf(m, "Master IER:\t%08x\n",
 880                            I915_READ(VLV_MASTER_IER));
 881
 882                 seq_printf(m, "Render IER:\t%08x\n",
 883                            I915_READ(GTIER));
 884                 seq_printf(m, "Render IIR:\t%08x\n",
 885                            I915_READ(GTIIR));
 886                 seq_printf(m, "Render IMR:\t%08x\n",
 887                            I915_READ(GTIMR));
 888
 889                 seq_printf(m, "PM IER:\t\t%08x\n",
 890                            I915_READ(GEN6_PMIER));
 891                 seq_printf(m, "PM IIR:\t\t%08x\n",
 892                            I915_READ(GEN6_PMIIR));
 893                 seq_printf(m, "PM IMR:\t\t%08x\n",
 894                            I915_READ(GEN6_PMIMR));
 895
 896                 seq_printf(m, "Port hotplug:\t%08x\n",
 897                            I915_READ(PORT_HOTPLUG_EN));
 898                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 899                            I915_READ(VLV_DPFLIPSTAT));
 900                 seq_printf(m, "DPINVGTT:\t%08x\n",
 901                            I915_READ(DPINVGTT));
 902
 903         } else if (!HAS_PCH_SPLIT(dev)) {
 904                 seq_printf(m, "Interrupt enable:    %08x\n",
 905                            I915_READ(IER));
 906                 seq_printf(m, "Interrupt identity:  %08x\n",
 907                            I915_READ(IIR));
 908                 seq_printf(m, "Interrupt mask:      %08x\n",
 909                            I915_READ(IMR));
 910                 for_each_pipe(dev_priv, pipe)
 911                         seq_printf(m, "Pipe %c stat:         %08x\n",
 912                                    pipe_name(pipe),
 913                                    I915_READ(PIPESTAT(pipe)));
 914         } else {
 915                 seq_printf(m, "North Display Interrupt enable:          %08x\n",
 916                            I915_READ(DEIER));
 917                 seq_printf(m, "North Display Interrupt identity:        %08x\n",
 918                            I915_READ(DEIIR));
 919                 seq_printf(m, "North Display Interrupt mask:            %08x\n",
 920                            I915_READ(DEIMR));
 921                 seq_printf(m, "South Display Interrupt enable:          %08x\n",
 922                            I915_READ(SDEIER));
 923                 seq_printf(m, "South Display Interrupt identity:        %08x\n",
 924                            I915_READ(SDEIIR));
 925                 seq_printf(m, "South Display Interrupt mask:            %08x\n",
 926                            I915_READ(SDEIMR));
 927                 seq_printf(m, "Graphics Interrupt enable:               %08x\n",
 928                            I915_READ(GTIER));
 929                 seq_printf(m, "Graphics Interrupt identity:             %08x\n",
 930                            I915_READ(GTIIR));
 931                 seq_printf(m, "Graphics Interrupt mask:         %08x\n",
 932                            I915_READ(GTIMR));
 933         }
 934         for_each_ring(ring, dev_priv, i) {
 935                 if (INTEL_INFO(dev)->gen >= 6) {
 936                         seq_printf(m,
 937                                    "Graphics Interrupt mask (%s):       %08x\n",
 938                                    ring->name, I915_READ_IMR(ring));
 939                 }
 940                 i915_ring_seqno_info(m, ring);
 941         }
 942         intel_runtime_pm_put(dev_priv);
 943         mutex_unlock(&dev->struct_mutex);
 944
 945         return 0;
 946 }
 947
 948 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
 949 {
 950         struct drm_info_node *node = m->private;
 951         struct drm_device *dev = node->minor->dev;
 952         struct drm_i915_private *dev_priv = dev->dev_private;
 953         int i, ret;
 954
 955         ret = mutex_lock_interruptible(&dev->struct_mutex);
 956         if (ret)
 957                 return ret;
 958
 959         seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
 960         for (i = 0; i < dev_priv->num_fence_regs; i++) {
 961                 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
 962
 963                 seq_printf(m, "Fence %d, pin count = %d, object = ",
 964                            i, dev_priv->fence_regs[i].pin_count);
 965                 if (obj == NULL)
 966                         seq_puts(m, "unused");
 967                 else
 968                         describe_obj(m, obj);
 969                 seq_putc(m, '\n');
 970         }
 971
 972         mutex_unlock(&dev->struct_mutex);
 973         return 0;
 974 }
 975
 976 static int i915_hws_info(struct seq_file *m, void *data)
 977 {
 978         struct drm_info_node *node = m->private;
 979         struct drm_device *dev = node->minor->dev;
 980         struct drm_i915_private *dev_priv = dev->dev_private;
 981         struct intel_engine_cs *ring;
 982         const u32 *hws;
 983         int i;
 984
 985         ring = &dev_priv->ring[(uintptr_t)node->info_ent->data];
 986         hws = ring->status_page.page_addr;
 987         if (hws == NULL)
 988                 return 0;
 989
 990         for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
 991                 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
 992                            i * 4,
 993                            hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
 994         }
 995         return 0;
 996 }
 997
 998 static ssize_t
 999 i915_error_state_write(struct file *filp,
1000                        const char __user *ubuf,
1001                        size_t cnt,
1002                        loff_t *ppos)
1003 {
1004         struct i915_error_state_file_priv *error_priv = filp->private_data;
1005         struct drm_device *dev = error_priv->dev;
1006         int ret;
1007
1008         DRM_DEBUG_DRIVER("Resetting error state\n");
1009
1010         ret = mutex_lock_interruptible(&dev->struct_mutex);
1011         if (ret)
1012                 return ret;
1013
1014         i915_destroy_error_state(dev);
1015         mutex_unlock(&dev->struct_mutex);
1016
1017         return cnt;
1018 }
1019
1020 static int i915_error_state_open(struct inode *inode, struct file *file)
1021 {
1022         struct drm_device *dev = inode->i_private;
1023         struct i915_error_state_file_priv *error_priv;
1024
1025         error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
1026         if (!error_priv)
1027                 return -ENOMEM;
1028
1029         error_priv->dev = dev;
1030
1031         i915_error_state_get(dev, error_priv);
1032
1033         file->private_data = error_priv;
1034
1035         return 0;
1036 }
1037
1038 static int i915_error_state_release(struct inode *inode, struct file *file)
1039 {
1040         struct i915_error_state_file_priv *error_priv = file->private_data;
1041
1042         i915_error_state_put(error_priv);
1043         kfree(error_priv);
1044
1045         return 0;
1046 }
1047
1048 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1049                                      size_t count, loff_t *pos)
1050 {
1051         struct i915_error_state_file_priv *error_priv = file->private_data;
1052         struct drm_i915_error_state_buf error_str;
1053         loff_t tmp_pos = 0;
1054         ssize_t ret_count = 0;
1055         int ret;
1056
1057         ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
1058         if (ret)
1059                 return ret;
1060
1061         ret = i915_error_state_to_str(&error_str, error_priv);
1062         if (ret)
1063                 goto out;
1064
1065         ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1066                                             error_str.buf,
1067                                             error_str.bytes);
1068
1069         if (ret_count < 0)
1070                 ret = ret_count;
1071         else
1072                 *pos = error_str.start + ret_count;
1073 out:
1074         i915_error_state_buf_release(&error_str);
1075         return ret ?: ret_count;
1076 }
1077
1078 static const struct file_operations i915_error_state_fops = {
1079         .owner = THIS_MODULE,
1080         .open = i915_error_state_open,
1081         .read = i915_error_state_read,
1082         .write = i915_error_state_write,
1083         .llseek = default_llseek,
1084         .release = i915_error_state_release,
1085 };
1086
1087 static int
1088 i915_next_seqno_get(void *data, u64 *val)
1089 {
1090         struct drm_device *dev = data;
1091         struct drm_i915_private *dev_priv = dev->dev_private;
1092         int ret;
1093
1094         ret = mutex_lock_interruptible(&dev->struct_mutex);
1095         if (ret)
1096                 return ret;
1097
1098         *val = dev_priv->next_seqno;
1099         mutex_unlock(&dev->struct_mutex);
1100
1101         return 0;
1102 }
1103
1104 static int
1105 i915_next_seqno_set(void *data, u64 val)
1106 {
1107         struct drm_device *dev = data;
1108         int ret;
1109
1110         ret = mutex_lock_interruptible(&dev->struct_mutex);
1111         if (ret)
1112                 return ret;
1113
1114         ret = i915_gem_set_seqno(dev, val);
1115         mutex_unlock(&dev->struct_mutex);
1116
1117         return ret;
1118 }
1119
1120 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1121                         i915_next_seqno_get, i915_next_seqno_set,
1122                         "0x%llx\n");
1123
1124 static int i915_frequency_info(struct seq_file *m, void *unused)
1125 {
1126         struct drm_info_node *node = m->private;
1127         struct drm_device *dev = node->minor->dev;
1128         struct drm_i915_private *dev_priv = dev->dev_private;
1129         int ret = 0;
1130
1131         intel_runtime_pm_get(dev_priv);
1132
1133         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1134
1135         if (IS_GEN5(dev)) {
1136                 u16 rgvswctl = I915_READ16(MEMSWCTL);
1137                 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1138
1139                 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1140                 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1141                 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1142                            MEMSTAT_VID_SHIFT);
1143                 seq_printf(m, "Current P-state: %d\n",
1144                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1145         } else if (IS_GEN6(dev) || (IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) ||
1146                    IS_BROADWELL(dev) || IS_GEN9(dev)) {
1147                 u32 rp_state_limits;
1148                 u32 gt_perf_status;
1149                 u32 rp_state_cap;
1150                 u32 rpmodectl, rpinclimit, rpdeclimit;
1151                 u32 rpstat, cagf, reqf;
1152                 u32 rpupei, rpcurup, rpprevup;
1153                 u32 rpdownei, rpcurdown, rpprevdown;
1154                 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1155                 int max_freq;
1156
1157                 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1158                 if (IS_BROXTON(dev)) {
1159                         rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1160                         gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1161                 } else {
1162                         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1163                         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1164                 }
1165
1166                 /* RPSTAT1 is in the GT power well */
1167                 ret = mutex_lock_interruptible(&dev->struct_mutex);
1168                 if (ret)
1169                         goto out;
1170
1171                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1172
1173                 reqf = I915_READ(GEN6_RPNSWREQ);
1174                 if (IS_GEN9(dev))
1175                         reqf >>= 23;
1176                 else {
1177                         reqf &= ~GEN6_TURBO_DISABLE;
1178                         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1179                                 reqf >>= 24;
1180                         else
1181                                 reqf >>= 25;
1182                 }
1183                 reqf = intel_gpu_freq(dev_priv, reqf);
1184
1185                 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1186                 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1187                 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1188
1189                 rpstat = I915_READ(GEN6_RPSTAT1);
1190                 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
1191                 rpcurup = I915_READ(GEN6_RP_CUR_UP);
1192                 rpprevup = I915_READ(GEN6_RP_PREV_UP);
1193                 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
1194                 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
1195                 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
1196                 if (IS_GEN9(dev))
1197                         cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1198                 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1199                         cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1200                 else
1201                         cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1202                 cagf = intel_gpu_freq(dev_priv, cagf);
1203
1204                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1205                 mutex_unlock(&dev->struct_mutex);
1206
1207                 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1208                         pm_ier = I915_READ(GEN6_PMIER);
1209                         pm_imr = I915_READ(GEN6_PMIMR);
1210                         pm_isr = I915_READ(GEN6_PMISR);
1211                         pm_iir = I915_READ(GEN6_PMIIR);
1212                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1213                 } else {
1214                         pm_ier = I915_READ(GEN8_GT_IER(2));
1215                         pm_imr = I915_READ(GEN8_GT_IMR(2));
1216                         pm_isr = I915_READ(GEN8_GT_ISR(2));
1217                         pm_iir = I915_READ(GEN8_GT_IIR(2));
1218                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1219                 }
1220                 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1221                            pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1222                 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1223                 seq_printf(m, "Render p-state ratio: %d\n",
1224                            (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
1225                 seq_printf(m, "Render p-state VID: %d\n",
1226                            gt_perf_status & 0xff);
1227                 seq_printf(m, "Render p-state limit: %d\n",
1228                            rp_state_limits & 0xff);
1229                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1230                 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1231                 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1232                 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1233                 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1234                 seq_printf(m, "CAGF: %dMHz\n", cagf);
1235                 seq_printf(m, "RP CUR UP EI: %dus\n", rpupei &
1236                            GEN6_CURICONT_MASK);
1237                 seq_printf(m, "RP CUR UP: %dus\n", rpcurup &
1238                            GEN6_CURBSYTAVG_MASK);
1239                 seq_printf(m, "RP PREV UP: %dus\n", rpprevup &
1240                            GEN6_CURBSYTAVG_MASK);
1241                 seq_printf(m, "Up threshold: %d%%\n",
1242                            dev_priv->rps.up_threshold);
1243
1244                 seq_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
1245                            GEN6_CURIAVG_MASK);
1246                 seq_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
1247                            GEN6_CURBSYTAVG_MASK);
1248                 seq_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
1249                            GEN6_CURBSYTAVG_MASK);
1250                 seq_printf(m, "Down threshold: %d%%\n",
1251                            dev_priv->rps.down_threshold);
1252
1253                 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 :
1254                             rp_state_cap >> 16) & 0xff;
1255                 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1256                              GEN9_FREQ_SCALER : 1);
1257                 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1258                            intel_gpu_freq(dev_priv, max_freq));
1259
1260                 max_freq = (rp_state_cap & 0xff00) >> 8;
1261                 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1262                              GEN9_FREQ_SCALER : 1);
1263                 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1264                            intel_gpu_freq(dev_priv, max_freq));
1265
1266                 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 :
1267                             rp_state_cap >> 0) & 0xff;
1268                 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1269                              GEN9_FREQ_SCALER : 1);
1270                 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1271                            intel_gpu_freq(dev_priv, max_freq));
1272                 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1273                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1274
1275                 seq_printf(m, "Current freq: %d MHz\n",
1276                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1277                 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1278                 seq_printf(m, "Idle freq: %d MHz\n",
1279                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1280                 seq_printf(m, "Min freq: %d MHz\n",
1281                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1282                 seq_printf(m, "Max freq: %d MHz\n",
1283                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1284                 seq_printf(m,
1285                            "efficient (RPe) frequency: %d MHz\n",
1286                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1287         } else if (IS_VALLEYVIEW(dev)) {
1288                 u32 freq_sts;
1289
1290                 mutex_lock(&dev_priv->rps.hw_lock);
1291                 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1292                 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1293                 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1294
1295                 seq_printf(m, "actual GPU freq: %d MHz\n",
1296                            intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1297
1298                 seq_printf(m, "current GPU freq: %d MHz\n",
1299                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1300
1301                 seq_printf(m, "max GPU freq: %d MHz\n",
1302                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1303
1304                 seq_printf(m, "min GPU freq: %d MHz\n",
1305                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1306
1307                 seq_printf(m, "idle GPU freq: %d MHz\n",
1308                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1309
1310                 seq_printf(m,
1311                            "efficient (RPe) frequency: %d MHz\n",
1312                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1313                 mutex_unlock(&dev_priv->rps.hw_lock);
1314         } else {
1315                 seq_puts(m, "no P-state info available\n");
1316         }
1317
1318         seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
1319         seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1320         seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1321
1322 out:
1323         intel_runtime_pm_put(dev_priv);
1324         return ret;
1325 }
1326
1327 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1328 {
1329         struct drm_info_node *node = m->private;
1330         struct drm_device *dev = node->minor->dev;
1331         struct drm_i915_private *dev_priv = dev->dev_private;
1332         struct intel_engine_cs *ring;
1333         u64 acthd[I915_NUM_RINGS];
1334         u32 seqno[I915_NUM_RINGS];
1335         int i;
1336
1337         if (!i915.enable_hangcheck) {
1338                 seq_printf(m, "Hangcheck disabled\n");
1339                 return 0;
1340         }
1341
1342         intel_runtime_pm_get(dev_priv);
1343
1344         for_each_ring(ring, dev_priv, i) {
1345                 seqno[i] = ring->get_seqno(ring, false);
1346                 acthd[i] = intel_ring_get_active_head(ring);
1347         }
1348
1349         intel_runtime_pm_put(dev_priv);
1350
1351         if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1352                 seq_printf(m, "Hangcheck active, fires in %dms\n",
1353                            jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1354                                             jiffies));
1355         } else
1356                 seq_printf(m, "Hangcheck inactive\n");
1357
1358         for_each_ring(ring, dev_priv, i) {
1359                 seq_printf(m, "%s:\n", ring->name);
1360                 seq_printf(m, "\tseqno = %x [current %x]\n",
1361                            ring->hangcheck.seqno, seqno[i]);
1362                 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1363                            (long long)ring->hangcheck.acthd,
1364                            (long long)acthd[i]);
1365                 seq_printf(m, "\tmax ACTHD = 0x%08llx\n",
1366                            (long long)ring->hangcheck.max_acthd);
1367                 seq_printf(m, "\tscore = %d\n", ring->hangcheck.score);
1368                 seq_printf(m, "\taction = %d\n", ring->hangcheck.action);
1369         }
1370
1371         return 0;
1372 }
1373
1374 static int ironlake_drpc_info(struct seq_file *m)
1375 {
1376         struct drm_info_node *node = m->private;
1377         struct drm_device *dev = node->minor->dev;
1378         struct drm_i915_private *dev_priv = dev->dev_private;
1379         u32 rgvmodectl, rstdbyctl;
1380         u16 crstandvid;
1381         int ret;
1382
1383         ret = mutex_lock_interruptible(&dev->struct_mutex);
1384         if (ret)
1385                 return ret;
1386         intel_runtime_pm_get(dev_priv);
1387
1388         rgvmodectl = I915_READ(MEMMODECTL);
1389         rstdbyctl = I915_READ(RSTDBYCTL);
1390         crstandvid = I915_READ16(CRSTANDVID);
1391
1392         intel_runtime_pm_put(dev_priv);
1393         mutex_unlock(&dev->struct_mutex);
1394
1395         seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1396         seq_printf(m, "Boost freq: %d\n",
1397                    (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1398                    MEMMODE_BOOST_FREQ_SHIFT);
1399         seq_printf(m, "HW control enabled: %s\n",
1400                    yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1401         seq_printf(m, "SW control enabled: %s\n",
1402                    yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1403         seq_printf(m, "Gated voltage change: %s\n",
1404                    yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1405         seq_printf(m, "Starting frequency: P%d\n",
1406                    (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1407         seq_printf(m, "Max P-state: P%d\n",
1408                    (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1409         seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1410         seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1411         seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1412         seq_printf(m, "Render standby enabled: %s\n",
1413                    yesno(!(rstdbyctl & RCX_SW_EXIT)));
1414         seq_puts(m, "Current RS state: ");
1415         switch (rstdbyctl & RSX_STATUS_MASK) {
1416         case RSX_STATUS_ON:
1417                 seq_puts(m, "on\n");
1418                 break;
1419         case RSX_STATUS_RC1:
1420                 seq_puts(m, "RC1\n");
1421                 break;
1422         case RSX_STATUS_RC1E:
1423                 seq_puts(m, "RC1E\n");
1424                 break;
1425         case RSX_STATUS_RS1:
1426                 seq_puts(m, "RS1\n");
1427                 break;
1428         case RSX_STATUS_RS2:
1429                 seq_puts(m, "RS2 (RC6)\n");
1430                 break;
1431         case RSX_STATUS_RS3:
1432                 seq_puts(m, "RC3 (RC6+)\n");
1433                 break;
1434         default:
1435                 seq_puts(m, "unknown\n");
1436                 break;
1437         }
1438
1439         return 0;
1440 }
1441
1442 static int i915_forcewake_domains(struct seq_file *m, void *data)
1443 {
1444         struct drm_info_node *node = m->private;
1445         struct drm_device *dev = node->minor->dev;
1446         struct drm_i915_private *dev_priv = dev->dev_private;
1447         struct intel_uncore_forcewake_domain *fw_domain;
1448         int i;
1449
1450         spin_lock_irq(&dev_priv->uncore.lock);
1451         for_each_fw_domain(fw_domain, dev_priv, i) {
1452                 seq_printf(m, "%s.wake_count = %u\n",
1453                            intel_uncore_forcewake_domain_to_str(i),
1454                            fw_domain->wake_count);
1455         }
1456         spin_unlock_irq(&dev_priv->uncore.lock);
1457
1458         return 0;
1459 }
1460
1461 static int vlv_drpc_info(struct seq_file *m)
1462 {
1463         struct drm_info_node *node = m->private;
1464         struct drm_device *dev = node->minor->dev;
1465         struct drm_i915_private *dev_priv = dev->dev_private;
1466         u32 rpmodectl1, rcctl1, pw_status;
1467
1468         intel_runtime_pm_get(dev_priv);
1469
1470         pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1471         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1472         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1473
1474         intel_runtime_pm_put(dev_priv);
1475
1476         seq_printf(m, "Video Turbo Mode: %s\n",
1477                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1478         seq_printf(m, "Turbo enabled: %s\n",
1479                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1480         seq_printf(m, "HW control enabled: %s\n",
1481                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1482         seq_printf(m, "SW control enabled: %s\n",
1483                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1484                           GEN6_RP_MEDIA_SW_MODE));
1485         seq_printf(m, "RC6 Enabled: %s\n",
1486                    yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1487                                         GEN6_RC_CTL_EI_MODE(1))));
1488         seq_printf(m, "Render Power Well: %s\n",
1489                    (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1490         seq_printf(m, "Media Power Well: %s\n",
1491                    (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1492
1493         seq_printf(m, "Render RC6 residency since boot: %u\n",
1494                    I915_READ(VLV_GT_RENDER_RC6));
1495         seq_printf(m, "Media RC6 residency since boot: %u\n",
1496                    I915_READ(VLV_GT_MEDIA_RC6));
1497
1498         return i915_forcewake_domains(m, NULL);
1499 }
1500
1501 static int gen6_drpc_info(struct seq_file *m)
1502 {
1503         struct drm_info_node *node = m->private;
1504         struct drm_device *dev = node->minor->dev;
1505         struct drm_i915_private *dev_priv = dev->dev_private;
1506         u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1507         unsigned forcewake_count;
1508         int count = 0, ret;
1509
1510         ret = mutex_lock_interruptible(&dev->struct_mutex);
1511         if (ret)
1512                 return ret;
1513         intel_runtime_pm_get(dev_priv);
1514
1515         spin_lock_irq(&dev_priv->uncore.lock);
1516         forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1517         spin_unlock_irq(&dev_priv->uncore.lock);
1518
1519         if (forcewake_count) {
1520                 seq_puts(m, "RC information inaccurate because somebody "
1521                             "holds a forcewake reference \n");
1522         } else {
1523                 /* NB: we cannot use forcewake, else we read the wrong values */
1524                 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1525                         udelay(10);
1526                 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1527         }
1528
1529         gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1530         trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1531
1532         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1533         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1534         mutex_unlock(&dev->struct_mutex);
1535         mutex_lock(&dev_priv->rps.hw_lock);
1536         sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1537         mutex_unlock(&dev_priv->rps.hw_lock);
1538
1539         intel_runtime_pm_put(dev_priv);
1540
1541         seq_printf(m, "Video Turbo Mode: %s\n",
1542                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1543         seq_printf(m, "HW control enabled: %s\n",
1544                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1545         seq_printf(m, "SW control enabled: %s\n",
1546                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1547                           GEN6_RP_MEDIA_SW_MODE));
1548         seq_printf(m, "RC1e Enabled: %s\n",
1549                    yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1550         seq_printf(m, "RC6 Enabled: %s\n",
1551                    yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1552         seq_printf(m, "Deep RC6 Enabled: %s\n",
1553                    yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1554         seq_printf(m, "Deepest RC6 Enabled: %s\n",
1555                    yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1556         seq_puts(m, "Current RC state: ");
1557         switch (gt_core_status & GEN6_RCn_MASK) {
1558         case GEN6_RC0:
1559                 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1560                         seq_puts(m, "Core Power Down\n");
1561                 else
1562                         seq_puts(m, "on\n");
1563                 break;
1564         case GEN6_RC3:
1565                 seq_puts(m, "RC3\n");
1566                 break;
1567         case GEN6_RC6:
1568                 seq_puts(m, "RC6\n");
1569                 break;
1570         case GEN6_RC7:
1571                 seq_puts(m, "RC7\n");
1572                 break;
1573         default:
1574                 seq_puts(m, "Unknown\n");
1575                 break;
1576         }
1577
1578         seq_printf(m, "Core Power Down: %s\n",
1579                    yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1580
1581         /* Not exactly sure what this is */
1582         seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1583                    I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1584         seq_printf(m, "RC6 residency since boot: %u\n",
1585                    I915_READ(GEN6_GT_GFX_RC6));
1586         seq_printf(m, "RC6+ residency since boot: %u\n",
1587                    I915_READ(GEN6_GT_GFX_RC6p));
1588         seq_printf(m, "RC6++ residency since boot: %u\n",
1589                    I915_READ(GEN6_GT_GFX_RC6pp));
1590
1591         seq_printf(m, "RC6   voltage: %dmV\n",
1592                    GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1593         seq_printf(m, "RC6+  voltage: %dmV\n",
1594                    GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1595         seq_printf(m, "RC6++ voltage: %dmV\n",
1596                    GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1597         return 0;
1598 }
1599
1600 static int i915_drpc_info(struct seq_file *m, void *unused)
1601 {
1602         struct drm_info_node *node = m->private;
1603         struct drm_device *dev = node->minor->dev;
1604
1605         if (IS_VALLEYVIEW(dev))
1606                 return vlv_drpc_info(m);
1607         else if (INTEL_INFO(dev)->gen >= 6)
1608                 return gen6_drpc_info(m);
1609         else
1610                 return ironlake_drpc_info(m);
1611 }
1612
1613 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1614 {
1615         struct drm_info_node *node = m->private;
1616         struct drm_device *dev = node->minor->dev;
1617         struct drm_i915_private *dev_priv = dev->dev_private;
1618
1619         seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1620                    dev_priv->fb_tracking.busy_bits);
1621
1622         seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1623                    dev_priv->fb_tracking.flip_bits);
1624
1625         return 0;
1626 }
1627
1628 static int i915_fbc_status(struct seq_file *m, void *unused)
1629 {
1630         struct drm_info_node *node = m->private;
1631         struct drm_device *dev = node->minor->dev;
1632         struct drm_i915_private *dev_priv = dev->dev_private;
1633
1634         if (!HAS_FBC(dev)) {
1635                 seq_puts(m, "FBC unsupported on this chipset\n");
1636                 return 0;
1637         }
1638
1639         intel_runtime_pm_get(dev_priv);
1640         mutex_lock(&dev_priv->fbc.lock);
1641
1642         if (intel_fbc_enabled(dev_priv))
1643                 seq_puts(m, "FBC enabled\n");
1644         else
1645                 seq_printf(m, "FBC disabled: %s\n",
1646                            dev_priv->fbc.no_fbc_reason);
1647
1648         if (INTEL_INFO(dev_priv)->gen >= 7)
1649                 seq_printf(m, "Compressing: %s\n",
1650                            yesno(I915_READ(FBC_STATUS2) &
1651                                  FBC_COMPRESSION_MASK));
1652
1653         mutex_unlock(&dev_priv->fbc.lock);
1654         intel_runtime_pm_put(dev_priv);
1655
1656         return 0;
1657 }
1658
1659 static int i915_fbc_fc_get(void *data, u64 *val)
1660 {
1661         struct drm_device *dev = data;
1662         struct drm_i915_private *dev_priv = dev->dev_private;
1663
1664         if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1665                 return -ENODEV;
1666
1667         *val = dev_priv->fbc.false_color;
1668
1669         return 0;
1670 }
1671
1672 static int i915_fbc_fc_set(void *data, u64 val)
1673 {
1674         struct drm_device *dev = data;
1675         struct drm_i915_private *dev_priv = dev->dev_private;
1676         u32 reg;
1677
1678         if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1679                 return -ENODEV;
1680
1681         mutex_lock(&dev_priv->fbc.lock);
1682
1683         reg = I915_READ(ILK_DPFC_CONTROL);
1684         dev_priv->fbc.false_color = val;
1685
1686         I915_WRITE(ILK_DPFC_CONTROL, val ?
1687                    (reg | FBC_CTL_FALSE_COLOR) :
1688                    (reg & ~FBC_CTL_FALSE_COLOR));
1689
1690         mutex_unlock(&dev_priv->fbc.lock);
1691         return 0;
1692 }
1693
1694 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1695                         i915_fbc_fc_get, i915_fbc_fc_set,
1696                         "%llu\n");
1697
1698 static int i915_ips_status(struct seq_file *m, void *unused)
1699 {
1700         struct drm_info_node *node = m->private;
1701         struct drm_device *dev = node->minor->dev;
1702         struct drm_i915_private *dev_priv = dev->dev_private;
1703
1704         if (!HAS_IPS(dev)) {
1705                 seq_puts(m, "not supported\n");
1706                 return 0;
1707         }
1708
1709         intel_runtime_pm_get(dev_priv);
1710
1711         seq_printf(m, "Enabled by kernel parameter: %s\n",
1712                    yesno(i915.enable_ips));
1713
1714         if (INTEL_INFO(dev)->gen >= 8) {
1715                 seq_puts(m, "Currently: unknown\n");
1716         } else {
1717                 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1718                         seq_puts(m, "Currently: enabled\n");
1719                 else
1720                         seq_puts(m, "Currently: disabled\n");
1721         }
1722
1723         intel_runtime_pm_put(dev_priv);
1724
1725         return 0;
1726 }
1727
1728 static int i915_sr_status(struct seq_file *m, void *unused)
1729 {
1730         struct drm_info_node *node = m->private;
1731         struct drm_device *dev = node->minor->dev;
1732         struct drm_i915_private *dev_priv = dev->dev_private;
1733         bool sr_enabled = false;
1734
1735         intel_runtime_pm_get(dev_priv);
1736
1737         if (HAS_PCH_SPLIT(dev))
1738                 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1739         else if (IS_CRESTLINE(dev) || IS_G4X(dev) ||
1740                  IS_I945G(dev) || IS_I945GM(dev))
1741                 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1742         else if (IS_I915GM(dev))
1743                 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1744         else if (IS_PINEVIEW(dev))
1745                 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1746         else if (IS_VALLEYVIEW(dev))
1747                 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1748
1749         intel_runtime_pm_put(dev_priv);
1750
1751         seq_printf(m, "self-refresh: %s\n",
1752                    sr_enabled ? "enabled" : "disabled");
1753
1754         return 0;
1755 }
1756
1757 static int i915_emon_status(struct seq_file *m, void *unused)
1758 {
1759         struct drm_info_node *node = m->private;
1760         struct drm_device *dev = node->minor->dev;
1761         struct drm_i915_private *dev_priv = dev->dev_private;
1762         unsigned long temp, chipset, gfx;
1763         int ret;
1764
1765         if (!IS_GEN5(dev))
1766                 return -ENODEV;
1767
1768         ret = mutex_lock_interruptible(&dev->struct_mutex);
1769         if (ret)
1770                 return ret;
1771
1772         temp = i915_mch_val(dev_priv);
1773         chipset = i915_chipset_val(dev_priv);
1774         gfx = i915_gfx_val(dev_priv);
1775         mutex_unlock(&dev->struct_mutex);
1776
1777         seq_printf(m, "GMCH temp: %ld\n", temp);
1778         seq_printf(m, "Chipset power: %ld\n", chipset);
1779         seq_printf(m, "GFX power: %ld\n", gfx);
1780         seq_printf(m, "Total power: %ld\n", chipset + gfx);
1781
1782         return 0;
1783 }
1784
1785 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1786 {
1787         struct drm_info_node *node = m->private;
1788         struct drm_device *dev = node->minor->dev;
1789         struct drm_i915_private *dev_priv = dev->dev_private;
1790         int ret = 0;
1791         int gpu_freq, ia_freq;
1792         unsigned int max_gpu_freq, min_gpu_freq;
1793
1794         if (!HAS_CORE_RING_FREQ(dev)) {
1795                 seq_puts(m, "unsupported on this chipset\n");
1796                 return 0;
1797         }
1798
1799         intel_runtime_pm_get(dev_priv);
1800
1801         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
1802
1803         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1804         if (ret)
1805                 goto out;
1806
1807         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
1808                 /* Convert GT frequency to 50 HZ units */
1809                 min_gpu_freq =
1810                         dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1811                 max_gpu_freq =
1812                         dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1813         } else {
1814                 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1815                 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1816         }
1817
1818         seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1819
1820         for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1821                 ia_freq = gpu_freq;
1822                 sandybridge_pcode_read(dev_priv,
1823                                        GEN6_PCODE_READ_MIN_FREQ_TABLE,
1824                                        &ia_freq);
1825                 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1826                            intel_gpu_freq(dev_priv, (gpu_freq *
1827                                 (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1828                                  GEN9_FREQ_SCALER : 1))),
1829                            ((ia_freq >> 0) & 0xff) * 100,
1830                            ((ia_freq >> 8) & 0xff) * 100);
1831         }
1832
1833         mutex_unlock(&dev_priv->rps.hw_lock);
1834
1835 out:
1836         intel_runtime_pm_put(dev_priv);
1837         return ret;
1838 }
1839
1840 static int i915_opregion(struct seq_file *m, void *unused)
1841 {
1842         struct drm_info_node *node = m->private;
1843         struct drm_device *dev = node->minor->dev;
1844         struct drm_i915_private *dev_priv = dev->dev_private;
1845         struct intel_opregion *opregion = &dev_priv->opregion;
1846         void *data = kmalloc(OPREGION_SIZE, GFP_KERNEL);
1847         int ret;
1848
1849         if (data == NULL)
1850                 return -ENOMEM;
1851
1852         ret = mutex_lock_interruptible(&dev->struct_mutex);
1853         if (ret)
1854                 goto out;
1855
1856         if (opregion->header) {
1857                 memcpy(data, opregion->header, OPREGION_SIZE);
1858                 seq_write(m, data, OPREGION_SIZE);
1859         }
1860
1861         mutex_unlock(&dev->struct_mutex);
1862
1863 out:
1864         kfree(data);
1865         return 0;
1866 }
1867
1868 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1869 {
1870         struct drm_info_node *node = m->private;
1871         struct drm_device *dev = node->minor->dev;
1872         struct intel_framebuffer *fbdev_fb = NULL;
1873         struct drm_framebuffer *drm_fb;
1874
1875 #ifdef CONFIG_DRM_FBDEV_EMULATION
1876        if (to_i915(dev)->fbdev) {
1877                fbdev_fb = to_intel_framebuffer(to_i915(dev)->fbdev->helper.fb);
1878
1879                seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1880                          fbdev_fb->base.width,
1881                          fbdev_fb->base.height,
1882                          fbdev_fb->base.depth,
1883                          fbdev_fb->base.bits_per_pixel,
1884                          fbdev_fb->base.modifier[0],
1885                          atomic_read(&fbdev_fb->base.refcount.refcount));
1886                describe_obj(m, fbdev_fb->obj);
1887                seq_putc(m, '\n');
1888        }
1889 #endif
1890
1891         mutex_lock(&dev->mode_config.fb_lock);
1892         drm_for_each_fb(drm_fb, dev) {
1893                 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
1894                 if (fb == fbdev_fb)
1895                         continue;
1896
1897                 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1898                            fb->base.width,
1899                            fb->base.height,
1900                            fb->base.depth,
1901                            fb->base.bits_per_pixel,
1902                            fb->base.modifier[0],
1903                            atomic_read(&fb->base.refcount.refcount));
1904                 describe_obj(m, fb->obj);
1905                 seq_putc(m, '\n');
1906         }
1907         mutex_unlock(&dev->mode_config.fb_lock);
1908
1909         return 0;
1910 }
1911
1912 static void describe_ctx_ringbuf(struct seq_file *m,
1913                                  struct intel_ringbuffer *ringbuf)
1914 {
1915         seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1916                    ringbuf->space, ringbuf->head, ringbuf->tail,
1917                    ringbuf->last_retired_head);
1918 }
1919
1920 static int i915_context_status(struct seq_file *m, void *unused)
1921 {
1922         struct drm_info_node *node = m->private;
1923         struct drm_device *dev = node->minor->dev;
1924         struct drm_i915_private *dev_priv = dev->dev_private;
1925         struct intel_engine_cs *ring;
1926         struct intel_context *ctx;
1927         int ret, i;
1928
1929         ret = mutex_lock_interruptible(&dev->struct_mutex);
1930         if (ret)
1931                 return ret;
1932
1933         list_for_each_entry(ctx, &dev_priv->context_list, link) {
1934                 if (!i915.enable_execlists &&
1935                     ctx->legacy_hw_ctx.rcs_state == NULL)
1936                         continue;
1937
1938                 seq_puts(m, "HW context ");
1939                 describe_ctx(m, ctx);
1940                 for_each_ring(ring, dev_priv, i) {
1941                         if (ring->default_context == ctx)
1942                                 seq_printf(m, "(default context %s) ",
1943                                            ring->name);
1944                 }
1945
1946                 if (i915.enable_execlists) {
1947                         seq_putc(m, '\n');
1948                         for_each_ring(ring, dev_priv, i) {
1949                                 struct drm_i915_gem_object *ctx_obj =
1950                                         ctx->engine[i].state;
1951                                 struct intel_ringbuffer *ringbuf =
1952                                         ctx->engine[i].ringbuf;
1953
1954                                 seq_printf(m, "%s: ", ring->name);
1955                                 if (ctx_obj)
1956                                         describe_obj(m, ctx_obj);
1957                                 if (ringbuf)
1958                                         describe_ctx_ringbuf(m, ringbuf);
1959                                 seq_putc(m, '\n');
1960                         }
1961                 } else {
1962                         describe_obj(m, ctx->legacy_hw_ctx.rcs_state);
1963                 }
1964
1965                 seq_putc(m, '\n');
1966         }
1967
1968         mutex_unlock(&dev->struct_mutex);
1969
1970         return 0;
1971 }
1972
1973 static void i915_dump_lrc_obj(struct seq_file *m,
1974                               struct intel_engine_cs *ring,
1975                               struct drm_i915_gem_object *ctx_obj)
1976 {
1977         struct page *page;
1978         uint32_t *reg_state;
1979         int j;
1980         unsigned long ggtt_offset = 0;
1981
1982         if (ctx_obj == NULL) {
1983                 seq_printf(m, "Context on %s with no gem object\n",
1984                            ring->name);
1985                 return;
1986         }
1987
1988         seq_printf(m, "CONTEXT: %s %u\n", ring->name,
1989                    intel_execlists_ctx_id(ctx_obj));
1990
1991         if (!i915_gem_obj_ggtt_bound(ctx_obj))
1992                 seq_puts(m, "\tNot bound in GGTT\n");
1993         else
1994                 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
1995
1996         if (i915_gem_object_get_pages(ctx_obj)) {
1997                 seq_puts(m, "\tFailed to get pages for context object\n");
1998                 return;
1999         }
2000
2001         page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
2002         if (!WARN_ON(page == NULL)) {
2003                 reg_state = kmap_atomic(page);
2004
2005                 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2006                         seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2007                                    ggtt_offset + 4096 + (j * 4),
2008                                    reg_state[j], reg_state[j + 1],
2009                                    reg_state[j + 2], reg_state[j + 3]);
2010                 }
2011                 kunmap_atomic(reg_state);
2012         }
2013
2014         seq_putc(m, '\n');
2015 }
2016
2017 static int i915_dump_lrc(struct seq_file *m, void *unused)
2018 {
2019         struct drm_info_node *node = (struct drm_info_node *) m->private;
2020         struct drm_device *dev = node->minor->dev;
2021         struct drm_i915_private *dev_priv = dev->dev_private;
2022         struct intel_engine_cs *ring;
2023         struct intel_context *ctx;
2024         int ret, i;
2025
2026         if (!i915.enable_execlists) {
2027                 seq_printf(m, "Logical Ring Contexts are disabled\n");
2028                 return 0;
2029         }
2030
2031         ret = mutex_lock_interruptible(&dev->struct_mutex);
2032         if (ret)
2033                 return ret;
2034
2035         list_for_each_entry(ctx, &dev_priv->context_list, link) {
2036                 for_each_ring(ring, dev_priv, i) {
2037                         if (ring->default_context != ctx)
2038                                 i915_dump_lrc_obj(m, ring,
2039                                                   ctx->engine[i].state);
2040                 }
2041         }
2042
2043         mutex_unlock(&dev->struct_mutex);
2044
2045         return 0;
2046 }
2047
2048 static int i915_execlists(struct seq_file *m, void *data)
2049 {
2050         struct drm_info_node *node = (struct drm_info_node *)m->private;
2051         struct drm_device *dev = node->minor->dev;
2052         struct drm_i915_private *dev_priv = dev->dev_private;
2053         struct intel_engine_cs *ring;
2054         u32 status_pointer;
2055         u8 read_pointer;
2056         u8 write_pointer;
2057         u32 status;
2058         u32 ctx_id;
2059         struct list_head *cursor;
2060         int ring_id, i;
2061         int ret;
2062
2063         if (!i915.enable_execlists) {
2064                 seq_puts(m, "Logical Ring Contexts are disabled\n");
2065                 return 0;
2066         }
2067
2068         ret = mutex_lock_interruptible(&dev->struct_mutex);
2069         if (ret)
2070                 return ret;
2071
2072         intel_runtime_pm_get(dev_priv);
2073
2074         for_each_ring(ring, dev_priv, ring_id) {
2075                 struct drm_i915_gem_request *head_req = NULL;
2076                 int count = 0;
2077                 unsigned long flags;
2078
2079                 seq_printf(m, "%s\n", ring->name);
2080
2081                 status = I915_READ(RING_EXECLIST_STATUS_LO(ring));
2082                 ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(ring));
2083                 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2084                            status, ctx_id);
2085
2086                 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring));
2087                 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2088
2089                 read_pointer = ring->next_context_status_buffer;
2090                 write_pointer = status_pointer & 0x07;
2091                 if (read_pointer > write_pointer)
2092                         write_pointer += 6;
2093                 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2094                            read_pointer, write_pointer);
2095
2096                 for (i = 0; i < 6; i++) {
2097                         status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(ring, i));
2098                         ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(ring, i));
2099
2100                         seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2101                                    i, status, ctx_id);
2102                 }
2103
2104                 spin_lock_irqsave(&ring->execlist_lock, flags);
2105                 list_for_each(cursor, &ring->execlist_queue)
2106                         count++;
2107                 head_req = list_first_entry_or_null(&ring->execlist_queue,
2108                                 struct drm_i915_gem_request, execlist_link);
2109                 spin_unlock_irqrestore(&ring->execlist_lock, flags);
2110
2111                 seq_printf(m, "\t%d requests in queue\n", count);
2112                 if (head_req) {
2113                         struct drm_i915_gem_object *ctx_obj;
2114
2115                         ctx_obj = head_req->ctx->engine[ring_id].state;
2116                         seq_printf(m, "\tHead request id: %u\n",
2117                                    intel_execlists_ctx_id(ctx_obj));
2118                         seq_printf(m, "\tHead request tail: %u\n",
2119                                    head_req->tail);
2120                 }
2121
2122                 seq_putc(m, '\n');
2123         }
2124
2125         intel_runtime_pm_put(dev_priv);
2126         mutex_unlock(&dev->struct_mutex);
2127
2128         return 0;
2129 }
2130
2131 static const char *swizzle_string(unsigned swizzle)
2132 {
2133         switch (swizzle) {
2134         case I915_BIT_6_SWIZZLE_NONE:
2135                 return "none";
2136         case I915_BIT_6_SWIZZLE_9:
2137                 return "bit9";
2138         case I915_BIT_6_SWIZZLE_9_10:
2139                 return "bit9/bit10";
2140         case I915_BIT_6_SWIZZLE_9_11:
2141                 return "bit9/bit11";
2142         case I915_BIT_6_SWIZZLE_9_10_11:
2143                 return "bit9/bit10/bit11";
2144         case I915_BIT_6_SWIZZLE_9_17:
2145                 return "bit9/bit17";
2146         case I915_BIT_6_SWIZZLE_9_10_17:
2147                 return "bit9/bit10/bit17";
2148         case I915_BIT_6_SWIZZLE_UNKNOWN:
2149                 return "unknown";
2150         }
2151
2152         return "bug";
2153 }
2154
2155 static int i915_swizzle_info(struct seq_file *m, void *data)
2156 {
2157         struct drm_info_node *node = m->private;
2158         struct drm_device *dev = node->minor->dev;
2159         struct drm_i915_private *dev_priv = dev->dev_private;
2160         int ret;
2161
2162         ret = mutex_lock_interruptible(&dev->struct_mutex);
2163         if (ret)
2164                 return ret;
2165         intel_runtime_pm_get(dev_priv);
2166
2167         seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2168                    swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2169         seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2170                    swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2171
2172         if (IS_GEN3(dev) || IS_GEN4(dev)) {
2173                 seq_printf(m, "DDC = 0x%08x\n",
2174                            I915_READ(DCC));
2175                 seq_printf(m, "DDC2 = 0x%08x\n",
2176                            I915_READ(DCC2));
2177                 seq_printf(m, "C0DRB3 = 0x%04x\n",
2178                            I915_READ16(C0DRB3));
2179                 seq_printf(m, "C1DRB3 = 0x%04x\n",
2180                            I915_READ16(C1DRB3));
2181         } else if (INTEL_INFO(dev)->gen >= 6) {
2182                 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2183                            I915_READ(MAD_DIMM_C0));
2184                 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2185                            I915_READ(MAD_DIMM_C1));
2186                 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2187                            I915_READ(MAD_DIMM_C2));
2188                 seq_printf(m, "TILECTL = 0x%08x\n",
2189                            I915_READ(TILECTL));
2190                 if (INTEL_INFO(dev)->gen >= 8)
2191                         seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2192                                    I915_READ(GAMTARBMODE));
2193                 else
2194                         seq_printf(m, "ARB_MODE = 0x%08x\n",
2195                                    I915_READ(ARB_MODE));
2196                 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2197                            I915_READ(DISP_ARB_CTL));
2198         }
2199
2200         if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2201                 seq_puts(m, "L-shaped memory detected\n");
2202
2203         intel_runtime_pm_put(dev_priv);
2204         mutex_unlock(&dev->struct_mutex);
2205
2206         return 0;
2207 }
2208
2209 static int per_file_ctx(int id, void *ptr, void *data)
2210 {
2211         struct intel_context *ctx = ptr;
2212         struct seq_file *m = data;
2213         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2214
2215         if (!ppgtt) {
2216                 seq_printf(m, "  no ppgtt for context %d\n",
2217                            ctx->user_handle);
2218                 return 0;
2219         }
2220
2221         if (i915_gem_context_is_default(ctx))
2222                 seq_puts(m, "  default context:\n");
2223         else
2224                 seq_printf(m, "  context %d:\n", ctx->user_handle);
2225         ppgtt->debug_dump(ppgtt, m);
2226
2227         return 0;
2228 }
2229
2230 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2231 {
2232         struct drm_i915_private *dev_priv = dev->dev_private;
2233         struct intel_engine_cs *ring;
2234         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2235         int unused, i;
2236
2237         if (!ppgtt)
2238                 return;
2239
2240         for_each_ring(ring, dev_priv, unused) {
2241                 seq_printf(m, "%s\n", ring->name);
2242                 for (i = 0; i < 4; i++) {
2243                         u64 pdp = I915_READ(GEN8_RING_PDP_UDW(ring, i));
2244                         pdp <<= 32;
2245                         pdp |= I915_READ(GEN8_RING_PDP_LDW(ring, i));
2246                         seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2247                 }
2248         }
2249 }
2250
2251 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2252 {
2253         struct drm_i915_private *dev_priv = dev->dev_private;
2254         struct intel_engine_cs *ring;
2255         int i;
2256
2257         if (INTEL_INFO(dev)->gen == 6)
2258                 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2259
2260         for_each_ring(ring, dev_priv, i) {
2261                 seq_printf(m, "%s\n", ring->name);
2262                 if (INTEL_INFO(dev)->gen == 7)
2263                         seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
2264                 seq_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
2265                 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
2266                 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
2267         }
2268         if (dev_priv->mm.aliasing_ppgtt) {
2269                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2270
2271                 seq_puts(m, "aliasing PPGTT:\n");
2272                 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2273
2274                 ppgtt->debug_dump(ppgtt, m);
2275         }
2276
2277         seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2278 }
2279
2280 static int i915_ppgtt_info(struct seq_file *m, void *data)
2281 {
2282         struct drm_info_node *node = m->private;
2283         struct drm_device *dev = node->minor->dev;
2284         struct drm_i915_private *dev_priv = dev->dev_private;
2285         struct drm_file *file;
2286
2287         int ret = mutex_lock_interruptible(&dev->struct_mutex);
2288         if (ret)
2289                 return ret;
2290         intel_runtime_pm_get(dev_priv);
2291
2292         if (INTEL_INFO(dev)->gen >= 8)
2293                 gen8_ppgtt_info(m, dev);
2294         else if (INTEL_INFO(dev)->gen >= 6)
2295                 gen6_ppgtt_info(m, dev);
2296
2297         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2298                 struct drm_i915_file_private *file_priv = file->driver_priv;
2299                 struct task_struct *task;
2300
2301                 task = get_pid_task(file->pid, PIDTYPE_PID);
2302                 if (!task) {
2303                         ret = -ESRCH;
2304                         goto out_put;
2305                 }
2306                 seq_printf(m, "\nproc: %s\n", task->comm);
2307                 put_task_struct(task);
2308                 idr_for_each(&file_priv->context_idr, per_file_ctx,
2309                              (void *)(unsigned long)m);
2310         }
2311
2312 out_put:
2313         intel_runtime_pm_put(dev_priv);
2314         mutex_unlock(&dev->struct_mutex);
2315
2316         return ret;
2317 }
2318
2319 static int count_irq_waiters(struct drm_i915_private *i915)
2320 {
2321         struct intel_engine_cs *ring;
2322         int count = 0;
2323         int i;
2324
2325         for_each_ring(ring, i915, i)
2326                 count += ring->irq_refcount;
2327
2328         return count;
2329 }
2330
2331 static int i915_rps_boost_info(struct seq_file *m, void *data)
2332 {
2333         struct drm_info_node *node = m->private;
2334         struct drm_device *dev = node->minor->dev;
2335         struct drm_i915_private *dev_priv = dev->dev_private;
2336         struct drm_file *file;
2337
2338         seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2339         seq_printf(m, "GPU busy? %d\n", dev_priv->mm.busy);
2340         seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2341         seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2342                    intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2343                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2344                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2345                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2346                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2347         spin_lock(&dev_priv->rps.client_lock);
2348         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2349                 struct drm_i915_file_private *file_priv = file->driver_priv;
2350                 struct task_struct *task;
2351
2352                 rcu_read_lock();
2353                 task = pid_task(file->pid, PIDTYPE_PID);
2354                 seq_printf(m, "%s [%d]: %d boosts%s\n",
2355                            task ? task->comm : "<unknown>",
2356                            task ? task->pid : -1,
2357                            file_priv->rps.boosts,
2358                            list_empty(&file_priv->rps.link) ? "" : ", active");
2359                 rcu_read_unlock();
2360         }
2361         seq_printf(m, "Semaphore boosts: %d%s\n",
2362                    dev_priv->rps.semaphores.boosts,
2363                    list_empty(&dev_priv->rps.semaphores.link) ? "" : ", active");
2364         seq_printf(m, "MMIO flip boosts: %d%s\n",
2365                    dev_priv->rps.mmioflips.boosts,
2366                    list_empty(&dev_priv->rps.mmioflips.link) ? "" : ", active");
2367         seq_printf(m, "Kernel boosts: %d\n", dev_priv->rps.boosts);
2368         spin_unlock(&dev_priv->rps.client_lock);
2369
2370         return 0;
2371 }
2372
2373 static int i915_llc(struct seq_file *m, void *data)
2374 {
2375         struct drm_info_node *node = m->private;
2376         struct drm_device *dev = node->minor->dev;
2377         struct drm_i915_private *dev_priv = dev->dev_private;
2378
2379         /* Size calculation for LLC is a bit of a pain. Ignore for now. */
2380         seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2381         seq_printf(m, "eLLC: %zuMB\n", dev_priv->ellc_size);
2382
2383         return 0;
2384 }
2385
2386 static int i915_guc_load_status_info(struct seq_file *m, void *data)
2387 {
2388         struct drm_info_node *node = m->private;
2389         struct drm_i915_private *dev_priv = node->minor->dev->dev_private;
2390         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
2391         u32 tmp, i;
2392
2393         if (!HAS_GUC_UCODE(dev_priv->dev))
2394                 return 0;
2395
2396         seq_printf(m, "GuC firmware status:\n");
2397         seq_printf(m, "\tpath: %s\n",
2398                 guc_fw->guc_fw_path);
2399         seq_printf(m, "\tfetch: %s\n",
2400                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
2401         seq_printf(m, "\tload: %s\n",
2402                 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
2403         seq_printf(m, "\tversion wanted: %d.%d\n",
2404                 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2405         seq_printf(m, "\tversion found: %d.%d\n",
2406                 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
2407         seq_printf(m, "\theader: offset is %d; size = %d\n",
2408                 guc_fw->header_offset, guc_fw->header_size);
2409         seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2410                 guc_fw->ucode_offset, guc_fw->ucode_size);
2411         seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2412                 guc_fw->rsa_offset, guc_fw->rsa_size);
2413
2414         tmp = I915_READ(GUC_STATUS);
2415
2416         seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2417         seq_printf(m, "\tBootrom status = 0x%x\n",
2418                 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2419         seq_printf(m, "\tuKernel status = 0x%x\n",
2420                 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2421         seq_printf(m, "\tMIA Core status = 0x%x\n",
2422                 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2423         seq_puts(m, "\nScratch registers:\n");
2424         for (i = 0; i < 16; i++)
2425                 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2426
2427         return 0;
2428 }
2429
2430 static void i915_guc_client_info(struct seq_file *m,
2431                                  struct drm_i915_private *dev_priv,
2432                                  struct i915_guc_client *client)
2433 {
2434         struct intel_engine_cs *ring;
2435         uint64_t tot = 0;
2436         uint32_t i;
2437
2438         seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2439                 client->priority, client->ctx_index, client->proc_desc_offset);
2440         seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2441                 client->doorbell_id, client->doorbell_offset, client->cookie);
2442         seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2443                 client->wq_size, client->wq_offset, client->wq_tail);
2444
2445         seq_printf(m, "\tFailed to queue: %u\n", client->q_fail);
2446         seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2447         seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2448
2449         for_each_ring(ring, dev_priv, i) {
2450                 seq_printf(m, "\tSubmissions: %llu %s\n",
2451                                 client->submissions[i],
2452                                 ring->name);
2453                 tot += client->submissions[i];
2454         }
2455         seq_printf(m, "\tTotal: %llu\n", tot);
2456 }
2457
2458 static int i915_guc_info(struct seq_file *m, void *data)
2459 {
2460         struct drm_info_node *node = m->private;
2461         struct drm_device *dev = node->minor->dev;
2462         struct drm_i915_private *dev_priv = dev->dev_private;
2463         struct intel_guc guc;
2464         struct i915_guc_client client = {};
2465         struct intel_engine_cs *ring;
2466         enum intel_ring_id i;
2467         u64 total = 0;
2468
2469         if (!HAS_GUC_SCHED(dev_priv->dev))
2470                 return 0;
2471
2472         /* Take a local copy of the GuC data, so we can dump it at leisure */
2473         spin_lock(&dev_priv->guc.host2guc_lock);
2474         guc = dev_priv->guc;
2475         if (guc.execbuf_client) {
2476                 spin_lock(&guc.execbuf_client->wq_lock);
2477                 client = *guc.execbuf_client;
2478                 spin_unlock(&guc.execbuf_client->wq_lock);
2479         }
2480         spin_unlock(&dev_priv->guc.host2guc_lock);
2481
2482         seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
2483         seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
2484         seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
2485         seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
2486         seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
2487
2488         seq_printf(m, "\nGuC submissions:\n");
2489         for_each_ring(ring, dev_priv, i) {
2490                 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x %9d\n",
2491                         ring->name, guc.submissions[i],
2492                         guc.last_seqno[i], guc.last_seqno[i]);
2493                 total += guc.submissions[i];
2494         }
2495         seq_printf(m, "\t%s: %llu\n", "Total", total);
2496
2497         seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
2498         i915_guc_client_info(m, dev_priv, &client);
2499
2500         /* Add more as required ... */
2501
2502         return 0;
2503 }
2504
2505 static int i915_guc_log_dump(struct seq_file *m, void *data)
2506 {
2507         struct drm_info_node *node = m->private;
2508         struct drm_device *dev = node->minor->dev;
2509         struct drm_i915_private *dev_priv = dev->dev_private;
2510         struct drm_i915_gem_object *log_obj = dev_priv->guc.log_obj;
2511         u32 *log;
2512         int i = 0, pg;
2513
2514         if (!log_obj)
2515                 return 0;
2516
2517         for (pg = 0; pg < log_obj->base.size / PAGE_SIZE; pg++) {
2518                 log = kmap_atomic(i915_gem_object_get_page(log_obj, pg));
2519
2520                 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2521                         seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2522                                    *(log + i), *(log + i + 1),
2523                                    *(log + i + 2), *(log + i + 3));
2524
2525                 kunmap_atomic(log);
2526         }
2527
2528         seq_putc(m, '\n');
2529
2530         return 0;
2531 }
2532
2533 static int i915_edp_psr_status(struct seq_file *m, void *data)
2534 {
2535         struct drm_info_node *node = m->private;
2536         struct drm_device *dev = node->minor->dev;
2537         struct drm_i915_private *dev_priv = dev->dev_private;
2538         u32 psrperf = 0;
2539         u32 stat[3];
2540         enum pipe pipe;
2541         bool enabled = false;
2542
2543         if (!HAS_PSR(dev)) {
2544                 seq_puts(m, "PSR not supported\n");
2545                 return 0;
2546         }
2547
2548         intel_runtime_pm_get(dev_priv);
2549
2550         mutex_lock(&dev_priv->psr.lock);
2551         seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2552         seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2553         seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2554         seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2555         seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2556                    dev_priv->psr.busy_frontbuffer_bits);
2557         seq_printf(m, "Re-enable work scheduled: %s\n",
2558                    yesno(work_busy(&dev_priv->psr.work.work)));
2559
2560         if (HAS_DDI(dev))
2561                 enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2562         else {
2563                 for_each_pipe(dev_priv, pipe) {
2564                         stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2565                                 VLV_EDP_PSR_CURR_STATE_MASK;
2566                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2567                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2568                                 enabled = true;
2569                 }
2570         }
2571         seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2572
2573         if (!HAS_DDI(dev))
2574                 for_each_pipe(dev_priv, pipe) {
2575                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2576                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2577                                 seq_printf(m, " pipe %c", pipe_name(pipe));
2578                 }
2579         seq_puts(m, "\n");
2580
2581         /*
2582          * VLV/CHV PSR has no kind of performance counter
2583          * SKL+ Perf counter is reset to 0 everytime DC state is entered
2584          */
2585         if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2586                 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
2587                         EDP_PSR_PERF_CNT_MASK;
2588
2589                 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2590         }
2591         mutex_unlock(&dev_priv->psr.lock);
2592
2593         intel_runtime_pm_put(dev_priv);
2594         return 0;
2595 }
2596
2597 static int i915_sink_crc(struct seq_file *m, void *data)
2598 {
2599         struct drm_info_node *node = m->private;
2600         struct drm_device *dev = node->minor->dev;
2601         struct intel_encoder *encoder;
2602         struct intel_connector *connector;
2603         struct intel_dp *intel_dp = NULL;
2604         int ret;
2605         u8 crc[6];
2606
2607         drm_modeset_lock_all(dev);
2608         for_each_intel_connector(dev, connector) {
2609
2610                 if (connector->base.dpms != DRM_MODE_DPMS_ON)
2611                         continue;
2612
2613                 if (!connector->base.encoder)
2614                         continue;
2615
2616                 encoder = to_intel_encoder(connector->base.encoder);
2617                 if (encoder->type != INTEL_OUTPUT_EDP)
2618                         continue;
2619
2620                 intel_dp = enc_to_intel_dp(&encoder->base);
2621
2622                 ret = intel_dp_sink_crc(intel_dp, crc);
2623                 if (ret)
2624                         goto out;
2625
2626                 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2627                            crc[0], crc[1], crc[2],
2628                            crc[3], crc[4], crc[5]);
2629                 goto out;
2630         }
2631         ret = -ENODEV;
2632 out:
2633         drm_modeset_unlock_all(dev);
2634         return ret;
2635 }
2636
2637 static int i915_energy_uJ(struct seq_file *m, void *data)
2638 {
2639         struct drm_info_node *node = m->private;
2640         struct drm_device *dev = node->minor->dev;
2641         struct drm_i915_private *dev_priv = dev->dev_private;
2642         u64 power;
2643         u32 units;
2644
2645         if (INTEL_INFO(dev)->gen < 6)
2646                 return -ENODEV;
2647
2648         intel_runtime_pm_get(dev_priv);
2649
2650         rdmsrl(MSR_RAPL_POWER_UNIT, power);
2651         power = (power & 0x1f00) >> 8;
2652         units = 1000000 / (1 << power); /* convert to uJ */
2653         power = I915_READ(MCH_SECP_NRG_STTS);
2654         power *= units;
2655
2656         intel_runtime_pm_put(dev_priv);
2657
2658         seq_printf(m, "%llu", (long long unsigned)power);
2659
2660         return 0;
2661 }
2662
2663 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2664 {
2665         struct drm_info_node *node = m->private;
2666         struct drm_device *dev = node->minor->dev;
2667         struct drm_i915_private *dev_priv = dev->dev_private;
2668
2669         if (!HAS_RUNTIME_PM(dev)) {
2670                 seq_puts(m, "not supported\n");
2671                 return 0;
2672         }
2673
2674         seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->mm.busy));
2675         seq_printf(m, "IRQs disabled: %s\n",
2676                    yesno(!intel_irqs_enabled(dev_priv)));
2677 #ifdef CONFIG_PM
2678         seq_printf(m, "Usage count: %d\n",
2679                    atomic_read(&dev->dev->power.usage_count));
2680 #else
2681         seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2682 #endif
2683
2684         return 0;
2685 }
2686
2687 static int i915_power_domain_info(struct seq_file *m, void *unused)
2688 {
2689         struct drm_info_node *node = m->private;
2690         struct drm_device *dev = node->minor->dev;
2691         struct drm_i915_private *dev_priv = dev->dev_private;
2692         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2693         int i;
2694
2695         mutex_lock(&power_domains->lock);
2696
2697         seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2698         for (i = 0; i < power_domains->power_well_count; i++) {
2699                 struct i915_power_well *power_well;
2700                 enum intel_display_power_domain power_domain;
2701
2702                 power_well = &power_domains->power_wells[i];
2703                 seq_printf(m, "%-25s %d\n", power_well->name,
2704                            power_well->count);
2705
2706                 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2707                      power_domain++) {
2708                         if (!(BIT(power_domain) & power_well->domains))
2709                                 continue;
2710
2711                         seq_printf(m, "  %-23s %d\n",
2712                                  intel_display_power_domain_str(power_domain),
2713                                  power_domains->domain_use_count[power_domain]);
2714                 }
2715         }
2716
2717         mutex_unlock(&power_domains->lock);
2718
2719         return 0;
2720 }
2721
2722 static int i915_dmc_info(struct seq_file *m, void *unused)
2723 {
2724         struct drm_info_node *node = m->private;
2725         struct drm_device *dev = node->minor->dev;
2726         struct drm_i915_private *dev_priv = dev->dev_private;
2727         struct intel_csr *csr;
2728
2729         if (!HAS_CSR(dev)) {
2730                 seq_puts(m, "not supported\n");
2731                 return 0;
2732         }
2733
2734         csr = &dev_priv->csr;
2735
2736         intel_runtime_pm_get(dev_priv);
2737
2738         seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2739         seq_printf(m, "path: %s\n", csr->fw_path);
2740
2741         if (!csr->dmc_payload)
2742                 goto out;
2743
2744         seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2745                    CSR_VERSION_MINOR(csr->version));
2746
2747         if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) {
2748                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2749                            I915_READ(SKL_CSR_DC3_DC5_COUNT));
2750                 seq_printf(m, "DC5 -> DC6 count: %d\n",
2751                            I915_READ(SKL_CSR_DC5_DC6_COUNT));
2752         } else if (IS_BROXTON(dev) && csr->version >= CSR_VERSION(1, 4)) {
2753                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2754                            I915_READ(BXT_CSR_DC3_DC5_COUNT));
2755         }
2756
2757 out:
2758         seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2759         seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2760         seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2761
2762         intel_runtime_pm_put(dev_priv);
2763
2764         return 0;
2765 }
2766
2767 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2768                                  struct drm_display_mode *mode)
2769 {
2770         int i;
2771
2772         for (i = 0; i < tabs; i++)
2773                 seq_putc(m, '\t');
2774
2775         seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2776                    mode->base.id, mode->name,
2777                    mode->vrefresh, mode->clock,
2778                    mode->hdisplay, mode->hsync_start,
2779                    mode->hsync_end, mode->htotal,
2780                    mode->vdisplay, mode->vsync_start,
2781                    mode->vsync_end, mode->vtotal,
2782                    mode->type, mode->flags);
2783 }
2784
2785 static void intel_encoder_info(struct seq_file *m,
2786                                struct intel_crtc *intel_crtc,
2787                                struct intel_encoder *intel_encoder)
2788 {
2789         struct drm_info_node *node = m->private;
2790         struct drm_device *dev = node->minor->dev;
2791         struct drm_crtc *crtc = &intel_crtc->base;
2792         struct intel_connector *intel_connector;
2793         struct drm_encoder *encoder;
2794
2795         encoder = &intel_encoder->base;
2796         seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2797                    encoder->base.id, encoder->name);
2798         for_each_connector_on_encoder(dev, encoder, intel_connector) {
2799                 struct drm_connector *connector = &intel_connector->base;
2800                 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2801                            connector->base.id,
2802                            connector->name,
2803                            drm_get_connector_status_name(connector->status));
2804                 if (connector->status == connector_status_connected) {
2805                         struct drm_display_mode *mode = &crtc->mode;
2806                         seq_printf(m, ", mode:\n");
2807                         intel_seq_print_mode(m, 2, mode);
2808                 } else {
2809                         seq_putc(m, '\n');
2810                 }
2811         }
2812 }
2813
2814 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2815 {
2816         struct drm_info_node *node = m->private;
2817         struct drm_device *dev = node->minor->dev;
2818         struct drm_crtc *crtc = &intel_crtc->base;
2819         struct intel_encoder *intel_encoder;
2820         struct drm_plane_state *plane_state = crtc->primary->state;
2821         struct drm_framebuffer *fb = plane_state->fb;
2822
2823         if (fb)
2824                 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2825                            fb->base.id, plane_state->src_x >> 16,
2826                            plane_state->src_y >> 16, fb->width, fb->height);
2827         else
2828                 seq_puts(m, "\tprimary plane disabled\n");
2829         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2830                 intel_encoder_info(m, intel_crtc, intel_encoder);
2831 }
2832
2833 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2834 {
2835         struct drm_display_mode *mode = panel->fixed_mode;
2836
2837         seq_printf(m, "\tfixed mode:\n");
2838         intel_seq_print_mode(m, 2, mode);
2839 }
2840
2841 static void intel_dp_info(struct seq_file *m,
2842                           struct intel_connector *intel_connector)
2843 {
2844         struct intel_encoder *intel_encoder = intel_connector->encoder;
2845         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2846
2847         seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2848         seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2849         if (intel_encoder->type == INTEL_OUTPUT_EDP)
2850                 intel_panel_info(m, &intel_connector->panel);
2851 }
2852
2853 static void intel_hdmi_info(struct seq_file *m,
2854                             struct intel_connector *intel_connector)
2855 {
2856         struct intel_encoder *intel_encoder = intel_connector->encoder;
2857         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2858
2859         seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
2860 }
2861
2862 static void intel_lvds_info(struct seq_file *m,
2863                             struct intel_connector *intel_connector)
2864 {
2865         intel_panel_info(m, &intel_connector->panel);
2866 }
2867
2868 static void intel_connector_info(struct seq_file *m,
2869                                  struct drm_connector *connector)
2870 {
2871         struct intel_connector *intel_connector = to_intel_connector(connector);
2872         struct intel_encoder *intel_encoder = intel_connector->encoder;
2873         struct drm_display_mode *mode;
2874
2875         seq_printf(m, "connector %d: type %s, status: %s\n",
2876                    connector->base.id, connector->name,
2877                    drm_get_connector_status_name(connector->status));
2878         if (connector->status == connector_status_connected) {
2879                 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2880                 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2881                            connector->display_info.width_mm,
2882                            connector->display_info.height_mm);
2883                 seq_printf(m, "\tsubpixel order: %s\n",
2884                            drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2885                 seq_printf(m, "\tCEA rev: %d\n",
2886                            connector->display_info.cea_rev);
2887         }
2888         if (intel_encoder) {
2889                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2890                     intel_encoder->type == INTEL_OUTPUT_EDP)
2891                         intel_dp_info(m, intel_connector);
2892                 else if (intel_encoder->type == INTEL_OUTPUT_HDMI)
2893                         intel_hdmi_info(m, intel_connector);
2894                 else if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2895                         intel_lvds_info(m, intel_connector);
2896         }
2897
2898         seq_printf(m, "\tmodes:\n");
2899         list_for_each_entry(mode, &connector->modes, head)
2900                 intel_seq_print_mode(m, 2, mode);
2901 }
2902
2903 static bool cursor_active(struct drm_device *dev, int pipe)
2904 {
2905         struct drm_i915_private *dev_priv = dev->dev_private;
2906         u32 state;
2907
2908         if (IS_845G(dev) || IS_I865G(dev))
2909                 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
2910         else
2911                 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2912
2913         return state;
2914 }
2915
2916 static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
2917 {
2918         struct drm_i915_private *dev_priv = dev->dev_private;
2919         u32 pos;
2920
2921         pos = I915_READ(CURPOS(pipe));
2922
2923         *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
2924         if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
2925                 *x = -*x;
2926
2927         *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
2928         if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
2929                 *y = -*y;
2930
2931         return cursor_active(dev, pipe);
2932 }
2933
2934 static const char *plane_type(enum drm_plane_type type)
2935 {
2936         switch (type) {
2937         case DRM_PLANE_TYPE_OVERLAY:
2938                 return "OVL";
2939         case DRM_PLANE_TYPE_PRIMARY:
2940                 return "PRI";
2941         case DRM_PLANE_TYPE_CURSOR:
2942                 return "CUR";
2943         /*
2944          * Deliberately omitting default: to generate compiler warnings
2945          * when a new drm_plane_type gets added.
2946          */
2947         }
2948
2949         return "unknown";
2950 }
2951
2952 static const char *plane_rotation(unsigned int rotation)
2953 {
2954         static char buf[48];
2955         /*
2956          * According to doc only one DRM_ROTATE_ is allowed but this
2957          * will print them all to visualize if the values are misused
2958          */
2959         snprintf(buf, sizeof(buf),
2960                  "%s%s%s%s%s%s(0x%08x)",
2961                  (rotation & BIT(DRM_ROTATE_0)) ? "0 " : "",
2962                  (rotation & BIT(DRM_ROTATE_90)) ? "90 " : "",
2963                  (rotation & BIT(DRM_ROTATE_180)) ? "180 " : "",
2964                  (rotation & BIT(DRM_ROTATE_270)) ? "270 " : "",
2965                  (rotation & BIT(DRM_REFLECT_X)) ? "FLIPX " : "",
2966                  (rotation & BIT(DRM_REFLECT_Y)) ? "FLIPY " : "",
2967                  rotation);
2968
2969         return buf;
2970 }
2971
2972 static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2973 {
2974         struct drm_info_node *node = m->private;
2975         struct drm_device *dev = node->minor->dev;
2976         struct intel_plane *intel_plane;
2977
2978         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2979                 struct drm_plane_state *state;
2980                 struct drm_plane *plane = &intel_plane->base;
2981
2982                 if (!plane->state) {
2983                         seq_puts(m, "plane->state is NULL!\n");
2984                         continue;
2985                 }
2986
2987                 state = plane->state;
2988
2989                 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
2990                            plane->base.id,
2991                            plane_type(intel_plane->base.type),
2992                            state->crtc_x, state->crtc_y,
2993                            state->crtc_w, state->crtc_h,
2994                            (state->src_x >> 16),
2995                            ((state->src_x & 0xffff) * 15625) >> 10,
2996                            (state->src_y >> 16),
2997                            ((state->src_y & 0xffff) * 15625) >> 10,
2998                            (state->src_w >> 16),
2999                            ((state->src_w & 0xffff) * 15625) >> 10,
3000                            (state->src_h >> 16),
3001                            ((state->src_h & 0xffff) * 15625) >> 10,
3002                            state->fb ? drm_get_format_name(state->fb->pixel_format) : "N/A",
3003                            plane_rotation(state->rotation));
3004         }
3005 }
3006
3007 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3008 {
3009         struct intel_crtc_state *pipe_config;
3010         int num_scalers = intel_crtc->num_scalers;
3011         int i;
3012
3013         pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3014
3015         /* Not all platformas have a scaler */
3016         if (num_scalers) {
3017                 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3018                            num_scalers,
3019                            pipe_config->scaler_state.scaler_users,
3020                            pipe_config->scaler_state.scaler_id);
3021
3022                 for (i = 0; i < SKL_NUM_SCALERS; i++) {
3023                         struct intel_scaler *sc =
3024                                         &pipe_config->scaler_state.scalers[i];
3025
3026                         seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3027                                    i, yesno(sc->in_use), sc->mode);
3028                 }
3029                 seq_puts(m, "\n");
3030         } else {
3031                 seq_puts(m, "\tNo scalers available on this platform\n");
3032         }
3033 }
3034
3035 static int i915_display_info(struct seq_file *m, void *unused)
3036 {
3037         struct drm_info_node *node = m->private;
3038         struct drm_device *dev = node->minor->dev;
3039         struct drm_i915_private *dev_priv = dev->dev_private;
3040         struct intel_crtc *crtc;
3041         struct drm_connector *connector;
3042
3043         intel_runtime_pm_get(dev_priv);
3044         drm_modeset_lock_all(dev);
3045         seq_printf(m, "CRTC info\n");
3046         seq_printf(m, "---------\n");
3047         for_each_intel_crtc(dev, crtc) {
3048                 bool active;
3049                 struct intel_crtc_state *pipe_config;
3050                 int x, y;
3051
3052                 pipe_config = to_intel_crtc_state(crtc->base.state);
3053
3054                 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3055                            crtc->base.base.id, pipe_name(crtc->pipe),
3056                            yesno(pipe_config->base.active),
3057                            pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3058                            yesno(pipe_config->dither), pipe_config->pipe_bpp);
3059
3060                 if (pipe_config->base.active) {
3061                         intel_crtc_info(m, crtc);
3062
3063                         active = cursor_position(dev, crtc->pipe, &x, &y);
3064                         seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
3065                                    yesno(crtc->cursor_base),
3066                                    x, y, crtc->base.cursor->state->crtc_w,
3067                                    crtc->base.cursor->state->crtc_h,
3068                                    crtc->cursor_addr, yesno(active));
3069                         intel_scaler_info(m, crtc);
3070                         intel_plane_info(m, crtc);
3071                 }
3072
3073                 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3074                            yesno(!crtc->cpu_fifo_underrun_disabled),
3075                            yesno(!crtc->pch_fifo_underrun_disabled));
3076         }
3077
3078         seq_printf(m, "\n");
3079         seq_printf(m, "Connector info\n");
3080         seq_printf(m, "--------------\n");
3081         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3082                 intel_connector_info(m, connector);
3083         }
3084         drm_modeset_unlock_all(dev);
3085         intel_runtime_pm_put(dev_priv);
3086
3087         return 0;
3088 }
3089
3090 static int i915_semaphore_status(struct seq_file *m, void *unused)
3091 {
3092         struct drm_info_node *node = (struct drm_info_node *) m->private;
3093         struct drm_device *dev = node->minor->dev;
3094         struct drm_i915_private *dev_priv = dev->dev_private;
3095         struct intel_engine_cs *ring;
3096         int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
3097         int i, j, ret;
3098
3099         if (!i915_semaphore_is_enabled(dev)) {
3100                 seq_puts(m, "Semaphores are disabled\n");
3101                 return 0;
3102         }
3103
3104         ret = mutex_lock_interruptible(&dev->struct_mutex);
3105         if (ret)
3106                 return ret;
3107         intel_runtime_pm_get(dev_priv);
3108
3109         if (IS_BROADWELL(dev)) {
3110                 struct page *page;
3111                 uint64_t *seqno;
3112
3113                 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
3114
3115                 seqno = (uint64_t *)kmap_atomic(page);
3116                 for_each_ring(ring, dev_priv, i) {
3117                         uint64_t offset;
3118
3119                         seq_printf(m, "%s\n", ring->name);
3120
3121                         seq_puts(m, "  Last signal:");
3122                         for (j = 0; j < num_rings; j++) {
3123                                 offset = i * I915_NUM_RINGS + j;
3124                                 seq_printf(m, "0x%08llx (0x%02llx) ",
3125                                            seqno[offset], offset * 8);
3126                         }
3127                         seq_putc(m, '\n');
3128
3129                         seq_puts(m, "  Last wait:  ");
3130                         for (j = 0; j < num_rings; j++) {
3131                                 offset = i + (j * I915_NUM_RINGS);
3132                                 seq_printf(m, "0x%08llx (0x%02llx) ",
3133                                            seqno[offset], offset * 8);
3134                         }
3135                         seq_putc(m, '\n');
3136
3137                 }
3138                 kunmap_atomic(seqno);
3139         } else {
3140                 seq_puts(m, "  Last signal:");
3141                 for_each_ring(ring, dev_priv, i)
3142                         for (j = 0; j < num_rings; j++)
3143                                 seq_printf(m, "0x%08x\n",
3144                                            I915_READ(ring->semaphore.mbox.signal[j]));
3145                 seq_putc(m, '\n');
3146         }
3147
3148         seq_puts(m, "\nSync seqno:\n");
3149         for_each_ring(ring, dev_priv, i) {
3150                 for (j = 0; j < num_rings; j++) {
3151                         seq_printf(m, "  0x%08x ", ring->semaphore.sync_seqno[j]);
3152                 }
3153                 seq_putc(m, '\n');
3154         }
3155         seq_putc(m, '\n');
3156
3157         intel_runtime_pm_put(dev_priv);
3158         mutex_unlock(&dev->struct_mutex);
3159         return 0;
3160 }
3161
3162 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3163 {
3164         struct drm_info_node *node = (struct drm_info_node *) m->private;
3165         struct drm_device *dev = node->minor->dev;
3166         struct drm_i915_private *dev_priv = dev->dev_private;
3167         int i;
3168
3169         drm_modeset_lock_all(dev);
3170         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3171                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3172
3173                 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3174                 seq_printf(m, " crtc_mask: 0x%08x, active: %d, on: %s\n",
3175                            pll->config.crtc_mask, pll->active, yesno(pll->on));
3176                 seq_printf(m, " tracked hardware state:\n");
3177                 seq_printf(m, " dpll:    0x%08x\n", pll->config.hw_state.dpll);
3178                 seq_printf(m, " dpll_md: 0x%08x\n",
3179                            pll->config.hw_state.dpll_md);
3180                 seq_printf(m, " fp0:     0x%08x\n", pll->config.hw_state.fp0);
3181                 seq_printf(m, " fp1:     0x%08x\n", pll->config.hw_state.fp1);
3182                 seq_printf(m, " wrpll:   0x%08x\n", pll->config.hw_state.wrpll);
3183         }
3184         drm_modeset_unlock_all(dev);
3185
3186         return 0;
3187 }
3188
3189 static int i915_wa_registers(struct seq_file *m, void *unused)
3190 {
3191         int i;
3192         int ret;
3193         struct drm_info_node *node = (struct drm_info_node *) m->private;
3194         struct drm_device *dev = node->minor->dev;
3195         struct drm_i915_private *dev_priv = dev->dev_private;
3196
3197         ret = mutex_lock_interruptible(&dev->struct_mutex);
3198         if (ret)
3199                 return ret;
3200
3201         intel_runtime_pm_get(dev_priv);
3202
3203         seq_printf(m, "Workarounds applied: %d\n", dev_priv->workarounds.count);
3204         for (i = 0; i < dev_priv->workarounds.count; ++i) {
3205                 i915_reg_t addr;
3206                 u32 mask, value, read;
3207                 bool ok;
3208
3209                 addr = dev_priv->workarounds.reg[i].addr;
3210                 mask = dev_priv->workarounds.reg[i].mask;
3211                 value = dev_priv->workarounds.reg[i].value;
3212                 read = I915_READ(addr);
3213                 ok = (value & mask) == (read & mask);
3214                 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3215                            i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
3216         }
3217
3218         intel_runtime_pm_put(dev_priv);
3219         mutex_unlock(&dev->struct_mutex);
3220
3221         return 0;
3222 }
3223
3224 static int i915_ddb_info(struct seq_file *m, void *unused)
3225 {
3226         struct drm_info_node *node = m->private;
3227         struct drm_device *dev = node->minor->dev;
3228         struct drm_i915_private *dev_priv = dev->dev_private;
3229         struct skl_ddb_allocation *ddb;
3230         struct skl_ddb_entry *entry;
3231         enum pipe pipe;
3232         int plane;
3233
3234         if (INTEL_INFO(dev)->gen < 9)
3235                 return 0;
3236
3237         drm_modeset_lock_all(dev);
3238
3239         ddb = &dev_priv->wm.skl_hw.ddb;
3240
3241         seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3242
3243         for_each_pipe(dev_priv, pipe) {
3244                 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3245
3246                 for_each_plane(dev_priv, pipe, plane) {
3247                         entry = &ddb->plane[pipe][plane];
3248                         seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane + 1,
3249                                    entry->start, entry->end,
3250                                    skl_ddb_entry_size(entry));
3251                 }
3252
3253                 entry = &ddb->plane[pipe][PLANE_CURSOR];
3254                 seq_printf(m, "  %-13s%8u%8u%8u\n", "Cursor", entry->start,
3255                            entry->end, skl_ddb_entry_size(entry));
3256         }
3257
3258         drm_modeset_unlock_all(dev);
3259
3260         return 0;
3261 }
3262
3263 static void drrs_status_per_crtc(struct seq_file *m,
3264                 struct drm_device *dev, struct intel_crtc *intel_crtc)
3265 {
3266         struct intel_encoder *intel_encoder;
3267         struct drm_i915_private *dev_priv = dev->dev_private;
3268         struct i915_drrs *drrs = &dev_priv->drrs;
3269         int vrefresh = 0;
3270
3271         for_each_encoder_on_crtc(dev, &intel_crtc->base, intel_encoder) {
3272                 /* Encoder connected on this CRTC */
3273                 switch (intel_encoder->type) {
3274                 case INTEL_OUTPUT_EDP:
3275                         seq_puts(m, "eDP:\n");
3276                         break;
3277                 case INTEL_OUTPUT_DSI:
3278                         seq_puts(m, "DSI:\n");
3279                         break;
3280                 case INTEL_OUTPUT_HDMI:
3281                         seq_puts(m, "HDMI:\n");
3282                         break;
3283                 case INTEL_OUTPUT_DISPLAYPORT:
3284                         seq_puts(m, "DP:\n");
3285                         break;
3286                 default:
3287                         seq_printf(m, "Other encoder (id=%d).\n",
3288                                                 intel_encoder->type);
3289                         return;
3290                 }
3291         }
3292
3293         if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3294                 seq_puts(m, "\tVBT: DRRS_type: Static");
3295         else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3296                 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3297         else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3298                 seq_puts(m, "\tVBT: DRRS_type: None");
3299         else
3300                 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3301
3302         seq_puts(m, "\n\n");
3303
3304         if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3305                 struct intel_panel *panel;
3306
3307                 mutex_lock(&drrs->mutex);
3308                 /* DRRS Supported */
3309                 seq_puts(m, "\tDRRS Supported: Yes\n");
3310
3311                 /* disable_drrs() will make drrs->dp NULL */
3312                 if (!drrs->dp) {
3313                         seq_puts(m, "Idleness DRRS: Disabled");
3314                         mutex_unlock(&drrs->mutex);
3315                         return;
3316                 }
3317
3318                 panel = &drrs->dp->attached_connector->panel;
3319                 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3320                                         drrs->busy_frontbuffer_bits);
3321
3322                 seq_puts(m, "\n\t\t");
3323                 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3324                         seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3325                         vrefresh = panel->fixed_mode->vrefresh;
3326                 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3327                         seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3328                         vrefresh = panel->downclock_mode->vrefresh;
3329                 } else {
3330                         seq_printf(m, "DRRS_State: Unknown(%d)\n",
3331                                                 drrs->refresh_rate_type);
3332                         mutex_unlock(&drrs->mutex);
3333                         return;
3334                 }
3335                 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3336
3337                 seq_puts(m, "\n\t\t");
3338                 mutex_unlock(&drrs->mutex);
3339         } else {
3340                 /* DRRS not supported. Print the VBT parameter*/
3341                 seq_puts(m, "\tDRRS Supported : No");
3342         }
3343         seq_puts(m, "\n");
3344 }
3345
3346 static int i915_drrs_status(struct seq_file *m, void *unused)
3347 {
3348         struct drm_info_node *node = m->private;
3349         struct drm_device *dev = node->minor->dev;
3350         struct intel_crtc *intel_crtc;
3351         int active_crtc_cnt = 0;
3352
3353         for_each_intel_crtc(dev, intel_crtc) {
3354                 drm_modeset_lock(&intel_crtc->base.mutex, NULL);
3355
3356                 if (intel_crtc->base.state->active) {
3357                         active_crtc_cnt++;
3358                         seq_printf(m, "\nCRTC %d:  ", active_crtc_cnt);
3359
3360                         drrs_status_per_crtc(m, dev, intel_crtc);
3361                 }
3362
3363                 drm_modeset_unlock(&intel_crtc->base.mutex);
3364         }
3365
3366         if (!active_crtc_cnt)
3367                 seq_puts(m, "No active crtc found\n");
3368
3369         return 0;
3370 }
3371
3372 struct pipe_crc_info {
3373         const char *name;
3374         struct drm_device *dev;
3375         enum pipe pipe;
3376 };
3377
3378 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3379 {
3380         struct drm_info_node *node = (struct drm_info_node *) m->private;
3381         struct drm_device *dev = node->minor->dev;
3382         struct drm_encoder *encoder;
3383         struct intel_encoder *intel_encoder;
3384         struct intel_digital_port *intel_dig_port;
3385         drm_modeset_lock_all(dev);
3386         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3387                 intel_encoder = to_intel_encoder(encoder);
3388                 if (intel_encoder->type != INTEL_OUTPUT_DISPLAYPORT)
3389                         continue;
3390                 intel_dig_port = enc_to_dig_port(encoder);
3391                 if (!intel_dig_port->dp.can_mst)
3392                         continue;
3393
3394                 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3395         }
3396         drm_modeset_unlock_all(dev);
3397         return 0;
3398 }
3399
3400 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3401 {
3402         struct pipe_crc_info *info = inode->i_private;
3403         struct drm_i915_private *dev_priv = info->dev->dev_private;
3404         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3405
3406         if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3407                 return -ENODEV;
3408
3409         spin_lock_irq(&pipe_crc->lock);
3410
3411         if (pipe_crc->opened) {
3412                 spin_unlock_irq(&pipe_crc->lock);
3413                 return -EBUSY; /* already open */
3414         }
3415
3416         pipe_crc->opened = true;
3417         filep->private_data = inode->i_private;
3418
3419         spin_unlock_irq(&pipe_crc->lock);
3420
3421         return 0;
3422 }
3423
3424 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3425 {
3426         struct pipe_crc_info *info = inode->i_private;
3427         struct drm_i915_private *dev_priv = info->dev->dev_private;
3428         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3429
3430         spin_lock_irq(&pipe_crc->lock);
3431         pipe_crc->opened = false;
3432         spin_unlock_irq(&pipe_crc->lock);
3433
3434         return 0;
3435 }
3436
3437 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3438 #define PIPE_CRC_LINE_LEN       (6 * 8 + 5 + 1)
3439 /* account for \'0' */
3440 #define PIPE_CRC_BUFFER_LEN     (PIPE_CRC_LINE_LEN + 1)
3441
3442 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
3443 {
3444         assert_spin_locked(&pipe_crc->lock);
3445         return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3446                         INTEL_PIPE_CRC_ENTRIES_NR);
3447 }
3448
3449 static ssize_t
3450 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3451                    loff_t *pos)
3452 {
3453         struct pipe_crc_info *info = filep->private_data;
3454         struct drm_device *dev = info->dev;
3455         struct drm_i915_private *dev_priv = dev->dev_private;
3456         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3457         char buf[PIPE_CRC_BUFFER_LEN];
3458         int n_entries;
3459         ssize_t bytes_read;
3460
3461         /*
3462          * Don't allow user space to provide buffers not big enough to hold
3463          * a line of data.
3464          */
3465         if (count < PIPE_CRC_LINE_LEN)
3466                 return -EINVAL;
3467
3468         if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
3469                 return 0;
3470
3471         /* nothing to read */
3472         spin_lock_irq(&pipe_crc->lock);
3473         while (pipe_crc_data_count(pipe_crc) == 0) {
3474                 int ret;
3475
3476                 if (filep->f_flags & O_NONBLOCK) {
3477                         spin_unlock_irq(&pipe_crc->lock);
3478                         return -EAGAIN;
3479                 }
3480
3481                 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3482                                 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3483                 if (ret) {
3484                         spin_unlock_irq(&pipe_crc->lock);
3485                         return ret;
3486                 }
3487         }
3488
3489         /* We now have one or more entries to read */
3490         n_entries = count / PIPE_CRC_LINE_LEN;
3491
3492         bytes_read = 0;
3493         while (n_entries > 0) {
3494                 struct intel_pipe_crc_entry *entry =
3495                         &pipe_crc->entries[pipe_crc->tail];
3496                 int ret;
3497
3498                 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3499                              INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3500                         break;
3501
3502                 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3503                 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3504
3505                 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3506                                        "%8u %8x %8x %8x %8x %8x\n",
3507                                        entry->frame, entry->crc[0],
3508                                        entry->crc[1], entry->crc[2],
3509                                        entry->crc[3], entry->crc[4]);
3510
3511                 spin_unlock_irq(&pipe_crc->lock);
3512
3513                 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
3514                 if (ret == PIPE_CRC_LINE_LEN)
3515                         return -EFAULT;
3516
3517                 user_buf += PIPE_CRC_LINE_LEN;
3518                 n_entries--;
3519
3520                 spin_lock_irq(&pipe_crc->lock);
3521         }
3522
3523         spin_unlock_irq(&pipe_crc->lock);
3524
3525         return bytes_read;
3526 }
3527
3528 static const struct file_operations i915_pipe_crc_fops = {
3529         .owner = THIS_MODULE,
3530         .open = i915_pipe_crc_open,
3531         .read = i915_pipe_crc_read,
3532         .release = i915_pipe_crc_release,
3533 };
3534
3535 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3536         {
3537                 .name = "i915_pipe_A_crc",
3538                 .pipe = PIPE_A,
3539         },
3540         {
3541                 .name = "i915_pipe_B_crc",
3542                 .pipe = PIPE_B,
3543         },
3544         {
3545                 .name = "i915_pipe_C_crc",
3546                 .pipe = PIPE_C,
3547         },
3548 };
3549
3550 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3551                                 enum pipe pipe)
3552 {
3553         struct drm_device *dev = minor->dev;
3554         struct dentry *ent;
3555         struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3556
3557         info->dev = dev;
3558         ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3559                                   &i915_pipe_crc_fops);
3560         if (!ent)
3561                 return -ENOMEM;
3562
3563         return drm_add_fake_info_node(minor, ent, info);
3564 }
3565
3566 static const char * const pipe_crc_sources[] = {
3567         "none",
3568         "plane1",
3569         "plane2",
3570         "pf",
3571         "pipe",
3572         "TV",
3573         "DP-B",
3574         "DP-C",
3575         "DP-D",
3576         "auto",
3577 };
3578
3579 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3580 {
3581         BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3582         return pipe_crc_sources[source];
3583 }
3584
3585 static int display_crc_ctl_show(struct seq_file *m, void *data)
3586 {
3587         struct drm_device *dev = m->private;
3588         struct drm_i915_private *dev_priv = dev->dev_private;
3589         int i;
3590
3591         for (i = 0; i < I915_MAX_PIPES; i++)
3592                 seq_printf(m, "%c %s\n", pipe_name(i),
3593                            pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3594
3595         return 0;
3596 }
3597
3598 static int display_crc_ctl_open(struct inode *inode, struct file *file)
3599 {
3600         struct drm_device *dev = inode->i_private;
3601
3602         return single_open(file, display_crc_ctl_show, dev);
3603 }
3604
3605 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3606                                  uint32_t *val)
3607 {
3608         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3609                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3610
3611         switch (*source) {
3612         case INTEL_PIPE_CRC_SOURCE_PIPE:
3613                 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3614                 break;
3615         case INTEL_PIPE_CRC_SOURCE_NONE:
3616                 *val = 0;
3617                 break;
3618         default:
3619                 return -EINVAL;
3620         }
3621
3622         return 0;
3623 }
3624
3625 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3626                                      enum intel_pipe_crc_source *source)
3627 {
3628         struct intel_encoder *encoder;
3629         struct intel_crtc *crtc;
3630         struct intel_digital_port *dig_port;
3631         int ret = 0;
3632
3633         *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3634
3635         drm_modeset_lock_all(dev);
3636         for_each_intel_encoder(dev, encoder) {
3637                 if (!encoder->base.crtc)
3638                         continue;
3639
3640                 crtc = to_intel_crtc(encoder->base.crtc);
3641
3642                 if (crtc->pipe != pipe)
3643                         continue;
3644
3645                 switch (encoder->type) {
3646                 case INTEL_OUTPUT_TVOUT:
3647                         *source = INTEL_PIPE_CRC_SOURCE_TV;
3648                         break;
3649                 case INTEL_OUTPUT_DISPLAYPORT:
3650                 case INTEL_OUTPUT_EDP:
3651                         dig_port = enc_to_dig_port(&encoder->base);
3652                         switch (dig_port->port) {
3653                         case PORT_B:
3654                                 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3655                                 break;
3656                         case PORT_C:
3657                                 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3658                                 break;
3659                         case PORT_D:
3660                                 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3661                                 break;
3662                         default:
3663                                 WARN(1, "nonexisting DP port %c\n",
3664                                      port_name(dig_port->port));
3665                                 break;
3666                         }
3667                         break;
3668                 default:
3669                         break;
3670                 }
3671         }
3672         drm_modeset_unlock_all(dev);
3673
3674         return ret;
3675 }
3676
3677 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3678                                 enum pipe pipe,
3679                                 enum intel_pipe_crc_source *source,
3680                                 uint32_t *val)
3681 {
3682         struct drm_i915_private *dev_priv = dev->dev_private;
3683         bool need_stable_symbols = false;
3684
3685         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3686                 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3687                 if (ret)
3688                         return ret;
3689         }
3690
3691         switch (*source) {
3692         case INTEL_PIPE_CRC_SOURCE_PIPE:
3693                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3694                 break;
3695         case INTEL_PIPE_CRC_SOURCE_DP_B:
3696                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3697                 need_stable_symbols = true;
3698                 break;
3699         case INTEL_PIPE_CRC_SOURCE_DP_C:
3700                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3701                 need_stable_symbols = true;
3702                 break;
3703         case INTEL_PIPE_CRC_SOURCE_DP_D:
3704                 if (!IS_CHERRYVIEW(dev))
3705                         return -EINVAL;
3706                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3707                 need_stable_symbols = true;
3708                 break;
3709         case INTEL_PIPE_CRC_SOURCE_NONE:
3710                 *val = 0;
3711                 break;
3712         default:
3713                 return -EINVAL;
3714         }
3715
3716         /*
3717          * When the pipe CRC tap point is after the transcoders we need
3718          * to tweak symbol-level features to produce a deterministic series of
3719          * symbols for a given frame. We need to reset those features only once
3720          * a frame (instead of every nth symbol):
3721          *   - DC-balance: used to ensure a better clock recovery from the data
3722          *     link (SDVO)
3723          *   - DisplayPort scrambling: used for EMI reduction
3724          */
3725         if (need_stable_symbols) {
3726                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3727
3728                 tmp |= DC_BALANCE_RESET_VLV;
3729                 switch (pipe) {
3730                 case PIPE_A:
3731                         tmp |= PIPE_A_SCRAMBLE_RESET;
3732                         break;
3733                 case PIPE_B:
3734                         tmp |= PIPE_B_SCRAMBLE_RESET;
3735                         break;
3736                 case PIPE_C:
3737                         tmp |= PIPE_C_SCRAMBLE_RESET;
3738                         break;
3739                 default:
3740                         return -EINVAL;
3741                 }
3742                 I915_WRITE(PORT_DFT2_G4X, tmp);
3743         }
3744
3745         return 0;
3746 }
3747
3748 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
3749                                  enum pipe pipe,
3750                                  enum intel_pipe_crc_source *source,
3751                                  uint32_t *val)
3752 {
3753         struct drm_i915_private *dev_priv = dev->dev_private;
3754         bool need_stable_symbols = false;
3755
3756         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3757                 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3758                 if (ret)
3759                         return ret;
3760         }
3761
3762         switch (*source) {
3763         case INTEL_PIPE_CRC_SOURCE_PIPE:
3764                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3765                 break;
3766         case INTEL_PIPE_CRC_SOURCE_TV:
3767                 if (!SUPPORTS_TV(dev))
3768                         return -EINVAL;
3769                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3770                 break;
3771         case INTEL_PIPE_CRC_SOURCE_DP_B:
3772                 if (!IS_G4X(dev))
3773                         return -EINVAL;
3774                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3775                 need_stable_symbols = true;
3776                 break;
3777         case INTEL_PIPE_CRC_SOURCE_DP_C:
3778                 if (!IS_G4X(dev))
3779                         return -EINVAL;
3780                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3781                 need_stable_symbols = true;
3782                 break;
3783         case INTEL_PIPE_CRC_SOURCE_DP_D:
3784                 if (!IS_G4X(dev))
3785                         return -EINVAL;
3786                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3787                 need_stable_symbols = true;
3788                 break;
3789         case INTEL_PIPE_CRC_SOURCE_NONE:
3790                 *val = 0;
3791                 break;
3792         default:
3793                 return -EINVAL;
3794         }
3795
3796         /*
3797          * When the pipe CRC tap point is after the transcoders we need
3798          * to tweak symbol-level features to produce a deterministic series of
3799          * symbols for a given frame. We need to reset those features only once
3800          * a frame (instead of every nth symbol):
3801          *   - DC-balance: used to ensure a better clock recovery from the data
3802          *     link (SDVO)
3803          *   - DisplayPort scrambling: used for EMI reduction
3804          */
3805         if (need_stable_symbols) {
3806                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3807
3808                 WARN_ON(!IS_G4X(dev));
3809
3810                 I915_WRITE(PORT_DFT_I9XX,
3811                            I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3812
3813                 if (pipe == PIPE_A)
3814                         tmp |= PIPE_A_SCRAMBLE_RESET;
3815                 else
3816                         tmp |= PIPE_B_SCRAMBLE_RESET;
3817
3818                 I915_WRITE(PORT_DFT2_G4X, tmp);
3819         }
3820
3821         return 0;
3822 }
3823
3824 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3825                                          enum pipe pipe)
3826 {
3827         struct drm_i915_private *dev_priv = dev->dev_private;
3828         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3829
3830         switch (pipe) {
3831         case PIPE_A:
3832                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3833                 break;
3834         case PIPE_B:
3835                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3836                 break;
3837         case PIPE_C:
3838                 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3839                 break;
3840         default:
3841                 return;
3842         }
3843         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3844                 tmp &= ~DC_BALANCE_RESET_VLV;
3845         I915_WRITE(PORT_DFT2_G4X, tmp);
3846
3847 }
3848
3849 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3850                                          enum pipe pipe)
3851 {
3852         struct drm_i915_private *dev_priv = dev->dev_private;
3853         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3854
3855         if (pipe == PIPE_A)
3856                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3857         else
3858                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3859         I915_WRITE(PORT_DFT2_G4X, tmp);
3860
3861         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3862                 I915_WRITE(PORT_DFT_I9XX,
3863                            I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3864         }
3865 }
3866
3867 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3868                                 uint32_t *val)
3869 {
3870         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3871                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3872
3873         switch (*source) {
3874         case INTEL_PIPE_CRC_SOURCE_PLANE1:
3875                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
3876                 break;
3877         case INTEL_PIPE_CRC_SOURCE_PLANE2:
3878                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
3879                 break;
3880         case INTEL_PIPE_CRC_SOURCE_PIPE:
3881                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
3882                 break;
3883         case INTEL_PIPE_CRC_SOURCE_NONE:
3884                 *val = 0;
3885                 break;
3886         default:
3887                 return -EINVAL;
3888         }
3889
3890         return 0;
3891 }
3892
3893 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev, bool enable)
3894 {
3895         struct drm_i915_private *dev_priv = dev->dev_private;
3896         struct intel_crtc *crtc =
3897                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
3898         struct intel_crtc_state *pipe_config;
3899         struct drm_atomic_state *state;
3900         int ret = 0;
3901
3902         drm_modeset_lock_all(dev);
3903         state = drm_atomic_state_alloc(dev);
3904         if (!state) {
3905                 ret = -ENOMEM;
3906                 goto out;
3907         }
3908
3909         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
3910         pipe_config = intel_atomic_get_crtc_state(state, crtc);
3911         if (IS_ERR(pipe_config)) {
3912                 ret = PTR_ERR(pipe_config);
3913                 goto out;
3914         }
3915
3916         pipe_config->pch_pfit.force_thru = enable;
3917         if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
3918             pipe_config->pch_pfit.enabled != enable)
3919                 pipe_config->base.connectors_changed = true;
3920
3921         ret = drm_atomic_commit(state);
3922 out:
3923         drm_modeset_unlock_all(dev);
3924         WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
3925         if (ret)
3926                 drm_atomic_state_free(state);
3927 }
3928
3929 static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
3930                                 enum pipe pipe,
3931                                 enum intel_pipe_crc_source *source,
3932                                 uint32_t *val)
3933 {
3934         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3935                 *source = INTEL_PIPE_CRC_SOURCE_PF;
3936
3937         switch (*source) {
3938         case INTEL_PIPE_CRC_SOURCE_PLANE1:
3939                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
3940                 break;
3941         case INTEL_PIPE_CRC_SOURCE_PLANE2:
3942                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
3943                 break;
3944         case INTEL_PIPE_CRC_SOURCE_PF:
3945                 if (IS_HASWELL(dev) && pipe == PIPE_A)
3946                         hsw_trans_edp_pipe_A_crc_wa(dev, true);
3947
3948                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
3949                 break;
3950         case INTEL_PIPE_CRC_SOURCE_NONE:
3951                 *val = 0;
3952                 break;
3953         default:
3954                 return -EINVAL;
3955         }
3956
3957         return 0;
3958 }
3959
3960 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
3961                                enum intel_pipe_crc_source source)
3962 {
3963         struct drm_i915_private *dev_priv = dev->dev_private;
3964         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
3965         struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
3966                                                                         pipe));
3967         u32 val = 0; /* shut up gcc */
3968         int ret;
3969
3970         if (pipe_crc->source == source)
3971                 return 0;
3972
3973         /* forbid changing the source without going back to 'none' */
3974         if (pipe_crc->source && source)
3975                 return -EINVAL;
3976
3977         if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) {
3978                 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
3979                 return -EIO;
3980         }
3981
3982         if (IS_GEN2(dev))
3983                 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
3984         else if (INTEL_INFO(dev)->gen < 5)
3985                 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3986         else if (IS_VALLEYVIEW(dev))
3987                 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3988         else if (IS_GEN5(dev) || IS_GEN6(dev))
3989                 ret = ilk_pipe_crc_ctl_reg(&source, &val);
3990         else
3991                 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
3992
3993         if (ret != 0)
3994                 return ret;
3995
3996         /* none -> real source transition */
3997         if (source) {
3998                 struct intel_pipe_crc_entry *entries;
3999
4000                 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4001                                  pipe_name(pipe), pipe_crc_source_name(source));
4002
4003                 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
4004                                   sizeof(pipe_crc->entries[0]),
4005                                   GFP_KERNEL);
4006                 if (!entries)
4007                         return -ENOMEM;
4008
4009                 /*
4010                  * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4011                  * enabled and disabled dynamically based on package C states,
4012                  * user space can't make reliable use of the CRCs, so let's just
4013                  * completely disable it.
4014                  */
4015                 hsw_disable_ips(crtc);
4016
4017                 spin_lock_irq(&pipe_crc->lock);
4018                 kfree(pipe_crc->entries);
4019                 pipe_crc->entries = entries;
4020                 pipe_crc->head = 0;
4021                 pipe_crc->tail = 0;
4022                 spin_unlock_irq(&pipe_crc->lock);
4023         }
4024
4025         pipe_crc->source = source;
4026
4027         I915_WRITE(PIPE_CRC_CTL(pipe), val);
4028         POSTING_READ(PIPE_CRC_CTL(pipe));
4029
4030         /* real source -> none transition */
4031         if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
4032                 struct intel_pipe_crc_entry *entries;
4033                 struct intel_crtc *crtc =
4034                         to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
4035
4036                 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4037                                  pipe_name(pipe));
4038
4039                 drm_modeset_lock(&crtc->base.mutex, NULL);
4040                 if (crtc->base.state->active)
4041                         intel_wait_for_vblank(dev, pipe);
4042                 drm_modeset_unlock(&crtc->base.mutex);
4043
4044                 spin_lock_irq(&pipe_crc->lock);
4045                 entries = pipe_crc->entries;
4046                 pipe_crc->entries = NULL;
4047                 pipe_crc->head = 0;
4048                 pipe_crc->tail = 0;
4049                 spin_unlock_irq(&pipe_crc->lock);
4050
4051                 kfree(entries);
4052
4053                 if (IS_G4X(dev))
4054                         g4x_undo_pipe_scramble_reset(dev, pipe);
4055                 else if (IS_VALLEYVIEW(dev))
4056                         vlv_undo_pipe_scramble_reset(dev, pipe);
4057                 else if (IS_HASWELL(dev) && pipe == PIPE_A)
4058                         hsw_trans_edp_pipe_A_crc_wa(dev, false);
4059
4060                 hsw_enable_ips(crtc);
4061         }
4062
4063         return 0;
4064 }
4065
4066 /*
4067  * Parse pipe CRC command strings:
4068  *   command: wsp* object wsp+ name wsp+ source wsp*
4069  *   object: 'pipe'
4070  *   name: (A | B | C)
4071  *   source: (none | plane1 | plane2 | pf)
4072  *   wsp: (#0x20 | #0x9 | #0xA)+
4073  *
4074  * eg.:
4075  *  "pipe A plane1"  ->  Start CRC computations on plane1 of pipe A
4076  *  "pipe A none"    ->  Stop CRC
4077  */
4078 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
4079 {
4080         int n_words = 0;
4081
4082         while (*buf) {
4083                 char *end;
4084
4085                 /* skip leading white space */
4086                 buf = skip_spaces(buf);
4087                 if (!*buf)
4088                         break;  /* end of buffer */
4089
4090                 /* find end of word */
4091                 for (end = buf; *end && !isspace(*end); end++)
4092                         ;
4093
4094                 if (n_words == max_words) {
4095                         DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4096                                          max_words);
4097                         return -EINVAL; /* ran out of words[] before bytes */
4098                 }
4099
4100                 if (*end)
4101                         *end++ = '\0';
4102                 words[n_words++] = buf;
4103                 buf = end;
4104         }
4105
4106         return n_words;
4107 }
4108
4109 enum intel_pipe_crc_object {
4110         PIPE_CRC_OBJECT_PIPE,
4111 };
4112
4113 static const char * const pipe_crc_objects[] = {
4114         "pipe",
4115 };
4116
4117 static int
4118 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
4119 {
4120         int i;
4121
4122         for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
4123                 if (!strcmp(buf, pipe_crc_objects[i])) {
4124                         *o = i;
4125                         return 0;
4126                     }
4127
4128         return -EINVAL;
4129 }
4130
4131 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
4132 {
4133         const char name = buf[0];
4134
4135         if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
4136                 return -EINVAL;
4137
4138         *pipe = name - 'A';
4139
4140         return 0;
4141 }
4142
4143 static int
4144 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
4145 {
4146         int i;
4147
4148         for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
4149                 if (!strcmp(buf, pipe_crc_sources[i])) {
4150                         *s = i;
4151                         return 0;
4152                     }
4153
4154         return -EINVAL;
4155 }
4156
4157 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
4158 {
4159 #define N_WORDS 3
4160         int n_words;
4161         char *words[N_WORDS];
4162         enum pipe pipe;
4163         enum intel_pipe_crc_object object;
4164         enum intel_pipe_crc_source source;
4165
4166         n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
4167         if (n_words != N_WORDS) {
4168                 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4169                                  N_WORDS);
4170                 return -EINVAL;
4171         }
4172
4173         if (display_crc_ctl_parse_object(words[0], &object) < 0) {
4174                 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
4175                 return -EINVAL;
4176         }
4177
4178         if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
4179                 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
4180                 return -EINVAL;
4181         }
4182
4183         if (display_crc_ctl_parse_source(words[2], &source) < 0) {
4184                 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
4185                 return -EINVAL;
4186         }
4187
4188         return pipe_crc_set_source(dev, pipe, source);
4189 }
4190
4191 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
4192                                      size_t len, loff_t *offp)
4193 {
4194         struct seq_file *m = file->private_data;
4195         struct drm_device *dev = m->private;
4196         char *tmpbuf;
4197         int ret;
4198
4199         if (len == 0)
4200                 return 0;
4201
4202         if (len > PAGE_SIZE - 1) {
4203                 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4204                                  PAGE_SIZE);
4205                 return -E2BIG;
4206         }
4207
4208         tmpbuf = kmalloc(len + 1, GFP_KERNEL);
4209         if (!tmpbuf)
4210                 return -ENOMEM;
4211
4212         if (copy_from_user(tmpbuf, ubuf, len)) {
4213                 ret = -EFAULT;
4214                 goto out;
4215         }
4216         tmpbuf[len] = '\0';
4217
4218         ret = display_crc_ctl_parse(dev, tmpbuf, len);
4219
4220 out:
4221         kfree(tmpbuf);
4222         if (ret < 0)
4223                 return ret;
4224
4225         *offp += len;
4226         return len;
4227 }
4228
4229 static const struct file_operations i915_display_crc_ctl_fops = {
4230         .owner = THIS_MODULE,
4231         .open = display_crc_ctl_open,
4232         .read = seq_read,
4233         .llseek = seq_lseek,
4234         .release = single_release,
4235         .write = display_crc_ctl_write
4236 };
4237
4238 static ssize_t i915_displayport_test_active_write(struct file *file,
4239                                             const char __user *ubuf,
4240                                             size_t len, loff_t *offp)
4241 {
4242         char *input_buffer;
4243         int status = 0;
4244         struct drm_device *dev;
4245         struct drm_connector *connector;
4246         struct list_head *connector_list;
4247         struct intel_dp *intel_dp;
4248         int val = 0;
4249
4250         dev = ((struct seq_file *)file->private_data)->private;
4251
4252         connector_list = &dev->mode_config.connector_list;
4253
4254         if (len == 0)
4255                 return 0;
4256
4257         input_buffer = kmalloc(len + 1, GFP_KERNEL);
4258         if (!input_buffer)
4259                 return -ENOMEM;
4260
4261         if (copy_from_user(input_buffer, ubuf, len)) {
4262                 status = -EFAULT;
4263                 goto out;
4264         }
4265
4266         input_buffer[len] = '\0';
4267         DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4268
4269         list_for_each_entry(connector, connector_list, head) {
4270
4271                 if (connector->connector_type !=
4272                     DRM_MODE_CONNECTOR_DisplayPort)
4273                         continue;
4274
4275                 if (connector->status == connector_status_connected &&
4276                     connector->encoder != NULL) {
4277                         intel_dp = enc_to_intel_dp(connector->encoder);
4278                         status = kstrtoint(input_buffer, 10, &val);
4279                         if (status < 0)
4280                                 goto out;
4281                         DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4282                         /* To prevent erroneous activation of the compliance
4283                          * testing code, only accept an actual value of 1 here
4284                          */
4285                         if (val == 1)
4286                                 intel_dp->compliance_test_active = 1;
4287                         else
4288                                 intel_dp->compliance_test_active = 0;
4289                 }
4290         }
4291 out:
4292         kfree(input_buffer);
4293         if (status < 0)
4294                 return status;
4295
4296         *offp += len;
4297         return len;
4298 }
4299
4300 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4301 {
4302         struct drm_device *dev = m->private;
4303         struct drm_connector *connector;
4304         struct list_head *connector_list = &dev->mode_config.connector_list;
4305         struct intel_dp *intel_dp;
4306
4307         list_for_each_entry(connector, connector_list, head) {
4308
4309                 if (connector->connector_type !=
4310                     DRM_MODE_CONNECTOR_DisplayPort)
4311                         continue;
4312
4313                 if (connector->status == connector_status_connected &&
4314                     connector->encoder != NULL) {
4315                         intel_dp = enc_to_intel_dp(connector->encoder);
4316                         if (intel_dp->compliance_test_active)
4317                                 seq_puts(m, "1");
4318                         else
4319                                 seq_puts(m, "0");
4320                 } else
4321                         seq_puts(m, "0");
4322         }
4323
4324         return 0;
4325 }
4326
4327 static int i915_displayport_test_active_open(struct inode *inode,
4328                                        struct file *file)
4329 {
4330         struct drm_device *dev = inode->i_private;
4331
4332         return single_open(file, i915_displayport_test_active_show, dev);
4333 }
4334
4335 static const struct file_operations i915_displayport_test_active_fops = {
4336         .owner = THIS_MODULE,
4337         .open = i915_displayport_test_active_open,
4338         .read = seq_read,
4339         .llseek = seq_lseek,
4340         .release = single_release,
4341         .write = i915_displayport_test_active_write
4342 };
4343
4344 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4345 {
4346         struct drm_device *dev = m->private;
4347         struct drm_connector *connector;
4348         struct list_head *connector_list = &dev->mode_config.connector_list;
4349         struct intel_dp *intel_dp;
4350
4351         list_for_each_entry(connector, connector_list, head) {
4352
4353                 if (connector->connector_type !=
4354                     DRM_MODE_CONNECTOR_DisplayPort)
4355                         continue;
4356
4357                 if (connector->status == connector_status_connected &&
4358                     connector->encoder != NULL) {
4359                         intel_dp = enc_to_intel_dp(connector->encoder);
4360                         seq_printf(m, "%lx", intel_dp->compliance_test_data);
4361                 } else
4362                         seq_puts(m, "0");
4363         }
4364
4365         return 0;
4366 }
4367 static int i915_displayport_test_data_open(struct inode *inode,
4368                                        struct file *file)
4369 {
4370         struct drm_device *dev = inode->i_private;
4371
4372         return single_open(file, i915_displayport_test_data_show, dev);
4373 }
4374
4375 static const struct file_operations i915_displayport_test_data_fops = {
4376         .owner = THIS_MODULE,
4377         .open = i915_displayport_test_data_open,
4378         .read = seq_read,
4379         .llseek = seq_lseek,
4380         .release = single_release
4381 };
4382
4383 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4384 {
4385         struct drm_device *dev = m->private;
4386         struct drm_connector *connector;
4387         struct list_head *connector_list = &dev->mode_config.connector_list;
4388         struct intel_dp *intel_dp;
4389
4390         list_for_each_entry(connector, connector_list, head) {
4391
4392                 if (connector->connector_type !=
4393                     DRM_MODE_CONNECTOR_DisplayPort)
4394                         continue;
4395
4396                 if (connector->status == connector_status_connected &&
4397                     connector->encoder != NULL) {
4398                         intel_dp = enc_to_intel_dp(connector->encoder);
4399                         seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4400                 } else
4401                         seq_puts(m, "0");
4402         }
4403
4404         return 0;
4405 }
4406
4407 static int i915_displayport_test_type_open(struct inode *inode,
4408                                        struct file *file)
4409 {
4410         struct drm_device *dev = inode->i_private;
4411
4412         return single_open(file, i915_displayport_test_type_show, dev);
4413 }
4414
4415 static const struct file_operations i915_displayport_test_type_fops = {
4416         .owner = THIS_MODULE,
4417         .open = i915_displayport_test_type_open,
4418         .read = seq_read,
4419         .llseek = seq_lseek,
4420         .release = single_release
4421 };
4422
4423 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
4424 {
4425         struct drm_device *dev = m->private;
4426         int level;
4427         int num_levels;
4428
4429         if (IS_CHERRYVIEW(dev))
4430                 num_levels = 3;
4431         else if (IS_VALLEYVIEW(dev))
4432                 num_levels = 1;
4433         else
4434                 num_levels = ilk_wm_max_level(dev) + 1;
4435
4436         drm_modeset_lock_all(dev);
4437
4438         for (level = 0; level < num_levels; level++) {
4439                 unsigned int latency = wm[level];
4440
4441                 /*
4442                  * - WM1+ latency values in 0.5us units
4443                  * - latencies are in us on gen9/vlv/chv
4444                  */
4445                 if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev))
4446                         latency *= 10;
4447                 else if (level > 0)
4448                         latency *= 5;
4449
4450                 seq_printf(m, "WM%d %u (%u.%u usec)\n",
4451                            level, wm[level], latency / 10, latency % 10);
4452         }
4453
4454         drm_modeset_unlock_all(dev);
4455 }
4456
4457 static int pri_wm_latency_show(struct seq_file *m, void *data)
4458 {
4459         struct drm_device *dev = m->private;
4460         struct drm_i915_private *dev_priv = dev->dev_private;
4461         const uint16_t *latencies;
4462
4463         if (INTEL_INFO(dev)->gen >= 9)
4464                 latencies = dev_priv->wm.skl_latency;
4465         else
4466                 latencies = to_i915(dev)->wm.pri_latency;
4467
4468         wm_latency_show(m, latencies);
4469
4470         return 0;
4471 }
4472
4473 static int spr_wm_latency_show(struct seq_file *m, void *data)
4474 {
4475         struct drm_device *dev = m->private;
4476         struct drm_i915_private *dev_priv = dev->dev_private;
4477         const uint16_t *latencies;
4478
4479         if (INTEL_INFO(dev)->gen >= 9)
4480                 latencies = dev_priv->wm.skl_latency;
4481         else
4482                 latencies = to_i915(dev)->wm.spr_latency;
4483
4484         wm_latency_show(m, latencies);
4485
4486         return 0;
4487 }
4488
4489 static int cur_wm_latency_show(struct seq_file *m, void *data)
4490 {
4491         struct drm_device *dev = m->private;
4492         struct drm_i915_private *dev_priv = dev->dev_private;
4493         const uint16_t *latencies;
4494
4495         if (INTEL_INFO(dev)->gen >= 9)
4496                 latencies = dev_priv->wm.skl_latency;
4497         else
4498                 latencies = to_i915(dev)->wm.cur_latency;
4499
4500         wm_latency_show(m, latencies);
4501
4502         return 0;
4503 }
4504
4505 static int pri_wm_latency_open(struct inode *inode, struct file *file)
4506 {
4507         struct drm_device *dev = inode->i_private;
4508
4509         if (INTEL_INFO(dev)->gen < 5)
4510                 return -ENODEV;
4511
4512         return single_open(file, pri_wm_latency_show, dev);
4513 }
4514
4515 static int spr_wm_latency_open(struct inode *inode, struct file *file)
4516 {
4517         struct drm_device *dev = inode->i_private;
4518
4519         if (HAS_GMCH_DISPLAY(dev))
4520                 return -ENODEV;
4521
4522         return single_open(file, spr_wm_latency_show, dev);
4523 }
4524
4525 static int cur_wm_latency_open(struct inode *inode, struct file *file)
4526 {
4527         struct drm_device *dev = inode->i_private;
4528
4529         if (HAS_GMCH_DISPLAY(dev))
4530                 return -ENODEV;
4531
4532         return single_open(file, cur_wm_latency_show, dev);
4533 }
4534
4535 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
4536                                 size_t len, loff_t *offp, uint16_t wm[8])
4537 {
4538         struct seq_file *m = file->private_data;
4539         struct drm_device *dev = m->private;
4540         uint16_t new[8] = { 0 };
4541         int num_levels;
4542         int level;
4543         int ret;
4544         char tmp[32];
4545
4546         if (IS_CHERRYVIEW(dev))
4547                 num_levels = 3;
4548         else if (IS_VALLEYVIEW(dev))
4549                 num_levels = 1;
4550         else
4551                 num_levels = ilk_wm_max_level(dev) + 1;
4552
4553         if (len >= sizeof(tmp))
4554                 return -EINVAL;
4555
4556         if (copy_from_user(tmp, ubuf, len))
4557                 return -EFAULT;
4558
4559         tmp[len] = '\0';
4560
4561         ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4562                      &new[0], &new[1], &new[2], &new[3],
4563                      &new[4], &new[5], &new[6], &new[7]);
4564         if (ret != num_levels)
4565                 return -EINVAL;
4566
4567         drm_modeset_lock_all(dev);
4568
4569         for (level = 0; level < num_levels; level++)
4570                 wm[level] = new[level];
4571
4572         drm_modeset_unlock_all(dev);
4573
4574         return len;
4575 }
4576
4577
4578 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4579                                     size_t len, loff_t *offp)
4580 {
4581         struct seq_file *m = file->private_data;
4582         struct drm_device *dev = m->private;
4583         struct drm_i915_private *dev_priv = dev->dev_private;
4584         uint16_t *latencies;
4585
4586         if (INTEL_INFO(dev)->gen >= 9)
4587                 latencies = dev_priv->wm.skl_latency;
4588         else
4589                 latencies = to_i915(dev)->wm.pri_latency;
4590
4591         return wm_latency_write(file, ubuf, len, offp, latencies);
4592 }
4593
4594 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4595                                     size_t len, loff_t *offp)
4596 {
4597         struct seq_file *m = file->private_data;
4598         struct drm_device *dev = m->private;
4599         struct drm_i915_private *dev_priv = dev->dev_private;
4600         uint16_t *latencies;
4601
4602         if (INTEL_INFO(dev)->gen >= 9)
4603                 latencies = dev_priv->wm.skl_latency;
4604         else
4605                 latencies = to_i915(dev)->wm.spr_latency;
4606
4607         return wm_latency_write(file, ubuf, len, offp, latencies);
4608 }
4609
4610 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4611                                     size_t len, loff_t *offp)
4612 {
4613         struct seq_file *m = file->private_data;
4614         struct drm_device *dev = m->private;
4615         struct drm_i915_private *dev_priv = dev->dev_private;
4616         uint16_t *latencies;
4617
4618         if (INTEL_INFO(dev)->gen >= 9)
4619                 latencies = dev_priv->wm.skl_latency;
4620         else
4621                 latencies = to_i915(dev)->wm.cur_latency;
4622
4623         return wm_latency_write(file, ubuf, len, offp, latencies);
4624 }
4625
4626 static const struct file_operations i915_pri_wm_latency_fops = {
4627         .owner = THIS_MODULE,
4628         .open = pri_wm_latency_open,
4629         .read = seq_read,
4630         .llseek = seq_lseek,
4631         .release = single_release,
4632         .write = pri_wm_latency_write
4633 };
4634
4635 static const struct file_operations i915_spr_wm_latency_fops = {
4636         .owner = THIS_MODULE,
4637         .open = spr_wm_latency_open,
4638         .read = seq_read,
4639         .llseek = seq_lseek,
4640         .release = single_release,
4641         .write = spr_wm_latency_write
4642 };
4643
4644 static const struct file_operations i915_cur_wm_latency_fops = {
4645         .owner = THIS_MODULE,
4646         .open = cur_wm_latency_open,
4647         .read = seq_read,
4648         .llseek = seq_lseek,
4649         .release = single_release,
4650         .write = cur_wm_latency_write
4651 };
4652
4653 static int
4654 i915_wedged_get(void *data, u64 *val)
4655 {
4656         struct drm_device *dev = data;
4657         struct drm_i915_private *dev_priv = dev->dev_private;
4658
4659         *val = atomic_read(&dev_priv->gpu_error.reset_counter);
4660
4661         return 0;
4662 }
4663
4664 static int
4665 i915_wedged_set(void *data, u64 val)
4666 {
4667         struct drm_device *dev = data;
4668         struct drm_i915_private *dev_priv = dev->dev_private;
4669
4670         /*
4671          * There is no safeguard against this debugfs entry colliding
4672          * with the hangcheck calling same i915_handle_error() in
4673          * parallel, causing an explosion. For now we assume that the
4674          * test harness is responsible enough not to inject gpu hangs
4675          * while it is writing to 'i915_wedged'
4676          */
4677
4678         if (i915_reset_in_progress(&dev_priv->gpu_error))
4679                 return -EAGAIN;
4680
4681         intel_runtime_pm_get(dev_priv);
4682
4683         i915_handle_error(dev, val,
4684                           "Manually setting wedged to %llu", val);
4685
4686         intel_runtime_pm_put(dev_priv);
4687
4688         return 0;
4689 }
4690
4691 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4692                         i915_wedged_get, i915_wedged_set,
4693                         "%llu\n");
4694
4695 static int
4696 i915_ring_stop_get(void *data, u64 *val)
4697 {
4698         struct drm_device *dev = data;
4699         struct drm_i915_private *dev_priv = dev->dev_private;
4700
4701         *val = dev_priv->gpu_error.stop_rings;
4702
4703         return 0;
4704 }
4705
4706 static int
4707 i915_ring_stop_set(void *data, u64 val)
4708 {
4709         struct drm_device *dev = data;
4710         struct drm_i915_private *dev_priv = dev->dev_private;
4711         int ret;
4712
4713         DRM_DEBUG_DRIVER("Stopping rings 0x%08llx\n", val);
4714
4715         ret = mutex_lock_interruptible(&dev->struct_mutex);
4716         if (ret)
4717                 return ret;
4718
4719         dev_priv->gpu_error.stop_rings = val;
4720         mutex_unlock(&dev->struct_mutex);
4721
4722         return 0;
4723 }
4724
4725 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_stop_fops,
4726                         i915_ring_stop_get, i915_ring_stop_set,
4727                         "0x%08llx\n");
4728
4729 static int
4730 i915_ring_missed_irq_get(void *data, u64 *val)
4731 {
4732         struct drm_device *dev = data;
4733         struct drm_i915_private *dev_priv = dev->dev_private;
4734
4735         *val = dev_priv->gpu_error.missed_irq_rings;
4736         return 0;
4737 }
4738
4739 static int
4740 i915_ring_missed_irq_set(void *data, u64 val)
4741 {
4742         struct drm_device *dev = data;
4743         struct drm_i915_private *dev_priv = dev->dev_private;
4744         int ret;
4745
4746         /* Lock against concurrent debugfs callers */
4747         ret = mutex_lock_interruptible(&dev->struct_mutex);
4748         if (ret)
4749                 return ret;
4750         dev_priv->gpu_error.missed_irq_rings = val;
4751         mutex_unlock(&dev->struct_mutex);
4752
4753         return 0;
4754 }
4755
4756 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4757                         i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4758                         "0x%08llx\n");
4759
4760 static int
4761 i915_ring_test_irq_get(void *data, u64 *val)
4762 {
4763         struct drm_device *dev = data;
4764         struct drm_i915_private *dev_priv = dev->dev_private;
4765
4766         *val = dev_priv->gpu_error.test_irq_rings;
4767
4768         return 0;
4769 }
4770
4771 static int
4772 i915_ring_test_irq_set(void *data, u64 val)
4773 {
4774         struct drm_device *dev = data;
4775         struct drm_i915_private *dev_priv = dev->dev_private;
4776         int ret;
4777
4778         DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4779
4780         /* Lock against concurrent debugfs callers */
4781         ret = mutex_lock_interruptible(&dev->struct_mutex);
4782         if (ret)
4783                 return ret;
4784
4785         dev_priv->gpu_error.test_irq_rings = val;
4786         mutex_unlock(&dev->struct_mutex);
4787
4788         return 0;
4789 }
4790
4791 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4792                         i915_ring_test_irq_get, i915_ring_test_irq_set,
4793                         "0x%08llx\n");
4794
4795 #define DROP_UNBOUND 0x1
4796 #define DROP_BOUND 0x2
4797 #define DROP_RETIRE 0x4
4798 #define DROP_ACTIVE 0x8
4799 #define DROP_ALL (DROP_UNBOUND | \
4800                   DROP_BOUND | \
4801                   DROP_RETIRE | \
4802                   DROP_ACTIVE)
4803 static int
4804 i915_drop_caches_get(void *data, u64 *val)
4805 {
4806         *val = DROP_ALL;
4807
4808         return 0;
4809 }
4810
4811 static int
4812 i915_drop_caches_set(void *data, u64 val)
4813 {
4814         struct drm_device *dev = data;
4815         struct drm_i915_private *dev_priv = dev->dev_private;
4816         int ret;
4817
4818         DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4819
4820         /* No need to check and wait for gpu resets, only libdrm auto-restarts
4821          * on ioctls on -EAGAIN. */
4822         ret = mutex_lock_interruptible(&dev->struct_mutex);
4823         if (ret)
4824                 return ret;
4825
4826         if (val & DROP_ACTIVE) {
4827                 ret = i915_gpu_idle(dev);
4828                 if (ret)
4829                         goto unlock;
4830         }
4831
4832         if (val & (DROP_RETIRE | DROP_ACTIVE))
4833                 i915_gem_retire_requests(dev);
4834
4835         if (val & DROP_BOUND)
4836                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4837
4838         if (val & DROP_UNBOUND)
4839                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4840
4841 unlock:
4842         mutex_unlock(&dev->struct_mutex);
4843
4844         return ret;
4845 }
4846
4847 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4848                         i915_drop_caches_get, i915_drop_caches_set,
4849                         "0x%08llx\n");
4850
4851 static int
4852 i915_max_freq_get(void *data, u64 *val)
4853 {
4854         struct drm_device *dev = data;
4855         struct drm_i915_private *dev_priv = dev->dev_private;
4856         int ret;
4857
4858         if (INTEL_INFO(dev)->gen < 6)
4859                 return -ENODEV;
4860
4861         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4862
4863         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4864         if (ret)
4865                 return ret;
4866
4867         *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4868         mutex_unlock(&dev_priv->rps.hw_lock);
4869
4870         return 0;
4871 }
4872
4873 static int
4874 i915_max_freq_set(void *data, u64 val)
4875 {
4876         struct drm_device *dev = data;
4877         struct drm_i915_private *dev_priv = dev->dev_private;
4878         u32 hw_max, hw_min;
4879         int ret;
4880
4881         if (INTEL_INFO(dev)->gen < 6)
4882                 return -ENODEV;
4883
4884         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4885
4886         DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4887
4888         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4889         if (ret)
4890                 return ret;
4891
4892         /*
4893          * Turbo will still be enabled, but won't go above the set value.
4894          */
4895         val = intel_freq_opcode(dev_priv, val);
4896
4897         hw_max = dev_priv->rps.max_freq;
4898         hw_min = dev_priv->rps.min_freq;
4899
4900         if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4901                 mutex_unlock(&dev_priv->rps.hw_lock);
4902                 return -EINVAL;
4903         }
4904
4905         dev_priv->rps.max_freq_softlimit = val;
4906
4907         intel_set_rps(dev, val);
4908
4909         mutex_unlock(&dev_priv->rps.hw_lock);
4910
4911         return 0;
4912 }
4913
4914 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
4915                         i915_max_freq_get, i915_max_freq_set,
4916                         "%llu\n");
4917
4918 static int
4919 i915_min_freq_get(void *data, u64 *val)
4920 {
4921         struct drm_device *dev = data;
4922         struct drm_i915_private *dev_priv = dev->dev_private;
4923         int ret;
4924
4925         if (INTEL_INFO(dev)->gen < 6)
4926                 return -ENODEV;
4927
4928         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4929
4930         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4931         if (ret)
4932                 return ret;
4933
4934         *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
4935         mutex_unlock(&dev_priv->rps.hw_lock);
4936
4937         return 0;
4938 }
4939
4940 static int
4941 i915_min_freq_set(void *data, u64 val)
4942 {
4943         struct drm_device *dev = data;
4944         struct drm_i915_private *dev_priv = dev->dev_private;
4945         u32 hw_max, hw_min;
4946         int ret;
4947
4948         if (INTEL_INFO(dev)->gen < 6)
4949                 return -ENODEV;
4950
4951         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
4952
4953         DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
4954
4955         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4956         if (ret)
4957                 return ret;
4958
4959         /*
4960          * Turbo will still be enabled, but won't go below the set value.
4961          */
4962         val = intel_freq_opcode(dev_priv, val);
4963
4964         hw_max = dev_priv->rps.max_freq;
4965         hw_min = dev_priv->rps.min_freq;
4966
4967         if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
4968                 mutex_unlock(&dev_priv->rps.hw_lock);
4969                 return -EINVAL;
4970         }
4971
4972         dev_priv->rps.min_freq_softlimit = val;
4973
4974         intel_set_rps(dev, val);
4975
4976         mutex_unlock(&dev_priv->rps.hw_lock);
4977
4978         return 0;
4979 }
4980
4981 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
4982                         i915_min_freq_get, i915_min_freq_set,
4983                         "%llu\n");
4984
4985 static int
4986 i915_cache_sharing_get(void *data, u64 *val)
4987 {
4988         struct drm_device *dev = data;
4989         struct drm_i915_private *dev_priv = dev->dev_private;
4990         u32 snpcr;
4991         int ret;
4992
4993         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
4994                 return -ENODEV;
4995
4996         ret = mutex_lock_interruptible(&dev->struct_mutex);
4997         if (ret)
4998                 return ret;
4999         intel_runtime_pm_get(dev_priv);
5000
5001         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5002
5003         intel_runtime_pm_put(dev_priv);
5004         mutex_unlock(&dev_priv->dev->struct_mutex);
5005
5006         *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
5007
5008         return 0;
5009 }
5010
5011 static int
5012 i915_cache_sharing_set(void *data, u64 val)
5013 {
5014         struct drm_device *dev = data;
5015         struct drm_i915_private *dev_priv = dev->dev_private;
5016         u32 snpcr;
5017
5018         if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5019                 return -ENODEV;
5020
5021         if (val > 3)
5022                 return -EINVAL;
5023
5024         intel_runtime_pm_get(dev_priv);
5025         DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
5026
5027         /* Update the cache sharing policy here as well */
5028         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5029         snpcr &= ~GEN6_MBC_SNPCR_MASK;
5030         snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
5031         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5032
5033         intel_runtime_pm_put(dev_priv);
5034         return 0;
5035 }
5036
5037 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
5038                         i915_cache_sharing_get, i915_cache_sharing_set,
5039                         "%llu\n");
5040
5041 struct sseu_dev_status {
5042         unsigned int slice_total;
5043         unsigned int subslice_total;
5044         unsigned int subslice_per_slice;
5045         unsigned int eu_total;
5046         unsigned int eu_per_subslice;
5047 };
5048
5049 static void cherryview_sseu_device_status(struct drm_device *dev,
5050                                           struct sseu_dev_status *stat)
5051 {
5052         struct drm_i915_private *dev_priv = dev->dev_private;
5053         int ss_max = 2;
5054         int ss;
5055         u32 sig1[ss_max], sig2[ss_max];
5056
5057         sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
5058         sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
5059         sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
5060         sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
5061
5062         for (ss = 0; ss < ss_max; ss++) {
5063                 unsigned int eu_cnt;
5064
5065                 if (sig1[ss] & CHV_SS_PG_ENABLE)
5066                         /* skip disabled subslice */
5067                         continue;
5068
5069                 stat->slice_total = 1;
5070                 stat->subslice_per_slice++;
5071                 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
5072                          ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
5073                          ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
5074                          ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
5075                 stat->eu_total += eu_cnt;
5076                 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
5077         }
5078         stat->subslice_total = stat->subslice_per_slice;
5079 }
5080
5081 static void gen9_sseu_device_status(struct drm_device *dev,
5082                                     struct sseu_dev_status *stat)
5083 {
5084         struct drm_i915_private *dev_priv = dev->dev_private;
5085         int s_max = 3, ss_max = 4;
5086         int s, ss;
5087         u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
5088
5089         /* BXT has a single slice and at most 3 subslices. */
5090         if (IS_BROXTON(dev)) {
5091                 s_max = 1;
5092                 ss_max = 3;
5093         }
5094
5095         for (s = 0; s < s_max; s++) {
5096                 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
5097                 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
5098                 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
5099         }
5100
5101         eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
5102                      GEN9_PGCTL_SSA_EU19_ACK |
5103                      GEN9_PGCTL_SSA_EU210_ACK |
5104                      GEN9_PGCTL_SSA_EU311_ACK;
5105         eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
5106                      GEN9_PGCTL_SSB_EU19_ACK |
5107                      GEN9_PGCTL_SSB_EU210_ACK |
5108                      GEN9_PGCTL_SSB_EU311_ACK;
5109
5110         for (s = 0; s < s_max; s++) {
5111                 unsigned int ss_cnt = 0;
5112
5113                 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
5114                         /* skip disabled slice */
5115                         continue;
5116
5117                 stat->slice_total++;
5118
5119                 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
5120                         ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
5121
5122                 for (ss = 0; ss < ss_max; ss++) {
5123                         unsigned int eu_cnt;
5124
5125                         if (IS_BROXTON(dev) &&
5126                             !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
5127                                 /* skip disabled subslice */
5128                                 continue;
5129
5130                         if (IS_BROXTON(dev))
5131                                 ss_cnt++;
5132
5133                         eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
5134                                                eu_mask[ss%2]);
5135                         stat->eu_total += eu_cnt;
5136                         stat->eu_per_subslice = max(stat->eu_per_subslice,
5137                                                     eu_cnt);
5138                 }
5139
5140                 stat->subslice_total += ss_cnt;
5141                 stat->subslice_per_slice = max(stat->subslice_per_slice,
5142                                                ss_cnt);
5143         }
5144 }
5145
5146 static void broadwell_sseu_device_status(struct drm_device *dev,
5147                                          struct sseu_dev_status *stat)
5148 {
5149         struct drm_i915_private *dev_priv = dev->dev_private;
5150         int s;
5151         u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
5152
5153         stat->slice_total = hweight32(slice_info & GEN8_LSLICESTAT_MASK);
5154
5155         if (stat->slice_total) {
5156                 stat->subslice_per_slice = INTEL_INFO(dev)->subslice_per_slice;
5157                 stat->subslice_total = stat->slice_total *
5158                                        stat->subslice_per_slice;
5159                 stat->eu_per_subslice = INTEL_INFO(dev)->eu_per_subslice;
5160                 stat->eu_total = stat->eu_per_subslice * stat->subslice_total;
5161
5162                 /* subtract fused off EU(s) from enabled slice(s) */
5163                 for (s = 0; s < stat->slice_total; s++) {
5164                         u8 subslice_7eu = INTEL_INFO(dev)->subslice_7eu[s];
5165
5166                         stat->eu_total -= hweight8(subslice_7eu);
5167                 }
5168         }
5169 }
5170
5171 static int i915_sseu_status(struct seq_file *m, void *unused)
5172 {
5173         struct drm_info_node *node = (struct drm_info_node *) m->private;
5174         struct drm_device *dev = node->minor->dev;
5175         struct sseu_dev_status stat;
5176
5177         if (INTEL_INFO(dev)->gen < 8)
5178                 return -ENODEV;
5179
5180         seq_puts(m, "SSEU Device Info\n");
5181         seq_printf(m, "  Available Slice Total: %u\n",
5182                    INTEL_INFO(dev)->slice_total);
5183         seq_printf(m, "  Available Subslice Total: %u\n",
5184                    INTEL_INFO(dev)->subslice_total);
5185         seq_printf(m, "  Available Subslice Per Slice: %u\n",
5186                    INTEL_INFO(dev)->subslice_per_slice);
5187         seq_printf(m, "  Available EU Total: %u\n",
5188                    INTEL_INFO(dev)->eu_total);
5189         seq_printf(m, "  Available EU Per Subslice: %u\n",
5190                    INTEL_INFO(dev)->eu_per_subslice);
5191         seq_printf(m, "  Has Slice Power Gating: %s\n",
5192                    yesno(INTEL_INFO(dev)->has_slice_pg));
5193         seq_printf(m, "  Has Subslice Power Gating: %s\n",
5194                    yesno(INTEL_INFO(dev)->has_subslice_pg));
5195         seq_printf(m, "  Has EU Power Gating: %s\n",
5196                    yesno(INTEL_INFO(dev)->has_eu_pg));
5197
5198         seq_puts(m, "SSEU Device Status\n");
5199         memset(&stat, 0, sizeof(stat));
5200         if (IS_CHERRYVIEW(dev)) {
5201                 cherryview_sseu_device_status(dev, &stat);
5202         } else if (IS_BROADWELL(dev)) {
5203                 broadwell_sseu_device_status(dev, &stat);
5204         } else if (INTEL_INFO(dev)->gen >= 9) {
5205                 gen9_sseu_device_status(dev, &stat);
5206         }
5207         seq_printf(m, "  Enabled Slice Total: %u\n",
5208                    stat.slice_total);
5209         seq_printf(m, "  Enabled Subslice Total: %u\n",
5210                    stat.subslice_total);
5211         seq_printf(m, "  Enabled Subslice Per Slice: %u\n",
5212                    stat.subslice_per_slice);
5213         seq_printf(m, "  Enabled EU Total: %u\n",
5214                    stat.eu_total);
5215         seq_printf(m, "  Enabled EU Per Subslice: %u\n",
5216                    stat.eu_per_subslice);
5217
5218         return 0;
5219 }
5220
5221 static int i915_forcewake_open(struct inode *inode, struct file *file)
5222 {
5223         struct drm_device *dev = inode->i_private;
5224         struct drm_i915_private *dev_priv = dev->dev_private;
5225
5226         if (INTEL_INFO(dev)->gen < 6)
5227                 return 0;
5228
5229         intel_runtime_pm_get(dev_priv);
5230         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5231
5232         return 0;
5233 }
5234
5235 static int i915_forcewake_release(struct inode *inode, struct file *file)
5236 {
5237         struct drm_device *dev = inode->i_private;
5238         struct drm_i915_private *dev_priv = dev->dev_private;
5239
5240         if (INTEL_INFO(dev)->gen < 6)
5241                 return 0;
5242
5243         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5244         intel_runtime_pm_put(dev_priv);
5245
5246         return 0;
5247 }
5248
5249 static const struct file_operations i915_forcewake_fops = {
5250         .owner = THIS_MODULE,
5251         .open = i915_forcewake_open,
5252         .release = i915_forcewake_release,
5253 };
5254
5255 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5256 {
5257         struct drm_device *dev = minor->dev;
5258         struct dentry *ent;
5259
5260         ent = debugfs_create_file("i915_forcewake_user",
5261                                   S_IRUSR,
5262                                   root, dev,
5263                                   &i915_forcewake_fops);
5264         if (!ent)
5265                 return -ENOMEM;
5266
5267         return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
5268 }
5269
5270 static int i915_debugfs_create(struct dentry *root,
5271                                struct drm_minor *minor,
5272                                const char *name,
5273                                const struct file_operations *fops)
5274 {
5275         struct drm_device *dev = minor->dev;
5276         struct dentry *ent;
5277
5278         ent = debugfs_create_file(name,
5279                                   S_IRUGO | S_IWUSR,
5280                                   root, dev,
5281                                   fops);
5282         if (!ent)
5283                 return -ENOMEM;
5284
5285         return drm_add_fake_info_node(minor, ent, fops);
5286 }
5287
5288 static const struct drm_info_list i915_debugfs_list[] = {
5289         {"i915_capabilities", i915_capabilities, 0},
5290         {"i915_gem_objects", i915_gem_object_info, 0},
5291         {"i915_gem_gtt", i915_gem_gtt_info, 0},
5292         {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
5293         {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
5294         {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
5295         {"i915_gem_stolen", i915_gem_stolen_list_info },
5296         {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
5297         {"i915_gem_request", i915_gem_request_info, 0},
5298         {"i915_gem_seqno", i915_gem_seqno_info, 0},
5299         {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
5300         {"i915_gem_interrupt", i915_interrupt_info, 0},
5301         {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5302         {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5303         {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
5304         {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
5305         {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
5306         {"i915_guc_info", i915_guc_info, 0},
5307         {"i915_guc_load_status", i915_guc_load_status_info, 0},
5308         {"i915_guc_log_dump", i915_guc_log_dump, 0},
5309         {"i915_frequency_info", i915_frequency_info, 0},
5310         {"i915_hangcheck_info", i915_hangcheck_info, 0},
5311         {"i915_drpc_info", i915_drpc_info, 0},
5312         {"i915_emon_status", i915_emon_status, 0},
5313         {"i915_ring_freq_table", i915_ring_freq_table, 0},
5314         {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
5315         {"i915_fbc_status", i915_fbc_status, 0},
5316         {"i915_ips_status", i915_ips_status, 0},
5317         {"i915_sr_status", i915_sr_status, 0},
5318         {"i915_opregion", i915_opregion, 0},
5319         {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
5320         {"i915_context_status", i915_context_status, 0},
5321         {"i915_dump_lrc", i915_dump_lrc, 0},
5322         {"i915_execlists", i915_execlists, 0},
5323         {"i915_forcewake_domains", i915_forcewake_domains, 0},
5324         {"i915_swizzle_info", i915_swizzle_info, 0},
5325         {"i915_ppgtt_info", i915_ppgtt_info, 0},
5326         {"i915_llc", i915_llc, 0},
5327         {"i915_edp_psr_status", i915_edp_psr_status, 0},
5328         {"i915_sink_crc_eDP1", i915_sink_crc, 0},
5329         {"i915_energy_uJ", i915_energy_uJ, 0},
5330         {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
5331         {"i915_power_domain_info", i915_power_domain_info, 0},
5332         {"i915_dmc_info", i915_dmc_info, 0},
5333         {"i915_display_info", i915_display_info, 0},
5334         {"i915_semaphore_status", i915_semaphore_status, 0},
5335         {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
5336         {"i915_dp_mst_info", i915_dp_mst_info, 0},
5337         {"i915_wa_registers", i915_wa_registers, 0},
5338         {"i915_ddb_info", i915_ddb_info, 0},
5339         {"i915_sseu_status", i915_sseu_status, 0},
5340         {"i915_drrs_status", i915_drrs_status, 0},
5341         {"i915_rps_boost_info", i915_rps_boost_info, 0},
5342 };
5343 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5344
5345 static const struct i915_debugfs_files {
5346         const char *name;
5347         const struct file_operations *fops;
5348 } i915_debugfs_files[] = {
5349         {"i915_wedged", &i915_wedged_fops},
5350         {"i915_max_freq", &i915_max_freq_fops},
5351         {"i915_min_freq", &i915_min_freq_fops},
5352         {"i915_cache_sharing", &i915_cache_sharing_fops},
5353         {"i915_ring_stop", &i915_ring_stop_fops},
5354         {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5355         {"i915_ring_test_irq", &i915_ring_test_irq_fops},
5356         {"i915_gem_drop_caches", &i915_drop_caches_fops},
5357         {"i915_error_state", &i915_error_state_fops},
5358         {"i915_next_seqno", &i915_next_seqno_fops},
5359         {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
5360         {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5361         {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5362         {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
5363         {"i915_fbc_false_color", &i915_fbc_fc_fops},
5364         {"i915_dp_test_data", &i915_displayport_test_data_fops},
5365         {"i915_dp_test_type", &i915_displayport_test_type_fops},
5366         {"i915_dp_test_active", &i915_displayport_test_active_fops}
5367 };
5368
5369 void intel_display_crc_init(struct drm_device *dev)
5370 {
5371         struct drm_i915_private *dev_priv = dev->dev_private;
5372         enum pipe pipe;
5373
5374         for_each_pipe(dev_priv, pipe) {
5375                 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
5376
5377                 pipe_crc->opened = false;
5378                 spin_lock_init(&pipe_crc->lock);
5379                 init_waitqueue_head(&pipe_crc->wq);
5380         }
5381 }
5382
5383 int i915_debugfs_init(struct drm_minor *minor)
5384 {
5385         int ret, i;
5386
5387         ret = i915_forcewake_create(minor->debugfs_root, minor);
5388         if (ret)
5389                 return ret;
5390
5391         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5392                 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5393                 if (ret)
5394                         return ret;
5395         }
5396
5397         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5398                 ret = i915_debugfs_create(minor->debugfs_root, minor,
5399                                           i915_debugfs_files[i].name,
5400                                           i915_debugfs_files[i].fops);
5401                 if (ret)
5402                         return ret;
5403         }
5404
5405         return drm_debugfs_create_files(i915_debugfs_list,
5406                                         I915_DEBUGFS_ENTRIES,
5407                                         minor->debugfs_root, minor);
5408 }
5409
5410 void i915_debugfs_cleanup(struct drm_minor *minor)
5411 {
5412         int i;
5413
5414         drm_debugfs_remove_files(i915_debugfs_list,
5415                                  I915_DEBUGFS_ENTRIES, minor);
5416
5417         drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
5418                                  1, minor);
5419
5420         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5421                 struct drm_info_list *info_list =
5422                         (struct drm_info_list *)&i915_pipe_crc_data[i];
5423
5424                 drm_debugfs_remove_files(info_list, 1, minor);
5425         }
5426
5427         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5428                 struct drm_info_list *info_list =
5429                         (struct drm_info_list *) i915_debugfs_files[i].fops;
5430
5431                 drm_debugfs_remove_files(info_list, 1, minor);
5432         }
5433 }
5434
5435 struct dpcd_block {
5436         /* DPCD dump start address. */
5437         unsigned int offset;
5438         /* DPCD dump end address, inclusive. If unset, .size will be used. */
5439         unsigned int end;
5440         /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5441         size_t size;
5442         /* Only valid for eDP. */
5443         bool edp;
5444 };
5445
5446 static const struct dpcd_block i915_dpcd_debug[] = {
5447         { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5448         { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5449         { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5450         { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5451         { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5452         { .offset = DP_SET_POWER },
5453         { .offset = DP_EDP_DPCD_REV },
5454         { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5455         { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5456         { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5457 };
5458
5459 static int i915_dpcd_show(struct seq_file *m, void *data)
5460 {
5461         struct drm_connector *connector = m->private;
5462         struct intel_dp *intel_dp =
5463                 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5464         uint8_t buf[16];
5465         ssize_t err;
5466         int i;
5467
5468         if (connector->status != connector_status_connected)
5469                 return -ENODEV;
5470
5471         for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5472                 const struct dpcd_block *b = &i915_dpcd_debug[i];
5473                 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5474
5475                 if (b->edp &&
5476                     connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5477                         continue;
5478
5479                 /* low tech for now */
5480                 if (WARN_ON(size > sizeof(buf)))
5481                         continue;
5482
5483                 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5484                 if (err <= 0) {
5485                         DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5486                                   size, b->offset, err);
5487                         continue;
5488                 }
5489
5490                 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
5491         }
5492
5493         return 0;
5494 }
5495
5496 static int i915_dpcd_open(struct inode *inode, struct file *file)
5497 {
5498         return single_open(file, i915_dpcd_show, inode->i_private);
5499 }
5500
5501 static const struct file_operations i915_dpcd_fops = {
5502         .owner = THIS_MODULE,
5503         .open = i915_dpcd_open,
5504         .read = seq_read,
5505         .llseek = seq_lseek,
5506         .release = single_release,
5507 };
5508
5509 /**
5510  * i915_debugfs_connector_add - add i915 specific connector debugfs files
5511  * @connector: pointer to a registered drm_connector
5512  *
5513  * Cleanup will be done by drm_connector_unregister() through a call to
5514  * drm_debugfs_connector_remove().
5515  *
5516  * Returns 0 on success, negative error codes on error.
5517  */
5518 int i915_debugfs_connector_add(struct drm_connector *connector)
5519 {
5520         struct dentry *root = connector->debugfs_entry;
5521
5522         /* The connector must have been registered beforehands. */
5523         if (!root)
5524                 return -ENODEV;
5525
5526         if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5527             connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5528                 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,
5529                                     &i915_dpcd_fops);
5530
5531         return 0;
5532 }