2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
29 #include <linux/seq_file.h>
30 #include <linux/circ_buf.h>
31 #include <linux/ctype.h>
32 #include <linux/debugfs.h>
33 #include <linux/slab.h>
34 #include <linux/export.h>
35 #include <linux/list_sort.h>
36 #include <asm/msr-index.h>
38 #include "intel_drv.h"
39 #include "intel_ringbuffer.h"
40 #include <drm/i915_drm.h>
49 /* As the drm_debugfs_init() routines are called before dev->dev_private is
50 * allocated we need to hook into the minor for release. */
52 drm_add_fake_info_node(struct drm_minor *minor,
56 struct drm_info_node *node;
58 node = kmalloc(sizeof(*node), GFP_KERNEL);
66 node->info_ent = (void *) key;
68 mutex_lock(&minor->debugfs_lock);
69 list_add(&node->list, &minor->debugfs_list);
70 mutex_unlock(&minor->debugfs_lock);
75 static int i915_capabilities(struct seq_file *m, void *data)
77 struct drm_info_node *node = m->private;
78 struct drm_device *dev = node->minor->dev;
79 const struct intel_device_info *info = INTEL_INFO(dev);
81 seq_printf(m, "gen: %d\n", info->gen);
82 seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
83 #define PRINT_FLAG(x) seq_printf(m, #x ": %s\n", yesno(info->x))
84 #define SEP_SEMICOLON ;
85 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_SEMICOLON);
92 static char get_active_flag(struct drm_i915_gem_object *obj)
94 return obj->active ? '*' : ' ';
97 static char get_pin_flag(struct drm_i915_gem_object *obj)
99 return obj->pin_display ? 'p' : ' ';
102 static char get_tiling_flag(struct drm_i915_gem_object *obj)
104 switch (obj->tiling_mode) {
106 case I915_TILING_NONE: return ' ';
107 case I915_TILING_X: return 'X';
108 case I915_TILING_Y: return 'Y';
112 static char get_global_flag(struct drm_i915_gem_object *obj)
114 return i915_gem_obj_to_ggtt(obj) ? 'g' : ' ';
117 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
119 return obj->mapping ? 'M' : ' ';
122 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
125 struct i915_vma *vma;
127 list_for_each_entry(vma, &obj->vma_list, obj_link) {
128 if (vma->is_ggtt && drm_mm_node_allocated(&vma->node))
129 size += vma->node.size;
136 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
138 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
139 struct intel_engine_cs *engine;
140 struct i915_vma *vma;
142 enum intel_engine_id id;
144 lockdep_assert_held(&obj->base.dev->struct_mutex);
146 seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x [ ",
148 get_active_flag(obj),
150 get_tiling_flag(obj),
151 get_global_flag(obj),
152 get_pin_mapped_flag(obj),
153 obj->base.size / 1024,
154 obj->base.read_domains,
155 obj->base.write_domain);
156 for_each_engine_id(engine, dev_priv, id)
158 i915_gem_active_get_seqno(&obj->last_read[id],
159 &obj->base.dev->struct_mutex));
160 seq_printf(m, "] %x %x%s%s%s",
161 i915_gem_active_get_seqno(&obj->last_write,
162 &obj->base.dev->struct_mutex),
163 i915_gem_active_get_seqno(&obj->last_fence,
164 &obj->base.dev->struct_mutex),
165 i915_cache_level_str(to_i915(obj->base.dev), obj->cache_level),
166 obj->dirty ? " dirty" : "",
167 obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
169 seq_printf(m, " (name: %d)", obj->base.name);
170 list_for_each_entry(vma, &obj->vma_list, obj_link) {
171 if (vma->pin_count > 0)
174 seq_printf(m, " (pinned x %d)", pin_count);
175 if (obj->pin_display)
176 seq_printf(m, " (display)");
177 if (obj->fence_reg != I915_FENCE_REG_NONE)
178 seq_printf(m, " (fence: %d)", obj->fence_reg);
179 list_for_each_entry(vma, &obj->vma_list, obj_link) {
180 if (!drm_mm_node_allocated(&vma->node))
183 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
184 vma->is_ggtt ? "g" : "pp",
185 vma->node.start, vma->node.size);
187 seq_printf(m, ", type: %u", vma->ggtt_view.type);
191 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
192 if (obj->pin_display || obj->fault_mappable) {
194 if (obj->pin_display)
196 if (obj->fault_mappable)
199 seq_printf(m, " (%s mappable)", s);
202 engine = i915_gem_active_get_engine(&obj->last_write,
203 &obj->base.dev->struct_mutex);
205 seq_printf(m, " (%s)", engine->name);
207 if (obj->frontbuffer_bits)
208 seq_printf(m, " (frontbuffer: 0x%03x)", obj->frontbuffer_bits);
211 static int i915_gem_object_list_info(struct seq_file *m, void *data)
213 struct drm_info_node *node = m->private;
214 uintptr_t list = (uintptr_t) node->info_ent->data;
215 struct list_head *head;
216 struct drm_device *dev = node->minor->dev;
217 struct drm_i915_private *dev_priv = to_i915(dev);
218 struct i915_ggtt *ggtt = &dev_priv->ggtt;
219 struct i915_vma *vma;
220 u64 total_obj_size, total_gtt_size;
223 ret = mutex_lock_interruptible(&dev->struct_mutex);
227 /* FIXME: the user of this interface might want more than just GGTT */
230 seq_puts(m, "Active:\n");
231 head = &ggtt->base.active_list;
234 seq_puts(m, "Inactive:\n");
235 head = &ggtt->base.inactive_list;
238 mutex_unlock(&dev->struct_mutex);
242 total_obj_size = total_gtt_size = count = 0;
243 list_for_each_entry(vma, head, vm_link) {
245 describe_obj(m, vma->obj);
247 total_obj_size += vma->obj->base.size;
248 total_gtt_size += vma->node.size;
251 mutex_unlock(&dev->struct_mutex);
253 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
254 count, total_obj_size, total_gtt_size);
258 static int obj_rank_by_stolen(void *priv,
259 struct list_head *A, struct list_head *B)
261 struct drm_i915_gem_object *a =
262 container_of(A, struct drm_i915_gem_object, obj_exec_link);
263 struct drm_i915_gem_object *b =
264 container_of(B, struct drm_i915_gem_object, obj_exec_link);
266 if (a->stolen->start < b->stolen->start)
268 if (a->stolen->start > b->stolen->start)
273 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
275 struct drm_info_node *node = m->private;
276 struct drm_device *dev = node->minor->dev;
277 struct drm_i915_private *dev_priv = to_i915(dev);
278 struct drm_i915_gem_object *obj;
279 u64 total_obj_size, total_gtt_size;
283 ret = mutex_lock_interruptible(&dev->struct_mutex);
287 total_obj_size = total_gtt_size = count = 0;
288 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
289 if (obj->stolen == NULL)
292 list_add(&obj->obj_exec_link, &stolen);
294 total_obj_size += obj->base.size;
295 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
298 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
299 if (obj->stolen == NULL)
302 list_add(&obj->obj_exec_link, &stolen);
304 total_obj_size += obj->base.size;
307 list_sort(NULL, &stolen, obj_rank_by_stolen);
308 seq_puts(m, "Stolen:\n");
309 while (!list_empty(&stolen)) {
310 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
312 describe_obj(m, obj);
314 list_del_init(&obj->obj_exec_link);
316 mutex_unlock(&dev->struct_mutex);
318 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
319 count, total_obj_size, total_gtt_size);
323 #define count_objects(list, member) do { \
324 list_for_each_entry(obj, list, member) { \
325 size += i915_gem_obj_total_ggtt_size(obj); \
327 if (obj->map_and_fenceable) { \
328 mappable_size += i915_gem_obj_ggtt_size(obj); \
335 struct drm_i915_file_private *file_priv;
339 u64 active, inactive;
342 static int per_file_stats(int id, void *ptr, void *data)
344 struct drm_i915_gem_object *obj = ptr;
345 struct file_stats *stats = data;
346 struct i915_vma *vma;
349 stats->total += obj->base.size;
350 if (!obj->bind_count)
351 stats->unbound += obj->base.size;
352 if (obj->base.name || obj->base.dma_buf)
353 stats->shared += obj->base.size;
355 list_for_each_entry(vma, &obj->vma_list, obj_link) {
356 if (!drm_mm_node_allocated(&vma->node))
360 stats->global += vma->node.size;
362 struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm);
364 if (ppgtt->base.file != stats->file_priv)
368 if (obj->active) /* XXX per-vma statistic */
369 stats->active += vma->node.size;
371 stats->inactive += vma->node.size;
377 #define print_file_stats(m, name, stats) do { \
379 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
390 static void print_batch_pool_stats(struct seq_file *m,
391 struct drm_i915_private *dev_priv)
393 struct drm_i915_gem_object *obj;
394 struct file_stats stats;
395 struct intel_engine_cs *engine;
398 memset(&stats, 0, sizeof(stats));
400 for_each_engine(engine, dev_priv) {
401 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
402 list_for_each_entry(obj,
403 &engine->batch_pool.cache_list[j],
405 per_file_stats(0, obj, &stats);
409 print_file_stats(m, "[k]batch pool", stats);
412 static int per_file_ctx_stats(int id, void *ptr, void *data)
414 struct i915_gem_context *ctx = ptr;
417 for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) {
418 if (ctx->engine[n].state)
419 per_file_stats(0, ctx->engine[n].state, data);
420 if (ctx->engine[n].ring)
421 per_file_stats(0, ctx->engine[n].ring->obj, data);
427 static void print_context_stats(struct seq_file *m,
428 struct drm_i915_private *dev_priv)
430 struct file_stats stats;
431 struct drm_file *file;
433 memset(&stats, 0, sizeof(stats));
435 mutex_lock(&dev_priv->drm.struct_mutex);
436 if (dev_priv->kernel_context)
437 per_file_ctx_stats(0, dev_priv->kernel_context, &stats);
439 list_for_each_entry(file, &dev_priv->drm.filelist, lhead) {
440 struct drm_i915_file_private *fpriv = file->driver_priv;
441 idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats);
443 mutex_unlock(&dev_priv->drm.struct_mutex);
445 print_file_stats(m, "[k]contexts", stats);
448 #define count_vmas(list, member) do { \
449 list_for_each_entry(vma, list, member) { \
450 size += i915_gem_obj_total_ggtt_size(vma->obj); \
452 if (vma->obj->map_and_fenceable) { \
453 mappable_size += i915_gem_obj_ggtt_size(vma->obj); \
459 static int i915_gem_object_info(struct seq_file *m, void* data)
461 struct drm_info_node *node = m->private;
462 struct drm_device *dev = node->minor->dev;
463 struct drm_i915_private *dev_priv = to_i915(dev);
464 struct i915_ggtt *ggtt = &dev_priv->ggtt;
465 u32 count, mappable_count, purgeable_count;
466 u64 size, mappable_size, purgeable_size;
467 unsigned long pin_mapped_count = 0, pin_mapped_purgeable_count = 0;
468 u64 pin_mapped_size = 0, pin_mapped_purgeable_size = 0;
469 struct drm_i915_gem_object *obj;
470 struct drm_file *file;
471 struct i915_vma *vma;
474 ret = mutex_lock_interruptible(&dev->struct_mutex);
478 seq_printf(m, "%u objects, %zu bytes\n",
479 dev_priv->mm.object_count,
480 dev_priv->mm.object_memory);
482 size = count = mappable_size = mappable_count = 0;
483 count_objects(&dev_priv->mm.bound_list, global_list);
484 seq_printf(m, "%u [%u] objects, %llu [%llu] bytes in gtt\n",
485 count, mappable_count, size, mappable_size);
487 size = count = mappable_size = mappable_count = 0;
488 count_vmas(&ggtt->base.active_list, vm_link);
489 seq_printf(m, " %u [%u] active objects, %llu [%llu] bytes\n",
490 count, mappable_count, size, mappable_size);
492 size = count = mappable_size = mappable_count = 0;
493 count_vmas(&ggtt->base.inactive_list, vm_link);
494 seq_printf(m, " %u [%u] inactive objects, %llu [%llu] bytes\n",
495 count, mappable_count, size, mappable_size);
497 size = count = purgeable_size = purgeable_count = 0;
498 list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
499 size += obj->base.size, ++count;
500 if (obj->madv == I915_MADV_DONTNEED)
501 purgeable_size += obj->base.size, ++purgeable_count;
504 pin_mapped_size += obj->base.size;
505 if (obj->pages_pin_count == 0) {
506 pin_mapped_purgeable_count++;
507 pin_mapped_purgeable_size += obj->base.size;
511 seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
513 size = count = mappable_size = mappable_count = 0;
514 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
515 if (obj->fault_mappable) {
516 size += i915_gem_obj_ggtt_size(obj);
519 if (obj->pin_display) {
520 mappable_size += i915_gem_obj_ggtt_size(obj);
523 if (obj->madv == I915_MADV_DONTNEED) {
524 purgeable_size += obj->base.size;
529 pin_mapped_size += obj->base.size;
530 if (obj->pages_pin_count == 0) {
531 pin_mapped_purgeable_count++;
532 pin_mapped_purgeable_size += obj->base.size;
536 seq_printf(m, "%u purgeable objects, %llu bytes\n",
537 purgeable_count, purgeable_size);
538 seq_printf(m, "%u pinned mappable objects, %llu bytes\n",
539 mappable_count, mappable_size);
540 seq_printf(m, "%u fault mappable objects, %llu bytes\n",
543 "%lu [%lu] pin mapped objects, %llu [%llu] bytes [purgeable]\n",
544 pin_mapped_count, pin_mapped_purgeable_count,
545 pin_mapped_size, pin_mapped_purgeable_size);
547 seq_printf(m, "%llu [%llu] gtt total\n",
548 ggtt->base.total, ggtt->mappable_end - ggtt->base.start);
551 print_batch_pool_stats(m, dev_priv);
552 mutex_unlock(&dev->struct_mutex);
554 mutex_lock(&dev->filelist_mutex);
555 print_context_stats(m, dev_priv);
556 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
557 struct file_stats stats;
558 struct task_struct *task;
560 memset(&stats, 0, sizeof(stats));
561 stats.file_priv = file->driver_priv;
562 spin_lock(&file->table_lock);
563 idr_for_each(&file->object_idr, per_file_stats, &stats);
564 spin_unlock(&file->table_lock);
566 * Although we have a valid reference on file->pid, that does
567 * not guarantee that the task_struct who called get_pid() is
568 * still alive (e.g. get_pid(current) => fork() => exit()).
569 * Therefore, we need to protect this ->comm access using RCU.
572 task = pid_task(file->pid, PIDTYPE_PID);
573 print_file_stats(m, task ? task->comm : "<unknown>", stats);
576 mutex_unlock(&dev->filelist_mutex);
581 static int i915_gem_gtt_info(struct seq_file *m, void *data)
583 struct drm_info_node *node = m->private;
584 struct drm_device *dev = node->minor->dev;
585 uintptr_t list = (uintptr_t) node->info_ent->data;
586 struct drm_i915_private *dev_priv = to_i915(dev);
587 struct drm_i915_gem_object *obj;
588 u64 total_obj_size, total_gtt_size;
591 ret = mutex_lock_interruptible(&dev->struct_mutex);
595 total_obj_size = total_gtt_size = count = 0;
596 list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
597 if (list == PINNED_LIST && !i915_gem_obj_is_pinned(obj))
601 describe_obj(m, obj);
603 total_obj_size += obj->base.size;
604 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
608 mutex_unlock(&dev->struct_mutex);
610 seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
611 count, total_obj_size, total_gtt_size);
616 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
618 struct drm_info_node *node = m->private;
619 struct drm_device *dev = node->minor->dev;
620 struct drm_i915_private *dev_priv = to_i915(dev);
621 struct intel_crtc *crtc;
624 ret = mutex_lock_interruptible(&dev->struct_mutex);
628 for_each_intel_crtc(dev, crtc) {
629 const char pipe = pipe_name(crtc->pipe);
630 const char plane = plane_name(crtc->plane);
631 struct intel_flip_work *work;
633 spin_lock_irq(&dev->event_lock);
634 work = crtc->flip_work;
636 seq_printf(m, "No flip due on pipe %c (plane %c)\n",
642 pending = atomic_read(&work->pending);
644 seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n",
647 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
650 if (work->flip_queued_req) {
651 struct intel_engine_cs *engine = i915_gem_request_get_engine(work->flip_queued_req);
653 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
655 i915_gem_request_get_seqno(work->flip_queued_req),
656 dev_priv->next_seqno,
657 intel_engine_get_seqno(engine),
658 i915_gem_request_completed(work->flip_queued_req));
660 seq_printf(m, "Flip not associated with any ring\n");
661 seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
662 work->flip_queued_vblank,
663 work->flip_ready_vblank,
664 intel_crtc_get_vblank_counter(crtc));
665 seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
667 if (INTEL_INFO(dev)->gen >= 4)
668 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
670 addr = I915_READ(DSPADDR(crtc->plane));
671 seq_printf(m, "Current scanout address 0x%08x\n", addr);
673 if (work->pending_flip_obj) {
674 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
675 seq_printf(m, "MMIO update completed? %d\n", addr == work->gtt_offset);
678 spin_unlock_irq(&dev->event_lock);
681 mutex_unlock(&dev->struct_mutex);
686 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
688 struct drm_info_node *node = m->private;
689 struct drm_device *dev = node->minor->dev;
690 struct drm_i915_private *dev_priv = to_i915(dev);
691 struct drm_i915_gem_object *obj;
692 struct intel_engine_cs *engine;
696 ret = mutex_lock_interruptible(&dev->struct_mutex);
700 for_each_engine(engine, dev_priv) {
701 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
705 list_for_each_entry(obj,
706 &engine->batch_pool.cache_list[j],
709 seq_printf(m, "%s cache[%d]: %d objects\n",
710 engine->name, j, count);
712 list_for_each_entry(obj,
713 &engine->batch_pool.cache_list[j],
716 describe_obj(m, obj);
724 seq_printf(m, "total: %d\n", total);
726 mutex_unlock(&dev->struct_mutex);
731 static int i915_gem_request_info(struct seq_file *m, void *data)
733 struct drm_info_node *node = m->private;
734 struct drm_device *dev = node->minor->dev;
735 struct drm_i915_private *dev_priv = to_i915(dev);
736 struct intel_engine_cs *engine;
737 struct drm_i915_gem_request *req;
740 ret = mutex_lock_interruptible(&dev->struct_mutex);
745 for_each_engine(engine, dev_priv) {
749 list_for_each_entry(req, &engine->request_list, link)
754 seq_printf(m, "%s requests: %d\n", engine->name, count);
755 list_for_each_entry(req, &engine->request_list, link) {
756 struct task_struct *task;
761 task = pid_task(req->pid, PIDTYPE_PID);
762 seq_printf(m, " %x @ %d: %s [%d]\n",
764 (int) (jiffies - req->emitted_jiffies),
765 task ? task->comm : "<unknown>",
766 task ? task->pid : -1);
772 mutex_unlock(&dev->struct_mutex);
775 seq_puts(m, "No requests\n");
780 static void i915_ring_seqno_info(struct seq_file *m,
781 struct intel_engine_cs *engine)
783 struct intel_breadcrumbs *b = &engine->breadcrumbs;
786 seq_printf(m, "Current sequence (%s): %x\n",
787 engine->name, intel_engine_get_seqno(engine));
788 seq_printf(m, "Current user interrupts (%s): %lx\n",
789 engine->name, READ_ONCE(engine->breadcrumbs.irq_wakeups));
792 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
793 struct intel_wait *w = container_of(rb, typeof(*w), node);
795 seq_printf(m, "Waiting (%s): %s [%d] on %x\n",
796 engine->name, w->tsk->comm, w->tsk->pid, w->seqno);
798 spin_unlock(&b->lock);
801 static int i915_gem_seqno_info(struct seq_file *m, void *data)
803 struct drm_info_node *node = m->private;
804 struct drm_device *dev = node->minor->dev;
805 struct drm_i915_private *dev_priv = to_i915(dev);
806 struct intel_engine_cs *engine;
809 ret = mutex_lock_interruptible(&dev->struct_mutex);
812 intel_runtime_pm_get(dev_priv);
814 for_each_engine(engine, dev_priv)
815 i915_ring_seqno_info(m, engine);
817 intel_runtime_pm_put(dev_priv);
818 mutex_unlock(&dev->struct_mutex);
824 static int i915_interrupt_info(struct seq_file *m, void *data)
826 struct drm_info_node *node = m->private;
827 struct drm_device *dev = node->minor->dev;
828 struct drm_i915_private *dev_priv = to_i915(dev);
829 struct intel_engine_cs *engine;
832 ret = mutex_lock_interruptible(&dev->struct_mutex);
835 intel_runtime_pm_get(dev_priv);
837 if (IS_CHERRYVIEW(dev)) {
838 seq_printf(m, "Master Interrupt Control:\t%08x\n",
839 I915_READ(GEN8_MASTER_IRQ));
841 seq_printf(m, "Display IER:\t%08x\n",
843 seq_printf(m, "Display IIR:\t%08x\n",
845 seq_printf(m, "Display IIR_RW:\t%08x\n",
846 I915_READ(VLV_IIR_RW));
847 seq_printf(m, "Display IMR:\t%08x\n",
849 for_each_pipe(dev_priv, pipe)
850 seq_printf(m, "Pipe %c stat:\t%08x\n",
852 I915_READ(PIPESTAT(pipe)));
854 seq_printf(m, "Port hotplug:\t%08x\n",
855 I915_READ(PORT_HOTPLUG_EN));
856 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
857 I915_READ(VLV_DPFLIPSTAT));
858 seq_printf(m, "DPINVGTT:\t%08x\n",
859 I915_READ(DPINVGTT));
861 for (i = 0; i < 4; i++) {
862 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
863 i, I915_READ(GEN8_GT_IMR(i)));
864 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
865 i, I915_READ(GEN8_GT_IIR(i)));
866 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
867 i, I915_READ(GEN8_GT_IER(i)));
870 seq_printf(m, "PCU interrupt mask:\t%08x\n",
871 I915_READ(GEN8_PCU_IMR));
872 seq_printf(m, "PCU interrupt identity:\t%08x\n",
873 I915_READ(GEN8_PCU_IIR));
874 seq_printf(m, "PCU interrupt enable:\t%08x\n",
875 I915_READ(GEN8_PCU_IER));
876 } else if (INTEL_INFO(dev)->gen >= 8) {
877 seq_printf(m, "Master Interrupt Control:\t%08x\n",
878 I915_READ(GEN8_MASTER_IRQ));
880 for (i = 0; i < 4; i++) {
881 seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
882 i, I915_READ(GEN8_GT_IMR(i)));
883 seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
884 i, I915_READ(GEN8_GT_IIR(i)));
885 seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
886 i, I915_READ(GEN8_GT_IER(i)));
889 for_each_pipe(dev_priv, pipe) {
890 enum intel_display_power_domain power_domain;
892 power_domain = POWER_DOMAIN_PIPE(pipe);
893 if (!intel_display_power_get_if_enabled(dev_priv,
895 seq_printf(m, "Pipe %c power disabled\n",
899 seq_printf(m, "Pipe %c IMR:\t%08x\n",
901 I915_READ(GEN8_DE_PIPE_IMR(pipe)));
902 seq_printf(m, "Pipe %c IIR:\t%08x\n",
904 I915_READ(GEN8_DE_PIPE_IIR(pipe)));
905 seq_printf(m, "Pipe %c IER:\t%08x\n",
907 I915_READ(GEN8_DE_PIPE_IER(pipe)));
909 intel_display_power_put(dev_priv, power_domain);
912 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
913 I915_READ(GEN8_DE_PORT_IMR));
914 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
915 I915_READ(GEN8_DE_PORT_IIR));
916 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
917 I915_READ(GEN8_DE_PORT_IER));
919 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
920 I915_READ(GEN8_DE_MISC_IMR));
921 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
922 I915_READ(GEN8_DE_MISC_IIR));
923 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
924 I915_READ(GEN8_DE_MISC_IER));
926 seq_printf(m, "PCU interrupt mask:\t%08x\n",
927 I915_READ(GEN8_PCU_IMR));
928 seq_printf(m, "PCU interrupt identity:\t%08x\n",
929 I915_READ(GEN8_PCU_IIR));
930 seq_printf(m, "PCU interrupt enable:\t%08x\n",
931 I915_READ(GEN8_PCU_IER));
932 } else if (IS_VALLEYVIEW(dev)) {
933 seq_printf(m, "Display IER:\t%08x\n",
935 seq_printf(m, "Display IIR:\t%08x\n",
937 seq_printf(m, "Display IIR_RW:\t%08x\n",
938 I915_READ(VLV_IIR_RW));
939 seq_printf(m, "Display IMR:\t%08x\n",
941 for_each_pipe(dev_priv, pipe)
942 seq_printf(m, "Pipe %c stat:\t%08x\n",
944 I915_READ(PIPESTAT(pipe)));
946 seq_printf(m, "Master IER:\t%08x\n",
947 I915_READ(VLV_MASTER_IER));
949 seq_printf(m, "Render IER:\t%08x\n",
951 seq_printf(m, "Render IIR:\t%08x\n",
953 seq_printf(m, "Render IMR:\t%08x\n",
956 seq_printf(m, "PM IER:\t\t%08x\n",
957 I915_READ(GEN6_PMIER));
958 seq_printf(m, "PM IIR:\t\t%08x\n",
959 I915_READ(GEN6_PMIIR));
960 seq_printf(m, "PM IMR:\t\t%08x\n",
961 I915_READ(GEN6_PMIMR));
963 seq_printf(m, "Port hotplug:\t%08x\n",
964 I915_READ(PORT_HOTPLUG_EN));
965 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
966 I915_READ(VLV_DPFLIPSTAT));
967 seq_printf(m, "DPINVGTT:\t%08x\n",
968 I915_READ(DPINVGTT));
970 } else if (!HAS_PCH_SPLIT(dev)) {
971 seq_printf(m, "Interrupt enable: %08x\n",
973 seq_printf(m, "Interrupt identity: %08x\n",
975 seq_printf(m, "Interrupt mask: %08x\n",
977 for_each_pipe(dev_priv, pipe)
978 seq_printf(m, "Pipe %c stat: %08x\n",
980 I915_READ(PIPESTAT(pipe)));
982 seq_printf(m, "North Display Interrupt enable: %08x\n",
984 seq_printf(m, "North Display Interrupt identity: %08x\n",
986 seq_printf(m, "North Display Interrupt mask: %08x\n",
988 seq_printf(m, "South Display Interrupt enable: %08x\n",
990 seq_printf(m, "South Display Interrupt identity: %08x\n",
992 seq_printf(m, "South Display Interrupt mask: %08x\n",
994 seq_printf(m, "Graphics Interrupt enable: %08x\n",
996 seq_printf(m, "Graphics Interrupt identity: %08x\n",
998 seq_printf(m, "Graphics Interrupt mask: %08x\n",
1001 for_each_engine(engine, dev_priv) {
1002 if (INTEL_INFO(dev)->gen >= 6) {
1004 "Graphics Interrupt mask (%s): %08x\n",
1005 engine->name, I915_READ_IMR(engine));
1007 i915_ring_seqno_info(m, engine);
1009 intel_runtime_pm_put(dev_priv);
1010 mutex_unlock(&dev->struct_mutex);
1015 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
1017 struct drm_info_node *node = m->private;
1018 struct drm_device *dev = node->minor->dev;
1019 struct drm_i915_private *dev_priv = to_i915(dev);
1022 ret = mutex_lock_interruptible(&dev->struct_mutex);
1026 seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
1027 for (i = 0; i < dev_priv->num_fence_regs; i++) {
1028 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
1030 seq_printf(m, "Fence %d, pin count = %d, object = ",
1031 i, dev_priv->fence_regs[i].pin_count);
1033 seq_puts(m, "unused");
1035 describe_obj(m, obj);
1039 mutex_unlock(&dev->struct_mutex);
1043 static int i915_hws_info(struct seq_file *m, void *data)
1045 struct drm_info_node *node = m->private;
1046 struct drm_device *dev = node->minor->dev;
1047 struct drm_i915_private *dev_priv = to_i915(dev);
1048 struct intel_engine_cs *engine;
1052 engine = &dev_priv->engine[(uintptr_t)node->info_ent->data];
1053 hws = engine->status_page.page_addr;
1057 for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
1058 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
1060 hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
1066 i915_error_state_write(struct file *filp,
1067 const char __user *ubuf,
1071 struct i915_error_state_file_priv *error_priv = filp->private_data;
1072 struct drm_device *dev = error_priv->dev;
1075 DRM_DEBUG_DRIVER("Resetting error state\n");
1077 ret = mutex_lock_interruptible(&dev->struct_mutex);
1081 i915_destroy_error_state(dev);
1082 mutex_unlock(&dev->struct_mutex);
1087 static int i915_error_state_open(struct inode *inode, struct file *file)
1089 struct drm_device *dev = inode->i_private;
1090 struct i915_error_state_file_priv *error_priv;
1092 error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
1096 error_priv->dev = dev;
1098 i915_error_state_get(dev, error_priv);
1100 file->private_data = error_priv;
1105 static int i915_error_state_release(struct inode *inode, struct file *file)
1107 struct i915_error_state_file_priv *error_priv = file->private_data;
1109 i915_error_state_put(error_priv);
1115 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1116 size_t count, loff_t *pos)
1118 struct i915_error_state_file_priv *error_priv = file->private_data;
1119 struct drm_i915_error_state_buf error_str;
1121 ssize_t ret_count = 0;
1124 ret = i915_error_state_buf_init(&error_str, to_i915(error_priv->dev), count, *pos);
1128 ret = i915_error_state_to_str(&error_str, error_priv);
1132 ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1139 *pos = error_str.start + ret_count;
1141 i915_error_state_buf_release(&error_str);
1142 return ret ?: ret_count;
1145 static const struct file_operations i915_error_state_fops = {
1146 .owner = THIS_MODULE,
1147 .open = i915_error_state_open,
1148 .read = i915_error_state_read,
1149 .write = i915_error_state_write,
1150 .llseek = default_llseek,
1151 .release = i915_error_state_release,
1155 i915_next_seqno_get(void *data, u64 *val)
1157 struct drm_device *dev = data;
1158 struct drm_i915_private *dev_priv = to_i915(dev);
1161 ret = mutex_lock_interruptible(&dev->struct_mutex);
1165 *val = dev_priv->next_seqno;
1166 mutex_unlock(&dev->struct_mutex);
1172 i915_next_seqno_set(void *data, u64 val)
1174 struct drm_device *dev = data;
1177 ret = mutex_lock_interruptible(&dev->struct_mutex);
1181 ret = i915_gem_set_seqno(dev, val);
1182 mutex_unlock(&dev->struct_mutex);
1187 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1188 i915_next_seqno_get, i915_next_seqno_set,
1191 static int i915_frequency_info(struct seq_file *m, void *unused)
1193 struct drm_info_node *node = m->private;
1194 struct drm_device *dev = node->minor->dev;
1195 struct drm_i915_private *dev_priv = to_i915(dev);
1198 intel_runtime_pm_get(dev_priv);
1201 u16 rgvswctl = I915_READ16(MEMSWCTL);
1202 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1204 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1205 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1206 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1208 seq_printf(m, "Current P-state: %d\n",
1209 (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1210 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1213 mutex_lock(&dev_priv->rps.hw_lock);
1214 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1215 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1216 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1218 seq_printf(m, "actual GPU freq: %d MHz\n",
1219 intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1221 seq_printf(m, "current GPU freq: %d MHz\n",
1222 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1224 seq_printf(m, "max GPU freq: %d MHz\n",
1225 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1227 seq_printf(m, "min GPU freq: %d MHz\n",
1228 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1230 seq_printf(m, "idle GPU freq: %d MHz\n",
1231 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1234 "efficient (RPe) frequency: %d MHz\n",
1235 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1236 mutex_unlock(&dev_priv->rps.hw_lock);
1237 } else if (INTEL_INFO(dev)->gen >= 6) {
1238 u32 rp_state_limits;
1241 u32 rpmodectl, rpinclimit, rpdeclimit;
1242 u32 rpstat, cagf, reqf;
1243 u32 rpupei, rpcurup, rpprevup;
1244 u32 rpdownei, rpcurdown, rpprevdown;
1245 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1248 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1249 if (IS_BROXTON(dev)) {
1250 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1251 gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1253 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1254 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1257 /* RPSTAT1 is in the GT power well */
1258 ret = mutex_lock_interruptible(&dev->struct_mutex);
1262 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1264 reqf = I915_READ(GEN6_RPNSWREQ);
1268 reqf &= ~GEN6_TURBO_DISABLE;
1269 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1274 reqf = intel_gpu_freq(dev_priv, reqf);
1276 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1277 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1278 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1280 rpstat = I915_READ(GEN6_RPSTAT1);
1281 rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
1282 rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
1283 rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
1284 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
1285 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
1286 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
1288 cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1289 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1290 cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1292 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1293 cagf = intel_gpu_freq(dev_priv, cagf);
1295 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1296 mutex_unlock(&dev->struct_mutex);
1298 if (IS_GEN6(dev) || IS_GEN7(dev)) {
1299 pm_ier = I915_READ(GEN6_PMIER);
1300 pm_imr = I915_READ(GEN6_PMIMR);
1301 pm_isr = I915_READ(GEN6_PMISR);
1302 pm_iir = I915_READ(GEN6_PMIIR);
1303 pm_mask = I915_READ(GEN6_PMINTRMSK);
1305 pm_ier = I915_READ(GEN8_GT_IER(2));
1306 pm_imr = I915_READ(GEN8_GT_IMR(2));
1307 pm_isr = I915_READ(GEN8_GT_ISR(2));
1308 pm_iir = I915_READ(GEN8_GT_IIR(2));
1309 pm_mask = I915_READ(GEN6_PMINTRMSK);
1311 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1312 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1313 seq_printf(m, "pm_intr_keep: 0x%08x\n", dev_priv->rps.pm_intr_keep);
1314 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1315 seq_printf(m, "Render p-state ratio: %d\n",
1316 (gt_perf_status & (IS_GEN9(dev) ? 0x1ff00 : 0xff00)) >> 8);
1317 seq_printf(m, "Render p-state VID: %d\n",
1318 gt_perf_status & 0xff);
1319 seq_printf(m, "Render p-state limit: %d\n",
1320 rp_state_limits & 0xff);
1321 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1322 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1323 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1324 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1325 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1326 seq_printf(m, "CAGF: %dMHz\n", cagf);
1327 seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
1328 rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei));
1329 seq_printf(m, "RP CUR UP: %d (%dus)\n",
1330 rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
1331 seq_printf(m, "RP PREV UP: %d (%dus)\n",
1332 rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
1333 seq_printf(m, "Up threshold: %d%%\n",
1334 dev_priv->rps.up_threshold);
1336 seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
1337 rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
1338 seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
1339 rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown));
1340 seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
1341 rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown));
1342 seq_printf(m, "Down threshold: %d%%\n",
1343 dev_priv->rps.down_threshold);
1345 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 0 :
1346 rp_state_cap >> 16) & 0xff;
1347 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1348 GEN9_FREQ_SCALER : 1);
1349 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1350 intel_gpu_freq(dev_priv, max_freq));
1352 max_freq = (rp_state_cap & 0xff00) >> 8;
1353 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1354 GEN9_FREQ_SCALER : 1);
1355 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1356 intel_gpu_freq(dev_priv, max_freq));
1358 max_freq = (IS_BROXTON(dev) ? rp_state_cap >> 16 :
1359 rp_state_cap >> 0) & 0xff;
1360 max_freq *= (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1361 GEN9_FREQ_SCALER : 1);
1362 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1363 intel_gpu_freq(dev_priv, max_freq));
1364 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1365 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1367 seq_printf(m, "Current freq: %d MHz\n",
1368 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1369 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1370 seq_printf(m, "Idle freq: %d MHz\n",
1371 intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1372 seq_printf(m, "Min freq: %d MHz\n",
1373 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1374 seq_printf(m, "Boost freq: %d MHz\n",
1375 intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
1376 seq_printf(m, "Max freq: %d MHz\n",
1377 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1379 "efficient (RPe) frequency: %d MHz\n",
1380 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1382 seq_puts(m, "no P-state info available\n");
1385 seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
1386 seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1387 seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1390 intel_runtime_pm_put(dev_priv);
1394 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1396 struct drm_info_node *node = m->private;
1397 struct drm_device *dev = node->minor->dev;
1398 struct drm_i915_private *dev_priv = to_i915(dev);
1399 struct intel_engine_cs *engine;
1400 u64 acthd[I915_NUM_ENGINES];
1401 u32 seqno[I915_NUM_ENGINES];
1402 u32 instdone[I915_NUM_INSTDONE_REG];
1403 enum intel_engine_id id;
1406 if (!i915.enable_hangcheck) {
1407 seq_printf(m, "Hangcheck disabled\n");
1411 intel_runtime_pm_get(dev_priv);
1413 for_each_engine_id(engine, dev_priv, id) {
1414 acthd[id] = intel_engine_get_active_head(engine);
1415 seqno[id] = intel_engine_get_seqno(engine);
1418 i915_get_extra_instdone(dev_priv, instdone);
1420 intel_runtime_pm_put(dev_priv);
1422 if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1423 seq_printf(m, "Hangcheck active, fires in %dms\n",
1424 jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1427 seq_printf(m, "Hangcheck inactive\n");
1429 for_each_engine_id(engine, dev_priv, id) {
1430 seq_printf(m, "%s:\n", engine->name);
1431 seq_printf(m, "\tseqno = %x [current %x, last %x]\n",
1432 engine->hangcheck.seqno,
1434 engine->last_submitted_seqno);
1435 seq_printf(m, "\twaiters? %d\n",
1436 intel_engine_has_waiter(engine));
1437 seq_printf(m, "\tuser interrupts = %lx [current %lx]\n",
1438 engine->hangcheck.user_interrupts,
1439 READ_ONCE(engine->breadcrumbs.irq_wakeups));
1440 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1441 (long long)engine->hangcheck.acthd,
1442 (long long)acthd[id]);
1443 seq_printf(m, "\tscore = %d\n", engine->hangcheck.score);
1444 seq_printf(m, "\taction = %d\n", engine->hangcheck.action);
1446 if (engine->id == RCS) {
1447 seq_puts(m, "\tinstdone read =");
1449 for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1450 seq_printf(m, " 0x%08x", instdone[j]);
1452 seq_puts(m, "\n\tinstdone accu =");
1454 for (j = 0; j < I915_NUM_INSTDONE_REG; j++)
1455 seq_printf(m, " 0x%08x",
1456 engine->hangcheck.instdone[j]);
1465 static int ironlake_drpc_info(struct seq_file *m)
1467 struct drm_info_node *node = m->private;
1468 struct drm_device *dev = node->minor->dev;
1469 struct drm_i915_private *dev_priv = to_i915(dev);
1470 u32 rgvmodectl, rstdbyctl;
1474 ret = mutex_lock_interruptible(&dev->struct_mutex);
1477 intel_runtime_pm_get(dev_priv);
1479 rgvmodectl = I915_READ(MEMMODECTL);
1480 rstdbyctl = I915_READ(RSTDBYCTL);
1481 crstandvid = I915_READ16(CRSTANDVID);
1483 intel_runtime_pm_put(dev_priv);
1484 mutex_unlock(&dev->struct_mutex);
1486 seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1487 seq_printf(m, "Boost freq: %d\n",
1488 (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1489 MEMMODE_BOOST_FREQ_SHIFT);
1490 seq_printf(m, "HW control enabled: %s\n",
1491 yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1492 seq_printf(m, "SW control enabled: %s\n",
1493 yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1494 seq_printf(m, "Gated voltage change: %s\n",
1495 yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1496 seq_printf(m, "Starting frequency: P%d\n",
1497 (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1498 seq_printf(m, "Max P-state: P%d\n",
1499 (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1500 seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1501 seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1502 seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1503 seq_printf(m, "Render standby enabled: %s\n",
1504 yesno(!(rstdbyctl & RCX_SW_EXIT)));
1505 seq_puts(m, "Current RS state: ");
1506 switch (rstdbyctl & RSX_STATUS_MASK) {
1508 seq_puts(m, "on\n");
1510 case RSX_STATUS_RC1:
1511 seq_puts(m, "RC1\n");
1513 case RSX_STATUS_RC1E:
1514 seq_puts(m, "RC1E\n");
1516 case RSX_STATUS_RS1:
1517 seq_puts(m, "RS1\n");
1519 case RSX_STATUS_RS2:
1520 seq_puts(m, "RS2 (RC6)\n");
1522 case RSX_STATUS_RS3:
1523 seq_puts(m, "RC3 (RC6+)\n");
1526 seq_puts(m, "unknown\n");
1533 static int i915_forcewake_domains(struct seq_file *m, void *data)
1535 struct drm_info_node *node = m->private;
1536 struct drm_device *dev = node->minor->dev;
1537 struct drm_i915_private *dev_priv = to_i915(dev);
1538 struct intel_uncore_forcewake_domain *fw_domain;
1540 spin_lock_irq(&dev_priv->uncore.lock);
1541 for_each_fw_domain(fw_domain, dev_priv) {
1542 seq_printf(m, "%s.wake_count = %u\n",
1543 intel_uncore_forcewake_domain_to_str(fw_domain->id),
1544 fw_domain->wake_count);
1546 spin_unlock_irq(&dev_priv->uncore.lock);
1551 static int vlv_drpc_info(struct seq_file *m)
1553 struct drm_info_node *node = m->private;
1554 struct drm_device *dev = node->minor->dev;
1555 struct drm_i915_private *dev_priv = to_i915(dev);
1556 u32 rpmodectl1, rcctl1, pw_status;
1558 intel_runtime_pm_get(dev_priv);
1560 pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1561 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1562 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1564 intel_runtime_pm_put(dev_priv);
1566 seq_printf(m, "Video Turbo Mode: %s\n",
1567 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1568 seq_printf(m, "Turbo enabled: %s\n",
1569 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1570 seq_printf(m, "HW control enabled: %s\n",
1571 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1572 seq_printf(m, "SW control enabled: %s\n",
1573 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1574 GEN6_RP_MEDIA_SW_MODE));
1575 seq_printf(m, "RC6 Enabled: %s\n",
1576 yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1577 GEN6_RC_CTL_EI_MODE(1))));
1578 seq_printf(m, "Render Power Well: %s\n",
1579 (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1580 seq_printf(m, "Media Power Well: %s\n",
1581 (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1583 seq_printf(m, "Render RC6 residency since boot: %u\n",
1584 I915_READ(VLV_GT_RENDER_RC6));
1585 seq_printf(m, "Media RC6 residency since boot: %u\n",
1586 I915_READ(VLV_GT_MEDIA_RC6));
1588 return i915_forcewake_domains(m, NULL);
1591 static int gen6_drpc_info(struct seq_file *m)
1593 struct drm_info_node *node = m->private;
1594 struct drm_device *dev = node->minor->dev;
1595 struct drm_i915_private *dev_priv = to_i915(dev);
1596 u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1597 u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
1598 unsigned forcewake_count;
1601 ret = mutex_lock_interruptible(&dev->struct_mutex);
1604 intel_runtime_pm_get(dev_priv);
1606 spin_lock_irq(&dev_priv->uncore.lock);
1607 forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1608 spin_unlock_irq(&dev_priv->uncore.lock);
1610 if (forcewake_count) {
1611 seq_puts(m, "RC information inaccurate because somebody "
1612 "holds a forcewake reference \n");
1614 /* NB: we cannot use forcewake, else we read the wrong values */
1615 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1617 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1620 gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1621 trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1623 rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1624 rcctl1 = I915_READ(GEN6_RC_CONTROL);
1625 if (INTEL_INFO(dev)->gen >= 9) {
1626 gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE);
1627 gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
1629 mutex_unlock(&dev->struct_mutex);
1630 mutex_lock(&dev_priv->rps.hw_lock);
1631 sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1632 mutex_unlock(&dev_priv->rps.hw_lock);
1634 intel_runtime_pm_put(dev_priv);
1636 seq_printf(m, "Video Turbo Mode: %s\n",
1637 yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1638 seq_printf(m, "HW control enabled: %s\n",
1639 yesno(rpmodectl1 & GEN6_RP_ENABLE));
1640 seq_printf(m, "SW control enabled: %s\n",
1641 yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1642 GEN6_RP_MEDIA_SW_MODE));
1643 seq_printf(m, "RC1e Enabled: %s\n",
1644 yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1645 seq_printf(m, "RC6 Enabled: %s\n",
1646 yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1647 if (INTEL_INFO(dev)->gen >= 9) {
1648 seq_printf(m, "Render Well Gating Enabled: %s\n",
1649 yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
1650 seq_printf(m, "Media Well Gating Enabled: %s\n",
1651 yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE));
1653 seq_printf(m, "Deep RC6 Enabled: %s\n",
1654 yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1655 seq_printf(m, "Deepest RC6 Enabled: %s\n",
1656 yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1657 seq_puts(m, "Current RC state: ");
1658 switch (gt_core_status & GEN6_RCn_MASK) {
1660 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1661 seq_puts(m, "Core Power Down\n");
1663 seq_puts(m, "on\n");
1666 seq_puts(m, "RC3\n");
1669 seq_puts(m, "RC6\n");
1672 seq_puts(m, "RC7\n");
1675 seq_puts(m, "Unknown\n");
1679 seq_printf(m, "Core Power Down: %s\n",
1680 yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1681 if (INTEL_INFO(dev)->gen >= 9) {
1682 seq_printf(m, "Render Power Well: %s\n",
1683 (gen9_powergate_status &
1684 GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
1685 seq_printf(m, "Media Power Well: %s\n",
1686 (gen9_powergate_status &
1687 GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
1690 /* Not exactly sure what this is */
1691 seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1692 I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1693 seq_printf(m, "RC6 residency since boot: %u\n",
1694 I915_READ(GEN6_GT_GFX_RC6));
1695 seq_printf(m, "RC6+ residency since boot: %u\n",
1696 I915_READ(GEN6_GT_GFX_RC6p));
1697 seq_printf(m, "RC6++ residency since boot: %u\n",
1698 I915_READ(GEN6_GT_GFX_RC6pp));
1700 seq_printf(m, "RC6 voltage: %dmV\n",
1701 GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1702 seq_printf(m, "RC6+ voltage: %dmV\n",
1703 GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1704 seq_printf(m, "RC6++ voltage: %dmV\n",
1705 GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1706 return i915_forcewake_domains(m, NULL);
1709 static int i915_drpc_info(struct seq_file *m, void *unused)
1711 struct drm_info_node *node = m->private;
1712 struct drm_device *dev = node->minor->dev;
1714 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
1715 return vlv_drpc_info(m);
1716 else if (INTEL_INFO(dev)->gen >= 6)
1717 return gen6_drpc_info(m);
1719 return ironlake_drpc_info(m);
1722 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1724 struct drm_info_node *node = m->private;
1725 struct drm_device *dev = node->minor->dev;
1726 struct drm_i915_private *dev_priv = to_i915(dev);
1728 seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1729 dev_priv->fb_tracking.busy_bits);
1731 seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1732 dev_priv->fb_tracking.flip_bits);
1737 static int i915_fbc_status(struct seq_file *m, void *unused)
1739 struct drm_info_node *node = m->private;
1740 struct drm_device *dev = node->minor->dev;
1741 struct drm_i915_private *dev_priv = to_i915(dev);
1743 if (!HAS_FBC(dev)) {
1744 seq_puts(m, "FBC unsupported on this chipset\n");
1748 intel_runtime_pm_get(dev_priv);
1749 mutex_lock(&dev_priv->fbc.lock);
1751 if (intel_fbc_is_active(dev_priv))
1752 seq_puts(m, "FBC enabled\n");
1754 seq_printf(m, "FBC disabled: %s\n",
1755 dev_priv->fbc.no_fbc_reason);
1757 if (INTEL_INFO(dev_priv)->gen >= 7)
1758 seq_printf(m, "Compressing: %s\n",
1759 yesno(I915_READ(FBC_STATUS2) &
1760 FBC_COMPRESSION_MASK));
1762 mutex_unlock(&dev_priv->fbc.lock);
1763 intel_runtime_pm_put(dev_priv);
1768 static int i915_fbc_fc_get(void *data, u64 *val)
1770 struct drm_device *dev = data;
1771 struct drm_i915_private *dev_priv = to_i915(dev);
1773 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1776 *val = dev_priv->fbc.false_color;
1781 static int i915_fbc_fc_set(void *data, u64 val)
1783 struct drm_device *dev = data;
1784 struct drm_i915_private *dev_priv = to_i915(dev);
1787 if (INTEL_INFO(dev)->gen < 7 || !HAS_FBC(dev))
1790 mutex_lock(&dev_priv->fbc.lock);
1792 reg = I915_READ(ILK_DPFC_CONTROL);
1793 dev_priv->fbc.false_color = val;
1795 I915_WRITE(ILK_DPFC_CONTROL, val ?
1796 (reg | FBC_CTL_FALSE_COLOR) :
1797 (reg & ~FBC_CTL_FALSE_COLOR));
1799 mutex_unlock(&dev_priv->fbc.lock);
1803 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1804 i915_fbc_fc_get, i915_fbc_fc_set,
1807 static int i915_ips_status(struct seq_file *m, void *unused)
1809 struct drm_info_node *node = m->private;
1810 struct drm_device *dev = node->minor->dev;
1811 struct drm_i915_private *dev_priv = to_i915(dev);
1813 if (!HAS_IPS(dev)) {
1814 seq_puts(m, "not supported\n");
1818 intel_runtime_pm_get(dev_priv);
1820 seq_printf(m, "Enabled by kernel parameter: %s\n",
1821 yesno(i915.enable_ips));
1823 if (INTEL_INFO(dev)->gen >= 8) {
1824 seq_puts(m, "Currently: unknown\n");
1826 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1827 seq_puts(m, "Currently: enabled\n");
1829 seq_puts(m, "Currently: disabled\n");
1832 intel_runtime_pm_put(dev_priv);
1837 static int i915_sr_status(struct seq_file *m, void *unused)
1839 struct drm_info_node *node = m->private;
1840 struct drm_device *dev = node->minor->dev;
1841 struct drm_i915_private *dev_priv = to_i915(dev);
1842 bool sr_enabled = false;
1844 intel_runtime_pm_get(dev_priv);
1846 if (HAS_PCH_SPLIT(dev))
1847 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1848 else if (IS_CRESTLINE(dev) || IS_G4X(dev) ||
1849 IS_I945G(dev) || IS_I945GM(dev))
1850 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1851 else if (IS_I915GM(dev))
1852 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1853 else if (IS_PINEVIEW(dev))
1854 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1855 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
1856 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1858 intel_runtime_pm_put(dev_priv);
1860 seq_printf(m, "self-refresh: %s\n",
1861 sr_enabled ? "enabled" : "disabled");
1866 static int i915_emon_status(struct seq_file *m, void *unused)
1868 struct drm_info_node *node = m->private;
1869 struct drm_device *dev = node->minor->dev;
1870 struct drm_i915_private *dev_priv = to_i915(dev);
1871 unsigned long temp, chipset, gfx;
1877 ret = mutex_lock_interruptible(&dev->struct_mutex);
1881 temp = i915_mch_val(dev_priv);
1882 chipset = i915_chipset_val(dev_priv);
1883 gfx = i915_gfx_val(dev_priv);
1884 mutex_unlock(&dev->struct_mutex);
1886 seq_printf(m, "GMCH temp: %ld\n", temp);
1887 seq_printf(m, "Chipset power: %ld\n", chipset);
1888 seq_printf(m, "GFX power: %ld\n", gfx);
1889 seq_printf(m, "Total power: %ld\n", chipset + gfx);
1894 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1896 struct drm_info_node *node = m->private;
1897 struct drm_device *dev = node->minor->dev;
1898 struct drm_i915_private *dev_priv = to_i915(dev);
1900 int gpu_freq, ia_freq;
1901 unsigned int max_gpu_freq, min_gpu_freq;
1903 if (!HAS_CORE_RING_FREQ(dev)) {
1904 seq_puts(m, "unsupported on this chipset\n");
1908 intel_runtime_pm_get(dev_priv);
1910 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1914 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
1915 /* Convert GT frequency to 50 HZ units */
1917 dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1919 dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1921 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1922 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1925 seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1927 for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1929 sandybridge_pcode_read(dev_priv,
1930 GEN6_PCODE_READ_MIN_FREQ_TABLE,
1932 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1933 intel_gpu_freq(dev_priv, (gpu_freq *
1934 (IS_SKYLAKE(dev) || IS_KABYLAKE(dev) ?
1935 GEN9_FREQ_SCALER : 1))),
1936 ((ia_freq >> 0) & 0xff) * 100,
1937 ((ia_freq >> 8) & 0xff) * 100);
1940 mutex_unlock(&dev_priv->rps.hw_lock);
1943 intel_runtime_pm_put(dev_priv);
1947 static int i915_opregion(struct seq_file *m, void *unused)
1949 struct drm_info_node *node = m->private;
1950 struct drm_device *dev = node->minor->dev;
1951 struct drm_i915_private *dev_priv = to_i915(dev);
1952 struct intel_opregion *opregion = &dev_priv->opregion;
1955 ret = mutex_lock_interruptible(&dev->struct_mutex);
1959 if (opregion->header)
1960 seq_write(m, opregion->header, OPREGION_SIZE);
1962 mutex_unlock(&dev->struct_mutex);
1968 static int i915_vbt(struct seq_file *m, void *unused)
1970 struct drm_info_node *node = m->private;
1971 struct drm_device *dev = node->minor->dev;
1972 struct drm_i915_private *dev_priv = to_i915(dev);
1973 struct intel_opregion *opregion = &dev_priv->opregion;
1976 seq_write(m, opregion->vbt, opregion->vbt_size);
1981 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1983 struct drm_info_node *node = m->private;
1984 struct drm_device *dev = node->minor->dev;
1985 struct intel_framebuffer *fbdev_fb = NULL;
1986 struct drm_framebuffer *drm_fb;
1989 ret = mutex_lock_interruptible(&dev->struct_mutex);
1993 #ifdef CONFIG_DRM_FBDEV_EMULATION
1994 if (to_i915(dev)->fbdev) {
1995 fbdev_fb = to_intel_framebuffer(to_i915(dev)->fbdev->helper.fb);
1997 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1998 fbdev_fb->base.width,
1999 fbdev_fb->base.height,
2000 fbdev_fb->base.depth,
2001 fbdev_fb->base.bits_per_pixel,
2002 fbdev_fb->base.modifier[0],
2003 drm_framebuffer_read_refcount(&fbdev_fb->base));
2004 describe_obj(m, fbdev_fb->obj);
2009 mutex_lock(&dev->mode_config.fb_lock);
2010 drm_for_each_fb(drm_fb, dev) {
2011 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
2015 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
2019 fb->base.bits_per_pixel,
2020 fb->base.modifier[0],
2021 drm_framebuffer_read_refcount(&fb->base));
2022 describe_obj(m, fb->obj);
2025 mutex_unlock(&dev->mode_config.fb_lock);
2026 mutex_unlock(&dev->struct_mutex);
2031 static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring)
2033 seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
2034 ring->space, ring->head, ring->tail,
2035 ring->last_retired_head);
2038 static int i915_context_status(struct seq_file *m, void *unused)
2040 struct drm_info_node *node = m->private;
2041 struct drm_device *dev = node->minor->dev;
2042 struct drm_i915_private *dev_priv = to_i915(dev);
2043 struct intel_engine_cs *engine;
2044 struct i915_gem_context *ctx;
2047 ret = mutex_lock_interruptible(&dev->struct_mutex);
2051 list_for_each_entry(ctx, &dev_priv->context_list, link) {
2052 seq_printf(m, "HW context %u ", ctx->hw_id);
2053 if (IS_ERR(ctx->file_priv)) {
2054 seq_puts(m, "(deleted) ");
2055 } else if (ctx->file_priv) {
2056 struct pid *pid = ctx->file_priv->file->pid;
2057 struct task_struct *task;
2059 task = get_pid_task(pid, PIDTYPE_PID);
2061 seq_printf(m, "(%s [%d]) ",
2062 task->comm, task->pid);
2063 put_task_struct(task);
2066 seq_puts(m, "(kernel) ");
2069 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
2072 for_each_engine(engine, dev_priv) {
2073 struct intel_context *ce = &ctx->engine[engine->id];
2075 seq_printf(m, "%s: ", engine->name);
2076 seq_putc(m, ce->initialised ? 'I' : 'i');
2078 describe_obj(m, ce->state);
2080 describe_ctx_ring(m, ce->ring);
2087 mutex_unlock(&dev->struct_mutex);
2092 static void i915_dump_lrc_obj(struct seq_file *m,
2093 struct i915_gem_context *ctx,
2094 struct intel_engine_cs *engine)
2096 struct drm_i915_gem_object *ctx_obj = ctx->engine[engine->id].state;
2098 uint32_t *reg_state;
2100 unsigned long ggtt_offset = 0;
2102 seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id);
2104 if (ctx_obj == NULL) {
2105 seq_puts(m, "\tNot allocated\n");
2109 if (!i915_gem_obj_ggtt_bound(ctx_obj))
2110 seq_puts(m, "\tNot bound in GGTT\n");
2112 ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
2114 if (i915_gem_object_get_pages(ctx_obj)) {
2115 seq_puts(m, "\tFailed to get pages for context object\n");
2119 page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN);
2120 if (!WARN_ON(page == NULL)) {
2121 reg_state = kmap_atomic(page);
2123 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2124 seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2125 ggtt_offset + 4096 + (j * 4),
2126 reg_state[j], reg_state[j + 1],
2127 reg_state[j + 2], reg_state[j + 3]);
2129 kunmap_atomic(reg_state);
2135 static int i915_dump_lrc(struct seq_file *m, void *unused)
2137 struct drm_info_node *node = (struct drm_info_node *) m->private;
2138 struct drm_device *dev = node->minor->dev;
2139 struct drm_i915_private *dev_priv = to_i915(dev);
2140 struct intel_engine_cs *engine;
2141 struct i915_gem_context *ctx;
2144 if (!i915.enable_execlists) {
2145 seq_printf(m, "Logical Ring Contexts are disabled\n");
2149 ret = mutex_lock_interruptible(&dev->struct_mutex);
2153 list_for_each_entry(ctx, &dev_priv->context_list, link)
2154 for_each_engine(engine, dev_priv)
2155 i915_dump_lrc_obj(m, ctx, engine);
2157 mutex_unlock(&dev->struct_mutex);
2162 static int i915_execlists(struct seq_file *m, void *data)
2164 struct drm_info_node *node = (struct drm_info_node *)m->private;
2165 struct drm_device *dev = node->minor->dev;
2166 struct drm_i915_private *dev_priv = to_i915(dev);
2167 struct intel_engine_cs *engine;
2173 struct list_head *cursor;
2176 if (!i915.enable_execlists) {
2177 seq_puts(m, "Logical Ring Contexts are disabled\n");
2181 ret = mutex_lock_interruptible(&dev->struct_mutex);
2185 intel_runtime_pm_get(dev_priv);
2187 for_each_engine(engine, dev_priv) {
2188 struct drm_i915_gem_request *head_req = NULL;
2191 seq_printf(m, "%s\n", engine->name);
2193 status = I915_READ(RING_EXECLIST_STATUS_LO(engine));
2194 ctx_id = I915_READ(RING_EXECLIST_STATUS_HI(engine));
2195 seq_printf(m, "\tExeclist status: 0x%08X, context: %u\n",
2198 status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
2199 seq_printf(m, "\tStatus pointer: 0x%08X\n", status_pointer);
2201 read_pointer = engine->next_context_status_buffer;
2202 write_pointer = GEN8_CSB_WRITE_PTR(status_pointer);
2203 if (read_pointer > write_pointer)
2204 write_pointer += GEN8_CSB_ENTRIES;
2205 seq_printf(m, "\tRead pointer: 0x%08X, write pointer 0x%08X\n",
2206 read_pointer, write_pointer);
2208 for (i = 0; i < GEN8_CSB_ENTRIES; i++) {
2209 status = I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, i));
2210 ctx_id = I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, i));
2212 seq_printf(m, "\tStatus buffer %d: 0x%08X, context: %u\n",
2216 spin_lock_bh(&engine->execlist_lock);
2217 list_for_each(cursor, &engine->execlist_queue)
2219 head_req = list_first_entry_or_null(&engine->execlist_queue,
2220 struct drm_i915_gem_request,
2222 spin_unlock_bh(&engine->execlist_lock);
2224 seq_printf(m, "\t%d requests in queue\n", count);
2226 seq_printf(m, "\tHead request context: %u\n",
2227 head_req->ctx->hw_id);
2228 seq_printf(m, "\tHead request tail: %u\n",
2235 intel_runtime_pm_put(dev_priv);
2236 mutex_unlock(&dev->struct_mutex);
2241 static const char *swizzle_string(unsigned swizzle)
2244 case I915_BIT_6_SWIZZLE_NONE:
2246 case I915_BIT_6_SWIZZLE_9:
2248 case I915_BIT_6_SWIZZLE_9_10:
2249 return "bit9/bit10";
2250 case I915_BIT_6_SWIZZLE_9_11:
2251 return "bit9/bit11";
2252 case I915_BIT_6_SWIZZLE_9_10_11:
2253 return "bit9/bit10/bit11";
2254 case I915_BIT_6_SWIZZLE_9_17:
2255 return "bit9/bit17";
2256 case I915_BIT_6_SWIZZLE_9_10_17:
2257 return "bit9/bit10/bit17";
2258 case I915_BIT_6_SWIZZLE_UNKNOWN:
2265 static int i915_swizzle_info(struct seq_file *m, void *data)
2267 struct drm_info_node *node = m->private;
2268 struct drm_device *dev = node->minor->dev;
2269 struct drm_i915_private *dev_priv = to_i915(dev);
2272 ret = mutex_lock_interruptible(&dev->struct_mutex);
2275 intel_runtime_pm_get(dev_priv);
2277 seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2278 swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2279 seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2280 swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2282 if (IS_GEN3(dev) || IS_GEN4(dev)) {
2283 seq_printf(m, "DDC = 0x%08x\n",
2285 seq_printf(m, "DDC2 = 0x%08x\n",
2287 seq_printf(m, "C0DRB3 = 0x%04x\n",
2288 I915_READ16(C0DRB3));
2289 seq_printf(m, "C1DRB3 = 0x%04x\n",
2290 I915_READ16(C1DRB3));
2291 } else if (INTEL_INFO(dev)->gen >= 6) {
2292 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2293 I915_READ(MAD_DIMM_C0));
2294 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2295 I915_READ(MAD_DIMM_C1));
2296 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2297 I915_READ(MAD_DIMM_C2));
2298 seq_printf(m, "TILECTL = 0x%08x\n",
2299 I915_READ(TILECTL));
2300 if (INTEL_INFO(dev)->gen >= 8)
2301 seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2302 I915_READ(GAMTARBMODE));
2304 seq_printf(m, "ARB_MODE = 0x%08x\n",
2305 I915_READ(ARB_MODE));
2306 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2307 I915_READ(DISP_ARB_CTL));
2310 if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2311 seq_puts(m, "L-shaped memory detected\n");
2313 intel_runtime_pm_put(dev_priv);
2314 mutex_unlock(&dev->struct_mutex);
2319 static int per_file_ctx(int id, void *ptr, void *data)
2321 struct i915_gem_context *ctx = ptr;
2322 struct seq_file *m = data;
2323 struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2326 seq_printf(m, " no ppgtt for context %d\n",
2331 if (i915_gem_context_is_default(ctx))
2332 seq_puts(m, " default context:\n");
2334 seq_printf(m, " context %d:\n", ctx->user_handle);
2335 ppgtt->debug_dump(ppgtt, m);
2340 static void gen8_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2342 struct drm_i915_private *dev_priv = to_i915(dev);
2343 struct intel_engine_cs *engine;
2344 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2350 for_each_engine(engine, dev_priv) {
2351 seq_printf(m, "%s\n", engine->name);
2352 for (i = 0; i < 4; i++) {
2353 u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
2355 pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
2356 seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2361 static void gen6_ppgtt_info(struct seq_file *m, struct drm_device *dev)
2363 struct drm_i915_private *dev_priv = to_i915(dev);
2364 struct intel_engine_cs *engine;
2366 if (IS_GEN6(dev_priv))
2367 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2369 for_each_engine(engine, dev_priv) {
2370 seq_printf(m, "%s\n", engine->name);
2371 if (IS_GEN7(dev_priv))
2372 seq_printf(m, "GFX_MODE: 0x%08x\n",
2373 I915_READ(RING_MODE_GEN7(engine)));
2374 seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
2375 I915_READ(RING_PP_DIR_BASE(engine)));
2376 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
2377 I915_READ(RING_PP_DIR_BASE_READ(engine)));
2378 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
2379 I915_READ(RING_PP_DIR_DCLV(engine)));
2381 if (dev_priv->mm.aliasing_ppgtt) {
2382 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2384 seq_puts(m, "aliasing PPGTT:\n");
2385 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2387 ppgtt->debug_dump(ppgtt, m);
2390 seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2393 static int i915_ppgtt_info(struct seq_file *m, void *data)
2395 struct drm_info_node *node = m->private;
2396 struct drm_device *dev = node->minor->dev;
2397 struct drm_i915_private *dev_priv = to_i915(dev);
2398 struct drm_file *file;
2400 int ret = mutex_lock_interruptible(&dev->struct_mutex);
2403 intel_runtime_pm_get(dev_priv);
2405 if (INTEL_INFO(dev)->gen >= 8)
2406 gen8_ppgtt_info(m, dev);
2407 else if (INTEL_INFO(dev)->gen >= 6)
2408 gen6_ppgtt_info(m, dev);
2410 mutex_lock(&dev->filelist_mutex);
2411 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2412 struct drm_i915_file_private *file_priv = file->driver_priv;
2413 struct task_struct *task;
2415 task = get_pid_task(file->pid, PIDTYPE_PID);
2420 seq_printf(m, "\nproc: %s\n", task->comm);
2421 put_task_struct(task);
2422 idr_for_each(&file_priv->context_idr, per_file_ctx,
2423 (void *)(unsigned long)m);
2426 mutex_unlock(&dev->filelist_mutex);
2428 intel_runtime_pm_put(dev_priv);
2429 mutex_unlock(&dev->struct_mutex);
2434 static int count_irq_waiters(struct drm_i915_private *i915)
2436 struct intel_engine_cs *engine;
2439 for_each_engine(engine, i915)
2440 count += intel_engine_has_waiter(engine);
2445 static int i915_rps_boost_info(struct seq_file *m, void *data)
2447 struct drm_info_node *node = m->private;
2448 struct drm_device *dev = node->minor->dev;
2449 struct drm_i915_private *dev_priv = to_i915(dev);
2450 struct drm_file *file;
2452 seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2453 seq_printf(m, "GPU busy? %s [%x]\n",
2454 yesno(dev_priv->gt.awake), dev_priv->gt.active_engines);
2455 seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2456 seq_printf(m, "Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2457 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2458 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2459 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2460 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2461 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2463 mutex_lock(&dev->filelist_mutex);
2464 spin_lock(&dev_priv->rps.client_lock);
2465 list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2466 struct drm_i915_file_private *file_priv = file->driver_priv;
2467 struct task_struct *task;
2470 task = pid_task(file->pid, PIDTYPE_PID);
2471 seq_printf(m, "%s [%d]: %d boosts%s\n",
2472 task ? task->comm : "<unknown>",
2473 task ? task->pid : -1,
2474 file_priv->rps.boosts,
2475 list_empty(&file_priv->rps.link) ? "" : ", active");
2478 seq_printf(m, "Kernel (anonymous) boosts: %d\n", dev_priv->rps.boosts);
2479 spin_unlock(&dev_priv->rps.client_lock);
2480 mutex_unlock(&dev->filelist_mutex);
2485 static int i915_llc(struct seq_file *m, void *data)
2487 struct drm_info_node *node = m->private;
2488 struct drm_device *dev = node->minor->dev;
2489 struct drm_i915_private *dev_priv = to_i915(dev);
2490 const bool edram = INTEL_GEN(dev_priv) > 8;
2492 seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev)));
2493 seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
2494 intel_uncore_edram_size(dev_priv)/1024/1024);
2499 static int i915_guc_load_status_info(struct seq_file *m, void *data)
2501 struct drm_info_node *node = m->private;
2502 struct drm_i915_private *dev_priv = to_i915(node->minor->dev);
2503 struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
2506 if (!HAS_GUC_UCODE(dev_priv))
2509 seq_printf(m, "GuC firmware status:\n");
2510 seq_printf(m, "\tpath: %s\n",
2511 guc_fw->guc_fw_path);
2512 seq_printf(m, "\tfetch: %s\n",
2513 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
2514 seq_printf(m, "\tload: %s\n",
2515 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
2516 seq_printf(m, "\tversion wanted: %d.%d\n",
2517 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2518 seq_printf(m, "\tversion found: %d.%d\n",
2519 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
2520 seq_printf(m, "\theader: offset is %d; size = %d\n",
2521 guc_fw->header_offset, guc_fw->header_size);
2522 seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2523 guc_fw->ucode_offset, guc_fw->ucode_size);
2524 seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2525 guc_fw->rsa_offset, guc_fw->rsa_size);
2527 tmp = I915_READ(GUC_STATUS);
2529 seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2530 seq_printf(m, "\tBootrom status = 0x%x\n",
2531 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2532 seq_printf(m, "\tuKernel status = 0x%x\n",
2533 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2534 seq_printf(m, "\tMIA Core status = 0x%x\n",
2535 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2536 seq_puts(m, "\nScratch registers:\n");
2537 for (i = 0; i < 16; i++)
2538 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2543 static void i915_guc_client_info(struct seq_file *m,
2544 struct drm_i915_private *dev_priv,
2545 struct i915_guc_client *client)
2547 struct intel_engine_cs *engine;
2550 seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2551 client->priority, client->ctx_index, client->proc_desc_offset);
2552 seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2553 client->doorbell_id, client->doorbell_offset, client->cookie);
2554 seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2555 client->wq_size, client->wq_offset, client->wq_tail);
2557 seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space);
2558 seq_printf(m, "\tFailed to queue: %u\n", client->q_fail);
2559 seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2560 seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2562 for_each_engine(engine, dev_priv) {
2563 seq_printf(m, "\tSubmissions: %llu %s\n",
2564 client->submissions[engine->id],
2566 tot += client->submissions[engine->id];
2568 seq_printf(m, "\tTotal: %llu\n", tot);
2571 static int i915_guc_info(struct seq_file *m, void *data)
2573 struct drm_info_node *node = m->private;
2574 struct drm_device *dev = node->minor->dev;
2575 struct drm_i915_private *dev_priv = to_i915(dev);
2576 struct intel_guc guc;
2577 struct i915_guc_client client = {};
2578 struct intel_engine_cs *engine;
2581 if (!HAS_GUC_SCHED(dev_priv))
2584 if (mutex_lock_interruptible(&dev->struct_mutex))
2587 /* Take a local copy of the GuC data, so we can dump it at leisure */
2588 guc = dev_priv->guc;
2589 if (guc.execbuf_client)
2590 client = *guc.execbuf_client;
2592 mutex_unlock(&dev->struct_mutex);
2594 seq_printf(m, "Doorbell map:\n");
2595 seq_printf(m, "\t%*pb\n", GUC_MAX_DOORBELLS, guc.doorbell_bitmap);
2596 seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc.db_cacheline);
2598 seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
2599 seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
2600 seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
2601 seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
2602 seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
2604 seq_printf(m, "\nGuC submissions:\n");
2605 for_each_engine(engine, dev_priv) {
2606 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",
2607 engine->name, guc.submissions[engine->id],
2608 guc.last_seqno[engine->id]);
2609 total += guc.submissions[engine->id];
2611 seq_printf(m, "\t%s: %llu\n", "Total", total);
2613 seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
2614 i915_guc_client_info(m, dev_priv, &client);
2616 /* Add more as required ... */
2621 static int i915_guc_log_dump(struct seq_file *m, void *data)
2623 struct drm_info_node *node = m->private;
2624 struct drm_device *dev = node->minor->dev;
2625 struct drm_i915_private *dev_priv = to_i915(dev);
2626 struct drm_i915_gem_object *log_obj = dev_priv->guc.log_obj;
2633 for (pg = 0; pg < log_obj->base.size / PAGE_SIZE; pg++) {
2634 log = kmap_atomic(i915_gem_object_get_page(log_obj, pg));
2636 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2637 seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2638 *(log + i), *(log + i + 1),
2639 *(log + i + 2), *(log + i + 3));
2649 static int i915_edp_psr_status(struct seq_file *m, void *data)
2651 struct drm_info_node *node = m->private;
2652 struct drm_device *dev = node->minor->dev;
2653 struct drm_i915_private *dev_priv = to_i915(dev);
2657 bool enabled = false;
2659 if (!HAS_PSR(dev)) {
2660 seq_puts(m, "PSR not supported\n");
2664 intel_runtime_pm_get(dev_priv);
2666 mutex_lock(&dev_priv->psr.lock);
2667 seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2668 seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2669 seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2670 seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2671 seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2672 dev_priv->psr.busy_frontbuffer_bits);
2673 seq_printf(m, "Re-enable work scheduled: %s\n",
2674 yesno(work_busy(&dev_priv->psr.work.work)));
2677 enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2679 for_each_pipe(dev_priv, pipe) {
2680 stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2681 VLV_EDP_PSR_CURR_STATE_MASK;
2682 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2683 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2688 seq_printf(m, "Main link in standby mode: %s\n",
2689 yesno(dev_priv->psr.link_standby));
2691 seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2694 for_each_pipe(dev_priv, pipe) {
2695 if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2696 (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2697 seq_printf(m, " pipe %c", pipe_name(pipe));
2702 * VLV/CHV PSR has no kind of performance counter
2703 * SKL+ Perf counter is reset to 0 everytime DC state is entered
2705 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2706 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
2707 EDP_PSR_PERF_CNT_MASK;
2709 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2711 mutex_unlock(&dev_priv->psr.lock);
2713 intel_runtime_pm_put(dev_priv);
2717 static int i915_sink_crc(struct seq_file *m, void *data)
2719 struct drm_info_node *node = m->private;
2720 struct drm_device *dev = node->minor->dev;
2721 struct intel_connector *connector;
2722 struct intel_dp *intel_dp = NULL;
2726 drm_modeset_lock_all(dev);
2727 for_each_intel_connector(dev, connector) {
2728 struct drm_crtc *crtc;
2730 if (!connector->base.state->best_encoder)
2733 crtc = connector->base.state->crtc;
2734 if (!crtc->state->active)
2737 if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
2740 intel_dp = enc_to_intel_dp(connector->base.state->best_encoder);
2742 ret = intel_dp_sink_crc(intel_dp, crc);
2746 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2747 crc[0], crc[1], crc[2],
2748 crc[3], crc[4], crc[5]);
2753 drm_modeset_unlock_all(dev);
2757 static int i915_energy_uJ(struct seq_file *m, void *data)
2759 struct drm_info_node *node = m->private;
2760 struct drm_device *dev = node->minor->dev;
2761 struct drm_i915_private *dev_priv = to_i915(dev);
2765 if (INTEL_INFO(dev)->gen < 6)
2768 intel_runtime_pm_get(dev_priv);
2770 rdmsrl(MSR_RAPL_POWER_UNIT, power);
2771 power = (power & 0x1f00) >> 8;
2772 units = 1000000 / (1 << power); /* convert to uJ */
2773 power = I915_READ(MCH_SECP_NRG_STTS);
2776 intel_runtime_pm_put(dev_priv);
2778 seq_printf(m, "%llu", (long long unsigned)power);
2783 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2785 struct drm_info_node *node = m->private;
2786 struct drm_device *dev = node->minor->dev;
2787 struct drm_i915_private *dev_priv = to_i915(dev);
2789 if (!HAS_RUNTIME_PM(dev_priv))
2790 seq_puts(m, "Runtime power management not supported\n");
2792 seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
2793 seq_printf(m, "IRQs disabled: %s\n",
2794 yesno(!intel_irqs_enabled(dev_priv)));
2796 seq_printf(m, "Usage count: %d\n",
2797 atomic_read(&dev->dev->power.usage_count));
2799 seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2801 seq_printf(m, "PCI device power state: %s [%d]\n",
2802 pci_power_name(dev_priv->drm.pdev->current_state),
2803 dev_priv->drm.pdev->current_state);
2808 static int i915_power_domain_info(struct seq_file *m, void *unused)
2810 struct drm_info_node *node = m->private;
2811 struct drm_device *dev = node->minor->dev;
2812 struct drm_i915_private *dev_priv = to_i915(dev);
2813 struct i915_power_domains *power_domains = &dev_priv->power_domains;
2816 mutex_lock(&power_domains->lock);
2818 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2819 for (i = 0; i < power_domains->power_well_count; i++) {
2820 struct i915_power_well *power_well;
2821 enum intel_display_power_domain power_domain;
2823 power_well = &power_domains->power_wells[i];
2824 seq_printf(m, "%-25s %d\n", power_well->name,
2827 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2829 if (!(BIT(power_domain) & power_well->domains))
2832 seq_printf(m, " %-23s %d\n",
2833 intel_display_power_domain_str(power_domain),
2834 power_domains->domain_use_count[power_domain]);
2838 mutex_unlock(&power_domains->lock);
2843 static int i915_dmc_info(struct seq_file *m, void *unused)
2845 struct drm_info_node *node = m->private;
2846 struct drm_device *dev = node->minor->dev;
2847 struct drm_i915_private *dev_priv = to_i915(dev);
2848 struct intel_csr *csr;
2850 if (!HAS_CSR(dev)) {
2851 seq_puts(m, "not supported\n");
2855 csr = &dev_priv->csr;
2857 intel_runtime_pm_get(dev_priv);
2859 seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2860 seq_printf(m, "path: %s\n", csr->fw_path);
2862 if (!csr->dmc_payload)
2865 seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2866 CSR_VERSION_MINOR(csr->version));
2868 if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) {
2869 seq_printf(m, "DC3 -> DC5 count: %d\n",
2870 I915_READ(SKL_CSR_DC3_DC5_COUNT));
2871 seq_printf(m, "DC5 -> DC6 count: %d\n",
2872 I915_READ(SKL_CSR_DC5_DC6_COUNT));
2873 } else if (IS_BROXTON(dev) && csr->version >= CSR_VERSION(1, 4)) {
2874 seq_printf(m, "DC3 -> DC5 count: %d\n",
2875 I915_READ(BXT_CSR_DC3_DC5_COUNT));
2879 seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2880 seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2881 seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2883 intel_runtime_pm_put(dev_priv);
2888 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2889 struct drm_display_mode *mode)
2893 for (i = 0; i < tabs; i++)
2896 seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2897 mode->base.id, mode->name,
2898 mode->vrefresh, mode->clock,
2899 mode->hdisplay, mode->hsync_start,
2900 mode->hsync_end, mode->htotal,
2901 mode->vdisplay, mode->vsync_start,
2902 mode->vsync_end, mode->vtotal,
2903 mode->type, mode->flags);
2906 static void intel_encoder_info(struct seq_file *m,
2907 struct intel_crtc *intel_crtc,
2908 struct intel_encoder *intel_encoder)
2910 struct drm_info_node *node = m->private;
2911 struct drm_device *dev = node->minor->dev;
2912 struct drm_crtc *crtc = &intel_crtc->base;
2913 struct intel_connector *intel_connector;
2914 struct drm_encoder *encoder;
2916 encoder = &intel_encoder->base;
2917 seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2918 encoder->base.id, encoder->name);
2919 for_each_connector_on_encoder(dev, encoder, intel_connector) {
2920 struct drm_connector *connector = &intel_connector->base;
2921 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2924 drm_get_connector_status_name(connector->status));
2925 if (connector->status == connector_status_connected) {
2926 struct drm_display_mode *mode = &crtc->mode;
2927 seq_printf(m, ", mode:\n");
2928 intel_seq_print_mode(m, 2, mode);
2935 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2937 struct drm_info_node *node = m->private;
2938 struct drm_device *dev = node->minor->dev;
2939 struct drm_crtc *crtc = &intel_crtc->base;
2940 struct intel_encoder *intel_encoder;
2941 struct drm_plane_state *plane_state = crtc->primary->state;
2942 struct drm_framebuffer *fb = plane_state->fb;
2945 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2946 fb->base.id, plane_state->src_x >> 16,
2947 plane_state->src_y >> 16, fb->width, fb->height);
2949 seq_puts(m, "\tprimary plane disabled\n");
2950 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2951 intel_encoder_info(m, intel_crtc, intel_encoder);
2954 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2956 struct drm_display_mode *mode = panel->fixed_mode;
2958 seq_printf(m, "\tfixed mode:\n");
2959 intel_seq_print_mode(m, 2, mode);
2962 static void intel_dp_info(struct seq_file *m,
2963 struct intel_connector *intel_connector)
2965 struct intel_encoder *intel_encoder = intel_connector->encoder;
2966 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2968 seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2969 seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2970 if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
2971 intel_panel_info(m, &intel_connector->panel);
2974 static void intel_hdmi_info(struct seq_file *m,
2975 struct intel_connector *intel_connector)
2977 struct intel_encoder *intel_encoder = intel_connector->encoder;
2978 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2980 seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
2983 static void intel_lvds_info(struct seq_file *m,
2984 struct intel_connector *intel_connector)
2986 intel_panel_info(m, &intel_connector->panel);
2989 static void intel_connector_info(struct seq_file *m,
2990 struct drm_connector *connector)
2992 struct intel_connector *intel_connector = to_intel_connector(connector);
2993 struct intel_encoder *intel_encoder = intel_connector->encoder;
2994 struct drm_display_mode *mode;
2996 seq_printf(m, "connector %d: type %s, status: %s\n",
2997 connector->base.id, connector->name,
2998 drm_get_connector_status_name(connector->status));
2999 if (connector->status == connector_status_connected) {
3000 seq_printf(m, "\tname: %s\n", connector->display_info.name);
3001 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
3002 connector->display_info.width_mm,
3003 connector->display_info.height_mm);
3004 seq_printf(m, "\tsubpixel order: %s\n",
3005 drm_get_subpixel_order_name(connector->display_info.subpixel_order));
3006 seq_printf(m, "\tCEA rev: %d\n",
3007 connector->display_info.cea_rev);
3010 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
3013 switch (connector->connector_type) {
3014 case DRM_MODE_CONNECTOR_DisplayPort:
3015 case DRM_MODE_CONNECTOR_eDP:
3016 intel_dp_info(m, intel_connector);
3018 case DRM_MODE_CONNECTOR_LVDS:
3019 if (intel_encoder->type == INTEL_OUTPUT_LVDS)
3020 intel_lvds_info(m, intel_connector);
3022 case DRM_MODE_CONNECTOR_HDMIA:
3023 if (intel_encoder->type == INTEL_OUTPUT_HDMI ||
3024 intel_encoder->type == INTEL_OUTPUT_UNKNOWN)
3025 intel_hdmi_info(m, intel_connector);
3031 seq_printf(m, "\tmodes:\n");
3032 list_for_each_entry(mode, &connector->modes, head)
3033 intel_seq_print_mode(m, 2, mode);
3036 static bool cursor_active(struct drm_device *dev, int pipe)
3038 struct drm_i915_private *dev_priv = to_i915(dev);
3041 if (IS_845G(dev) || IS_I865G(dev))
3042 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
3044 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
3049 static bool cursor_position(struct drm_device *dev, int pipe, int *x, int *y)
3051 struct drm_i915_private *dev_priv = to_i915(dev);
3054 pos = I915_READ(CURPOS(pipe));
3056 *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
3057 if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
3060 *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
3061 if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
3064 return cursor_active(dev, pipe);
3067 static const char *plane_type(enum drm_plane_type type)
3070 case DRM_PLANE_TYPE_OVERLAY:
3072 case DRM_PLANE_TYPE_PRIMARY:
3074 case DRM_PLANE_TYPE_CURSOR:
3077 * Deliberately omitting default: to generate compiler warnings
3078 * when a new drm_plane_type gets added.
3085 static const char *plane_rotation(unsigned int rotation)
3087 static char buf[48];
3089 * According to doc only one DRM_ROTATE_ is allowed but this
3090 * will print them all to visualize if the values are misused
3092 snprintf(buf, sizeof(buf),
3093 "%s%s%s%s%s%s(0x%08x)",
3094 (rotation & BIT(DRM_ROTATE_0)) ? "0 " : "",
3095 (rotation & BIT(DRM_ROTATE_90)) ? "90 " : "",
3096 (rotation & BIT(DRM_ROTATE_180)) ? "180 " : "",
3097 (rotation & BIT(DRM_ROTATE_270)) ? "270 " : "",
3098 (rotation & BIT(DRM_REFLECT_X)) ? "FLIPX " : "",
3099 (rotation & BIT(DRM_REFLECT_Y)) ? "FLIPY " : "",
3105 static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3107 struct drm_info_node *node = m->private;
3108 struct drm_device *dev = node->minor->dev;
3109 struct intel_plane *intel_plane;
3111 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3112 struct drm_plane_state *state;
3113 struct drm_plane *plane = &intel_plane->base;
3115 if (!plane->state) {
3116 seq_puts(m, "plane->state is NULL!\n");
3120 state = plane->state;
3122 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3124 plane_type(intel_plane->base.type),
3125 state->crtc_x, state->crtc_y,
3126 state->crtc_w, state->crtc_h,
3127 (state->src_x >> 16),
3128 ((state->src_x & 0xffff) * 15625) >> 10,
3129 (state->src_y >> 16),
3130 ((state->src_y & 0xffff) * 15625) >> 10,
3131 (state->src_w >> 16),
3132 ((state->src_w & 0xffff) * 15625) >> 10,
3133 (state->src_h >> 16),
3134 ((state->src_h & 0xffff) * 15625) >> 10,
3135 state->fb ? drm_get_format_name(state->fb->pixel_format) : "N/A",
3136 plane_rotation(state->rotation));
3140 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3142 struct intel_crtc_state *pipe_config;
3143 int num_scalers = intel_crtc->num_scalers;
3146 pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3148 /* Not all platformas have a scaler */
3150 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3152 pipe_config->scaler_state.scaler_users,
3153 pipe_config->scaler_state.scaler_id);
3155 for (i = 0; i < SKL_NUM_SCALERS; i++) {
3156 struct intel_scaler *sc =
3157 &pipe_config->scaler_state.scalers[i];
3159 seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3160 i, yesno(sc->in_use), sc->mode);
3164 seq_puts(m, "\tNo scalers available on this platform\n");
3168 static int i915_display_info(struct seq_file *m, void *unused)
3170 struct drm_info_node *node = m->private;
3171 struct drm_device *dev = node->minor->dev;
3172 struct drm_i915_private *dev_priv = to_i915(dev);
3173 struct intel_crtc *crtc;
3174 struct drm_connector *connector;
3176 intel_runtime_pm_get(dev_priv);
3177 drm_modeset_lock_all(dev);
3178 seq_printf(m, "CRTC info\n");
3179 seq_printf(m, "---------\n");
3180 for_each_intel_crtc(dev, crtc) {
3182 struct intel_crtc_state *pipe_config;
3185 pipe_config = to_intel_crtc_state(crtc->base.state);
3187 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3188 crtc->base.base.id, pipe_name(crtc->pipe),
3189 yesno(pipe_config->base.active),
3190 pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3191 yesno(pipe_config->dither), pipe_config->pipe_bpp);
3193 if (pipe_config->base.active) {
3194 intel_crtc_info(m, crtc);
3196 active = cursor_position(dev, crtc->pipe, &x, &y);
3197 seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
3198 yesno(crtc->cursor_base),
3199 x, y, crtc->base.cursor->state->crtc_w,
3200 crtc->base.cursor->state->crtc_h,
3201 crtc->cursor_addr, yesno(active));
3202 intel_scaler_info(m, crtc);
3203 intel_plane_info(m, crtc);
3206 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3207 yesno(!crtc->cpu_fifo_underrun_disabled),
3208 yesno(!crtc->pch_fifo_underrun_disabled));
3211 seq_printf(m, "\n");
3212 seq_printf(m, "Connector info\n");
3213 seq_printf(m, "--------------\n");
3214 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3215 intel_connector_info(m, connector);
3217 drm_modeset_unlock_all(dev);
3218 intel_runtime_pm_put(dev_priv);
3223 static int i915_semaphore_status(struct seq_file *m, void *unused)
3225 struct drm_info_node *node = (struct drm_info_node *) m->private;
3226 struct drm_device *dev = node->minor->dev;
3227 struct drm_i915_private *dev_priv = to_i915(dev);
3228 struct intel_engine_cs *engine;
3229 int num_rings = hweight32(INTEL_INFO(dev)->ring_mask);
3230 enum intel_engine_id id;
3233 if (!i915.semaphores) {
3234 seq_puts(m, "Semaphores are disabled\n");
3238 ret = mutex_lock_interruptible(&dev->struct_mutex);
3241 intel_runtime_pm_get(dev_priv);
3243 if (IS_BROADWELL(dev)) {
3247 page = i915_gem_object_get_page(dev_priv->semaphore_obj, 0);
3249 seqno = (uint64_t *)kmap_atomic(page);
3250 for_each_engine_id(engine, dev_priv, id) {
3253 seq_printf(m, "%s\n", engine->name);
3255 seq_puts(m, " Last signal:");
3256 for (j = 0; j < num_rings; j++) {
3257 offset = id * I915_NUM_ENGINES + j;
3258 seq_printf(m, "0x%08llx (0x%02llx) ",
3259 seqno[offset], offset * 8);
3263 seq_puts(m, " Last wait: ");
3264 for (j = 0; j < num_rings; j++) {
3265 offset = id + (j * I915_NUM_ENGINES);
3266 seq_printf(m, "0x%08llx (0x%02llx) ",
3267 seqno[offset], offset * 8);
3272 kunmap_atomic(seqno);
3274 seq_puts(m, " Last signal:");
3275 for_each_engine(engine, dev_priv)
3276 for (j = 0; j < num_rings; j++)
3277 seq_printf(m, "0x%08x\n",
3278 I915_READ(engine->semaphore.mbox.signal[j]));
3282 seq_puts(m, "\nSync seqno:\n");
3283 for_each_engine(engine, dev_priv) {
3284 for (j = 0; j < num_rings; j++)
3285 seq_printf(m, " 0x%08x ",
3286 engine->semaphore.sync_seqno[j]);
3291 intel_runtime_pm_put(dev_priv);
3292 mutex_unlock(&dev->struct_mutex);
3296 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3298 struct drm_info_node *node = (struct drm_info_node *) m->private;
3299 struct drm_device *dev = node->minor->dev;
3300 struct drm_i915_private *dev_priv = to_i915(dev);
3303 drm_modeset_lock_all(dev);
3304 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3305 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3307 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3308 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3309 pll->config.crtc_mask, pll->active_mask, yesno(pll->on));
3310 seq_printf(m, " tracked hardware state:\n");
3311 seq_printf(m, " dpll: 0x%08x\n", pll->config.hw_state.dpll);
3312 seq_printf(m, " dpll_md: 0x%08x\n",
3313 pll->config.hw_state.dpll_md);
3314 seq_printf(m, " fp0: 0x%08x\n", pll->config.hw_state.fp0);
3315 seq_printf(m, " fp1: 0x%08x\n", pll->config.hw_state.fp1);
3316 seq_printf(m, " wrpll: 0x%08x\n", pll->config.hw_state.wrpll);
3318 drm_modeset_unlock_all(dev);
3323 static int i915_wa_registers(struct seq_file *m, void *unused)
3327 struct intel_engine_cs *engine;
3328 struct drm_info_node *node = (struct drm_info_node *) m->private;
3329 struct drm_device *dev = node->minor->dev;
3330 struct drm_i915_private *dev_priv = to_i915(dev);
3331 struct i915_workarounds *workarounds = &dev_priv->workarounds;
3332 enum intel_engine_id id;
3334 ret = mutex_lock_interruptible(&dev->struct_mutex);
3338 intel_runtime_pm_get(dev_priv);
3340 seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
3341 for_each_engine_id(engine, dev_priv, id)
3342 seq_printf(m, "HW whitelist count for %s: %d\n",
3343 engine->name, workarounds->hw_whitelist_count[id]);
3344 for (i = 0; i < workarounds->count; ++i) {
3346 u32 mask, value, read;
3349 addr = workarounds->reg[i].addr;
3350 mask = workarounds->reg[i].mask;
3351 value = workarounds->reg[i].value;
3352 read = I915_READ(addr);
3353 ok = (value & mask) == (read & mask);
3354 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3355 i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
3358 intel_runtime_pm_put(dev_priv);
3359 mutex_unlock(&dev->struct_mutex);
3364 static int i915_ddb_info(struct seq_file *m, void *unused)
3366 struct drm_info_node *node = m->private;
3367 struct drm_device *dev = node->minor->dev;
3368 struct drm_i915_private *dev_priv = to_i915(dev);
3369 struct skl_ddb_allocation *ddb;
3370 struct skl_ddb_entry *entry;
3374 if (INTEL_INFO(dev)->gen < 9)
3377 drm_modeset_lock_all(dev);
3379 ddb = &dev_priv->wm.skl_hw.ddb;
3381 seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3383 for_each_pipe(dev_priv, pipe) {
3384 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3386 for_each_plane(dev_priv, pipe, plane) {
3387 entry = &ddb->plane[pipe][plane];
3388 seq_printf(m, " Plane%-8d%8u%8u%8u\n", plane + 1,
3389 entry->start, entry->end,
3390 skl_ddb_entry_size(entry));
3393 entry = &ddb->plane[pipe][PLANE_CURSOR];
3394 seq_printf(m, " %-13s%8u%8u%8u\n", "Cursor", entry->start,
3395 entry->end, skl_ddb_entry_size(entry));
3398 drm_modeset_unlock_all(dev);
3403 static void drrs_status_per_crtc(struct seq_file *m,
3404 struct drm_device *dev, struct intel_crtc *intel_crtc)
3406 struct drm_i915_private *dev_priv = to_i915(dev);
3407 struct i915_drrs *drrs = &dev_priv->drrs;
3409 struct drm_connector *connector;
3411 drm_for_each_connector(connector, dev) {
3412 if (connector->state->crtc != &intel_crtc->base)
3415 seq_printf(m, "%s:\n", connector->name);
3418 if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3419 seq_puts(m, "\tVBT: DRRS_type: Static");
3420 else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3421 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3422 else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3423 seq_puts(m, "\tVBT: DRRS_type: None");
3425 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3427 seq_puts(m, "\n\n");
3429 if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3430 struct intel_panel *panel;
3432 mutex_lock(&drrs->mutex);
3433 /* DRRS Supported */
3434 seq_puts(m, "\tDRRS Supported: Yes\n");
3436 /* disable_drrs() will make drrs->dp NULL */
3438 seq_puts(m, "Idleness DRRS: Disabled");
3439 mutex_unlock(&drrs->mutex);
3443 panel = &drrs->dp->attached_connector->panel;
3444 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3445 drrs->busy_frontbuffer_bits);
3447 seq_puts(m, "\n\t\t");
3448 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3449 seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3450 vrefresh = panel->fixed_mode->vrefresh;
3451 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3452 seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3453 vrefresh = panel->downclock_mode->vrefresh;
3455 seq_printf(m, "DRRS_State: Unknown(%d)\n",
3456 drrs->refresh_rate_type);
3457 mutex_unlock(&drrs->mutex);
3460 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3462 seq_puts(m, "\n\t\t");
3463 mutex_unlock(&drrs->mutex);
3465 /* DRRS not supported. Print the VBT parameter*/
3466 seq_puts(m, "\tDRRS Supported : No");
3471 static int i915_drrs_status(struct seq_file *m, void *unused)
3473 struct drm_info_node *node = m->private;
3474 struct drm_device *dev = node->minor->dev;
3475 struct intel_crtc *intel_crtc;
3476 int active_crtc_cnt = 0;
3478 drm_modeset_lock_all(dev);
3479 for_each_intel_crtc(dev, intel_crtc) {
3480 if (intel_crtc->base.state->active) {
3482 seq_printf(m, "\nCRTC %d: ", active_crtc_cnt);
3484 drrs_status_per_crtc(m, dev, intel_crtc);
3487 drm_modeset_unlock_all(dev);
3489 if (!active_crtc_cnt)
3490 seq_puts(m, "No active crtc found\n");
3495 struct pipe_crc_info {
3497 struct drm_device *dev;
3501 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3503 struct drm_info_node *node = (struct drm_info_node *) m->private;
3504 struct drm_device *dev = node->minor->dev;
3505 struct intel_encoder *intel_encoder;
3506 struct intel_digital_port *intel_dig_port;
3507 struct drm_connector *connector;
3509 drm_modeset_lock_all(dev);
3510 drm_for_each_connector(connector, dev) {
3511 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
3514 intel_encoder = intel_attached_encoder(connector);
3515 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
3518 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
3519 if (!intel_dig_port->dp.can_mst)
3522 seq_printf(m, "MST Source Port %c\n",
3523 port_name(intel_dig_port->port));
3524 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3526 drm_modeset_unlock_all(dev);
3530 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3532 struct pipe_crc_info *info = inode->i_private;
3533 struct drm_i915_private *dev_priv = to_i915(info->dev);
3534 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3536 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
3539 spin_lock_irq(&pipe_crc->lock);
3541 if (pipe_crc->opened) {
3542 spin_unlock_irq(&pipe_crc->lock);
3543 return -EBUSY; /* already open */
3546 pipe_crc->opened = true;
3547 filep->private_data = inode->i_private;
3549 spin_unlock_irq(&pipe_crc->lock);
3554 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3556 struct pipe_crc_info *info = inode->i_private;
3557 struct drm_i915_private *dev_priv = to_i915(info->dev);
3558 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3560 spin_lock_irq(&pipe_crc->lock);
3561 pipe_crc->opened = false;
3562 spin_unlock_irq(&pipe_crc->lock);
3567 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3568 #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1)
3569 /* account for \'0' */
3570 #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1)
3572 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
3574 assert_spin_locked(&pipe_crc->lock);
3575 return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3576 INTEL_PIPE_CRC_ENTRIES_NR);
3580 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3583 struct pipe_crc_info *info = filep->private_data;
3584 struct drm_device *dev = info->dev;
3585 struct drm_i915_private *dev_priv = to_i915(dev);
3586 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3587 char buf[PIPE_CRC_BUFFER_LEN];
3592 * Don't allow user space to provide buffers not big enough to hold
3595 if (count < PIPE_CRC_LINE_LEN)
3598 if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
3601 /* nothing to read */
3602 spin_lock_irq(&pipe_crc->lock);
3603 while (pipe_crc_data_count(pipe_crc) == 0) {
3606 if (filep->f_flags & O_NONBLOCK) {
3607 spin_unlock_irq(&pipe_crc->lock);
3611 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3612 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3614 spin_unlock_irq(&pipe_crc->lock);
3619 /* We now have one or more entries to read */
3620 n_entries = count / PIPE_CRC_LINE_LEN;
3623 while (n_entries > 0) {
3624 struct intel_pipe_crc_entry *entry =
3625 &pipe_crc->entries[pipe_crc->tail];
3628 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3629 INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3632 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3633 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3635 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3636 "%8u %8x %8x %8x %8x %8x\n",
3637 entry->frame, entry->crc[0],
3638 entry->crc[1], entry->crc[2],
3639 entry->crc[3], entry->crc[4]);
3641 spin_unlock_irq(&pipe_crc->lock);
3643 ret = copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN);
3644 if (ret == PIPE_CRC_LINE_LEN)
3647 user_buf += PIPE_CRC_LINE_LEN;
3650 spin_lock_irq(&pipe_crc->lock);
3653 spin_unlock_irq(&pipe_crc->lock);
3658 static const struct file_operations i915_pipe_crc_fops = {
3659 .owner = THIS_MODULE,
3660 .open = i915_pipe_crc_open,
3661 .read = i915_pipe_crc_read,
3662 .release = i915_pipe_crc_release,
3665 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3667 .name = "i915_pipe_A_crc",
3671 .name = "i915_pipe_B_crc",
3675 .name = "i915_pipe_C_crc",
3680 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3683 struct drm_device *dev = minor->dev;
3685 struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3688 ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3689 &i915_pipe_crc_fops);
3693 return drm_add_fake_info_node(minor, ent, info);
3696 static const char * const pipe_crc_sources[] = {
3709 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3711 BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3712 return pipe_crc_sources[source];
3715 static int display_crc_ctl_show(struct seq_file *m, void *data)
3717 struct drm_device *dev = m->private;
3718 struct drm_i915_private *dev_priv = to_i915(dev);
3721 for (i = 0; i < I915_MAX_PIPES; i++)
3722 seq_printf(m, "%c %s\n", pipe_name(i),
3723 pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3728 static int display_crc_ctl_open(struct inode *inode, struct file *file)
3730 struct drm_device *dev = inode->i_private;
3732 return single_open(file, display_crc_ctl_show, dev);
3735 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3738 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3739 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3742 case INTEL_PIPE_CRC_SOURCE_PIPE:
3743 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3745 case INTEL_PIPE_CRC_SOURCE_NONE:
3755 static int i9xx_pipe_crc_auto_source(struct drm_device *dev, enum pipe pipe,
3756 enum intel_pipe_crc_source *source)
3758 struct intel_encoder *encoder;
3759 struct intel_crtc *crtc;
3760 struct intel_digital_port *dig_port;
3763 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3765 drm_modeset_lock_all(dev);
3766 for_each_intel_encoder(dev, encoder) {
3767 if (!encoder->base.crtc)
3770 crtc = to_intel_crtc(encoder->base.crtc);
3772 if (crtc->pipe != pipe)
3775 switch (encoder->type) {
3776 case INTEL_OUTPUT_TVOUT:
3777 *source = INTEL_PIPE_CRC_SOURCE_TV;
3779 case INTEL_OUTPUT_DP:
3780 case INTEL_OUTPUT_EDP:
3781 dig_port = enc_to_dig_port(&encoder->base);
3782 switch (dig_port->port) {
3784 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3787 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3790 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3793 WARN(1, "nonexisting DP port %c\n",
3794 port_name(dig_port->port));
3802 drm_modeset_unlock_all(dev);
3807 static int vlv_pipe_crc_ctl_reg(struct drm_device *dev,
3809 enum intel_pipe_crc_source *source,
3812 struct drm_i915_private *dev_priv = to_i915(dev);
3813 bool need_stable_symbols = false;
3815 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3816 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3822 case INTEL_PIPE_CRC_SOURCE_PIPE:
3823 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3825 case INTEL_PIPE_CRC_SOURCE_DP_B:
3826 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3827 need_stable_symbols = true;
3829 case INTEL_PIPE_CRC_SOURCE_DP_C:
3830 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3831 need_stable_symbols = true;
3833 case INTEL_PIPE_CRC_SOURCE_DP_D:
3834 if (!IS_CHERRYVIEW(dev))
3836 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3837 need_stable_symbols = true;
3839 case INTEL_PIPE_CRC_SOURCE_NONE:
3847 * When the pipe CRC tap point is after the transcoders we need
3848 * to tweak symbol-level features to produce a deterministic series of
3849 * symbols for a given frame. We need to reset those features only once
3850 * a frame (instead of every nth symbol):
3851 * - DC-balance: used to ensure a better clock recovery from the data
3853 * - DisplayPort scrambling: used for EMI reduction
3855 if (need_stable_symbols) {
3856 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3858 tmp |= DC_BALANCE_RESET_VLV;
3861 tmp |= PIPE_A_SCRAMBLE_RESET;
3864 tmp |= PIPE_B_SCRAMBLE_RESET;
3867 tmp |= PIPE_C_SCRAMBLE_RESET;
3872 I915_WRITE(PORT_DFT2_G4X, tmp);
3878 static int i9xx_pipe_crc_ctl_reg(struct drm_device *dev,
3880 enum intel_pipe_crc_source *source,
3883 struct drm_i915_private *dev_priv = to_i915(dev);
3884 bool need_stable_symbols = false;
3886 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3887 int ret = i9xx_pipe_crc_auto_source(dev, pipe, source);
3893 case INTEL_PIPE_CRC_SOURCE_PIPE:
3894 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3896 case INTEL_PIPE_CRC_SOURCE_TV:
3897 if (!SUPPORTS_TV(dev))
3899 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3901 case INTEL_PIPE_CRC_SOURCE_DP_B:
3904 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3905 need_stable_symbols = true;
3907 case INTEL_PIPE_CRC_SOURCE_DP_C:
3910 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3911 need_stable_symbols = true;
3913 case INTEL_PIPE_CRC_SOURCE_DP_D:
3916 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3917 need_stable_symbols = true;
3919 case INTEL_PIPE_CRC_SOURCE_NONE:
3927 * When the pipe CRC tap point is after the transcoders we need
3928 * to tweak symbol-level features to produce a deterministic series of
3929 * symbols for a given frame. We need to reset those features only once
3930 * a frame (instead of every nth symbol):
3931 * - DC-balance: used to ensure a better clock recovery from the data
3933 * - DisplayPort scrambling: used for EMI reduction
3935 if (need_stable_symbols) {
3936 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3938 WARN_ON(!IS_G4X(dev));
3940 I915_WRITE(PORT_DFT_I9XX,
3941 I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
3944 tmp |= PIPE_A_SCRAMBLE_RESET;
3946 tmp |= PIPE_B_SCRAMBLE_RESET;
3948 I915_WRITE(PORT_DFT2_G4X, tmp);
3954 static void vlv_undo_pipe_scramble_reset(struct drm_device *dev,
3957 struct drm_i915_private *dev_priv = to_i915(dev);
3958 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3962 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3965 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3968 tmp &= ~PIPE_C_SCRAMBLE_RESET;
3973 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
3974 tmp &= ~DC_BALANCE_RESET_VLV;
3975 I915_WRITE(PORT_DFT2_G4X, tmp);
3979 static void g4x_undo_pipe_scramble_reset(struct drm_device *dev,
3982 struct drm_i915_private *dev_priv = to_i915(dev);
3983 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3986 tmp &= ~PIPE_A_SCRAMBLE_RESET;
3988 tmp &= ~PIPE_B_SCRAMBLE_RESET;
3989 I915_WRITE(PORT_DFT2_G4X, tmp);
3991 if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
3992 I915_WRITE(PORT_DFT_I9XX,
3993 I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
3997 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
4000 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
4001 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
4004 case INTEL_PIPE_CRC_SOURCE_PLANE1:
4005 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
4007 case INTEL_PIPE_CRC_SOURCE_PLANE2:
4008 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
4010 case INTEL_PIPE_CRC_SOURCE_PIPE:
4011 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
4013 case INTEL_PIPE_CRC_SOURCE_NONE:
4023 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_device *dev, bool enable)
4025 struct drm_i915_private *dev_priv = to_i915(dev);
4026 struct intel_crtc *crtc =
4027 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
4028 struct intel_crtc_state *pipe_config;
4029 struct drm_atomic_state *state;
4032 drm_modeset_lock_all(dev);
4033 state = drm_atomic_state_alloc(dev);
4039 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
4040 pipe_config = intel_atomic_get_crtc_state(state, crtc);
4041 if (IS_ERR(pipe_config)) {
4042 ret = PTR_ERR(pipe_config);
4046 pipe_config->pch_pfit.force_thru = enable;
4047 if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
4048 pipe_config->pch_pfit.enabled != enable)
4049 pipe_config->base.connectors_changed = true;
4051 ret = drm_atomic_commit(state);
4053 drm_modeset_unlock_all(dev);
4054 WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
4056 drm_atomic_state_free(state);
4059 static int ivb_pipe_crc_ctl_reg(struct drm_device *dev,
4061 enum intel_pipe_crc_source *source,
4064 if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
4065 *source = INTEL_PIPE_CRC_SOURCE_PF;
4068 case INTEL_PIPE_CRC_SOURCE_PLANE1:
4069 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
4071 case INTEL_PIPE_CRC_SOURCE_PLANE2:
4072 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
4074 case INTEL_PIPE_CRC_SOURCE_PF:
4075 if (IS_HASWELL(dev) && pipe == PIPE_A)
4076 hsw_trans_edp_pipe_A_crc_wa(dev, true);
4078 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
4080 case INTEL_PIPE_CRC_SOURCE_NONE:
4090 static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
4091 enum intel_pipe_crc_source source)
4093 struct drm_i915_private *dev_priv = to_i915(dev);
4094 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
4095 struct intel_crtc *crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev,
4097 enum intel_display_power_domain power_domain;
4098 u32 val = 0; /* shut up gcc */
4101 if (pipe_crc->source == source)
4104 /* forbid changing the source without going back to 'none' */
4105 if (pipe_crc->source && source)
4108 power_domain = POWER_DOMAIN_PIPE(pipe);
4109 if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
4110 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
4115 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
4116 else if (INTEL_INFO(dev)->gen < 5)
4117 ret = i9xx_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4118 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4119 ret = vlv_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4120 else if (IS_GEN5(dev) || IS_GEN6(dev))
4121 ret = ilk_pipe_crc_ctl_reg(&source, &val);
4123 ret = ivb_pipe_crc_ctl_reg(dev, pipe, &source, &val);
4128 /* none -> real source transition */
4130 struct intel_pipe_crc_entry *entries;
4132 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4133 pipe_name(pipe), pipe_crc_source_name(source));
4135 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
4136 sizeof(pipe_crc->entries[0]),
4144 * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4145 * enabled and disabled dynamically based on package C states,
4146 * user space can't make reliable use of the CRCs, so let's just
4147 * completely disable it.
4149 hsw_disable_ips(crtc);
4151 spin_lock_irq(&pipe_crc->lock);
4152 kfree(pipe_crc->entries);
4153 pipe_crc->entries = entries;
4156 spin_unlock_irq(&pipe_crc->lock);
4159 pipe_crc->source = source;
4161 I915_WRITE(PIPE_CRC_CTL(pipe), val);
4162 POSTING_READ(PIPE_CRC_CTL(pipe));
4164 /* real source -> none transition */
4165 if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
4166 struct intel_pipe_crc_entry *entries;
4167 struct intel_crtc *crtc =
4168 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
4170 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4173 drm_modeset_lock(&crtc->base.mutex, NULL);
4174 if (crtc->base.state->active)
4175 intel_wait_for_vblank(dev, pipe);
4176 drm_modeset_unlock(&crtc->base.mutex);
4178 spin_lock_irq(&pipe_crc->lock);
4179 entries = pipe_crc->entries;
4180 pipe_crc->entries = NULL;
4183 spin_unlock_irq(&pipe_crc->lock);
4188 g4x_undo_pipe_scramble_reset(dev, pipe);
4189 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
4190 vlv_undo_pipe_scramble_reset(dev, pipe);
4191 else if (IS_HASWELL(dev) && pipe == PIPE_A)
4192 hsw_trans_edp_pipe_A_crc_wa(dev, false);
4194 hsw_enable_ips(crtc);
4200 intel_display_power_put(dev_priv, power_domain);
4206 * Parse pipe CRC command strings:
4207 * command: wsp* object wsp+ name wsp+ source wsp*
4210 * source: (none | plane1 | plane2 | pf)
4211 * wsp: (#0x20 | #0x9 | #0xA)+
4214 * "pipe A plane1" -> Start CRC computations on plane1 of pipe A
4215 * "pipe A none" -> Stop CRC
4217 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
4224 /* skip leading white space */
4225 buf = skip_spaces(buf);
4227 break; /* end of buffer */
4229 /* find end of word */
4230 for (end = buf; *end && !isspace(*end); end++)
4233 if (n_words == max_words) {
4234 DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4236 return -EINVAL; /* ran out of words[] before bytes */
4241 words[n_words++] = buf;
4248 enum intel_pipe_crc_object {
4249 PIPE_CRC_OBJECT_PIPE,
4252 static const char * const pipe_crc_objects[] = {
4257 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
4261 for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
4262 if (!strcmp(buf, pipe_crc_objects[i])) {
4270 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
4272 const char name = buf[0];
4274 if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
4283 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
4287 for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
4288 if (!strcmp(buf, pipe_crc_sources[i])) {
4296 static int display_crc_ctl_parse(struct drm_device *dev, char *buf, size_t len)
4300 char *words[N_WORDS];
4302 enum intel_pipe_crc_object object;
4303 enum intel_pipe_crc_source source;
4305 n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
4306 if (n_words != N_WORDS) {
4307 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4312 if (display_crc_ctl_parse_object(words[0], &object) < 0) {
4313 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
4317 if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
4318 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
4322 if (display_crc_ctl_parse_source(words[2], &source) < 0) {
4323 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
4327 return pipe_crc_set_source(dev, pipe, source);
4330 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
4331 size_t len, loff_t *offp)
4333 struct seq_file *m = file->private_data;
4334 struct drm_device *dev = m->private;
4341 if (len > PAGE_SIZE - 1) {
4342 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4347 tmpbuf = kmalloc(len + 1, GFP_KERNEL);
4351 if (copy_from_user(tmpbuf, ubuf, len)) {
4357 ret = display_crc_ctl_parse(dev, tmpbuf, len);
4368 static const struct file_operations i915_display_crc_ctl_fops = {
4369 .owner = THIS_MODULE,
4370 .open = display_crc_ctl_open,
4372 .llseek = seq_lseek,
4373 .release = single_release,
4374 .write = display_crc_ctl_write
4377 static ssize_t i915_displayport_test_active_write(struct file *file,
4378 const char __user *ubuf,
4379 size_t len, loff_t *offp)
4383 struct drm_device *dev;
4384 struct drm_connector *connector;
4385 struct list_head *connector_list;
4386 struct intel_dp *intel_dp;
4389 dev = ((struct seq_file *)file->private_data)->private;
4391 connector_list = &dev->mode_config.connector_list;
4396 input_buffer = kmalloc(len + 1, GFP_KERNEL);
4400 if (copy_from_user(input_buffer, ubuf, len)) {
4405 input_buffer[len] = '\0';
4406 DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4408 list_for_each_entry(connector, connector_list, head) {
4410 if (connector->connector_type !=
4411 DRM_MODE_CONNECTOR_DisplayPort)
4414 if (connector->status == connector_status_connected &&
4415 connector->encoder != NULL) {
4416 intel_dp = enc_to_intel_dp(connector->encoder);
4417 status = kstrtoint(input_buffer, 10, &val);
4420 DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4421 /* To prevent erroneous activation of the compliance
4422 * testing code, only accept an actual value of 1 here
4425 intel_dp->compliance_test_active = 1;
4427 intel_dp->compliance_test_active = 0;
4431 kfree(input_buffer);
4439 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4441 struct drm_device *dev = m->private;
4442 struct drm_connector *connector;
4443 struct list_head *connector_list = &dev->mode_config.connector_list;
4444 struct intel_dp *intel_dp;
4446 list_for_each_entry(connector, connector_list, head) {
4448 if (connector->connector_type !=
4449 DRM_MODE_CONNECTOR_DisplayPort)
4452 if (connector->status == connector_status_connected &&
4453 connector->encoder != NULL) {
4454 intel_dp = enc_to_intel_dp(connector->encoder);
4455 if (intel_dp->compliance_test_active)
4466 static int i915_displayport_test_active_open(struct inode *inode,
4469 struct drm_device *dev = inode->i_private;
4471 return single_open(file, i915_displayport_test_active_show, dev);
4474 static const struct file_operations i915_displayport_test_active_fops = {
4475 .owner = THIS_MODULE,
4476 .open = i915_displayport_test_active_open,
4478 .llseek = seq_lseek,
4479 .release = single_release,
4480 .write = i915_displayport_test_active_write
4483 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4485 struct drm_device *dev = m->private;
4486 struct drm_connector *connector;
4487 struct list_head *connector_list = &dev->mode_config.connector_list;
4488 struct intel_dp *intel_dp;
4490 list_for_each_entry(connector, connector_list, head) {
4492 if (connector->connector_type !=
4493 DRM_MODE_CONNECTOR_DisplayPort)
4496 if (connector->status == connector_status_connected &&
4497 connector->encoder != NULL) {
4498 intel_dp = enc_to_intel_dp(connector->encoder);
4499 seq_printf(m, "%lx", intel_dp->compliance_test_data);
4506 static int i915_displayport_test_data_open(struct inode *inode,
4509 struct drm_device *dev = inode->i_private;
4511 return single_open(file, i915_displayport_test_data_show, dev);
4514 static const struct file_operations i915_displayport_test_data_fops = {
4515 .owner = THIS_MODULE,
4516 .open = i915_displayport_test_data_open,
4518 .llseek = seq_lseek,
4519 .release = single_release
4522 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4524 struct drm_device *dev = m->private;
4525 struct drm_connector *connector;
4526 struct list_head *connector_list = &dev->mode_config.connector_list;
4527 struct intel_dp *intel_dp;
4529 list_for_each_entry(connector, connector_list, head) {
4531 if (connector->connector_type !=
4532 DRM_MODE_CONNECTOR_DisplayPort)
4535 if (connector->status == connector_status_connected &&
4536 connector->encoder != NULL) {
4537 intel_dp = enc_to_intel_dp(connector->encoder);
4538 seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4546 static int i915_displayport_test_type_open(struct inode *inode,
4549 struct drm_device *dev = inode->i_private;
4551 return single_open(file, i915_displayport_test_type_show, dev);
4554 static const struct file_operations i915_displayport_test_type_fops = {
4555 .owner = THIS_MODULE,
4556 .open = i915_displayport_test_type_open,
4558 .llseek = seq_lseek,
4559 .release = single_release
4562 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
4564 struct drm_device *dev = m->private;
4568 if (IS_CHERRYVIEW(dev))
4570 else if (IS_VALLEYVIEW(dev))
4573 num_levels = ilk_wm_max_level(dev) + 1;
4575 drm_modeset_lock_all(dev);
4577 for (level = 0; level < num_levels; level++) {
4578 unsigned int latency = wm[level];
4581 * - WM1+ latency values in 0.5us units
4582 * - latencies are in us on gen9/vlv/chv
4584 if (INTEL_INFO(dev)->gen >= 9 || IS_VALLEYVIEW(dev) ||
4590 seq_printf(m, "WM%d %u (%u.%u usec)\n",
4591 level, wm[level], latency / 10, latency % 10);
4594 drm_modeset_unlock_all(dev);
4597 static int pri_wm_latency_show(struct seq_file *m, void *data)
4599 struct drm_device *dev = m->private;
4600 struct drm_i915_private *dev_priv = to_i915(dev);
4601 const uint16_t *latencies;
4603 if (INTEL_INFO(dev)->gen >= 9)
4604 latencies = dev_priv->wm.skl_latency;
4606 latencies = to_i915(dev)->wm.pri_latency;
4608 wm_latency_show(m, latencies);
4613 static int spr_wm_latency_show(struct seq_file *m, void *data)
4615 struct drm_device *dev = m->private;
4616 struct drm_i915_private *dev_priv = to_i915(dev);
4617 const uint16_t *latencies;
4619 if (INTEL_INFO(dev)->gen >= 9)
4620 latencies = dev_priv->wm.skl_latency;
4622 latencies = to_i915(dev)->wm.spr_latency;
4624 wm_latency_show(m, latencies);
4629 static int cur_wm_latency_show(struct seq_file *m, void *data)
4631 struct drm_device *dev = m->private;
4632 struct drm_i915_private *dev_priv = to_i915(dev);
4633 const uint16_t *latencies;
4635 if (INTEL_INFO(dev)->gen >= 9)
4636 latencies = dev_priv->wm.skl_latency;
4638 latencies = to_i915(dev)->wm.cur_latency;
4640 wm_latency_show(m, latencies);
4645 static int pri_wm_latency_open(struct inode *inode, struct file *file)
4647 struct drm_device *dev = inode->i_private;
4649 if (INTEL_INFO(dev)->gen < 5)
4652 return single_open(file, pri_wm_latency_show, dev);
4655 static int spr_wm_latency_open(struct inode *inode, struct file *file)
4657 struct drm_device *dev = inode->i_private;
4659 if (HAS_GMCH_DISPLAY(dev))
4662 return single_open(file, spr_wm_latency_show, dev);
4665 static int cur_wm_latency_open(struct inode *inode, struct file *file)
4667 struct drm_device *dev = inode->i_private;
4669 if (HAS_GMCH_DISPLAY(dev))
4672 return single_open(file, cur_wm_latency_show, dev);
4675 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
4676 size_t len, loff_t *offp, uint16_t wm[8])
4678 struct seq_file *m = file->private_data;
4679 struct drm_device *dev = m->private;
4680 uint16_t new[8] = { 0 };
4686 if (IS_CHERRYVIEW(dev))
4688 else if (IS_VALLEYVIEW(dev))
4691 num_levels = ilk_wm_max_level(dev) + 1;
4693 if (len >= sizeof(tmp))
4696 if (copy_from_user(tmp, ubuf, len))
4701 ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4702 &new[0], &new[1], &new[2], &new[3],
4703 &new[4], &new[5], &new[6], &new[7]);
4704 if (ret != num_levels)
4707 drm_modeset_lock_all(dev);
4709 for (level = 0; level < num_levels; level++)
4710 wm[level] = new[level];
4712 drm_modeset_unlock_all(dev);
4718 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4719 size_t len, loff_t *offp)
4721 struct seq_file *m = file->private_data;
4722 struct drm_device *dev = m->private;
4723 struct drm_i915_private *dev_priv = to_i915(dev);
4724 uint16_t *latencies;
4726 if (INTEL_INFO(dev)->gen >= 9)
4727 latencies = dev_priv->wm.skl_latency;
4729 latencies = to_i915(dev)->wm.pri_latency;
4731 return wm_latency_write(file, ubuf, len, offp, latencies);
4734 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4735 size_t len, loff_t *offp)
4737 struct seq_file *m = file->private_data;
4738 struct drm_device *dev = m->private;
4739 struct drm_i915_private *dev_priv = to_i915(dev);
4740 uint16_t *latencies;
4742 if (INTEL_INFO(dev)->gen >= 9)
4743 latencies = dev_priv->wm.skl_latency;
4745 latencies = to_i915(dev)->wm.spr_latency;
4747 return wm_latency_write(file, ubuf, len, offp, latencies);
4750 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4751 size_t len, loff_t *offp)
4753 struct seq_file *m = file->private_data;
4754 struct drm_device *dev = m->private;
4755 struct drm_i915_private *dev_priv = to_i915(dev);
4756 uint16_t *latencies;
4758 if (INTEL_INFO(dev)->gen >= 9)
4759 latencies = dev_priv->wm.skl_latency;
4761 latencies = to_i915(dev)->wm.cur_latency;
4763 return wm_latency_write(file, ubuf, len, offp, latencies);
4766 static const struct file_operations i915_pri_wm_latency_fops = {
4767 .owner = THIS_MODULE,
4768 .open = pri_wm_latency_open,
4770 .llseek = seq_lseek,
4771 .release = single_release,
4772 .write = pri_wm_latency_write
4775 static const struct file_operations i915_spr_wm_latency_fops = {
4776 .owner = THIS_MODULE,
4777 .open = spr_wm_latency_open,
4779 .llseek = seq_lseek,
4780 .release = single_release,
4781 .write = spr_wm_latency_write
4784 static const struct file_operations i915_cur_wm_latency_fops = {
4785 .owner = THIS_MODULE,
4786 .open = cur_wm_latency_open,
4788 .llseek = seq_lseek,
4789 .release = single_release,
4790 .write = cur_wm_latency_write
4794 i915_wedged_get(void *data, u64 *val)
4796 struct drm_device *dev = data;
4797 struct drm_i915_private *dev_priv = to_i915(dev);
4799 *val = i915_terminally_wedged(&dev_priv->gpu_error);
4805 i915_wedged_set(void *data, u64 val)
4807 struct drm_device *dev = data;
4808 struct drm_i915_private *dev_priv = to_i915(dev);
4811 * There is no safeguard against this debugfs entry colliding
4812 * with the hangcheck calling same i915_handle_error() in
4813 * parallel, causing an explosion. For now we assume that the
4814 * test harness is responsible enough not to inject gpu hangs
4815 * while it is writing to 'i915_wedged'
4818 if (i915_reset_in_progress(&dev_priv->gpu_error))
4821 intel_runtime_pm_get(dev_priv);
4823 i915_handle_error(dev_priv, val,
4824 "Manually setting wedged to %llu", val);
4826 intel_runtime_pm_put(dev_priv);
4831 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4832 i915_wedged_get, i915_wedged_set,
4836 i915_ring_missed_irq_get(void *data, u64 *val)
4838 struct drm_device *dev = data;
4839 struct drm_i915_private *dev_priv = to_i915(dev);
4841 *val = dev_priv->gpu_error.missed_irq_rings;
4846 i915_ring_missed_irq_set(void *data, u64 val)
4848 struct drm_device *dev = data;
4849 struct drm_i915_private *dev_priv = to_i915(dev);
4852 /* Lock against concurrent debugfs callers */
4853 ret = mutex_lock_interruptible(&dev->struct_mutex);
4856 dev_priv->gpu_error.missed_irq_rings = val;
4857 mutex_unlock(&dev->struct_mutex);
4862 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4863 i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4867 i915_ring_test_irq_get(void *data, u64 *val)
4869 struct drm_device *dev = data;
4870 struct drm_i915_private *dev_priv = to_i915(dev);
4872 *val = dev_priv->gpu_error.test_irq_rings;
4878 i915_ring_test_irq_set(void *data, u64 val)
4880 struct drm_device *dev = data;
4881 struct drm_i915_private *dev_priv = to_i915(dev);
4883 val &= INTEL_INFO(dev_priv)->ring_mask;
4884 DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4885 dev_priv->gpu_error.test_irq_rings = val;
4890 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4891 i915_ring_test_irq_get, i915_ring_test_irq_set,
4894 #define DROP_UNBOUND 0x1
4895 #define DROP_BOUND 0x2
4896 #define DROP_RETIRE 0x4
4897 #define DROP_ACTIVE 0x8
4898 #define DROP_ALL (DROP_UNBOUND | \
4903 i915_drop_caches_get(void *data, u64 *val)
4911 i915_drop_caches_set(void *data, u64 val)
4913 struct drm_device *dev = data;
4914 struct drm_i915_private *dev_priv = to_i915(dev);
4917 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4919 /* No need to check and wait for gpu resets, only libdrm auto-restarts
4920 * on ioctls on -EAGAIN. */
4921 ret = mutex_lock_interruptible(&dev->struct_mutex);
4925 if (val & DROP_ACTIVE) {
4926 ret = i915_gem_wait_for_idle(dev_priv);
4931 if (val & (DROP_RETIRE | DROP_ACTIVE))
4932 i915_gem_retire_requests(dev_priv);
4934 if (val & DROP_BOUND)
4935 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4937 if (val & DROP_UNBOUND)
4938 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
4941 mutex_unlock(&dev->struct_mutex);
4946 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
4947 i915_drop_caches_get, i915_drop_caches_set,
4951 i915_max_freq_get(void *data, u64 *val)
4953 struct drm_device *dev = data;
4954 struct drm_i915_private *dev_priv = to_i915(dev);
4956 if (INTEL_INFO(dev)->gen < 6)
4959 *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
4964 i915_max_freq_set(void *data, u64 val)
4966 struct drm_device *dev = data;
4967 struct drm_i915_private *dev_priv = to_i915(dev);
4971 if (INTEL_INFO(dev)->gen < 6)
4974 DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
4976 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
4981 * Turbo will still be enabled, but won't go above the set value.
4983 val = intel_freq_opcode(dev_priv, val);
4985 hw_max = dev_priv->rps.max_freq;
4986 hw_min = dev_priv->rps.min_freq;
4988 if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
4989 mutex_unlock(&dev_priv->rps.hw_lock);
4993 dev_priv->rps.max_freq_softlimit = val;
4995 intel_set_rps(dev_priv, val);
4997 mutex_unlock(&dev_priv->rps.hw_lock);
5002 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
5003 i915_max_freq_get, i915_max_freq_set,
5007 i915_min_freq_get(void *data, u64 *val)
5009 struct drm_device *dev = data;
5010 struct drm_i915_private *dev_priv = to_i915(dev);
5012 if (INTEL_GEN(dev_priv) < 6)
5015 *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
5020 i915_min_freq_set(void *data, u64 val)
5022 struct drm_device *dev = data;
5023 struct drm_i915_private *dev_priv = to_i915(dev);
5027 if (INTEL_GEN(dev_priv) < 6)
5030 DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
5032 ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
5037 * Turbo will still be enabled, but won't go below the set value.
5039 val = intel_freq_opcode(dev_priv, val);
5041 hw_max = dev_priv->rps.max_freq;
5042 hw_min = dev_priv->rps.min_freq;
5044 if (val < hw_min || val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
5045 mutex_unlock(&dev_priv->rps.hw_lock);
5049 dev_priv->rps.min_freq_softlimit = val;
5051 intel_set_rps(dev_priv, val);
5053 mutex_unlock(&dev_priv->rps.hw_lock);
5058 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
5059 i915_min_freq_get, i915_min_freq_set,
5063 i915_cache_sharing_get(void *data, u64 *val)
5065 struct drm_device *dev = data;
5066 struct drm_i915_private *dev_priv = to_i915(dev);
5070 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5073 ret = mutex_lock_interruptible(&dev->struct_mutex);
5076 intel_runtime_pm_get(dev_priv);
5078 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5080 intel_runtime_pm_put(dev_priv);
5081 mutex_unlock(&dev_priv->drm.struct_mutex);
5083 *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
5089 i915_cache_sharing_set(void *data, u64 val)
5091 struct drm_device *dev = data;
5092 struct drm_i915_private *dev_priv = to_i915(dev);
5095 if (!(IS_GEN6(dev) || IS_GEN7(dev)))
5101 intel_runtime_pm_get(dev_priv);
5102 DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
5104 /* Update the cache sharing policy here as well */
5105 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5106 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5107 snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
5108 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5110 intel_runtime_pm_put(dev_priv);
5114 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
5115 i915_cache_sharing_get, i915_cache_sharing_set,
5118 struct sseu_dev_status {
5119 unsigned int slice_total;
5120 unsigned int subslice_total;
5121 unsigned int subslice_per_slice;
5122 unsigned int eu_total;
5123 unsigned int eu_per_subslice;
5126 static void cherryview_sseu_device_status(struct drm_device *dev,
5127 struct sseu_dev_status *stat)
5129 struct drm_i915_private *dev_priv = to_i915(dev);
5132 u32 sig1[ss_max], sig2[ss_max];
5134 sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
5135 sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
5136 sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
5137 sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
5139 for (ss = 0; ss < ss_max; ss++) {
5140 unsigned int eu_cnt;
5142 if (sig1[ss] & CHV_SS_PG_ENABLE)
5143 /* skip disabled subslice */
5146 stat->slice_total = 1;
5147 stat->subslice_per_slice++;
5148 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
5149 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
5150 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
5151 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
5152 stat->eu_total += eu_cnt;
5153 stat->eu_per_subslice = max(stat->eu_per_subslice, eu_cnt);
5155 stat->subslice_total = stat->subslice_per_slice;
5158 static void gen9_sseu_device_status(struct drm_device *dev,
5159 struct sseu_dev_status *stat)
5161 struct drm_i915_private *dev_priv = to_i915(dev);
5162 int s_max = 3, ss_max = 4;
5164 u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
5166 /* BXT has a single slice and at most 3 subslices. */
5167 if (IS_BROXTON(dev)) {
5172 for (s = 0; s < s_max; s++) {
5173 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
5174 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
5175 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
5178 eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
5179 GEN9_PGCTL_SSA_EU19_ACK |
5180 GEN9_PGCTL_SSA_EU210_ACK |
5181 GEN9_PGCTL_SSA_EU311_ACK;
5182 eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
5183 GEN9_PGCTL_SSB_EU19_ACK |
5184 GEN9_PGCTL_SSB_EU210_ACK |
5185 GEN9_PGCTL_SSB_EU311_ACK;
5187 for (s = 0; s < s_max; s++) {
5188 unsigned int ss_cnt = 0;
5190 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
5191 /* skip disabled slice */
5194 stat->slice_total++;
5196 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
5197 ss_cnt = INTEL_INFO(dev)->subslice_per_slice;
5199 for (ss = 0; ss < ss_max; ss++) {
5200 unsigned int eu_cnt;
5202 if (IS_BROXTON(dev) &&
5203 !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
5204 /* skip disabled subslice */
5207 if (IS_BROXTON(dev))
5210 eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
5212 stat->eu_total += eu_cnt;
5213 stat->eu_per_subslice = max(stat->eu_per_subslice,
5217 stat->subslice_total += ss_cnt;
5218 stat->subslice_per_slice = max(stat->subslice_per_slice,
5223 static void broadwell_sseu_device_status(struct drm_device *dev,
5224 struct sseu_dev_status *stat)
5226 struct drm_i915_private *dev_priv = to_i915(dev);
5228 u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
5230 stat->slice_total = hweight32(slice_info & GEN8_LSLICESTAT_MASK);
5232 if (stat->slice_total) {
5233 stat->subslice_per_slice = INTEL_INFO(dev)->subslice_per_slice;
5234 stat->subslice_total = stat->slice_total *
5235 stat->subslice_per_slice;
5236 stat->eu_per_subslice = INTEL_INFO(dev)->eu_per_subslice;
5237 stat->eu_total = stat->eu_per_subslice * stat->subslice_total;
5239 /* subtract fused off EU(s) from enabled slice(s) */
5240 for (s = 0; s < stat->slice_total; s++) {
5241 u8 subslice_7eu = INTEL_INFO(dev)->subslice_7eu[s];
5243 stat->eu_total -= hweight8(subslice_7eu);
5248 static int i915_sseu_status(struct seq_file *m, void *unused)
5250 struct drm_info_node *node = (struct drm_info_node *) m->private;
5251 struct drm_i915_private *dev_priv = to_i915(node->minor->dev);
5252 struct drm_device *dev = &dev_priv->drm;
5253 struct sseu_dev_status stat;
5255 if (INTEL_INFO(dev)->gen < 8)
5258 seq_puts(m, "SSEU Device Info\n");
5259 seq_printf(m, " Available Slice Total: %u\n",
5260 INTEL_INFO(dev)->slice_total);
5261 seq_printf(m, " Available Subslice Total: %u\n",
5262 INTEL_INFO(dev)->subslice_total);
5263 seq_printf(m, " Available Subslice Per Slice: %u\n",
5264 INTEL_INFO(dev)->subslice_per_slice);
5265 seq_printf(m, " Available EU Total: %u\n",
5266 INTEL_INFO(dev)->eu_total);
5267 seq_printf(m, " Available EU Per Subslice: %u\n",
5268 INTEL_INFO(dev)->eu_per_subslice);
5269 seq_printf(m, " Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev)));
5270 if (HAS_POOLED_EU(dev))
5271 seq_printf(m, " Min EU in pool: %u\n",
5272 INTEL_INFO(dev)->min_eu_in_pool);
5273 seq_printf(m, " Has Slice Power Gating: %s\n",
5274 yesno(INTEL_INFO(dev)->has_slice_pg));
5275 seq_printf(m, " Has Subslice Power Gating: %s\n",
5276 yesno(INTEL_INFO(dev)->has_subslice_pg));
5277 seq_printf(m, " Has EU Power Gating: %s\n",
5278 yesno(INTEL_INFO(dev)->has_eu_pg));
5280 seq_puts(m, "SSEU Device Status\n");
5281 memset(&stat, 0, sizeof(stat));
5283 intel_runtime_pm_get(dev_priv);
5285 if (IS_CHERRYVIEW(dev)) {
5286 cherryview_sseu_device_status(dev, &stat);
5287 } else if (IS_BROADWELL(dev)) {
5288 broadwell_sseu_device_status(dev, &stat);
5289 } else if (INTEL_INFO(dev)->gen >= 9) {
5290 gen9_sseu_device_status(dev, &stat);
5293 intel_runtime_pm_put(dev_priv);
5295 seq_printf(m, " Enabled Slice Total: %u\n",
5297 seq_printf(m, " Enabled Subslice Total: %u\n",
5298 stat.subslice_total);
5299 seq_printf(m, " Enabled Subslice Per Slice: %u\n",
5300 stat.subslice_per_slice);
5301 seq_printf(m, " Enabled EU Total: %u\n",
5303 seq_printf(m, " Enabled EU Per Subslice: %u\n",
5304 stat.eu_per_subslice);
5309 static int i915_forcewake_open(struct inode *inode, struct file *file)
5311 struct drm_device *dev = inode->i_private;
5312 struct drm_i915_private *dev_priv = to_i915(dev);
5314 if (INTEL_INFO(dev)->gen < 6)
5317 intel_runtime_pm_get(dev_priv);
5318 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5323 static int i915_forcewake_release(struct inode *inode, struct file *file)
5325 struct drm_device *dev = inode->i_private;
5326 struct drm_i915_private *dev_priv = to_i915(dev);
5328 if (INTEL_INFO(dev)->gen < 6)
5331 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5332 intel_runtime_pm_put(dev_priv);
5337 static const struct file_operations i915_forcewake_fops = {
5338 .owner = THIS_MODULE,
5339 .open = i915_forcewake_open,
5340 .release = i915_forcewake_release,
5343 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5345 struct drm_device *dev = minor->dev;
5348 ent = debugfs_create_file("i915_forcewake_user",
5351 &i915_forcewake_fops);
5355 return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
5358 static int i915_debugfs_create(struct dentry *root,
5359 struct drm_minor *minor,
5361 const struct file_operations *fops)
5363 struct drm_device *dev = minor->dev;
5366 ent = debugfs_create_file(name,
5373 return drm_add_fake_info_node(minor, ent, fops);
5376 static const struct drm_info_list i915_debugfs_list[] = {
5377 {"i915_capabilities", i915_capabilities, 0},
5378 {"i915_gem_objects", i915_gem_object_info, 0},
5379 {"i915_gem_gtt", i915_gem_gtt_info, 0},
5380 {"i915_gem_pinned", i915_gem_gtt_info, 0, (void *) PINNED_LIST},
5381 {"i915_gem_active", i915_gem_object_list_info, 0, (void *) ACTIVE_LIST},
5382 {"i915_gem_inactive", i915_gem_object_list_info, 0, (void *) INACTIVE_LIST},
5383 {"i915_gem_stolen", i915_gem_stolen_list_info },
5384 {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
5385 {"i915_gem_request", i915_gem_request_info, 0},
5386 {"i915_gem_seqno", i915_gem_seqno_info, 0},
5387 {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
5388 {"i915_gem_interrupt", i915_interrupt_info, 0},
5389 {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5390 {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5391 {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
5392 {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
5393 {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
5394 {"i915_guc_info", i915_guc_info, 0},
5395 {"i915_guc_load_status", i915_guc_load_status_info, 0},
5396 {"i915_guc_log_dump", i915_guc_log_dump, 0},
5397 {"i915_frequency_info", i915_frequency_info, 0},
5398 {"i915_hangcheck_info", i915_hangcheck_info, 0},
5399 {"i915_drpc_info", i915_drpc_info, 0},
5400 {"i915_emon_status", i915_emon_status, 0},
5401 {"i915_ring_freq_table", i915_ring_freq_table, 0},
5402 {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
5403 {"i915_fbc_status", i915_fbc_status, 0},
5404 {"i915_ips_status", i915_ips_status, 0},
5405 {"i915_sr_status", i915_sr_status, 0},
5406 {"i915_opregion", i915_opregion, 0},
5407 {"i915_vbt", i915_vbt, 0},
5408 {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
5409 {"i915_context_status", i915_context_status, 0},
5410 {"i915_dump_lrc", i915_dump_lrc, 0},
5411 {"i915_execlists", i915_execlists, 0},
5412 {"i915_forcewake_domains", i915_forcewake_domains, 0},
5413 {"i915_swizzle_info", i915_swizzle_info, 0},
5414 {"i915_ppgtt_info", i915_ppgtt_info, 0},
5415 {"i915_llc", i915_llc, 0},
5416 {"i915_edp_psr_status", i915_edp_psr_status, 0},
5417 {"i915_sink_crc_eDP1", i915_sink_crc, 0},
5418 {"i915_energy_uJ", i915_energy_uJ, 0},
5419 {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
5420 {"i915_power_domain_info", i915_power_domain_info, 0},
5421 {"i915_dmc_info", i915_dmc_info, 0},
5422 {"i915_display_info", i915_display_info, 0},
5423 {"i915_semaphore_status", i915_semaphore_status, 0},
5424 {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
5425 {"i915_dp_mst_info", i915_dp_mst_info, 0},
5426 {"i915_wa_registers", i915_wa_registers, 0},
5427 {"i915_ddb_info", i915_ddb_info, 0},
5428 {"i915_sseu_status", i915_sseu_status, 0},
5429 {"i915_drrs_status", i915_drrs_status, 0},
5430 {"i915_rps_boost_info", i915_rps_boost_info, 0},
5432 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5434 static const struct i915_debugfs_files {
5436 const struct file_operations *fops;
5437 } i915_debugfs_files[] = {
5438 {"i915_wedged", &i915_wedged_fops},
5439 {"i915_max_freq", &i915_max_freq_fops},
5440 {"i915_min_freq", &i915_min_freq_fops},
5441 {"i915_cache_sharing", &i915_cache_sharing_fops},
5442 {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5443 {"i915_ring_test_irq", &i915_ring_test_irq_fops},
5444 {"i915_gem_drop_caches", &i915_drop_caches_fops},
5445 {"i915_error_state", &i915_error_state_fops},
5446 {"i915_next_seqno", &i915_next_seqno_fops},
5447 {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
5448 {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5449 {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5450 {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
5451 {"i915_fbc_false_color", &i915_fbc_fc_fops},
5452 {"i915_dp_test_data", &i915_displayport_test_data_fops},
5453 {"i915_dp_test_type", &i915_displayport_test_type_fops},
5454 {"i915_dp_test_active", &i915_displayport_test_active_fops}
5457 void intel_display_crc_init(struct drm_device *dev)
5459 struct drm_i915_private *dev_priv = to_i915(dev);
5462 for_each_pipe(dev_priv, pipe) {
5463 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
5465 pipe_crc->opened = false;
5466 spin_lock_init(&pipe_crc->lock);
5467 init_waitqueue_head(&pipe_crc->wq);
5471 int i915_debugfs_register(struct drm_i915_private *dev_priv)
5473 struct drm_minor *minor = dev_priv->drm.primary;
5476 ret = i915_forcewake_create(minor->debugfs_root, minor);
5480 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5481 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5486 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5487 ret = i915_debugfs_create(minor->debugfs_root, minor,
5488 i915_debugfs_files[i].name,
5489 i915_debugfs_files[i].fops);
5494 return drm_debugfs_create_files(i915_debugfs_list,
5495 I915_DEBUGFS_ENTRIES,
5496 minor->debugfs_root, minor);
5499 void i915_debugfs_unregister(struct drm_i915_private *dev_priv)
5501 struct drm_minor *minor = dev_priv->drm.primary;
5504 drm_debugfs_remove_files(i915_debugfs_list,
5505 I915_DEBUGFS_ENTRIES, minor);
5507 drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
5510 for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5511 struct drm_info_list *info_list =
5512 (struct drm_info_list *)&i915_pipe_crc_data[i];
5514 drm_debugfs_remove_files(info_list, 1, minor);
5517 for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5518 struct drm_info_list *info_list =
5519 (struct drm_info_list *) i915_debugfs_files[i].fops;
5521 drm_debugfs_remove_files(info_list, 1, minor);
5526 /* DPCD dump start address. */
5527 unsigned int offset;
5528 /* DPCD dump end address, inclusive. If unset, .size will be used. */
5530 /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5532 /* Only valid for eDP. */
5536 static const struct dpcd_block i915_dpcd_debug[] = {
5537 { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5538 { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5539 { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5540 { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5541 { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5542 { .offset = DP_SET_POWER },
5543 { .offset = DP_EDP_DPCD_REV },
5544 { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5545 { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5546 { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5549 static int i915_dpcd_show(struct seq_file *m, void *data)
5551 struct drm_connector *connector = m->private;
5552 struct intel_dp *intel_dp =
5553 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5558 if (connector->status != connector_status_connected)
5561 for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5562 const struct dpcd_block *b = &i915_dpcd_debug[i];
5563 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5566 connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5569 /* low tech for now */
5570 if (WARN_ON(size > sizeof(buf)))
5573 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5575 DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5576 size, b->offset, err);
5580 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
5586 static int i915_dpcd_open(struct inode *inode, struct file *file)
5588 return single_open(file, i915_dpcd_show, inode->i_private);
5591 static const struct file_operations i915_dpcd_fops = {
5592 .owner = THIS_MODULE,
5593 .open = i915_dpcd_open,
5595 .llseek = seq_lseek,
5596 .release = single_release,
5600 * i915_debugfs_connector_add - add i915 specific connector debugfs files
5601 * @connector: pointer to a registered drm_connector
5603 * Cleanup will be done by drm_connector_unregister() through a call to
5604 * drm_debugfs_connector_remove().
5606 * Returns 0 on success, negative error codes on error.
5608 int i915_debugfs_connector_add(struct drm_connector *connector)
5610 struct dentry *root = connector->debugfs_entry;
5612 /* The connector must have been registered beforehands. */
5616 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5617 connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5618 debugfs_create_file("i915_dpcd", S_IRUGO, root, connector,