drivers/gpu/drm/i915/i915_debugfs.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *
  27  */
  28
  29 #include <linux/seq_file.h>
  30 #include <linux/circ_buf.h>
  31 #include <linux/ctype.h>
  32 #include <linux/debugfs.h>
  33 #include <linux/slab.h>
  34 #include <linux/export.h>
  35 #include <linux/list_sort.h>
  36 #include <asm/msr-index.h>
  37 #include <drm/drmP.h>
  38 #include "intel_drv.h"
  39 #include "intel_ringbuffer.h"
  40 #include <drm/i915_drm.h>
  41 #include "i915_drv.h"
  42
  43 static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
  44 {
  45         return to_i915(node->minor->dev);
  46 }
  47
  48 /* As the drm_debugfs_init() routines are called before dev->dev_private is
  49  * allocated we need to hook into the minor for release. */
  50 static int
  51 drm_add_fake_info_node(struct drm_minor *minor,
  52                        struct dentry *ent,
  53                        const void *key)
  54 {
  55         struct drm_info_node *node;
  56
  57         node = kmalloc(sizeof(*node), GFP_KERNEL);
  58         if (node == NULL) {
  59                 debugfs_remove(ent);
  60                 return -ENOMEM;
  61         }
  62
  63         node->minor = minor;
  64         node->dent = ent;
  65         node->info_ent = (void *)key;
  66
  67         mutex_lock(&minor->debugfs_lock);
  68         list_add(&node->list, &minor->debugfs_list);
  69         mutex_unlock(&minor->debugfs_lock);
  70
  71         return 0;
  72 }
  73
  74 static int i915_capabilities(struct seq_file *m, void *data)
  75 {
  76         struct drm_i915_private *dev_priv = node_to_i915(m->private);
  77         const struct intel_device_info *info = INTEL_INFO(dev_priv);
  78
  79         seq_printf(m, "gen: %d\n", INTEL_GEN(dev_priv));
  80         seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev_priv));
  81 #define PRINT_FLAG(x)  seq_printf(m, #x ": %s\n", yesno(info->x))
  82         DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
  83 #undef PRINT_FLAG
  84
  85         return 0;
  86 }
  87
  88 static char get_active_flag(struct drm_i915_gem_object *obj)
  89 {
  90         return i915_gem_object_is_active(obj) ? '*' : ' ';
  91 }
  92
  93 static char get_pin_flag(struct drm_i915_gem_object *obj)
  94 {
  95         return obj->pin_display ? 'p' : ' ';
  96 }
  97
  98 static char get_tiling_flag(struct drm_i915_gem_object *obj)
  99 {
 100         switch (i915_gem_object_get_tiling(obj)) {
 101         default:
 102         case I915_TILING_NONE: return ' ';
 103         case I915_TILING_X: return 'X';
 104         case I915_TILING_Y: return 'Y';
 105         }
 106 }
 107
 108 static char get_global_flag(struct drm_i915_gem_object *obj)
 109 {
 110         return !list_empty(&obj->userfault_link) ? 'g' : ' ';
 111 }
 112
 113 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
 114 {
 115         return obj->mapping ? 'M' : ' ';
 116 }
 117
 118 static u64 i915_gem_obj_total_ggtt_size(struct drm_i915_gem_object *obj)
 119 {
 120         u64 size = 0;
 121         struct i915_vma *vma;
 122
 123         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 124                 if (i915_vma_is_ggtt(vma) && drm_mm_node_allocated(&vma->node))
 125                         size += vma->node.size;
 126         }
 127
 128         return size;
 129 }
 130
 131 static void
 132 describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
 133 {
 134         struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
 135         struct intel_engine_cs *engine;
 136         struct i915_vma *vma;
 137         unsigned int frontbuffer_bits;
 138         int pin_count = 0;
 139         enum intel_engine_id id;
 140
 141         lockdep_assert_held(&obj->base.dev->struct_mutex);
 142
 143         seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x [ ",
 144                    &obj->base,
 145                    get_active_flag(obj),
 146                    get_pin_flag(obj),
 147                    get_tiling_flag(obj),
 148                    get_global_flag(obj),
 149                    get_pin_mapped_flag(obj),
 150                    obj->base.size / 1024,
 151                    obj->base.read_domains,
 152                    obj->base.write_domain);
 153         for_each_engine(engine, dev_priv, id)
 154                 seq_printf(m, "%x ",
 155                            i915_gem_active_get_seqno(&obj->last_read[id],
 156                                                      &obj->base.dev->struct_mutex));
 157         seq_printf(m, "] %x %s%s%s",
 158                    i915_gem_active_get_seqno(&obj->last_write,
 159                                              &obj->base.dev->struct_mutex),
 160                    i915_cache_level_str(dev_priv, obj->cache_level),
 161                    obj->dirty ? " dirty" : "",
 162                    obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
 163         if (obj->base.name)
 164                 seq_printf(m, " (name: %d)", obj->base.name);
 165         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 166                 if (i915_vma_is_pinned(vma))
 167                         pin_count++;
 168         }
 169         seq_printf(m, " (pinned x %d)", pin_count);
 170         if (obj->pin_display)
 171                 seq_printf(m, " (display)");
 172         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 173                 if (!drm_mm_node_allocated(&vma->node))
 174                         continue;
 175
 176                 seq_printf(m, " (%sgtt offset: %08llx, size: %08llx",
 177                            i915_vma_is_ggtt(vma) ? "g" : "pp",
 178                            vma->node.start, vma->node.size);
 179                 if (i915_vma_is_ggtt(vma))
 180                         seq_printf(m, ", type: %u", vma->ggtt_view.type);
 181                 if (vma->fence)
 182                         seq_printf(m, " , fence: %d%s",
 183                                    vma->fence->id,
 184                                    i915_gem_active_isset(&vma->last_fence) ? "*" : "");
 185                 seq_puts(m, ")");
 186         }
 187         if (obj->stolen)
 188                 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
 189
 190         engine = i915_gem_active_get_engine(&obj->last_write,
 191                                             &dev_priv->drm.struct_mutex);
 192         if (engine)
 193                 seq_printf(m, " (%s)", engine->name);
 194
 195         frontbuffer_bits = atomic_read(&obj->frontbuffer_bits);
 196         if (frontbuffer_bits)
 197                 seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits);
 198 }
 199
 200 static int obj_rank_by_stolen(void *priv,
 201                               struct list_head *A, struct list_head *B)
 202 {
 203         struct drm_i915_gem_object *a =
 204                 container_of(A, struct drm_i915_gem_object, obj_exec_link);
 205         struct drm_i915_gem_object *b =
 206                 container_of(B, struct drm_i915_gem_object, obj_exec_link);
 207
 208         if (a->stolen->start < b->stolen->start)
 209                 return -1;
 210         if (a->stolen->start > b->stolen->start)
 211                 return 1;
 212         return 0;
 213 }
 214
 215 static int i915_gem_stolen_list_info(struct seq_file *m, void *data)
 216 {
 217         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 218         struct drm_device *dev = &dev_priv->drm;
 219         struct drm_i915_gem_object *obj;
 220         u64 total_obj_size, total_gtt_size;
 221         LIST_HEAD(stolen);
 222         int count, ret;
 223
 224         ret = mutex_lock_interruptible(&dev->struct_mutex);
 225         if (ret)
 226                 return ret;
 227
 228         total_obj_size = total_gtt_size = count = 0;
 229         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 230                 if (obj->stolen == NULL)
 231                         continue;
 232
 233                 list_add(&obj->obj_exec_link, &stolen);
 234
 235                 total_obj_size += obj->base.size;
 236                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 237                 count++;
 238         }
 239         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 240                 if (obj->stolen == NULL)
 241                         continue;
 242
 243                 list_add(&obj->obj_exec_link, &stolen);
 244
 245                 total_obj_size += obj->base.size;
 246                 count++;
 247         }
 248         list_sort(NULL, &stolen, obj_rank_by_stolen);
 249         seq_puts(m, "Stolen:\n");
 250         while (!list_empty(&stolen)) {
 251                 obj = list_first_entry(&stolen, typeof(*obj), obj_exec_link);
 252                 seq_puts(m, "   ");
 253                 describe_obj(m, obj);
 254                 seq_putc(m, '\n');
 255                 list_del_init(&obj->obj_exec_link);
 256         }
 257         mutex_unlock(&dev->struct_mutex);
 258
 259         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 260                    count, total_obj_size, total_gtt_size);
 261         return 0;
 262 }
 263
 264 struct file_stats {
 265         struct drm_i915_file_private *file_priv;
 266         unsigned long count;
 267         u64 total, unbound;
 268         u64 global, shared;
 269         u64 active, inactive;
 270 };
 271
 272 static int per_file_stats(int id, void *ptr, void *data)
 273 {
 274         struct drm_i915_gem_object *obj = ptr;
 275         struct file_stats *stats = data;
 276         struct i915_vma *vma;
 277
 278         stats->count++;
 279         stats->total += obj->base.size;
 280         if (!obj->bind_count)
 281                 stats->unbound += obj->base.size;
 282         if (obj->base.name || obj->base.dma_buf)
 283                 stats->shared += obj->base.size;
 284
 285         list_for_each_entry(vma, &obj->vma_list, obj_link) {
 286                 if (!drm_mm_node_allocated(&vma->node))
 287                         continue;
 288
 289                 if (i915_vma_is_ggtt(vma)) {
 290                         stats->global += vma->node.size;
 291                 } else {
 292                         struct i915_hw_ppgtt *ppgtt = i915_vm_to_ppgtt(vma->vm);
 293
 294                         if (ppgtt->base.file != stats->file_priv)
 295                                 continue;
 296                 }
 297
 298                 if (i915_vma_is_active(vma))
 299                         stats->active += vma->node.size;
 300                 else
 301                         stats->inactive += vma->node.size;
 302         }
 303
 304         return 0;
 305 }
 306
 307 #define print_file_stats(m, name, stats) do { \
 308         if (stats.count) \
 309                 seq_printf(m, "%s: %lu objects, %llu bytes (%llu active, %llu inactive, %llu global, %llu shared, %llu unbound)\n", \
 310                            name, \
 311                            stats.count, \
 312                            stats.total, \
 313                            stats.active, \
 314                            stats.inactive, \
 315                            stats.global, \
 316                            stats.shared, \
 317                            stats.unbound); \
 318 } while (0)
 319
 320 static void print_batch_pool_stats(struct seq_file *m,
 321                                    struct drm_i915_private *dev_priv)
 322 {
 323         struct drm_i915_gem_object *obj;
 324         struct file_stats stats;
 325         struct intel_engine_cs *engine;
 326         enum intel_engine_id id;
 327         int j;
 328
 329         memset(&stats, 0, sizeof(stats));
 330
 331         for_each_engine(engine, dev_priv, id) {
 332                 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
 333                         list_for_each_entry(obj,
 334                                             &engine->batch_pool.cache_list[j],
 335                                             batch_pool_link)
 336                                 per_file_stats(0, obj, &stats);
 337                 }
 338         }
 339
 340         print_file_stats(m, "[k]batch pool", stats);
 341 }
 342
 343 static int per_file_ctx_stats(int id, void *ptr, void *data)
 344 {
 345         struct i915_gem_context *ctx = ptr;
 346         int n;
 347
 348         for (n = 0; n < ARRAY_SIZE(ctx->engine); n++) {
 349                 if (ctx->engine[n].state)
 350                         per_file_stats(0, ctx->engine[n].state->obj, data);
 351                 if (ctx->engine[n].ring)
 352                         per_file_stats(0, ctx->engine[n].ring->vma->obj, data);
 353         }
 354
 355         return 0;
 356 }
 357
 358 static void print_context_stats(struct seq_file *m,
 359                                 struct drm_i915_private *dev_priv)
 360 {
 361         struct drm_device *dev = &dev_priv->drm;
 362         struct file_stats stats;
 363         struct drm_file *file;
 364
 365         memset(&stats, 0, sizeof(stats));
 366
 367         mutex_lock(&dev->struct_mutex);
 368         if (dev_priv->kernel_context)
 369                 per_file_ctx_stats(0, dev_priv->kernel_context, &stats);
 370
 371         list_for_each_entry(file, &dev->filelist, lhead) {
 372                 struct drm_i915_file_private *fpriv = file->driver_priv;
 373                 idr_for_each(&fpriv->context_idr, per_file_ctx_stats, &stats);
 374         }
 375         mutex_unlock(&dev->struct_mutex);
 376
 377         print_file_stats(m, "[k]contexts", stats);
 378 }
 379
 380 static int i915_gem_object_info(struct seq_file *m, void *data)
 381 {
 382         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 383         struct drm_device *dev = &dev_priv->drm;
 384         struct i915_ggtt *ggtt = &dev_priv->ggtt;
 385         u32 count, mapped_count, purgeable_count, dpy_count;
 386         u64 size, mapped_size, purgeable_size, dpy_size;
 387         struct drm_i915_gem_object *obj;
 388         struct drm_file *file;
 389         int ret;
 390
 391         ret = mutex_lock_interruptible(&dev->struct_mutex);
 392         if (ret)
 393                 return ret;
 394
 395         seq_printf(m, "%u objects, %llu bytes\n",
 396                    dev_priv->mm.object_count,
 397                    dev_priv->mm.object_memory);
 398
 399         size = count = 0;
 400         mapped_size = mapped_count = 0;
 401         purgeable_size = purgeable_count = 0;
 402         list_for_each_entry(obj, &dev_priv->mm.unbound_list, global_list) {
 403                 size += obj->base.size;
 404                 ++count;
 405
 406                 if (obj->madv == I915_MADV_DONTNEED) {
 407                         purgeable_size += obj->base.size;
 408                         ++purgeable_count;
 409                 }
 410
 411                 if (obj->mapping) {
 412                         mapped_count++;
 413                         mapped_size += obj->base.size;
 414                 }
 415         }
 416         seq_printf(m, "%u unbound objects, %llu bytes\n", count, size);
 417
 418         size = count = dpy_size = dpy_count = 0;
 419         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 420                 size += obj->base.size;
 421                 ++count;
 422
 423                 if (obj->pin_display) {
 424                         dpy_size += obj->base.size;
 425                         ++dpy_count;
 426                 }
 427
 428                 if (obj->madv == I915_MADV_DONTNEED) {
 429                         purgeable_size += obj->base.size;
 430                         ++purgeable_count;
 431                 }
 432
 433                 if (obj->mapping) {
 434                         mapped_count++;
 435                         mapped_size += obj->base.size;
 436                 }
 437         }
 438         seq_printf(m, "%u bound objects, %llu bytes\n",
 439                    count, size);
 440         seq_printf(m, "%u purgeable objects, %llu bytes\n",
 441                    purgeable_count, purgeable_size);
 442         seq_printf(m, "%u mapped objects, %llu bytes\n",
 443                    mapped_count, mapped_size);
 444         seq_printf(m, "%u display objects (pinned), %llu bytes\n",
 445                    dpy_count, dpy_size);
 446
 447         seq_printf(m, "%llu [%llu] gtt total\n",
 448                    ggtt->base.total, ggtt->mappable_end - ggtt->base.start);
 449
 450         seq_putc(m, '\n');
 451         print_batch_pool_stats(m, dev_priv);
 452         mutex_unlock(&dev->struct_mutex);
 453
 454         mutex_lock(&dev->filelist_mutex);
 455         print_context_stats(m, dev_priv);
 456         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
 457                 struct file_stats stats;
 458                 struct drm_i915_file_private *file_priv = file->driver_priv;
 459                 struct drm_i915_gem_request *request;
 460                 struct task_struct *task;
 461
 462                 memset(&stats, 0, sizeof(stats));
 463                 stats.file_priv = file->driver_priv;
 464                 spin_lock(&file->table_lock);
 465                 idr_for_each(&file->object_idr, per_file_stats, &stats);
 466                 spin_unlock(&file->table_lock);
 467                 /*
 468                  * Although we have a valid reference on file->pid, that does
 469                  * not guarantee that the task_struct who called get_pid() is
 470                  * still alive (e.g. get_pid(current) => fork() => exit()).
 471                  * Therefore, we need to protect this ->comm access using RCU.
 472                  */
 473                 mutex_lock(&dev->struct_mutex);
 474                 request = list_first_entry_or_null(&file_priv->mm.request_list,
 475                                                    struct drm_i915_gem_request,
 476                                                    client_list);
 477                 rcu_read_lock();
 478                 task = pid_task(request && request->ctx->pid ?
 479                                 request->ctx->pid : file->pid,
 480                                 PIDTYPE_PID);
 481                 print_file_stats(m, task ? task->comm : "<unknown>", stats);
 482                 rcu_read_unlock();
 483                 mutex_unlock(&dev->struct_mutex);
 484         }
 485         mutex_unlock(&dev->filelist_mutex);
 486
 487         return 0;
 488 }
 489
 490 static int i915_gem_gtt_info(struct seq_file *m, void *data)
 491 {
 492         struct drm_info_node *node = m->private;
 493         struct drm_i915_private *dev_priv = node_to_i915(node);
 494         struct drm_device *dev = &dev_priv->drm;
 495         bool show_pin_display_only = !!node->info_ent->data;
 496         struct drm_i915_gem_object *obj;
 497         u64 total_obj_size, total_gtt_size;
 498         int count, ret;
 499
 500         ret = mutex_lock_interruptible(&dev->struct_mutex);
 501         if (ret)
 502                 return ret;
 503
 504         total_obj_size = total_gtt_size = count = 0;
 505         list_for_each_entry(obj, &dev_priv->mm.bound_list, global_list) {
 506                 if (show_pin_display_only && !obj->pin_display)
 507                         continue;
 508
 509                 seq_puts(m, "   ");
 510                 describe_obj(m, obj);
 511                 seq_putc(m, '\n');
 512                 total_obj_size += obj->base.size;
 513                 total_gtt_size += i915_gem_obj_total_ggtt_size(obj);
 514                 count++;
 515         }
 516
 517         mutex_unlock(&dev->struct_mutex);
 518
 519         seq_printf(m, "Total %d objects, %llu bytes, %llu GTT size\n",
 520                    count, total_obj_size, total_gtt_size);
 521
 522         return 0;
 523 }
 524
 525 static int i915_gem_pageflip_info(struct seq_file *m, void *data)
 526 {
 527         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 528         struct drm_device *dev = &dev_priv->drm;
 529         struct intel_crtc *crtc;
 530         int ret;
 531
 532         ret = mutex_lock_interruptible(&dev->struct_mutex);
 533         if (ret)
 534                 return ret;
 535
 536         for_each_intel_crtc(dev, crtc) {
 537                 const char pipe = pipe_name(crtc->pipe);
 538                 const char plane = plane_name(crtc->plane);
 539                 struct intel_flip_work *work;
 540
 541                 spin_lock_irq(&dev->event_lock);
 542                 work = crtc->flip_work;
 543                 if (work == NULL) {
 544                         seq_printf(m, "No flip due on pipe %c (plane %c)\n",
 545                                    pipe, plane);
 546                 } else {
 547                         u32 pending;
 548                         u32 addr;
 549
 550                         pending = atomic_read(&work->pending);
 551                         if (pending) {
 552                                 seq_printf(m, "Flip ioctl preparing on pipe %c (plane %c)\n",
 553                                            pipe, plane);
 554                         } else {
 555                                 seq_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
 556                                            pipe, plane);
 557                         }
 558                         if (work->flip_queued_req) {
 559                                 struct intel_engine_cs *engine = i915_gem_request_get_engine(work->flip_queued_req);
 560
 561                                 seq_printf(m, "Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d\n",
 562                                            engine->name,
 563                                            i915_gem_request_get_seqno(work->flip_queued_req),
 564                                            dev_priv->next_seqno,
 565                                            intel_engine_get_seqno(engine),
 566                                            i915_gem_request_completed(work->flip_queued_req));
 567                         } else
 568                                 seq_printf(m, "Flip not associated with any ring\n");
 569                         seq_printf(m, "Flip queued on frame %d, (was ready on frame %d), now %d\n",
 570                                    work->flip_queued_vblank,
 571                                    work->flip_ready_vblank,
 572                                    intel_crtc_get_vblank_counter(crtc));
 573                         seq_printf(m, "%d prepares\n", atomic_read(&work->pending));
 574
 575                         if (INTEL_GEN(dev_priv) >= 4)
 576                                 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(crtc->plane)));
 577                         else
 578                                 addr = I915_READ(DSPADDR(crtc->plane));
 579                         seq_printf(m, "Current scanout address 0x%08x\n", addr);
 580
 581                         if (work->pending_flip_obj) {
 582                                 seq_printf(m, "New framebuffer address 0x%08lx\n", (long)work->gtt_offset);
 583                                 seq_printf(m, "MMIO update completed? %d\n",  addr == work->gtt_offset);
 584                         }
 585                 }
 586                 spin_unlock_irq(&dev->event_lock);
 587         }
 588
 589         mutex_unlock(&dev->struct_mutex);
 590
 591         return 0;
 592 }
 593
 594 static int i915_gem_batch_pool_info(struct seq_file *m, void *data)
 595 {
 596         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 597         struct drm_device *dev = &dev_priv->drm;
 598         struct drm_i915_gem_object *obj;
 599         struct intel_engine_cs *engine;
 600         enum intel_engine_id id;
 601         int total = 0;
 602         int ret, j;
 603
 604         ret = mutex_lock_interruptible(&dev->struct_mutex);
 605         if (ret)
 606                 return ret;
 607
 608         for_each_engine(engine, dev_priv, id) {
 609                 for (j = 0; j < ARRAY_SIZE(engine->batch_pool.cache_list); j++) {
 610                         int count;
 611
 612                         count = 0;
 613                         list_for_each_entry(obj,
 614                                             &engine->batch_pool.cache_list[j],
 615                                             batch_pool_link)
 616                                 count++;
 617                         seq_printf(m, "%s cache[%d]: %d objects\n",
 618                                    engine->name, j, count);
 619
 620                         list_for_each_entry(obj,
 621                                             &engine->batch_pool.cache_list[j],
 622                                             batch_pool_link) {
 623                                 seq_puts(m, "   ");
 624                                 describe_obj(m, obj);
 625                                 seq_putc(m, '\n');
 626                         }
 627
 628                         total += count;
 629                 }
 630         }
 631
 632         seq_printf(m, "total: %d\n", total);
 633
 634         mutex_unlock(&dev->struct_mutex);
 635
 636         return 0;
 637 }
 638
 639 static void print_request(struct seq_file *m,
 640                           struct drm_i915_gem_request *rq,
 641                           const char *prefix)
 642 {
 643         struct pid *pid = rq->ctx->pid;
 644         struct task_struct *task;
 645
 646         rcu_read_lock();
 647         task = pid ? pid_task(pid, PIDTYPE_PID) : NULL;
 648         seq_printf(m, "%s%x [%x:%x] @ %d: %s [%d]\n", prefix,
 649                    rq->fence.seqno, rq->ctx->hw_id, rq->fence.seqno,
 650                    jiffies_to_msecs(jiffies - rq->emitted_jiffies),
 651                    task ? task->comm : "<unknown>",
 652                    task ? task->pid : -1);
 653         rcu_read_unlock();
 654 }
 655
 656 static int i915_gem_request_info(struct seq_file *m, void *data)
 657 {
 658         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 659         struct drm_device *dev = &dev_priv->drm;
 660         struct drm_i915_gem_request *req;
 661         struct intel_engine_cs *engine;
 662         enum intel_engine_id id;
 663         int ret, any;
 664
 665         ret = mutex_lock_interruptible(&dev->struct_mutex);
 666         if (ret)
 667                 return ret;
 668
 669         any = 0;
 670         for_each_engine(engine, dev_priv, id) {
 671                 int count;
 672
 673                 count = 0;
 674                 list_for_each_entry(req, &engine->request_list, link)
 675                         count++;
 676                 if (count == 0)
 677                         continue;
 678
 679                 seq_printf(m, "%s requests: %d\n", engine->name, count);
 680                 list_for_each_entry(req, &engine->request_list, link)
 681                         print_request(m, req, "    ");
 682
 683                 any++;
 684         }
 685         mutex_unlock(&dev->struct_mutex);
 686
 687         if (any == 0)
 688                 seq_puts(m, "No requests\n");
 689
 690         return 0;
 691 }
 692
 693 static void i915_ring_seqno_info(struct seq_file *m,
 694                                  struct intel_engine_cs *engine)
 695 {
 696         struct intel_breadcrumbs *b = &engine->breadcrumbs;
 697         struct rb_node *rb;
 698
 699         seq_printf(m, "Current sequence (%s): %x\n",
 700                    engine->name, intel_engine_get_seqno(engine));
 701
 702         spin_lock(&b->lock);
 703         for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
 704                 struct intel_wait *w = container_of(rb, typeof(*w), node);
 705
 706                 seq_printf(m, "Waiting (%s): %s [%d] on %x\n",
 707                            engine->name, w->tsk->comm, w->tsk->pid, w->seqno);
 708         }
 709         spin_unlock(&b->lock);
 710 }
 711
 712 static int i915_gem_seqno_info(struct seq_file *m, void *data)
 713 {
 714         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 715         struct intel_engine_cs *engine;
 716         enum intel_engine_id id;
 717
 718         for_each_engine(engine, dev_priv, id)
 719                 i915_ring_seqno_info(m, engine);
 720
 721         return 0;
 722 }
 723
 724
 725 static int i915_interrupt_info(struct seq_file *m, void *data)
 726 {
 727         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 728         struct intel_engine_cs *engine;
 729         enum intel_engine_id id;
 730         int i, pipe;
 731
 732         intel_runtime_pm_get(dev_priv);
 733
 734         if (IS_CHERRYVIEW(dev_priv)) {
 735                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 736                            I915_READ(GEN8_MASTER_IRQ));
 737
 738                 seq_printf(m, "Display IER:\t%08x\n",
 739                            I915_READ(VLV_IER));
 740                 seq_printf(m, "Display IIR:\t%08x\n",
 741                            I915_READ(VLV_IIR));
 742                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 743                            I915_READ(VLV_IIR_RW));
 744                 seq_printf(m, "Display IMR:\t%08x\n",
 745                            I915_READ(VLV_IMR));
 746                 for_each_pipe(dev_priv, pipe) {
 747                         enum intel_display_power_domain power_domain;
 748
 749                         power_domain = POWER_DOMAIN_PIPE(pipe);
 750                         if (!intel_display_power_get_if_enabled(dev_priv,
 751                                                                 power_domain)) {
 752                                 seq_printf(m, "Pipe %c power disabled\n",
 753                                            pipe_name(pipe));
 754                                 continue;
 755                         }
 756
 757                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 758                                    pipe_name(pipe),
 759                                    I915_READ(PIPESTAT(pipe)));
 760
 761                         intel_display_power_put(dev_priv, power_domain);
 762                 }
 763
 764                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 765                 seq_printf(m, "Port hotplug:\t%08x\n",
 766                            I915_READ(PORT_HOTPLUG_EN));
 767                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 768                            I915_READ(VLV_DPFLIPSTAT));
 769                 seq_printf(m, "DPINVGTT:\t%08x\n",
 770                            I915_READ(DPINVGTT));
 771                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 772
 773                 for (i = 0; i < 4; i++) {
 774                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 775                                    i, I915_READ(GEN8_GT_IMR(i)));
 776                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 777                                    i, I915_READ(GEN8_GT_IIR(i)));
 778                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 779                                    i, I915_READ(GEN8_GT_IER(i)));
 780                 }
 781
 782                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 783                            I915_READ(GEN8_PCU_IMR));
 784                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 785                            I915_READ(GEN8_PCU_IIR));
 786                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 787                            I915_READ(GEN8_PCU_IER));
 788         } else if (INTEL_GEN(dev_priv) >= 8) {
 789                 seq_printf(m, "Master Interrupt Control:\t%08x\n",
 790                            I915_READ(GEN8_MASTER_IRQ));
 791
 792                 for (i = 0; i < 4; i++) {
 793                         seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
 794                                    i, I915_READ(GEN8_GT_IMR(i)));
 795                         seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
 796                                    i, I915_READ(GEN8_GT_IIR(i)));
 797                         seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
 798                                    i, I915_READ(GEN8_GT_IER(i)));
 799                 }
 800
 801                 for_each_pipe(dev_priv, pipe) {
 802                         enum intel_display_power_domain power_domain;
 803
 804                         power_domain = POWER_DOMAIN_PIPE(pipe);
 805                         if (!intel_display_power_get_if_enabled(dev_priv,
 806                                                                 power_domain)) {
 807                                 seq_printf(m, "Pipe %c power disabled\n",
 808                                            pipe_name(pipe));
 809                                 continue;
 810                         }
 811                         seq_printf(m, "Pipe %c IMR:\t%08x\n",
 812                                    pipe_name(pipe),
 813                                    I915_READ(GEN8_DE_PIPE_IMR(pipe)));
 814                         seq_printf(m, "Pipe %c IIR:\t%08x\n",
 815                                    pipe_name(pipe),
 816                                    I915_READ(GEN8_DE_PIPE_IIR(pipe)));
 817                         seq_printf(m, "Pipe %c IER:\t%08x\n",
 818                                    pipe_name(pipe),
 819                                    I915_READ(GEN8_DE_PIPE_IER(pipe)));
 820
 821                         intel_display_power_put(dev_priv, power_domain);
 822                 }
 823
 824                 seq_printf(m, "Display Engine port interrupt mask:\t%08x\n",
 825                            I915_READ(GEN8_DE_PORT_IMR));
 826                 seq_printf(m, "Display Engine port interrupt identity:\t%08x\n",
 827                            I915_READ(GEN8_DE_PORT_IIR));
 828                 seq_printf(m, "Display Engine port interrupt enable:\t%08x\n",
 829                            I915_READ(GEN8_DE_PORT_IER));
 830
 831                 seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n",
 832                            I915_READ(GEN8_DE_MISC_IMR));
 833                 seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n",
 834                            I915_READ(GEN8_DE_MISC_IIR));
 835                 seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n",
 836                            I915_READ(GEN8_DE_MISC_IER));
 837
 838                 seq_printf(m, "PCU interrupt mask:\t%08x\n",
 839                            I915_READ(GEN8_PCU_IMR));
 840                 seq_printf(m, "PCU interrupt identity:\t%08x\n",
 841                            I915_READ(GEN8_PCU_IIR));
 842                 seq_printf(m, "PCU interrupt enable:\t%08x\n",
 843                            I915_READ(GEN8_PCU_IER));
 844         } else if (IS_VALLEYVIEW(dev_priv)) {
 845                 seq_printf(m, "Display IER:\t%08x\n",
 846                            I915_READ(VLV_IER));
 847                 seq_printf(m, "Display IIR:\t%08x\n",
 848                            I915_READ(VLV_IIR));
 849                 seq_printf(m, "Display IIR_RW:\t%08x\n",
 850                            I915_READ(VLV_IIR_RW));
 851                 seq_printf(m, "Display IMR:\t%08x\n",
 852                            I915_READ(VLV_IMR));
 853                 for_each_pipe(dev_priv, pipe)
 854                         seq_printf(m, "Pipe %c stat:\t%08x\n",
 855                                    pipe_name(pipe),
 856                                    I915_READ(PIPESTAT(pipe)));
 857
 858                 seq_printf(m, "Master IER:\t%08x\n",
 859                            I915_READ(VLV_MASTER_IER));
 860
 861                 seq_printf(m, "Render IER:\t%08x\n",
 862                            I915_READ(GTIER));
 863                 seq_printf(m, "Render IIR:\t%08x\n",
 864                            I915_READ(GTIIR));
 865                 seq_printf(m, "Render IMR:\t%08x\n",
 866                            I915_READ(GTIMR));
 867
 868                 seq_printf(m, "PM IER:\t\t%08x\n",
 869                            I915_READ(GEN6_PMIER));
 870                 seq_printf(m, "PM IIR:\t\t%08x\n",
 871                            I915_READ(GEN6_PMIIR));
 872                 seq_printf(m, "PM IMR:\t\t%08x\n",
 873                            I915_READ(GEN6_PMIMR));
 874
 875                 seq_printf(m, "Port hotplug:\t%08x\n",
 876                            I915_READ(PORT_HOTPLUG_EN));
 877                 seq_printf(m, "DPFLIPSTAT:\t%08x\n",
 878                            I915_READ(VLV_DPFLIPSTAT));
 879                 seq_printf(m, "DPINVGTT:\t%08x\n",
 880                            I915_READ(DPINVGTT));
 881
 882         } else if (!HAS_PCH_SPLIT(dev_priv)) {
 883                 seq_printf(m, "Interrupt enable:    %08x\n",
 884                            I915_READ(IER));
 885                 seq_printf(m, "Interrupt identity:  %08x\n",
 886                            I915_READ(IIR));
 887                 seq_printf(m, "Interrupt mask:      %08x\n",
 888                            I915_READ(IMR));
 889                 for_each_pipe(dev_priv, pipe)
 890                         seq_printf(m, "Pipe %c stat:         %08x\n",
 891                                    pipe_name(pipe),
 892                                    I915_READ(PIPESTAT(pipe)));
 893         } else {
 894                 seq_printf(m, "North Display Interrupt enable:          %08x\n",
 895                            I915_READ(DEIER));
 896                 seq_printf(m, "North Display Interrupt identity:        %08x\n",
 897                            I915_READ(DEIIR));
 898                 seq_printf(m, "North Display Interrupt mask:            %08x\n",
 899                            I915_READ(DEIMR));
 900                 seq_printf(m, "South Display Interrupt enable:          %08x\n",
 901                            I915_READ(SDEIER));
 902                 seq_printf(m, "South Display Interrupt identity:        %08x\n",
 903                            I915_READ(SDEIIR));
 904                 seq_printf(m, "South Display Interrupt mask:            %08x\n",
 905                            I915_READ(SDEIMR));
 906                 seq_printf(m, "Graphics Interrupt enable:               %08x\n",
 907                            I915_READ(GTIER));
 908                 seq_printf(m, "Graphics Interrupt identity:             %08x\n",
 909                            I915_READ(GTIIR));
 910                 seq_printf(m, "Graphics Interrupt mask:         %08x\n",
 911                            I915_READ(GTIMR));
 912         }
 913         for_each_engine(engine, dev_priv, id) {
 914                 if (INTEL_GEN(dev_priv) >= 6) {
 915                         seq_printf(m,
 916                                    "Graphics Interrupt mask (%s):       %08x\n",
 917                                    engine->name, I915_READ_IMR(engine));
 918                 }
 919                 i915_ring_seqno_info(m, engine);
 920         }
 921         intel_runtime_pm_put(dev_priv);
 922
 923         return 0;
 924 }
 925
 926 static int i915_gem_fence_regs_info(struct seq_file *m, void *data)
 927 {
 928         struct drm_i915_private *dev_priv = node_to_i915(m->private);
 929         struct drm_device *dev = &dev_priv->drm;
 930         int i, ret;
 931
 932         ret = mutex_lock_interruptible(&dev->struct_mutex);
 933         if (ret)
 934                 return ret;
 935
 936         seq_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
 937         for (i = 0; i < dev_priv->num_fence_regs; i++) {
 938                 struct i915_vma *vma = dev_priv->fence_regs[i].vma;
 939
 940                 seq_printf(m, "Fence %d, pin count = %d, object = ",
 941                            i, dev_priv->fence_regs[i].pin_count);
 942                 if (!vma)
 943                         seq_puts(m, "unused");
 944                 else
 945                         describe_obj(m, vma->obj);
 946                 seq_putc(m, '\n');
 947         }
 948
 949         mutex_unlock(&dev->struct_mutex);
 950         return 0;
 951 }
 952
 953 static int i915_hws_info(struct seq_file *m, void *data)
 954 {
 955         struct drm_info_node *node = m->private;
 956         struct drm_i915_private *dev_priv = node_to_i915(node);
 957         struct intel_engine_cs *engine;
 958         const u32 *hws;
 959         int i;
 960
 961         engine = dev_priv->engine[(uintptr_t)node->info_ent->data];
 962         hws = engine->status_page.page_addr;
 963         if (hws == NULL)
 964                 return 0;
 965
 966         for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
 967                 seq_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
 968                            i * 4,
 969                            hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
 970         }
 971         return 0;
 972 }
 973
 974 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
 975
 976 static ssize_t
 977 i915_error_state_write(struct file *filp,
 978                        const char __user *ubuf,
 979                        size_t cnt,
 980                        loff_t *ppos)
 981 {
 982         struct i915_error_state_file_priv *error_priv = filp->private_data;
 983
 984         DRM_DEBUG_DRIVER("Resetting error state\n");
 985         i915_destroy_error_state(error_priv->dev);
 986
 987         return cnt;
 988 }
 989
 990 static int i915_error_state_open(struct inode *inode, struct file *file)
 991 {
 992         struct drm_i915_private *dev_priv = inode->i_private;
 993         struct i915_error_state_file_priv *error_priv;
 994
 995         error_priv = kzalloc(sizeof(*error_priv), GFP_KERNEL);
 996         if (!error_priv)
 997                 return -ENOMEM;
 998
 999         error_priv->dev = &dev_priv->drm;
1000
1001         i915_error_state_get(&dev_priv->drm, error_priv);
1002
1003         file->private_data = error_priv;
1004
1005         return 0;
1006 }
1007
1008 static int i915_error_state_release(struct inode *inode, struct file *file)
1009 {
1010         struct i915_error_state_file_priv *error_priv = file->private_data;
1011
1012         i915_error_state_put(error_priv);
1013         kfree(error_priv);
1014
1015         return 0;
1016 }
1017
1018 static ssize_t i915_error_state_read(struct file *file, char __user *userbuf,
1019                                      size_t count, loff_t *pos)
1020 {
1021         struct i915_error_state_file_priv *error_priv = file->private_data;
1022         struct drm_i915_error_state_buf error_str;
1023         loff_t tmp_pos = 0;
1024         ssize_t ret_count = 0;
1025         int ret;
1026
1027         ret = i915_error_state_buf_init(&error_str,
1028                                         to_i915(error_priv->dev), count, *pos);
1029         if (ret)
1030                 return ret;
1031
1032         ret = i915_error_state_to_str(&error_str, error_priv);
1033         if (ret)
1034                 goto out;
1035
1036         ret_count = simple_read_from_buffer(userbuf, count, &tmp_pos,
1037                                             error_str.buf,
1038                                             error_str.bytes);
1039
1040         if (ret_count < 0)
1041                 ret = ret_count;
1042         else
1043                 *pos = error_str.start + ret_count;
1044 out:
1045         i915_error_state_buf_release(&error_str);
1046         return ret ?: ret_count;
1047 }
1048
1049 static const struct file_operations i915_error_state_fops = {
1050         .owner = THIS_MODULE,
1051         .open = i915_error_state_open,
1052         .read = i915_error_state_read,
1053         .write = i915_error_state_write,
1054         .llseek = default_llseek,
1055         .release = i915_error_state_release,
1056 };
1057
1058 #endif
1059
1060 static int
1061 i915_next_seqno_get(void *data, u64 *val)
1062 {
1063         struct drm_i915_private *dev_priv = data;
1064         int ret;
1065
1066         ret = mutex_lock_interruptible(&dev_priv->drm.struct_mutex);
1067         if (ret)
1068                 return ret;
1069
1070         *val = dev_priv->next_seqno;
1071         mutex_unlock(&dev_priv->drm.struct_mutex);
1072
1073         return 0;
1074 }
1075
1076 static int
1077 i915_next_seqno_set(void *data, u64 val)
1078 {
1079         struct drm_i915_private *dev_priv = data;
1080         struct drm_device *dev = &dev_priv->drm;
1081         int ret;
1082
1083         ret = mutex_lock_interruptible(&dev->struct_mutex);
1084         if (ret)
1085                 return ret;
1086
1087         ret = i915_gem_set_seqno(dev, val);
1088         mutex_unlock(&dev->struct_mutex);
1089
1090         return ret;
1091 }
1092
1093 DEFINE_SIMPLE_ATTRIBUTE(i915_next_seqno_fops,
1094                         i915_next_seqno_get, i915_next_seqno_set,
1095                         "0x%llx\n");
1096
1097 static int i915_frequency_info(struct seq_file *m, void *unused)
1098 {
1099         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1100         struct drm_device *dev = &dev_priv->drm;
1101         int ret = 0;
1102
1103         intel_runtime_pm_get(dev_priv);
1104
1105         if (IS_GEN5(dev_priv)) {
1106                 u16 rgvswctl = I915_READ16(MEMSWCTL);
1107                 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
1108
1109                 seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
1110                 seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
1111                 seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
1112                            MEMSTAT_VID_SHIFT);
1113                 seq_printf(m, "Current P-state: %d\n",
1114                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
1115         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1116                 u32 freq_sts;
1117
1118                 mutex_lock(&dev_priv->rps.hw_lock);
1119                 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
1120                 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1121                 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1122
1123                 seq_printf(m, "actual GPU freq: %d MHz\n",
1124                            intel_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1125
1126                 seq_printf(m, "current GPU freq: %d MHz\n",
1127                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1128
1129                 seq_printf(m, "max GPU freq: %d MHz\n",
1130                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1131
1132                 seq_printf(m, "min GPU freq: %d MHz\n",
1133                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1134
1135                 seq_printf(m, "idle GPU freq: %d MHz\n",
1136                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1137
1138                 seq_printf(m,
1139                            "efficient (RPe) frequency: %d MHz\n",
1140                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1141                 mutex_unlock(&dev_priv->rps.hw_lock);
1142         } else if (INTEL_GEN(dev_priv) >= 6) {
1143                 u32 rp_state_limits;
1144                 u32 gt_perf_status;
1145                 u32 rp_state_cap;
1146                 u32 rpmodectl, rpinclimit, rpdeclimit;
1147                 u32 rpstat, cagf, reqf;
1148                 u32 rpupei, rpcurup, rpprevup;
1149                 u32 rpdownei, rpcurdown, rpprevdown;
1150                 u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
1151                 int max_freq;
1152
1153                 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
1154                 if (IS_BROXTON(dev_priv)) {
1155                         rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
1156                         gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
1157                 } else {
1158                         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
1159                         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
1160                 }
1161
1162                 /* RPSTAT1 is in the GT power well */
1163                 ret = mutex_lock_interruptible(&dev->struct_mutex);
1164                 if (ret)
1165                         goto out;
1166
1167                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
1168
1169                 reqf = I915_READ(GEN6_RPNSWREQ);
1170                 if (IS_GEN9(dev_priv))
1171                         reqf >>= 23;
1172                 else {
1173                         reqf &= ~GEN6_TURBO_DISABLE;
1174                         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1175                                 reqf >>= 24;
1176                         else
1177                                 reqf >>= 25;
1178                 }
1179                 reqf = intel_gpu_freq(dev_priv, reqf);
1180
1181                 rpmodectl = I915_READ(GEN6_RP_CONTROL);
1182                 rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
1183                 rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
1184
1185                 rpstat = I915_READ(GEN6_RPSTAT1);
1186                 rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
1187                 rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
1188                 rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
1189                 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
1190                 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
1191                 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
1192                 if (IS_GEN9(dev_priv))
1193                         cagf = (rpstat & GEN9_CAGF_MASK) >> GEN9_CAGF_SHIFT;
1194                 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
1195                         cagf = (rpstat & HSW_CAGF_MASK) >> HSW_CAGF_SHIFT;
1196                 else
1197                         cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
1198                 cagf = intel_gpu_freq(dev_priv, cagf);
1199
1200                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
1201                 mutex_unlock(&dev->struct_mutex);
1202
1203                 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
1204                         pm_ier = I915_READ(GEN6_PMIER);
1205                         pm_imr = I915_READ(GEN6_PMIMR);
1206                         pm_isr = I915_READ(GEN6_PMISR);
1207                         pm_iir = I915_READ(GEN6_PMIIR);
1208                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1209                 } else {
1210                         pm_ier = I915_READ(GEN8_GT_IER(2));
1211                         pm_imr = I915_READ(GEN8_GT_IMR(2));
1212                         pm_isr = I915_READ(GEN8_GT_ISR(2));
1213                         pm_iir = I915_READ(GEN8_GT_IIR(2));
1214                         pm_mask = I915_READ(GEN6_PMINTRMSK);
1215                 }
1216                 seq_printf(m, "PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x\n",
1217                            pm_ier, pm_imr, pm_isr, pm_iir, pm_mask);
1218                 seq_printf(m, "pm_intr_keep: 0x%08x\n", dev_priv->rps.pm_intr_keep);
1219                 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
1220                 seq_printf(m, "Render p-state ratio: %d\n",
1221                            (gt_perf_status & (IS_GEN9(dev_priv) ? 0x1ff00 : 0xff00)) >> 8);
1222                 seq_printf(m, "Render p-state VID: %d\n",
1223                            gt_perf_status & 0xff);
1224                 seq_printf(m, "Render p-state limit: %d\n",
1225                            rp_state_limits & 0xff);
1226                 seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
1227                 seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
1228                 seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
1229                 seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
1230                 seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
1231                 seq_printf(m, "CAGF: %dMHz\n", cagf);
1232                 seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
1233                            rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei));
1234                 seq_printf(m, "RP CUR UP: %d (%dus)\n",
1235                            rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
1236                 seq_printf(m, "RP PREV UP: %d (%dus)\n",
1237                            rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
1238                 seq_printf(m, "Up threshold: %d%%\n",
1239                            dev_priv->rps.up_threshold);
1240
1241                 seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
1242                            rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
1243                 seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
1244                            rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown));
1245                 seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
1246                            rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown));
1247                 seq_printf(m, "Down threshold: %d%%\n",
1248                            dev_priv->rps.down_threshold);
1249
1250                 max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 0 :
1251                             rp_state_cap >> 16) & 0xff;
1252                 max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1253                              GEN9_FREQ_SCALER : 1);
1254                 seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
1255                            intel_gpu_freq(dev_priv, max_freq));
1256
1257                 max_freq = (rp_state_cap & 0xff00) >> 8;
1258                 max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1259                              GEN9_FREQ_SCALER : 1);
1260                 seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
1261                            intel_gpu_freq(dev_priv, max_freq));
1262
1263                 max_freq = (IS_BROXTON(dev_priv) ? rp_state_cap >> 16 :
1264                             rp_state_cap >> 0) & 0xff;
1265                 max_freq *= (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1266                              GEN9_FREQ_SCALER : 1);
1267                 seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
1268                            intel_gpu_freq(dev_priv, max_freq));
1269                 seq_printf(m, "Max overclocked frequency: %dMHz\n",
1270                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1271
1272                 seq_printf(m, "Current freq: %d MHz\n",
1273                            intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
1274                 seq_printf(m, "Actual freq: %d MHz\n", cagf);
1275                 seq_printf(m, "Idle freq: %d MHz\n",
1276                            intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq));
1277                 seq_printf(m, "Min freq: %d MHz\n",
1278                            intel_gpu_freq(dev_priv, dev_priv->rps.min_freq));
1279                 seq_printf(m, "Boost freq: %d MHz\n",
1280                            intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
1281                 seq_printf(m, "Max freq: %d MHz\n",
1282                            intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
1283                 seq_printf(m,
1284                            "efficient (RPe) frequency: %d MHz\n",
1285                            intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq));
1286         } else {
1287                 seq_puts(m, "no P-state info available\n");
1288         }
1289
1290         seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk_freq);
1291         seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
1292         seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
1293
1294 out:
1295         intel_runtime_pm_put(dev_priv);
1296         return ret;
1297 }
1298
1299 static void i915_instdone_info(struct drm_i915_private *dev_priv,
1300                                struct seq_file *m,
1301                                struct intel_instdone *instdone)
1302 {
1303         int slice;
1304         int subslice;
1305
1306         seq_printf(m, "\t\tINSTDONE: 0x%08x\n",
1307                    instdone->instdone);
1308
1309         if (INTEL_GEN(dev_priv) <= 3)
1310                 return;
1311
1312         seq_printf(m, "\t\tSC_INSTDONE: 0x%08x\n",
1313                    instdone->slice_common);
1314
1315         if (INTEL_GEN(dev_priv) <= 6)
1316                 return;
1317
1318         for_each_instdone_slice_subslice(dev_priv, slice, subslice)
1319                 seq_printf(m, "\t\tSAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
1320                            slice, subslice, instdone->sampler[slice][subslice]);
1321
1322         for_each_instdone_slice_subslice(dev_priv, slice, subslice)
1323                 seq_printf(m, "\t\tROW_INSTDONE[%d][%d]: 0x%08x\n",
1324                            slice, subslice, instdone->row[slice][subslice]);
1325 }
1326
1327 static int i915_hangcheck_info(struct seq_file *m, void *unused)
1328 {
1329         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1330         struct intel_engine_cs *engine;
1331         u64 acthd[I915_NUM_ENGINES];
1332         u32 seqno[I915_NUM_ENGINES];
1333         struct intel_instdone instdone;
1334         enum intel_engine_id id;
1335
1336         if (test_bit(I915_WEDGED, &dev_priv->gpu_error.flags))
1337                 seq_printf(m, "Wedged\n");
1338         if (test_bit(I915_RESET_IN_PROGRESS, &dev_priv->gpu_error.flags))
1339                 seq_printf(m, "Reset in progress\n");
1340         if (waitqueue_active(&dev_priv->gpu_error.wait_queue))
1341                 seq_printf(m, "Waiter holding struct mutex\n");
1342         if (waitqueue_active(&dev_priv->gpu_error.reset_queue))
1343                 seq_printf(m, "struct_mutex blocked for reset\n");
1344
1345         if (!i915.enable_hangcheck) {
1346                 seq_printf(m, "Hangcheck disabled\n");
1347                 return 0;
1348         }
1349
1350         intel_runtime_pm_get(dev_priv);
1351
1352         for_each_engine(engine, dev_priv, id) {
1353                 acthd[id] = intel_engine_get_active_head(engine);
1354                 seqno[id] = intel_engine_get_seqno(engine);
1355         }
1356
1357         intel_engine_get_instdone(dev_priv->engine[RCS], &instdone);
1358
1359         intel_runtime_pm_put(dev_priv);
1360
1361         if (delayed_work_pending(&dev_priv->gpu_error.hangcheck_work)) {
1362                 seq_printf(m, "Hangcheck active, fires in %dms\n",
1363                            jiffies_to_msecs(dev_priv->gpu_error.hangcheck_work.timer.expires -
1364                                             jiffies));
1365         } else
1366                 seq_printf(m, "Hangcheck inactive\n");
1367
1368         for_each_engine(engine, dev_priv, id) {
1369                 struct intel_breadcrumbs *b = &engine->breadcrumbs;
1370                 struct rb_node *rb;
1371
1372                 seq_printf(m, "%s:\n", engine->name);
1373                 seq_printf(m, "\tseqno = %x [current %x, last %x]\n",
1374                            engine->hangcheck.seqno,
1375                            seqno[id],
1376                            engine->last_submitted_seqno);
1377                 seq_printf(m, "\twaiters? %s, fake irq active? %s\n",
1378                            yesno(intel_engine_has_waiter(engine)),
1379                            yesno(test_bit(engine->id,
1380                                           &dev_priv->gpu_error.missed_irq_rings)));
1381                 spin_lock(&b->lock);
1382                 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
1383                         struct intel_wait *w = container_of(rb, typeof(*w), node);
1384
1385                         seq_printf(m, "\t%s [%d] waiting for %x\n",
1386                                    w->tsk->comm, w->tsk->pid, w->seqno);
1387                 }
1388                 spin_unlock(&b->lock);
1389
1390                 seq_printf(m, "\tACTHD = 0x%08llx [current 0x%08llx]\n",
1391                            (long long)engine->hangcheck.acthd,
1392                            (long long)acthd[id]);
1393                 seq_printf(m, "\tscore = %d\n", engine->hangcheck.score);
1394                 seq_printf(m, "\taction = %d\n", engine->hangcheck.action);
1395
1396                 if (engine->id == RCS) {
1397                         seq_puts(m, "\tinstdone read =\n");
1398
1399                         i915_instdone_info(dev_priv, m, &instdone);
1400
1401                         seq_puts(m, "\tinstdone accu =\n");
1402
1403                         i915_instdone_info(dev_priv, m,
1404                                            &engine->hangcheck.instdone);
1405                 }
1406         }
1407
1408         return 0;
1409 }
1410
1411 static int ironlake_drpc_info(struct seq_file *m)
1412 {
1413         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1414         u32 rgvmodectl, rstdbyctl;
1415         u16 crstandvid;
1416
1417         intel_runtime_pm_get(dev_priv);
1418
1419         rgvmodectl = I915_READ(MEMMODECTL);
1420         rstdbyctl = I915_READ(RSTDBYCTL);
1421         crstandvid = I915_READ16(CRSTANDVID);
1422
1423         intel_runtime_pm_put(dev_priv);
1424
1425         seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
1426         seq_printf(m, "Boost freq: %d\n",
1427                    (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
1428                    MEMMODE_BOOST_FREQ_SHIFT);
1429         seq_printf(m, "HW control enabled: %s\n",
1430                    yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
1431         seq_printf(m, "SW control enabled: %s\n",
1432                    yesno(rgvmodectl & MEMMODE_SWMODE_EN));
1433         seq_printf(m, "Gated voltage change: %s\n",
1434                    yesno(rgvmodectl & MEMMODE_RCLK_GATE));
1435         seq_printf(m, "Starting frequency: P%d\n",
1436                    (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
1437         seq_printf(m, "Max P-state: P%d\n",
1438                    (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
1439         seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
1440         seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
1441         seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
1442         seq_printf(m, "Render standby enabled: %s\n",
1443                    yesno(!(rstdbyctl & RCX_SW_EXIT)));
1444         seq_puts(m, "Current RS state: ");
1445         switch (rstdbyctl & RSX_STATUS_MASK) {
1446         case RSX_STATUS_ON:
1447                 seq_puts(m, "on\n");
1448                 break;
1449         case RSX_STATUS_RC1:
1450                 seq_puts(m, "RC1\n");
1451                 break;
1452         case RSX_STATUS_RC1E:
1453                 seq_puts(m, "RC1E\n");
1454                 break;
1455         case RSX_STATUS_RS1:
1456                 seq_puts(m, "RS1\n");
1457                 break;
1458         case RSX_STATUS_RS2:
1459                 seq_puts(m, "RS2 (RC6)\n");
1460                 break;
1461         case RSX_STATUS_RS3:
1462                 seq_puts(m, "RC3 (RC6+)\n");
1463                 break;
1464         default:
1465                 seq_puts(m, "unknown\n");
1466                 break;
1467         }
1468
1469         return 0;
1470 }
1471
1472 static int i915_forcewake_domains(struct seq_file *m, void *data)
1473 {
1474         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1475         struct intel_uncore_forcewake_domain *fw_domain;
1476
1477         spin_lock_irq(&dev_priv->uncore.lock);
1478         for_each_fw_domain(fw_domain, dev_priv) {
1479                 seq_printf(m, "%s.wake_count = %u\n",
1480                            intel_uncore_forcewake_domain_to_str(fw_domain->id),
1481                            fw_domain->wake_count);
1482         }
1483         spin_unlock_irq(&dev_priv->uncore.lock);
1484
1485         return 0;
1486 }
1487
1488 static int vlv_drpc_info(struct seq_file *m)
1489 {
1490         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1491         u32 rpmodectl1, rcctl1, pw_status;
1492
1493         intel_runtime_pm_get(dev_priv);
1494
1495         pw_status = I915_READ(VLV_GTLC_PW_STATUS);
1496         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1497         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1498
1499         intel_runtime_pm_put(dev_priv);
1500
1501         seq_printf(m, "Video Turbo Mode: %s\n",
1502                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1503         seq_printf(m, "Turbo enabled: %s\n",
1504                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1505         seq_printf(m, "HW control enabled: %s\n",
1506                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1507         seq_printf(m, "SW control enabled: %s\n",
1508                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1509                           GEN6_RP_MEDIA_SW_MODE));
1510         seq_printf(m, "RC6 Enabled: %s\n",
1511                    yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
1512                                         GEN6_RC_CTL_EI_MODE(1))));
1513         seq_printf(m, "Render Power Well: %s\n",
1514                    (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
1515         seq_printf(m, "Media Power Well: %s\n",
1516                    (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
1517
1518         seq_printf(m, "Render RC6 residency since boot: %u\n",
1519                    I915_READ(VLV_GT_RENDER_RC6));
1520         seq_printf(m, "Media RC6 residency since boot: %u\n",
1521                    I915_READ(VLV_GT_MEDIA_RC6));
1522
1523         return i915_forcewake_domains(m, NULL);
1524 }
1525
1526 static int gen6_drpc_info(struct seq_file *m)
1527 {
1528         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1529         struct drm_device *dev = &dev_priv->drm;
1530         u32 rpmodectl1, gt_core_status, rcctl1, rc6vids = 0;
1531         u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
1532         unsigned forcewake_count;
1533         int count = 0, ret;
1534
1535         ret = mutex_lock_interruptible(&dev->struct_mutex);
1536         if (ret)
1537                 return ret;
1538         intel_runtime_pm_get(dev_priv);
1539
1540         spin_lock_irq(&dev_priv->uncore.lock);
1541         forcewake_count = dev_priv->uncore.fw_domain[FW_DOMAIN_ID_RENDER].wake_count;
1542         spin_unlock_irq(&dev_priv->uncore.lock);
1543
1544         if (forcewake_count) {
1545                 seq_puts(m, "RC information inaccurate because somebody "
1546                             "holds a forcewake reference \n");
1547         } else {
1548                 /* NB: we cannot use forcewake, else we read the wrong values */
1549                 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1550                         udelay(10);
1551                 seq_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1552         }
1553
1554         gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
1555         trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
1556
1557         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1558         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1559         if (INTEL_GEN(dev_priv) >= 9) {
1560                 gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE);
1561                 gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
1562         }
1563         mutex_unlock(&dev->struct_mutex);
1564         mutex_lock(&dev_priv->rps.hw_lock);
1565         sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
1566         mutex_unlock(&dev_priv->rps.hw_lock);
1567
1568         intel_runtime_pm_put(dev_priv);
1569
1570         seq_printf(m, "Video Turbo Mode: %s\n",
1571                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1572         seq_printf(m, "HW control enabled: %s\n",
1573                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1574         seq_printf(m, "SW control enabled: %s\n",
1575                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1576                           GEN6_RP_MEDIA_SW_MODE));
1577         seq_printf(m, "RC1e Enabled: %s\n",
1578                    yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1579         seq_printf(m, "RC6 Enabled: %s\n",
1580                    yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1581         if (INTEL_GEN(dev_priv) >= 9) {
1582                 seq_printf(m, "Render Well Gating Enabled: %s\n",
1583                         yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
1584                 seq_printf(m, "Media Well Gating Enabled: %s\n",
1585                         yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE));
1586         }
1587         seq_printf(m, "Deep RC6 Enabled: %s\n",
1588                    yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1589         seq_printf(m, "Deepest RC6 Enabled: %s\n",
1590                    yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1591         seq_puts(m, "Current RC state: ");
1592         switch (gt_core_status & GEN6_RCn_MASK) {
1593         case GEN6_RC0:
1594                 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1595                         seq_puts(m, "Core Power Down\n");
1596                 else
1597                         seq_puts(m, "on\n");
1598                 break;
1599         case GEN6_RC3:
1600                 seq_puts(m, "RC3\n");
1601                 break;
1602         case GEN6_RC6:
1603                 seq_puts(m, "RC6\n");
1604                 break;
1605         case GEN6_RC7:
1606                 seq_puts(m, "RC7\n");
1607                 break;
1608         default:
1609                 seq_puts(m, "Unknown\n");
1610                 break;
1611         }
1612
1613         seq_printf(m, "Core Power Down: %s\n",
1614                    yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1615         if (INTEL_GEN(dev_priv) >= 9) {
1616                 seq_printf(m, "Render Power Well: %s\n",
1617                         (gen9_powergate_status &
1618                          GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
1619                 seq_printf(m, "Media Power Well: %s\n",
1620                         (gen9_powergate_status &
1621                          GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
1622         }
1623
1624         /* Not exactly sure what this is */
1625         seq_printf(m, "RC6 \"Locked to RPn\" residency since boot: %u\n",
1626                    I915_READ(GEN6_GT_GFX_RC6_LOCKED));
1627         seq_printf(m, "RC6 residency since boot: %u\n",
1628                    I915_READ(GEN6_GT_GFX_RC6));
1629         seq_printf(m, "RC6+ residency since boot: %u\n",
1630                    I915_READ(GEN6_GT_GFX_RC6p));
1631         seq_printf(m, "RC6++ residency since boot: %u\n",
1632                    I915_READ(GEN6_GT_GFX_RC6pp));
1633
1634         seq_printf(m, "RC6   voltage: %dmV\n",
1635                    GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
1636         seq_printf(m, "RC6+  voltage: %dmV\n",
1637                    GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
1638         seq_printf(m, "RC6++ voltage: %dmV\n",
1639                    GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
1640         return i915_forcewake_domains(m, NULL);
1641 }
1642
1643 static int i915_drpc_info(struct seq_file *m, void *unused)
1644 {
1645         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1646
1647         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1648                 return vlv_drpc_info(m);
1649         else if (INTEL_GEN(dev_priv) >= 6)
1650                 return gen6_drpc_info(m);
1651         else
1652                 return ironlake_drpc_info(m);
1653 }
1654
1655 static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
1656 {
1657         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1658
1659         seq_printf(m, "FB tracking busy bits: 0x%08x\n",
1660                    dev_priv->fb_tracking.busy_bits);
1661
1662         seq_printf(m, "FB tracking flip bits: 0x%08x\n",
1663                    dev_priv->fb_tracking.flip_bits);
1664
1665         return 0;
1666 }
1667
1668 static int i915_fbc_status(struct seq_file *m, void *unused)
1669 {
1670         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1671
1672         if (!HAS_FBC(dev_priv)) {
1673                 seq_puts(m, "FBC unsupported on this chipset\n");
1674                 return 0;
1675         }
1676
1677         intel_runtime_pm_get(dev_priv);
1678         mutex_lock(&dev_priv->fbc.lock);
1679
1680         if (intel_fbc_is_active(dev_priv))
1681                 seq_puts(m, "FBC enabled\n");
1682         else
1683                 seq_printf(m, "FBC disabled: %s\n",
1684                            dev_priv->fbc.no_fbc_reason);
1685
1686         if (intel_fbc_is_active(dev_priv) && INTEL_GEN(dev_priv) >= 7) {
1687                 uint32_t mask = INTEL_GEN(dev_priv) >= 8 ?
1688                                 BDW_FBC_COMPRESSION_MASK :
1689                                 IVB_FBC_COMPRESSION_MASK;
1690                 seq_printf(m, "Compressing: %s\n",
1691                            yesno(I915_READ(FBC_STATUS2) & mask));
1692         }
1693
1694         mutex_unlock(&dev_priv->fbc.lock);
1695         intel_runtime_pm_put(dev_priv);
1696
1697         return 0;
1698 }
1699
1700 static int i915_fbc_fc_get(void *data, u64 *val)
1701 {
1702         struct drm_i915_private *dev_priv = data;
1703
1704         if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1705                 return -ENODEV;
1706
1707         *val = dev_priv->fbc.false_color;
1708
1709         return 0;
1710 }
1711
1712 static int i915_fbc_fc_set(void *data, u64 val)
1713 {
1714         struct drm_i915_private *dev_priv = data;
1715         u32 reg;
1716
1717         if (INTEL_GEN(dev_priv) < 7 || !HAS_FBC(dev_priv))
1718                 return -ENODEV;
1719
1720         mutex_lock(&dev_priv->fbc.lock);
1721
1722         reg = I915_READ(ILK_DPFC_CONTROL);
1723         dev_priv->fbc.false_color = val;
1724
1725         I915_WRITE(ILK_DPFC_CONTROL, val ?
1726                    (reg | FBC_CTL_FALSE_COLOR) :
1727                    (reg & ~FBC_CTL_FALSE_COLOR));
1728
1729         mutex_unlock(&dev_priv->fbc.lock);
1730         return 0;
1731 }
1732
1733 DEFINE_SIMPLE_ATTRIBUTE(i915_fbc_fc_fops,
1734                         i915_fbc_fc_get, i915_fbc_fc_set,
1735                         "%llu\n");
1736
1737 static int i915_ips_status(struct seq_file *m, void *unused)
1738 {
1739         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1740
1741         if (!HAS_IPS(dev_priv)) {
1742                 seq_puts(m, "not supported\n");
1743                 return 0;
1744         }
1745
1746         intel_runtime_pm_get(dev_priv);
1747
1748         seq_printf(m, "Enabled by kernel parameter: %s\n",
1749                    yesno(i915.enable_ips));
1750
1751         if (INTEL_GEN(dev_priv) >= 8) {
1752                 seq_puts(m, "Currently: unknown\n");
1753         } else {
1754                 if (I915_READ(IPS_CTL) & IPS_ENABLE)
1755                         seq_puts(m, "Currently: enabled\n");
1756                 else
1757                         seq_puts(m, "Currently: disabled\n");
1758         }
1759
1760         intel_runtime_pm_put(dev_priv);
1761
1762         return 0;
1763 }
1764
1765 static int i915_sr_status(struct seq_file *m, void *unused)
1766 {
1767         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1768         bool sr_enabled = false;
1769
1770         intel_runtime_pm_get(dev_priv);
1771         intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
1772
1773         if (HAS_PCH_SPLIT(dev_priv))
1774                 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1775         else if (IS_CRESTLINE(dev_priv) || IS_G4X(dev_priv) ||
1776                  IS_I945G(dev_priv) || IS_I945GM(dev_priv))
1777                 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1778         else if (IS_I915GM(dev_priv))
1779                 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1780         else if (IS_PINEVIEW(dev_priv))
1781                 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1782         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1783                 sr_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
1784
1785         intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
1786         intel_runtime_pm_put(dev_priv);
1787
1788         seq_printf(m, "self-refresh: %s\n",
1789                    sr_enabled ? "enabled" : "disabled");
1790
1791         return 0;
1792 }
1793
1794 static int i915_emon_status(struct seq_file *m, void *unused)
1795 {
1796         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1797         struct drm_device *dev = &dev_priv->drm;
1798         unsigned long temp, chipset, gfx;
1799         int ret;
1800
1801         if (!IS_GEN5(dev_priv))
1802                 return -ENODEV;
1803
1804         ret = mutex_lock_interruptible(&dev->struct_mutex);
1805         if (ret)
1806                 return ret;
1807
1808         temp = i915_mch_val(dev_priv);
1809         chipset = i915_chipset_val(dev_priv);
1810         gfx = i915_gfx_val(dev_priv);
1811         mutex_unlock(&dev->struct_mutex);
1812
1813         seq_printf(m, "GMCH temp: %ld\n", temp);
1814         seq_printf(m, "Chipset power: %ld\n", chipset);
1815         seq_printf(m, "GFX power: %ld\n", gfx);
1816         seq_printf(m, "Total power: %ld\n", chipset + gfx);
1817
1818         return 0;
1819 }
1820
1821 static int i915_ring_freq_table(struct seq_file *m, void *unused)
1822 {
1823         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1824         int ret = 0;
1825         int gpu_freq, ia_freq;
1826         unsigned int max_gpu_freq, min_gpu_freq;
1827
1828         if (!HAS_LLC(dev_priv)) {
1829                 seq_puts(m, "unsupported on this chipset\n");
1830                 return 0;
1831         }
1832
1833         intel_runtime_pm_get(dev_priv);
1834
1835         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
1836         if (ret)
1837                 goto out;
1838
1839         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
1840                 /* Convert GT frequency to 50 HZ units */
1841                 min_gpu_freq =
1842                         dev_priv->rps.min_freq_softlimit / GEN9_FREQ_SCALER;
1843                 max_gpu_freq =
1844                         dev_priv->rps.max_freq_softlimit / GEN9_FREQ_SCALER;
1845         } else {
1846                 min_gpu_freq = dev_priv->rps.min_freq_softlimit;
1847                 max_gpu_freq = dev_priv->rps.max_freq_softlimit;
1848         }
1849
1850         seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
1851
1852         for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
1853                 ia_freq = gpu_freq;
1854                 sandybridge_pcode_read(dev_priv,
1855                                        GEN6_PCODE_READ_MIN_FREQ_TABLE,
1856                                        &ia_freq);
1857                 seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
1858                            intel_gpu_freq(dev_priv, (gpu_freq *
1859                                 (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv) ?
1860                                  GEN9_FREQ_SCALER : 1))),
1861                            ((ia_freq >> 0) & 0xff) * 100,
1862                            ((ia_freq >> 8) & 0xff) * 100);
1863         }
1864
1865         mutex_unlock(&dev_priv->rps.hw_lock);
1866
1867 out:
1868         intel_runtime_pm_put(dev_priv);
1869         return ret;
1870 }
1871
1872 static int i915_opregion(struct seq_file *m, void *unused)
1873 {
1874         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1875         struct drm_device *dev = &dev_priv->drm;
1876         struct intel_opregion *opregion = &dev_priv->opregion;
1877         int ret;
1878
1879         ret = mutex_lock_interruptible(&dev->struct_mutex);
1880         if (ret)
1881                 goto out;
1882
1883         if (opregion->header)
1884                 seq_write(m, opregion->header, OPREGION_SIZE);
1885
1886         mutex_unlock(&dev->struct_mutex);
1887
1888 out:
1889         return 0;
1890 }
1891
1892 static int i915_vbt(struct seq_file *m, void *unused)
1893 {
1894         struct intel_opregion *opregion = &node_to_i915(m->private)->opregion;
1895
1896         if (opregion->vbt)
1897                 seq_write(m, opregion->vbt, opregion->vbt_size);
1898
1899         return 0;
1900 }
1901
1902 static int i915_gem_framebuffer_info(struct seq_file *m, void *data)
1903 {
1904         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1905         struct drm_device *dev = &dev_priv->drm;
1906         struct intel_framebuffer *fbdev_fb = NULL;
1907         struct drm_framebuffer *drm_fb;
1908         int ret;
1909
1910         ret = mutex_lock_interruptible(&dev->struct_mutex);
1911         if (ret)
1912                 return ret;
1913
1914 #ifdef CONFIG_DRM_FBDEV_EMULATION
1915         if (dev_priv->fbdev) {
1916                 fbdev_fb = to_intel_framebuffer(dev_priv->fbdev->helper.fb);
1917
1918                 seq_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1919                            fbdev_fb->base.width,
1920                            fbdev_fb->base.height,
1921                            fbdev_fb->base.depth,
1922                            fbdev_fb->base.bits_per_pixel,
1923                            fbdev_fb->base.modifier[0],
1924                            drm_framebuffer_read_refcount(&fbdev_fb->base));
1925                 describe_obj(m, fbdev_fb->obj);
1926                 seq_putc(m, '\n');
1927         }
1928 #endif
1929
1930         mutex_lock(&dev->mode_config.fb_lock);
1931         drm_for_each_fb(drm_fb, dev) {
1932                 struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
1933                 if (fb == fbdev_fb)
1934                         continue;
1935
1936                 seq_printf(m, "user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj ",
1937                            fb->base.width,
1938                            fb->base.height,
1939                            fb->base.depth,
1940                            fb->base.bits_per_pixel,
1941                            fb->base.modifier[0],
1942                            drm_framebuffer_read_refcount(&fb->base));
1943                 describe_obj(m, fb->obj);
1944                 seq_putc(m, '\n');
1945         }
1946         mutex_unlock(&dev->mode_config.fb_lock);
1947         mutex_unlock(&dev->struct_mutex);
1948
1949         return 0;
1950 }
1951
1952 static void describe_ctx_ring(struct seq_file *m, struct intel_ring *ring)
1953 {
1954         seq_printf(m, " (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)",
1955                    ring->space, ring->head, ring->tail,
1956                    ring->last_retired_head);
1957 }
1958
1959 static int i915_context_status(struct seq_file *m, void *unused)
1960 {
1961         struct drm_i915_private *dev_priv = node_to_i915(m->private);
1962         struct drm_device *dev = &dev_priv->drm;
1963         struct intel_engine_cs *engine;
1964         struct i915_gem_context *ctx;
1965         enum intel_engine_id id;
1966         int ret;
1967
1968         ret = mutex_lock_interruptible(&dev->struct_mutex);
1969         if (ret)
1970                 return ret;
1971
1972         list_for_each_entry(ctx, &dev_priv->context_list, link) {
1973                 seq_printf(m, "HW context %u ", ctx->hw_id);
1974                 if (ctx->pid) {
1975                         struct task_struct *task;
1976
1977                         task = get_pid_task(ctx->pid, PIDTYPE_PID);
1978                         if (task) {
1979                                 seq_printf(m, "(%s [%d]) ",
1980                                            task->comm, task->pid);
1981                                 put_task_struct(task);
1982                         }
1983                 } else if (IS_ERR(ctx->file_priv)) {
1984                         seq_puts(m, "(deleted) ");
1985                 } else {
1986                         seq_puts(m, "(kernel) ");
1987                 }
1988
1989                 seq_putc(m, ctx->remap_slice ? 'R' : 'r');
1990                 seq_putc(m, '\n');
1991
1992                 for_each_engine(engine, dev_priv, id) {
1993                         struct intel_context *ce = &ctx->engine[engine->id];
1994
1995                         seq_printf(m, "%s: ", engine->name);
1996                         seq_putc(m, ce->initialised ? 'I' : 'i');
1997                         if (ce->state)
1998                                 describe_obj(m, ce->state->obj);
1999                         if (ce->ring)
2000                                 describe_ctx_ring(m, ce->ring);
2001                         seq_putc(m, '\n');
2002                 }
2003
2004                 seq_putc(m, '\n');
2005         }
2006
2007         mutex_unlock(&dev->struct_mutex);
2008
2009         return 0;
2010 }
2011
2012 static void i915_dump_lrc_obj(struct seq_file *m,
2013                               struct i915_gem_context *ctx,
2014                               struct intel_engine_cs *engine)
2015 {
2016         struct i915_vma *vma = ctx->engine[engine->id].state;
2017         struct page *page;
2018         int j;
2019
2020         seq_printf(m, "CONTEXT: %s %u\n", engine->name, ctx->hw_id);
2021
2022         if (!vma) {
2023                 seq_puts(m, "\tFake context\n");
2024                 return;
2025         }
2026
2027         if (vma->flags & I915_VMA_GLOBAL_BIND)
2028                 seq_printf(m, "\tBound in GGTT at 0x%08x\n",
2029                            i915_ggtt_offset(vma));
2030
2031         if (i915_gem_object_get_pages(vma->obj)) {
2032                 seq_puts(m, "\tFailed to get pages for context object\n\n");
2033                 return;
2034         }
2035
2036         page = i915_gem_object_get_page(vma->obj, LRC_STATE_PN);
2037         if (page) {
2038                 u32 *reg_state = kmap_atomic(page);
2039
2040                 for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
2041                         seq_printf(m,
2042                                    "\t[0x%04x] 0x%08x 0x%08x 0x%08x 0x%08x\n",
2043                                    j * 4,
2044                                    reg_state[j], reg_state[j + 1],
2045                                    reg_state[j + 2], reg_state[j + 3]);
2046                 }
2047                 kunmap_atomic(reg_state);
2048         }
2049
2050         seq_putc(m, '\n');
2051 }
2052
2053 static int i915_dump_lrc(struct seq_file *m, void *unused)
2054 {
2055         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2056         struct drm_device *dev = &dev_priv->drm;
2057         struct intel_engine_cs *engine;
2058         struct i915_gem_context *ctx;
2059         enum intel_engine_id id;
2060         int ret;
2061
2062         if (!i915.enable_execlists) {
2063                 seq_printf(m, "Logical Ring Contexts are disabled\n");
2064                 return 0;
2065         }
2066
2067         ret = mutex_lock_interruptible(&dev->struct_mutex);
2068         if (ret)
2069                 return ret;
2070
2071         list_for_each_entry(ctx, &dev_priv->context_list, link)
2072                 for_each_engine(engine, dev_priv, id)
2073                         i915_dump_lrc_obj(m, ctx, engine);
2074
2075         mutex_unlock(&dev->struct_mutex);
2076
2077         return 0;
2078 }
2079
2080 static const char *swizzle_string(unsigned swizzle)
2081 {
2082         switch (swizzle) {
2083         case I915_BIT_6_SWIZZLE_NONE:
2084                 return "none";
2085         case I915_BIT_6_SWIZZLE_9:
2086                 return "bit9";
2087         case I915_BIT_6_SWIZZLE_9_10:
2088                 return "bit9/bit10";
2089         case I915_BIT_6_SWIZZLE_9_11:
2090                 return "bit9/bit11";
2091         case I915_BIT_6_SWIZZLE_9_10_11:
2092                 return "bit9/bit10/bit11";
2093         case I915_BIT_6_SWIZZLE_9_17:
2094                 return "bit9/bit17";
2095         case I915_BIT_6_SWIZZLE_9_10_17:
2096                 return "bit9/bit10/bit17";
2097         case I915_BIT_6_SWIZZLE_UNKNOWN:
2098                 return "unknown";
2099         }
2100
2101         return "bug";
2102 }
2103
2104 static int i915_swizzle_info(struct seq_file *m, void *data)
2105 {
2106         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2107
2108         intel_runtime_pm_get(dev_priv);
2109
2110         seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
2111                    swizzle_string(dev_priv->mm.bit_6_swizzle_x));
2112         seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
2113                    swizzle_string(dev_priv->mm.bit_6_swizzle_y));
2114
2115         if (IS_GEN3(dev_priv) || IS_GEN4(dev_priv)) {
2116                 seq_printf(m, "DDC = 0x%08x\n",
2117                            I915_READ(DCC));
2118                 seq_printf(m, "DDC2 = 0x%08x\n",
2119                            I915_READ(DCC2));
2120                 seq_printf(m, "C0DRB3 = 0x%04x\n",
2121                            I915_READ16(C0DRB3));
2122                 seq_printf(m, "C1DRB3 = 0x%04x\n",
2123                            I915_READ16(C1DRB3));
2124         } else if (INTEL_GEN(dev_priv) >= 6) {
2125                 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
2126                            I915_READ(MAD_DIMM_C0));
2127                 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
2128                            I915_READ(MAD_DIMM_C1));
2129                 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
2130                            I915_READ(MAD_DIMM_C2));
2131                 seq_printf(m, "TILECTL = 0x%08x\n",
2132                            I915_READ(TILECTL));
2133                 if (INTEL_GEN(dev_priv) >= 8)
2134                         seq_printf(m, "GAMTARBMODE = 0x%08x\n",
2135                                    I915_READ(GAMTARBMODE));
2136                 else
2137                         seq_printf(m, "ARB_MODE = 0x%08x\n",
2138                                    I915_READ(ARB_MODE));
2139                 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
2140                            I915_READ(DISP_ARB_CTL));
2141         }
2142
2143         if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
2144                 seq_puts(m, "L-shaped memory detected\n");
2145
2146         intel_runtime_pm_put(dev_priv);
2147
2148         return 0;
2149 }
2150
2151 static int per_file_ctx(int id, void *ptr, void *data)
2152 {
2153         struct i915_gem_context *ctx = ptr;
2154         struct seq_file *m = data;
2155         struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
2156
2157         if (!ppgtt) {
2158                 seq_printf(m, "  no ppgtt for context %d\n",
2159                            ctx->user_handle);
2160                 return 0;
2161         }
2162
2163         if (i915_gem_context_is_default(ctx))
2164                 seq_puts(m, "  default context:\n");
2165         else
2166                 seq_printf(m, "  context %d:\n", ctx->user_handle);
2167         ppgtt->debug_dump(ppgtt, m);
2168
2169         return 0;
2170 }
2171
2172 static void gen8_ppgtt_info(struct seq_file *m,
2173                             struct drm_i915_private *dev_priv)
2174 {
2175         struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2176         struct intel_engine_cs *engine;
2177         enum intel_engine_id id;
2178         int i;
2179
2180         if (!ppgtt)
2181                 return;
2182
2183         for_each_engine(engine, dev_priv, id) {
2184                 seq_printf(m, "%s\n", engine->name);
2185                 for (i = 0; i < 4; i++) {
2186                         u64 pdp = I915_READ(GEN8_RING_PDP_UDW(engine, i));
2187                         pdp <<= 32;
2188                         pdp |= I915_READ(GEN8_RING_PDP_LDW(engine, i));
2189                         seq_printf(m, "\tPDP%d 0x%016llx\n", i, pdp);
2190                 }
2191         }
2192 }
2193
2194 static void gen6_ppgtt_info(struct seq_file *m,
2195                             struct drm_i915_private *dev_priv)
2196 {
2197         struct intel_engine_cs *engine;
2198         enum intel_engine_id id;
2199
2200         if (IS_GEN6(dev_priv))
2201                 seq_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
2202
2203         for_each_engine(engine, dev_priv, id) {
2204                 seq_printf(m, "%s\n", engine->name);
2205                 if (IS_GEN7(dev_priv))
2206                         seq_printf(m, "GFX_MODE: 0x%08x\n",
2207                                    I915_READ(RING_MODE_GEN7(engine)));
2208                 seq_printf(m, "PP_DIR_BASE: 0x%08x\n",
2209                            I915_READ(RING_PP_DIR_BASE(engine)));
2210                 seq_printf(m, "PP_DIR_BASE_READ: 0x%08x\n",
2211                            I915_READ(RING_PP_DIR_BASE_READ(engine)));
2212                 seq_printf(m, "PP_DIR_DCLV: 0x%08x\n",
2213                            I915_READ(RING_PP_DIR_DCLV(engine)));
2214         }
2215         if (dev_priv->mm.aliasing_ppgtt) {
2216                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
2217
2218                 seq_puts(m, "aliasing PPGTT:\n");
2219                 seq_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd.base.ggtt_offset);
2220
2221                 ppgtt->debug_dump(ppgtt, m);
2222         }
2223
2224         seq_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
2225 }
2226
2227 static int i915_ppgtt_info(struct seq_file *m, void *data)
2228 {
2229         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2230         struct drm_device *dev = &dev_priv->drm;
2231         struct drm_file *file;
2232         int ret;
2233
2234         mutex_lock(&dev->filelist_mutex);
2235         ret = mutex_lock_interruptible(&dev->struct_mutex);
2236         if (ret)
2237                 goto out_unlock;
2238
2239         intel_runtime_pm_get(dev_priv);
2240
2241         if (INTEL_GEN(dev_priv) >= 8)
2242                 gen8_ppgtt_info(m, dev_priv);
2243         else if (INTEL_GEN(dev_priv) >= 6)
2244                 gen6_ppgtt_info(m, dev_priv);
2245
2246         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2247                 struct drm_i915_file_private *file_priv = file->driver_priv;
2248                 struct task_struct *task;
2249
2250                 task = get_pid_task(file->pid, PIDTYPE_PID);
2251                 if (!task) {
2252                         ret = -ESRCH;
2253                         goto out_rpm;
2254                 }
2255                 seq_printf(m, "\nproc: %s\n", task->comm);
2256                 put_task_struct(task);
2257                 idr_for_each(&file_priv->context_idr, per_file_ctx,
2258                              (void *)(unsigned long)m);
2259         }
2260
2261 out_rpm:
2262         intel_runtime_pm_put(dev_priv);
2263         mutex_unlock(&dev->struct_mutex);
2264 out_unlock:
2265         mutex_unlock(&dev->filelist_mutex);
2266         return ret;
2267 }
2268
2269 static int count_irq_waiters(struct drm_i915_private *i915)
2270 {
2271         struct intel_engine_cs *engine;
2272         enum intel_engine_id id;
2273         int count = 0;
2274
2275         for_each_engine(engine, i915, id)
2276                 count += intel_engine_has_waiter(engine);
2277
2278         return count;
2279 }
2280
2281 static const char *rps_power_to_str(unsigned int power)
2282 {
2283         static const char * const strings[] = {
2284                 [LOW_POWER] = "low power",
2285                 [BETWEEN] = "mixed",
2286                 [HIGH_POWER] = "high power",
2287         };
2288
2289         if (power >= ARRAY_SIZE(strings) || !strings[power])
2290                 return "unknown";
2291
2292         return strings[power];
2293 }
2294
2295 static int i915_rps_boost_info(struct seq_file *m, void *data)
2296 {
2297         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2298         struct drm_device *dev = &dev_priv->drm;
2299         struct drm_file *file;
2300
2301         seq_printf(m, "RPS enabled? %d\n", dev_priv->rps.enabled);
2302         seq_printf(m, "GPU busy? %s [%x]\n",
2303                    yesno(dev_priv->gt.awake), dev_priv->gt.active_engines);
2304         seq_printf(m, "CPU waiting? %d\n", count_irq_waiters(dev_priv));
2305         seq_printf(m, "Frequency requested %d\n",
2306                    intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq));
2307         seq_printf(m, "  min hard:%d, soft:%d; max soft:%d, hard:%d\n",
2308                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2309                    intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit),
2310                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit),
2311                    intel_gpu_freq(dev_priv, dev_priv->rps.max_freq));
2312         seq_printf(m, "  idle:%d, efficient:%d, boost:%d\n",
2313                    intel_gpu_freq(dev_priv, dev_priv->rps.idle_freq),
2314                    intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2315                    intel_gpu_freq(dev_priv, dev_priv->rps.boost_freq));
2316
2317         mutex_lock(&dev->filelist_mutex);
2318         spin_lock(&dev_priv->rps.client_lock);
2319         list_for_each_entry_reverse(file, &dev->filelist, lhead) {
2320                 struct drm_i915_file_private *file_priv = file->driver_priv;
2321                 struct task_struct *task;
2322
2323                 rcu_read_lock();
2324                 task = pid_task(file->pid, PIDTYPE_PID);
2325                 seq_printf(m, "%s [%d]: %d boosts%s\n",
2326                            task ? task->comm : "<unknown>",
2327                            task ? task->pid : -1,
2328                            file_priv->rps.boosts,
2329                            list_empty(&file_priv->rps.link) ? "" : ", active");
2330                 rcu_read_unlock();
2331         }
2332         seq_printf(m, "Kernel (anonymous) boosts: %d\n", dev_priv->rps.boosts);
2333         spin_unlock(&dev_priv->rps.client_lock);
2334         mutex_unlock(&dev->filelist_mutex);
2335
2336         if (INTEL_GEN(dev_priv) >= 6 &&
2337             dev_priv->rps.enabled &&
2338             dev_priv->gt.active_engines) {
2339                 u32 rpup, rpupei;
2340                 u32 rpdown, rpdownei;
2341
2342                 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2343                 rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK;
2344                 rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK;
2345                 rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK;
2346                 rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK;
2347                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2348
2349                 seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n",
2350                            rps_power_to_str(dev_priv->rps.power));
2351                 seq_printf(m, "  Avg. up: %d%% [above threshold? %d%%]\n",
2352                            100 * rpup / rpupei,
2353                            dev_priv->rps.up_threshold);
2354                 seq_printf(m, "  Avg. down: %d%% [below threshold? %d%%]\n",
2355                            100 * rpdown / rpdownei,
2356                            dev_priv->rps.down_threshold);
2357         } else {
2358                 seq_puts(m, "\nRPS Autotuning inactive\n");
2359         }
2360
2361         return 0;
2362 }
2363
2364 static int i915_llc(struct seq_file *m, void *data)
2365 {
2366         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2367         const bool edram = INTEL_GEN(dev_priv) > 8;
2368
2369         seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv)));
2370         seq_printf(m, "%s: %lluMB\n", edram ? "eDRAM" : "eLLC",
2371                    intel_uncore_edram_size(dev_priv)/1024/1024);
2372
2373         return 0;
2374 }
2375
2376 static int i915_guc_load_status_info(struct seq_file *m, void *data)
2377 {
2378         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2379         struct intel_guc_fw *guc_fw = &dev_priv->guc.guc_fw;
2380         u32 tmp, i;
2381
2382         if (!HAS_GUC_UCODE(dev_priv))
2383                 return 0;
2384
2385         seq_printf(m, "GuC firmware status:\n");
2386         seq_printf(m, "\tpath: %s\n",
2387                 guc_fw->guc_fw_path);
2388         seq_printf(m, "\tfetch: %s\n",
2389                 intel_guc_fw_status_repr(guc_fw->guc_fw_fetch_status));
2390         seq_printf(m, "\tload: %s\n",
2391                 intel_guc_fw_status_repr(guc_fw->guc_fw_load_status));
2392         seq_printf(m, "\tversion wanted: %d.%d\n",
2393                 guc_fw->guc_fw_major_wanted, guc_fw->guc_fw_minor_wanted);
2394         seq_printf(m, "\tversion found: %d.%d\n",
2395                 guc_fw->guc_fw_major_found, guc_fw->guc_fw_minor_found);
2396         seq_printf(m, "\theader: offset is %d; size = %d\n",
2397                 guc_fw->header_offset, guc_fw->header_size);
2398         seq_printf(m, "\tuCode: offset is %d; size = %d\n",
2399                 guc_fw->ucode_offset, guc_fw->ucode_size);
2400         seq_printf(m, "\tRSA: offset is %d; size = %d\n",
2401                 guc_fw->rsa_offset, guc_fw->rsa_size);
2402
2403         tmp = I915_READ(GUC_STATUS);
2404
2405         seq_printf(m, "\nGuC status 0x%08x:\n", tmp);
2406         seq_printf(m, "\tBootrom status = 0x%x\n",
2407                 (tmp & GS_BOOTROM_MASK) >> GS_BOOTROM_SHIFT);
2408         seq_printf(m, "\tuKernel status = 0x%x\n",
2409                 (tmp & GS_UKERNEL_MASK) >> GS_UKERNEL_SHIFT);
2410         seq_printf(m, "\tMIA Core status = 0x%x\n",
2411                 (tmp & GS_MIA_MASK) >> GS_MIA_SHIFT);
2412         seq_puts(m, "\nScratch registers:\n");
2413         for (i = 0; i < 16; i++)
2414                 seq_printf(m, "\t%2d: \t0x%x\n", i, I915_READ(SOFT_SCRATCH(i)));
2415
2416         return 0;
2417 }
2418
2419 static void i915_guc_log_info(struct seq_file *m,
2420                               struct drm_i915_private *dev_priv)
2421 {
2422         struct intel_guc *guc = &dev_priv->guc;
2423
2424         seq_puts(m, "\nGuC logging stats:\n");
2425
2426         seq_printf(m, "\tISR:   flush count %10u, overflow count %10u\n",
2427                    guc->log.flush_count[GUC_ISR_LOG_BUFFER],
2428                    guc->log.total_overflow_count[GUC_ISR_LOG_BUFFER]);
2429
2430         seq_printf(m, "\tDPC:   flush count %10u, overflow count %10u\n",
2431                    guc->log.flush_count[GUC_DPC_LOG_BUFFER],
2432                    guc->log.total_overflow_count[GUC_DPC_LOG_BUFFER]);
2433
2434         seq_printf(m, "\tCRASH: flush count %10u, overflow count %10u\n",
2435                    guc->log.flush_count[GUC_CRASH_DUMP_LOG_BUFFER],
2436                    guc->log.total_overflow_count[GUC_CRASH_DUMP_LOG_BUFFER]);
2437
2438         seq_printf(m, "\tTotal flush interrupt count: %u\n",
2439                    guc->log.flush_interrupt_count);
2440
2441         seq_printf(m, "\tCapture miss count: %u\n",
2442                    guc->log.capture_miss_count);
2443 }
2444
2445 static void i915_guc_client_info(struct seq_file *m,
2446                                  struct drm_i915_private *dev_priv,
2447                                  struct i915_guc_client *client)
2448 {
2449         struct intel_engine_cs *engine;
2450         enum intel_engine_id id;
2451         uint64_t tot = 0;
2452
2453         seq_printf(m, "\tPriority %d, GuC ctx index: %u, PD offset 0x%x\n",
2454                 client->priority, client->ctx_index, client->proc_desc_offset);
2455         seq_printf(m, "\tDoorbell id %d, offset: 0x%x, cookie 0x%x\n",
2456                 client->doorbell_id, client->doorbell_offset, client->cookie);
2457         seq_printf(m, "\tWQ size %d, offset: 0x%x, tail %d\n",
2458                 client->wq_size, client->wq_offset, client->wq_tail);
2459
2460         seq_printf(m, "\tWork queue full: %u\n", client->no_wq_space);
2461         seq_printf(m, "\tFailed doorbell: %u\n", client->b_fail);
2462         seq_printf(m, "\tLast submission result: %d\n", client->retcode);
2463
2464         for_each_engine(engine, dev_priv, id) {
2465                 u64 submissions = client->submissions[id];
2466                 tot += submissions;
2467                 seq_printf(m, "\tSubmissions: %llu %s\n",
2468                                 submissions, engine->name);
2469         }
2470         seq_printf(m, "\tTotal: %llu\n", tot);
2471 }
2472
2473 static int i915_guc_info(struct seq_file *m, void *data)
2474 {
2475         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2476         struct drm_device *dev = &dev_priv->drm;
2477         struct intel_guc guc;
2478         struct i915_guc_client client = {};
2479         struct intel_engine_cs *engine;
2480         enum intel_engine_id id;
2481         u64 total = 0;
2482
2483         if (!HAS_GUC_SCHED(dev_priv))
2484                 return 0;
2485
2486         if (mutex_lock_interruptible(&dev->struct_mutex))
2487                 return 0;
2488
2489         /* Take a local copy of the GuC data, so we can dump it at leisure */
2490         guc = dev_priv->guc;
2491         if (guc.execbuf_client)
2492                 client = *guc.execbuf_client;
2493
2494         mutex_unlock(&dev->struct_mutex);
2495
2496         seq_printf(m, "Doorbell map:\n");
2497         seq_printf(m, "\t%*pb\n", GUC_MAX_DOORBELLS, guc.doorbell_bitmap);
2498         seq_printf(m, "Doorbell next cacheline: 0x%x\n\n", guc.db_cacheline);
2499
2500         seq_printf(m, "GuC total action count: %llu\n", guc.action_count);
2501         seq_printf(m, "GuC action failure count: %u\n", guc.action_fail);
2502         seq_printf(m, "GuC last action command: 0x%x\n", guc.action_cmd);
2503         seq_printf(m, "GuC last action status: 0x%x\n", guc.action_status);
2504         seq_printf(m, "GuC last action error code: %d\n", guc.action_err);
2505
2506         seq_printf(m, "\nGuC submissions:\n");
2507         for_each_engine(engine, dev_priv, id) {
2508                 u64 submissions = guc.submissions[id];
2509                 total += submissions;
2510                 seq_printf(m, "\t%-24s: %10llu, last seqno 0x%08x\n",
2511                         engine->name, submissions, guc.last_seqno[id]);
2512         }
2513         seq_printf(m, "\t%s: %llu\n", "Total", total);
2514
2515         seq_printf(m, "\nGuC execbuf client @ %p:\n", guc.execbuf_client);
2516         i915_guc_client_info(m, dev_priv, &client);
2517
2518         i915_guc_log_info(m, dev_priv);
2519
2520         /* Add more as required ... */
2521
2522         return 0;
2523 }
2524
2525 static int i915_guc_log_dump(struct seq_file *m, void *data)
2526 {
2527         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2528         struct drm_i915_gem_object *obj;
2529         int i = 0, pg;
2530
2531         if (!dev_priv->guc.log.vma)
2532                 return 0;
2533
2534         obj = dev_priv->guc.log.vma->obj;
2535         for (pg = 0; pg < obj->base.size / PAGE_SIZE; pg++) {
2536                 u32 *log = kmap_atomic(i915_gem_object_get_page(obj, pg));
2537
2538                 for (i = 0; i < PAGE_SIZE / sizeof(u32); i += 4)
2539                         seq_printf(m, "0x%08x 0x%08x 0x%08x 0x%08x\n",
2540                                    *(log + i), *(log + i + 1),
2541                                    *(log + i + 2), *(log + i + 3));
2542
2543                 kunmap_atomic(log);
2544         }
2545
2546         seq_putc(m, '\n');
2547
2548         return 0;
2549 }
2550
2551 static int i915_guc_log_control_get(void *data, u64 *val)
2552 {
2553         struct drm_device *dev = data;
2554         struct drm_i915_private *dev_priv = to_i915(dev);
2555
2556         if (!dev_priv->guc.log.vma)
2557                 return -EINVAL;
2558
2559         *val = i915.guc_log_level;
2560
2561         return 0;
2562 }
2563
2564 static int i915_guc_log_control_set(void *data, u64 val)
2565 {
2566         struct drm_device *dev = data;
2567         struct drm_i915_private *dev_priv = to_i915(dev);
2568         int ret;
2569
2570         if (!dev_priv->guc.log.vma)
2571                 return -EINVAL;
2572
2573         ret = mutex_lock_interruptible(&dev->struct_mutex);
2574         if (ret)
2575                 return ret;
2576
2577         intel_runtime_pm_get(dev_priv);
2578         ret = i915_guc_log_control(dev_priv, val);
2579         intel_runtime_pm_put(dev_priv);
2580
2581         mutex_unlock(&dev->struct_mutex);
2582         return ret;
2583 }
2584
2585 DEFINE_SIMPLE_ATTRIBUTE(i915_guc_log_control_fops,
2586                         i915_guc_log_control_get, i915_guc_log_control_set,
2587                         "%lld\n");
2588
2589 static int i915_edp_psr_status(struct seq_file *m, void *data)
2590 {
2591         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2592         u32 psrperf = 0;
2593         u32 stat[3];
2594         enum pipe pipe;
2595         bool enabled = false;
2596
2597         if (!HAS_PSR(dev_priv)) {
2598                 seq_puts(m, "PSR not supported\n");
2599                 return 0;
2600         }
2601
2602         intel_runtime_pm_get(dev_priv);
2603
2604         mutex_lock(&dev_priv->psr.lock);
2605         seq_printf(m, "Sink_Support: %s\n", yesno(dev_priv->psr.sink_support));
2606         seq_printf(m, "Source_OK: %s\n", yesno(dev_priv->psr.source_ok));
2607         seq_printf(m, "Enabled: %s\n", yesno((bool)dev_priv->psr.enabled));
2608         seq_printf(m, "Active: %s\n", yesno(dev_priv->psr.active));
2609         seq_printf(m, "Busy frontbuffer bits: 0x%03x\n",
2610                    dev_priv->psr.busy_frontbuffer_bits);
2611         seq_printf(m, "Re-enable work scheduled: %s\n",
2612                    yesno(work_busy(&dev_priv->psr.work.work)));
2613
2614         if (HAS_DDI(dev_priv))
2615                 enabled = I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE;
2616         else {
2617                 for_each_pipe(dev_priv, pipe) {
2618                         enum transcoder cpu_transcoder =
2619                                 intel_pipe_to_cpu_transcoder(dev_priv, pipe);
2620                         enum intel_display_power_domain power_domain;
2621
2622                         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
2623                         if (!intel_display_power_get_if_enabled(dev_priv,
2624                                                                 power_domain))
2625                                 continue;
2626
2627                         stat[pipe] = I915_READ(VLV_PSRSTAT(pipe)) &
2628                                 VLV_EDP_PSR_CURR_STATE_MASK;
2629                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2630                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2631                                 enabled = true;
2632
2633                         intel_display_power_put(dev_priv, power_domain);
2634                 }
2635         }
2636
2637         seq_printf(m, "Main link in standby mode: %s\n",
2638                    yesno(dev_priv->psr.link_standby));
2639
2640         seq_printf(m, "HW Enabled & Active bit: %s", yesno(enabled));
2641
2642         if (!HAS_DDI(dev_priv))
2643                 for_each_pipe(dev_priv, pipe) {
2644                         if ((stat[pipe] == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
2645                             (stat[pipe] == VLV_EDP_PSR_ACTIVE_SF_UPDATE))
2646                                 seq_printf(m, " pipe %c", pipe_name(pipe));
2647                 }
2648         seq_puts(m, "\n");
2649
2650         /*
2651          * VLV/CHV PSR has no kind of performance counter
2652          * SKL+ Perf counter is reset to 0 everytime DC state is entered
2653          */
2654         if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
2655                 psrperf = I915_READ(EDP_PSR_PERF_CNT) &
2656                         EDP_PSR_PERF_CNT_MASK;
2657
2658                 seq_printf(m, "Performance_Counter: %u\n", psrperf);
2659         }
2660         mutex_unlock(&dev_priv->psr.lock);
2661
2662         intel_runtime_pm_put(dev_priv);
2663         return 0;
2664 }
2665
2666 static int i915_sink_crc(struct seq_file *m, void *data)
2667 {
2668         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2669         struct drm_device *dev = &dev_priv->drm;
2670         struct intel_connector *connector;
2671         struct intel_dp *intel_dp = NULL;
2672         int ret;
2673         u8 crc[6];
2674
2675         drm_modeset_lock_all(dev);
2676         for_each_intel_connector(dev, connector) {
2677                 struct drm_crtc *crtc;
2678
2679                 if (!connector->base.state->best_encoder)
2680                         continue;
2681
2682                 crtc = connector->base.state->crtc;
2683                 if (!crtc->state->active)
2684                         continue;
2685
2686                 if (connector->base.connector_type != DRM_MODE_CONNECTOR_eDP)
2687                         continue;
2688
2689                 intel_dp = enc_to_intel_dp(connector->base.state->best_encoder);
2690
2691                 ret = intel_dp_sink_crc(intel_dp, crc);
2692                 if (ret)
2693                         goto out;
2694
2695                 seq_printf(m, "%02x%02x%02x%02x%02x%02x\n",
2696                            crc[0], crc[1], crc[2],
2697                            crc[3], crc[4], crc[5]);
2698                 goto out;
2699         }
2700         ret = -ENODEV;
2701 out:
2702         drm_modeset_unlock_all(dev);
2703         return ret;
2704 }
2705
2706 static int i915_energy_uJ(struct seq_file *m, void *data)
2707 {
2708         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2709         u64 power;
2710         u32 units;
2711
2712         if (INTEL_GEN(dev_priv) < 6)
2713                 return -ENODEV;
2714
2715         intel_runtime_pm_get(dev_priv);
2716
2717         rdmsrl(MSR_RAPL_POWER_UNIT, power);
2718         power = (power & 0x1f00) >> 8;
2719         units = 1000000 / (1 << power); /* convert to uJ */
2720         power = I915_READ(MCH_SECP_NRG_STTS);
2721         power *= units;
2722
2723         intel_runtime_pm_put(dev_priv);
2724
2725         seq_printf(m, "%llu", (long long unsigned)power);
2726
2727         return 0;
2728 }
2729
2730 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
2731 {
2732         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2733         struct pci_dev *pdev = dev_priv->drm.pdev;
2734
2735         if (!HAS_RUNTIME_PM(dev_priv))
2736                 seq_puts(m, "Runtime power management not supported\n");
2737
2738         seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
2739         seq_printf(m, "IRQs disabled: %s\n",
2740                    yesno(!intel_irqs_enabled(dev_priv)));
2741 #ifdef CONFIG_PM
2742         seq_printf(m, "Usage count: %d\n",
2743                    atomic_read(&dev_priv->drm.dev->power.usage_count));
2744 #else
2745         seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
2746 #endif
2747         seq_printf(m, "PCI device power state: %s [%d]\n",
2748                    pci_power_name(pdev->current_state),
2749                    pdev->current_state);
2750
2751         return 0;
2752 }
2753
2754 static int i915_power_domain_info(struct seq_file *m, void *unused)
2755 {
2756         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2757         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2758         int i;
2759
2760         mutex_lock(&power_domains->lock);
2761
2762         seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
2763         for (i = 0; i < power_domains->power_well_count; i++) {
2764                 struct i915_power_well *power_well;
2765                 enum intel_display_power_domain power_domain;
2766
2767                 power_well = &power_domains->power_wells[i];
2768                 seq_printf(m, "%-25s %d\n", power_well->name,
2769                            power_well->count);
2770
2771                 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
2772                      power_domain++) {
2773                         if (!(BIT(power_domain) & power_well->domains))
2774                                 continue;
2775
2776                         seq_printf(m, "  %-23s %d\n",
2777                                  intel_display_power_domain_str(power_domain),
2778                                  power_domains->domain_use_count[power_domain]);
2779                 }
2780         }
2781
2782         mutex_unlock(&power_domains->lock);
2783
2784         return 0;
2785 }
2786
2787 static int i915_dmc_info(struct seq_file *m, void *unused)
2788 {
2789         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2790         struct intel_csr *csr;
2791
2792         if (!HAS_CSR(dev_priv)) {
2793                 seq_puts(m, "not supported\n");
2794                 return 0;
2795         }
2796
2797         csr = &dev_priv->csr;
2798
2799         intel_runtime_pm_get(dev_priv);
2800
2801         seq_printf(m, "fw loaded: %s\n", yesno(csr->dmc_payload != NULL));
2802         seq_printf(m, "path: %s\n", csr->fw_path);
2803
2804         if (!csr->dmc_payload)
2805                 goto out;
2806
2807         seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
2808                    CSR_VERSION_MINOR(csr->version));
2809
2810         if (IS_SKYLAKE(dev_priv) && csr->version >= CSR_VERSION(1, 6)) {
2811                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2812                            I915_READ(SKL_CSR_DC3_DC5_COUNT));
2813                 seq_printf(m, "DC5 -> DC6 count: %d\n",
2814                            I915_READ(SKL_CSR_DC5_DC6_COUNT));
2815         } else if (IS_BROXTON(dev_priv) && csr->version >= CSR_VERSION(1, 4)) {
2816                 seq_printf(m, "DC3 -> DC5 count: %d\n",
2817                            I915_READ(BXT_CSR_DC3_DC5_COUNT));
2818         }
2819
2820 out:
2821         seq_printf(m, "program base: 0x%08x\n", I915_READ(CSR_PROGRAM(0)));
2822         seq_printf(m, "ssp base: 0x%08x\n", I915_READ(CSR_SSP_BASE));
2823         seq_printf(m, "htp: 0x%08x\n", I915_READ(CSR_HTP_SKL));
2824
2825         intel_runtime_pm_put(dev_priv);
2826
2827         return 0;
2828 }
2829
2830 static void intel_seq_print_mode(struct seq_file *m, int tabs,
2831                                  struct drm_display_mode *mode)
2832 {
2833         int i;
2834
2835         for (i = 0; i < tabs; i++)
2836                 seq_putc(m, '\t');
2837
2838         seq_printf(m, "id %d:\"%s\" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x\n",
2839                    mode->base.id, mode->name,
2840                    mode->vrefresh, mode->clock,
2841                    mode->hdisplay, mode->hsync_start,
2842                    mode->hsync_end, mode->htotal,
2843                    mode->vdisplay, mode->vsync_start,
2844                    mode->vsync_end, mode->vtotal,
2845                    mode->type, mode->flags);
2846 }
2847
2848 static void intel_encoder_info(struct seq_file *m,
2849                                struct intel_crtc *intel_crtc,
2850                                struct intel_encoder *intel_encoder)
2851 {
2852         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2853         struct drm_device *dev = &dev_priv->drm;
2854         struct drm_crtc *crtc = &intel_crtc->base;
2855         struct intel_connector *intel_connector;
2856         struct drm_encoder *encoder;
2857
2858         encoder = &intel_encoder->base;
2859         seq_printf(m, "\tencoder %d: type: %s, connectors:\n",
2860                    encoder->base.id, encoder->name);
2861         for_each_connector_on_encoder(dev, encoder, intel_connector) {
2862                 struct drm_connector *connector = &intel_connector->base;
2863                 seq_printf(m, "\t\tconnector %d: type: %s, status: %s",
2864                            connector->base.id,
2865                            connector->name,
2866                            drm_get_connector_status_name(connector->status));
2867                 if (connector->status == connector_status_connected) {
2868                         struct drm_display_mode *mode = &crtc->mode;
2869                         seq_printf(m, ", mode:\n");
2870                         intel_seq_print_mode(m, 2, mode);
2871                 } else {
2872                         seq_putc(m, '\n');
2873                 }
2874         }
2875 }
2876
2877 static void intel_crtc_info(struct seq_file *m, struct intel_crtc *intel_crtc)
2878 {
2879         struct drm_i915_private *dev_priv = node_to_i915(m->private);
2880         struct drm_device *dev = &dev_priv->drm;
2881         struct drm_crtc *crtc = &intel_crtc->base;
2882         struct intel_encoder *intel_encoder;
2883         struct drm_plane_state *plane_state = crtc->primary->state;
2884         struct drm_framebuffer *fb = plane_state->fb;
2885
2886         if (fb)
2887                 seq_printf(m, "\tfb: %d, pos: %dx%d, size: %dx%d\n",
2888                            fb->base.id, plane_state->src_x >> 16,
2889                            plane_state->src_y >> 16, fb->width, fb->height);
2890         else
2891                 seq_puts(m, "\tprimary plane disabled\n");
2892         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
2893                 intel_encoder_info(m, intel_crtc, intel_encoder);
2894 }
2895
2896 static void intel_panel_info(struct seq_file *m, struct intel_panel *panel)
2897 {
2898         struct drm_display_mode *mode = panel->fixed_mode;
2899
2900         seq_printf(m, "\tfixed mode:\n");
2901         intel_seq_print_mode(m, 2, mode);
2902 }
2903
2904 static void intel_dp_info(struct seq_file *m,
2905                           struct intel_connector *intel_connector)
2906 {
2907         struct intel_encoder *intel_encoder = intel_connector->encoder;
2908         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2909
2910         seq_printf(m, "\tDPCD rev: %x\n", intel_dp->dpcd[DP_DPCD_REV]);
2911         seq_printf(m, "\taudio support: %s\n", yesno(intel_dp->has_audio));
2912         if (intel_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)
2913                 intel_panel_info(m, &intel_connector->panel);
2914
2915         drm_dp_downstream_debug(m, intel_dp->dpcd, intel_dp->downstream_ports,
2916                                 &intel_dp->aux);
2917 }
2918
2919 static void intel_hdmi_info(struct seq_file *m,
2920                             struct intel_connector *intel_connector)
2921 {
2922         struct intel_encoder *intel_encoder = intel_connector->encoder;
2923         struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
2924
2925         seq_printf(m, "\taudio support: %s\n", yesno(intel_hdmi->has_audio));
2926 }
2927
2928 static void intel_lvds_info(struct seq_file *m,
2929                             struct intel_connector *intel_connector)
2930 {
2931         intel_panel_info(m, &intel_connector->panel);
2932 }
2933
2934 static void intel_connector_info(struct seq_file *m,
2935                                  struct drm_connector *connector)
2936 {
2937         struct intel_connector *intel_connector = to_intel_connector(connector);
2938         struct intel_encoder *intel_encoder = intel_connector->encoder;
2939         struct drm_display_mode *mode;
2940
2941         seq_printf(m, "connector %d: type %s, status: %s\n",
2942                    connector->base.id, connector->name,
2943                    drm_get_connector_status_name(connector->status));
2944         if (connector->status == connector_status_connected) {
2945                 seq_printf(m, "\tname: %s\n", connector->display_info.name);
2946                 seq_printf(m, "\tphysical dimensions: %dx%dmm\n",
2947                            connector->display_info.width_mm,
2948                            connector->display_info.height_mm);
2949                 seq_printf(m, "\tsubpixel order: %s\n",
2950                            drm_get_subpixel_order_name(connector->display_info.subpixel_order));
2951                 seq_printf(m, "\tCEA rev: %d\n",
2952                            connector->display_info.cea_rev);
2953         }
2954
2955         if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
2956                 return;
2957
2958         switch (connector->connector_type) {
2959         case DRM_MODE_CONNECTOR_DisplayPort:
2960         case DRM_MODE_CONNECTOR_eDP:
2961                 intel_dp_info(m, intel_connector);
2962                 break;
2963         case DRM_MODE_CONNECTOR_LVDS:
2964                 if (intel_encoder->type == INTEL_OUTPUT_LVDS)
2965                         intel_lvds_info(m, intel_connector);
2966                 break;
2967         case DRM_MODE_CONNECTOR_HDMIA:
2968                 if (intel_encoder->type == INTEL_OUTPUT_HDMI ||
2969                     intel_encoder->type == INTEL_OUTPUT_UNKNOWN)
2970                         intel_hdmi_info(m, intel_connector);
2971                 break;
2972         default:
2973                 break;
2974         }
2975
2976         seq_printf(m, "\tmodes:\n");
2977         list_for_each_entry(mode, &connector->modes, head)
2978                 intel_seq_print_mode(m, 2, mode);
2979 }
2980
2981 static bool cursor_active(struct drm_i915_private *dev_priv, int pipe)
2982 {
2983         u32 state;
2984
2985         if (IS_845G(dev_priv) || IS_I865G(dev_priv))
2986                 state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
2987         else
2988                 state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
2989
2990         return state;
2991 }
2992
2993 static bool cursor_position(struct drm_i915_private *dev_priv,
2994                             int pipe, int *x, int *y)
2995 {
2996         u32 pos;
2997
2998         pos = I915_READ(CURPOS(pipe));
2999
3000         *x = (pos >> CURSOR_X_SHIFT) & CURSOR_POS_MASK;
3001         if (pos & (CURSOR_POS_SIGN << CURSOR_X_SHIFT))
3002                 *x = -*x;
3003
3004         *y = (pos >> CURSOR_Y_SHIFT) & CURSOR_POS_MASK;
3005         if (pos & (CURSOR_POS_SIGN << CURSOR_Y_SHIFT))
3006                 *y = -*y;
3007
3008         return cursor_active(dev_priv, pipe);
3009 }
3010
3011 static const char *plane_type(enum drm_plane_type type)
3012 {
3013         switch (type) {
3014         case DRM_PLANE_TYPE_OVERLAY:
3015                 return "OVL";
3016         case DRM_PLANE_TYPE_PRIMARY:
3017                 return "PRI";
3018         case DRM_PLANE_TYPE_CURSOR:
3019                 return "CUR";
3020         /*
3021          * Deliberately omitting default: to generate compiler warnings
3022          * when a new drm_plane_type gets added.
3023          */
3024         }
3025
3026         return "unknown";
3027 }
3028
3029 static const char *plane_rotation(unsigned int rotation)
3030 {
3031         static char buf[48];
3032         /*
3033          * According to doc only one DRM_ROTATE_ is allowed but this
3034          * will print them all to visualize if the values are misused
3035          */
3036         snprintf(buf, sizeof(buf),
3037                  "%s%s%s%s%s%s(0x%08x)",
3038                  (rotation & DRM_ROTATE_0) ? "0 " : "",
3039                  (rotation & DRM_ROTATE_90) ? "90 " : "",
3040                  (rotation & DRM_ROTATE_180) ? "180 " : "",
3041                  (rotation & DRM_ROTATE_270) ? "270 " : "",
3042                  (rotation & DRM_REFLECT_X) ? "FLIPX " : "",
3043                  (rotation & DRM_REFLECT_Y) ? "FLIPY " : "",
3044                  rotation);
3045
3046         return buf;
3047 }
3048
3049 static void intel_plane_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3050 {
3051         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3052         struct drm_device *dev = &dev_priv->drm;
3053         struct intel_plane *intel_plane;
3054
3055         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3056                 struct drm_plane_state *state;
3057                 struct drm_plane *plane = &intel_plane->base;
3058                 char *format_name;
3059
3060                 if (!plane->state) {
3061                         seq_puts(m, "plane->state is NULL!\n");
3062                         continue;
3063                 }
3064
3065                 state = plane->state;
3066
3067                 if (state->fb) {
3068                         format_name = drm_get_format_name(state->fb->pixel_format);
3069                 } else {
3070                         format_name = kstrdup("N/A", GFP_KERNEL);
3071                 }
3072
3073                 seq_printf(m, "\t--Plane id %d: type=%s, crtc_pos=%4dx%4d, crtc_size=%4dx%4d, src_pos=%d.%04ux%d.%04u, src_size=%d.%04ux%d.%04u, format=%s, rotation=%s\n",
3074                            plane->base.id,
3075                            plane_type(intel_plane->base.type),
3076                            state->crtc_x, state->crtc_y,
3077                            state->crtc_w, state->crtc_h,
3078                            (state->src_x >> 16),
3079                            ((state->src_x & 0xffff) * 15625) >> 10,
3080                            (state->src_y >> 16),
3081                            ((state->src_y & 0xffff) * 15625) >> 10,
3082                            (state->src_w >> 16),
3083                            ((state->src_w & 0xffff) * 15625) >> 10,
3084                            (state->src_h >> 16),
3085                            ((state->src_h & 0xffff) * 15625) >> 10,
3086                            format_name,
3087                            plane_rotation(state->rotation));
3088
3089                 kfree(format_name);
3090         }
3091 }
3092
3093 static void intel_scaler_info(struct seq_file *m, struct intel_crtc *intel_crtc)
3094 {
3095         struct intel_crtc_state *pipe_config;
3096         int num_scalers = intel_crtc->num_scalers;
3097         int i;
3098
3099         pipe_config = to_intel_crtc_state(intel_crtc->base.state);
3100
3101         /* Not all platformas have a scaler */
3102         if (num_scalers) {
3103                 seq_printf(m, "\tnum_scalers=%d, scaler_users=%x scaler_id=%d",
3104                            num_scalers,
3105                            pipe_config->scaler_state.scaler_users,
3106                            pipe_config->scaler_state.scaler_id);
3107
3108                 for (i = 0; i < SKL_NUM_SCALERS; i++) {
3109                         struct intel_scaler *sc =
3110                                         &pipe_config->scaler_state.scalers[i];
3111
3112                         seq_printf(m, ", scalers[%d]: use=%s, mode=%x",
3113                                    i, yesno(sc->in_use), sc->mode);
3114                 }
3115                 seq_puts(m, "\n");
3116         } else {
3117                 seq_puts(m, "\tNo scalers available on this platform\n");
3118         }
3119 }
3120
3121 static int i915_display_info(struct seq_file *m, void *unused)
3122 {
3123         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3124         struct drm_device *dev = &dev_priv->drm;
3125         struct intel_crtc *crtc;
3126         struct drm_connector *connector;
3127
3128         intel_runtime_pm_get(dev_priv);
3129         drm_modeset_lock_all(dev);
3130         seq_printf(m, "CRTC info\n");
3131         seq_printf(m, "---------\n");
3132         for_each_intel_crtc(dev, crtc) {
3133                 bool active;
3134                 struct intel_crtc_state *pipe_config;
3135                 int x, y;
3136
3137                 pipe_config = to_intel_crtc_state(crtc->base.state);
3138
3139                 seq_printf(m, "CRTC %d: pipe: %c, active=%s, (size=%dx%d), dither=%s, bpp=%d\n",
3140                            crtc->base.base.id, pipe_name(crtc->pipe),
3141                            yesno(pipe_config->base.active),
3142                            pipe_config->pipe_src_w, pipe_config->pipe_src_h,
3143                            yesno(pipe_config->dither), pipe_config->pipe_bpp);
3144
3145                 if (pipe_config->base.active) {
3146                         intel_crtc_info(m, crtc);
3147
3148                         active = cursor_position(dev_priv, crtc->pipe, &x, &y);
3149                         seq_printf(m, "\tcursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s\n",
3150                                    yesno(crtc->cursor_base),
3151                                    x, y, crtc->base.cursor->state->crtc_w,
3152                                    crtc->base.cursor->state->crtc_h,
3153                                    crtc->cursor_addr, yesno(active));
3154                         intel_scaler_info(m, crtc);
3155                         intel_plane_info(m, crtc);
3156                 }
3157
3158                 seq_printf(m, "\tunderrun reporting: cpu=%s pch=%s \n",
3159                            yesno(!crtc->cpu_fifo_underrun_disabled),
3160                            yesno(!crtc->pch_fifo_underrun_disabled));
3161         }
3162
3163         seq_printf(m, "\n");
3164         seq_printf(m, "Connector info\n");
3165         seq_printf(m, "--------------\n");
3166         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3167                 intel_connector_info(m, connector);
3168         }
3169         drm_modeset_unlock_all(dev);
3170         intel_runtime_pm_put(dev_priv);
3171
3172         return 0;
3173 }
3174
3175 static int i915_engine_info(struct seq_file *m, void *unused)
3176 {
3177         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3178         struct intel_engine_cs *engine;
3179         enum intel_engine_id id;
3180
3181         intel_runtime_pm_get(dev_priv);
3182
3183         for_each_engine(engine, dev_priv, id) {
3184                 struct intel_breadcrumbs *b = &engine->breadcrumbs;
3185                 struct drm_i915_gem_request *rq;
3186                 struct rb_node *rb;
3187                 u64 addr;
3188
3189                 seq_printf(m, "%s\n", engine->name);
3190                 seq_printf(m, "\tcurrent seqno %x, last %x, hangcheck %x [score %d]\n",
3191                            intel_engine_get_seqno(engine),
3192                            engine->last_submitted_seqno,
3193                            engine->hangcheck.seqno,
3194                            engine->hangcheck.score);
3195
3196                 rcu_read_lock();
3197
3198                 seq_printf(m, "\tRequests:\n");
3199
3200                 rq = list_first_entry(&engine->request_list,
3201                                 struct drm_i915_gem_request, link);
3202                 if (&rq->link != &engine->request_list)
3203                         print_request(m, rq, "\t\tfirst  ");
3204
3205                 rq = list_last_entry(&engine->request_list,
3206                                 struct drm_i915_gem_request, link);
3207                 if (&rq->link != &engine->request_list)
3208                         print_request(m, rq, "\t\tlast   ");
3209
3210                 rq = i915_gem_find_active_request(engine);
3211                 if (rq) {
3212                         print_request(m, rq, "\t\tactive ");
3213                         seq_printf(m,
3214                                    "\t\t[head %04x, postfix %04x, tail %04x, batch 0x%08x_%08x]\n",
3215                                    rq->head, rq->postfix, rq->tail,
3216                                    rq->batch ? upper_32_bits(rq->batch->node.start) : ~0u,
3217                                    rq->batch ? lower_32_bits(rq->batch->node.start) : ~0u);
3218                 }
3219
3220                 seq_printf(m, "\tRING_START: 0x%08x [0x%08x]\n",
3221                            I915_READ(RING_START(engine->mmio_base)),
3222                            rq ? i915_ggtt_offset(rq->ring->vma) : 0);
3223                 seq_printf(m, "\tRING_HEAD:  0x%08x [0x%08x]\n",
3224                            I915_READ(RING_HEAD(engine->mmio_base)) & HEAD_ADDR,
3225                            rq ? rq->ring->head : 0);
3226                 seq_printf(m, "\tRING_TAIL:  0x%08x [0x%08x]\n",
3227                            I915_READ(RING_TAIL(engine->mmio_base)) & TAIL_ADDR,
3228                            rq ? rq->ring->tail : 0);
3229                 seq_printf(m, "\tRING_CTL:   0x%08x [%s]\n",
3230                            I915_READ(RING_CTL(engine->mmio_base)),
3231                            I915_READ(RING_CTL(engine->mmio_base)) & (RING_WAIT | RING_WAIT_SEMAPHORE) ? "waiting" : "");
3232
3233                 rcu_read_unlock();
3234
3235                 addr = intel_engine_get_active_head(engine);
3236                 seq_printf(m, "\tACTHD:  0x%08x_%08x\n",
3237                            upper_32_bits(addr), lower_32_bits(addr));
3238                 addr = intel_engine_get_last_batch_head(engine);
3239                 seq_printf(m, "\tBBADDR: 0x%08x_%08x\n",
3240                            upper_32_bits(addr), lower_32_bits(addr));
3241
3242                 if (i915.enable_execlists) {
3243                         u32 ptr, read, write;
3244
3245                         seq_printf(m, "\tExeclist status: 0x%08x %08x\n",
3246                                    I915_READ(RING_EXECLIST_STATUS_LO(engine)),
3247                                    I915_READ(RING_EXECLIST_STATUS_HI(engine)));
3248
3249                         ptr = I915_READ(RING_CONTEXT_STATUS_PTR(engine));
3250                         read = GEN8_CSB_READ_PTR(ptr);
3251                         write = GEN8_CSB_WRITE_PTR(ptr);
3252                         seq_printf(m, "\tExeclist CSB read %d, write %d\n",
3253                                    read, write);
3254                         if (read >= GEN8_CSB_ENTRIES)
3255                                 read = 0;
3256                         if (write >= GEN8_CSB_ENTRIES)
3257                                 write = 0;
3258                         if (read > write)
3259                                 write += GEN8_CSB_ENTRIES;
3260                         while (read < write) {
3261                                 unsigned int idx = ++read % GEN8_CSB_ENTRIES;
3262
3263                                 seq_printf(m, "\tExeclist CSB[%d]: 0x%08x, context: %d\n",
3264                                            idx,
3265                                            I915_READ(RING_CONTEXT_STATUS_BUF_LO(engine, idx)),
3266                                            I915_READ(RING_CONTEXT_STATUS_BUF_HI(engine, idx)));
3267                         }
3268
3269                         rcu_read_lock();
3270                         rq = READ_ONCE(engine->execlist_port[0].request);
3271                         if (rq)
3272                                 print_request(m, rq, "\t\tELSP[0] ");
3273                         else
3274                                 seq_printf(m, "\t\tELSP[0] idle\n");
3275                         rq = READ_ONCE(engine->execlist_port[1].request);
3276                         if (rq)
3277                                 print_request(m, rq, "\t\tELSP[1] ");
3278                         else
3279                                 seq_printf(m, "\t\tELSP[1] idle\n");
3280                         rcu_read_unlock();
3281                 } else if (INTEL_GEN(dev_priv) > 6) {
3282                         seq_printf(m, "\tPP_DIR_BASE: 0x%08x\n",
3283                                    I915_READ(RING_PP_DIR_BASE(engine)));
3284                         seq_printf(m, "\tPP_DIR_BASE_READ: 0x%08x\n",
3285                                    I915_READ(RING_PP_DIR_BASE_READ(engine)));
3286                         seq_printf(m, "\tPP_DIR_DCLV: 0x%08x\n",
3287                                    I915_READ(RING_PP_DIR_DCLV(engine)));
3288                 }
3289
3290                 spin_lock(&b->lock);
3291                 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
3292                         struct intel_wait *w = container_of(rb, typeof(*w), node);
3293
3294                         seq_printf(m, "\t%s [%d] waiting for %x\n",
3295                                    w->tsk->comm, w->tsk->pid, w->seqno);
3296                 }
3297                 spin_unlock(&b->lock);
3298
3299                 seq_puts(m, "\n");
3300         }
3301
3302         intel_runtime_pm_put(dev_priv);
3303
3304         return 0;
3305 }
3306
3307 static int i915_semaphore_status(struct seq_file *m, void *unused)
3308 {
3309         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3310         struct drm_device *dev = &dev_priv->drm;
3311         struct intel_engine_cs *engine;
3312         int num_rings = INTEL_INFO(dev_priv)->num_rings;
3313         enum intel_engine_id id;
3314         int j, ret;
3315
3316         if (!i915.semaphores) {
3317                 seq_puts(m, "Semaphores are disabled\n");
3318                 return 0;
3319         }
3320
3321         ret = mutex_lock_interruptible(&dev->struct_mutex);
3322         if (ret)
3323                 return ret;
3324         intel_runtime_pm_get(dev_priv);
3325
3326         if (IS_BROADWELL(dev_priv)) {
3327                 struct page *page;
3328                 uint64_t *seqno;
3329
3330                 page = i915_gem_object_get_page(dev_priv->semaphore->obj, 0);
3331
3332                 seqno = (uint64_t *)kmap_atomic(page);
3333                 for_each_engine(engine, dev_priv, id) {
3334                         uint64_t offset;
3335
3336                         seq_printf(m, "%s\n", engine->name);
3337
3338                         seq_puts(m, "  Last signal:");
3339                         for (j = 0; j < num_rings; j++) {
3340                                 offset = id * I915_NUM_ENGINES + j;
3341                                 seq_printf(m, "0x%08llx (0x%02llx) ",
3342                                            seqno[offset], offset * 8);
3343                         }
3344                         seq_putc(m, '\n');
3345
3346                         seq_puts(m, "  Last wait:  ");
3347                         for (j = 0; j < num_rings; j++) {
3348                                 offset = id + (j * I915_NUM_ENGINES);
3349                                 seq_printf(m, "0x%08llx (0x%02llx) ",
3350                                            seqno[offset], offset * 8);
3351                         }
3352                         seq_putc(m, '\n');
3353
3354                 }
3355                 kunmap_atomic(seqno);
3356         } else {
3357                 seq_puts(m, "  Last signal:");
3358                 for_each_engine(engine, dev_priv, id)
3359                         for (j = 0; j < num_rings; j++)
3360                                 seq_printf(m, "0x%08x\n",
3361                                            I915_READ(engine->semaphore.mbox.signal[j]));
3362                 seq_putc(m, '\n');
3363         }
3364
3365         seq_puts(m, "\nSync seqno:\n");
3366         for_each_engine(engine, dev_priv, id) {
3367                 for (j = 0; j < num_rings; j++)
3368                         seq_printf(m, "  0x%08x ",
3369                                    engine->semaphore.sync_seqno[j]);
3370                 seq_putc(m, '\n');
3371         }
3372         seq_putc(m, '\n');
3373
3374         intel_runtime_pm_put(dev_priv);
3375         mutex_unlock(&dev->struct_mutex);
3376         return 0;
3377 }
3378
3379 static int i915_shared_dplls_info(struct seq_file *m, void *unused)
3380 {
3381         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3382         struct drm_device *dev = &dev_priv->drm;
3383         int i;
3384
3385         drm_modeset_lock_all(dev);
3386         for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3387                 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
3388
3389                 seq_printf(m, "DPLL%i: %s, id: %i\n", i, pll->name, pll->id);
3390                 seq_printf(m, " crtc_mask: 0x%08x, active: 0x%x, on: %s\n",
3391                            pll->config.crtc_mask, pll->active_mask, yesno(pll->on));
3392                 seq_printf(m, " tracked hardware state:\n");
3393                 seq_printf(m, " dpll:    0x%08x\n", pll->config.hw_state.dpll);
3394                 seq_printf(m, " dpll_md: 0x%08x\n",
3395                            pll->config.hw_state.dpll_md);
3396                 seq_printf(m, " fp0:     0x%08x\n", pll->config.hw_state.fp0);
3397                 seq_printf(m, " fp1:     0x%08x\n", pll->config.hw_state.fp1);
3398                 seq_printf(m, " wrpll:   0x%08x\n", pll->config.hw_state.wrpll);
3399         }
3400         drm_modeset_unlock_all(dev);
3401
3402         return 0;
3403 }
3404
3405 static int i915_wa_registers(struct seq_file *m, void *unused)
3406 {
3407         int i;
3408         int ret;
3409         struct intel_engine_cs *engine;
3410         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3411         struct drm_device *dev = &dev_priv->drm;
3412         struct i915_workarounds *workarounds = &dev_priv->workarounds;
3413         enum intel_engine_id id;
3414
3415         ret = mutex_lock_interruptible(&dev->struct_mutex);
3416         if (ret)
3417                 return ret;
3418
3419         intel_runtime_pm_get(dev_priv);
3420
3421         seq_printf(m, "Workarounds applied: %d\n", workarounds->count);
3422         for_each_engine(engine, dev_priv, id)
3423                 seq_printf(m, "HW whitelist count for %s: %d\n",
3424                            engine->name, workarounds->hw_whitelist_count[id]);
3425         for (i = 0; i < workarounds->count; ++i) {
3426                 i915_reg_t addr;
3427                 u32 mask, value, read;
3428                 bool ok;
3429
3430                 addr = workarounds->reg[i].addr;
3431                 mask = workarounds->reg[i].mask;
3432                 value = workarounds->reg[i].value;
3433                 read = I915_READ(addr);
3434                 ok = (value & mask) == (read & mask);
3435                 seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s\n",
3436                            i915_mmio_reg_offset(addr), value, mask, read, ok ? "OK" : "FAIL");
3437         }
3438
3439         intel_runtime_pm_put(dev_priv);
3440         mutex_unlock(&dev->struct_mutex);
3441
3442         return 0;
3443 }
3444
3445 static int i915_ddb_info(struct seq_file *m, void *unused)
3446 {
3447         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3448         struct drm_device *dev = &dev_priv->drm;
3449         struct skl_ddb_allocation *ddb;
3450         struct skl_ddb_entry *entry;
3451         enum pipe pipe;
3452         int plane;
3453
3454         if (INTEL_GEN(dev_priv) < 9)
3455                 return 0;
3456
3457         drm_modeset_lock_all(dev);
3458
3459         ddb = &dev_priv->wm.skl_hw.ddb;
3460
3461         seq_printf(m, "%-15s%8s%8s%8s\n", "", "Start", "End", "Size");
3462
3463         for_each_pipe(dev_priv, pipe) {
3464                 seq_printf(m, "Pipe %c\n", pipe_name(pipe));
3465
3466                 for_each_plane(dev_priv, pipe, plane) {
3467                         entry = &ddb->plane[pipe][plane];
3468                         seq_printf(m, "  Plane%-8d%8u%8u%8u\n", plane + 1,
3469                                    entry->start, entry->end,
3470                                    skl_ddb_entry_size(entry));
3471                 }
3472
3473                 entry = &ddb->plane[pipe][PLANE_CURSOR];
3474                 seq_printf(m, "  %-13s%8u%8u%8u\n", "Cursor", entry->start,
3475                            entry->end, skl_ddb_entry_size(entry));
3476         }
3477
3478         drm_modeset_unlock_all(dev);
3479
3480         return 0;
3481 }
3482
3483 static void drrs_status_per_crtc(struct seq_file *m,
3484                                  struct drm_device *dev,
3485                                  struct intel_crtc *intel_crtc)
3486 {
3487         struct drm_i915_private *dev_priv = to_i915(dev);
3488         struct i915_drrs *drrs = &dev_priv->drrs;
3489         int vrefresh = 0;
3490         struct drm_connector *connector;
3491
3492         drm_for_each_connector(connector, dev) {
3493                 if (connector->state->crtc != &intel_crtc->base)
3494                         continue;
3495
3496                 seq_printf(m, "%s:\n", connector->name);
3497         }
3498
3499         if (dev_priv->vbt.drrs_type == STATIC_DRRS_SUPPORT)
3500                 seq_puts(m, "\tVBT: DRRS_type: Static");
3501         else if (dev_priv->vbt.drrs_type == SEAMLESS_DRRS_SUPPORT)
3502                 seq_puts(m, "\tVBT: DRRS_type: Seamless");
3503         else if (dev_priv->vbt.drrs_type == DRRS_NOT_SUPPORTED)
3504                 seq_puts(m, "\tVBT: DRRS_type: None");
3505         else
3506                 seq_puts(m, "\tVBT: DRRS_type: FIXME: Unrecognized Value");
3507
3508         seq_puts(m, "\n\n");
3509
3510         if (to_intel_crtc_state(intel_crtc->base.state)->has_drrs) {
3511                 struct intel_panel *panel;
3512
3513                 mutex_lock(&drrs->mutex);
3514                 /* DRRS Supported */
3515                 seq_puts(m, "\tDRRS Supported: Yes\n");
3516
3517                 /* disable_drrs() will make drrs->dp NULL */
3518                 if (!drrs->dp) {
3519                         seq_puts(m, "Idleness DRRS: Disabled");
3520                         mutex_unlock(&drrs->mutex);
3521                         return;
3522                 }
3523
3524                 panel = &drrs->dp->attached_connector->panel;
3525                 seq_printf(m, "\t\tBusy_frontbuffer_bits: 0x%X",
3526                                         drrs->busy_frontbuffer_bits);
3527
3528                 seq_puts(m, "\n\t\t");
3529                 if (drrs->refresh_rate_type == DRRS_HIGH_RR) {
3530                         seq_puts(m, "DRRS_State: DRRS_HIGH_RR\n");
3531                         vrefresh = panel->fixed_mode->vrefresh;
3532                 } else if (drrs->refresh_rate_type == DRRS_LOW_RR) {
3533                         seq_puts(m, "DRRS_State: DRRS_LOW_RR\n");
3534                         vrefresh = panel->downclock_mode->vrefresh;
3535                 } else {
3536                         seq_printf(m, "DRRS_State: Unknown(%d)\n",
3537                                                 drrs->refresh_rate_type);
3538                         mutex_unlock(&drrs->mutex);
3539                         return;
3540                 }
3541                 seq_printf(m, "\t\tVrefresh: %d", vrefresh);
3542
3543                 seq_puts(m, "\n\t\t");
3544                 mutex_unlock(&drrs->mutex);
3545         } else {
3546                 /* DRRS not supported. Print the VBT parameter*/
3547                 seq_puts(m, "\tDRRS Supported : No");
3548         }
3549         seq_puts(m, "\n");
3550 }
3551
3552 static int i915_drrs_status(struct seq_file *m, void *unused)
3553 {
3554         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3555         struct drm_device *dev = &dev_priv->drm;
3556         struct intel_crtc *intel_crtc;
3557         int active_crtc_cnt = 0;
3558
3559         drm_modeset_lock_all(dev);
3560         for_each_intel_crtc(dev, intel_crtc) {
3561                 if (intel_crtc->base.state->active) {
3562                         active_crtc_cnt++;
3563                         seq_printf(m, "\nCRTC %d:  ", active_crtc_cnt);
3564
3565                         drrs_status_per_crtc(m, dev, intel_crtc);
3566                 }
3567         }
3568         drm_modeset_unlock_all(dev);
3569
3570         if (!active_crtc_cnt)
3571                 seq_puts(m, "No active crtc found\n");
3572
3573         return 0;
3574 }
3575
3576 struct pipe_crc_info {
3577         const char *name;
3578         struct drm_i915_private *dev_priv;
3579         enum pipe pipe;
3580 };
3581
3582 static int i915_dp_mst_info(struct seq_file *m, void *unused)
3583 {
3584         struct drm_i915_private *dev_priv = node_to_i915(m->private);
3585         struct drm_device *dev = &dev_priv->drm;
3586         struct intel_encoder *intel_encoder;
3587         struct intel_digital_port *intel_dig_port;
3588         struct drm_connector *connector;
3589
3590         drm_modeset_lock_all(dev);
3591         drm_for_each_connector(connector, dev) {
3592                 if (connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort)
3593                         continue;
3594
3595                 intel_encoder = intel_attached_encoder(connector);
3596                 if (!intel_encoder || intel_encoder->type == INTEL_OUTPUT_DP_MST)
3597                         continue;
3598
3599                 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
3600                 if (!intel_dig_port->dp.can_mst)
3601                         continue;
3602
3603                 seq_printf(m, "MST Source Port %c\n",
3604                            port_name(intel_dig_port->port));
3605                 drm_dp_mst_dump_topology(m, &intel_dig_port->dp.mst_mgr);
3606         }
3607         drm_modeset_unlock_all(dev);
3608         return 0;
3609 }
3610
3611 static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
3612 {
3613         struct pipe_crc_info *info = inode->i_private;
3614         struct drm_i915_private *dev_priv = info->dev_priv;
3615         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3616
3617         if (info->pipe >= INTEL_INFO(dev_priv)->num_pipes)
3618                 return -ENODEV;
3619
3620         spin_lock_irq(&pipe_crc->lock);
3621
3622         if (pipe_crc->opened) {
3623                 spin_unlock_irq(&pipe_crc->lock);
3624                 return -EBUSY; /* already open */
3625         }
3626
3627         pipe_crc->opened = true;
3628         filep->private_data = inode->i_private;
3629
3630         spin_unlock_irq(&pipe_crc->lock);
3631
3632         return 0;
3633 }
3634
3635 static int i915_pipe_crc_release(struct inode *inode, struct file *filep)
3636 {
3637         struct pipe_crc_info *info = inode->i_private;
3638         struct drm_i915_private *dev_priv = info->dev_priv;
3639         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3640
3641         spin_lock_irq(&pipe_crc->lock);
3642         pipe_crc->opened = false;
3643         spin_unlock_irq(&pipe_crc->lock);
3644
3645         return 0;
3646 }
3647
3648 /* (6 fields, 8 chars each, space separated (5) + '\n') */
3649 #define PIPE_CRC_LINE_LEN       (6 * 8 + 5 + 1)
3650 /* account for \'0' */
3651 #define PIPE_CRC_BUFFER_LEN     (PIPE_CRC_LINE_LEN + 1)
3652
3653 static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc)
3654 {
3655         assert_spin_locked(&pipe_crc->lock);
3656         return CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3657                         INTEL_PIPE_CRC_ENTRIES_NR);
3658 }
3659
3660 static ssize_t
3661 i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count,
3662                    loff_t *pos)
3663 {
3664         struct pipe_crc_info *info = filep->private_data;
3665         struct drm_i915_private *dev_priv = info->dev_priv;
3666         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
3667         char buf[PIPE_CRC_BUFFER_LEN];
3668         int n_entries;
3669         ssize_t bytes_read;
3670
3671         /*
3672          * Don't allow user space to provide buffers not big enough to hold
3673          * a line of data.
3674          */
3675         if (count < PIPE_CRC_LINE_LEN)
3676                 return -EINVAL;
3677
3678         if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE)
3679                 return 0;
3680
3681         /* nothing to read */
3682         spin_lock_irq(&pipe_crc->lock);
3683         while (pipe_crc_data_count(pipe_crc) == 0) {
3684                 int ret;
3685
3686                 if (filep->f_flags & O_NONBLOCK) {
3687                         spin_unlock_irq(&pipe_crc->lock);
3688                         return -EAGAIN;
3689                 }
3690
3691                 ret = wait_event_interruptible_lock_irq(pipe_crc->wq,
3692                                 pipe_crc_data_count(pipe_crc), pipe_crc->lock);
3693                 if (ret) {
3694                         spin_unlock_irq(&pipe_crc->lock);
3695                         return ret;
3696                 }
3697         }
3698
3699         /* We now have one or more entries to read */
3700         n_entries = count / PIPE_CRC_LINE_LEN;
3701
3702         bytes_read = 0;
3703         while (n_entries > 0) {
3704                 struct intel_pipe_crc_entry *entry =
3705                         &pipe_crc->entries[pipe_crc->tail];
3706
3707                 if (CIRC_CNT(pipe_crc->head, pipe_crc->tail,
3708                              INTEL_PIPE_CRC_ENTRIES_NR) < 1)
3709                         break;
3710
3711                 BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR);
3712                 pipe_crc->tail = (pipe_crc->tail + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
3713
3714                 bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN,
3715                                        "%8u %8x %8x %8x %8x %8x\n",
3716                                        entry->frame, entry->crc[0],
3717                                        entry->crc[1], entry->crc[2],
3718                                        entry->crc[3], entry->crc[4]);
3719
3720                 spin_unlock_irq(&pipe_crc->lock);
3721
3722                 if (copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN))
3723                         return -EFAULT;
3724
3725                 user_buf += PIPE_CRC_LINE_LEN;
3726                 n_entries--;
3727
3728                 spin_lock_irq(&pipe_crc->lock);
3729         }
3730
3731         spin_unlock_irq(&pipe_crc->lock);
3732
3733         return bytes_read;
3734 }
3735
3736 static const struct file_operations i915_pipe_crc_fops = {
3737         .owner = THIS_MODULE,
3738         .open = i915_pipe_crc_open,
3739         .read = i915_pipe_crc_read,
3740         .release = i915_pipe_crc_release,
3741 };
3742
3743 static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = {
3744         {
3745                 .name = "i915_pipe_A_crc",
3746                 .pipe = PIPE_A,
3747         },
3748         {
3749                 .name = "i915_pipe_B_crc",
3750                 .pipe = PIPE_B,
3751         },
3752         {
3753                 .name = "i915_pipe_C_crc",
3754                 .pipe = PIPE_C,
3755         },
3756 };
3757
3758 static int i915_pipe_crc_create(struct dentry *root, struct drm_minor *minor,
3759                                 enum pipe pipe)
3760 {
3761         struct drm_i915_private *dev_priv = to_i915(minor->dev);
3762         struct dentry *ent;
3763         struct pipe_crc_info *info = &i915_pipe_crc_data[pipe];
3764
3765         info->dev_priv = dev_priv;
3766         ent = debugfs_create_file(info->name, S_IRUGO, root, info,
3767                                   &i915_pipe_crc_fops);
3768         if (!ent)
3769                 return -ENOMEM;
3770
3771         return drm_add_fake_info_node(minor, ent, info);
3772 }
3773
3774 static const char * const pipe_crc_sources[] = {
3775         "none",
3776         "plane1",
3777         "plane2",
3778         "pf",
3779         "pipe",
3780         "TV",
3781         "DP-B",
3782         "DP-C",
3783         "DP-D",
3784         "auto",
3785 };
3786
3787 static const char *pipe_crc_source_name(enum intel_pipe_crc_source source)
3788 {
3789         BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX);
3790         return pipe_crc_sources[source];
3791 }
3792
3793 static int display_crc_ctl_show(struct seq_file *m, void *data)
3794 {
3795         struct drm_i915_private *dev_priv = m->private;
3796         int i;
3797
3798         for (i = 0; i < I915_MAX_PIPES; i++)
3799                 seq_printf(m, "%c %s\n", pipe_name(i),
3800                            pipe_crc_source_name(dev_priv->pipe_crc[i].source));
3801
3802         return 0;
3803 }
3804
3805 static int display_crc_ctl_open(struct inode *inode, struct file *file)
3806 {
3807         return single_open(file, display_crc_ctl_show, inode->i_private);
3808 }
3809
3810 static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
3811                                  uint32_t *val)
3812 {
3813         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
3814                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3815
3816         switch (*source) {
3817         case INTEL_PIPE_CRC_SOURCE_PIPE:
3818                 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX;
3819                 break;
3820         case INTEL_PIPE_CRC_SOURCE_NONE:
3821                 *val = 0;
3822                 break;
3823         default:
3824                 return -EINVAL;
3825         }
3826
3827         return 0;
3828 }
3829
3830 static int i9xx_pipe_crc_auto_source(struct drm_i915_private *dev_priv,
3831                                      enum pipe pipe,
3832                                      enum intel_pipe_crc_source *source)
3833 {
3834         struct drm_device *dev = &dev_priv->drm;
3835         struct intel_encoder *encoder;
3836         struct intel_crtc *crtc;
3837         struct intel_digital_port *dig_port;
3838         int ret = 0;
3839
3840         *source = INTEL_PIPE_CRC_SOURCE_PIPE;
3841
3842         drm_modeset_lock_all(dev);
3843         for_each_intel_encoder(dev, encoder) {
3844                 if (!encoder->base.crtc)
3845                         continue;
3846
3847                 crtc = to_intel_crtc(encoder->base.crtc);
3848
3849                 if (crtc->pipe != pipe)
3850                         continue;
3851
3852                 switch (encoder->type) {
3853                 case INTEL_OUTPUT_TVOUT:
3854                         *source = INTEL_PIPE_CRC_SOURCE_TV;
3855                         break;
3856                 case INTEL_OUTPUT_DP:
3857                 case INTEL_OUTPUT_EDP:
3858                         dig_port = enc_to_dig_port(&encoder->base);
3859                         switch (dig_port->port) {
3860                         case PORT_B:
3861                                 *source = INTEL_PIPE_CRC_SOURCE_DP_B;
3862                                 break;
3863                         case PORT_C:
3864                                 *source = INTEL_PIPE_CRC_SOURCE_DP_C;
3865                                 break;
3866                         case PORT_D:
3867                                 *source = INTEL_PIPE_CRC_SOURCE_DP_D;
3868                                 break;
3869                         default:
3870                                 WARN(1, "nonexisting DP port %c\n",
3871                                      port_name(dig_port->port));
3872                                 break;
3873                         }
3874                         break;
3875                 default:
3876                         break;
3877                 }
3878         }
3879         drm_modeset_unlock_all(dev);
3880
3881         return ret;
3882 }
3883
3884 static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
3885                                 enum pipe pipe,
3886                                 enum intel_pipe_crc_source *source,
3887                                 uint32_t *val)
3888 {
3889         bool need_stable_symbols = false;
3890
3891         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3892                 int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
3893                 if (ret)
3894                         return ret;
3895         }
3896
3897         switch (*source) {
3898         case INTEL_PIPE_CRC_SOURCE_PIPE:
3899                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV;
3900                 break;
3901         case INTEL_PIPE_CRC_SOURCE_DP_B:
3902                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV;
3903                 need_stable_symbols = true;
3904                 break;
3905         case INTEL_PIPE_CRC_SOURCE_DP_C:
3906                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV;
3907                 need_stable_symbols = true;
3908                 break;
3909         case INTEL_PIPE_CRC_SOURCE_DP_D:
3910                 if (!IS_CHERRYVIEW(dev_priv))
3911                         return -EINVAL;
3912                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV;
3913                 need_stable_symbols = true;
3914                 break;
3915         case INTEL_PIPE_CRC_SOURCE_NONE:
3916                 *val = 0;
3917                 break;
3918         default:
3919                 return -EINVAL;
3920         }
3921
3922         /*
3923          * When the pipe CRC tap point is after the transcoders we need
3924          * to tweak symbol-level features to produce a deterministic series of
3925          * symbols for a given frame. We need to reset those features only once
3926          * a frame (instead of every nth symbol):
3927          *   - DC-balance: used to ensure a better clock recovery from the data
3928          *     link (SDVO)
3929          *   - DisplayPort scrambling: used for EMI reduction
3930          */
3931         if (need_stable_symbols) {
3932                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
3933
3934                 tmp |= DC_BALANCE_RESET_VLV;
3935                 switch (pipe) {
3936                 case PIPE_A:
3937                         tmp |= PIPE_A_SCRAMBLE_RESET;
3938                         break;
3939                 case PIPE_B:
3940                         tmp |= PIPE_B_SCRAMBLE_RESET;
3941                         break;
3942                 case PIPE_C:
3943                         tmp |= PIPE_C_SCRAMBLE_RESET;
3944                         break;
3945                 default:
3946                         return -EINVAL;
3947                 }
3948                 I915_WRITE(PORT_DFT2_G4X, tmp);
3949         }
3950
3951         return 0;
3952 }
3953
3954 static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
3955                                  enum pipe pipe,
3956                                  enum intel_pipe_crc_source *source,
3957                                  uint32_t *val)
3958 {
3959         bool need_stable_symbols = false;
3960
3961         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) {
3962                 int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source);
3963                 if (ret)
3964                         return ret;
3965         }
3966
3967         switch (*source) {
3968         case INTEL_PIPE_CRC_SOURCE_PIPE:
3969                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX;
3970                 break;
3971         case INTEL_PIPE_CRC_SOURCE_TV:
3972                 if (!SUPPORTS_TV(dev_priv))
3973                         return -EINVAL;
3974                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE;
3975                 break;
3976         case INTEL_PIPE_CRC_SOURCE_DP_B:
3977                 if (!IS_G4X(dev_priv))
3978                         return -EINVAL;
3979                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X;
3980                 need_stable_symbols = true;
3981                 break;
3982         case INTEL_PIPE_CRC_SOURCE_DP_C:
3983                 if (!IS_G4X(dev_priv))
3984                         return -EINVAL;
3985                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X;
3986                 need_stable_symbols = true;
3987                 break;
3988         case INTEL_PIPE_CRC_SOURCE_DP_D:
3989                 if (!IS_G4X(dev_priv))
3990                         return -EINVAL;
3991                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X;
3992                 need_stable_symbols = true;
3993                 break;
3994         case INTEL_PIPE_CRC_SOURCE_NONE:
3995                 *val = 0;
3996                 break;
3997         default:
3998                 return -EINVAL;
3999         }
4000
4001         /*
4002          * When the pipe CRC tap point is after the transcoders we need
4003          * to tweak symbol-level features to produce a deterministic series of
4004          * symbols for a given frame. We need to reset those features only once
4005          * a frame (instead of every nth symbol):
4006          *   - DC-balance: used to ensure a better clock recovery from the data
4007          *     link (SDVO)
4008          *   - DisplayPort scrambling: used for EMI reduction
4009          */
4010         if (need_stable_symbols) {
4011                 uint32_t tmp = I915_READ(PORT_DFT2_G4X);
4012
4013                 WARN_ON(!IS_G4X(dev_priv));
4014
4015                 I915_WRITE(PORT_DFT_I9XX,
4016                            I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET);
4017
4018                 if (pipe == PIPE_A)
4019                         tmp |= PIPE_A_SCRAMBLE_RESET;
4020                 else
4021                         tmp |= PIPE_B_SCRAMBLE_RESET;
4022
4023                 I915_WRITE(PORT_DFT2_G4X, tmp);
4024         }
4025
4026         return 0;
4027 }
4028
4029 static void vlv_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
4030                                          enum pipe pipe)
4031 {
4032         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
4033
4034         switch (pipe) {
4035         case PIPE_A:
4036                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
4037                 break;
4038         case PIPE_B:
4039                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
4040                 break;
4041         case PIPE_C:
4042                 tmp &= ~PIPE_C_SCRAMBLE_RESET;
4043                 break;
4044         default:
4045                 return;
4046         }
4047         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK))
4048                 tmp &= ~DC_BALANCE_RESET_VLV;
4049         I915_WRITE(PORT_DFT2_G4X, tmp);
4050
4051 }
4052
4053 static void g4x_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv,
4054                                          enum pipe pipe)
4055 {
4056         uint32_t tmp = I915_READ(PORT_DFT2_G4X);
4057
4058         if (pipe == PIPE_A)
4059                 tmp &= ~PIPE_A_SCRAMBLE_RESET;
4060         else
4061                 tmp &= ~PIPE_B_SCRAMBLE_RESET;
4062         I915_WRITE(PORT_DFT2_G4X, tmp);
4063
4064         if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) {
4065                 I915_WRITE(PORT_DFT_I9XX,
4066                            I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET);
4067         }
4068 }
4069
4070 static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source,
4071                                 uint32_t *val)
4072 {
4073         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
4074                 *source = INTEL_PIPE_CRC_SOURCE_PIPE;
4075
4076         switch (*source) {
4077         case INTEL_PIPE_CRC_SOURCE_PLANE1:
4078                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK;
4079                 break;
4080         case INTEL_PIPE_CRC_SOURCE_PLANE2:
4081                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK;
4082                 break;
4083         case INTEL_PIPE_CRC_SOURCE_PIPE:
4084                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK;
4085                 break;
4086         case INTEL_PIPE_CRC_SOURCE_NONE:
4087                 *val = 0;
4088                 break;
4089         default:
4090                 return -EINVAL;
4091         }
4092
4093         return 0;
4094 }
4095
4096 static void hsw_trans_edp_pipe_A_crc_wa(struct drm_i915_private *dev_priv,
4097                                         bool enable)
4098 {
4099         struct drm_device *dev = &dev_priv->drm;
4100         struct intel_crtc *crtc =
4101                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_A]);
4102         struct intel_crtc_state *pipe_config;
4103         struct drm_atomic_state *state;
4104         int ret = 0;
4105
4106         drm_modeset_lock_all(dev);
4107         state = drm_atomic_state_alloc(dev);
4108         if (!state) {
4109                 ret = -ENOMEM;
4110                 goto out;
4111         }
4112
4113         state->acquire_ctx = drm_modeset_legacy_acquire_ctx(&crtc->base);
4114         pipe_config = intel_atomic_get_crtc_state(state, crtc);
4115         if (IS_ERR(pipe_config)) {
4116                 ret = PTR_ERR(pipe_config);
4117                 goto out;
4118         }
4119
4120         pipe_config->pch_pfit.force_thru = enable;
4121         if (pipe_config->cpu_transcoder == TRANSCODER_EDP &&
4122             pipe_config->pch_pfit.enabled != enable)
4123                 pipe_config->base.connectors_changed = true;
4124
4125         ret = drm_atomic_commit(state);
4126 out:
4127         WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret);
4128         drm_modeset_unlock_all(dev);
4129         drm_atomic_state_put(state);
4130 }
4131
4132 static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
4133                                 enum pipe pipe,
4134                                 enum intel_pipe_crc_source *source,
4135                                 uint32_t *val)
4136 {
4137         if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
4138                 *source = INTEL_PIPE_CRC_SOURCE_PF;
4139
4140         switch (*source) {
4141         case INTEL_PIPE_CRC_SOURCE_PLANE1:
4142                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB;
4143                 break;
4144         case INTEL_PIPE_CRC_SOURCE_PLANE2:
4145                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
4146                 break;
4147         case INTEL_PIPE_CRC_SOURCE_PF:
4148                 if (IS_HASWELL(dev_priv) && pipe == PIPE_A)
4149                         hsw_trans_edp_pipe_A_crc_wa(dev_priv, true);
4150
4151                 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB;
4152                 break;
4153         case INTEL_PIPE_CRC_SOURCE_NONE:
4154                 *val = 0;
4155                 break;
4156         default:
4157                 return -EINVAL;
4158         }
4159
4160         return 0;
4161 }
4162
4163 static int pipe_crc_set_source(struct drm_i915_private *dev_priv,
4164                                enum pipe pipe,
4165                                enum intel_pipe_crc_source source)
4166 {
4167         struct drm_device *dev = &dev_priv->drm;
4168         struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
4169         struct intel_crtc *crtc =
4170                         to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
4171         enum intel_display_power_domain power_domain;
4172         u32 val = 0; /* shut up gcc */
4173         int ret;
4174
4175         if (pipe_crc->source == source)
4176                 return 0;
4177
4178         /* forbid changing the source without going back to 'none' */
4179         if (pipe_crc->source && source)
4180                 return -EINVAL;
4181
4182         power_domain = POWER_DOMAIN_PIPE(pipe);
4183         if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) {
4184                 DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n");
4185                 return -EIO;
4186         }
4187
4188         if (IS_GEN2(dev_priv))
4189                 ret = i8xx_pipe_crc_ctl_reg(&source, &val);
4190         else if (INTEL_GEN(dev_priv) < 5)
4191                 ret = i9xx_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val);
4192         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4193                 ret = vlv_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val);
4194         else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv))
4195                 ret = ilk_pipe_crc_ctl_reg(&source, &val);
4196         else
4197                 ret = ivb_pipe_crc_ctl_reg(dev_priv, pipe, &source, &val);
4198
4199         if (ret != 0)
4200                 goto out;
4201
4202         /* none -> real source transition */
4203         if (source) {
4204                 struct intel_pipe_crc_entry *entries;
4205
4206                 DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n",
4207                                  pipe_name(pipe), pipe_crc_source_name(source));
4208
4209                 entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR,
4210                                   sizeof(pipe_crc->entries[0]),
4211                                   GFP_KERNEL);
4212                 if (!entries) {
4213                         ret = -ENOMEM;
4214                         goto out;
4215                 }
4216
4217                 /*
4218                  * When IPS gets enabled, the pipe CRC changes. Since IPS gets
4219                  * enabled and disabled dynamically based on package C states,
4220                  * user space can't make reliable use of the CRCs, so let's just
4221                  * completely disable it.
4222                  */
4223                 hsw_disable_ips(crtc);
4224
4225                 spin_lock_irq(&pipe_crc->lock);
4226                 kfree(pipe_crc->entries);
4227                 pipe_crc->entries = entries;
4228                 pipe_crc->head = 0;
4229                 pipe_crc->tail = 0;
4230                 spin_unlock_irq(&pipe_crc->lock);
4231         }
4232
4233         pipe_crc->source = source;
4234
4235         I915_WRITE(PIPE_CRC_CTL(pipe), val);
4236         POSTING_READ(PIPE_CRC_CTL(pipe));
4237
4238         /* real source -> none transition */
4239         if (source == INTEL_PIPE_CRC_SOURCE_NONE) {
4240                 struct intel_pipe_crc_entry *entries;
4241                 struct intel_crtc *crtc =
4242                         to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
4243
4244                 DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n",
4245                                  pipe_name(pipe));
4246
4247                 drm_modeset_lock(&crtc->base.mutex, NULL);
4248                 if (crtc->base.state->active)
4249                         intel_wait_for_vblank(dev, pipe);
4250                 drm_modeset_unlock(&crtc->base.mutex);
4251
4252                 spin_lock_irq(&pipe_crc->lock);
4253                 entries = pipe_crc->entries;
4254                 pipe_crc->entries = NULL;
4255                 pipe_crc->head = 0;
4256                 pipe_crc->tail = 0;
4257                 spin_unlock_irq(&pipe_crc->lock);
4258
4259                 kfree(entries);
4260
4261                 if (IS_G4X(dev_priv))
4262                         g4x_undo_pipe_scramble_reset(dev_priv, pipe);
4263                 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4264                         vlv_undo_pipe_scramble_reset(dev_priv, pipe);
4265                 else if (IS_HASWELL(dev_priv) && pipe == PIPE_A)
4266                         hsw_trans_edp_pipe_A_crc_wa(dev_priv, false);
4267
4268                 hsw_enable_ips(crtc);
4269         }
4270
4271         ret = 0;
4272
4273 out:
4274         intel_display_power_put(dev_priv, power_domain);
4275
4276         return ret;
4277 }
4278
4279 /*
4280  * Parse pipe CRC command strings:
4281  *   command: wsp* object wsp+ name wsp+ source wsp*
4282  *   object: 'pipe'
4283  *   name: (A | B | C)
4284  *   source: (none | plane1 | plane2 | pf)
4285  *   wsp: (#0x20 | #0x9 | #0xA)+
4286  *
4287  * eg.:
4288  *  "pipe A plane1"  ->  Start CRC computations on plane1 of pipe A
4289  *  "pipe A none"    ->  Stop CRC
4290  */
4291 static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words)
4292 {
4293         int n_words = 0;
4294
4295         while (*buf) {
4296                 char *end;
4297
4298                 /* skip leading white space */
4299                 buf = skip_spaces(buf);
4300                 if (!*buf)
4301                         break;  /* end of buffer */
4302
4303                 /* find end of word */
4304                 for (end = buf; *end && !isspace(*end); end++)
4305                         ;
4306
4307                 if (n_words == max_words) {
4308                         DRM_DEBUG_DRIVER("too many words, allowed <= %d\n",
4309                                          max_words);
4310                         return -EINVAL; /* ran out of words[] before bytes */
4311                 }
4312
4313                 if (*end)
4314                         *end++ = '\0';
4315                 words[n_words++] = buf;
4316                 buf = end;
4317         }
4318
4319         return n_words;
4320 }
4321
4322 enum intel_pipe_crc_object {
4323         PIPE_CRC_OBJECT_PIPE,
4324 };
4325
4326 static const char * const pipe_crc_objects[] = {
4327         "pipe",
4328 };
4329
4330 static int
4331 display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
4332 {
4333         int i;
4334
4335         for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
4336                 if (!strcmp(buf, pipe_crc_objects[i])) {
4337                         *o = i;
4338                         return 0;
4339                     }
4340
4341         return -EINVAL;
4342 }
4343
4344 static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe)
4345 {
4346         const char name = buf[0];
4347
4348         if (name < 'A' || name >= pipe_name(I915_MAX_PIPES))
4349                 return -EINVAL;
4350
4351         *pipe = name - 'A';
4352
4353         return 0;
4354 }
4355
4356 static int
4357 display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
4358 {
4359         int i;
4360
4361         for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
4362                 if (!strcmp(buf, pipe_crc_sources[i])) {
4363                         *s = i;
4364                         return 0;
4365                     }
4366
4367         return -EINVAL;
4368 }
4369
4370 static int display_crc_ctl_parse(struct drm_i915_private *dev_priv,
4371                                  char *buf, size_t len)
4372 {
4373 #define N_WORDS 3
4374         int n_words;
4375         char *words[N_WORDS];
4376         enum pipe pipe;
4377         enum intel_pipe_crc_object object;
4378         enum intel_pipe_crc_source source;
4379
4380         n_words = display_crc_ctl_tokenize(buf, words, N_WORDS);
4381         if (n_words != N_WORDS) {
4382                 DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n",
4383                                  N_WORDS);
4384                 return -EINVAL;
4385         }
4386
4387         if (display_crc_ctl_parse_object(words[0], &object) < 0) {
4388                 DRM_DEBUG_DRIVER("unknown object %s\n", words[0]);
4389                 return -EINVAL;
4390         }
4391
4392         if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) {
4393                 DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]);
4394                 return -EINVAL;
4395         }
4396
4397         if (display_crc_ctl_parse_source(words[2], &source) < 0) {
4398                 DRM_DEBUG_DRIVER("unknown source %s\n", words[2]);
4399                 return -EINVAL;
4400         }
4401
4402         return pipe_crc_set_source(dev_priv, pipe, source);
4403 }
4404
4405 static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf,
4406                                      size_t len, loff_t *offp)
4407 {
4408         struct seq_file *m = file->private_data;
4409         struct drm_i915_private *dev_priv = m->private;
4410         char *tmpbuf;
4411         int ret;
4412
4413         if (len == 0)
4414                 return 0;
4415
4416         if (len > PAGE_SIZE - 1) {
4417                 DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n",
4418                                  PAGE_SIZE);
4419                 return -E2BIG;
4420         }
4421
4422         tmpbuf = kmalloc(len + 1, GFP_KERNEL);
4423         if (!tmpbuf)
4424                 return -ENOMEM;
4425
4426         if (copy_from_user(tmpbuf, ubuf, len)) {
4427                 ret = -EFAULT;
4428                 goto out;
4429         }
4430         tmpbuf[len] = '\0';
4431
4432         ret = display_crc_ctl_parse(dev_priv, tmpbuf, len);
4433
4434 out:
4435         kfree(tmpbuf);
4436         if (ret < 0)
4437                 return ret;
4438
4439         *offp += len;
4440         return len;
4441 }
4442
4443 static const struct file_operations i915_display_crc_ctl_fops = {
4444         .owner = THIS_MODULE,
4445         .open = display_crc_ctl_open,
4446         .read = seq_read,
4447         .llseek = seq_lseek,
4448         .release = single_release,
4449         .write = display_crc_ctl_write
4450 };
4451
4452 static ssize_t i915_displayport_test_active_write(struct file *file,
4453                                                   const char __user *ubuf,
4454                                                   size_t len, loff_t *offp)
4455 {
4456         char *input_buffer;
4457         int status = 0;
4458         struct drm_device *dev;
4459         struct drm_connector *connector;
4460         struct list_head *connector_list;
4461         struct intel_dp *intel_dp;
4462         int val = 0;
4463
4464         dev = ((struct seq_file *)file->private_data)->private;
4465
4466         connector_list = &dev->mode_config.connector_list;
4467
4468         if (len == 0)
4469                 return 0;
4470
4471         input_buffer = kmalloc(len + 1, GFP_KERNEL);
4472         if (!input_buffer)
4473                 return -ENOMEM;
4474
4475         if (copy_from_user(input_buffer, ubuf, len)) {
4476                 status = -EFAULT;
4477                 goto out;
4478         }
4479
4480         input_buffer[len] = '\0';
4481         DRM_DEBUG_DRIVER("Copied %d bytes from user\n", (unsigned int)len);
4482
4483         list_for_each_entry(connector, connector_list, head) {
4484                 if (connector->connector_type !=
4485                     DRM_MODE_CONNECTOR_DisplayPort)
4486                         continue;
4487
4488                 if (connector->status == connector_status_connected &&
4489                     connector->encoder != NULL) {
4490                         intel_dp = enc_to_intel_dp(connector->encoder);
4491                         status = kstrtoint(input_buffer, 10, &val);
4492                         if (status < 0)
4493                                 goto out;
4494                         DRM_DEBUG_DRIVER("Got %d for test active\n", val);
4495                         /* To prevent erroneous activation of the compliance
4496                          * testing code, only accept an actual value of 1 here
4497                          */
4498                         if (val == 1)
4499                                 intel_dp->compliance_test_active = 1;
4500                         else
4501                                 intel_dp->compliance_test_active = 0;
4502                 }
4503         }
4504 out:
4505         kfree(input_buffer);
4506         if (status < 0)
4507                 return status;
4508
4509         *offp += len;
4510         return len;
4511 }
4512
4513 static int i915_displayport_test_active_show(struct seq_file *m, void *data)
4514 {
4515         struct drm_device *dev = m->private;
4516         struct drm_connector *connector;
4517         struct list_head *connector_list = &dev->mode_config.connector_list;
4518         struct intel_dp *intel_dp;
4519
4520         list_for_each_entry(connector, connector_list, head) {
4521                 if (connector->connector_type !=
4522                     DRM_MODE_CONNECTOR_DisplayPort)
4523                         continue;
4524
4525                 if (connector->status == connector_status_connected &&
4526                     connector->encoder != NULL) {
4527                         intel_dp = enc_to_intel_dp(connector->encoder);
4528                         if (intel_dp->compliance_test_active)
4529                                 seq_puts(m, "1");
4530                         else
4531                                 seq_puts(m, "0");
4532                 } else
4533                         seq_puts(m, "0");
4534         }
4535
4536         return 0;
4537 }
4538
4539 static int i915_displayport_test_active_open(struct inode *inode,
4540                                              struct file *file)
4541 {
4542         struct drm_i915_private *dev_priv = inode->i_private;
4543
4544         return single_open(file, i915_displayport_test_active_show,
4545                            &dev_priv->drm);
4546 }
4547
4548 static const struct file_operations i915_displayport_test_active_fops = {
4549         .owner = THIS_MODULE,
4550         .open = i915_displayport_test_active_open,
4551         .read = seq_read,
4552         .llseek = seq_lseek,
4553         .release = single_release,
4554         .write = i915_displayport_test_active_write
4555 };
4556
4557 static int i915_displayport_test_data_show(struct seq_file *m, void *data)
4558 {
4559         struct drm_device *dev = m->private;
4560         struct drm_connector *connector;
4561         struct list_head *connector_list = &dev->mode_config.connector_list;
4562         struct intel_dp *intel_dp;
4563
4564         list_for_each_entry(connector, connector_list, head) {
4565                 if (connector->connector_type !=
4566                     DRM_MODE_CONNECTOR_DisplayPort)
4567                         continue;
4568
4569                 if (connector->status == connector_status_connected &&
4570                     connector->encoder != NULL) {
4571                         intel_dp = enc_to_intel_dp(connector->encoder);
4572                         seq_printf(m, "%lx", intel_dp->compliance_test_data);
4573                 } else
4574                         seq_puts(m, "0");
4575         }
4576
4577         return 0;
4578 }
4579 static int i915_displayport_test_data_open(struct inode *inode,
4580                                            struct file *file)
4581 {
4582         struct drm_i915_private *dev_priv = inode->i_private;
4583
4584         return single_open(file, i915_displayport_test_data_show,
4585                            &dev_priv->drm);
4586 }
4587
4588 static const struct file_operations i915_displayport_test_data_fops = {
4589         .owner = THIS_MODULE,
4590         .open = i915_displayport_test_data_open,
4591         .read = seq_read,
4592         .llseek = seq_lseek,
4593         .release = single_release
4594 };
4595
4596 static int i915_displayport_test_type_show(struct seq_file *m, void *data)
4597 {
4598         struct drm_device *dev = m->private;
4599         struct drm_connector *connector;
4600         struct list_head *connector_list = &dev->mode_config.connector_list;
4601         struct intel_dp *intel_dp;
4602
4603         list_for_each_entry(connector, connector_list, head) {
4604                 if (connector->connector_type !=
4605                     DRM_MODE_CONNECTOR_DisplayPort)
4606                         continue;
4607
4608                 if (connector->status == connector_status_connected &&
4609                     connector->encoder != NULL) {
4610                         intel_dp = enc_to_intel_dp(connector->encoder);
4611                         seq_printf(m, "%02lx", intel_dp->compliance_test_type);
4612                 } else
4613                         seq_puts(m, "0");
4614         }
4615
4616         return 0;
4617 }
4618
4619 static int i915_displayport_test_type_open(struct inode *inode,
4620                                        struct file *file)
4621 {
4622         struct drm_i915_private *dev_priv = inode->i_private;
4623
4624         return single_open(file, i915_displayport_test_type_show,
4625                            &dev_priv->drm);
4626 }
4627
4628 static const struct file_operations i915_displayport_test_type_fops = {
4629         .owner = THIS_MODULE,
4630         .open = i915_displayport_test_type_open,
4631         .read = seq_read,
4632         .llseek = seq_lseek,
4633         .release = single_release
4634 };
4635
4636 static void wm_latency_show(struct seq_file *m, const uint16_t wm[8])
4637 {
4638         struct drm_i915_private *dev_priv = m->private;
4639         struct drm_device *dev = &dev_priv->drm;
4640         int level;
4641         int num_levels;
4642
4643         if (IS_CHERRYVIEW(dev_priv))
4644                 num_levels = 3;
4645         else if (IS_VALLEYVIEW(dev_priv))
4646                 num_levels = 1;
4647         else
4648                 num_levels = ilk_wm_max_level(dev_priv) + 1;
4649
4650         drm_modeset_lock_all(dev);
4651
4652         for (level = 0; level < num_levels; level++) {
4653                 unsigned int latency = wm[level];
4654
4655                 /*
4656                  * - WM1+ latency values in 0.5us units
4657                  * - latencies are in us on gen9/vlv/chv
4658                  */
4659                 if (INTEL_GEN(dev_priv) >= 9 || IS_VALLEYVIEW(dev_priv) ||
4660                     IS_CHERRYVIEW(dev_priv))
4661                         latency *= 10;
4662                 else if (level > 0)
4663                         latency *= 5;
4664
4665                 seq_printf(m, "WM%d %u (%u.%u usec)\n",
4666                            level, wm[level], latency / 10, latency % 10);
4667         }
4668
4669         drm_modeset_unlock_all(dev);
4670 }
4671
4672 static int pri_wm_latency_show(struct seq_file *m, void *data)
4673 {
4674         struct drm_i915_private *dev_priv = m->private;
4675         const uint16_t *latencies;
4676
4677         if (INTEL_GEN(dev_priv) >= 9)
4678                 latencies = dev_priv->wm.skl_latency;
4679         else
4680                 latencies = dev_priv->wm.pri_latency;
4681
4682         wm_latency_show(m, latencies);
4683
4684         return 0;
4685 }
4686
4687 static int spr_wm_latency_show(struct seq_file *m, void *data)
4688 {
4689         struct drm_i915_private *dev_priv = m->private;
4690         const uint16_t *latencies;
4691
4692         if (INTEL_GEN(dev_priv) >= 9)
4693                 latencies = dev_priv->wm.skl_latency;
4694         else
4695                 latencies = dev_priv->wm.spr_latency;
4696
4697         wm_latency_show(m, latencies);
4698
4699         return 0;
4700 }
4701
4702 static int cur_wm_latency_show(struct seq_file *m, void *data)
4703 {
4704         struct drm_i915_private *dev_priv = m->private;
4705         const uint16_t *latencies;
4706
4707         if (INTEL_GEN(dev_priv) >= 9)
4708                 latencies = dev_priv->wm.skl_latency;
4709         else
4710                 latencies = dev_priv->wm.cur_latency;
4711
4712         wm_latency_show(m, latencies);
4713
4714         return 0;
4715 }
4716
4717 static int pri_wm_latency_open(struct inode *inode, struct file *file)
4718 {
4719         struct drm_i915_private *dev_priv = inode->i_private;
4720
4721         if (INTEL_GEN(dev_priv) < 5)
4722                 return -ENODEV;
4723
4724         return single_open(file, pri_wm_latency_show, dev_priv);
4725 }
4726
4727 static int spr_wm_latency_open(struct inode *inode, struct file *file)
4728 {
4729         struct drm_i915_private *dev_priv = inode->i_private;
4730
4731         if (HAS_GMCH_DISPLAY(dev_priv))
4732                 return -ENODEV;
4733
4734         return single_open(file, spr_wm_latency_show, dev_priv);
4735 }
4736
4737 static int cur_wm_latency_open(struct inode *inode, struct file *file)
4738 {
4739         struct drm_i915_private *dev_priv = inode->i_private;
4740
4741         if (HAS_GMCH_DISPLAY(dev_priv))
4742                 return -ENODEV;
4743
4744         return single_open(file, cur_wm_latency_show, dev_priv);
4745 }
4746
4747 static ssize_t wm_latency_write(struct file *file, const char __user *ubuf,
4748                                 size_t len, loff_t *offp, uint16_t wm[8])
4749 {
4750         struct seq_file *m = file->private_data;
4751         struct drm_i915_private *dev_priv = m->private;
4752         struct drm_device *dev = &dev_priv->drm;
4753         uint16_t new[8] = { 0 };
4754         int num_levels;
4755         int level;
4756         int ret;
4757         char tmp[32];
4758
4759         if (IS_CHERRYVIEW(dev_priv))
4760                 num_levels = 3;
4761         else if (IS_VALLEYVIEW(dev_priv))
4762                 num_levels = 1;
4763         else
4764                 num_levels = ilk_wm_max_level(dev_priv) + 1;
4765
4766         if (len >= sizeof(tmp))
4767                 return -EINVAL;
4768
4769         if (copy_from_user(tmp, ubuf, len))
4770                 return -EFAULT;
4771
4772         tmp[len] = '\0';
4773
4774         ret = sscanf(tmp, "%hu %hu %hu %hu %hu %hu %hu %hu",
4775                      &new[0], &new[1], &new[2], &new[3],
4776                      &new[4], &new[5], &new[6], &new[7]);
4777         if (ret != num_levels)
4778                 return -EINVAL;
4779
4780         drm_modeset_lock_all(dev);
4781
4782         for (level = 0; level < num_levels; level++)
4783                 wm[level] = new[level];
4784
4785         drm_modeset_unlock_all(dev);
4786
4787         return len;
4788 }
4789
4790
4791 static ssize_t pri_wm_latency_write(struct file *file, const char __user *ubuf,
4792                                     size_t len, loff_t *offp)
4793 {
4794         struct seq_file *m = file->private_data;
4795         struct drm_i915_private *dev_priv = m->private;
4796         uint16_t *latencies;
4797
4798         if (INTEL_GEN(dev_priv) >= 9)
4799                 latencies = dev_priv->wm.skl_latency;
4800         else
4801                 latencies = dev_priv->wm.pri_latency;
4802
4803         return wm_latency_write(file, ubuf, len, offp, latencies);
4804 }
4805
4806 static ssize_t spr_wm_latency_write(struct file *file, const char __user *ubuf,
4807                                     size_t len, loff_t *offp)
4808 {
4809         struct seq_file *m = file->private_data;
4810         struct drm_i915_private *dev_priv = m->private;
4811         uint16_t *latencies;
4812
4813         if (INTEL_GEN(dev_priv) >= 9)
4814                 latencies = dev_priv->wm.skl_latency;
4815         else
4816                 latencies = dev_priv->wm.spr_latency;
4817
4818         return wm_latency_write(file, ubuf, len, offp, latencies);
4819 }
4820
4821 static ssize_t cur_wm_latency_write(struct file *file, const char __user *ubuf,
4822                                     size_t len, loff_t *offp)
4823 {
4824         struct seq_file *m = file->private_data;
4825         struct drm_i915_private *dev_priv = m->private;
4826         uint16_t *latencies;
4827
4828         if (INTEL_GEN(dev_priv) >= 9)
4829                 latencies = dev_priv->wm.skl_latency;
4830         else
4831                 latencies = dev_priv->wm.cur_latency;
4832
4833         return wm_latency_write(file, ubuf, len, offp, latencies);
4834 }
4835
4836 static const struct file_operations i915_pri_wm_latency_fops = {
4837         .owner = THIS_MODULE,
4838         .open = pri_wm_latency_open,
4839         .read = seq_read,
4840         .llseek = seq_lseek,
4841         .release = single_release,
4842         .write = pri_wm_latency_write
4843 };
4844
4845 static const struct file_operations i915_spr_wm_latency_fops = {
4846         .owner = THIS_MODULE,
4847         .open = spr_wm_latency_open,
4848         .read = seq_read,
4849         .llseek = seq_lseek,
4850         .release = single_release,
4851         .write = spr_wm_latency_write
4852 };
4853
4854 static const struct file_operations i915_cur_wm_latency_fops = {
4855         .owner = THIS_MODULE,
4856         .open = cur_wm_latency_open,
4857         .read = seq_read,
4858         .llseek = seq_lseek,
4859         .release = single_release,
4860         .write = cur_wm_latency_write
4861 };
4862
4863 static int
4864 i915_wedged_get(void *data, u64 *val)
4865 {
4866         struct drm_i915_private *dev_priv = data;
4867
4868         *val = i915_terminally_wedged(&dev_priv->gpu_error);
4869
4870         return 0;
4871 }
4872
4873 static int
4874 i915_wedged_set(void *data, u64 val)
4875 {
4876         struct drm_i915_private *dev_priv = data;
4877
4878         /*
4879          * There is no safeguard against this debugfs entry colliding
4880          * with the hangcheck calling same i915_handle_error() in
4881          * parallel, causing an explosion. For now we assume that the
4882          * test harness is responsible enough not to inject gpu hangs
4883          * while it is writing to 'i915_wedged'
4884          */
4885
4886         if (i915_reset_in_progress(&dev_priv->gpu_error))
4887                 return -EAGAIN;
4888
4889         i915_handle_error(dev_priv, val,
4890                           "Manually setting wedged to %llu", val);
4891
4892         return 0;
4893 }
4894
4895 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
4896                         i915_wedged_get, i915_wedged_set,
4897                         "%llu\n");
4898
4899 static int
4900 i915_ring_missed_irq_get(void *data, u64 *val)
4901 {
4902         struct drm_i915_private *dev_priv = data;
4903
4904         *val = dev_priv->gpu_error.missed_irq_rings;
4905         return 0;
4906 }
4907
4908 static int
4909 i915_ring_missed_irq_set(void *data, u64 val)
4910 {
4911         struct drm_i915_private *dev_priv = data;
4912         struct drm_device *dev = &dev_priv->drm;
4913         int ret;
4914
4915         /* Lock against concurrent debugfs callers */
4916         ret = mutex_lock_interruptible(&dev->struct_mutex);
4917         if (ret)
4918                 return ret;
4919         dev_priv->gpu_error.missed_irq_rings = val;
4920         mutex_unlock(&dev->struct_mutex);
4921
4922         return 0;
4923 }
4924
4925 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_missed_irq_fops,
4926                         i915_ring_missed_irq_get, i915_ring_missed_irq_set,
4927                         "0x%08llx\n");
4928
4929 static int
4930 i915_ring_test_irq_get(void *data, u64 *val)
4931 {
4932         struct drm_i915_private *dev_priv = data;
4933
4934         *val = dev_priv->gpu_error.test_irq_rings;
4935
4936         return 0;
4937 }
4938
4939 static int
4940 i915_ring_test_irq_set(void *data, u64 val)
4941 {
4942         struct drm_i915_private *dev_priv = data;
4943
4944         val &= INTEL_INFO(dev_priv)->ring_mask;
4945         DRM_DEBUG_DRIVER("Masking interrupts on rings 0x%08llx\n", val);
4946         dev_priv->gpu_error.test_irq_rings = val;
4947
4948         return 0;
4949 }
4950
4951 DEFINE_SIMPLE_ATTRIBUTE(i915_ring_test_irq_fops,
4952                         i915_ring_test_irq_get, i915_ring_test_irq_set,
4953                         "0x%08llx\n");
4954
4955 #define DROP_UNBOUND 0x1
4956 #define DROP_BOUND 0x2
4957 #define DROP_RETIRE 0x4
4958 #define DROP_ACTIVE 0x8
4959 #define DROP_ALL (DROP_UNBOUND | \
4960                   DROP_BOUND | \
4961                   DROP_RETIRE | \
4962                   DROP_ACTIVE)
4963 static int
4964 i915_drop_caches_get(void *data, u64 *val)
4965 {
4966         *val = DROP_ALL;
4967
4968         return 0;
4969 }
4970
4971 static int
4972 i915_drop_caches_set(void *data, u64 val)
4973 {
4974         struct drm_i915_private *dev_priv = data;
4975         struct drm_device *dev = &dev_priv->drm;
4976         int ret;
4977
4978         DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
4979
4980         /* No need to check and wait for gpu resets, only libdrm auto-restarts
4981          * on ioctls on -EAGAIN. */
4982         ret = mutex_lock_interruptible(&dev->struct_mutex);
4983         if (ret)
4984                 return ret;
4985
4986         if (val & DROP_ACTIVE) {
4987                 ret = i915_gem_wait_for_idle(dev_priv,
4988                                              I915_WAIT_INTERRUPTIBLE |
4989                                              I915_WAIT_LOCKED);
4990                 if (ret)
4991                         goto unlock;
4992         }
4993
4994         if (val & (DROP_RETIRE | DROP_ACTIVE))
4995                 i915_gem_retire_requests(dev_priv);
4996
4997         if (val & DROP_BOUND)
4998                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_BOUND);
4999
5000         if (val & DROP_UNBOUND)
5001                 i915_gem_shrink(dev_priv, LONG_MAX, I915_SHRINK_UNBOUND);
5002
5003 unlock:
5004         mutex_unlock(&dev->struct_mutex);
5005
5006         return ret;
5007 }
5008
5009 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
5010                         i915_drop_caches_get, i915_drop_caches_set,
5011                         "0x%08llx\n");
5012
5013 static int
5014 i915_max_freq_get(void *data, u64 *val)
5015 {
5016         struct drm_i915_private *dev_priv = data;
5017
5018         if (INTEL_GEN(dev_priv) < 6)
5019                 return -ENODEV;
5020
5021         *val = intel_gpu_freq(dev_priv, dev_priv->rps.max_freq_softlimit);
5022         return 0;
5023 }
5024
5025 static int
5026 i915_max_freq_set(void *data, u64 val)
5027 {
5028         struct drm_i915_private *dev_priv = data;
5029         u32 hw_max, hw_min;
5030         int ret;
5031
5032         if (INTEL_GEN(dev_priv) < 6)
5033                 return -ENODEV;
5034
5035         DRM_DEBUG_DRIVER("Manually setting max freq to %llu\n", val);
5036
5037         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
5038         if (ret)
5039                 return ret;
5040
5041         /*
5042          * Turbo will still be enabled, but won't go above the set value.
5043          */
5044         val = intel_freq_opcode(dev_priv, val);
5045
5046         hw_max = dev_priv->rps.max_freq;
5047         hw_min = dev_priv->rps.min_freq;
5048
5049         if (val < hw_min || val > hw_max || val < dev_priv->rps.min_freq_softlimit) {
5050                 mutex_unlock(&dev_priv->rps.hw_lock);
5051                 return -EINVAL;
5052         }
5053
5054         dev_priv->rps.max_freq_softlimit = val;
5055
5056         intel_set_rps(dev_priv, val);
5057
5058         mutex_unlock(&dev_priv->rps.hw_lock);
5059
5060         return 0;
5061 }
5062
5063 DEFINE_SIMPLE_ATTRIBUTE(i915_max_freq_fops,
5064                         i915_max_freq_get, i915_max_freq_set,
5065                         "%llu\n");
5066
5067 static int
5068 i915_min_freq_get(void *data, u64 *val)
5069 {
5070         struct drm_i915_private *dev_priv = data;
5071
5072         if (INTEL_GEN(dev_priv) < 6)
5073                 return -ENODEV;
5074
5075         *val = intel_gpu_freq(dev_priv, dev_priv->rps.min_freq_softlimit);
5076         return 0;
5077 }
5078
5079 static int
5080 i915_min_freq_set(void *data, u64 val)
5081 {
5082         struct drm_i915_private *dev_priv = data;
5083         u32 hw_max, hw_min;
5084         int ret;
5085
5086         if (INTEL_GEN(dev_priv) < 6)
5087                 return -ENODEV;
5088
5089         DRM_DEBUG_DRIVER("Manually setting min freq to %llu\n", val);
5090
5091         ret = mutex_lock_interruptible(&dev_priv->rps.hw_lock);
5092         if (ret)
5093                 return ret;
5094
5095         /*
5096          * Turbo will still be enabled, but won't go below the set value.
5097          */
5098         val = intel_freq_opcode(dev_priv, val);
5099
5100         hw_max = dev_priv->rps.max_freq;
5101         hw_min = dev_priv->rps.min_freq;
5102
5103         if (val < hw_min ||
5104             val > hw_max || val > dev_priv->rps.max_freq_softlimit) {
5105                 mutex_unlock(&dev_priv->rps.hw_lock);
5106                 return -EINVAL;
5107         }
5108
5109         dev_priv->rps.min_freq_softlimit = val;
5110
5111         intel_set_rps(dev_priv, val);
5112
5113         mutex_unlock(&dev_priv->rps.hw_lock);
5114
5115         return 0;
5116 }
5117
5118 DEFINE_SIMPLE_ATTRIBUTE(i915_min_freq_fops,
5119                         i915_min_freq_get, i915_min_freq_set,
5120                         "%llu\n");
5121
5122 static int
5123 i915_cache_sharing_get(void *data, u64 *val)
5124 {
5125         struct drm_i915_private *dev_priv = data;
5126         u32 snpcr;
5127
5128         if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
5129                 return -ENODEV;
5130
5131         intel_runtime_pm_get(dev_priv);
5132
5133         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5134
5135         intel_runtime_pm_put(dev_priv);
5136
5137         *val = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
5138
5139         return 0;
5140 }
5141
5142 static int
5143 i915_cache_sharing_set(void *data, u64 val)
5144 {
5145         struct drm_i915_private *dev_priv = data;
5146         u32 snpcr;
5147
5148         if (!(IS_GEN6(dev_priv) || IS_GEN7(dev_priv)))
5149                 return -ENODEV;
5150
5151         if (val > 3)
5152                 return -EINVAL;
5153
5154         intel_runtime_pm_get(dev_priv);
5155         DRM_DEBUG_DRIVER("Manually setting uncore sharing to %llu\n", val);
5156
5157         /* Update the cache sharing policy here as well */
5158         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5159         snpcr &= ~GEN6_MBC_SNPCR_MASK;
5160         snpcr |= (val << GEN6_MBC_SNPCR_SHIFT);
5161         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
5162
5163         intel_runtime_pm_put(dev_priv);
5164         return 0;
5165 }
5166
5167 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
5168                         i915_cache_sharing_get, i915_cache_sharing_set,
5169                         "%llu\n");
5170
5171 static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
5172                                           struct sseu_dev_info *sseu)
5173 {
5174         int ss_max = 2;
5175         int ss;
5176         u32 sig1[ss_max], sig2[ss_max];
5177
5178         sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
5179         sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
5180         sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
5181         sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
5182
5183         for (ss = 0; ss < ss_max; ss++) {
5184                 unsigned int eu_cnt;
5185
5186                 if (sig1[ss] & CHV_SS_PG_ENABLE)
5187                         /* skip disabled subslice */
5188                         continue;
5189
5190                 sseu->slice_mask = BIT(0);
5191                 sseu->subslice_mask |= BIT(ss);
5192                 eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
5193                          ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
5194                          ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
5195                          ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
5196                 sseu->eu_total += eu_cnt;
5197                 sseu->eu_per_subslice = max_t(unsigned int,
5198                                               sseu->eu_per_subslice, eu_cnt);
5199         }
5200 }
5201
5202 static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
5203                                     struct sseu_dev_info *sseu)
5204 {
5205         int s_max = 3, ss_max = 4;
5206         int s, ss;
5207         u32 s_reg[s_max], eu_reg[2*s_max], eu_mask[2];
5208
5209         /* BXT has a single slice and at most 3 subslices. */
5210         if (IS_BROXTON(dev_priv)) {
5211                 s_max = 1;
5212                 ss_max = 3;
5213         }
5214
5215         for (s = 0; s < s_max; s++) {
5216                 s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
5217                 eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
5218                 eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
5219         }
5220
5221         eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
5222                      GEN9_PGCTL_SSA_EU19_ACK |
5223                      GEN9_PGCTL_SSA_EU210_ACK |
5224                      GEN9_PGCTL_SSA_EU311_ACK;
5225         eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
5226                      GEN9_PGCTL_SSB_EU19_ACK |
5227                      GEN9_PGCTL_SSB_EU210_ACK |
5228                      GEN9_PGCTL_SSB_EU311_ACK;
5229
5230         for (s = 0; s < s_max; s++) {
5231                 if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
5232                         /* skip disabled slice */
5233                         continue;
5234
5235                 sseu->slice_mask |= BIT(s);
5236
5237                 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
5238                         sseu->subslice_mask =
5239                                 INTEL_INFO(dev_priv)->sseu.subslice_mask;
5240
5241                 for (ss = 0; ss < ss_max; ss++) {
5242                         unsigned int eu_cnt;
5243
5244                         if (IS_BROXTON(dev_priv)) {
5245                                 if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
5246                                         /* skip disabled subslice */
5247                                         continue;
5248
5249                                 sseu->subslice_mask |= BIT(ss);
5250                         }
5251
5252                         eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
5253                                                eu_mask[ss%2]);
5254                         sseu->eu_total += eu_cnt;
5255                         sseu->eu_per_subslice = max_t(unsigned int,
5256                                                       sseu->eu_per_subslice,
5257                                                       eu_cnt);
5258                 }
5259         }
5260 }
5261
5262 static void broadwell_sseu_device_status(struct drm_i915_private *dev_priv,
5263                                          struct sseu_dev_info *sseu)
5264 {
5265         u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
5266         int s;
5267
5268         sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK;
5269
5270         if (sseu->slice_mask) {
5271                 sseu->subslice_mask = INTEL_INFO(dev_priv)->sseu.subslice_mask;
5272                 sseu->eu_per_subslice =
5273                                 INTEL_INFO(dev_priv)->sseu.eu_per_subslice;
5274                 sseu->eu_total = sseu->eu_per_subslice *
5275                                  sseu_subslice_total(sseu);
5276
5277                 /* subtract fused off EU(s) from enabled slice(s) */
5278                 for (s = 0; s < fls(sseu->slice_mask); s++) {
5279                         u8 subslice_7eu =
5280                                 INTEL_INFO(dev_priv)->sseu.subslice_7eu[s];
5281
5282                         sseu->eu_total -= hweight8(subslice_7eu);
5283                 }
5284         }
5285 }
5286
5287 static void i915_print_sseu_info(struct seq_file *m, bool is_available_info,
5288                                  const struct sseu_dev_info *sseu)
5289 {
5290         struct drm_i915_private *dev_priv = node_to_i915(m->private);
5291         const char *type = is_available_info ? "Available" : "Enabled";
5292
5293         seq_printf(m, "  %s Slice Mask: %04x\n", type,
5294                    sseu->slice_mask);
5295         seq_printf(m, "  %s Slice Total: %u\n", type,
5296                    hweight8(sseu->slice_mask));
5297         seq_printf(m, "  %s Subslice Total: %u\n", type,
5298                    sseu_subslice_total(sseu));
5299         seq_printf(m, "  %s Subslice Mask: %04x\n", type,
5300                    sseu->subslice_mask);
5301         seq_printf(m, "  %s Subslice Per Slice: %u\n", type,
5302                    hweight8(sseu->subslice_mask));
5303         seq_printf(m, "  %s EU Total: %u\n", type,
5304                    sseu->eu_total);
5305         seq_printf(m, "  %s EU Per Subslice: %u\n", type,
5306                    sseu->eu_per_subslice);
5307
5308         if (!is_available_info)
5309                 return;
5310
5311         seq_printf(m, "  Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv)));
5312         if (HAS_POOLED_EU(dev_priv))
5313                 seq_printf(m, "  Min EU in pool: %u\n", sseu->min_eu_in_pool);
5314
5315         seq_printf(m, "  Has Slice Power Gating: %s\n",
5316                    yesno(sseu->has_slice_pg));
5317         seq_printf(m, "  Has Subslice Power Gating: %s\n",
5318                    yesno(sseu->has_subslice_pg));
5319         seq_printf(m, "  Has EU Power Gating: %s\n",
5320                    yesno(sseu->has_eu_pg));
5321 }
5322
5323 static int i915_sseu_status(struct seq_file *m, void *unused)
5324 {
5325         struct drm_i915_private *dev_priv = node_to_i915(m->private);
5326         struct sseu_dev_info sseu;
5327
5328         if (INTEL_GEN(dev_priv) < 8)
5329                 return -ENODEV;
5330
5331         seq_puts(m, "SSEU Device Info\n");
5332         i915_print_sseu_info(m, true, &INTEL_INFO(dev_priv)->sseu);
5333
5334         seq_puts(m, "SSEU Device Status\n");
5335         memset(&sseu, 0, sizeof(sseu));
5336
5337         intel_runtime_pm_get(dev_priv);
5338
5339         if (IS_CHERRYVIEW(dev_priv)) {
5340                 cherryview_sseu_device_status(dev_priv, &sseu);
5341         } else if (IS_BROADWELL(dev_priv)) {
5342                 broadwell_sseu_device_status(dev_priv, &sseu);
5343         } else if (INTEL_GEN(dev_priv) >= 9) {
5344                 gen9_sseu_device_status(dev_priv, &sseu);
5345         }
5346
5347         intel_runtime_pm_put(dev_priv);
5348
5349         i915_print_sseu_info(m, false, &sseu);
5350
5351         return 0;
5352 }
5353
5354 static int i915_forcewake_open(struct inode *inode, struct file *file)
5355 {
5356         struct drm_i915_private *dev_priv = inode->i_private;
5357
5358         if (INTEL_GEN(dev_priv) < 6)
5359                 return 0;
5360
5361         intel_runtime_pm_get(dev_priv);
5362         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5363
5364         return 0;
5365 }
5366
5367 static int i915_forcewake_release(struct inode *inode, struct file *file)
5368 {
5369         struct drm_i915_private *dev_priv = inode->i_private;
5370
5371         if (INTEL_GEN(dev_priv) < 6)
5372                 return 0;
5373
5374         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5375         intel_runtime_pm_put(dev_priv);
5376
5377         return 0;
5378 }
5379
5380 static const struct file_operations i915_forcewake_fops = {
5381         .owner = THIS_MODULE,
5382         .open = i915_forcewake_open,
5383         .release = i915_forcewake_release,
5384 };
5385
5386 static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
5387 {
5388         struct dentry *ent;
5389
5390         ent = debugfs_create_file("i915_forcewake_user",
5391                                   S_IRUSR,
5392                                   root, to_i915(minor->dev),
5393                                   &i915_forcewake_fops);
5394         if (!ent)
5395                 return -ENOMEM;
5396
5397         return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
5398 }
5399
5400 static int i915_debugfs_create(struct dentry *root,
5401                                struct drm_minor *minor,
5402                                const char *name,
5403                                const struct file_operations *fops)
5404 {
5405         struct dentry *ent;
5406
5407         ent = debugfs_create_file(name,
5408                                   S_IRUGO | S_IWUSR,
5409                                   root, to_i915(minor->dev),
5410                                   fops);
5411         if (!ent)
5412                 return -ENOMEM;
5413
5414         return drm_add_fake_info_node(minor, ent, fops);
5415 }
5416
5417 static const struct drm_info_list i915_debugfs_list[] = {
5418         {"i915_capabilities", i915_capabilities, 0},
5419         {"i915_gem_objects", i915_gem_object_info, 0},
5420         {"i915_gem_gtt", i915_gem_gtt_info, 0},
5421         {"i915_gem_pin_display", i915_gem_gtt_info, 0, (void *)1},
5422         {"i915_gem_stolen", i915_gem_stolen_list_info },
5423         {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
5424         {"i915_gem_request", i915_gem_request_info, 0},
5425         {"i915_gem_seqno", i915_gem_seqno_info, 0},
5426         {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
5427         {"i915_gem_interrupt", i915_interrupt_info, 0},
5428         {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
5429         {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
5430         {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
5431         {"i915_gem_hws_vebox", i915_hws_info, 0, (void *)VECS},
5432         {"i915_gem_batch_pool", i915_gem_batch_pool_info, 0},
5433         {"i915_guc_info", i915_guc_info, 0},
5434         {"i915_guc_load_status", i915_guc_load_status_info, 0},
5435         {"i915_guc_log_dump", i915_guc_log_dump, 0},
5436         {"i915_frequency_info", i915_frequency_info, 0},
5437         {"i915_hangcheck_info", i915_hangcheck_info, 0},
5438         {"i915_drpc_info", i915_drpc_info, 0},
5439         {"i915_emon_status", i915_emon_status, 0},
5440         {"i915_ring_freq_table", i915_ring_freq_table, 0},
5441         {"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
5442         {"i915_fbc_status", i915_fbc_status, 0},
5443         {"i915_ips_status", i915_ips_status, 0},
5444         {"i915_sr_status", i915_sr_status, 0},
5445         {"i915_opregion", i915_opregion, 0},
5446         {"i915_vbt", i915_vbt, 0},
5447         {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
5448         {"i915_context_status", i915_context_status, 0},
5449         {"i915_dump_lrc", i915_dump_lrc, 0},
5450         {"i915_forcewake_domains", i915_forcewake_domains, 0},
5451         {"i915_swizzle_info", i915_swizzle_info, 0},
5452         {"i915_ppgtt_info", i915_ppgtt_info, 0},
5453         {"i915_llc", i915_llc, 0},
5454         {"i915_edp_psr_status", i915_edp_psr_status, 0},
5455         {"i915_sink_crc_eDP1", i915_sink_crc, 0},
5456         {"i915_energy_uJ", i915_energy_uJ, 0},
5457         {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
5458         {"i915_power_domain_info", i915_power_domain_info, 0},
5459         {"i915_dmc_info", i915_dmc_info, 0},
5460         {"i915_display_info", i915_display_info, 0},
5461         {"i915_engine_info", i915_engine_info, 0},
5462         {"i915_semaphore_status", i915_semaphore_status, 0},
5463         {"i915_shared_dplls_info", i915_shared_dplls_info, 0},
5464         {"i915_dp_mst_info", i915_dp_mst_info, 0},
5465         {"i915_wa_registers", i915_wa_registers, 0},
5466         {"i915_ddb_info", i915_ddb_info, 0},
5467         {"i915_sseu_status", i915_sseu_status, 0},
5468         {"i915_drrs_status", i915_drrs_status, 0},
5469         {"i915_rps_boost_info", i915_rps_boost_info, 0},
5470 };
5471 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
5472
5473 static const struct i915_debugfs_files {
5474         const char *name;
5475         const struct file_operations *fops;
5476 } i915_debugfs_files[] = {
5477         {"i915_wedged", &i915_wedged_fops},
5478         {"i915_max_freq", &i915_max_freq_fops},
5479         {"i915_min_freq", &i915_min_freq_fops},
5480         {"i915_cache_sharing", &i915_cache_sharing_fops},
5481         {"i915_ring_missed_irq", &i915_ring_missed_irq_fops},
5482         {"i915_ring_test_irq", &i915_ring_test_irq_fops},
5483         {"i915_gem_drop_caches", &i915_drop_caches_fops},
5484 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
5485         {"i915_error_state", &i915_error_state_fops},
5486 #endif
5487         {"i915_next_seqno", &i915_next_seqno_fops},
5488         {"i915_display_crc_ctl", &i915_display_crc_ctl_fops},
5489         {"i915_pri_wm_latency", &i915_pri_wm_latency_fops},
5490         {"i915_spr_wm_latency", &i915_spr_wm_latency_fops},
5491         {"i915_cur_wm_latency", &i915_cur_wm_latency_fops},
5492         {"i915_fbc_false_color", &i915_fbc_fc_fops},
5493         {"i915_dp_test_data", &i915_displayport_test_data_fops},
5494         {"i915_dp_test_type", &i915_displayport_test_type_fops},
5495         {"i915_dp_test_active", &i915_displayport_test_active_fops},
5496         {"i915_guc_log_control", &i915_guc_log_control_fops}
5497 };
5498
5499 void intel_display_crc_init(struct drm_i915_private *dev_priv)
5500 {
5501         enum pipe pipe;
5502
5503         for_each_pipe(dev_priv, pipe) {
5504                 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
5505
5506                 pipe_crc->opened = false;
5507                 spin_lock_init(&pipe_crc->lock);
5508                 init_waitqueue_head(&pipe_crc->wq);
5509         }
5510 }
5511
5512 int i915_debugfs_register(struct drm_i915_private *dev_priv)
5513 {
5514         struct drm_minor *minor = dev_priv->drm.primary;
5515         int ret, i;
5516
5517         ret = i915_forcewake_create(minor->debugfs_root, minor);
5518         if (ret)
5519                 return ret;
5520
5521         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5522                 ret = i915_pipe_crc_create(minor->debugfs_root, minor, i);
5523                 if (ret)
5524                         return ret;
5525         }
5526
5527         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5528                 ret = i915_debugfs_create(minor->debugfs_root, minor,
5529                                           i915_debugfs_files[i].name,
5530                                           i915_debugfs_files[i].fops);
5531                 if (ret)
5532                         return ret;
5533         }
5534
5535         return drm_debugfs_create_files(i915_debugfs_list,
5536                                         I915_DEBUGFS_ENTRIES,
5537                                         minor->debugfs_root, minor);
5538 }
5539
5540 void i915_debugfs_unregister(struct drm_i915_private *dev_priv)
5541 {
5542         struct drm_minor *minor = dev_priv->drm.primary;
5543         int i;
5544
5545         drm_debugfs_remove_files(i915_debugfs_list,
5546                                  I915_DEBUGFS_ENTRIES, minor);
5547
5548         drm_debugfs_remove_files((struct drm_info_list *)&i915_forcewake_fops,
5549                                  1, minor);
5550
5551         for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) {
5552                 struct drm_info_list *info_list =
5553                         (struct drm_info_list *)&i915_pipe_crc_data[i];
5554
5555                 drm_debugfs_remove_files(info_list, 1, minor);
5556         }
5557
5558         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
5559                 struct drm_info_list *info_list =
5560                         (struct drm_info_list *)i915_debugfs_files[i].fops;
5561
5562                 drm_debugfs_remove_files(info_list, 1, minor);
5563         }
5564 }
5565
5566 struct dpcd_block {
5567         /* DPCD dump start address. */
5568         unsigned int offset;
5569         /* DPCD dump end address, inclusive. If unset, .size will be used. */
5570         unsigned int end;
5571         /* DPCD dump size. Used if .end is unset. If unset, defaults to 1. */
5572         size_t size;
5573         /* Only valid for eDP. */
5574         bool edp;
5575 };
5576
5577 static const struct dpcd_block i915_dpcd_debug[] = {
5578         { .offset = DP_DPCD_REV, .size = DP_RECEIVER_CAP_SIZE },
5579         { .offset = DP_PSR_SUPPORT, .end = DP_PSR_CAPS },
5580         { .offset = DP_DOWNSTREAM_PORT_0, .size = 16 },
5581         { .offset = DP_LINK_BW_SET, .end = DP_EDP_CONFIGURATION_SET },
5582         { .offset = DP_SINK_COUNT, .end = DP_ADJUST_REQUEST_LANE2_3 },
5583         { .offset = DP_SET_POWER },
5584         { .offset = DP_EDP_DPCD_REV },
5585         { .offset = DP_EDP_GENERAL_CAP_1, .end = DP_EDP_GENERAL_CAP_3 },
5586         { .offset = DP_EDP_DISPLAY_CONTROL_REGISTER, .end = DP_EDP_BACKLIGHT_FREQ_CAP_MAX_LSB },
5587         { .offset = DP_EDP_DBC_MINIMUM_BRIGHTNESS_SET, .end = DP_EDP_DBC_MAXIMUM_BRIGHTNESS_SET },
5588 };
5589
5590 static int i915_dpcd_show(struct seq_file *m, void *data)
5591 {
5592         struct drm_connector *connector = m->private;
5593         struct intel_dp *intel_dp =
5594                 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5595         uint8_t buf[16];
5596         ssize_t err;
5597         int i;
5598
5599         if (connector->status != connector_status_connected)
5600                 return -ENODEV;
5601
5602         for (i = 0; i < ARRAY_SIZE(i915_dpcd_debug); i++) {
5603                 const struct dpcd_block *b = &i915_dpcd_debug[i];
5604                 size_t size = b->end ? b->end - b->offset + 1 : (b->size ?: 1);
5605
5606                 if (b->edp &&
5607                     connector->connector_type != DRM_MODE_CONNECTOR_eDP)
5608                         continue;
5609
5610                 /* low tech for now */
5611                 if (WARN_ON(size > sizeof(buf)))
5612                         continue;
5613
5614                 err = drm_dp_dpcd_read(&intel_dp->aux, b->offset, buf, size);
5615                 if (err <= 0) {
5616                         DRM_ERROR("dpcd read (%zu bytes at %u) failed (%zd)\n",
5617                                   size, b->offset, err);
5618                         continue;
5619                 }
5620
5621                 seq_printf(m, "%04x: %*ph\n", b->offset, (int) size, buf);
5622         }
5623
5624         return 0;
5625 }
5626
5627 static int i915_dpcd_open(struct inode *inode, struct file *file)
5628 {
5629         return single_open(file, i915_dpcd_show, inode->i_private);
5630 }
5631
5632 static const struct file_operations i915_dpcd_fops = {
5633         .owner = THIS_MODULE,
5634         .open = i915_dpcd_open,
5635         .read = seq_read,
5636         .llseek = seq_lseek,
5637         .release = single_release,
5638 };
5639
5640 static int i915_panel_show(struct seq_file *m, void *data)
5641 {
5642         struct drm_connector *connector = m->private;
5643         struct intel_dp *intel_dp =
5644                 enc_to_intel_dp(&intel_attached_encoder(connector)->base);
5645
5646         if (connector->status != connector_status_connected)
5647                 return -ENODEV;
5648
5649         seq_printf(m, "Panel power up delay: %d\n",
5650                    intel_dp->panel_power_up_delay);
5651         seq_printf(m, "Panel power down delay: %d\n",
5652                    intel_dp->panel_power_down_delay);
5653         seq_printf(m, "Backlight on delay: %d\n",
5654                    intel_dp->backlight_on_delay);
5655         seq_printf(m, "Backlight off delay: %d\n",
5656                    intel_dp->backlight_off_delay);
5657
5658         return 0;
5659 }
5660
5661 static int i915_panel_open(struct inode *inode, struct file *file)
5662 {
5663         return single_open(file, i915_panel_show, inode->i_private);
5664 }
5665
5666 static const struct file_operations i915_panel_fops = {
5667         .owner = THIS_MODULE,
5668         .open = i915_panel_open,
5669         .read = seq_read,
5670         .llseek = seq_lseek,
5671         .release = single_release,
5672 };
5673
5674 /**
5675  * i915_debugfs_connector_add - add i915 specific connector debugfs files
5676  * @connector: pointer to a registered drm_connector
5677  *
5678  * Cleanup will be done by drm_connector_unregister() through a call to
5679  * drm_debugfs_connector_remove().
5680  *
5681  * Returns 0 on success, negative error codes on error.
5682  */
5683 int i915_debugfs_connector_add(struct drm_connector *connector)
5684 {
5685         struct dentry *root = connector->debugfs_entry;
5686
5687         /* The connector must have been registered beforehands. */
5688         if (!root)
5689                 return -ENODEV;
5690
5691         if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort ||
5692             connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5693                 debugfs_create_file("i915_dpcd", S_IRUGO, root,
5694                                     connector, &i915_dpcd_fops);
5695
5696         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
5697                 debugfs_create_file("i915_panel_timings", S_IRUGO, root,
5698                                     connector, &i915_panel_fops);
5699
5700         return 0;
5701 }