drivers/gpu/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "drm_crtc_helper.h"
  32 #include "drm_fb_helper.h"
  33 #include "intel_drv.h"
  34 #include "i915_drm.h"
  35 #include "i915_drv.h"
  36 #include "i915_trace.h"
  37 #include <linux/vgaarb.h>
  38 #include <linux/acpi.h>
  39 #include <linux/pnp.h>
  40 #include <linux/vga_switcheroo.h>
  41 #include <linux/slab.h>
  42
  43 extern int intel_max_stolen; /* from AGP driver */
  44
  45 /**
  46  * Sets up the hardware status page for devices that need a physical address
  47  * in the register.
  48  */
  49 static int i915_init_phys_hws(struct drm_device *dev)
  50 {
  51         drm_i915_private_t *dev_priv = dev->dev_private;
  52         /* Program Hardware Status Page */
  53         dev_priv->status_page_dmah =
  54                 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE);
  55
  56         if (!dev_priv->status_page_dmah) {
  57                 DRM_ERROR("Can not allocate hardware status page\n");
  58                 return -ENOMEM;
  59         }
  60         dev_priv->render_ring.status_page.page_addr
  61                 = dev_priv->status_page_dmah->vaddr;
  62         dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
  63
  64         memset(dev_priv->render_ring.status_page.page_addr, 0, PAGE_SIZE);
  65
  66         if (IS_I965G(dev))
  67                 dev_priv->dma_status_page |= (dev_priv->dma_status_page >> 28) &
  68                                              0xf0;
  69
  70         I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
  71         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
  72         return 0;
  73 }
  74
  75 /**
  76  * Frees the hardware status page, whether it's a physical address or a virtual
  77  * address set up by the X Server.
  78  */
  79 static void i915_free_hws(struct drm_device *dev)
  80 {
  81         drm_i915_private_t *dev_priv = dev->dev_private;
  82         if (dev_priv->status_page_dmah) {
  83                 drm_pci_free(dev, dev_priv->status_page_dmah);
  84                 dev_priv->status_page_dmah = NULL;
  85         }
  86
  87         if (dev_priv->render_ring.status_page.gfx_addr) {
  88                 dev_priv->render_ring.status_page.gfx_addr = 0;
  89                 drm_core_ioremapfree(&dev_priv->hws_map, dev);
  90         }
  91
  92         /* Need to rewrite hardware status page */
  93         I915_WRITE(HWS_PGA, 0x1ffff000);
  94 }
  95
  96 void i915_kernel_lost_context(struct drm_device * dev)
  97 {
  98         drm_i915_private_t *dev_priv = dev->dev_private;
  99         struct drm_i915_master_private *master_priv;
 100         struct intel_ring_buffer *ring = &dev_priv->render_ring;
 101
 102         /*
 103          * We should never lose context on the ring with modesetting
 104          * as we don't expose it to userspace
 105          */
 106         if (drm_core_check_feature(dev, DRIVER_MODESET))
 107                 return;
 108
 109         ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
 110         ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
 111         ring->space = ring->head - (ring->tail + 8);
 112         if (ring->space < 0)
 113                 ring->space += ring->size;
 114
 115         if (!dev->primary->master)
 116                 return;
 117
 118         master_priv = dev->primary->master->driver_priv;
 119         if (ring->head == ring->tail && master_priv->sarea_priv)
 120                 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
 121 }
 122
 123 static int i915_dma_cleanup(struct drm_device * dev)
 124 {
 125         drm_i915_private_t *dev_priv = dev->dev_private;
 126         /* Make sure interrupts are disabled here because the uninstall ioctl
 127          * may not have been called from userspace and after dev_private
 128          * is freed, it's too late.
 129          */
 130         if (dev->irq_enabled)
 131                 drm_irq_uninstall(dev);
 132
 133         mutex_lock(&dev->struct_mutex);
 134         intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
 135         if (HAS_BSD(dev))
 136                 intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring);
 137         mutex_unlock(&dev->struct_mutex);
 138
 139         /* Clear the HWS virtual address at teardown */
 140         if (I915_NEED_GFX_HWS(dev))
 141                 i915_free_hws(dev);
 142
 143         return 0;
 144 }
 145
 146 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
 147 {
 148         drm_i915_private_t *dev_priv = dev->dev_private;
 149         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 150
 151         master_priv->sarea = drm_getsarea(dev);
 152         if (master_priv->sarea) {
 153                 master_priv->sarea_priv = (drm_i915_sarea_t *)
 154                         ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
 155         } else {
 156                 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
 157         }
 158
 159         if (init->ring_size != 0) {
 160                 if (dev_priv->render_ring.gem_object != NULL) {
 161                         i915_dma_cleanup(dev);
 162                         DRM_ERROR("Client tried to initialize ringbuffer in "
 163                                   "GEM mode\n");
 164                         return -EINVAL;
 165                 }
 166
 167                 dev_priv->render_ring.size = init->ring_size;
 168
 169                 dev_priv->render_ring.map.offset = init->ring_start;
 170                 dev_priv->render_ring.map.size = init->ring_size;
 171                 dev_priv->render_ring.map.type = 0;
 172                 dev_priv->render_ring.map.flags = 0;
 173                 dev_priv->render_ring.map.mtrr = 0;
 174
 175                 drm_core_ioremap_wc(&dev_priv->render_ring.map, dev);
 176
 177                 if (dev_priv->render_ring.map.handle == NULL) {
 178                         i915_dma_cleanup(dev);
 179                         DRM_ERROR("can not ioremap virtual address for"
 180                                   " ring buffer\n");
 181                         return -ENOMEM;
 182                 }
 183         }
 184
 185         dev_priv->render_ring.virtual_start = dev_priv->render_ring.map.handle;
 186
 187         dev_priv->cpp = init->cpp;
 188         dev_priv->back_offset = init->back_offset;
 189         dev_priv->front_offset = init->front_offset;
 190         dev_priv->current_page = 0;
 191         if (master_priv->sarea_priv)
 192                 master_priv->sarea_priv->pf_current_page = 0;
 193
 194         /* Allow hardware batchbuffers unless told otherwise.
 195          */
 196         dev_priv->allow_batchbuffer = 1;
 197
 198         return 0;
 199 }
 200
 201 static int i915_dma_resume(struct drm_device * dev)
 202 {
 203         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 204
 205         struct intel_ring_buffer *ring;
 206         DRM_DEBUG_DRIVER("%s\n", __func__);
 207
 208         ring = &dev_priv->render_ring;
 209
 210         if (ring->map.handle == NULL) {
 211                 DRM_ERROR("can not ioremap virtual address for"
 212                           " ring buffer\n");
 213                 return -ENOMEM;
 214         }
 215
 216         /* Program Hardware Status Page */
 217         if (!ring->status_page.page_addr) {
 218                 DRM_ERROR("Can not find hardware status page\n");
 219                 return -EINVAL;
 220         }
 221         DRM_DEBUG_DRIVER("hw status page @ %p\n",
 222                                 ring->status_page.page_addr);
 223         if (ring->status_page.gfx_addr != 0)
 224                 ring->setup_status_page(dev, ring);
 225         else
 226                 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
 227
 228         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
 229
 230         return 0;
 231 }
 232
 233 static int i915_dma_init(struct drm_device *dev, void *data,
 234                          struct drm_file *file_priv)
 235 {
 236         drm_i915_init_t *init = data;
 237         int retcode = 0;
 238
 239         switch (init->func) {
 240         case I915_INIT_DMA:
 241                 retcode = i915_initialize(dev, init);
 242                 break;
 243         case I915_CLEANUP_DMA:
 244                 retcode = i915_dma_cleanup(dev);
 245                 break;
 246         case I915_RESUME_DMA:
 247                 retcode = i915_dma_resume(dev);
 248                 break;
 249         default:
 250                 retcode = -EINVAL;
 251                 break;
 252         }
 253
 254         return retcode;
 255 }
 256
 257 /* Implement basically the same security restrictions as hardware does
 258  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 259  *
 260  * Most of the calculations below involve calculating the size of a
 261  * particular instruction.  It's important to get the size right as
 262  * that tells us where the next instruction to check is.  Any illegal
 263  * instruction detected will be given a size of zero, which is a
 264  * signal to abort the rest of the buffer.
 265  */
 266 static int do_validate_cmd(int cmd)
 267 {
 268         switch (((cmd >> 29) & 0x7)) {
 269         case 0x0:
 270                 switch ((cmd >> 23) & 0x3f) {
 271                 case 0x0:
 272                         return 1;       /* MI_NOOP */
 273                 case 0x4:
 274                         return 1;       /* MI_FLUSH */
 275                 default:
 276                         return 0;       /* disallow everything else */
 277                 }
 278                 break;
 279         case 0x1:
 280                 return 0;       /* reserved */
 281         case 0x2:
 282                 return (cmd & 0xff) + 2;        /* 2d commands */
 283         case 0x3:
 284                 if (((cmd >> 24) & 0x1f) <= 0x18)
 285                         return 1;
 286
 287                 switch ((cmd >> 24) & 0x1f) {
 288                 case 0x1c:
 289                         return 1;
 290                 case 0x1d:
 291                         switch ((cmd >> 16) & 0xff) {
 292                         case 0x3:
 293                                 return (cmd & 0x1f) + 2;
 294                         case 0x4:
 295                                 return (cmd & 0xf) + 2;
 296                         default:
 297                                 return (cmd & 0xffff) + 2;
 298                         }
 299                 case 0x1e:
 300                         if (cmd & (1 << 23))
 301                                 return (cmd & 0xffff) + 1;
 302                         else
 303                                 return 1;
 304                 case 0x1f:
 305                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 306                                 return (cmd & 0x1ffff) + 2;
 307                         else if (cmd & (1 << 17))       /* indirect random */
 308                                 if ((cmd & 0xffff) == 0)
 309                                         return 0;       /* unknown length, too hard */
 310                                 else
 311                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 312                         else
 313                                 return 2;       /* indirect sequential */
 314                 default:
 315                         return 0;
 316                 }
 317         default:
 318                 return 0;
 319         }
 320
 321         return 0;
 322 }
 323
 324 static int validate_cmd(int cmd)
 325 {
 326         int ret = do_validate_cmd(cmd);
 327
 328 /*      printk("validate_cmd( %x ): %d\n", cmd, ret); */
 329
 330         return ret;
 331 }
 332
 333 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
 334 {
 335         drm_i915_private_t *dev_priv = dev->dev_private;
 336         int i;
 337
 338         if ((dwords+1) * sizeof(int) >= dev_priv->render_ring.size - 8)
 339                 return -EINVAL;
 340
 341         BEGIN_LP_RING((dwords+1)&~1);
 342
 343         for (i = 0; i < dwords;) {
 344                 int cmd, sz;
 345
 346                 cmd = buffer[i];
 347
 348                 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
 349                         return -EINVAL;
 350
 351                 OUT_RING(cmd);
 352
 353                 while (++i, --sz) {
 354                         OUT_RING(buffer[i]);
 355                 }
 356         }
 357
 358         if (dwords & 1)
 359                 OUT_RING(0);
 360
 361         ADVANCE_LP_RING();
 362
 363         return 0;
 364 }
 365
 366 int
 367 i915_emit_box(struct drm_device *dev,
 368               struct drm_clip_rect *boxes,
 369               int i, int DR1, int DR4)
 370 {
 371         struct drm_clip_rect box = boxes[i];
 372
 373         if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
 374                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 375                           box.x1, box.y1, box.x2, box.y2);
 376                 return -EINVAL;
 377         }
 378
 379         if (IS_I965G(dev)) {
 380                 BEGIN_LP_RING(4);
 381                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 382                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 383                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 384                 OUT_RING(DR4);
 385                 ADVANCE_LP_RING();
 386         } else {
 387                 BEGIN_LP_RING(6);
 388                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 389                 OUT_RING(DR1);
 390                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 391                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 392                 OUT_RING(DR4);
 393                 OUT_RING(0);
 394                 ADVANCE_LP_RING();
 395         }
 396
 397         return 0;
 398 }
 399
 400 /* XXX: Emitting the counter should really be moved to part of the IRQ
 401  * emit. For now, do it in both places:
 402  */
 403
 404 static void i915_emit_breadcrumb(struct drm_device *dev)
 405 {
 406         drm_i915_private_t *dev_priv = dev->dev_private;
 407         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 408
 409         dev_priv->counter++;
 410         if (dev_priv->counter > 0x7FFFFFFFUL)
 411                 dev_priv->counter = 0;
 412         if (master_priv->sarea_priv)
 413                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
 414
 415         BEGIN_LP_RING(4);
 416         OUT_RING(MI_STORE_DWORD_INDEX);
 417         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 418         OUT_RING(dev_priv->counter);
 419         OUT_RING(0);
 420         ADVANCE_LP_RING();
 421 }
 422
 423 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 424                                    drm_i915_cmdbuffer_t *cmd,
 425                                    struct drm_clip_rect *cliprects,
 426                                    void *cmdbuf)
 427 {
 428         int nbox = cmd->num_cliprects;
 429         int i = 0, count, ret;
 430
 431         if (cmd->sz & 0x3) {
 432                 DRM_ERROR("alignment");
 433                 return -EINVAL;
 434         }
 435
 436         i915_kernel_lost_context(dev);
 437
 438         count = nbox ? nbox : 1;
 439
 440         for (i = 0; i < count; i++) {
 441                 if (i < nbox) {
 442                         ret = i915_emit_box(dev, cliprects, i,
 443                                             cmd->DR1, cmd->DR4);
 444                         if (ret)
 445                                 return ret;
 446                 }
 447
 448                 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
 449                 if (ret)
 450                         return ret;
 451         }
 452
 453         i915_emit_breadcrumb(dev);
 454         return 0;
 455 }
 456
 457 static int i915_dispatch_batchbuffer(struct drm_device * dev,
 458                                      drm_i915_batchbuffer_t * batch,
 459                                      struct drm_clip_rect *cliprects)
 460 {
 461         int nbox = batch->num_cliprects;
 462         int i = 0, count;
 463
 464         if ((batch->start | batch->used) & 0x7) {
 465                 DRM_ERROR("alignment");
 466                 return -EINVAL;
 467         }
 468
 469         i915_kernel_lost_context(dev);
 470
 471         count = nbox ? nbox : 1;
 472
 473         for (i = 0; i < count; i++) {
 474                 if (i < nbox) {
 475                         int ret = i915_emit_box(dev, cliprects, i,
 476                                                 batch->DR1, batch->DR4);
 477                         if (ret)
 478                                 return ret;
 479                 }
 480
 481                 if (!IS_I830(dev) && !IS_845G(dev)) {
 482                         BEGIN_LP_RING(2);
 483                         if (IS_I965G(dev)) {
 484                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
 485                                 OUT_RING(batch->start);
 486                         } else {
 487                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 488                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 489                         }
 490                         ADVANCE_LP_RING();
 491                 } else {
 492                         BEGIN_LP_RING(4);
 493                         OUT_RING(MI_BATCH_BUFFER);
 494                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 495                         OUT_RING(batch->start + batch->used - 4);
 496                         OUT_RING(0);
 497                         ADVANCE_LP_RING();
 498                 }
 499         }
 500
 501         i915_emit_breadcrumb(dev);
 502
 503         return 0;
 504 }
 505
 506 static int i915_dispatch_flip(struct drm_device * dev)
 507 {
 508         drm_i915_private_t *dev_priv = dev->dev_private;
 509         struct drm_i915_master_private *master_priv =
 510                 dev->primary->master->driver_priv;
 511
 512         if (!master_priv->sarea_priv)
 513                 return -EINVAL;
 514
 515         DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
 516                           __func__,
 517                          dev_priv->current_page,
 518                          master_priv->sarea_priv->pf_current_page);
 519
 520         i915_kernel_lost_context(dev);
 521
 522         BEGIN_LP_RING(2);
 523         OUT_RING(MI_FLUSH | MI_READ_FLUSH);
 524         OUT_RING(0);
 525         ADVANCE_LP_RING();
 526
 527         BEGIN_LP_RING(6);
 528         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
 529         OUT_RING(0);
 530         if (dev_priv->current_page == 0) {
 531                 OUT_RING(dev_priv->back_offset);
 532                 dev_priv->current_page = 1;
 533         } else {
 534                 OUT_RING(dev_priv->front_offset);
 535                 dev_priv->current_page = 0;
 536         }
 537         OUT_RING(0);
 538         ADVANCE_LP_RING();
 539
 540         BEGIN_LP_RING(2);
 541         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
 542         OUT_RING(0);
 543         ADVANCE_LP_RING();
 544
 545         master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
 546
 547         BEGIN_LP_RING(4);
 548         OUT_RING(MI_STORE_DWORD_INDEX);
 549         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 550         OUT_RING(dev_priv->counter);
 551         OUT_RING(0);
 552         ADVANCE_LP_RING();
 553
 554         master_priv->sarea_priv->pf_current_page = dev_priv->current_page;
 555         return 0;
 556 }
 557
 558 static int i915_quiescent(struct drm_device * dev)
 559 {
 560         drm_i915_private_t *dev_priv = dev->dev_private;
 561
 562         i915_kernel_lost_context(dev);
 563         return intel_wait_ring_buffer(dev, &dev_priv->render_ring,
 564                                       dev_priv->render_ring.size - 8);
 565 }
 566
 567 static int i915_flush_ioctl(struct drm_device *dev, void *data,
 568                             struct drm_file *file_priv)
 569 {
 570         int ret;
 571
 572         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 573
 574         mutex_lock(&dev->struct_mutex);
 575         ret = i915_quiescent(dev);
 576         mutex_unlock(&dev->struct_mutex);
 577
 578         return ret;
 579 }
 580
 581 static int i915_batchbuffer(struct drm_device *dev, void *data,
 582                             struct drm_file *file_priv)
 583 {
 584         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 585         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 586         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 587             master_priv->sarea_priv;
 588         drm_i915_batchbuffer_t *batch = data;
 589         int ret;
 590         struct drm_clip_rect *cliprects = NULL;
 591
 592         if (!dev_priv->allow_batchbuffer) {
 593                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 594                 return -EINVAL;
 595         }
 596
 597         DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
 598                         batch->start, batch->used, batch->num_cliprects);
 599
 600         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 601
 602         if (batch->num_cliprects < 0)
 603                 return -EINVAL;
 604
 605         if (batch->num_cliprects) {
 606                 cliprects = kcalloc(batch->num_cliprects,
 607                                     sizeof(struct drm_clip_rect),
 608                                     GFP_KERNEL);
 609                 if (cliprects == NULL)
 610                         return -ENOMEM;
 611
 612                 ret = copy_from_user(cliprects, batch->cliprects,
 613                                      batch->num_cliprects *
 614                                      sizeof(struct drm_clip_rect));
 615                 if (ret != 0)
 616                         goto fail_free;
 617         }
 618
 619         mutex_lock(&dev->struct_mutex);
 620         ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
 621         mutex_unlock(&dev->struct_mutex);
 622
 623         if (sarea_priv)
 624                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 625
 626 fail_free:
 627         kfree(cliprects);
 628
 629         return ret;
 630 }
 631
 632 static int i915_cmdbuffer(struct drm_device *dev, void *data,
 633                           struct drm_file *file_priv)
 634 {
 635         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 636         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 637         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 638             master_priv->sarea_priv;
 639         drm_i915_cmdbuffer_t *cmdbuf = data;
 640         struct drm_clip_rect *cliprects = NULL;
 641         void *batch_data;
 642         int ret;
 643
 644         DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 645                         cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 646
 647         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 648
 649         if (cmdbuf->num_cliprects < 0)
 650                 return -EINVAL;
 651
 652         batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
 653         if (batch_data == NULL)
 654                 return -ENOMEM;
 655
 656         ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
 657         if (ret != 0)
 658                 goto fail_batch_free;
 659
 660         if (cmdbuf->num_cliprects) {
 661                 cliprects = kcalloc(cmdbuf->num_cliprects,
 662                                     sizeof(struct drm_clip_rect), GFP_KERNEL);
 663                 if (cliprects == NULL) {
 664                         ret = -ENOMEM;
 665                         goto fail_batch_free;
 666                 }
 667
 668                 ret = copy_from_user(cliprects, cmdbuf->cliprects,
 669                                      cmdbuf->num_cliprects *
 670                                      sizeof(struct drm_clip_rect));
 671                 if (ret != 0)
 672                         goto fail_clip_free;
 673         }
 674
 675         mutex_lock(&dev->struct_mutex);
 676         ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
 677         mutex_unlock(&dev->struct_mutex);
 678         if (ret) {
 679                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 680                 goto fail_clip_free;
 681         }
 682
 683         if (sarea_priv)
 684                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 685
 686 fail_clip_free:
 687         kfree(cliprects);
 688 fail_batch_free:
 689         kfree(batch_data);
 690
 691         return ret;
 692 }
 693
 694 static int i915_flip_bufs(struct drm_device *dev, void *data,
 695                           struct drm_file *file_priv)
 696 {
 697         int ret;
 698
 699         DRM_DEBUG_DRIVER("%s\n", __func__);
 700
 701         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 702
 703         mutex_lock(&dev->struct_mutex);
 704         ret = i915_dispatch_flip(dev);
 705         mutex_unlock(&dev->struct_mutex);
 706
 707         return ret;
 708 }
 709
 710 static int i915_getparam(struct drm_device *dev, void *data,
 711                          struct drm_file *file_priv)
 712 {
 713         drm_i915_private_t *dev_priv = dev->dev_private;
 714         drm_i915_getparam_t *param = data;
 715         int value;
 716
 717         if (!dev_priv) {
 718                 DRM_ERROR("called with no initialization\n");
 719                 return -EINVAL;
 720         }
 721
 722         switch (param->param) {
 723         case I915_PARAM_IRQ_ACTIVE:
 724                 value = dev->pdev->irq ? 1 : 0;
 725                 break;
 726         case I915_PARAM_ALLOW_BATCHBUFFER:
 727                 value = dev_priv->allow_batchbuffer ? 1 : 0;
 728                 break;
 729         case I915_PARAM_LAST_DISPATCH:
 730                 value = READ_BREADCRUMB(dev_priv);
 731                 break;
 732         case I915_PARAM_CHIPSET_ID:
 733                 value = dev->pci_device;
 734                 break;
 735         case I915_PARAM_HAS_GEM:
 736                 value = dev_priv->has_gem;
 737                 break;
 738         case I915_PARAM_NUM_FENCES_AVAIL:
 739                 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
 740                 break;
 741         case I915_PARAM_HAS_OVERLAY:
 742                 value = dev_priv->overlay ? 1 : 0;
 743                 break;
 744         case I915_PARAM_HAS_PAGEFLIPPING:
 745                 value = 1;
 746                 break;
 747         case I915_PARAM_HAS_EXECBUF2:
 748                 /* depends on GEM */
 749                 value = dev_priv->has_gem;
 750                 break;
 751         case I915_PARAM_HAS_BSD:
 752                 value = HAS_BSD(dev);
 753                 break;
 754         default:
 755                 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
 756                                  param->param);
 757                 return -EINVAL;
 758         }
 759
 760         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
 761                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 762                 return -EFAULT;
 763         }
 764
 765         return 0;
 766 }
 767
 768 static int i915_setparam(struct drm_device *dev, void *data,
 769                          struct drm_file *file_priv)
 770 {
 771         drm_i915_private_t *dev_priv = dev->dev_private;
 772         drm_i915_setparam_t *param = data;
 773
 774         if (!dev_priv) {
 775                 DRM_ERROR("called with no initialization\n");
 776                 return -EINVAL;
 777         }
 778
 779         switch (param->param) {
 780         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
 781                 break;
 782         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
 783                 dev_priv->tex_lru_log_granularity = param->value;
 784                 break;
 785         case I915_SETPARAM_ALLOW_BATCHBUFFER:
 786                 dev_priv->allow_batchbuffer = param->value;
 787                 break;
 788         case I915_SETPARAM_NUM_USED_FENCES:
 789                 if (param->value > dev_priv->num_fence_regs ||
 790                     param->value < 0)
 791                         return -EINVAL;
 792                 /* Userspace can use first N regs */
 793                 dev_priv->fence_reg_start = param->value;
 794                 break;
 795         default:
 796                 DRM_DEBUG_DRIVER("unknown parameter %d\n",
 797                                         param->param);
 798                 return -EINVAL;
 799         }
 800
 801         return 0;
 802 }
 803
 804 static int i915_set_status_page(struct drm_device *dev, void *data,
 805                                 struct drm_file *file_priv)
 806 {
 807         drm_i915_private_t *dev_priv = dev->dev_private;
 808         drm_i915_hws_addr_t *hws = data;
 809         struct intel_ring_buffer *ring = &dev_priv->render_ring;
 810
 811         if (!I915_NEED_GFX_HWS(dev))
 812                 return -EINVAL;
 813
 814         if (!dev_priv) {
 815                 DRM_ERROR("called with no initialization\n");
 816                 return -EINVAL;
 817         }
 818
 819         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 820                 WARN(1, "tried to set status page when mode setting active\n");
 821                 return 0;
 822         }
 823
 824         DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
 825
 826         ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
 827
 828         dev_priv->hws_map.offset = dev->agp->base + hws->addr;
 829         dev_priv->hws_map.size = 4*1024;
 830         dev_priv->hws_map.type = 0;
 831         dev_priv->hws_map.flags = 0;
 832         dev_priv->hws_map.mtrr = 0;
 833
 834         drm_core_ioremap_wc(&dev_priv->hws_map, dev);
 835         if (dev_priv->hws_map.handle == NULL) {
 836                 i915_dma_cleanup(dev);
 837                 ring->status_page.gfx_addr = 0;
 838                 DRM_ERROR("can not ioremap virtual address for"
 839                                 " G33 hw status page\n");
 840                 return -ENOMEM;
 841         }
 842         ring->status_page.page_addr = dev_priv->hws_map.handle;
 843         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
 844         I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
 845
 846         DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
 847                          ring->status_page.gfx_addr);
 848         DRM_DEBUG_DRIVER("load hws at %p\n",
 849                          ring->status_page.page_addr);
 850         return 0;
 851 }
 852
 853 static int i915_get_bridge_dev(struct drm_device *dev)
 854 {
 855         struct drm_i915_private *dev_priv = dev->dev_private;
 856
 857         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
 858         if (!dev_priv->bridge_dev) {
 859                 DRM_ERROR("bridge device not found\n");
 860                 return -1;
 861         }
 862         return 0;
 863 }
 864
 865 #define MCHBAR_I915 0x44
 866 #define MCHBAR_I965 0x48
 867 #define MCHBAR_SIZE (4*4096)
 868
 869 #define DEVEN_REG 0x54
 870 #define   DEVEN_MCHBAR_EN (1 << 28)
 871
 872 /* Allocate space for the MCH regs if needed, return nonzero on error */
 873 static int
 874 intel_alloc_mchbar_resource(struct drm_device *dev)
 875 {
 876         drm_i915_private_t *dev_priv = dev->dev_private;
 877         int reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
 878         u32 temp_lo, temp_hi = 0;
 879         u64 mchbar_addr;
 880         int ret = 0;
 881
 882         if (IS_I965G(dev))
 883                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 884         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 885         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 886
 887         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 888 #ifdef CONFIG_PNP
 889         if (mchbar_addr &&
 890             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE)) {
 891                 ret = 0;
 892                 goto out;
 893         }
 894 #endif
 895
 896         /* Get some space for it */
 897         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus, &dev_priv->mch_res,
 898                                      MCHBAR_SIZE, MCHBAR_SIZE,
 899                                      PCIBIOS_MIN_MEM,
 900                                      0,   pcibios_align_resource,
 901                                      dev_priv->bridge_dev);
 902         if (ret) {
 903                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 904                 dev_priv->mch_res.start = 0;
 905                 goto out;
 906         }
 907
 908         if (IS_I965G(dev))
 909                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 910                                        upper_32_bits(dev_priv->mch_res.start));
 911
 912         pci_write_config_dword(dev_priv->bridge_dev, reg,
 913                                lower_32_bits(dev_priv->mch_res.start));
 914 out:
 915         return ret;
 916 }
 917
 918 /* Setup MCHBAR if possible, return true if we should disable it again */
 919 static void
 920 intel_setup_mchbar(struct drm_device *dev)
 921 {
 922         drm_i915_private_t *dev_priv = dev->dev_private;
 923         int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
 924         u32 temp;
 925         bool enabled;
 926
 927         dev_priv->mchbar_need_disable = false;
 928
 929         if (IS_I915G(dev) || IS_I915GM(dev)) {
 930                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
 931                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 932         } else {
 933                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 934                 enabled = temp & 1;
 935         }
 936
 937         /* If it's already enabled, don't have to do anything */
 938         if (enabled)
 939                 return;
 940
 941         if (intel_alloc_mchbar_resource(dev))
 942                 return;
 943
 944         dev_priv->mchbar_need_disable = true;
 945
 946         /* Space is allocated or reserved, so enable it. */
 947         if (IS_I915G(dev) || IS_I915GM(dev)) {
 948                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
 949                                        temp | DEVEN_MCHBAR_EN);
 950         } else {
 951                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 952                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 953         }
 954 }
 955
 956 static void
 957 intel_teardown_mchbar(struct drm_device *dev)
 958 {
 959         drm_i915_private_t *dev_priv = dev->dev_private;
 960         int mchbar_reg = IS_I965G(dev) ? MCHBAR_I965 : MCHBAR_I915;
 961         u32 temp;
 962
 963         if (dev_priv->mchbar_need_disable) {
 964                 if (IS_I915G(dev) || IS_I915GM(dev)) {
 965                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
 966                         temp &= ~DEVEN_MCHBAR_EN;
 967                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
 968                 } else {
 969                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 970                         temp &= ~1;
 971                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
 972                 }
 973         }
 974
 975         if (dev_priv->mch_res.start)
 976                 release_resource(&dev_priv->mch_res);
 977 }
 978
 979 /**
 980  * i915_probe_agp - get AGP bootup configuration
 981  * @pdev: PCI device
 982  * @aperture_size: returns AGP aperture configured size
 983  * @preallocated_size: returns size of BIOS preallocated AGP space
 984  *
 985  * Since Intel integrated graphics are UMA, the BIOS has to set aside
 986  * some RAM for the framebuffer at early boot.  This code figures out
 987  * how much was set aside so we can use it for our own purposes.
 988  */
 989 static int i915_probe_agp(struct drm_device *dev, uint32_t *aperture_size,
 990                           uint32_t *preallocated_size,
 991                           uint32_t *start)
 992 {
 993         struct drm_i915_private *dev_priv = dev->dev_private;
 994         u16 tmp = 0;
 995         unsigned long overhead;
 996         unsigned long stolen;
 997
 998         /* Get the fb aperture size and "stolen" memory amount. */
 999         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &tmp);
1000
1001         *aperture_size = 1024 * 1024;
1002         *preallocated_size = 1024 * 1024;
1003
1004         switch (dev->pdev->device) {
1005         case PCI_DEVICE_ID_INTEL_82830_CGC:
1006         case PCI_DEVICE_ID_INTEL_82845G_IG:
1007         case PCI_DEVICE_ID_INTEL_82855GM_IG:
1008         case PCI_DEVICE_ID_INTEL_82865_IG:
1009                 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
1010                         *aperture_size *= 64;
1011                 else
1012                         *aperture_size *= 128;
1013                 break;
1014         default:
1015                 /* 9xx supports large sizes, just look at the length */
1016                 *aperture_size = pci_resource_len(dev->pdev, 2);
1017                 break;
1018         }
1019
1020         /*
1021          * Some of the preallocated space is taken by the GTT
1022          * and popup.  GTT is 1K per MB of aperture size, and popup is 4K.
1023          */
1024         if (IS_G4X(dev) || IS_PINEVIEW(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev))
1025                 overhead = 4096;
1026         else
1027                 overhead = (*aperture_size / 1024) + 4096;
1028
1029         if (IS_GEN6(dev)) {
1030                 /* SNB has memory control reg at 0x50.w */
1031                 pci_read_config_word(dev->pdev, SNB_GMCH_CTRL, &tmp);
1032
1033                 switch (tmp & SNB_GMCH_GMS_STOLEN_MASK) {
1034                 case INTEL_855_GMCH_GMS_DISABLED:
1035                         DRM_ERROR("video memory is disabled\n");
1036                         return -1;
1037                 case SNB_GMCH_GMS_STOLEN_32M:
1038                         stolen = 32 * 1024 * 1024;
1039                         break;
1040                 case SNB_GMCH_GMS_STOLEN_64M:
1041                         stolen = 64 * 1024 * 1024;
1042                         break;
1043                 case SNB_GMCH_GMS_STOLEN_96M:
1044                         stolen = 96 * 1024 * 1024;
1045                         break;
1046                 case SNB_GMCH_GMS_STOLEN_128M:
1047                         stolen = 128 * 1024 * 1024;
1048                         break;
1049                 case SNB_GMCH_GMS_STOLEN_160M:
1050                         stolen = 160 * 1024 * 1024;
1051                         break;
1052                 case SNB_GMCH_GMS_STOLEN_192M:
1053                         stolen = 192 * 1024 * 1024;
1054                         break;
1055                 case SNB_GMCH_GMS_STOLEN_224M:
1056                         stolen = 224 * 1024 * 1024;
1057                         break;
1058                 case SNB_GMCH_GMS_STOLEN_256M:
1059                         stolen = 256 * 1024 * 1024;
1060                         break;
1061                 case SNB_GMCH_GMS_STOLEN_288M:
1062                         stolen = 288 * 1024 * 1024;
1063                         break;
1064                 case SNB_GMCH_GMS_STOLEN_320M:
1065                         stolen = 320 * 1024 * 1024;
1066                         break;
1067                 case SNB_GMCH_GMS_STOLEN_352M:
1068                         stolen = 352 * 1024 * 1024;
1069                         break;
1070                 case SNB_GMCH_GMS_STOLEN_384M:
1071                         stolen = 384 * 1024 * 1024;
1072                         break;
1073                 case SNB_GMCH_GMS_STOLEN_416M:
1074                         stolen = 416 * 1024 * 1024;
1075                         break;
1076                 case SNB_GMCH_GMS_STOLEN_448M:
1077                         stolen = 448 * 1024 * 1024;
1078                         break;
1079                 case SNB_GMCH_GMS_STOLEN_480M:
1080                         stolen = 480 * 1024 * 1024;
1081                         break;
1082                 case SNB_GMCH_GMS_STOLEN_512M:
1083                         stolen = 512 * 1024 * 1024;
1084                         break;
1085                 default:
1086                         DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
1087                                   tmp & SNB_GMCH_GMS_STOLEN_MASK);
1088                         return -1;
1089                 }
1090         } else {
1091                 switch (tmp & INTEL_GMCH_GMS_MASK) {
1092                 case INTEL_855_GMCH_GMS_DISABLED:
1093                         DRM_ERROR("video memory is disabled\n");
1094                         return -1;
1095                 case INTEL_855_GMCH_GMS_STOLEN_1M:
1096                         stolen = 1 * 1024 * 1024;
1097                         break;
1098                 case INTEL_855_GMCH_GMS_STOLEN_4M:
1099                         stolen = 4 * 1024 * 1024;
1100                         break;
1101                 case INTEL_855_GMCH_GMS_STOLEN_8M:
1102                         stolen = 8 * 1024 * 1024;
1103                         break;
1104                 case INTEL_855_GMCH_GMS_STOLEN_16M:
1105                         stolen = 16 * 1024 * 1024;
1106                         break;
1107                 case INTEL_855_GMCH_GMS_STOLEN_32M:
1108                         stolen = 32 * 1024 * 1024;
1109                         break;
1110                 case INTEL_915G_GMCH_GMS_STOLEN_48M:
1111                         stolen = 48 * 1024 * 1024;
1112                         break;
1113                 case INTEL_915G_GMCH_GMS_STOLEN_64M:
1114                         stolen = 64 * 1024 * 1024;
1115                         break;
1116                 case INTEL_GMCH_GMS_STOLEN_128M:
1117                         stolen = 128 * 1024 * 1024;
1118                         break;
1119                 case INTEL_GMCH_GMS_STOLEN_256M:
1120                         stolen = 256 * 1024 * 1024;
1121                         break;
1122                 case INTEL_GMCH_GMS_STOLEN_96M:
1123                         stolen = 96 * 1024 * 1024;
1124                         break;
1125                 case INTEL_GMCH_GMS_STOLEN_160M:
1126                         stolen = 160 * 1024 * 1024;
1127                         break;
1128                 case INTEL_GMCH_GMS_STOLEN_224M:
1129                         stolen = 224 * 1024 * 1024;
1130                         break;
1131                 case INTEL_GMCH_GMS_STOLEN_352M:
1132                         stolen = 352 * 1024 * 1024;
1133                         break;
1134                 default:
1135                         DRM_ERROR("unexpected GMCH_GMS value: 0x%02x\n",
1136                                   tmp & INTEL_GMCH_GMS_MASK);
1137                         return -1;
1138                 }
1139         }
1140
1141         *preallocated_size = stolen - overhead;
1142         *start = overhead;
1143
1144         return 0;
1145 }
1146
1147 #define PTE_ADDRESS_MASK                0xfffff000
1148 #define PTE_ADDRESS_MASK_HIGH           0x000000f0 /* i915+ */
1149 #define PTE_MAPPING_TYPE_UNCACHED       (0 << 1)
1150 #define PTE_MAPPING_TYPE_DCACHE         (1 << 1) /* i830 only */
1151 #define PTE_MAPPING_TYPE_CACHED         (3 << 1)
1152 #define PTE_MAPPING_TYPE_MASK           (3 << 1)
1153 #define PTE_VALID                       (1 << 0)
1154
1155 /**
1156  * i915_gtt_to_phys - take a GTT address and turn it into a physical one
1157  * @dev: drm device
1158  * @gtt_addr: address to translate
1159  *
1160  * Some chip functions require allocations from stolen space but need the
1161  * physical address of the memory in question.  We use this routine
1162  * to get a physical address suitable for register programming from a given
1163  * GTT address.
1164  */
1165 static unsigned long i915_gtt_to_phys(struct drm_device *dev,
1166                                       unsigned long gtt_addr)
1167 {
1168         unsigned long *gtt;
1169         unsigned long entry, phys;
1170         int gtt_bar = IS_I9XX(dev) ? 0 : 1;
1171         int gtt_offset, gtt_size;
1172
1173         if (IS_I965G(dev)) {
1174                 if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) {
1175                         gtt_offset = 2*1024*1024;
1176                         gtt_size = 2*1024*1024;
1177                 } else {
1178                         gtt_offset = 512*1024;
1179                         gtt_size = 512*1024;
1180                 }
1181         } else {
1182                 gtt_bar = 3;
1183                 gtt_offset = 0;
1184                 gtt_size = pci_resource_len(dev->pdev, gtt_bar);
1185         }
1186
1187         gtt = ioremap_wc(pci_resource_start(dev->pdev, gtt_bar) + gtt_offset,
1188                          gtt_size);
1189         if (!gtt) {
1190                 DRM_ERROR("ioremap of GTT failed\n");
1191                 return 0;
1192         }
1193
1194         entry = *(volatile u32 *)(gtt + (gtt_addr / 1024));
1195
1196         DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, PTE: 0x%08lx\n", gtt_addr, entry);
1197
1198         /* Mask out these reserved bits on this hardware. */
1199         if (!IS_I9XX(dev) || IS_I915G(dev) || IS_I915GM(dev) ||
1200             IS_I945G(dev) || IS_I945GM(dev)) {
1201                 entry &= ~PTE_ADDRESS_MASK_HIGH;
1202         }
1203
1204         /* If it's not a mapping type we know, then bail. */
1205         if ((entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_UNCACHED &&
1206             (entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_CACHED) {
1207                 iounmap(gtt);
1208                 return 0;
1209         }
1210
1211         if (!(entry & PTE_VALID)) {
1212                 DRM_ERROR("bad GTT entry in stolen space\n");
1213                 iounmap(gtt);
1214                 return 0;
1215         }
1216
1217         iounmap(gtt);
1218
1219         phys =(entry & PTE_ADDRESS_MASK) |
1220                 ((uint64_t)(entry & PTE_ADDRESS_MASK_HIGH) << (32 - 4));
1221
1222         DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, phys addr: 0x%08lx\n", gtt_addr, phys);
1223
1224         return phys;
1225 }
1226
1227 static void i915_warn_stolen(struct drm_device *dev)
1228 {
1229         DRM_ERROR("not enough stolen space for compressed buffer, disabling\n");
1230         DRM_ERROR("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n");
1231 }
1232
1233 static void i915_setup_compression(struct drm_device *dev, int size)
1234 {
1235         struct drm_i915_private *dev_priv = dev->dev_private;
1236         struct drm_mm_node *compressed_fb, *uninitialized_var(compressed_llb);
1237         unsigned long cfb_base;
1238         unsigned long ll_base = 0;
1239
1240         /* Leave 1M for line length buffer & misc. */
1241         compressed_fb = drm_mm_search_free(&dev_priv->vram, size, 4096, 0);
1242         if (!compressed_fb) {
1243                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1244                 i915_warn_stolen(dev);
1245                 return;
1246         }
1247
1248         compressed_fb = drm_mm_get_block(compressed_fb, size, 4096);
1249         if (!compressed_fb) {
1250                 i915_warn_stolen(dev);
1251                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1252                 return;
1253         }
1254
1255         cfb_base = i915_gtt_to_phys(dev, compressed_fb->start);
1256         if (!cfb_base) {
1257                 DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
1258                 drm_mm_put_block(compressed_fb);
1259         }
1260
1261         if (!IS_GM45(dev)) {
1262                 compressed_llb = drm_mm_search_free(&dev_priv->vram, 4096,
1263                                                     4096, 0);
1264                 if (!compressed_llb) {
1265                         i915_warn_stolen(dev);
1266                         return;
1267                 }
1268
1269                 compressed_llb = drm_mm_get_block(compressed_llb, 4096, 4096);
1270                 if (!compressed_llb) {
1271                         i915_warn_stolen(dev);
1272                         return;
1273                 }
1274
1275                 ll_base = i915_gtt_to_phys(dev, compressed_llb->start);
1276                 if (!ll_base) {
1277                         DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
1278                         drm_mm_put_block(compressed_fb);
1279                         drm_mm_put_block(compressed_llb);
1280                 }
1281         }
1282
1283         dev_priv->cfb_size = size;
1284
1285         intel_disable_fbc(dev);
1286         dev_priv->compressed_fb = compressed_fb;
1287
1288         if (IS_GM45(dev)) {
1289                 I915_WRITE(DPFC_CB_BASE, compressed_fb->start);
1290         } else {
1291                 I915_WRITE(FBC_CFB_BASE, cfb_base);
1292                 I915_WRITE(FBC_LL_BASE, ll_base);
1293                 dev_priv->compressed_llb = compressed_llb;
1294         }
1295
1296         DRM_DEBUG("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n", cfb_base,
1297                   ll_base, size >> 20);
1298 }
1299
1300 static void i915_cleanup_compression(struct drm_device *dev)
1301 {
1302         struct drm_i915_private *dev_priv = dev->dev_private;
1303
1304         drm_mm_put_block(dev_priv->compressed_fb);
1305         if (dev_priv->compressed_llb)
1306                 drm_mm_put_block(dev_priv->compressed_llb);
1307 }
1308
1309 /* true = enable decode, false = disable decoder */
1310 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1311 {
1312         struct drm_device *dev = cookie;
1313
1314         intel_modeset_vga_set_state(dev, state);
1315         if (state)
1316                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1317                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1318         else
1319                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1320 }
1321
1322 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1323 {
1324         struct drm_device *dev = pci_get_drvdata(pdev);
1325         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1326         if (state == VGA_SWITCHEROO_ON) {
1327                 printk(KERN_INFO "i915: switched on\n");
1328                 /* i915 resume handler doesn't set to D0 */
1329                 pci_set_power_state(dev->pdev, PCI_D0);
1330                 i915_resume(dev);
1331                 drm_kms_helper_poll_enable(dev);
1332         } else {
1333                 printk(KERN_ERR "i915: switched off\n");
1334                 drm_kms_helper_poll_disable(dev);
1335                 i915_suspend(dev, pmm);
1336         }
1337 }
1338
1339 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1340 {
1341         struct drm_device *dev = pci_get_drvdata(pdev);
1342         bool can_switch;
1343
1344         spin_lock(&dev->count_lock);
1345         can_switch = (dev->open_count == 0);
1346         spin_unlock(&dev->count_lock);
1347         return can_switch;
1348 }
1349
1350 static int i915_load_modeset_init(struct drm_device *dev,
1351                                   unsigned long prealloc_start,
1352                                   unsigned long prealloc_size,
1353                                   unsigned long agp_size)
1354 {
1355         struct drm_i915_private *dev_priv = dev->dev_private;
1356         int fb_bar = IS_I9XX(dev) ? 2 : 0;
1357         int ret = 0;
1358
1359         dev->mode_config.fb_base = drm_get_resource_start(dev, fb_bar) &
1360                 0xff000000;
1361
1362         /* Basic memrange allocator for stolen space (aka vram) */
1363         drm_mm_init(&dev_priv->vram, 0, prealloc_size);
1364         DRM_INFO("set up %ldM of stolen space\n", prealloc_size / (1024*1024));
1365
1366         /* We're off and running w/KMS */
1367         dev_priv->mm.suspended = 0;
1368
1369         /* Let GEM Manage from end of prealloc space to end of aperture.
1370          *
1371          * However, leave one page at the end still bound to the scratch page.
1372          * There are a number of places where the hardware apparently
1373          * prefetches past the end of the object, and we've seen multiple
1374          * hangs with the GPU head pointer stuck in a batchbuffer bound
1375          * at the last page of the aperture.  One page should be enough to
1376          * keep any prefetching inside of the aperture.
1377          */
1378         i915_gem_do_init(dev, prealloc_size, agp_size - 4096);
1379
1380         mutex_lock(&dev->struct_mutex);
1381         ret = i915_gem_init_ringbuffer(dev);
1382         mutex_unlock(&dev->struct_mutex);
1383         if (ret)
1384                 goto out;
1385
1386         /* Try to set up FBC with a reasonable compressed buffer size */
1387         if (I915_HAS_FBC(dev) && i915_powersave) {
1388                 int cfb_size;
1389
1390                 /* Try to get an 8M buffer... */
1391                 if (prealloc_size > (9*1024*1024))
1392                         cfb_size = 8*1024*1024;
1393                 else /* fall back to 7/8 of the stolen space */
1394                         cfb_size = prealloc_size * 7 / 8;
1395                 i915_setup_compression(dev, cfb_size);
1396         }
1397
1398         /* Allow hardware batchbuffers unless told otherwise.
1399          */
1400         dev_priv->allow_batchbuffer = 1;
1401
1402         ret = intel_init_bios(dev);
1403         if (ret)
1404                 DRM_INFO("failed to find VBIOS tables\n");
1405
1406         /* if we have > 1 VGA cards, then disable the radeon VGA resources */
1407         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1408         if (ret)
1409                 goto cleanup_ringbuffer;
1410
1411         ret = vga_switcheroo_register_client(dev->pdev,
1412                                              i915_switcheroo_set_state,
1413                                              i915_switcheroo_can_switch);
1414         if (ret)
1415                 goto cleanup_vga_client;
1416
1417         /* IIR "flip pending" bit means done if this bit is set */
1418         if (IS_GEN3(dev) && (I915_READ(ECOSKPD) & ECO_FLIP_DONE))
1419                 dev_priv->flip_pending_is_done = true;
1420
1421         intel_modeset_init(dev);
1422
1423         ret = drm_irq_install(dev);
1424         if (ret)
1425                 goto cleanup_vga_switcheroo;
1426
1427         /* Always safe in the mode setting case. */
1428         /* FIXME: do pre/post-mode set stuff in core KMS code */
1429         dev->vblank_disable_allowed = 1;
1430
1431         /*
1432          * Initialize the hardware status page IRQ location.
1433          */
1434
1435         I915_WRITE(INSTPM, (1 << 5) | (1 << 21));
1436
1437         ret = intel_fbdev_init(dev);
1438         if (ret)
1439                 goto cleanup_irq;
1440
1441         drm_kms_helper_poll_init(dev);
1442         return 0;
1443
1444 cleanup_irq:
1445         drm_irq_uninstall(dev);
1446 cleanup_vga_switcheroo:
1447         vga_switcheroo_unregister_client(dev->pdev);
1448 cleanup_vga_client:
1449         vga_client_register(dev->pdev, NULL, NULL, NULL);
1450 cleanup_ringbuffer:
1451         mutex_lock(&dev->struct_mutex);
1452         i915_gem_cleanup_ringbuffer(dev);
1453         mutex_unlock(&dev->struct_mutex);
1454 out:
1455         return ret;
1456 }
1457
1458 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1459 {
1460         struct drm_i915_master_private *master_priv;
1461
1462         master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1463         if (!master_priv)
1464                 return -ENOMEM;
1465
1466         master->driver_priv = master_priv;
1467         return 0;
1468 }
1469
1470 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1471 {
1472         struct drm_i915_master_private *master_priv = master->driver_priv;
1473
1474         if (!master_priv)
1475                 return;
1476
1477         kfree(master_priv);
1478
1479         master->driver_priv = NULL;
1480 }
1481
1482 static void i915_pineview_get_mem_freq(struct drm_device *dev)
1483 {
1484         drm_i915_private_t *dev_priv = dev->dev_private;
1485         u32 tmp;
1486
1487         tmp = I915_READ(CLKCFG);
1488
1489         switch (tmp & CLKCFG_FSB_MASK) {
1490         case CLKCFG_FSB_533:
1491                 dev_priv->fsb_freq = 533; /* 133*4 */
1492                 break;
1493         case CLKCFG_FSB_800:
1494                 dev_priv->fsb_freq = 800; /* 200*4 */
1495                 break;
1496         case CLKCFG_FSB_667:
1497                 dev_priv->fsb_freq =  667; /* 167*4 */
1498                 break;
1499         case CLKCFG_FSB_400:
1500                 dev_priv->fsb_freq = 400; /* 100*4 */
1501                 break;
1502         }
1503
1504         switch (tmp & CLKCFG_MEM_MASK) {
1505         case CLKCFG_MEM_533:
1506                 dev_priv->mem_freq = 533;
1507                 break;
1508         case CLKCFG_MEM_667:
1509                 dev_priv->mem_freq = 667;
1510                 break;
1511         case CLKCFG_MEM_800:
1512                 dev_priv->mem_freq = 800;
1513                 break;
1514         }
1515
1516         /* detect pineview DDR3 setting */
1517         tmp = I915_READ(CSHRDDR3CTL);
1518         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
1519 }
1520
1521 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
1522 {
1523         drm_i915_private_t *dev_priv = dev->dev_private;
1524         u16 ddrpll, csipll;
1525
1526         ddrpll = I915_READ16(DDRMPLL1);
1527         csipll = I915_READ16(CSIPLL0);
1528
1529         switch (ddrpll & 0xff) {
1530         case 0xc:
1531                 dev_priv->mem_freq = 800;
1532                 break;
1533         case 0x10:
1534                 dev_priv->mem_freq = 1066;
1535                 break;
1536         case 0x14:
1537                 dev_priv->mem_freq = 1333;
1538                 break;
1539         case 0x18:
1540                 dev_priv->mem_freq = 1600;
1541                 break;
1542         default:
1543                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
1544                                  ddrpll & 0xff);
1545                 dev_priv->mem_freq = 0;
1546                 break;
1547         }
1548
1549         dev_priv->r_t = dev_priv->mem_freq;
1550
1551         switch (csipll & 0x3ff) {
1552         case 0x00c:
1553                 dev_priv->fsb_freq = 3200;
1554                 break;
1555         case 0x00e:
1556                 dev_priv->fsb_freq = 3733;
1557                 break;
1558         case 0x010:
1559                 dev_priv->fsb_freq = 4266;
1560                 break;
1561         case 0x012:
1562                 dev_priv->fsb_freq = 4800;
1563                 break;
1564         case 0x014:
1565                 dev_priv->fsb_freq = 5333;
1566                 break;
1567         case 0x016:
1568                 dev_priv->fsb_freq = 5866;
1569                 break;
1570         case 0x018:
1571                 dev_priv->fsb_freq = 6400;
1572                 break;
1573         default:
1574                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
1575                                  csipll & 0x3ff);
1576                 dev_priv->fsb_freq = 0;
1577                 break;
1578         }
1579
1580         if (dev_priv->fsb_freq == 3200) {
1581                 dev_priv->c_m = 0;
1582         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
1583                 dev_priv->c_m = 1;
1584         } else {
1585                 dev_priv->c_m = 2;
1586         }
1587 }
1588
1589 struct v_table {
1590         u8 vid;
1591         unsigned long vd; /* in .1 mil */
1592         unsigned long vm; /* in .1 mil */
1593         u8 pvid;
1594 };
1595
1596 static struct v_table v_table[] = {
1597         { 0, 16125, 15000, 0x7f, },
1598         { 1, 16000, 14875, 0x7e, },
1599         { 2, 15875, 14750, 0x7d, },
1600         { 3, 15750, 14625, 0x7c, },
1601         { 4, 15625, 14500, 0x7b, },
1602         { 5, 15500, 14375, 0x7a, },
1603         { 6, 15375, 14250, 0x79, },
1604         { 7, 15250, 14125, 0x78, },
1605         { 8, 15125, 14000, 0x77, },
1606         { 9, 15000, 13875, 0x76, },
1607         { 10, 14875, 13750, 0x75, },
1608         { 11, 14750, 13625, 0x74, },
1609         { 12, 14625, 13500, 0x73, },
1610         { 13, 14500, 13375, 0x72, },
1611         { 14, 14375, 13250, 0x71, },
1612         { 15, 14250, 13125, 0x70, },
1613         { 16, 14125, 13000, 0x6f, },
1614         { 17, 14000, 12875, 0x6e, },
1615         { 18, 13875, 12750, 0x6d, },
1616         { 19, 13750, 12625, 0x6c, },
1617         { 20, 13625, 12500, 0x6b, },
1618         { 21, 13500, 12375, 0x6a, },
1619         { 22, 13375, 12250, 0x69, },
1620         { 23, 13250, 12125, 0x68, },
1621         { 24, 13125, 12000, 0x67, },
1622         { 25, 13000, 11875, 0x66, },
1623         { 26, 12875, 11750, 0x65, },
1624         { 27, 12750, 11625, 0x64, },
1625         { 28, 12625, 11500, 0x63, },
1626         { 29, 12500, 11375, 0x62, },
1627         { 30, 12375, 11250, 0x61, },
1628         { 31, 12250, 11125, 0x60, },
1629         { 32, 12125, 11000, 0x5f, },
1630         { 33, 12000, 10875, 0x5e, },
1631         { 34, 11875, 10750, 0x5d, },
1632         { 35, 11750, 10625, 0x5c, },
1633         { 36, 11625, 10500, 0x5b, },
1634         { 37, 11500, 10375, 0x5a, },
1635         { 38, 11375, 10250, 0x59, },
1636         { 39, 11250, 10125, 0x58, },
1637         { 40, 11125, 10000, 0x57, },
1638         { 41, 11000, 9875, 0x56, },
1639         { 42, 10875, 9750, 0x55, },
1640         { 43, 10750, 9625, 0x54, },
1641         { 44, 10625, 9500, 0x53, },
1642         { 45, 10500, 9375, 0x52, },
1643         { 46, 10375, 9250, 0x51, },
1644         { 47, 10250, 9125, 0x50, },
1645         { 48, 10125, 9000, 0x4f, },
1646         { 49, 10000, 8875, 0x4e, },
1647         { 50, 9875, 8750, 0x4d, },
1648         { 51, 9750, 8625, 0x4c, },
1649         { 52, 9625, 8500, 0x4b, },
1650         { 53, 9500, 8375, 0x4a, },
1651         { 54, 9375, 8250, 0x49, },
1652         { 55, 9250, 8125, 0x48, },
1653         { 56, 9125, 8000, 0x47, },
1654         { 57, 9000, 7875, 0x46, },
1655         { 58, 8875, 7750, 0x45, },
1656         { 59, 8750, 7625, 0x44, },
1657         { 60, 8625, 7500, 0x43, },
1658         { 61, 8500, 7375, 0x42, },
1659         { 62, 8375, 7250, 0x41, },
1660         { 63, 8250, 7125, 0x40, },
1661         { 64, 8125, 7000, 0x3f, },
1662         { 65, 8000, 6875, 0x3e, },
1663         { 66, 7875, 6750, 0x3d, },
1664         { 67, 7750, 6625, 0x3c, },
1665         { 68, 7625, 6500, 0x3b, },
1666         { 69, 7500, 6375, 0x3a, },
1667         { 70, 7375, 6250, 0x39, },
1668         { 71, 7250, 6125, 0x38, },
1669         { 72, 7125, 6000, 0x37, },
1670         { 73, 7000, 5875, 0x36, },
1671         { 74, 6875, 5750, 0x35, },
1672         { 75, 6750, 5625, 0x34, },
1673         { 76, 6625, 5500, 0x33, },
1674         { 77, 6500, 5375, 0x32, },
1675         { 78, 6375, 5250, 0x31, },
1676         { 79, 6250, 5125, 0x30, },
1677         { 80, 6125, 5000, 0x2f, },
1678         { 81, 6000, 4875, 0x2e, },
1679         { 82, 5875, 4750, 0x2d, },
1680         { 83, 5750, 4625, 0x2c, },
1681         { 84, 5625, 4500, 0x2b, },
1682         { 85, 5500, 4375, 0x2a, },
1683         { 86, 5375, 4250, 0x29, },
1684         { 87, 5250, 4125, 0x28, },
1685         { 88, 5125, 4000, 0x27, },
1686         { 89, 5000, 3875, 0x26, },
1687         { 90, 4875, 3750, 0x25, },
1688         { 91, 4750, 3625, 0x24, },
1689         { 92, 4625, 3500, 0x23, },
1690         { 93, 4500, 3375, 0x22, },
1691         { 94, 4375, 3250, 0x21, },
1692         { 95, 4250, 3125, 0x20, },
1693         { 96, 4125, 3000, 0x1f, },
1694         { 97, 4125, 3000, 0x1e, },
1695         { 98, 4125, 3000, 0x1d, },
1696         { 99, 4125, 3000, 0x1c, },
1697         { 100, 4125, 3000, 0x1b, },
1698         { 101, 4125, 3000, 0x1a, },
1699         { 102, 4125, 3000, 0x19, },
1700         { 103, 4125, 3000, 0x18, },
1701         { 104, 4125, 3000, 0x17, },
1702         { 105, 4125, 3000, 0x16, },
1703         { 106, 4125, 3000, 0x15, },
1704         { 107, 4125, 3000, 0x14, },
1705         { 108, 4125, 3000, 0x13, },
1706         { 109, 4125, 3000, 0x12, },
1707         { 110, 4125, 3000, 0x11, },
1708         { 111, 4125, 3000, 0x10, },
1709         { 112, 4125, 3000, 0x0f, },
1710         { 113, 4125, 3000, 0x0e, },
1711         { 114, 4125, 3000, 0x0d, },
1712         { 115, 4125, 3000, 0x0c, },
1713         { 116, 4125, 3000, 0x0b, },
1714         { 117, 4125, 3000, 0x0a, },
1715         { 118, 4125, 3000, 0x09, },
1716         { 119, 4125, 3000, 0x08, },
1717         { 120, 1125, 0, 0x07, },
1718         { 121, 1000, 0, 0x06, },
1719         { 122, 875, 0, 0x05, },
1720         { 123, 750, 0, 0x04, },
1721         { 124, 625, 0, 0x03, },
1722         { 125, 500, 0, 0x02, },
1723         { 126, 375, 0, 0x01, },
1724         { 127, 0, 0, 0x00, },
1725 };
1726
1727 struct cparams {
1728         int i;
1729         int t;
1730         int m;
1731         int c;
1732 };
1733
1734 static struct cparams cparams[] = {
1735         { 1, 1333, 301, 28664 },
1736         { 1, 1066, 294, 24460 },
1737         { 1, 800, 294, 25192 },
1738         { 0, 1333, 276, 27605 },
1739         { 0, 1066, 276, 27605 },
1740         { 0, 800, 231, 23784 },
1741 };
1742
1743 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
1744 {
1745         u64 total_count, diff, ret;
1746         u32 count1, count2, count3, m = 0, c = 0;
1747         unsigned long now = jiffies_to_msecs(jiffies), diff1;
1748         int i;
1749
1750         diff1 = now - dev_priv->last_time1;
1751
1752         count1 = I915_READ(DMIEC);
1753         count2 = I915_READ(DDREC);
1754         count3 = I915_READ(CSIEC);
1755
1756         total_count = count1 + count2 + count3;
1757
1758         /* FIXME: handle per-counter overflow */
1759         if (total_count < dev_priv->last_count1) {
1760                 diff = ~0UL - dev_priv->last_count1;
1761                 diff += total_count;
1762         } else {
1763                 diff = total_count - dev_priv->last_count1;
1764         }
1765
1766         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
1767                 if (cparams[i].i == dev_priv->c_m &&
1768                     cparams[i].t == dev_priv->r_t) {
1769                         m = cparams[i].m;
1770                         c = cparams[i].c;
1771                         break;
1772                 }
1773         }
1774
1775         div_u64(diff, diff1);
1776         ret = ((m * diff) + c);
1777         div_u64(ret, 10);
1778
1779         dev_priv->last_count1 = total_count;
1780         dev_priv->last_time1 = now;
1781
1782         return ret;
1783 }
1784
1785 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
1786 {
1787         unsigned long m, x, b;
1788         u32 tsfs;
1789
1790         tsfs = I915_READ(TSFS);
1791
1792         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
1793         x = I915_READ8(TR1);
1794
1795         b = tsfs & TSFS_INTR_MASK;
1796
1797         return ((m * x) / 127) - b;
1798 }
1799
1800 static unsigned long pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
1801 {
1802         unsigned long val = 0;
1803         int i;
1804
1805         for (i = 0; i < ARRAY_SIZE(v_table); i++) {
1806                 if (v_table[i].pvid == pxvid) {
1807                         if (IS_MOBILE(dev_priv->dev))
1808                                 val = v_table[i].vm;
1809                         else
1810                                 val = v_table[i].vd;
1811                 }
1812         }
1813
1814         return val;
1815 }
1816
1817 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
1818 {
1819         struct timespec now, diff1;
1820         u64 diff;
1821         unsigned long diffms;
1822         u32 count;
1823
1824         getrawmonotonic(&now);
1825         diff1 = timespec_sub(now, dev_priv->last_time2);
1826
1827         /* Don't divide by 0 */
1828         diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
1829         if (!diffms)
1830                 return;
1831
1832         count = I915_READ(GFXEC);
1833
1834         if (count < dev_priv->last_count2) {
1835                 diff = ~0UL - dev_priv->last_count2;
1836                 diff += count;
1837         } else {
1838                 diff = count - dev_priv->last_count2;
1839         }
1840
1841         dev_priv->last_count2 = count;
1842         dev_priv->last_time2 = now;
1843
1844         /* More magic constants... */
1845         diff = diff * 1181;
1846         div_u64(diff, diffms * 10);
1847         dev_priv->gfx_power = diff;
1848 }
1849
1850 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
1851 {
1852         unsigned long t, corr, state1, corr2, state2;
1853         u32 pxvid, ext_v;
1854
1855         pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->cur_delay * 4));
1856         pxvid = (pxvid >> 24) & 0x7f;
1857         ext_v = pvid_to_extvid(dev_priv, pxvid);
1858
1859         state1 = ext_v;
1860
1861         t = i915_mch_val(dev_priv);
1862
1863         /* Revel in the empirically derived constants */
1864
1865         /* Correction factor in 1/100000 units */
1866         if (t > 80)
1867                 corr = ((t * 2349) + 135940);
1868         else if (t >= 50)
1869                 corr = ((t * 964) + 29317);
1870         else /* < 50 */
1871                 corr = ((t * 301) + 1004);
1872
1873         corr = corr * ((150142 * state1) / 10000 - 78642);
1874         corr /= 100000;
1875         corr2 = (corr * dev_priv->corr);
1876
1877         state2 = (corr2 * state1) / 10000;
1878         state2 /= 100; /* convert to mW */
1879
1880         i915_update_gfx_val(dev_priv);
1881
1882         return dev_priv->gfx_power + state2;
1883 }
1884
1885 /* Global for IPS driver to get at the current i915 device */
1886 static struct drm_i915_private *i915_mch_dev;
1887 /*
1888  * Lock protecting IPS related data structures
1889  *   - i915_mch_dev
1890  *   - dev_priv->max_delay
1891  *   - dev_priv->min_delay
1892  *   - dev_priv->fmax
1893  *   - dev_priv->gpu_busy
1894  */
1895 DEFINE_SPINLOCK(mchdev_lock);
1896
1897 /**
1898  * i915_read_mch_val - return value for IPS use
1899  *
1900  * Calculate and return a value for the IPS driver to use when deciding whether
1901  * we have thermal and power headroom to increase CPU or GPU power budget.
1902  */
1903 unsigned long i915_read_mch_val(void)
1904 {
1905         struct drm_i915_private *dev_priv;
1906         unsigned long chipset_val, graphics_val, ret = 0;
1907
1908         spin_lock(&mchdev_lock);
1909         if (!i915_mch_dev)
1910                 goto out_unlock;
1911         dev_priv = i915_mch_dev;
1912
1913         chipset_val = i915_chipset_val(dev_priv);
1914         graphics_val = i915_gfx_val(dev_priv);
1915
1916         ret = chipset_val + graphics_val;
1917
1918 out_unlock:
1919         spin_unlock(&mchdev_lock);
1920
1921         return ret;
1922 }
1923 EXPORT_SYMBOL_GPL(i915_read_mch_val);
1924
1925 /**
1926  * i915_gpu_raise - raise GPU frequency limit
1927  *
1928  * Raise the limit; IPS indicates we have thermal headroom.
1929  */
1930 bool i915_gpu_raise(void)
1931 {
1932         struct drm_i915_private *dev_priv;
1933         bool ret = true;
1934
1935         spin_lock(&mchdev_lock);
1936         if (!i915_mch_dev) {
1937                 ret = false;
1938                 goto out_unlock;
1939         }
1940         dev_priv = i915_mch_dev;
1941
1942         if (dev_priv->max_delay > dev_priv->fmax)
1943                 dev_priv->max_delay--;
1944
1945 out_unlock:
1946         spin_unlock(&mchdev_lock);
1947
1948         return ret;
1949 }
1950 EXPORT_SYMBOL_GPL(i915_gpu_raise);
1951
1952 /**
1953  * i915_gpu_lower - lower GPU frequency limit
1954  *
1955  * IPS indicates we're close to a thermal limit, so throttle back the GPU
1956  * frequency maximum.
1957  */
1958 bool i915_gpu_lower(void)
1959 {
1960         struct drm_i915_private *dev_priv;
1961         bool ret = true;
1962
1963         spin_lock(&mchdev_lock);
1964         if (!i915_mch_dev) {
1965                 ret = false;
1966                 goto out_unlock;
1967         }
1968         dev_priv = i915_mch_dev;
1969
1970         if (dev_priv->max_delay < dev_priv->min_delay)
1971                 dev_priv->max_delay++;
1972
1973 out_unlock:
1974         spin_unlock(&mchdev_lock);
1975
1976         return ret;
1977 }
1978 EXPORT_SYMBOL_GPL(i915_gpu_lower);
1979
1980 /**
1981  * i915_gpu_busy - indicate GPU business to IPS
1982  *
1983  * Tell the IPS driver whether or not the GPU is busy.
1984  */
1985 bool i915_gpu_busy(void)
1986 {
1987         struct drm_i915_private *dev_priv;
1988         bool ret = false;
1989
1990         spin_lock(&mchdev_lock);
1991         if (!i915_mch_dev)
1992                 goto out_unlock;
1993         dev_priv = i915_mch_dev;
1994
1995         ret = dev_priv->busy;
1996
1997 out_unlock:
1998         spin_unlock(&mchdev_lock);
1999
2000         return ret;
2001 }
2002 EXPORT_SYMBOL_GPL(i915_gpu_busy);
2003
2004 /**
2005  * i915_gpu_turbo_disable - disable graphics turbo
2006  *
2007  * Disable graphics turbo by resetting the max frequency and setting the
2008  * current frequency to the default.
2009  */
2010 bool i915_gpu_turbo_disable(void)
2011 {
2012         struct drm_i915_private *dev_priv;
2013         bool ret = true;
2014
2015         spin_lock(&mchdev_lock);
2016         if (!i915_mch_dev) {
2017                 ret = false;
2018                 goto out_unlock;
2019         }
2020         dev_priv = i915_mch_dev;
2021
2022         dev_priv->max_delay = dev_priv->fstart;
2023
2024         if (!ironlake_set_drps(dev_priv->dev, dev_priv->fstart))
2025                 ret = false;
2026
2027 out_unlock:
2028         spin_unlock(&mchdev_lock);
2029
2030         return ret;
2031 }
2032 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
2033
2034 /**
2035  * i915_driver_load - setup chip and create an initial config
2036  * @dev: DRM device
2037  * @flags: startup flags
2038  *
2039  * The driver load routine has to do several things:
2040  *   - drive output discovery via intel_modeset_init()
2041  *   - initialize the memory manager
2042  *   - allocate initial config memory
2043  *   - setup the DRM framebuffer with the allocated memory
2044  */
2045 int i915_driver_load(struct drm_device *dev, unsigned long flags)
2046 {
2047         struct drm_i915_private *dev_priv;
2048         resource_size_t base, size;
2049         int ret = 0, mmio_bar;
2050         uint32_t agp_size, prealloc_size, prealloc_start;
2051         /* i915 has 4 more counters */
2052         dev->counters += 4;
2053         dev->types[6] = _DRM_STAT_IRQ;
2054         dev->types[7] = _DRM_STAT_PRIMARY;
2055         dev->types[8] = _DRM_STAT_SECONDARY;
2056         dev->types[9] = _DRM_STAT_DMA;
2057
2058         dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
2059         if (dev_priv == NULL)
2060                 return -ENOMEM;
2061
2062         dev->dev_private = (void *)dev_priv;
2063         dev_priv->dev = dev;
2064         dev_priv->info = (struct intel_device_info *) flags;
2065
2066         /* Add register map (needed for suspend/resume) */
2067         mmio_bar = IS_I9XX(dev) ? 0 : 1;
2068         base = drm_get_resource_start(dev, mmio_bar);
2069         size = drm_get_resource_len(dev, mmio_bar);
2070
2071         if (i915_get_bridge_dev(dev)) {
2072                 ret = -EIO;
2073                 goto free_priv;
2074         }
2075
2076         dev_priv->regs = ioremap(base, size);
2077         if (!dev_priv->regs) {
2078                 DRM_ERROR("failed to map registers\n");
2079                 ret = -EIO;
2080                 goto put_bridge;
2081         }
2082
2083         dev_priv->mm.gtt_mapping =
2084                 io_mapping_create_wc(dev->agp->base,
2085                                      dev->agp->agp_info.aper_size * 1024*1024);
2086         if (dev_priv->mm.gtt_mapping == NULL) {
2087                 ret = -EIO;
2088                 goto out_rmmap;
2089         }
2090
2091         /* Set up a WC MTRR for non-PAT systems.  This is more common than
2092          * one would think, because the kernel disables PAT on first
2093          * generation Core chips because WC PAT gets overridden by a UC
2094          * MTRR if present.  Even if a UC MTRR isn't present.
2095          */
2096         dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base,
2097                                          dev->agp->agp_info.aper_size *
2098                                          1024 * 1024,
2099                                          MTRR_TYPE_WRCOMB, 1);
2100         if (dev_priv->mm.gtt_mtrr < 0) {
2101                 DRM_INFO("MTRR allocation failed.  Graphics "
2102                          "performance may suffer.\n");
2103         }
2104
2105         ret = i915_probe_agp(dev, &agp_size, &prealloc_size, &prealloc_start);
2106         if (ret)
2107                 goto out_iomapfree;
2108
2109         if (prealloc_size > intel_max_stolen) {
2110                 DRM_INFO("detected %dM stolen memory, trimming to %dM\n",
2111                          prealloc_size >> 20, intel_max_stolen >> 20);
2112                 prealloc_size = intel_max_stolen;
2113         }
2114
2115         dev_priv->wq = create_singlethread_workqueue("i915");
2116         if (dev_priv->wq == NULL) {
2117                 DRM_ERROR("Failed to create our workqueue.\n");
2118                 ret = -ENOMEM;
2119                 goto out_iomapfree;
2120         }
2121
2122         /* enable GEM by default */
2123         dev_priv->has_gem = 1;
2124
2125         if (prealloc_size > agp_size * 3 / 4) {
2126                 DRM_ERROR("Detected broken video BIOS with %d/%dkB of video "
2127                           "memory stolen.\n",
2128                           prealloc_size / 1024, agp_size / 1024);
2129                 DRM_ERROR("Disabling GEM. (try reducing stolen memory or "
2130                           "updating the BIOS to fix).\n");
2131                 dev_priv->has_gem = 0;
2132         }
2133
2134         if (dev_priv->has_gem == 0 &&
2135             drm_core_check_feature(dev, DRIVER_MODESET)) {
2136                 DRM_ERROR("kernel modesetting requires GEM, disabling driver.\n");
2137                 ret = -ENODEV;
2138                 goto out_iomapfree;
2139         }
2140
2141         dev->driver->get_vblank_counter = i915_get_vblank_counter;
2142         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
2143         if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) {
2144                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
2145                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
2146         }
2147
2148         /* Try to make sure MCHBAR is enabled before poking at it */
2149         intel_setup_mchbar(dev);
2150
2151         i915_gem_load(dev);
2152
2153         /* Init HWS */
2154         if (!I915_NEED_GFX_HWS(dev)) {
2155                 ret = i915_init_phys_hws(dev);
2156                 if (ret != 0)
2157                         goto out_workqueue_free;
2158         }
2159
2160         if (IS_PINEVIEW(dev))
2161                 i915_pineview_get_mem_freq(dev);
2162         else if (IS_IRONLAKE(dev))
2163                 i915_ironlake_get_mem_freq(dev);
2164
2165         /* On the 945G/GM, the chipset reports the MSI capability on the
2166          * integrated graphics even though the support isn't actually there
2167          * according to the published specs.  It doesn't appear to function
2168          * correctly in testing on 945G.
2169          * This may be a side effect of MSI having been made available for PEG
2170          * and the registers being closely associated.
2171          *
2172          * According to chipset errata, on the 965GM, MSI interrupts may
2173          * be lost or delayed, but we use them anyways to avoid
2174          * stuck interrupts on some machines.
2175          */
2176         if (!IS_I945G(dev) && !IS_I945GM(dev))
2177                 pci_enable_msi(dev->pdev);
2178
2179         spin_lock_init(&dev_priv->user_irq_lock);
2180         spin_lock_init(&dev_priv->error_lock);
2181         dev_priv->trace_irq_seqno = 0;
2182
2183         ret = drm_vblank_init(dev, I915_NUM_PIPE);
2184
2185         if (ret) {
2186                 (void) i915_driver_unload(dev);
2187                 return ret;
2188         }
2189
2190         /* Start out suspended */
2191         dev_priv->mm.suspended = 1;
2192
2193         intel_detect_pch(dev);
2194
2195         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2196                 ret = i915_load_modeset_init(dev, prealloc_start,
2197                                              prealloc_size, agp_size);
2198                 if (ret < 0) {
2199                         DRM_ERROR("failed to init modeset\n");
2200                         goto out_workqueue_free;
2201                 }
2202         }
2203
2204         /* Must be done after probing outputs */
2205         intel_opregion_init(dev, 0);
2206
2207         setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
2208                     (unsigned long) dev);
2209
2210         spin_lock(&mchdev_lock);
2211         i915_mch_dev = dev_priv;
2212         dev_priv->mchdev_lock = &mchdev_lock;
2213         spin_unlock(&mchdev_lock);
2214
2215         return 0;
2216
2217 out_workqueue_free:
2218         destroy_workqueue(dev_priv->wq);
2219 out_iomapfree:
2220         io_mapping_free(dev_priv->mm.gtt_mapping);
2221 out_rmmap:
2222         iounmap(dev_priv->regs);
2223 put_bridge:
2224         pci_dev_put(dev_priv->bridge_dev);
2225 free_priv:
2226         kfree(dev_priv);
2227         return ret;
2228 }
2229
2230 int i915_driver_unload(struct drm_device *dev)
2231 {
2232         struct drm_i915_private *dev_priv = dev->dev_private;
2233
2234         i915_destroy_error_state(dev);
2235
2236         spin_lock(&mchdev_lock);
2237         i915_mch_dev = NULL;
2238         spin_unlock(&mchdev_lock);
2239
2240         destroy_workqueue(dev_priv->wq);
2241         del_timer_sync(&dev_priv->hangcheck_timer);
2242
2243         io_mapping_free(dev_priv->mm.gtt_mapping);
2244         if (dev_priv->mm.gtt_mtrr >= 0) {
2245                 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
2246                          dev->agp->agp_info.aper_size * 1024 * 1024);
2247                 dev_priv->mm.gtt_mtrr = -1;
2248         }
2249
2250         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2251                 intel_modeset_cleanup(dev);
2252
2253                 /*
2254                  * free the memory space allocated for the child device
2255                  * config parsed from VBT
2256                  */
2257                 if (dev_priv->child_dev && dev_priv->child_dev_num) {
2258                         kfree(dev_priv->child_dev);
2259                         dev_priv->child_dev = NULL;
2260                         dev_priv->child_dev_num = 0;
2261                 }
2262                 drm_irq_uninstall(dev);
2263                 vga_switcheroo_unregister_client(dev->pdev);
2264                 vga_client_register(dev->pdev, NULL, NULL, NULL);
2265         }
2266
2267         if (dev->pdev->msi_enabled)
2268                 pci_disable_msi(dev->pdev);
2269
2270         if (dev_priv->regs != NULL)
2271                 iounmap(dev_priv->regs);
2272
2273         intel_opregion_free(dev, 0);
2274
2275         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2276                 i915_gem_free_all_phys_object(dev);
2277
2278                 mutex_lock(&dev->struct_mutex);
2279                 i915_gem_cleanup_ringbuffer(dev);
2280                 mutex_unlock(&dev->struct_mutex);
2281                 if (I915_HAS_FBC(dev) && i915_powersave)
2282                         i915_cleanup_compression(dev);
2283                 drm_mm_takedown(&dev_priv->vram);
2284                 i915_gem_lastclose(dev);
2285
2286                 intel_cleanup_overlay(dev);
2287         }
2288
2289         intel_teardown_mchbar(dev);
2290
2291         pci_dev_put(dev_priv->bridge_dev);
2292         kfree(dev->dev_private);
2293
2294         return 0;
2295 }
2296
2297 int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
2298 {
2299         struct drm_i915_file_private *i915_file_priv;
2300
2301         DRM_DEBUG_DRIVER("\n");
2302         i915_file_priv = (struct drm_i915_file_private *)
2303             kmalloc(sizeof(*i915_file_priv), GFP_KERNEL);
2304
2305         if (!i915_file_priv)
2306                 return -ENOMEM;
2307
2308         file_priv->driver_priv = i915_file_priv;
2309
2310         INIT_LIST_HEAD(&i915_file_priv->mm.request_list);
2311
2312         return 0;
2313 }
2314
2315 /**
2316  * i915_driver_lastclose - clean up after all DRM clients have exited
2317  * @dev: DRM device
2318  *
2319  * Take care of cleaning up after all DRM clients have exited.  In the
2320  * mode setting case, we want to restore the kernel's initial mode (just
2321  * in case the last client left us in a bad state).
2322  *
2323  * Additionally, in the non-mode setting case, we'll tear down the AGP
2324  * and DMA structures, since the kernel won't be using them, and clea
2325  * up any GEM state.
2326  */
2327 void i915_driver_lastclose(struct drm_device * dev)
2328 {
2329         drm_i915_private_t *dev_priv = dev->dev_private;
2330
2331         if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
2332                 drm_fb_helper_restore();
2333                 vga_switcheroo_process_delayed_switch();
2334                 return;
2335         }
2336
2337         i915_gem_lastclose(dev);
2338
2339         if (dev_priv->agp_heap)
2340                 i915_mem_takedown(&(dev_priv->agp_heap));
2341
2342         i915_dma_cleanup(dev);
2343 }
2344
2345 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
2346 {
2347         drm_i915_private_t *dev_priv = dev->dev_private;
2348         i915_gem_release(dev, file_priv);
2349         if (!drm_core_check_feature(dev, DRIVER_MODESET))
2350                 i915_mem_release(dev, file_priv, dev_priv->agp_heap);
2351 }
2352
2353 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
2354 {
2355         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
2356
2357         kfree(i915_file_priv);
2358 }
2359
2360 struct drm_ioctl_desc i915_ioctls[] = {
2361         DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2362         DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
2363         DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
2364         DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
2365         DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
2366         DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
2367         DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
2368         DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2369         DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH),
2370         DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH),
2371         DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2372         DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
2373         DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP,  i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
2374         DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE,  i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
2375         DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH ),
2376         DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
2377         DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2378         DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2379         DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
2380         DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
2381         DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2382         DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2383         DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
2384         DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
2385         DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2386         DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2387         DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
2388         DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
2389         DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
2390         DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
2391         DRM_IOCTL_DEF(DRM_I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
2392         DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
2393         DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
2394         DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
2395         DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
2396         DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
2397         DRM_IOCTL_DEF(DRM_I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
2398         DRM_IOCTL_DEF(DRM_I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
2399         DRM_IOCTL_DEF(DRM_I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2400         DRM_IOCTL_DEF(DRM_I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2401 };
2402
2403 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
2404
2405 /**
2406  * Determine if the device really is AGP or not.
2407  *
2408  * All Intel graphics chipsets are treated as AGP, even if they are really
2409  * PCI-e.
2410  *
2411  * \param dev   The device to be tested.
2412  *
2413  * \returns
2414  * A value of 1 is always retured to indictate every i9x5 is AGP.
2415  */
2416 int i915_driver_device_is_agp(struct drm_device * dev)
2417 {
2418         return 1;
2419 }