drivers/gpu/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "drm_crtc_helper.h"
  32 #include "drm_fb_helper.h"
  33 #include "intel_drv.h"
  34 #include "i915_drm.h"
  35 #include "i915_drv.h"
  36 #include "i915_trace.h"
  37 #include <linux/pci.h>
  38 #include <linux/vgaarb.h>
  39 #include <linux/acpi.h>
  40 #include <linux/pnp.h>
  41 #include <linux/vga_switcheroo.h>
  42 #include <linux/slab.h>
  43 #include <acpi/video.h>
  44
  45 /**
  46  * Sets up the hardware status page for devices that need a physical address
  47  * in the register.
  48  */
  49 static int i915_init_phys_hws(struct drm_device *dev)
  50 {
  51         drm_i915_private_t *dev_priv = dev->dev_private;
  52         struct intel_ring_buffer *ring = LP_RING(dev_priv);
  53
  54         /* Program Hardware Status Page */
  55         dev_priv->status_page_dmah =
  56                 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE);
  57
  58         if (!dev_priv->status_page_dmah) {
  59                 DRM_ERROR("Can not allocate hardware status page\n");
  60                 return -ENOMEM;
  61         }
  62         ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
  63         dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
  64
  65         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
  66
  67         if (INTEL_INFO(dev)->gen >= 4)
  68                 dev_priv->dma_status_page |= (dev_priv->dma_status_page >> 28) &
  69                                              0xf0;
  70
  71         I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
  72         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
  73         return 0;
  74 }
  75
  76 /**
  77  * Frees the hardware status page, whether it's a physical address or a virtual
  78  * address set up by the X Server.
  79  */
  80 static void i915_free_hws(struct drm_device *dev)
  81 {
  82         drm_i915_private_t *dev_priv = dev->dev_private;
  83         struct intel_ring_buffer *ring = LP_RING(dev_priv);
  84
  85         if (dev_priv->status_page_dmah) {
  86                 drm_pci_free(dev, dev_priv->status_page_dmah);
  87                 dev_priv->status_page_dmah = NULL;
  88         }
  89
  90         if (ring->status_page.gfx_addr) {
  91                 ring->status_page.gfx_addr = 0;
  92                 drm_core_ioremapfree(&dev_priv->hws_map, dev);
  93         }
  94
  95         /* Need to rewrite hardware status page */
  96         I915_WRITE(HWS_PGA, 0x1ffff000);
  97 }
  98
  99 void i915_kernel_lost_context(struct drm_device * dev)
 100 {
 101         drm_i915_private_t *dev_priv = dev->dev_private;
 102         struct drm_i915_master_private *master_priv;
 103         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 104
 105         /*
 106          * We should never lose context on the ring with modesetting
 107          * as we don't expose it to userspace
 108          */
 109         if (drm_core_check_feature(dev, DRIVER_MODESET))
 110                 return;
 111
 112         ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
 113         ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 114         ring->space = ring->head - (ring->tail + 8);
 115         if (ring->space < 0)
 116                 ring->space += ring->size;
 117
 118         if (!dev->primary->master)
 119                 return;
 120
 121         master_priv = dev->primary->master->driver_priv;
 122         if (ring->head == ring->tail && master_priv->sarea_priv)
 123                 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
 124 }
 125
 126 static int i915_dma_cleanup(struct drm_device * dev)
 127 {
 128         drm_i915_private_t *dev_priv = dev->dev_private;
 129         int i;
 130
 131         /* Make sure interrupts are disabled here because the uninstall ioctl
 132          * may not have been called from userspace and after dev_private
 133          * is freed, it's too late.
 134          */
 135         if (dev->irq_enabled)
 136                 drm_irq_uninstall(dev);
 137
 138         mutex_lock(&dev->struct_mutex);
 139         for (i = 0; i < I915_NUM_RINGS; i++)
 140                 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
 141         mutex_unlock(&dev->struct_mutex);
 142
 143         /* Clear the HWS virtual address at teardown */
 144         if (I915_NEED_GFX_HWS(dev))
 145                 i915_free_hws(dev);
 146
 147         return 0;
 148 }
 149
 150 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
 151 {
 152         drm_i915_private_t *dev_priv = dev->dev_private;
 153         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 154         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 155
 156         master_priv->sarea = drm_getsarea(dev);
 157         if (master_priv->sarea) {
 158                 master_priv->sarea_priv = (drm_i915_sarea_t *)
 159                         ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
 160         } else {
 161                 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
 162         }
 163
 164         if (init->ring_size != 0) {
 165                 if (ring->obj != NULL) {
 166                         i915_dma_cleanup(dev);
 167                         DRM_ERROR("Client tried to initialize ringbuffer in "
 168                                   "GEM mode\n");
 169                         return -EINVAL;
 170                 }
 171
 172                 ring->size = init->ring_size;
 173
 174                 ring->map.offset = init->ring_start;
 175                 ring->map.size = init->ring_size;
 176                 ring->map.type = 0;
 177                 ring->map.flags = 0;
 178                 ring->map.mtrr = 0;
 179
 180                 drm_core_ioremap_wc(&ring->map, dev);
 181
 182                 if (ring->map.handle == NULL) {
 183                         i915_dma_cleanup(dev);
 184                         DRM_ERROR("can not ioremap virtual address for"
 185                                   " ring buffer\n");
 186                         return -ENOMEM;
 187                 }
 188         }
 189
 190         ring->virtual_start = ring->map.handle;
 191
 192         dev_priv->cpp = init->cpp;
 193         dev_priv->back_offset = init->back_offset;
 194         dev_priv->front_offset = init->front_offset;
 195         dev_priv->current_page = 0;
 196         if (master_priv->sarea_priv)
 197                 master_priv->sarea_priv->pf_current_page = 0;
 198
 199         /* Allow hardware batchbuffers unless told otherwise.
 200          */
 201         dev_priv->allow_batchbuffer = 1;
 202
 203         return 0;
 204 }
 205
 206 static int i915_dma_resume(struct drm_device * dev)
 207 {
 208         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 209         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 210
 211         DRM_DEBUG_DRIVER("%s\n", __func__);
 212
 213         if (ring->map.handle == NULL) {
 214                 DRM_ERROR("can not ioremap virtual address for"
 215                           " ring buffer\n");
 216                 return -ENOMEM;
 217         }
 218
 219         /* Program Hardware Status Page */
 220         if (!ring->status_page.page_addr) {
 221                 DRM_ERROR("Can not find hardware status page\n");
 222                 return -EINVAL;
 223         }
 224         DRM_DEBUG_DRIVER("hw status page @ %p\n",
 225                                 ring->status_page.page_addr);
 226         if (ring->status_page.gfx_addr != 0)
 227                 intel_ring_setup_status_page(ring);
 228         else
 229                 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
 230
 231         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
 232
 233         return 0;
 234 }
 235
 236 static int i915_dma_init(struct drm_device *dev, void *data,
 237                          struct drm_file *file_priv)
 238 {
 239         drm_i915_init_t *init = data;
 240         int retcode = 0;
 241
 242         switch (init->func) {
 243         case I915_INIT_DMA:
 244                 retcode = i915_initialize(dev, init);
 245                 break;
 246         case I915_CLEANUP_DMA:
 247                 retcode = i915_dma_cleanup(dev);
 248                 break;
 249         case I915_RESUME_DMA:
 250                 retcode = i915_dma_resume(dev);
 251                 break;
 252         default:
 253                 retcode = -EINVAL;
 254                 break;
 255         }
 256
 257         return retcode;
 258 }
 259
 260 /* Implement basically the same security restrictions as hardware does
 261  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 262  *
 263  * Most of the calculations below involve calculating the size of a
 264  * particular instruction.  It's important to get the size right as
 265  * that tells us where the next instruction to check is.  Any illegal
 266  * instruction detected will be given a size of zero, which is a
 267  * signal to abort the rest of the buffer.
 268  */
 269 static int validate_cmd(int cmd)
 270 {
 271         switch (((cmd >> 29) & 0x7)) {
 272         case 0x0:
 273                 switch ((cmd >> 23) & 0x3f) {
 274                 case 0x0:
 275                         return 1;       /* MI_NOOP */
 276                 case 0x4:
 277                         return 1;       /* MI_FLUSH */
 278                 default:
 279                         return 0;       /* disallow everything else */
 280                 }
 281                 break;
 282         case 0x1:
 283                 return 0;       /* reserved */
 284         case 0x2:
 285                 return (cmd & 0xff) + 2;        /* 2d commands */
 286         case 0x3:
 287                 if (((cmd >> 24) & 0x1f) <= 0x18)
 288                         return 1;
 289
 290                 switch ((cmd >> 24) & 0x1f) {
 291                 case 0x1c:
 292                         return 1;
 293                 case 0x1d:
 294                         switch ((cmd >> 16) & 0xff) {
 295                         case 0x3:
 296                                 return (cmd & 0x1f) + 2;
 297                         case 0x4:
 298                                 return (cmd & 0xf) + 2;
 299                         default:
 300                                 return (cmd & 0xffff) + 2;
 301                         }
 302                 case 0x1e:
 303                         if (cmd & (1 << 23))
 304                                 return (cmd & 0xffff) + 1;
 305                         else
 306                                 return 1;
 307                 case 0x1f:
 308                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 309                                 return (cmd & 0x1ffff) + 2;
 310                         else if (cmd & (1 << 17))       /* indirect random */
 311                                 if ((cmd & 0xffff) == 0)
 312                                         return 0;       /* unknown length, too hard */
 313                                 else
 314                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 315                         else
 316                                 return 2;       /* indirect sequential */
 317                 default:
 318                         return 0;
 319                 }
 320         default:
 321                 return 0;
 322         }
 323
 324         return 0;
 325 }
 326
 327 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
 328 {
 329         drm_i915_private_t *dev_priv = dev->dev_private;
 330         int i, ret;
 331
 332         if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
 333                 return -EINVAL;
 334
 335         for (i = 0; i < dwords;) {
 336                 int sz = validate_cmd(buffer[i]);
 337                 if (sz == 0 || i + sz > dwords)
 338                         return -EINVAL;
 339                 i += sz;
 340         }
 341
 342         ret = BEGIN_LP_RING((dwords+1)&~1);
 343         if (ret)
 344                 return ret;
 345
 346         for (i = 0; i < dwords; i++)
 347                 OUT_RING(buffer[i]);
 348         if (dwords & 1)
 349                 OUT_RING(0);
 350
 351         ADVANCE_LP_RING();
 352
 353         return 0;
 354 }
 355
 356 int
 357 i915_emit_box(struct drm_device *dev,
 358               struct drm_clip_rect *box,
 359               int DR1, int DR4)
 360 {
 361         struct drm_i915_private *dev_priv = dev->dev_private;
 362         int ret;
 363
 364         if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
 365             box->y2 <= 0 || box->x2 <= 0) {
 366                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 367                           box->x1, box->y1, box->x2, box->y2);
 368                 return -EINVAL;
 369         }
 370
 371         if (INTEL_INFO(dev)->gen >= 4) {
 372                 ret = BEGIN_LP_RING(4);
 373                 if (ret)
 374                         return ret;
 375
 376                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 377                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 378                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 379                 OUT_RING(DR4);
 380         } else {
 381                 ret = BEGIN_LP_RING(6);
 382                 if (ret)
 383                         return ret;
 384
 385                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 386                 OUT_RING(DR1);
 387                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 388                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 389                 OUT_RING(DR4);
 390                 OUT_RING(0);
 391         }
 392         ADVANCE_LP_RING();
 393
 394         return 0;
 395 }
 396
 397 /* XXX: Emitting the counter should really be moved to part of the IRQ
 398  * emit. For now, do it in both places:
 399  */
 400
 401 static void i915_emit_breadcrumb(struct drm_device *dev)
 402 {
 403         drm_i915_private_t *dev_priv = dev->dev_private;
 404         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 405
 406         dev_priv->counter++;
 407         if (dev_priv->counter > 0x7FFFFFFFUL)
 408                 dev_priv->counter = 0;
 409         if (master_priv->sarea_priv)
 410                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
 411
 412         if (BEGIN_LP_RING(4) == 0) {
 413                 OUT_RING(MI_STORE_DWORD_INDEX);
 414                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 415                 OUT_RING(dev_priv->counter);
 416                 OUT_RING(0);
 417                 ADVANCE_LP_RING();
 418         }
 419 }
 420
 421 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 422                                    drm_i915_cmdbuffer_t *cmd,
 423                                    struct drm_clip_rect *cliprects,
 424                                    void *cmdbuf)
 425 {
 426         int nbox = cmd->num_cliprects;
 427         int i = 0, count, ret;
 428
 429         if (cmd->sz & 0x3) {
 430                 DRM_ERROR("alignment");
 431                 return -EINVAL;
 432         }
 433
 434         i915_kernel_lost_context(dev);
 435
 436         count = nbox ? nbox : 1;
 437
 438         for (i = 0; i < count; i++) {
 439                 if (i < nbox) {
 440                         ret = i915_emit_box(dev, &cliprects[i],
 441                                             cmd->DR1, cmd->DR4);
 442                         if (ret)
 443                                 return ret;
 444                 }
 445
 446                 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
 447                 if (ret)
 448                         return ret;
 449         }
 450
 451         i915_emit_breadcrumb(dev);
 452         return 0;
 453 }
 454
 455 static int i915_dispatch_batchbuffer(struct drm_device * dev,
 456                                      drm_i915_batchbuffer_t * batch,
 457                                      struct drm_clip_rect *cliprects)
 458 {
 459         struct drm_i915_private *dev_priv = dev->dev_private;
 460         int nbox = batch->num_cliprects;
 461         int i, count, ret;
 462
 463         if ((batch->start | batch->used) & 0x7) {
 464                 DRM_ERROR("alignment");
 465                 return -EINVAL;
 466         }
 467
 468         i915_kernel_lost_context(dev);
 469
 470         count = nbox ? nbox : 1;
 471         for (i = 0; i < count; i++) {
 472                 if (i < nbox) {
 473                         ret = i915_emit_box(dev, &cliprects[i],
 474                                             batch->DR1, batch->DR4);
 475                         if (ret)
 476                                 return ret;
 477                 }
 478
 479                 if (!IS_I830(dev) && !IS_845G(dev)) {
 480                         ret = BEGIN_LP_RING(2);
 481                         if (ret)
 482                                 return ret;
 483
 484                         if (INTEL_INFO(dev)->gen >= 4) {
 485                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
 486                                 OUT_RING(batch->start);
 487                         } else {
 488                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 489                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 490                         }
 491                 } else {
 492                         ret = BEGIN_LP_RING(4);
 493                         if (ret)
 494                                 return ret;
 495
 496                         OUT_RING(MI_BATCH_BUFFER);
 497                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 498                         OUT_RING(batch->start + batch->used - 4);
 499                         OUT_RING(0);
 500                 }
 501                 ADVANCE_LP_RING();
 502         }
 503
 504
 505         if (IS_G4X(dev) || IS_GEN5(dev)) {
 506                 if (BEGIN_LP_RING(2) == 0) {
 507                         OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
 508                         OUT_RING(MI_NOOP);
 509                         ADVANCE_LP_RING();
 510                 }
 511         }
 512
 513         i915_emit_breadcrumb(dev);
 514         return 0;
 515 }
 516
 517 static int i915_dispatch_flip(struct drm_device * dev)
 518 {
 519         drm_i915_private_t *dev_priv = dev->dev_private;
 520         struct drm_i915_master_private *master_priv =
 521                 dev->primary->master->driver_priv;
 522         int ret;
 523
 524         if (!master_priv->sarea_priv)
 525                 return -EINVAL;
 526
 527         DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
 528                           __func__,
 529                          dev_priv->current_page,
 530                          master_priv->sarea_priv->pf_current_page);
 531
 532         i915_kernel_lost_context(dev);
 533
 534         ret = BEGIN_LP_RING(10);
 535         if (ret)
 536                 return ret;
 537
 538         OUT_RING(MI_FLUSH | MI_READ_FLUSH);
 539         OUT_RING(0);
 540
 541         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
 542         OUT_RING(0);
 543         if (dev_priv->current_page == 0) {
 544                 OUT_RING(dev_priv->back_offset);
 545                 dev_priv->current_page = 1;
 546         } else {
 547                 OUT_RING(dev_priv->front_offset);
 548                 dev_priv->current_page = 0;
 549         }
 550         OUT_RING(0);
 551
 552         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
 553         OUT_RING(0);
 554
 555         ADVANCE_LP_RING();
 556
 557         master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
 558
 559         if (BEGIN_LP_RING(4) == 0) {
 560                 OUT_RING(MI_STORE_DWORD_INDEX);
 561                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 562                 OUT_RING(dev_priv->counter);
 563                 OUT_RING(0);
 564                 ADVANCE_LP_RING();
 565         }
 566
 567         master_priv->sarea_priv->pf_current_page = dev_priv->current_page;
 568         return 0;
 569 }
 570
 571 static int i915_quiescent(struct drm_device *dev)
 572 {
 573         struct intel_ring_buffer *ring = LP_RING(dev->dev_private);
 574
 575         i915_kernel_lost_context(dev);
 576         return intel_wait_ring_buffer(ring, ring->size - 8);
 577 }
 578
 579 static int i915_flush_ioctl(struct drm_device *dev, void *data,
 580                             struct drm_file *file_priv)
 581 {
 582         int ret;
 583
 584         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 585
 586         mutex_lock(&dev->struct_mutex);
 587         ret = i915_quiescent(dev);
 588         mutex_unlock(&dev->struct_mutex);
 589
 590         return ret;
 591 }
 592
 593 static int i915_batchbuffer(struct drm_device *dev, void *data,
 594                             struct drm_file *file_priv)
 595 {
 596         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 597         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 598         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 599             master_priv->sarea_priv;
 600         drm_i915_batchbuffer_t *batch = data;
 601         int ret;
 602         struct drm_clip_rect *cliprects = NULL;
 603
 604         if (!dev_priv->allow_batchbuffer) {
 605                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 606                 return -EINVAL;
 607         }
 608
 609         DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
 610                         batch->start, batch->used, batch->num_cliprects);
 611
 612         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 613
 614         if (batch->num_cliprects < 0)
 615                 return -EINVAL;
 616
 617         if (batch->num_cliprects) {
 618                 cliprects = kcalloc(batch->num_cliprects,
 619                                     sizeof(struct drm_clip_rect),
 620                                     GFP_KERNEL);
 621                 if (cliprects == NULL)
 622                         return -ENOMEM;
 623
 624                 ret = copy_from_user(cliprects, batch->cliprects,
 625                                      batch->num_cliprects *
 626                                      sizeof(struct drm_clip_rect));
 627                 if (ret != 0) {
 628                         ret = -EFAULT;
 629                         goto fail_free;
 630                 }
 631         }
 632
 633         mutex_lock(&dev->struct_mutex);
 634         ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
 635         mutex_unlock(&dev->struct_mutex);
 636
 637         if (sarea_priv)
 638                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 639
 640 fail_free:
 641         kfree(cliprects);
 642
 643         return ret;
 644 }
 645
 646 static int i915_cmdbuffer(struct drm_device *dev, void *data,
 647                           struct drm_file *file_priv)
 648 {
 649         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 650         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 651         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 652             master_priv->sarea_priv;
 653         drm_i915_cmdbuffer_t *cmdbuf = data;
 654         struct drm_clip_rect *cliprects = NULL;
 655         void *batch_data;
 656         int ret;
 657
 658         DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 659                         cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 660
 661         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 662
 663         if (cmdbuf->num_cliprects < 0)
 664                 return -EINVAL;
 665
 666         batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
 667         if (batch_data == NULL)
 668                 return -ENOMEM;
 669
 670         ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
 671         if (ret != 0) {
 672                 ret = -EFAULT;
 673                 goto fail_batch_free;
 674         }
 675
 676         if (cmdbuf->num_cliprects) {
 677                 cliprects = kcalloc(cmdbuf->num_cliprects,
 678                                     sizeof(struct drm_clip_rect), GFP_KERNEL);
 679                 if (cliprects == NULL) {
 680                         ret = -ENOMEM;
 681                         goto fail_batch_free;
 682                 }
 683
 684                 ret = copy_from_user(cliprects, cmdbuf->cliprects,
 685                                      cmdbuf->num_cliprects *
 686                                      sizeof(struct drm_clip_rect));
 687                 if (ret != 0) {
 688                         ret = -EFAULT;
 689                         goto fail_clip_free;
 690                 }
 691         }
 692
 693         mutex_lock(&dev->struct_mutex);
 694         ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
 695         mutex_unlock(&dev->struct_mutex);
 696         if (ret) {
 697                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 698                 goto fail_clip_free;
 699         }
 700
 701         if (sarea_priv)
 702                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 703
 704 fail_clip_free:
 705         kfree(cliprects);
 706 fail_batch_free:
 707         kfree(batch_data);
 708
 709         return ret;
 710 }
 711
 712 static int i915_flip_bufs(struct drm_device *dev, void *data,
 713                           struct drm_file *file_priv)
 714 {
 715         int ret;
 716
 717         DRM_DEBUG_DRIVER("%s\n", __func__);
 718
 719         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 720
 721         mutex_lock(&dev->struct_mutex);
 722         ret = i915_dispatch_flip(dev);
 723         mutex_unlock(&dev->struct_mutex);
 724
 725         return ret;
 726 }
 727
 728 static int i915_getparam(struct drm_device *dev, void *data,
 729                          struct drm_file *file_priv)
 730 {
 731         drm_i915_private_t *dev_priv = dev->dev_private;
 732         drm_i915_getparam_t *param = data;
 733         int value;
 734
 735         if (!dev_priv) {
 736                 DRM_ERROR("called with no initialization\n");
 737                 return -EINVAL;
 738         }
 739
 740         switch (param->param) {
 741         case I915_PARAM_IRQ_ACTIVE:
 742                 value = dev->pdev->irq ? 1 : 0;
 743                 break;
 744         case I915_PARAM_ALLOW_BATCHBUFFER:
 745                 value = dev_priv->allow_batchbuffer ? 1 : 0;
 746                 break;
 747         case I915_PARAM_LAST_DISPATCH:
 748                 value = READ_BREADCRUMB(dev_priv);
 749                 break;
 750         case I915_PARAM_CHIPSET_ID:
 751                 value = dev->pci_device;
 752                 break;
 753         case I915_PARAM_HAS_GEM:
 754                 value = dev_priv->has_gem;
 755                 break;
 756         case I915_PARAM_NUM_FENCES_AVAIL:
 757                 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
 758                 break;
 759         case I915_PARAM_HAS_OVERLAY:
 760                 value = dev_priv->overlay ? 1 : 0;
 761                 break;
 762         case I915_PARAM_HAS_PAGEFLIPPING:
 763                 value = 1;
 764                 break;
 765         case I915_PARAM_HAS_EXECBUF2:
 766                 /* depends on GEM */
 767                 value = dev_priv->has_gem;
 768                 break;
 769         case I915_PARAM_HAS_BSD:
 770                 value = HAS_BSD(dev);
 771                 break;
 772         case I915_PARAM_HAS_BLT:
 773                 value = HAS_BLT(dev);
 774                 break;
 775         case I915_PARAM_HAS_RELAXED_FENCING:
 776                 value = 1;
 777                 break;
 778         case I915_PARAM_HAS_COHERENT_RINGS:
 779                 value = 1;
 780                 break;
 781         case I915_PARAM_HAS_EXEC_CONSTANTS:
 782                 value = INTEL_INFO(dev)->gen >= 4;
 783                 break;
 784         default:
 785                 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
 786                                  param->param);
 787                 return -EINVAL;
 788         }
 789
 790         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
 791                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 792                 return -EFAULT;
 793         }
 794
 795         return 0;
 796 }
 797
 798 static int i915_setparam(struct drm_device *dev, void *data,
 799                          struct drm_file *file_priv)
 800 {
 801         drm_i915_private_t *dev_priv = dev->dev_private;
 802         drm_i915_setparam_t *param = data;
 803
 804         if (!dev_priv) {
 805                 DRM_ERROR("called with no initialization\n");
 806                 return -EINVAL;
 807         }
 808
 809         switch (param->param) {
 810         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
 811                 break;
 812         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
 813                 dev_priv->tex_lru_log_granularity = param->value;
 814                 break;
 815         case I915_SETPARAM_ALLOW_BATCHBUFFER:
 816                 dev_priv->allow_batchbuffer = param->value;
 817                 break;
 818         case I915_SETPARAM_NUM_USED_FENCES:
 819                 if (param->value > dev_priv->num_fence_regs ||
 820                     param->value < 0)
 821                         return -EINVAL;
 822                 /* Userspace can use first N regs */
 823                 dev_priv->fence_reg_start = param->value;
 824                 break;
 825         default:
 826                 DRM_DEBUG_DRIVER("unknown parameter %d\n",
 827                                         param->param);
 828                 return -EINVAL;
 829         }
 830
 831         return 0;
 832 }
 833
 834 static int i915_set_status_page(struct drm_device *dev, void *data,
 835                                 struct drm_file *file_priv)
 836 {
 837         drm_i915_private_t *dev_priv = dev->dev_private;
 838         drm_i915_hws_addr_t *hws = data;
 839         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 840
 841         if (!I915_NEED_GFX_HWS(dev))
 842                 return -EINVAL;
 843
 844         if (!dev_priv) {
 845                 DRM_ERROR("called with no initialization\n");
 846                 return -EINVAL;
 847         }
 848
 849         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 850                 WARN(1, "tried to set status page when mode setting active\n");
 851                 return 0;
 852         }
 853
 854         DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
 855
 856         ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
 857
 858         dev_priv->hws_map.offset = dev->agp->base + hws->addr;
 859         dev_priv->hws_map.size = 4*1024;
 860         dev_priv->hws_map.type = 0;
 861         dev_priv->hws_map.flags = 0;
 862         dev_priv->hws_map.mtrr = 0;
 863
 864         drm_core_ioremap_wc(&dev_priv->hws_map, dev);
 865         if (dev_priv->hws_map.handle == NULL) {
 866                 i915_dma_cleanup(dev);
 867                 ring->status_page.gfx_addr = 0;
 868                 DRM_ERROR("can not ioremap virtual address for"
 869                                 " G33 hw status page\n");
 870                 return -ENOMEM;
 871         }
 872         ring->status_page.page_addr = dev_priv->hws_map.handle;
 873         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
 874         I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
 875
 876         DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
 877                          ring->status_page.gfx_addr);
 878         DRM_DEBUG_DRIVER("load hws at %p\n",
 879                          ring->status_page.page_addr);
 880         return 0;
 881 }
 882
 883 static int i915_get_bridge_dev(struct drm_device *dev)
 884 {
 885         struct drm_i915_private *dev_priv = dev->dev_private;
 886
 887         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
 888         if (!dev_priv->bridge_dev) {
 889                 DRM_ERROR("bridge device not found\n");
 890                 return -1;
 891         }
 892         return 0;
 893 }
 894
 895 #define MCHBAR_I915 0x44
 896 #define MCHBAR_I965 0x48
 897 #define MCHBAR_SIZE (4*4096)
 898
 899 #define DEVEN_REG 0x54
 900 #define   DEVEN_MCHBAR_EN (1 << 28)
 901
 902 /* Allocate space for the MCH regs if needed, return nonzero on error */
 903 static int
 904 intel_alloc_mchbar_resource(struct drm_device *dev)
 905 {
 906         drm_i915_private_t *dev_priv = dev->dev_private;
 907         int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 908         u32 temp_lo, temp_hi = 0;
 909         u64 mchbar_addr;
 910         int ret;
 911
 912         if (INTEL_INFO(dev)->gen >= 4)
 913                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 914         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 915         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 916
 917         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 918 #ifdef CONFIG_PNP
 919         if (mchbar_addr &&
 920             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 921                 return 0;
 922 #endif
 923
 924         /* Get some space for it */
 925         dev_priv->mch_res.name = "i915 MCHBAR";
 926         dev_priv->mch_res.flags = IORESOURCE_MEM;
 927         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 928                                      &dev_priv->mch_res,
 929                                      MCHBAR_SIZE, MCHBAR_SIZE,
 930                                      PCIBIOS_MIN_MEM,
 931                                      0, pcibios_align_resource,
 932                                      dev_priv->bridge_dev);
 933         if (ret) {
 934                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 935                 dev_priv->mch_res.start = 0;
 936                 return ret;
 937         }
 938
 939         if (INTEL_INFO(dev)->gen >= 4)
 940                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 941                                        upper_32_bits(dev_priv->mch_res.start));
 942
 943         pci_write_config_dword(dev_priv->bridge_dev, reg,
 944                                lower_32_bits(dev_priv->mch_res.start));
 945         return 0;
 946 }
 947
 948 /* Setup MCHBAR if possible, return true if we should disable it again */
 949 static void
 950 intel_setup_mchbar(struct drm_device *dev)
 951 {
 952         drm_i915_private_t *dev_priv = dev->dev_private;
 953         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 954         u32 temp;
 955         bool enabled;
 956
 957         dev_priv->mchbar_need_disable = false;
 958
 959         if (IS_I915G(dev) || IS_I915GM(dev)) {
 960                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
 961                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 962         } else {
 963                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 964                 enabled = temp & 1;
 965         }
 966
 967         /* If it's already enabled, don't have to do anything */
 968         if (enabled)
 969                 return;
 970
 971         if (intel_alloc_mchbar_resource(dev))
 972                 return;
 973
 974         dev_priv->mchbar_need_disable = true;
 975
 976         /* Space is allocated or reserved, so enable it. */
 977         if (IS_I915G(dev) || IS_I915GM(dev)) {
 978                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
 979                                        temp | DEVEN_MCHBAR_EN);
 980         } else {
 981                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 982                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 983         }
 984 }
 985
 986 static void
 987 intel_teardown_mchbar(struct drm_device *dev)
 988 {
 989         drm_i915_private_t *dev_priv = dev->dev_private;
 990         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 991         u32 temp;
 992
 993         if (dev_priv->mchbar_need_disable) {
 994                 if (IS_I915G(dev) || IS_I915GM(dev)) {
 995                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
 996                         temp &= ~DEVEN_MCHBAR_EN;
 997                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
 998                 } else {
 999                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1000                         temp &= ~1;
1001                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
1002                 }
1003         }
1004
1005         if (dev_priv->mch_res.start)
1006                 release_resource(&dev_priv->mch_res);
1007 }
1008
1009 #define PTE_ADDRESS_MASK                0xfffff000
1010 #define PTE_ADDRESS_MASK_HIGH           0x000000f0 /* i915+ */
1011 #define PTE_MAPPING_TYPE_UNCACHED       (0 << 1)
1012 #define PTE_MAPPING_TYPE_DCACHE         (1 << 1) /* i830 only */
1013 #define PTE_MAPPING_TYPE_CACHED         (3 << 1)
1014 #define PTE_MAPPING_TYPE_MASK           (3 << 1)
1015 #define PTE_VALID                       (1 << 0)
1016
1017 /**
1018  * i915_stolen_to_phys - take an offset into stolen memory and turn it into
1019  *                       a physical one
1020  * @dev: drm device
1021  * @offset: address to translate
1022  *
1023  * Some chip functions require allocations from stolen space and need the
1024  * physical address of the memory in question.
1025  */
1026 static unsigned long i915_stolen_to_phys(struct drm_device *dev, u32 offset)
1027 {
1028         struct drm_i915_private *dev_priv = dev->dev_private;
1029         struct pci_dev *pdev = dev_priv->bridge_dev;
1030         u32 base;
1031
1032 #if 0
1033         /* On the machines I have tested the Graphics Base of Stolen Memory
1034          * is unreliable, so compute the base by subtracting the stolen memory
1035          * from the Top of Low Usable DRAM which is where the BIOS places
1036          * the graphics stolen memory.
1037          */
1038         if (INTEL_INFO(dev)->gen > 3 || IS_G33(dev)) {
1039                 /* top 32bits are reserved = 0 */
1040                 pci_read_config_dword(pdev, 0xA4, &base);
1041         } else {
1042                 /* XXX presume 8xx is the same as i915 */
1043                 pci_bus_read_config_dword(pdev->bus, 2, 0x5C, &base);
1044         }
1045 #else
1046         if (INTEL_INFO(dev)->gen > 3 || IS_G33(dev)) {
1047                 u16 val;
1048                 pci_read_config_word(pdev, 0xb0, &val);
1049                 base = val >> 4 << 20;
1050         } else {
1051                 u8 val;
1052                 pci_read_config_byte(pdev, 0x9c, &val);
1053                 base = val >> 3 << 27;
1054         }
1055         base -= dev_priv->mm.gtt->stolen_size;
1056 #endif
1057
1058         return base + offset;
1059 }
1060
1061 static void i915_warn_stolen(struct drm_device *dev)
1062 {
1063         DRM_ERROR("not enough stolen space for compressed buffer, disabling\n");
1064         DRM_ERROR("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n");
1065 }
1066
1067 static void i915_setup_compression(struct drm_device *dev, int size)
1068 {
1069         struct drm_i915_private *dev_priv = dev->dev_private;
1070         struct drm_mm_node *compressed_fb, *uninitialized_var(compressed_llb);
1071         unsigned long cfb_base;
1072         unsigned long ll_base = 0;
1073
1074         compressed_fb = drm_mm_search_free(&dev_priv->mm.stolen, size, 4096, 0);
1075         if (compressed_fb)
1076                 compressed_fb = drm_mm_get_block(compressed_fb, size, 4096);
1077         if (!compressed_fb)
1078                 goto err;
1079
1080         cfb_base = i915_stolen_to_phys(dev, compressed_fb->start);
1081         if (!cfb_base)
1082                 goto err_fb;
1083
1084         if (!(IS_GM45(dev) || HAS_PCH_SPLIT(dev))) {
1085                 compressed_llb = drm_mm_search_free(&dev_priv->mm.stolen,
1086                                                     4096, 4096, 0);
1087                 if (compressed_llb)
1088                         compressed_llb = drm_mm_get_block(compressed_llb,
1089                                                           4096, 4096);
1090                 if (!compressed_llb)
1091                         goto err_fb;
1092
1093                 ll_base = i915_stolen_to_phys(dev, compressed_llb->start);
1094                 if (!ll_base)
1095                         goto err_llb;
1096         }
1097
1098         dev_priv->cfb_size = size;
1099
1100         intel_disable_fbc(dev);
1101         dev_priv->compressed_fb = compressed_fb;
1102         if (HAS_PCH_SPLIT(dev))
1103                 I915_WRITE(ILK_DPFC_CB_BASE, compressed_fb->start);
1104         else if (IS_GM45(dev)) {
1105                 I915_WRITE(DPFC_CB_BASE, compressed_fb->start);
1106         } else {
1107                 I915_WRITE(FBC_CFB_BASE, cfb_base);
1108                 I915_WRITE(FBC_LL_BASE, ll_base);
1109                 dev_priv->compressed_llb = compressed_llb;
1110         }
1111
1112         DRM_DEBUG_KMS("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n",
1113                       cfb_base, ll_base, size >> 20);
1114         return;
1115
1116 err_llb:
1117         drm_mm_put_block(compressed_llb);
1118 err_fb:
1119         drm_mm_put_block(compressed_fb);
1120 err:
1121         dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1122         i915_warn_stolen(dev);
1123 }
1124
1125 static void i915_cleanup_compression(struct drm_device *dev)
1126 {
1127         struct drm_i915_private *dev_priv = dev->dev_private;
1128
1129         drm_mm_put_block(dev_priv->compressed_fb);
1130         if (dev_priv->compressed_llb)
1131                 drm_mm_put_block(dev_priv->compressed_llb);
1132 }
1133
1134 /* true = enable decode, false = disable decoder */
1135 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1136 {
1137         struct drm_device *dev = cookie;
1138
1139         intel_modeset_vga_set_state(dev, state);
1140         if (state)
1141                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1142                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1143         else
1144                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1145 }
1146
1147 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1148 {
1149         struct drm_device *dev = pci_get_drvdata(pdev);
1150         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1151         if (state == VGA_SWITCHEROO_ON) {
1152                 printk(KERN_INFO "i915: switched on\n");
1153                 /* i915 resume handler doesn't set to D0 */
1154                 pci_set_power_state(dev->pdev, PCI_D0);
1155                 i915_resume(dev);
1156         } else {
1157                 printk(KERN_ERR "i915: switched off\n");
1158                 i915_suspend(dev, pmm);
1159         }
1160 }
1161
1162 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1163 {
1164         struct drm_device *dev = pci_get_drvdata(pdev);
1165         bool can_switch;
1166
1167         spin_lock(&dev->count_lock);
1168         can_switch = (dev->open_count == 0);
1169         spin_unlock(&dev->count_lock);
1170         return can_switch;
1171 }
1172
1173 static int i915_load_modeset_init(struct drm_device *dev)
1174 {
1175         struct drm_i915_private *dev_priv = dev->dev_private;
1176         unsigned long prealloc_size, gtt_size, mappable_size;
1177         int ret = 0;
1178
1179         prealloc_size = dev_priv->mm.gtt->stolen_size;
1180         gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT;
1181         mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
1182
1183         /* Basic memrange allocator for stolen space */
1184         drm_mm_init(&dev_priv->mm.stolen, 0, prealloc_size);
1185
1186         /* Let GEM Manage all of the aperture.
1187          *
1188          * However, leave one page at the end still bound to the scratch page.
1189          * There are a number of places where the hardware apparently
1190          * prefetches past the end of the object, and we've seen multiple
1191          * hangs with the GPU head pointer stuck in a batchbuffer bound
1192          * at the last page of the aperture.  One page should be enough to
1193          * keep any prefetching inside of the aperture.
1194          */
1195         i915_gem_do_init(dev, 0, mappable_size, gtt_size - PAGE_SIZE);
1196
1197         mutex_lock(&dev->struct_mutex);
1198         ret = i915_gem_init_ringbuffer(dev);
1199         mutex_unlock(&dev->struct_mutex);
1200         if (ret)
1201                 goto out;
1202
1203         /* Try to set up FBC with a reasonable compressed buffer size */
1204         if (I915_HAS_FBC(dev) && i915_powersave) {
1205                 int cfb_size;
1206
1207                 /* Leave 1M for line length buffer & misc. */
1208
1209                 /* Try to get a 32M buffer... */
1210                 if (prealloc_size > (36*1024*1024))
1211                         cfb_size = 32*1024*1024;
1212                 else /* fall back to 7/8 of the stolen space */
1213                         cfb_size = prealloc_size * 7 / 8;
1214                 i915_setup_compression(dev, cfb_size);
1215         }
1216
1217         /* Allow hardware batchbuffers unless told otherwise. */
1218         dev_priv->allow_batchbuffer = 1;
1219
1220         ret = intel_parse_bios(dev);
1221         if (ret)
1222                 DRM_INFO("failed to find VBIOS tables\n");
1223
1224         /* if we have > 1 VGA cards, then disable the radeon VGA resources */
1225         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1226         if (ret)
1227                 goto cleanup_ringbuffer;
1228
1229         intel_register_dsm_handler();
1230
1231         ret = vga_switcheroo_register_client(dev->pdev,
1232                                              i915_switcheroo_set_state,
1233                                              i915_switcheroo_can_switch);
1234         if (ret)
1235                 goto cleanup_vga_client;
1236
1237         /* IIR "flip pending" bit means done if this bit is set */
1238         if (IS_GEN3(dev) && (I915_READ(ECOSKPD) & ECO_FLIP_DONE))
1239                 dev_priv->flip_pending_is_done = true;
1240
1241         intel_modeset_init(dev);
1242
1243         ret = drm_irq_install(dev);
1244         if (ret)
1245                 goto cleanup_vga_switcheroo;
1246
1247         /* Always safe in the mode setting case. */
1248         /* FIXME: do pre/post-mode set stuff in core KMS code */
1249         dev->vblank_disable_allowed = 1;
1250
1251         ret = intel_fbdev_init(dev);
1252         if (ret)
1253                 goto cleanup_irq;
1254
1255         drm_kms_helper_poll_init(dev);
1256
1257         /* We're off and running w/KMS */
1258         dev_priv->mm.suspended = 0;
1259
1260         return 0;
1261
1262 cleanup_irq:
1263         drm_irq_uninstall(dev);
1264 cleanup_vga_switcheroo:
1265         vga_switcheroo_unregister_client(dev->pdev);
1266 cleanup_vga_client:
1267         vga_client_register(dev->pdev, NULL, NULL, NULL);
1268 cleanup_ringbuffer:
1269         mutex_lock(&dev->struct_mutex);
1270         i915_gem_cleanup_ringbuffer(dev);
1271         mutex_unlock(&dev->struct_mutex);
1272 out:
1273         return ret;
1274 }
1275
1276 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1277 {
1278         struct drm_i915_master_private *master_priv;
1279
1280         master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1281         if (!master_priv)
1282                 return -ENOMEM;
1283
1284         master->driver_priv = master_priv;
1285         return 0;
1286 }
1287
1288 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1289 {
1290         struct drm_i915_master_private *master_priv = master->driver_priv;
1291
1292         if (!master_priv)
1293                 return;
1294
1295         kfree(master_priv);
1296
1297         master->driver_priv = NULL;
1298 }
1299
1300 static void i915_pineview_get_mem_freq(struct drm_device *dev)
1301 {
1302         drm_i915_private_t *dev_priv = dev->dev_private;
1303         u32 tmp;
1304
1305         tmp = I915_READ(CLKCFG);
1306
1307         switch (tmp & CLKCFG_FSB_MASK) {
1308         case CLKCFG_FSB_533:
1309                 dev_priv->fsb_freq = 533; /* 133*4 */
1310                 break;
1311         case CLKCFG_FSB_800:
1312                 dev_priv->fsb_freq = 800; /* 200*4 */
1313                 break;
1314         case CLKCFG_FSB_667:
1315                 dev_priv->fsb_freq =  667; /* 167*4 */
1316                 break;
1317         case CLKCFG_FSB_400:
1318                 dev_priv->fsb_freq = 400; /* 100*4 */
1319                 break;
1320         }
1321
1322         switch (tmp & CLKCFG_MEM_MASK) {
1323         case CLKCFG_MEM_533:
1324                 dev_priv->mem_freq = 533;
1325                 break;
1326         case CLKCFG_MEM_667:
1327                 dev_priv->mem_freq = 667;
1328                 break;
1329         case CLKCFG_MEM_800:
1330                 dev_priv->mem_freq = 800;
1331                 break;
1332         }
1333
1334         /* detect pineview DDR3 setting */
1335         tmp = I915_READ(CSHRDDR3CTL);
1336         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
1337 }
1338
1339 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
1340 {
1341         drm_i915_private_t *dev_priv = dev->dev_private;
1342         u16 ddrpll, csipll;
1343
1344         ddrpll = I915_READ16(DDRMPLL1);
1345         csipll = I915_READ16(CSIPLL0);
1346
1347         switch (ddrpll & 0xff) {
1348         case 0xc:
1349                 dev_priv->mem_freq = 800;
1350                 break;
1351         case 0x10:
1352                 dev_priv->mem_freq = 1066;
1353                 break;
1354         case 0x14:
1355                 dev_priv->mem_freq = 1333;
1356                 break;
1357         case 0x18:
1358                 dev_priv->mem_freq = 1600;
1359                 break;
1360         default:
1361                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
1362                                  ddrpll & 0xff);
1363                 dev_priv->mem_freq = 0;
1364                 break;
1365         }
1366
1367         dev_priv->r_t = dev_priv->mem_freq;
1368
1369         switch (csipll & 0x3ff) {
1370         case 0x00c:
1371                 dev_priv->fsb_freq = 3200;
1372                 break;
1373         case 0x00e:
1374                 dev_priv->fsb_freq = 3733;
1375                 break;
1376         case 0x010:
1377                 dev_priv->fsb_freq = 4266;
1378                 break;
1379         case 0x012:
1380                 dev_priv->fsb_freq = 4800;
1381                 break;
1382         case 0x014:
1383                 dev_priv->fsb_freq = 5333;
1384                 break;
1385         case 0x016:
1386                 dev_priv->fsb_freq = 5866;
1387                 break;
1388         case 0x018:
1389                 dev_priv->fsb_freq = 6400;
1390                 break;
1391         default:
1392                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
1393                                  csipll & 0x3ff);
1394                 dev_priv->fsb_freq = 0;
1395                 break;
1396         }
1397
1398         if (dev_priv->fsb_freq == 3200) {
1399                 dev_priv->c_m = 0;
1400         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
1401                 dev_priv->c_m = 1;
1402         } else {
1403                 dev_priv->c_m = 2;
1404         }
1405 }
1406
1407 static const struct cparams {
1408         u16 i;
1409         u16 t;
1410         u16 m;
1411         u16 c;
1412 } cparams[] = {
1413         { 1, 1333, 301, 28664 },
1414         { 1, 1066, 294, 24460 },
1415         { 1, 800, 294, 25192 },
1416         { 0, 1333, 276, 27605 },
1417         { 0, 1066, 276, 27605 },
1418         { 0, 800, 231, 23784 },
1419 };
1420
1421 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
1422 {
1423         u64 total_count, diff, ret;
1424         u32 count1, count2, count3, m = 0, c = 0;
1425         unsigned long now = jiffies_to_msecs(jiffies), diff1;
1426         int i;
1427
1428         diff1 = now - dev_priv->last_time1;
1429
1430         count1 = I915_READ(DMIEC);
1431         count2 = I915_READ(DDREC);
1432         count3 = I915_READ(CSIEC);
1433
1434         total_count = count1 + count2 + count3;
1435
1436         /* FIXME: handle per-counter overflow */
1437         if (total_count < dev_priv->last_count1) {
1438                 diff = ~0UL - dev_priv->last_count1;
1439                 diff += total_count;
1440         } else {
1441                 diff = total_count - dev_priv->last_count1;
1442         }
1443
1444         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
1445                 if (cparams[i].i == dev_priv->c_m &&
1446                     cparams[i].t == dev_priv->r_t) {
1447                         m = cparams[i].m;
1448                         c = cparams[i].c;
1449                         break;
1450                 }
1451         }
1452
1453         diff = div_u64(diff, diff1);
1454         ret = ((m * diff) + c);
1455         ret = div_u64(ret, 10);
1456
1457         dev_priv->last_count1 = total_count;
1458         dev_priv->last_time1 = now;
1459
1460         return ret;
1461 }
1462
1463 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
1464 {
1465         unsigned long m, x, b;
1466         u32 tsfs;
1467
1468         tsfs = I915_READ(TSFS);
1469
1470         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
1471         x = I915_READ8(TR1);
1472
1473         b = tsfs & TSFS_INTR_MASK;
1474
1475         return ((m * x) / 127) - b;
1476 }
1477
1478 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
1479 {
1480         static const struct v_table {
1481                 u16 vd; /* in .1 mil */
1482                 u16 vm; /* in .1 mil */
1483         } v_table[] = {
1484                 { 0, 0, },
1485                 { 375, 0, },
1486                 { 500, 0, },
1487                 { 625, 0, },
1488                 { 750, 0, },
1489                 { 875, 0, },
1490                 { 1000, 0, },
1491                 { 1125, 0, },
1492                 { 4125, 3000, },
1493                 { 4125, 3000, },
1494                 { 4125, 3000, },
1495                 { 4125, 3000, },
1496                 { 4125, 3000, },
1497                 { 4125, 3000, },
1498                 { 4125, 3000, },
1499                 { 4125, 3000, },
1500                 { 4125, 3000, },
1501                 { 4125, 3000, },
1502                 { 4125, 3000, },
1503                 { 4125, 3000, },
1504                 { 4125, 3000, },
1505                 { 4125, 3000, },
1506                 { 4125, 3000, },
1507                 { 4125, 3000, },
1508                 { 4125, 3000, },
1509                 { 4125, 3000, },
1510                 { 4125, 3000, },
1511                 { 4125, 3000, },
1512                 { 4125, 3000, },
1513                 { 4125, 3000, },
1514                 { 4125, 3000, },
1515                 { 4125, 3000, },
1516                 { 4250, 3125, },
1517                 { 4375, 3250, },
1518                 { 4500, 3375, },
1519                 { 4625, 3500, },
1520                 { 4750, 3625, },
1521                 { 4875, 3750, },
1522                 { 5000, 3875, },
1523                 { 5125, 4000, },
1524                 { 5250, 4125, },
1525                 { 5375, 4250, },
1526                 { 5500, 4375, },
1527                 { 5625, 4500, },
1528                 { 5750, 4625, },
1529                 { 5875, 4750, },
1530                 { 6000, 4875, },
1531                 { 6125, 5000, },
1532                 { 6250, 5125, },
1533                 { 6375, 5250, },
1534                 { 6500, 5375, },
1535                 { 6625, 5500, },
1536                 { 6750, 5625, },
1537                 { 6875, 5750, },
1538                 { 7000, 5875, },
1539                 { 7125, 6000, },
1540                 { 7250, 6125, },
1541                 { 7375, 6250, },
1542                 { 7500, 6375, },
1543                 { 7625, 6500, },
1544                 { 7750, 6625, },
1545                 { 7875, 6750, },
1546                 { 8000, 6875, },
1547                 { 8125, 7000, },
1548                 { 8250, 7125, },
1549                 { 8375, 7250, },
1550                 { 8500, 7375, },
1551                 { 8625, 7500, },
1552                 { 8750, 7625, },
1553                 { 8875, 7750, },
1554                 { 9000, 7875, },
1555                 { 9125, 8000, },
1556                 { 9250, 8125, },
1557                 { 9375, 8250, },
1558                 { 9500, 8375, },
1559                 { 9625, 8500, },
1560                 { 9750, 8625, },
1561                 { 9875, 8750, },
1562                 { 10000, 8875, },
1563                 { 10125, 9000, },
1564                 { 10250, 9125, },
1565                 { 10375, 9250, },
1566                 { 10500, 9375, },
1567                 { 10625, 9500, },
1568                 { 10750, 9625, },
1569                 { 10875, 9750, },
1570                 { 11000, 9875, },
1571                 { 11125, 10000, },
1572                 { 11250, 10125, },
1573                 { 11375, 10250, },
1574                 { 11500, 10375, },
1575                 { 11625, 10500, },
1576                 { 11750, 10625, },
1577                 { 11875, 10750, },
1578                 { 12000, 10875, },
1579                 { 12125, 11000, },
1580                 { 12250, 11125, },
1581                 { 12375, 11250, },
1582                 { 12500, 11375, },
1583                 { 12625, 11500, },
1584                 { 12750, 11625, },
1585                 { 12875, 11750, },
1586                 { 13000, 11875, },
1587                 { 13125, 12000, },
1588                 { 13250, 12125, },
1589                 { 13375, 12250, },
1590                 { 13500, 12375, },
1591                 { 13625, 12500, },
1592                 { 13750, 12625, },
1593                 { 13875, 12750, },
1594                 { 14000, 12875, },
1595                 { 14125, 13000, },
1596                 { 14250, 13125, },
1597                 { 14375, 13250, },
1598                 { 14500, 13375, },
1599                 { 14625, 13500, },
1600                 { 14750, 13625, },
1601                 { 14875, 13750, },
1602                 { 15000, 13875, },
1603                 { 15125, 14000, },
1604                 { 15250, 14125, },
1605                 { 15375, 14250, },
1606                 { 15500, 14375, },
1607                 { 15625, 14500, },
1608                 { 15750, 14625, },
1609                 { 15875, 14750, },
1610                 { 16000, 14875, },
1611                 { 16125, 15000, },
1612         };
1613         if (dev_priv->info->is_mobile)
1614                 return v_table[pxvid].vm;
1615         else
1616                 return v_table[pxvid].vd;
1617 }
1618
1619 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
1620 {
1621         struct timespec now, diff1;
1622         u64 diff;
1623         unsigned long diffms;
1624         u32 count;
1625
1626         getrawmonotonic(&now);
1627         diff1 = timespec_sub(now, dev_priv->last_time2);
1628
1629         /* Don't divide by 0 */
1630         diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
1631         if (!diffms)
1632                 return;
1633
1634         count = I915_READ(GFXEC);
1635
1636         if (count < dev_priv->last_count2) {
1637                 diff = ~0UL - dev_priv->last_count2;
1638                 diff += count;
1639         } else {
1640                 diff = count - dev_priv->last_count2;
1641         }
1642
1643         dev_priv->last_count2 = count;
1644         dev_priv->last_time2 = now;
1645
1646         /* More magic constants... */
1647         diff = diff * 1181;
1648         diff = div_u64(diff, diffms * 10);
1649         dev_priv->gfx_power = diff;
1650 }
1651
1652 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
1653 {
1654         unsigned long t, corr, state1, corr2, state2;
1655         u32 pxvid, ext_v;
1656
1657         pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->cur_delay * 4));
1658         pxvid = (pxvid >> 24) & 0x7f;
1659         ext_v = pvid_to_extvid(dev_priv, pxvid);
1660
1661         state1 = ext_v;
1662
1663         t = i915_mch_val(dev_priv);
1664
1665         /* Revel in the empirically derived constants */
1666
1667         /* Correction factor in 1/100000 units */
1668         if (t > 80)
1669                 corr = ((t * 2349) + 135940);
1670         else if (t >= 50)
1671                 corr = ((t * 964) + 29317);
1672         else /* < 50 */
1673                 corr = ((t * 301) + 1004);
1674
1675         corr = corr * ((150142 * state1) / 10000 - 78642);
1676         corr /= 100000;
1677         corr2 = (corr * dev_priv->corr);
1678
1679         state2 = (corr2 * state1) / 10000;
1680         state2 /= 100; /* convert to mW */
1681
1682         i915_update_gfx_val(dev_priv);
1683
1684         return dev_priv->gfx_power + state2;
1685 }
1686
1687 /* Global for IPS driver to get at the current i915 device */
1688 static struct drm_i915_private *i915_mch_dev;
1689 /*
1690  * Lock protecting IPS related data structures
1691  *   - i915_mch_dev
1692  *   - dev_priv->max_delay
1693  *   - dev_priv->min_delay
1694  *   - dev_priv->fmax
1695  *   - dev_priv->gpu_busy
1696  */
1697 static DEFINE_SPINLOCK(mchdev_lock);
1698
1699 /**
1700  * i915_read_mch_val - return value for IPS use
1701  *
1702  * Calculate and return a value for the IPS driver to use when deciding whether
1703  * we have thermal and power headroom to increase CPU or GPU power budget.
1704  */
1705 unsigned long i915_read_mch_val(void)
1706 {
1707         struct drm_i915_private *dev_priv;
1708         unsigned long chipset_val, graphics_val, ret = 0;
1709
1710         spin_lock(&mchdev_lock);
1711         if (!i915_mch_dev)
1712                 goto out_unlock;
1713         dev_priv = i915_mch_dev;
1714
1715         chipset_val = i915_chipset_val(dev_priv);
1716         graphics_val = i915_gfx_val(dev_priv);
1717
1718         ret = chipset_val + graphics_val;
1719
1720 out_unlock:
1721         spin_unlock(&mchdev_lock);
1722
1723         return ret;
1724 }
1725 EXPORT_SYMBOL_GPL(i915_read_mch_val);
1726
1727 /**
1728  * i915_gpu_raise - raise GPU frequency limit
1729  *
1730  * Raise the limit; IPS indicates we have thermal headroom.
1731  */
1732 bool i915_gpu_raise(void)
1733 {
1734         struct drm_i915_private *dev_priv;
1735         bool ret = true;
1736
1737         spin_lock(&mchdev_lock);
1738         if (!i915_mch_dev) {
1739                 ret = false;
1740                 goto out_unlock;
1741         }
1742         dev_priv = i915_mch_dev;
1743
1744         if (dev_priv->max_delay > dev_priv->fmax)
1745                 dev_priv->max_delay--;
1746
1747 out_unlock:
1748         spin_unlock(&mchdev_lock);
1749
1750         return ret;
1751 }
1752 EXPORT_SYMBOL_GPL(i915_gpu_raise);
1753
1754 /**
1755  * i915_gpu_lower - lower GPU frequency limit
1756  *
1757  * IPS indicates we're close to a thermal limit, so throttle back the GPU
1758  * frequency maximum.
1759  */
1760 bool i915_gpu_lower(void)
1761 {
1762         struct drm_i915_private *dev_priv;
1763         bool ret = true;
1764
1765         spin_lock(&mchdev_lock);
1766         if (!i915_mch_dev) {
1767                 ret = false;
1768                 goto out_unlock;
1769         }
1770         dev_priv = i915_mch_dev;
1771
1772         if (dev_priv->max_delay < dev_priv->min_delay)
1773                 dev_priv->max_delay++;
1774
1775 out_unlock:
1776         spin_unlock(&mchdev_lock);
1777
1778         return ret;
1779 }
1780 EXPORT_SYMBOL_GPL(i915_gpu_lower);
1781
1782 /**
1783  * i915_gpu_busy - indicate GPU business to IPS
1784  *
1785  * Tell the IPS driver whether or not the GPU is busy.
1786  */
1787 bool i915_gpu_busy(void)
1788 {
1789         struct drm_i915_private *dev_priv;
1790         bool ret = false;
1791
1792         spin_lock(&mchdev_lock);
1793         if (!i915_mch_dev)
1794                 goto out_unlock;
1795         dev_priv = i915_mch_dev;
1796
1797         ret = dev_priv->busy;
1798
1799 out_unlock:
1800         spin_unlock(&mchdev_lock);
1801
1802         return ret;
1803 }
1804 EXPORT_SYMBOL_GPL(i915_gpu_busy);
1805
1806 /**
1807  * i915_gpu_turbo_disable - disable graphics turbo
1808  *
1809  * Disable graphics turbo by resetting the max frequency and setting the
1810  * current frequency to the default.
1811  */
1812 bool i915_gpu_turbo_disable(void)
1813 {
1814         struct drm_i915_private *dev_priv;
1815         bool ret = true;
1816
1817         spin_lock(&mchdev_lock);
1818         if (!i915_mch_dev) {
1819                 ret = false;
1820                 goto out_unlock;
1821         }
1822         dev_priv = i915_mch_dev;
1823
1824         dev_priv->max_delay = dev_priv->fstart;
1825
1826         if (!ironlake_set_drps(dev_priv->dev, dev_priv->fstart))
1827                 ret = false;
1828
1829 out_unlock:
1830         spin_unlock(&mchdev_lock);
1831
1832         return ret;
1833 }
1834 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
1835
1836 /**
1837  * i915_driver_load - setup chip and create an initial config
1838  * @dev: DRM device
1839  * @flags: startup flags
1840  *
1841  * The driver load routine has to do several things:
1842  *   - drive output discovery via intel_modeset_init()
1843  *   - initialize the memory manager
1844  *   - allocate initial config memory
1845  *   - setup the DRM framebuffer with the allocated memory
1846  */
1847 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1848 {
1849         struct drm_i915_private *dev_priv;
1850         int ret = 0, mmio_bar;
1851         uint32_t agp_size;
1852
1853         /* i915 has 4 more counters */
1854         dev->counters += 4;
1855         dev->types[6] = _DRM_STAT_IRQ;
1856         dev->types[7] = _DRM_STAT_PRIMARY;
1857         dev->types[8] = _DRM_STAT_SECONDARY;
1858         dev->types[9] = _DRM_STAT_DMA;
1859
1860         dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
1861         if (dev_priv == NULL)
1862                 return -ENOMEM;
1863
1864         dev->dev_private = (void *)dev_priv;
1865         dev_priv->dev = dev;
1866         dev_priv->info = (struct intel_device_info *) flags;
1867
1868         if (i915_get_bridge_dev(dev)) {
1869                 ret = -EIO;
1870                 goto free_priv;
1871         }
1872
1873         /* overlay on gen2 is broken and can't address above 1G */
1874         if (IS_GEN2(dev))
1875                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1876
1877         mmio_bar = IS_GEN2(dev) ? 1 : 0;
1878         dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, 0);
1879         if (!dev_priv->regs) {
1880                 DRM_ERROR("failed to map registers\n");
1881                 ret = -EIO;
1882                 goto put_bridge;
1883         }
1884
1885         dev_priv->mm.gtt = intel_gtt_get();
1886         if (!dev_priv->mm.gtt) {
1887                 DRM_ERROR("Failed to initialize GTT\n");
1888                 ret = -ENODEV;
1889                 goto out_iomapfree;
1890         }
1891
1892         agp_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
1893
1894         dev_priv->mm.gtt_mapping =
1895                 io_mapping_create_wc(dev->agp->base, agp_size);
1896         if (dev_priv->mm.gtt_mapping == NULL) {
1897                 ret = -EIO;
1898                 goto out_rmmap;
1899         }
1900
1901         /* Set up a WC MTRR for non-PAT systems.  This is more common than
1902          * one would think, because the kernel disables PAT on first
1903          * generation Core chips because WC PAT gets overridden by a UC
1904          * MTRR if present.  Even if a UC MTRR isn't present.
1905          */
1906         dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base,
1907                                          agp_size,
1908                                          MTRR_TYPE_WRCOMB, 1);
1909         if (dev_priv->mm.gtt_mtrr < 0) {
1910                 DRM_INFO("MTRR allocation failed.  Graphics "
1911                          "performance may suffer.\n");
1912         }
1913
1914         /* The i915 workqueue is primarily used for batched retirement of
1915          * requests (and thus managing bo) once the task has been completed
1916          * by the GPU. i915_gem_retire_requests() is called directly when we
1917          * need high-priority retirement, such as waiting for an explicit
1918          * bo.
1919          *
1920          * It is also used for periodic low-priority events, such as
1921          * idle-timers and recording error state.
1922          *
1923          * All tasks on the workqueue are expected to acquire the dev mutex
1924          * so there is no point in running more than one instance of the
1925          * workqueue at any time: max_active = 1 and NON_REENTRANT.
1926          */
1927         dev_priv->wq = alloc_workqueue("i915",
1928                                        WQ_UNBOUND | WQ_NON_REENTRANT,
1929                                        1);
1930         if (dev_priv->wq == NULL) {
1931                 DRM_ERROR("Failed to create our workqueue.\n");
1932                 ret = -ENOMEM;
1933                 goto out_iomapfree;
1934         }
1935
1936         /* enable GEM by default */
1937         dev_priv->has_gem = 1;
1938
1939         if (dev_priv->has_gem == 0 &&
1940             drm_core_check_feature(dev, DRIVER_MODESET)) {
1941                 DRM_ERROR("kernel modesetting requires GEM, disabling driver.\n");
1942                 ret = -ENODEV;
1943                 goto out_workqueue_free;
1944         }
1945
1946         dev->driver->get_vblank_counter = i915_get_vblank_counter;
1947         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
1948         if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev)) {
1949                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
1950                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
1951         }
1952
1953         /* Try to make sure MCHBAR is enabled before poking at it */
1954         intel_setup_mchbar(dev);
1955         intel_setup_gmbus(dev);
1956         intel_opregion_setup(dev);
1957
1958         /* Make sure the bios did its job and set up vital registers */
1959         intel_setup_bios(dev);
1960
1961         i915_gem_load(dev);
1962
1963         /* Init HWS */
1964         if (!I915_NEED_GFX_HWS(dev)) {
1965                 ret = i915_init_phys_hws(dev);
1966                 if (ret)
1967                         goto out_gem_unload;
1968         }
1969
1970         if (IS_PINEVIEW(dev))
1971                 i915_pineview_get_mem_freq(dev);
1972         else if (IS_GEN5(dev))
1973                 i915_ironlake_get_mem_freq(dev);
1974
1975         /* On the 945G/GM, the chipset reports the MSI capability on the
1976          * integrated graphics even though the support isn't actually there
1977          * according to the published specs.  It doesn't appear to function
1978          * correctly in testing on 945G.
1979          * This may be a side effect of MSI having been made available for PEG
1980          * and the registers being closely associated.
1981          *
1982          * According to chipset errata, on the 965GM, MSI interrupts may
1983          * be lost or delayed, but we use them anyways to avoid
1984          * stuck interrupts on some machines.
1985          */
1986         if (!IS_I945G(dev) && !IS_I945GM(dev))
1987                 pci_enable_msi(dev->pdev);
1988
1989         spin_lock_init(&dev_priv->irq_lock);
1990         spin_lock_init(&dev_priv->error_lock);
1991         dev_priv->trace_irq_seqno = 0;
1992
1993         ret = drm_vblank_init(dev, I915_NUM_PIPE);
1994         if (ret)
1995                 goto out_gem_unload;
1996
1997         /* Start out suspended */
1998         dev_priv->mm.suspended = 1;
1999
2000         intel_detect_pch(dev);
2001
2002         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2003                 ret = i915_load_modeset_init(dev);
2004                 if (ret < 0) {
2005                         DRM_ERROR("failed to init modeset\n");
2006                         goto out_gem_unload;
2007                 }
2008         }
2009
2010         /* Must be done after probing outputs */
2011         intel_opregion_init(dev);
2012         acpi_video_register();
2013
2014         setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
2015                     (unsigned long) dev);
2016
2017         spin_lock(&mchdev_lock);
2018         i915_mch_dev = dev_priv;
2019         dev_priv->mchdev_lock = &mchdev_lock;
2020         spin_unlock(&mchdev_lock);
2021
2022         return 0;
2023
2024 out_gem_unload:
2025         if (dev->pdev->msi_enabled)
2026                 pci_disable_msi(dev->pdev);
2027
2028         intel_teardown_gmbus(dev);
2029         intel_teardown_mchbar(dev);
2030 out_workqueue_free:
2031         destroy_workqueue(dev_priv->wq);
2032 out_iomapfree:
2033         io_mapping_free(dev_priv->mm.gtt_mapping);
2034 out_rmmap:
2035         pci_iounmap(dev->pdev, dev_priv->regs);
2036 put_bridge:
2037         pci_dev_put(dev_priv->bridge_dev);
2038 free_priv:
2039         kfree(dev_priv);
2040         return ret;
2041 }
2042
2043 int i915_driver_unload(struct drm_device *dev)
2044 {
2045         struct drm_i915_private *dev_priv = dev->dev_private;
2046         int ret;
2047
2048         spin_lock(&mchdev_lock);
2049         i915_mch_dev = NULL;
2050         spin_unlock(&mchdev_lock);
2051
2052         if (dev_priv->mm.inactive_shrinker.shrink)
2053                 unregister_shrinker(&dev_priv->mm.inactive_shrinker);
2054
2055         mutex_lock(&dev->struct_mutex);
2056         ret = i915_gpu_idle(dev);
2057         if (ret)
2058                 DRM_ERROR("failed to idle hardware: %d\n", ret);
2059         mutex_unlock(&dev->struct_mutex);
2060
2061         /* Cancel the retire work handler, which should be idle now. */
2062         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
2063
2064         io_mapping_free(dev_priv->mm.gtt_mapping);
2065         if (dev_priv->mm.gtt_mtrr >= 0) {
2066                 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
2067                          dev->agp->agp_info.aper_size * 1024 * 1024);
2068                 dev_priv->mm.gtt_mtrr = -1;
2069         }
2070
2071         acpi_video_unregister();
2072
2073         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2074                 intel_fbdev_fini(dev);
2075                 intel_modeset_cleanup(dev);
2076
2077                 /*
2078                  * free the memory space allocated for the child device
2079                  * config parsed from VBT
2080                  */
2081                 if (dev_priv->child_dev && dev_priv->child_dev_num) {
2082                         kfree(dev_priv->child_dev);
2083                         dev_priv->child_dev = NULL;
2084                         dev_priv->child_dev_num = 0;
2085                 }
2086
2087                 vga_switcheroo_unregister_client(dev->pdev);
2088                 vga_client_register(dev->pdev, NULL, NULL, NULL);
2089         }
2090
2091         /* Free error state after interrupts are fully disabled. */
2092         del_timer_sync(&dev_priv->hangcheck_timer);
2093         cancel_work_sync(&dev_priv->error_work);
2094         i915_destroy_error_state(dev);
2095
2096         if (dev->pdev->msi_enabled)
2097                 pci_disable_msi(dev->pdev);
2098
2099         intel_opregion_fini(dev);
2100
2101         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2102                 /* Flush any outstanding unpin_work. */
2103                 flush_workqueue(dev_priv->wq);
2104
2105                 i915_gem_free_all_phys_object(dev);
2106
2107                 mutex_lock(&dev->struct_mutex);
2108                 i915_gem_cleanup_ringbuffer(dev);
2109                 mutex_unlock(&dev->struct_mutex);
2110                 if (I915_HAS_FBC(dev) && i915_powersave)
2111                         i915_cleanup_compression(dev);
2112                 drm_mm_takedown(&dev_priv->mm.stolen);
2113
2114                 intel_cleanup_overlay(dev);
2115
2116                 if (!I915_NEED_GFX_HWS(dev))
2117                         i915_free_hws(dev);
2118         }
2119
2120         if (dev_priv->regs != NULL)
2121                 pci_iounmap(dev->pdev, dev_priv->regs);
2122
2123         intel_teardown_gmbus(dev);
2124         intel_teardown_mchbar(dev);
2125
2126         destroy_workqueue(dev_priv->wq);
2127
2128         pci_dev_put(dev_priv->bridge_dev);
2129         kfree(dev->dev_private);
2130
2131         return 0;
2132 }
2133
2134 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
2135 {
2136         struct drm_i915_file_private *file_priv;
2137
2138         DRM_DEBUG_DRIVER("\n");
2139         file_priv = kmalloc(sizeof(*file_priv), GFP_KERNEL);
2140         if (!file_priv)
2141                 return -ENOMEM;
2142
2143         file->driver_priv = file_priv;
2144
2145         spin_lock_init(&file_priv->mm.lock);
2146         INIT_LIST_HEAD(&file_priv->mm.request_list);
2147
2148         return 0;
2149 }
2150
2151 /**
2152  * i915_driver_lastclose - clean up after all DRM clients have exited
2153  * @dev: DRM device
2154  *
2155  * Take care of cleaning up after all DRM clients have exited.  In the
2156  * mode setting case, we want to restore the kernel's initial mode (just
2157  * in case the last client left us in a bad state).
2158  *
2159  * Additionally, in the non-mode setting case, we'll tear down the AGP
2160  * and DMA structures, since the kernel won't be using them, and clea
2161  * up any GEM state.
2162  */
2163 void i915_driver_lastclose(struct drm_device * dev)
2164 {
2165         drm_i915_private_t *dev_priv = dev->dev_private;
2166
2167         if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
2168                 drm_fb_helper_restore();
2169                 vga_switcheroo_process_delayed_switch();
2170                 return;
2171         }
2172
2173         i915_gem_lastclose(dev);
2174
2175         if (dev_priv->agp_heap)
2176                 i915_mem_takedown(&(dev_priv->agp_heap));
2177
2178         i915_dma_cleanup(dev);
2179 }
2180
2181 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
2182 {
2183         drm_i915_private_t *dev_priv = dev->dev_private;
2184         i915_gem_release(dev, file_priv);
2185         if (!drm_core_check_feature(dev, DRIVER_MODESET))
2186                 i915_mem_release(dev, file_priv, dev_priv->agp_heap);
2187 }
2188
2189 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
2190 {
2191         struct drm_i915_file_private *file_priv = file->driver_priv;
2192
2193         kfree(file_priv);
2194 }
2195
2196 struct drm_ioctl_desc i915_ioctls[] = {
2197         DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2198         DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
2199         DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
2200         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
2201         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
2202         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
2203         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH),
2204         DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2205         DRM_IOCTL_DEF_DRV(I915_ALLOC, i915_mem_alloc, DRM_AUTH),
2206         DRM_IOCTL_DEF_DRV(I915_FREE, i915_mem_free, DRM_AUTH),
2207         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2208         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
2209         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2210         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2211         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH),
2212         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
2213         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2214         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2215         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
2216         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
2217         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2218         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2219         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
2220         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
2221         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2222         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2223         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
2224         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
2225         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
2226         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
2227         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
2228         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
2229         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
2230         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
2231         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
2232         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
2233         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
2234         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
2235         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2236         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2237 };
2238
2239 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
2240
2241 /**
2242  * Determine if the device really is AGP or not.
2243  *
2244  * All Intel graphics chipsets are treated as AGP, even if they are really
2245  * PCI-e.
2246  *
2247  * \param dev   The device to be tested.
2248  *
2249  * \returns
2250  * A value of 1 is always retured to indictate every i9x5 is AGP.
2251  */
2252 int i915_driver_device_is_agp(struct drm_device * dev)
2253 {
2254         return 1;
2255 }