drivers/gpu/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include "drmP.h"
  30 #include "drm.h"
  31 #include "drm_crtc_helper.h"
  32 #include "drm_fb_helper.h"
  33 #include "intel_drv.h"
  34 #include "i915_drm.h"
  35 #include "i915_drv.h"
  36 #include "i915_trace.h"
  37 #include <linux/pci.h>
  38 #include <linux/vgaarb.h>
  39 #include <linux/acpi.h>
  40 #include <linux/pnp.h>
  41 #include <linux/vga_switcheroo.h>
  42 #include <linux/slab.h>
  43 #include <acpi/video.h>
  44
  45 /**
  46  * Sets up the hardware status page for devices that need a physical address
  47  * in the register.
  48  */
  49 static int i915_init_phys_hws(struct drm_device *dev)
  50 {
  51         drm_i915_private_t *dev_priv = dev->dev_private;
  52         /* Program Hardware Status Page */
  53         dev_priv->status_page_dmah =
  54                 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE);
  55
  56         if (!dev_priv->status_page_dmah) {
  57                 DRM_ERROR("Can not allocate hardware status page\n");
  58                 return -ENOMEM;
  59         }
  60         dev_priv->render_ring.status_page.page_addr
  61                 = dev_priv->status_page_dmah->vaddr;
  62         dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
  63
  64         memset(dev_priv->render_ring.status_page.page_addr, 0, PAGE_SIZE);
  65
  66         if (INTEL_INFO(dev)->gen >= 4)
  67                 dev_priv->dma_status_page |= (dev_priv->dma_status_page >> 28) &
  68                                              0xf0;
  69
  70         I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
  71         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
  72         return 0;
  73 }
  74
  75 /**
  76  * Frees the hardware status page, whether it's a physical address or a virtual
  77  * address set up by the X Server.
  78  */
  79 static void i915_free_hws(struct drm_device *dev)
  80 {
  81         drm_i915_private_t *dev_priv = dev->dev_private;
  82         if (dev_priv->status_page_dmah) {
  83                 drm_pci_free(dev, dev_priv->status_page_dmah);
  84                 dev_priv->status_page_dmah = NULL;
  85         }
  86
  87         if (dev_priv->render_ring.status_page.gfx_addr) {
  88                 dev_priv->render_ring.status_page.gfx_addr = 0;
  89                 drm_core_ioremapfree(&dev_priv->hws_map, dev);
  90         }
  91
  92         /* Need to rewrite hardware status page */
  93         I915_WRITE(HWS_PGA, 0x1ffff000);
  94 }
  95
  96 void i915_kernel_lost_context(struct drm_device * dev)
  97 {
  98         drm_i915_private_t *dev_priv = dev->dev_private;
  99         struct drm_i915_master_private *master_priv;
 100         struct intel_ring_buffer *ring = &dev_priv->render_ring;
 101
 102         /*
 103          * We should never lose context on the ring with modesetting
 104          * as we don't expose it to userspace
 105          */
 106         if (drm_core_check_feature(dev, DRIVER_MODESET))
 107                 return;
 108
 109         ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
 110         ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
 111         ring->space = ring->head - (ring->tail + 8);
 112         if (ring->space < 0)
 113                 ring->space += ring->size;
 114
 115         if (!dev->primary->master)
 116                 return;
 117
 118         master_priv = dev->primary->master->driver_priv;
 119         if (ring->head == ring->tail && master_priv->sarea_priv)
 120                 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
 121 }
 122
 123 static int i915_dma_cleanup(struct drm_device * dev)
 124 {
 125         drm_i915_private_t *dev_priv = dev->dev_private;
 126         /* Make sure interrupts are disabled here because the uninstall ioctl
 127          * may not have been called from userspace and after dev_private
 128          * is freed, it's too late.
 129          */
 130         if (dev->irq_enabled)
 131                 drm_irq_uninstall(dev);
 132
 133         mutex_lock(&dev->struct_mutex);
 134         intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
 135         intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring);
 136         mutex_unlock(&dev->struct_mutex);
 137
 138         /* Clear the HWS virtual address at teardown */
 139         if (I915_NEED_GFX_HWS(dev))
 140                 i915_free_hws(dev);
 141
 142         return 0;
 143 }
 144
 145 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
 146 {
 147         drm_i915_private_t *dev_priv = dev->dev_private;
 148         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 149
 150         master_priv->sarea = drm_getsarea(dev);
 151         if (master_priv->sarea) {
 152                 master_priv->sarea_priv = (drm_i915_sarea_t *)
 153                         ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
 154         } else {
 155                 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
 156         }
 157
 158         if (init->ring_size != 0) {
 159                 if (dev_priv->render_ring.gem_object != NULL) {
 160                         i915_dma_cleanup(dev);
 161                         DRM_ERROR("Client tried to initialize ringbuffer in "
 162                                   "GEM mode\n");
 163                         return -EINVAL;
 164                 }
 165
 166                 dev_priv->render_ring.size = init->ring_size;
 167
 168                 dev_priv->render_ring.map.offset = init->ring_start;
 169                 dev_priv->render_ring.map.size = init->ring_size;
 170                 dev_priv->render_ring.map.type = 0;
 171                 dev_priv->render_ring.map.flags = 0;
 172                 dev_priv->render_ring.map.mtrr = 0;
 173
 174                 drm_core_ioremap_wc(&dev_priv->render_ring.map, dev);
 175
 176                 if (dev_priv->render_ring.map.handle == NULL) {
 177                         i915_dma_cleanup(dev);
 178                         DRM_ERROR("can not ioremap virtual address for"
 179                                   " ring buffer\n");
 180                         return -ENOMEM;
 181                 }
 182         }
 183
 184         dev_priv->render_ring.virtual_start = dev_priv->render_ring.map.handle;
 185
 186         dev_priv->cpp = init->cpp;
 187         dev_priv->back_offset = init->back_offset;
 188         dev_priv->front_offset = init->front_offset;
 189         dev_priv->current_page = 0;
 190         if (master_priv->sarea_priv)
 191                 master_priv->sarea_priv->pf_current_page = 0;
 192
 193         /* Allow hardware batchbuffers unless told otherwise.
 194          */
 195         dev_priv->allow_batchbuffer = 1;
 196
 197         return 0;
 198 }
 199
 200 static int i915_dma_resume(struct drm_device * dev)
 201 {
 202         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 203
 204         struct intel_ring_buffer *ring;
 205         DRM_DEBUG_DRIVER("%s\n", __func__);
 206
 207         ring = &dev_priv->render_ring;
 208
 209         if (ring->map.handle == NULL) {
 210                 DRM_ERROR("can not ioremap virtual address for"
 211                           " ring buffer\n");
 212                 return -ENOMEM;
 213         }
 214
 215         /* Program Hardware Status Page */
 216         if (!ring->status_page.page_addr) {
 217                 DRM_ERROR("Can not find hardware status page\n");
 218                 return -EINVAL;
 219         }
 220         DRM_DEBUG_DRIVER("hw status page @ %p\n",
 221                                 ring->status_page.page_addr);
 222         if (ring->status_page.gfx_addr != 0)
 223                 intel_ring_setup_status_page(dev, ring);
 224         else
 225                 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
 226
 227         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
 228
 229         return 0;
 230 }
 231
 232 static int i915_dma_init(struct drm_device *dev, void *data,
 233                          struct drm_file *file_priv)
 234 {
 235         drm_i915_init_t *init = data;
 236         int retcode = 0;
 237
 238         switch (init->func) {
 239         case I915_INIT_DMA:
 240                 retcode = i915_initialize(dev, init);
 241                 break;
 242         case I915_CLEANUP_DMA:
 243                 retcode = i915_dma_cleanup(dev);
 244                 break;
 245         case I915_RESUME_DMA:
 246                 retcode = i915_dma_resume(dev);
 247                 break;
 248         default:
 249                 retcode = -EINVAL;
 250                 break;
 251         }
 252
 253         return retcode;
 254 }
 255
 256 /* Implement basically the same security restrictions as hardware does
 257  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 258  *
 259  * Most of the calculations below involve calculating the size of a
 260  * particular instruction.  It's important to get the size right as
 261  * that tells us where the next instruction to check is.  Any illegal
 262  * instruction detected will be given a size of zero, which is a
 263  * signal to abort the rest of the buffer.
 264  */
 265 static int do_validate_cmd(int cmd)
 266 {
 267         switch (((cmd >> 29) & 0x7)) {
 268         case 0x0:
 269                 switch ((cmd >> 23) & 0x3f) {
 270                 case 0x0:
 271                         return 1;       /* MI_NOOP */
 272                 case 0x4:
 273                         return 1;       /* MI_FLUSH */
 274                 default:
 275                         return 0;       /* disallow everything else */
 276                 }
 277                 break;
 278         case 0x1:
 279                 return 0;       /* reserved */
 280         case 0x2:
 281                 return (cmd & 0xff) + 2;        /* 2d commands */
 282         case 0x3:
 283                 if (((cmd >> 24) & 0x1f) <= 0x18)
 284                         return 1;
 285
 286                 switch ((cmd >> 24) & 0x1f) {
 287                 case 0x1c:
 288                         return 1;
 289                 case 0x1d:
 290                         switch ((cmd >> 16) & 0xff) {
 291                         case 0x3:
 292                                 return (cmd & 0x1f) + 2;
 293                         case 0x4:
 294                                 return (cmd & 0xf) + 2;
 295                         default:
 296                                 return (cmd & 0xffff) + 2;
 297                         }
 298                 case 0x1e:
 299                         if (cmd & (1 << 23))
 300                                 return (cmd & 0xffff) + 1;
 301                         else
 302                                 return 1;
 303                 case 0x1f:
 304                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 305                                 return (cmd & 0x1ffff) + 2;
 306                         else if (cmd & (1 << 17))       /* indirect random */
 307                                 if ((cmd & 0xffff) == 0)
 308                                         return 0;       /* unknown length, too hard */
 309                                 else
 310                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 311                         else
 312                                 return 2;       /* indirect sequential */
 313                 default:
 314                         return 0;
 315                 }
 316         default:
 317                 return 0;
 318         }
 319
 320         return 0;
 321 }
 322
 323 static int validate_cmd(int cmd)
 324 {
 325         int ret = do_validate_cmd(cmd);
 326
 327 /*      printk("validate_cmd( %x ): %d\n", cmd, ret); */
 328
 329         return ret;
 330 }
 331
 332 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
 333 {
 334         drm_i915_private_t *dev_priv = dev->dev_private;
 335         int i;
 336
 337         if ((dwords+1) * sizeof(int) >= dev_priv->render_ring.size - 8)
 338                 return -EINVAL;
 339
 340         BEGIN_LP_RING((dwords+1)&~1);
 341
 342         for (i = 0; i < dwords;) {
 343                 int cmd, sz;
 344
 345                 cmd = buffer[i];
 346
 347                 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
 348                         return -EINVAL;
 349
 350                 OUT_RING(cmd);
 351
 352                 while (++i, --sz) {
 353                         OUT_RING(buffer[i]);
 354                 }
 355         }
 356
 357         if (dwords & 1)
 358                 OUT_RING(0);
 359
 360         ADVANCE_LP_RING();
 361
 362         return 0;
 363 }
 364
 365 int
 366 i915_emit_box(struct drm_device *dev,
 367               struct drm_clip_rect *boxes,
 368               int i, int DR1, int DR4)
 369 {
 370         struct drm_clip_rect box = boxes[i];
 371
 372         if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
 373                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 374                           box.x1, box.y1, box.x2, box.y2);
 375                 return -EINVAL;
 376         }
 377
 378         if (INTEL_INFO(dev)->gen >= 4) {
 379                 BEGIN_LP_RING(4);
 380                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 381                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 382                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 383                 OUT_RING(DR4);
 384                 ADVANCE_LP_RING();
 385         } else {
 386                 BEGIN_LP_RING(6);
 387                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 388                 OUT_RING(DR1);
 389                 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
 390                 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
 391                 OUT_RING(DR4);
 392                 OUT_RING(0);
 393                 ADVANCE_LP_RING();
 394         }
 395
 396         return 0;
 397 }
 398
 399 /* XXX: Emitting the counter should really be moved to part of the IRQ
 400  * emit. For now, do it in both places:
 401  */
 402
 403 static void i915_emit_breadcrumb(struct drm_device *dev)
 404 {
 405         drm_i915_private_t *dev_priv = dev->dev_private;
 406         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 407
 408         dev_priv->counter++;
 409         if (dev_priv->counter > 0x7FFFFFFFUL)
 410                 dev_priv->counter = 0;
 411         if (master_priv->sarea_priv)
 412                 master_priv->sarea_priv->last_enqueue = dev_priv->counter;
 413
 414         BEGIN_LP_RING(4);
 415         OUT_RING(MI_STORE_DWORD_INDEX);
 416         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 417         OUT_RING(dev_priv->counter);
 418         OUT_RING(0);
 419         ADVANCE_LP_RING();
 420 }
 421
 422 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 423                                    drm_i915_cmdbuffer_t *cmd,
 424                                    struct drm_clip_rect *cliprects,
 425                                    void *cmdbuf)
 426 {
 427         int nbox = cmd->num_cliprects;
 428         int i = 0, count, ret;
 429
 430         if (cmd->sz & 0x3) {
 431                 DRM_ERROR("alignment");
 432                 return -EINVAL;
 433         }
 434
 435         i915_kernel_lost_context(dev);
 436
 437         count = nbox ? nbox : 1;
 438
 439         for (i = 0; i < count; i++) {
 440                 if (i < nbox) {
 441                         ret = i915_emit_box(dev, cliprects, i,
 442                                             cmd->DR1, cmd->DR4);
 443                         if (ret)
 444                                 return ret;
 445                 }
 446
 447                 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
 448                 if (ret)
 449                         return ret;
 450         }
 451
 452         i915_emit_breadcrumb(dev);
 453         return 0;
 454 }
 455
 456 static int i915_dispatch_batchbuffer(struct drm_device * dev,
 457                                      drm_i915_batchbuffer_t * batch,
 458                                      struct drm_clip_rect *cliprects)
 459 {
 460         int nbox = batch->num_cliprects;
 461         int i = 0, count;
 462
 463         if ((batch->start | batch->used) & 0x7) {
 464                 DRM_ERROR("alignment");
 465                 return -EINVAL;
 466         }
 467
 468         i915_kernel_lost_context(dev);
 469
 470         count = nbox ? nbox : 1;
 471
 472         for (i = 0; i < count; i++) {
 473                 if (i < nbox) {
 474                         int ret = i915_emit_box(dev, cliprects, i,
 475                                                 batch->DR1, batch->DR4);
 476                         if (ret)
 477                                 return ret;
 478                 }
 479
 480                 if (!IS_I830(dev) && !IS_845G(dev)) {
 481                         BEGIN_LP_RING(2);
 482                         if (INTEL_INFO(dev)->gen >= 4) {
 483                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
 484                                 OUT_RING(batch->start);
 485                         } else {
 486                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 487                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 488                         }
 489                         ADVANCE_LP_RING();
 490                 } else {
 491                         BEGIN_LP_RING(4);
 492                         OUT_RING(MI_BATCH_BUFFER);
 493                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 494                         OUT_RING(batch->start + batch->used - 4);
 495                         OUT_RING(0);
 496                         ADVANCE_LP_RING();
 497                 }
 498         }
 499
 500
 501         if (IS_G4X(dev) || IS_IRONLAKE(dev)) {
 502                 BEGIN_LP_RING(2);
 503                 OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
 504                 OUT_RING(MI_NOOP);
 505                 ADVANCE_LP_RING();
 506         }
 507         i915_emit_breadcrumb(dev);
 508
 509         return 0;
 510 }
 511
 512 static int i915_dispatch_flip(struct drm_device * dev)
 513 {
 514         drm_i915_private_t *dev_priv = dev->dev_private;
 515         struct drm_i915_master_private *master_priv =
 516                 dev->primary->master->driver_priv;
 517
 518         if (!master_priv->sarea_priv)
 519                 return -EINVAL;
 520
 521         DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
 522                           __func__,
 523                          dev_priv->current_page,
 524                          master_priv->sarea_priv->pf_current_page);
 525
 526         i915_kernel_lost_context(dev);
 527
 528         BEGIN_LP_RING(2);
 529         OUT_RING(MI_FLUSH | MI_READ_FLUSH);
 530         OUT_RING(0);
 531         ADVANCE_LP_RING();
 532
 533         BEGIN_LP_RING(6);
 534         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
 535         OUT_RING(0);
 536         if (dev_priv->current_page == 0) {
 537                 OUT_RING(dev_priv->back_offset);
 538                 dev_priv->current_page = 1;
 539         } else {
 540                 OUT_RING(dev_priv->front_offset);
 541                 dev_priv->current_page = 0;
 542         }
 543         OUT_RING(0);
 544         ADVANCE_LP_RING();
 545
 546         BEGIN_LP_RING(2);
 547         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
 548         OUT_RING(0);
 549         ADVANCE_LP_RING();
 550
 551         master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
 552
 553         BEGIN_LP_RING(4);
 554         OUT_RING(MI_STORE_DWORD_INDEX);
 555         OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 556         OUT_RING(dev_priv->counter);
 557         OUT_RING(0);
 558         ADVANCE_LP_RING();
 559
 560         master_priv->sarea_priv->pf_current_page = dev_priv->current_page;
 561         return 0;
 562 }
 563
 564 static int i915_quiescent(struct drm_device * dev)
 565 {
 566         drm_i915_private_t *dev_priv = dev->dev_private;
 567
 568         i915_kernel_lost_context(dev);
 569         return intel_wait_ring_buffer(dev, &dev_priv->render_ring,
 570                                       dev_priv->render_ring.size - 8);
 571 }
 572
 573 static int i915_flush_ioctl(struct drm_device *dev, void *data,
 574                             struct drm_file *file_priv)
 575 {
 576         int ret;
 577
 578         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 579
 580         mutex_lock(&dev->struct_mutex);
 581         ret = i915_quiescent(dev);
 582         mutex_unlock(&dev->struct_mutex);
 583
 584         return ret;
 585 }
 586
 587 static int i915_batchbuffer(struct drm_device *dev, void *data,
 588                             struct drm_file *file_priv)
 589 {
 590         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 591         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 592         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 593             master_priv->sarea_priv;
 594         drm_i915_batchbuffer_t *batch = data;
 595         int ret;
 596         struct drm_clip_rect *cliprects = NULL;
 597
 598         if (!dev_priv->allow_batchbuffer) {
 599                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 600                 return -EINVAL;
 601         }
 602
 603         DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
 604                         batch->start, batch->used, batch->num_cliprects);
 605
 606         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 607
 608         if (batch->num_cliprects < 0)
 609                 return -EINVAL;
 610
 611         if (batch->num_cliprects) {
 612                 cliprects = kcalloc(batch->num_cliprects,
 613                                     sizeof(struct drm_clip_rect),
 614                                     GFP_KERNEL);
 615                 if (cliprects == NULL)
 616                         return -ENOMEM;
 617
 618                 ret = copy_from_user(cliprects, batch->cliprects,
 619                                      batch->num_cliprects *
 620                                      sizeof(struct drm_clip_rect));
 621                 if (ret != 0) {
 622                         ret = -EFAULT;
 623                         goto fail_free;
 624                 }
 625         }
 626
 627         mutex_lock(&dev->struct_mutex);
 628         ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
 629         mutex_unlock(&dev->struct_mutex);
 630
 631         if (sarea_priv)
 632                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 633
 634 fail_free:
 635         kfree(cliprects);
 636
 637         return ret;
 638 }
 639
 640 static int i915_cmdbuffer(struct drm_device *dev, void *data,
 641                           struct drm_file *file_priv)
 642 {
 643         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 644         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 645         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
 646             master_priv->sarea_priv;
 647         drm_i915_cmdbuffer_t *cmdbuf = data;
 648         struct drm_clip_rect *cliprects = NULL;
 649         void *batch_data;
 650         int ret;
 651
 652         DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 653                         cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 654
 655         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 656
 657         if (cmdbuf->num_cliprects < 0)
 658                 return -EINVAL;
 659
 660         batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
 661         if (batch_data == NULL)
 662                 return -ENOMEM;
 663
 664         ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
 665         if (ret != 0) {
 666                 ret = -EFAULT;
 667                 goto fail_batch_free;
 668         }
 669
 670         if (cmdbuf->num_cliprects) {
 671                 cliprects = kcalloc(cmdbuf->num_cliprects,
 672                                     sizeof(struct drm_clip_rect), GFP_KERNEL);
 673                 if (cliprects == NULL) {
 674                         ret = -ENOMEM;
 675                         goto fail_batch_free;
 676                 }
 677
 678                 ret = copy_from_user(cliprects, cmdbuf->cliprects,
 679                                      cmdbuf->num_cliprects *
 680                                      sizeof(struct drm_clip_rect));
 681                 if (ret != 0) {
 682                         ret = -EFAULT;
 683                         goto fail_clip_free;
 684                 }
 685         }
 686
 687         mutex_lock(&dev->struct_mutex);
 688         ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
 689         mutex_unlock(&dev->struct_mutex);
 690         if (ret) {
 691                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 692                 goto fail_clip_free;
 693         }
 694
 695         if (sarea_priv)
 696                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 697
 698 fail_clip_free:
 699         kfree(cliprects);
 700 fail_batch_free:
 701         kfree(batch_data);
 702
 703         return ret;
 704 }
 705
 706 static int i915_flip_bufs(struct drm_device *dev, void *data,
 707                           struct drm_file *file_priv)
 708 {
 709         int ret;
 710
 711         DRM_DEBUG_DRIVER("%s\n", __func__);
 712
 713         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 714
 715         mutex_lock(&dev->struct_mutex);
 716         ret = i915_dispatch_flip(dev);
 717         mutex_unlock(&dev->struct_mutex);
 718
 719         return ret;
 720 }
 721
 722 static int i915_getparam(struct drm_device *dev, void *data,
 723                          struct drm_file *file_priv)
 724 {
 725         drm_i915_private_t *dev_priv = dev->dev_private;
 726         drm_i915_getparam_t *param = data;
 727         int value;
 728
 729         if (!dev_priv) {
 730                 DRM_ERROR("called with no initialization\n");
 731                 return -EINVAL;
 732         }
 733
 734         switch (param->param) {
 735         case I915_PARAM_IRQ_ACTIVE:
 736                 value = dev->pdev->irq ? 1 : 0;
 737                 break;
 738         case I915_PARAM_ALLOW_BATCHBUFFER:
 739                 value = dev_priv->allow_batchbuffer ? 1 : 0;
 740                 break;
 741         case I915_PARAM_LAST_DISPATCH:
 742                 value = READ_BREADCRUMB(dev_priv);
 743                 break;
 744         case I915_PARAM_CHIPSET_ID:
 745                 value = dev->pci_device;
 746                 break;
 747         case I915_PARAM_HAS_GEM:
 748                 value = dev_priv->has_gem;
 749                 break;
 750         case I915_PARAM_NUM_FENCES_AVAIL:
 751                 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
 752                 break;
 753         case I915_PARAM_HAS_OVERLAY:
 754                 value = dev_priv->overlay ? 1 : 0;
 755                 break;
 756         case I915_PARAM_HAS_PAGEFLIPPING:
 757                 value = 1;
 758                 break;
 759         case I915_PARAM_HAS_EXECBUF2:
 760                 /* depends on GEM */
 761                 value = dev_priv->has_gem;
 762                 break;
 763         case I915_PARAM_HAS_BSD:
 764                 value = HAS_BSD(dev);
 765                 break;
 766         default:
 767                 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
 768                                  param->param);
 769                 return -EINVAL;
 770         }
 771
 772         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
 773                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
 774                 return -EFAULT;
 775         }
 776
 777         return 0;
 778 }
 779
 780 static int i915_setparam(struct drm_device *dev, void *data,
 781                          struct drm_file *file_priv)
 782 {
 783         drm_i915_private_t *dev_priv = dev->dev_private;
 784         drm_i915_setparam_t *param = data;
 785
 786         if (!dev_priv) {
 787                 DRM_ERROR("called with no initialization\n");
 788                 return -EINVAL;
 789         }
 790
 791         switch (param->param) {
 792         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
 793                 break;
 794         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
 795                 dev_priv->tex_lru_log_granularity = param->value;
 796                 break;
 797         case I915_SETPARAM_ALLOW_BATCHBUFFER:
 798                 dev_priv->allow_batchbuffer = param->value;
 799                 break;
 800         case I915_SETPARAM_NUM_USED_FENCES:
 801                 if (param->value > dev_priv->num_fence_regs ||
 802                     param->value < 0)
 803                         return -EINVAL;
 804                 /* Userspace can use first N regs */
 805                 dev_priv->fence_reg_start = param->value;
 806                 break;
 807         default:
 808                 DRM_DEBUG_DRIVER("unknown parameter %d\n",
 809                                         param->param);
 810                 return -EINVAL;
 811         }
 812
 813         return 0;
 814 }
 815
 816 static int i915_set_status_page(struct drm_device *dev, void *data,
 817                                 struct drm_file *file_priv)
 818 {
 819         drm_i915_private_t *dev_priv = dev->dev_private;
 820         drm_i915_hws_addr_t *hws = data;
 821         struct intel_ring_buffer *ring = &dev_priv->render_ring;
 822
 823         if (!I915_NEED_GFX_HWS(dev))
 824                 return -EINVAL;
 825
 826         if (!dev_priv) {
 827                 DRM_ERROR("called with no initialization\n");
 828                 return -EINVAL;
 829         }
 830
 831         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
 832                 WARN(1, "tried to set status page when mode setting active\n");
 833                 return 0;
 834         }
 835
 836         DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
 837
 838         ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
 839
 840         dev_priv->hws_map.offset = dev->agp->base + hws->addr;
 841         dev_priv->hws_map.size = 4*1024;
 842         dev_priv->hws_map.type = 0;
 843         dev_priv->hws_map.flags = 0;
 844         dev_priv->hws_map.mtrr = 0;
 845
 846         drm_core_ioremap_wc(&dev_priv->hws_map, dev);
 847         if (dev_priv->hws_map.handle == NULL) {
 848                 i915_dma_cleanup(dev);
 849                 ring->status_page.gfx_addr = 0;
 850                 DRM_ERROR("can not ioremap virtual address for"
 851                                 " G33 hw status page\n");
 852                 return -ENOMEM;
 853         }
 854         ring->status_page.page_addr = dev_priv->hws_map.handle;
 855         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
 856         I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
 857
 858         DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
 859                          ring->status_page.gfx_addr);
 860         DRM_DEBUG_DRIVER("load hws at %p\n",
 861                          ring->status_page.page_addr);
 862         return 0;
 863 }
 864
 865 static int i915_get_bridge_dev(struct drm_device *dev)
 866 {
 867         struct drm_i915_private *dev_priv = dev->dev_private;
 868
 869         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
 870         if (!dev_priv->bridge_dev) {
 871                 DRM_ERROR("bridge device not found\n");
 872                 return -1;
 873         }
 874         return 0;
 875 }
 876
 877 #define MCHBAR_I915 0x44
 878 #define MCHBAR_I965 0x48
 879 #define MCHBAR_SIZE (4*4096)
 880
 881 #define DEVEN_REG 0x54
 882 #define   DEVEN_MCHBAR_EN (1 << 28)
 883
 884 /* Allocate space for the MCH regs if needed, return nonzero on error */
 885 static int
 886 intel_alloc_mchbar_resource(struct drm_device *dev)
 887 {
 888         drm_i915_private_t *dev_priv = dev->dev_private;
 889         int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 890         u32 temp_lo, temp_hi = 0;
 891         u64 mchbar_addr;
 892         int ret;
 893
 894         if (INTEL_INFO(dev)->gen >= 4)
 895                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 896         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 897         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 898
 899         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 900 #ifdef CONFIG_PNP
 901         if (mchbar_addr &&
 902             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 903                 return 0;
 904 #endif
 905
 906         /* Get some space for it */
 907         dev_priv->mch_res.name = "i915 MCHBAR";
 908         dev_priv->mch_res.flags = IORESOURCE_MEM;
 909         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
 910                                      &dev_priv->mch_res,
 911                                      MCHBAR_SIZE, MCHBAR_SIZE,
 912                                      PCIBIOS_MIN_MEM,
 913                                      0, pcibios_align_resource,
 914                                      dev_priv->bridge_dev);
 915         if (ret) {
 916                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
 917                 dev_priv->mch_res.start = 0;
 918                 return ret;
 919         }
 920
 921         if (INTEL_INFO(dev)->gen >= 4)
 922                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 923                                        upper_32_bits(dev_priv->mch_res.start));
 924
 925         pci_write_config_dword(dev_priv->bridge_dev, reg,
 926                                lower_32_bits(dev_priv->mch_res.start));
 927         return 0;
 928 }
 929
 930 /* Setup MCHBAR if possible, return true if we should disable it again */
 931 static void
 932 intel_setup_mchbar(struct drm_device *dev)
 933 {
 934         drm_i915_private_t *dev_priv = dev->dev_private;
 935         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 936         u32 temp;
 937         bool enabled;
 938
 939         dev_priv->mchbar_need_disable = false;
 940
 941         if (IS_I915G(dev) || IS_I915GM(dev)) {
 942                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
 943                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 944         } else {
 945                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 946                 enabled = temp & 1;
 947         }
 948
 949         /* If it's already enabled, don't have to do anything */
 950         if (enabled)
 951                 return;
 952
 953         if (intel_alloc_mchbar_resource(dev))
 954                 return;
 955
 956         dev_priv->mchbar_need_disable = true;
 957
 958         /* Space is allocated or reserved, so enable it. */
 959         if (IS_I915G(dev) || IS_I915GM(dev)) {
 960                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
 961                                        temp | DEVEN_MCHBAR_EN);
 962         } else {
 963                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 964                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 965         }
 966 }
 967
 968 static void
 969 intel_teardown_mchbar(struct drm_device *dev)
 970 {
 971         drm_i915_private_t *dev_priv = dev->dev_private;
 972         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 973         u32 temp;
 974
 975         if (dev_priv->mchbar_need_disable) {
 976                 if (IS_I915G(dev) || IS_I915GM(dev)) {
 977                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
 978                         temp &= ~DEVEN_MCHBAR_EN;
 979                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
 980                 } else {
 981                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 982                         temp &= ~1;
 983                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
 984                 }
 985         }
 986
 987         if (dev_priv->mch_res.start)
 988                 release_resource(&dev_priv->mch_res);
 989 }
 990
 991 #define PTE_ADDRESS_MASK                0xfffff000
 992 #define PTE_ADDRESS_MASK_HIGH           0x000000f0 /* i915+ */
 993 #define PTE_MAPPING_TYPE_UNCACHED       (0 << 1)
 994 #define PTE_MAPPING_TYPE_DCACHE         (1 << 1) /* i830 only */
 995 #define PTE_MAPPING_TYPE_CACHED         (3 << 1)
 996 #define PTE_MAPPING_TYPE_MASK           (3 << 1)
 997 #define PTE_VALID                       (1 << 0)
 998
 999 /**
1000  * i915_gtt_to_phys - take a GTT address and turn it into a physical one
1001  * @dev: drm device
1002  * @gtt_addr: address to translate
1003  *
1004  * Some chip functions require allocations from stolen space but need the
1005  * physical address of the memory in question.  We use this routine
1006  * to get a physical address suitable for register programming from a given
1007  * GTT address.
1008  */
1009 static unsigned long i915_gtt_to_phys(struct drm_device *dev,
1010                                       unsigned long gtt_addr)
1011 {
1012         unsigned long *gtt;
1013         unsigned long entry, phys;
1014         int gtt_bar = IS_GEN2(dev) ? 1 : 0;
1015         int gtt_offset, gtt_size;
1016
1017         if (INTEL_INFO(dev)->gen >= 4) {
1018                 if (IS_G4X(dev) || INTEL_INFO(dev)->gen > 4) {
1019                         gtt_offset = 2*1024*1024;
1020                         gtt_size = 2*1024*1024;
1021                 } else {
1022                         gtt_offset = 512*1024;
1023                         gtt_size = 512*1024;
1024                 }
1025         } else {
1026                 gtt_bar = 3;
1027                 gtt_offset = 0;
1028                 gtt_size = pci_resource_len(dev->pdev, gtt_bar);
1029         }
1030
1031         gtt = ioremap_wc(pci_resource_start(dev->pdev, gtt_bar) + gtt_offset,
1032                          gtt_size);
1033         if (!gtt) {
1034                 DRM_ERROR("ioremap of GTT failed\n");
1035                 return 0;
1036         }
1037
1038         entry = *(volatile u32 *)(gtt + (gtt_addr / 1024));
1039
1040         DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, PTE: 0x%08lx\n", gtt_addr, entry);
1041
1042         /* Mask out these reserved bits on this hardware. */
1043         if (INTEL_INFO(dev)->gen < 4 && !IS_G33(dev))
1044                 entry &= ~PTE_ADDRESS_MASK_HIGH;
1045
1046         /* If it's not a mapping type we know, then bail. */
1047         if ((entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_UNCACHED &&
1048             (entry & PTE_MAPPING_TYPE_MASK) != PTE_MAPPING_TYPE_CACHED) {
1049                 iounmap(gtt);
1050                 return 0;
1051         }
1052
1053         if (!(entry & PTE_VALID)) {
1054                 DRM_ERROR("bad GTT entry in stolen space\n");
1055                 iounmap(gtt);
1056                 return 0;
1057         }
1058
1059         iounmap(gtt);
1060
1061         phys =(entry & PTE_ADDRESS_MASK) |
1062                 ((uint64_t)(entry & PTE_ADDRESS_MASK_HIGH) << (32 - 4));
1063
1064         DRM_DEBUG_DRIVER("GTT addr: 0x%08lx, phys addr: 0x%08lx\n", gtt_addr, phys);
1065
1066         return phys;
1067 }
1068
1069 static void i915_warn_stolen(struct drm_device *dev)
1070 {
1071         DRM_ERROR("not enough stolen space for compressed buffer, disabling\n");
1072         DRM_ERROR("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n");
1073 }
1074
1075 static void i915_setup_compression(struct drm_device *dev, int size)
1076 {
1077         struct drm_i915_private *dev_priv = dev->dev_private;
1078         struct drm_mm_node *compressed_fb, *uninitialized_var(compressed_llb);
1079         unsigned long cfb_base;
1080         unsigned long ll_base = 0;
1081
1082         /* Leave 1M for line length buffer & misc. */
1083         compressed_fb = drm_mm_search_free(&dev_priv->mm.vram, size, 4096, 0);
1084         if (!compressed_fb) {
1085                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1086                 i915_warn_stolen(dev);
1087                 return;
1088         }
1089
1090         compressed_fb = drm_mm_get_block(compressed_fb, size, 4096);
1091         if (!compressed_fb) {
1092                 i915_warn_stolen(dev);
1093                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1094                 return;
1095         }
1096
1097         cfb_base = i915_gtt_to_phys(dev, compressed_fb->start);
1098         if (!cfb_base) {
1099                 DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
1100                 drm_mm_put_block(compressed_fb);
1101         }
1102
1103         if (!(IS_GM45(dev) || IS_IRONLAKE_M(dev))) {
1104                 compressed_llb = drm_mm_search_free(&dev_priv->mm.vram, 4096,
1105                                                     4096, 0);
1106                 if (!compressed_llb) {
1107                         i915_warn_stolen(dev);
1108                         return;
1109                 }
1110
1111                 compressed_llb = drm_mm_get_block(compressed_llb, 4096, 4096);
1112                 if (!compressed_llb) {
1113                         i915_warn_stolen(dev);
1114                         return;
1115                 }
1116
1117                 ll_base = i915_gtt_to_phys(dev, compressed_llb->start);
1118                 if (!ll_base) {
1119                         DRM_ERROR("failed to get stolen phys addr, disabling FBC\n");
1120                         drm_mm_put_block(compressed_fb);
1121                         drm_mm_put_block(compressed_llb);
1122                 }
1123         }
1124
1125         dev_priv->cfb_size = size;
1126
1127         intel_disable_fbc(dev);
1128         dev_priv->compressed_fb = compressed_fb;
1129         if (IS_IRONLAKE_M(dev))
1130                 I915_WRITE(ILK_DPFC_CB_BASE, compressed_fb->start);
1131         else if (IS_GM45(dev)) {
1132                 I915_WRITE(DPFC_CB_BASE, compressed_fb->start);
1133         } else {
1134                 I915_WRITE(FBC_CFB_BASE, cfb_base);
1135                 I915_WRITE(FBC_LL_BASE, ll_base);
1136                 dev_priv->compressed_llb = compressed_llb;
1137         }
1138
1139         DRM_DEBUG_KMS("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n", cfb_base,
1140                   ll_base, size >> 20);
1141 }
1142
1143 static void i915_cleanup_compression(struct drm_device *dev)
1144 {
1145         struct drm_i915_private *dev_priv = dev->dev_private;
1146
1147         drm_mm_put_block(dev_priv->compressed_fb);
1148         if (dev_priv->compressed_llb)
1149                 drm_mm_put_block(dev_priv->compressed_llb);
1150 }
1151
1152 /* true = enable decode, false = disable decoder */
1153 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1154 {
1155         struct drm_device *dev = cookie;
1156
1157         intel_modeset_vga_set_state(dev, state);
1158         if (state)
1159                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1160                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1161         else
1162                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1163 }
1164
1165 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1166 {
1167         struct drm_device *dev = pci_get_drvdata(pdev);
1168         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1169         if (state == VGA_SWITCHEROO_ON) {
1170                 printk(KERN_INFO "i915: switched on\n");
1171                 /* i915 resume handler doesn't set to D0 */
1172                 pci_set_power_state(dev->pdev, PCI_D0);
1173                 i915_resume(dev);
1174         } else {
1175                 printk(KERN_ERR "i915: switched off\n");
1176                 i915_suspend(dev, pmm);
1177         }
1178 }
1179
1180 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1181 {
1182         struct drm_device *dev = pci_get_drvdata(pdev);
1183         bool can_switch;
1184
1185         spin_lock(&dev->count_lock);
1186         can_switch = (dev->open_count == 0);
1187         spin_unlock(&dev->count_lock);
1188         return can_switch;
1189 }
1190
1191 static int i915_load_modeset_init(struct drm_device *dev,
1192                                   unsigned long prealloc_size,
1193                                   unsigned long agp_size)
1194 {
1195         struct drm_i915_private *dev_priv = dev->dev_private;
1196         int ret = 0;
1197
1198         /* Basic memrange allocator for stolen space (aka mm.vram) */
1199         drm_mm_init(&dev_priv->mm.vram, 0, prealloc_size);
1200
1201         /* Let GEM Manage from end of prealloc space to end of aperture.
1202          *
1203          * However, leave one page at the end still bound to the scratch page.
1204          * There are a number of places where the hardware apparently
1205          * prefetches past the end of the object, and we've seen multiple
1206          * hangs with the GPU head pointer stuck in a batchbuffer bound
1207          * at the last page of the aperture.  One page should be enough to
1208          * keep any prefetching inside of the aperture.
1209          */
1210         i915_gem_do_init(dev, prealloc_size, agp_size - 4096);
1211
1212         mutex_lock(&dev->struct_mutex);
1213         ret = i915_gem_init_ringbuffer(dev);
1214         mutex_unlock(&dev->struct_mutex);
1215         if (ret)
1216                 goto out;
1217
1218         /* Try to set up FBC with a reasonable compressed buffer size */
1219         if (I915_HAS_FBC(dev) && i915_powersave) {
1220                 int cfb_size;
1221
1222                 /* Try to get an 8M buffer... */
1223                 if (prealloc_size > (9*1024*1024))
1224                         cfb_size = 8*1024*1024;
1225                 else /* fall back to 7/8 of the stolen space */
1226                         cfb_size = prealloc_size * 7 / 8;
1227                 i915_setup_compression(dev, cfb_size);
1228         }
1229
1230         /* Allow hardware batchbuffers unless told otherwise.
1231          */
1232         dev_priv->allow_batchbuffer = 1;
1233
1234         ret = intel_parse_bios(dev);
1235         if (ret)
1236                 DRM_INFO("failed to find VBIOS tables\n");
1237
1238         /* if we have > 1 VGA cards, then disable the radeon VGA resources */
1239         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1240         if (ret)
1241                 goto cleanup_ringbuffer;
1242
1243         intel_register_dsm_handler();
1244
1245         ret = vga_switcheroo_register_client(dev->pdev,
1246                                              i915_switcheroo_set_state,
1247                                              i915_switcheroo_can_switch);
1248         if (ret)
1249                 goto cleanup_vga_client;
1250
1251         /* IIR "flip pending" bit means done if this bit is set */
1252         if (IS_GEN3(dev) && (I915_READ(ECOSKPD) & ECO_FLIP_DONE))
1253                 dev_priv->flip_pending_is_done = true;
1254
1255         intel_modeset_init(dev);
1256
1257         ret = drm_irq_install(dev);
1258         if (ret)
1259                 goto cleanup_vga_switcheroo;
1260
1261         /* Always safe in the mode setting case. */
1262         /* FIXME: do pre/post-mode set stuff in core KMS code */
1263         dev->vblank_disable_allowed = 1;
1264
1265         ret = intel_fbdev_init(dev);
1266         if (ret)
1267                 goto cleanup_irq;
1268
1269         drm_kms_helper_poll_init(dev);
1270
1271         /* We're off and running w/KMS */
1272         dev_priv->mm.suspended = 0;
1273
1274         return 0;
1275
1276 cleanup_irq:
1277         drm_irq_uninstall(dev);
1278 cleanup_vga_switcheroo:
1279         vga_switcheroo_unregister_client(dev->pdev);
1280 cleanup_vga_client:
1281         vga_client_register(dev->pdev, NULL, NULL, NULL);
1282 cleanup_ringbuffer:
1283         mutex_lock(&dev->struct_mutex);
1284         i915_gem_cleanup_ringbuffer(dev);
1285         mutex_unlock(&dev->struct_mutex);
1286 out:
1287         return ret;
1288 }
1289
1290 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1291 {
1292         struct drm_i915_master_private *master_priv;
1293
1294         master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1295         if (!master_priv)
1296                 return -ENOMEM;
1297
1298         master->driver_priv = master_priv;
1299         return 0;
1300 }
1301
1302 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1303 {
1304         struct drm_i915_master_private *master_priv = master->driver_priv;
1305
1306         if (!master_priv)
1307                 return;
1308
1309         kfree(master_priv);
1310
1311         master->driver_priv = NULL;
1312 }
1313
1314 static void i915_pineview_get_mem_freq(struct drm_device *dev)
1315 {
1316         drm_i915_private_t *dev_priv = dev->dev_private;
1317         u32 tmp;
1318
1319         tmp = I915_READ(CLKCFG);
1320
1321         switch (tmp & CLKCFG_FSB_MASK) {
1322         case CLKCFG_FSB_533:
1323                 dev_priv->fsb_freq = 533; /* 133*4 */
1324                 break;
1325         case CLKCFG_FSB_800:
1326                 dev_priv->fsb_freq = 800; /* 200*4 */
1327                 break;
1328         case CLKCFG_FSB_667:
1329                 dev_priv->fsb_freq =  667; /* 167*4 */
1330                 break;
1331         case CLKCFG_FSB_400:
1332                 dev_priv->fsb_freq = 400; /* 100*4 */
1333                 break;
1334         }
1335
1336         switch (tmp & CLKCFG_MEM_MASK) {
1337         case CLKCFG_MEM_533:
1338                 dev_priv->mem_freq = 533;
1339                 break;
1340         case CLKCFG_MEM_667:
1341                 dev_priv->mem_freq = 667;
1342                 break;
1343         case CLKCFG_MEM_800:
1344                 dev_priv->mem_freq = 800;
1345                 break;
1346         }
1347
1348         /* detect pineview DDR3 setting */
1349         tmp = I915_READ(CSHRDDR3CTL);
1350         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
1351 }
1352
1353 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
1354 {
1355         drm_i915_private_t *dev_priv = dev->dev_private;
1356         u16 ddrpll, csipll;
1357
1358         ddrpll = I915_READ16(DDRMPLL1);
1359         csipll = I915_READ16(CSIPLL0);
1360
1361         switch (ddrpll & 0xff) {
1362         case 0xc:
1363                 dev_priv->mem_freq = 800;
1364                 break;
1365         case 0x10:
1366                 dev_priv->mem_freq = 1066;
1367                 break;
1368         case 0x14:
1369                 dev_priv->mem_freq = 1333;
1370                 break;
1371         case 0x18:
1372                 dev_priv->mem_freq = 1600;
1373                 break;
1374         default:
1375                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
1376                                  ddrpll & 0xff);
1377                 dev_priv->mem_freq = 0;
1378                 break;
1379         }
1380
1381         dev_priv->r_t = dev_priv->mem_freq;
1382
1383         switch (csipll & 0x3ff) {
1384         case 0x00c:
1385                 dev_priv->fsb_freq = 3200;
1386                 break;
1387         case 0x00e:
1388                 dev_priv->fsb_freq = 3733;
1389                 break;
1390         case 0x010:
1391                 dev_priv->fsb_freq = 4266;
1392                 break;
1393         case 0x012:
1394                 dev_priv->fsb_freq = 4800;
1395                 break;
1396         case 0x014:
1397                 dev_priv->fsb_freq = 5333;
1398                 break;
1399         case 0x016:
1400                 dev_priv->fsb_freq = 5866;
1401                 break;
1402         case 0x018:
1403                 dev_priv->fsb_freq = 6400;
1404                 break;
1405         default:
1406                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
1407                                  csipll & 0x3ff);
1408                 dev_priv->fsb_freq = 0;
1409                 break;
1410         }
1411
1412         if (dev_priv->fsb_freq == 3200) {
1413                 dev_priv->c_m = 0;
1414         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
1415                 dev_priv->c_m = 1;
1416         } else {
1417                 dev_priv->c_m = 2;
1418         }
1419 }
1420
1421 struct v_table {
1422         u8 vid;
1423         unsigned long vd; /* in .1 mil */
1424         unsigned long vm; /* in .1 mil */
1425         u8 pvid;
1426 };
1427
1428 static struct v_table v_table[] = {
1429         { 0, 16125, 15000, 0x7f, },
1430         { 1, 16000, 14875, 0x7e, },
1431         { 2, 15875, 14750, 0x7d, },
1432         { 3, 15750, 14625, 0x7c, },
1433         { 4, 15625, 14500, 0x7b, },
1434         { 5, 15500, 14375, 0x7a, },
1435         { 6, 15375, 14250, 0x79, },
1436         { 7, 15250, 14125, 0x78, },
1437         { 8, 15125, 14000, 0x77, },
1438         { 9, 15000, 13875, 0x76, },
1439         { 10, 14875, 13750, 0x75, },
1440         { 11, 14750, 13625, 0x74, },
1441         { 12, 14625, 13500, 0x73, },
1442         { 13, 14500, 13375, 0x72, },
1443         { 14, 14375, 13250, 0x71, },
1444         { 15, 14250, 13125, 0x70, },
1445         { 16, 14125, 13000, 0x6f, },
1446         { 17, 14000, 12875, 0x6e, },
1447         { 18, 13875, 12750, 0x6d, },
1448         { 19, 13750, 12625, 0x6c, },
1449         { 20, 13625, 12500, 0x6b, },
1450         { 21, 13500, 12375, 0x6a, },
1451         { 22, 13375, 12250, 0x69, },
1452         { 23, 13250, 12125, 0x68, },
1453         { 24, 13125, 12000, 0x67, },
1454         { 25, 13000, 11875, 0x66, },
1455         { 26, 12875, 11750, 0x65, },
1456         { 27, 12750, 11625, 0x64, },
1457         { 28, 12625, 11500, 0x63, },
1458         { 29, 12500, 11375, 0x62, },
1459         { 30, 12375, 11250, 0x61, },
1460         { 31, 12250, 11125, 0x60, },
1461         { 32, 12125, 11000, 0x5f, },
1462         { 33, 12000, 10875, 0x5e, },
1463         { 34, 11875, 10750, 0x5d, },
1464         { 35, 11750, 10625, 0x5c, },
1465         { 36, 11625, 10500, 0x5b, },
1466         { 37, 11500, 10375, 0x5a, },
1467         { 38, 11375, 10250, 0x59, },
1468         { 39, 11250, 10125, 0x58, },
1469         { 40, 11125, 10000, 0x57, },
1470         { 41, 11000, 9875, 0x56, },
1471         { 42, 10875, 9750, 0x55, },
1472         { 43, 10750, 9625, 0x54, },
1473         { 44, 10625, 9500, 0x53, },
1474         { 45, 10500, 9375, 0x52, },
1475         { 46, 10375, 9250, 0x51, },
1476         { 47, 10250, 9125, 0x50, },
1477         { 48, 10125, 9000, 0x4f, },
1478         { 49, 10000, 8875, 0x4e, },
1479         { 50, 9875, 8750, 0x4d, },
1480         { 51, 9750, 8625, 0x4c, },
1481         { 52, 9625, 8500, 0x4b, },
1482         { 53, 9500, 8375, 0x4a, },
1483         { 54, 9375, 8250, 0x49, },
1484         { 55, 9250, 8125, 0x48, },
1485         { 56, 9125, 8000, 0x47, },
1486         { 57, 9000, 7875, 0x46, },
1487         { 58, 8875, 7750, 0x45, },
1488         { 59, 8750, 7625, 0x44, },
1489         { 60, 8625, 7500, 0x43, },
1490         { 61, 8500, 7375, 0x42, },
1491         { 62, 8375, 7250, 0x41, },
1492         { 63, 8250, 7125, 0x40, },
1493         { 64, 8125, 7000, 0x3f, },
1494         { 65, 8000, 6875, 0x3e, },
1495         { 66, 7875, 6750, 0x3d, },
1496         { 67, 7750, 6625, 0x3c, },
1497         { 68, 7625, 6500, 0x3b, },
1498         { 69, 7500, 6375, 0x3a, },
1499         { 70, 7375, 6250, 0x39, },
1500         { 71, 7250, 6125, 0x38, },
1501         { 72, 7125, 6000, 0x37, },
1502         { 73, 7000, 5875, 0x36, },
1503         { 74, 6875, 5750, 0x35, },
1504         { 75, 6750, 5625, 0x34, },
1505         { 76, 6625, 5500, 0x33, },
1506         { 77, 6500, 5375, 0x32, },
1507         { 78, 6375, 5250, 0x31, },
1508         { 79, 6250, 5125, 0x30, },
1509         { 80, 6125, 5000, 0x2f, },
1510         { 81, 6000, 4875, 0x2e, },
1511         { 82, 5875, 4750, 0x2d, },
1512         { 83, 5750, 4625, 0x2c, },
1513         { 84, 5625, 4500, 0x2b, },
1514         { 85, 5500, 4375, 0x2a, },
1515         { 86, 5375, 4250, 0x29, },
1516         { 87, 5250, 4125, 0x28, },
1517         { 88, 5125, 4000, 0x27, },
1518         { 89, 5000, 3875, 0x26, },
1519         { 90, 4875, 3750, 0x25, },
1520         { 91, 4750, 3625, 0x24, },
1521         { 92, 4625, 3500, 0x23, },
1522         { 93, 4500, 3375, 0x22, },
1523         { 94, 4375, 3250, 0x21, },
1524         { 95, 4250, 3125, 0x20, },
1525         { 96, 4125, 3000, 0x1f, },
1526         { 97, 4125, 3000, 0x1e, },
1527         { 98, 4125, 3000, 0x1d, },
1528         { 99, 4125, 3000, 0x1c, },
1529         { 100, 4125, 3000, 0x1b, },
1530         { 101, 4125, 3000, 0x1a, },
1531         { 102, 4125, 3000, 0x19, },
1532         { 103, 4125, 3000, 0x18, },
1533         { 104, 4125, 3000, 0x17, },
1534         { 105, 4125, 3000, 0x16, },
1535         { 106, 4125, 3000, 0x15, },
1536         { 107, 4125, 3000, 0x14, },
1537         { 108, 4125, 3000, 0x13, },
1538         { 109, 4125, 3000, 0x12, },
1539         { 110, 4125, 3000, 0x11, },
1540         { 111, 4125, 3000, 0x10, },
1541         { 112, 4125, 3000, 0x0f, },
1542         { 113, 4125, 3000, 0x0e, },
1543         { 114, 4125, 3000, 0x0d, },
1544         { 115, 4125, 3000, 0x0c, },
1545         { 116, 4125, 3000, 0x0b, },
1546         { 117, 4125, 3000, 0x0a, },
1547         { 118, 4125, 3000, 0x09, },
1548         { 119, 4125, 3000, 0x08, },
1549         { 120, 1125, 0, 0x07, },
1550         { 121, 1000, 0, 0x06, },
1551         { 122, 875, 0, 0x05, },
1552         { 123, 750, 0, 0x04, },
1553         { 124, 625, 0, 0x03, },
1554         { 125, 500, 0, 0x02, },
1555         { 126, 375, 0, 0x01, },
1556         { 127, 0, 0, 0x00, },
1557 };
1558
1559 struct cparams {
1560         int i;
1561         int t;
1562         int m;
1563         int c;
1564 };
1565
1566 static struct cparams cparams[] = {
1567         { 1, 1333, 301, 28664 },
1568         { 1, 1066, 294, 24460 },
1569         { 1, 800, 294, 25192 },
1570         { 0, 1333, 276, 27605 },
1571         { 0, 1066, 276, 27605 },
1572         { 0, 800, 231, 23784 },
1573 };
1574
1575 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
1576 {
1577         u64 total_count, diff, ret;
1578         u32 count1, count2, count3, m = 0, c = 0;
1579         unsigned long now = jiffies_to_msecs(jiffies), diff1;
1580         int i;
1581
1582         diff1 = now - dev_priv->last_time1;
1583
1584         count1 = I915_READ(DMIEC);
1585         count2 = I915_READ(DDREC);
1586         count3 = I915_READ(CSIEC);
1587
1588         total_count = count1 + count2 + count3;
1589
1590         /* FIXME: handle per-counter overflow */
1591         if (total_count < dev_priv->last_count1) {
1592                 diff = ~0UL - dev_priv->last_count1;
1593                 diff += total_count;
1594         } else {
1595                 diff = total_count - dev_priv->last_count1;
1596         }
1597
1598         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
1599                 if (cparams[i].i == dev_priv->c_m &&
1600                     cparams[i].t == dev_priv->r_t) {
1601                         m = cparams[i].m;
1602                         c = cparams[i].c;
1603                         break;
1604                 }
1605         }
1606
1607         diff = div_u64(diff, diff1);
1608         ret = ((m * diff) + c);
1609         ret = div_u64(ret, 10);
1610
1611         dev_priv->last_count1 = total_count;
1612         dev_priv->last_time1 = now;
1613
1614         return ret;
1615 }
1616
1617 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
1618 {
1619         unsigned long m, x, b;
1620         u32 tsfs;
1621
1622         tsfs = I915_READ(TSFS);
1623
1624         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
1625         x = I915_READ8(TR1);
1626
1627         b = tsfs & TSFS_INTR_MASK;
1628
1629         return ((m * x) / 127) - b;
1630 }
1631
1632 static unsigned long pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
1633 {
1634         unsigned long val = 0;
1635         int i;
1636
1637         for (i = 0; i < ARRAY_SIZE(v_table); i++) {
1638                 if (v_table[i].pvid == pxvid) {
1639                         if (IS_MOBILE(dev_priv->dev))
1640                                 val = v_table[i].vm;
1641                         else
1642                                 val = v_table[i].vd;
1643                 }
1644         }
1645
1646         return val;
1647 }
1648
1649 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
1650 {
1651         struct timespec now, diff1;
1652         u64 diff;
1653         unsigned long diffms;
1654         u32 count;
1655
1656         getrawmonotonic(&now);
1657         diff1 = timespec_sub(now, dev_priv->last_time2);
1658
1659         /* Don't divide by 0 */
1660         diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
1661         if (!diffms)
1662                 return;
1663
1664         count = I915_READ(GFXEC);
1665
1666         if (count < dev_priv->last_count2) {
1667                 diff = ~0UL - dev_priv->last_count2;
1668                 diff += count;
1669         } else {
1670                 diff = count - dev_priv->last_count2;
1671         }
1672
1673         dev_priv->last_count2 = count;
1674         dev_priv->last_time2 = now;
1675
1676         /* More magic constants... */
1677         diff = diff * 1181;
1678         diff = div_u64(diff, diffms * 10);
1679         dev_priv->gfx_power = diff;
1680 }
1681
1682 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
1683 {
1684         unsigned long t, corr, state1, corr2, state2;
1685         u32 pxvid, ext_v;
1686
1687         pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->cur_delay * 4));
1688         pxvid = (pxvid >> 24) & 0x7f;
1689         ext_v = pvid_to_extvid(dev_priv, pxvid);
1690
1691         state1 = ext_v;
1692
1693         t = i915_mch_val(dev_priv);
1694
1695         /* Revel in the empirically derived constants */
1696
1697         /* Correction factor in 1/100000 units */
1698         if (t > 80)
1699                 corr = ((t * 2349) + 135940);
1700         else if (t >= 50)
1701                 corr = ((t * 964) + 29317);
1702         else /* < 50 */
1703                 corr = ((t * 301) + 1004);
1704
1705         corr = corr * ((150142 * state1) / 10000 - 78642);
1706         corr /= 100000;
1707         corr2 = (corr * dev_priv->corr);
1708
1709         state2 = (corr2 * state1) / 10000;
1710         state2 /= 100; /* convert to mW */
1711
1712         i915_update_gfx_val(dev_priv);
1713
1714         return dev_priv->gfx_power + state2;
1715 }
1716
1717 /* Global for IPS driver to get at the current i915 device */
1718 static struct drm_i915_private *i915_mch_dev;
1719 /*
1720  * Lock protecting IPS related data structures
1721  *   - i915_mch_dev
1722  *   - dev_priv->max_delay
1723  *   - dev_priv->min_delay
1724  *   - dev_priv->fmax
1725  *   - dev_priv->gpu_busy
1726  */
1727 static DEFINE_SPINLOCK(mchdev_lock);
1728
1729 /**
1730  * i915_read_mch_val - return value for IPS use
1731  *
1732  * Calculate and return a value for the IPS driver to use when deciding whether
1733  * we have thermal and power headroom to increase CPU or GPU power budget.
1734  */
1735 unsigned long i915_read_mch_val(void)
1736 {
1737         struct drm_i915_private *dev_priv;
1738         unsigned long chipset_val, graphics_val, ret = 0;
1739
1740         spin_lock(&mchdev_lock);
1741         if (!i915_mch_dev)
1742                 goto out_unlock;
1743         dev_priv = i915_mch_dev;
1744
1745         chipset_val = i915_chipset_val(dev_priv);
1746         graphics_val = i915_gfx_val(dev_priv);
1747
1748         ret = chipset_val + graphics_val;
1749
1750 out_unlock:
1751         spin_unlock(&mchdev_lock);
1752
1753         return ret;
1754 }
1755 EXPORT_SYMBOL_GPL(i915_read_mch_val);
1756
1757 /**
1758  * i915_gpu_raise - raise GPU frequency limit
1759  *
1760  * Raise the limit; IPS indicates we have thermal headroom.
1761  */
1762 bool i915_gpu_raise(void)
1763 {
1764         struct drm_i915_private *dev_priv;
1765         bool ret = true;
1766
1767         spin_lock(&mchdev_lock);
1768         if (!i915_mch_dev) {
1769                 ret = false;
1770                 goto out_unlock;
1771         }
1772         dev_priv = i915_mch_dev;
1773
1774         if (dev_priv->max_delay > dev_priv->fmax)
1775                 dev_priv->max_delay--;
1776
1777 out_unlock:
1778         spin_unlock(&mchdev_lock);
1779
1780         return ret;
1781 }
1782 EXPORT_SYMBOL_GPL(i915_gpu_raise);
1783
1784 /**
1785  * i915_gpu_lower - lower GPU frequency limit
1786  *
1787  * IPS indicates we're close to a thermal limit, so throttle back the GPU
1788  * frequency maximum.
1789  */
1790 bool i915_gpu_lower(void)
1791 {
1792         struct drm_i915_private *dev_priv;
1793         bool ret = true;
1794
1795         spin_lock(&mchdev_lock);
1796         if (!i915_mch_dev) {
1797                 ret = false;
1798                 goto out_unlock;
1799         }
1800         dev_priv = i915_mch_dev;
1801
1802         if (dev_priv->max_delay < dev_priv->min_delay)
1803                 dev_priv->max_delay++;
1804
1805 out_unlock:
1806         spin_unlock(&mchdev_lock);
1807
1808         return ret;
1809 }
1810 EXPORT_SYMBOL_GPL(i915_gpu_lower);
1811
1812 /**
1813  * i915_gpu_busy - indicate GPU business to IPS
1814  *
1815  * Tell the IPS driver whether or not the GPU is busy.
1816  */
1817 bool i915_gpu_busy(void)
1818 {
1819         struct drm_i915_private *dev_priv;
1820         bool ret = false;
1821
1822         spin_lock(&mchdev_lock);
1823         if (!i915_mch_dev)
1824                 goto out_unlock;
1825         dev_priv = i915_mch_dev;
1826
1827         ret = dev_priv->busy;
1828
1829 out_unlock:
1830         spin_unlock(&mchdev_lock);
1831
1832         return ret;
1833 }
1834 EXPORT_SYMBOL_GPL(i915_gpu_busy);
1835
1836 /**
1837  * i915_gpu_turbo_disable - disable graphics turbo
1838  *
1839  * Disable graphics turbo by resetting the max frequency and setting the
1840  * current frequency to the default.
1841  */
1842 bool i915_gpu_turbo_disable(void)
1843 {
1844         struct drm_i915_private *dev_priv;
1845         bool ret = true;
1846
1847         spin_lock(&mchdev_lock);
1848         if (!i915_mch_dev) {
1849                 ret = false;
1850                 goto out_unlock;
1851         }
1852         dev_priv = i915_mch_dev;
1853
1854         dev_priv->max_delay = dev_priv->fstart;
1855
1856         if (!ironlake_set_drps(dev_priv->dev, dev_priv->fstart))
1857                 ret = false;
1858
1859 out_unlock:
1860         spin_unlock(&mchdev_lock);
1861
1862         return ret;
1863 }
1864 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
1865
1866 /**
1867  * i915_driver_load - setup chip and create an initial config
1868  * @dev: DRM device
1869  * @flags: startup flags
1870  *
1871  * The driver load routine has to do several things:
1872  *   - drive output discovery via intel_modeset_init()
1873  *   - initialize the memory manager
1874  *   - allocate initial config memory
1875  *   - setup the DRM framebuffer with the allocated memory
1876  */
1877 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1878 {
1879         struct drm_i915_private *dev_priv;
1880         resource_size_t base, size;
1881         int ret = 0, mmio_bar;
1882         uint32_t agp_size, prealloc_size;
1883         /* i915 has 4 more counters */
1884         dev->counters += 4;
1885         dev->types[6] = _DRM_STAT_IRQ;
1886         dev->types[7] = _DRM_STAT_PRIMARY;
1887         dev->types[8] = _DRM_STAT_SECONDARY;
1888         dev->types[9] = _DRM_STAT_DMA;
1889
1890         dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
1891         if (dev_priv == NULL)
1892                 return -ENOMEM;
1893
1894         dev->dev_private = (void *)dev_priv;
1895         dev_priv->dev = dev;
1896         dev_priv->info = (struct intel_device_info *) flags;
1897
1898         /* Add register map (needed for suspend/resume) */
1899         mmio_bar = IS_GEN2(dev) ? 1 : 0;
1900         base = pci_resource_start(dev->pdev, mmio_bar);
1901         size = pci_resource_len(dev->pdev, mmio_bar);
1902
1903         if (i915_get_bridge_dev(dev)) {
1904                 ret = -EIO;
1905                 goto free_priv;
1906         }
1907
1908         /* overlay on gen2 is broken and can't address above 1G */
1909         if (IS_GEN2(dev))
1910                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1911
1912         dev_priv->regs = ioremap(base, size);
1913         if (!dev_priv->regs) {
1914                 DRM_ERROR("failed to map registers\n");
1915                 ret = -EIO;
1916                 goto put_bridge;
1917         }
1918
1919         dev_priv->mm.gtt_mapping =
1920                 io_mapping_create_wc(dev->agp->base,
1921                                      dev->agp->agp_info.aper_size * 1024*1024);
1922         if (dev_priv->mm.gtt_mapping == NULL) {
1923                 ret = -EIO;
1924                 goto out_rmmap;
1925         }
1926
1927         /* Set up a WC MTRR for non-PAT systems.  This is more common than
1928          * one would think, because the kernel disables PAT on first
1929          * generation Core chips because WC PAT gets overridden by a UC
1930          * MTRR if present.  Even if a UC MTRR isn't present.
1931          */
1932         dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base,
1933                                          dev->agp->agp_info.aper_size *
1934                                          1024 * 1024,
1935                                          MTRR_TYPE_WRCOMB, 1);
1936         if (dev_priv->mm.gtt_mtrr < 0) {
1937                 DRM_INFO("MTRR allocation failed.  Graphics "
1938                          "performance may suffer.\n");
1939         }
1940
1941         dev_priv->mm.gtt = intel_gtt_get();
1942         if (!dev_priv->mm.gtt) {
1943                 DRM_ERROR("Failed to initialize GTT\n");
1944                 ret = -ENODEV;
1945                 goto out_iomapfree;
1946         }
1947
1948         prealloc_size = dev_priv->mm.gtt->gtt_stolen_entries << PAGE_SHIFT;
1949         agp_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
1950
1951         /* The i915 workqueue is primarily used for batched retirement of
1952          * requests (and thus managing bo) once the task has been completed
1953          * by the GPU. i915_gem_retire_requests() is called directly when we
1954          * need high-priority retirement, such as waiting for an explicit
1955          * bo.
1956          *
1957          * It is also used for periodic low-priority events, such as
1958          * idle-timers and hangcheck.
1959          *
1960          * All tasks on the workqueue are expected to acquire the dev mutex
1961          * so there is no point in running more than one instance of the
1962          * workqueue at any time: max_active = 1 and NON_REENTRANT.
1963          */
1964         dev_priv->wq = alloc_workqueue("i915",
1965                                        WQ_UNBOUND | WQ_NON_REENTRANT,
1966                                        1);
1967         if (dev_priv->wq == NULL) {
1968                 DRM_ERROR("Failed to create our workqueue.\n");
1969                 ret = -ENOMEM;
1970                 goto out_iomapfree;
1971         }
1972
1973         /* enable GEM by default */
1974         dev_priv->has_gem = 1;
1975
1976         if (prealloc_size > agp_size * 3 / 4) {
1977                 DRM_ERROR("Detected broken video BIOS with %d/%dkB of video "
1978                           "memory stolen.\n",
1979                           prealloc_size / 1024, agp_size / 1024);
1980                 DRM_ERROR("Disabling GEM. (try reducing stolen memory or "
1981                           "updating the BIOS to fix).\n");
1982                 dev_priv->has_gem = 0;
1983         }
1984
1985         if (dev_priv->has_gem == 0 &&
1986             drm_core_check_feature(dev, DRIVER_MODESET)) {
1987                 DRM_ERROR("kernel modesetting requires GEM, disabling driver.\n");
1988                 ret = -ENODEV;
1989                 goto out_iomapfree;
1990         }
1991
1992         dev->driver->get_vblank_counter = i915_get_vblank_counter;
1993         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
1994         if (IS_G4X(dev) || IS_IRONLAKE(dev) || IS_GEN6(dev)) {
1995                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
1996                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
1997         }
1998
1999         /* Try to make sure MCHBAR is enabled before poking at it */
2000         intel_setup_mchbar(dev);
2001         intel_setup_gmbus(dev);
2002         intel_opregion_setup(dev);
2003
2004         /* Make sure the bios did its job and set up vital registers */
2005         intel_setup_bios(dev);
2006
2007         i915_gem_load(dev);
2008
2009         /* Init HWS */
2010         if (!I915_NEED_GFX_HWS(dev)) {
2011                 ret = i915_init_phys_hws(dev);
2012                 if (ret != 0)
2013                         goto out_workqueue_free;
2014         }
2015
2016         if (IS_PINEVIEW(dev))
2017                 i915_pineview_get_mem_freq(dev);
2018         else if (IS_IRONLAKE(dev))
2019                 i915_ironlake_get_mem_freq(dev);
2020
2021         /* On the 945G/GM, the chipset reports the MSI capability on the
2022          * integrated graphics even though the support isn't actually there
2023          * according to the published specs.  It doesn't appear to function
2024          * correctly in testing on 945G.
2025          * This may be a side effect of MSI having been made available for PEG
2026          * and the registers being closely associated.
2027          *
2028          * According to chipset errata, on the 965GM, MSI interrupts may
2029          * be lost or delayed, but we use them anyways to avoid
2030          * stuck interrupts on some machines.
2031          */
2032         if (!IS_I945G(dev) && !IS_I945GM(dev))
2033                 pci_enable_msi(dev->pdev);
2034
2035         spin_lock_init(&dev_priv->user_irq_lock);
2036         spin_lock_init(&dev_priv->error_lock);
2037         dev_priv->trace_irq_seqno = 0;
2038
2039         ret = drm_vblank_init(dev, I915_NUM_PIPE);
2040
2041         if (ret) {
2042                 (void) i915_driver_unload(dev);
2043                 return ret;
2044         }
2045
2046         /* Start out suspended */
2047         dev_priv->mm.suspended = 1;
2048
2049         intel_detect_pch(dev);
2050
2051         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2052                 ret = i915_load_modeset_init(dev, prealloc_size, agp_size);
2053                 if (ret < 0) {
2054                         DRM_ERROR("failed to init modeset\n");
2055                         goto out_workqueue_free;
2056                 }
2057         }
2058
2059         /* Must be done after probing outputs */
2060         intel_opregion_init(dev);
2061         acpi_video_register();
2062
2063         setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
2064                     (unsigned long) dev);
2065
2066         spin_lock(&mchdev_lock);
2067         i915_mch_dev = dev_priv;
2068         dev_priv->mchdev_lock = &mchdev_lock;
2069         spin_unlock(&mchdev_lock);
2070
2071         return 0;
2072
2073 out_workqueue_free:
2074         destroy_workqueue(dev_priv->wq);
2075 out_iomapfree:
2076         io_mapping_free(dev_priv->mm.gtt_mapping);
2077 out_rmmap:
2078         iounmap(dev_priv->regs);
2079 put_bridge:
2080         pci_dev_put(dev_priv->bridge_dev);
2081 free_priv:
2082         kfree(dev_priv);
2083         return ret;
2084 }
2085
2086 int i915_driver_unload(struct drm_device *dev)
2087 {
2088         struct drm_i915_private *dev_priv = dev->dev_private;
2089         int ret;
2090
2091         spin_lock(&mchdev_lock);
2092         i915_mch_dev = NULL;
2093         spin_unlock(&mchdev_lock);
2094
2095         mutex_lock(&dev->struct_mutex);
2096         ret = i915_gpu_idle(dev);
2097         if (ret)
2098                 DRM_ERROR("failed to idle hardware: %d\n", ret);
2099         mutex_unlock(&dev->struct_mutex);
2100
2101         /* Cancel the retire work handler, which should be idle now. */
2102         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
2103
2104         io_mapping_free(dev_priv->mm.gtt_mapping);
2105         if (dev_priv->mm.gtt_mtrr >= 0) {
2106                 mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
2107                          dev->agp->agp_info.aper_size * 1024 * 1024);
2108                 dev_priv->mm.gtt_mtrr = -1;
2109         }
2110
2111         acpi_video_unregister();
2112
2113         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2114                 intel_fbdev_fini(dev);
2115                 intel_modeset_cleanup(dev);
2116
2117                 /*
2118                  * free the memory space allocated for the child device
2119                  * config parsed from VBT
2120                  */
2121                 if (dev_priv->child_dev && dev_priv->child_dev_num) {
2122                         kfree(dev_priv->child_dev);
2123                         dev_priv->child_dev = NULL;
2124                         dev_priv->child_dev_num = 0;
2125                 }
2126
2127                 vga_switcheroo_unregister_client(dev->pdev);
2128                 vga_client_register(dev->pdev, NULL, NULL, NULL);
2129         }
2130
2131         /* Free error state after interrupts are fully disabled. */
2132         del_timer_sync(&dev_priv->hangcheck_timer);
2133         cancel_work_sync(&dev_priv->error_work);
2134         i915_destroy_error_state(dev);
2135
2136         if (dev->pdev->msi_enabled)
2137                 pci_disable_msi(dev->pdev);
2138
2139         intel_opregion_fini(dev);
2140
2141         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
2142                 /* Flush any outstanding unpin_work. */
2143                 flush_workqueue(dev_priv->wq);
2144
2145                 i915_gem_free_all_phys_object(dev);
2146
2147                 mutex_lock(&dev->struct_mutex);
2148                 i915_gem_cleanup_ringbuffer(dev);
2149                 mutex_unlock(&dev->struct_mutex);
2150                 if (I915_HAS_FBC(dev) && i915_powersave)
2151                         i915_cleanup_compression(dev);
2152                 drm_mm_takedown(&dev_priv->mm.vram);
2153
2154                 intel_cleanup_overlay(dev);
2155
2156                 if (!I915_NEED_GFX_HWS(dev))
2157                         i915_free_hws(dev);
2158         }
2159
2160         if (dev_priv->regs != NULL)
2161                 iounmap(dev_priv->regs);
2162
2163         intel_teardown_gmbus(dev);
2164         intel_teardown_mchbar(dev);
2165
2166         destroy_workqueue(dev_priv->wq);
2167
2168         pci_dev_put(dev_priv->bridge_dev);
2169         kfree(dev->dev_private);
2170
2171         return 0;
2172 }
2173
2174 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
2175 {
2176         struct drm_i915_file_private *file_priv;
2177
2178         DRM_DEBUG_DRIVER("\n");
2179         file_priv = kmalloc(sizeof(*file_priv), GFP_KERNEL);
2180         if (!file_priv)
2181                 return -ENOMEM;
2182
2183         file->driver_priv = file_priv;
2184
2185         spin_lock_init(&file_priv->mm.lock);
2186         INIT_LIST_HEAD(&file_priv->mm.request_list);
2187
2188         return 0;
2189 }
2190
2191 /**
2192  * i915_driver_lastclose - clean up after all DRM clients have exited
2193  * @dev: DRM device
2194  *
2195  * Take care of cleaning up after all DRM clients have exited.  In the
2196  * mode setting case, we want to restore the kernel's initial mode (just
2197  * in case the last client left us in a bad state).
2198  *
2199  * Additionally, in the non-mode setting case, we'll tear down the AGP
2200  * and DMA structures, since the kernel won't be using them, and clea
2201  * up any GEM state.
2202  */
2203 void i915_driver_lastclose(struct drm_device * dev)
2204 {
2205         drm_i915_private_t *dev_priv = dev->dev_private;
2206
2207         if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
2208                 drm_fb_helper_restore();
2209                 vga_switcheroo_process_delayed_switch();
2210                 return;
2211         }
2212
2213         i915_gem_lastclose(dev);
2214
2215         if (dev_priv->agp_heap)
2216                 i915_mem_takedown(&(dev_priv->agp_heap));
2217
2218         i915_dma_cleanup(dev);
2219 }
2220
2221 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
2222 {
2223         drm_i915_private_t *dev_priv = dev->dev_private;
2224         i915_gem_release(dev, file_priv);
2225         if (!drm_core_check_feature(dev, DRIVER_MODESET))
2226                 i915_mem_release(dev, file_priv, dev_priv->agp_heap);
2227 }
2228
2229 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
2230 {
2231         struct drm_i915_file_private *file_priv = file->driver_priv;
2232
2233         kfree(file_priv);
2234 }
2235
2236 struct drm_ioctl_desc i915_ioctls[] = {
2237         DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2238         DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
2239         DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
2240         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
2241         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
2242         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
2243         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH),
2244         DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2245         DRM_IOCTL_DEF_DRV(I915_ALLOC, i915_mem_alloc, DRM_AUTH),
2246         DRM_IOCTL_DEF_DRV(I915_FREE, i915_mem_free, DRM_AUTH),
2247         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2248         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
2249         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2250         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2251         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH),
2252         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
2253         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2254         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2255         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
2256         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
2257         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2258         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2259         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
2260         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
2261         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2262         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2263         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
2264         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
2265         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
2266         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
2267         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
2268         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
2269         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
2270         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
2271         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
2272         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
2273         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
2274         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
2275         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2276         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2277 };
2278
2279 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
2280
2281 /**
2282  * Determine if the device really is AGP or not.
2283  *
2284  * All Intel graphics chipsets are treated as AGP, even if they are really
2285  * PCI-e.
2286  *
2287  * \param dev   The device to be tested.
2288  *
2289  * \returns
2290  * A value of 1 is always retured to indictate every i9x5 is AGP.
2291  */
2292 int i915_driver_device_is_agp(struct drm_device * dev)
2293 {
2294         return 1;
2295 }