drivers/gpu/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <drm/drmP.h>
  32 #include <drm/drm_crtc_helper.h>
  33 #include <drm/drm_fb_helper.h>
  34 #include <drm/drm_legacy.h>
  35 #include "intel_drv.h"
  36 #include <drm/i915_drm.h>
  37 #include "i915_drv.h"
  38 #include "i915_trace.h"
  39 #include <linux/pci.h>
  40 #include <linux/console.h>
  41 #include <linux/vt.h>
  42 #include <linux/vgaarb.h>
  43 #include <linux/acpi.h>
  44 #include <linux/pnp.h>
  45 #include <linux/vga_switcheroo.h>
  46 #include <linux/slab.h>
  47 #include <acpi/video.h>
  48 #include <linux/pm.h>
  49 #include <linux/pm_runtime.h>
  50 #include <linux/oom.h>
  51
  52 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
  53
  54 #define BEGIN_LP_RING(n) \
  55         intel_ring_begin(LP_RING(dev_priv), (n))
  56
  57 #define OUT_RING(x) \
  58         intel_ring_emit(LP_RING(dev_priv), x)
  59
  60 #define ADVANCE_LP_RING() \
  61         __intel_ring_advance(LP_RING(dev_priv))
  62
  63 /**
  64  * Lock test for when it's just for synchronization of ring access.
  65  *
  66  * In that case, we don't need to do it when GEM is initialized as nobody else
  67  * has access to the ring.
  68  */
  69 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do {                      \
  70         if (LP_RING(dev->dev_private)->buffer->obj == NULL)                     \
  71                 LOCK_TEST_WITH_RETURN(dev, file);                       \
  72 } while (0)
  73
  74 static inline u32
  75 intel_read_legacy_status_page(struct drm_i915_private *dev_priv, int reg)
  76 {
  77         if (I915_NEED_GFX_HWS(dev_priv->dev))
  78                 return ioread32(dev_priv->dri1.gfx_hws_cpu_addr + reg);
  79         else
  80                 return intel_read_status_page(LP_RING(dev_priv), reg);
  81 }
  82
  83 #define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg)
  84 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
  85 #define I915_BREADCRUMB_INDEX           0x21
  86
  87 void i915_update_dri1_breadcrumb(struct drm_device *dev)
  88 {
  89         struct drm_i915_private *dev_priv = dev->dev_private;
  90         struct drm_i915_master_private *master_priv;
  91
  92         /*
  93          * The dri breadcrumb update races against the drm master disappearing.
  94          * Instead of trying to fix this (this is by far not the only ums issue)
  95          * just don't do the update in kms mode.
  96          */
  97         if (drm_core_check_feature(dev, DRIVER_MODESET))
  98                 return;
  99
 100         if (dev->primary->master) {
 101                 master_priv = dev->primary->master->driver_priv;
 102                 if (master_priv->sarea_priv)
 103                         master_priv->sarea_priv->last_dispatch =
 104                                 READ_BREADCRUMB(dev_priv);
 105         }
 106 }
 107
 108 static void i915_write_hws_pga(struct drm_device *dev)
 109 {
 110         struct drm_i915_private *dev_priv = dev->dev_private;
 111         u32 addr;
 112
 113         addr = dev_priv->status_page_dmah->busaddr;
 114         if (INTEL_INFO(dev)->gen >= 4)
 115                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
 116         I915_WRITE(HWS_PGA, addr);
 117 }
 118
 119 /**
 120  * Frees the hardware status page, whether it's a physical address or a virtual
 121  * address set up by the X Server.
 122  */
 123 static void i915_free_hws(struct drm_device *dev)
 124 {
 125         struct drm_i915_private *dev_priv = dev->dev_private;
 126         struct intel_engine_cs *ring = LP_RING(dev_priv);
 127
 128         if (dev_priv->status_page_dmah) {
 129                 drm_pci_free(dev, dev_priv->status_page_dmah);
 130                 dev_priv->status_page_dmah = NULL;
 131         }
 132
 133         if (ring->status_page.gfx_addr) {
 134                 ring->status_page.gfx_addr = 0;
 135                 iounmap(dev_priv->dri1.gfx_hws_cpu_addr);
 136         }
 137
 138         /* Need to rewrite hardware status page */
 139         I915_WRITE(HWS_PGA, 0x1ffff000);
 140 }
 141
 142 void i915_kernel_lost_context(struct drm_device *dev)
 143 {
 144         struct drm_i915_private *dev_priv = dev->dev_private;
 145         struct drm_i915_master_private *master_priv;
 146         struct intel_engine_cs *ring = LP_RING(dev_priv);
 147         struct intel_ringbuffer *ringbuf = ring->buffer;
 148
 149         /*
 150          * We should never lose context on the ring with modesetting
 151          * as we don't expose it to userspace
 152          */
 153         if (drm_core_check_feature(dev, DRIVER_MODESET))
 154                 return;
 155
 156         ringbuf->head = I915_READ_HEAD(ring) & HEAD_ADDR;
 157         ringbuf->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 158         ringbuf->space = ringbuf->head - (ringbuf->tail + I915_RING_FREE_SPACE);
 159         if (ringbuf->space < 0)
 160                 ringbuf->space += ringbuf->size;
 161
 162         if (!dev->primary->master)
 163                 return;
 164
 165         master_priv = dev->primary->master->driver_priv;
 166         if (ringbuf->head == ringbuf->tail && master_priv->sarea_priv)
 167                 master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
 168 }
 169
 170 static int i915_dma_cleanup(struct drm_device *dev)
 171 {
 172         struct drm_i915_private *dev_priv = dev->dev_private;
 173         int i;
 174
 175         /* Make sure interrupts are disabled here because the uninstall ioctl
 176          * may not have been called from userspace and after dev_private
 177          * is freed, it's too late.
 178          */
 179         if (dev->irq_enabled)
 180                 drm_irq_uninstall(dev);
 181
 182         mutex_lock(&dev->struct_mutex);
 183         for (i = 0; i < I915_NUM_RINGS; i++)
 184                 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
 185         mutex_unlock(&dev->struct_mutex);
 186
 187         /* Clear the HWS virtual address at teardown */
 188         if (I915_NEED_GFX_HWS(dev))
 189                 i915_free_hws(dev);
 190
 191         return 0;
 192 }
 193
 194 static int i915_initialize(struct drm_device *dev, drm_i915_init_t *init)
 195 {
 196         struct drm_i915_private *dev_priv = dev->dev_private;
 197         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 198         int ret;
 199
 200         master_priv->sarea = drm_legacy_getsarea(dev);
 201         if (master_priv->sarea) {
 202                 master_priv->sarea_priv = (drm_i915_sarea_t *)
 203                         ((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
 204         } else {
 205                 DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
 206         }
 207
 208         if (init->ring_size != 0) {
 209                 if (LP_RING(dev_priv)->buffer->obj != NULL) {
 210                         i915_dma_cleanup(dev);
 211                         DRM_ERROR("Client tried to initialize ringbuffer in "
 212                                   "GEM mode\n");
 213                         return -EINVAL;
 214                 }
 215
 216                 ret = intel_render_ring_init_dri(dev,
 217                                                  init->ring_start,
 218                                                  init->ring_size);
 219                 if (ret) {
 220                         i915_dma_cleanup(dev);
 221                         return ret;
 222                 }
 223         }
 224
 225         dev_priv->dri1.cpp = init->cpp;
 226         dev_priv->dri1.back_offset = init->back_offset;
 227         dev_priv->dri1.front_offset = init->front_offset;
 228         dev_priv->dri1.current_page = 0;
 229         if (master_priv->sarea_priv)
 230                 master_priv->sarea_priv->pf_current_page = 0;
 231
 232         /* Allow hardware batchbuffers unless told otherwise.
 233          */
 234         dev_priv->dri1.allow_batchbuffer = 1;
 235
 236         return 0;
 237 }
 238
 239 static int i915_dma_resume(struct drm_device *dev)
 240 {
 241         struct drm_i915_private *dev_priv = dev->dev_private;
 242         struct intel_engine_cs *ring = LP_RING(dev_priv);
 243
 244         DRM_DEBUG_DRIVER("%s\n", __func__);
 245
 246         if (ring->buffer->virtual_start == NULL) {
 247                 DRM_ERROR("can not ioremap virtual address for"
 248                           " ring buffer\n");
 249                 return -ENOMEM;
 250         }
 251
 252         /* Program Hardware Status Page */
 253         if (!ring->status_page.page_addr) {
 254                 DRM_ERROR("Can not find hardware status page\n");
 255                 return -EINVAL;
 256         }
 257         DRM_DEBUG_DRIVER("hw status page @ %p\n",
 258                                 ring->status_page.page_addr);
 259         if (ring->status_page.gfx_addr != 0)
 260                 intel_ring_setup_status_page(ring);
 261         else
 262                 i915_write_hws_pga(dev);
 263
 264         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
 265
 266         return 0;
 267 }
 268
 269 static int i915_dma_init(struct drm_device *dev, void *data,
 270                          struct drm_file *file_priv)
 271 {
 272         drm_i915_init_t *init = data;
 273         int retcode = 0;
 274
 275         if (drm_core_check_feature(dev, DRIVER_MODESET))
 276                 return -ENODEV;
 277
 278         switch (init->func) {
 279         case I915_INIT_DMA:
 280                 retcode = i915_initialize(dev, init);
 281                 break;
 282         case I915_CLEANUP_DMA:
 283                 retcode = i915_dma_cleanup(dev);
 284                 break;
 285         case I915_RESUME_DMA:
 286                 retcode = i915_dma_resume(dev);
 287                 break;
 288         default:
 289                 retcode = -EINVAL;
 290                 break;
 291         }
 292
 293         return retcode;
 294 }
 295
 296 /* Implement basically the same security restrictions as hardware does
 297  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 298  *
 299  * Most of the calculations below involve calculating the size of a
 300  * particular instruction.  It's important to get the size right as
 301  * that tells us where the next instruction to check is.  Any illegal
 302  * instruction detected will be given a size of zero, which is a
 303  * signal to abort the rest of the buffer.
 304  */
 305 static int validate_cmd(int cmd)
 306 {
 307         switch (((cmd >> 29) & 0x7)) {
 308         case 0x0:
 309                 switch ((cmd >> 23) & 0x3f) {
 310                 case 0x0:
 311                         return 1;       /* MI_NOOP */
 312                 case 0x4:
 313                         return 1;       /* MI_FLUSH */
 314                 default:
 315                         return 0;       /* disallow everything else */
 316                 }
 317                 break;
 318         case 0x1:
 319                 return 0;       /* reserved */
 320         case 0x2:
 321                 return (cmd & 0xff) + 2;        /* 2d commands */
 322         case 0x3:
 323                 if (((cmd >> 24) & 0x1f) <= 0x18)
 324                         return 1;
 325
 326                 switch ((cmd >> 24) & 0x1f) {
 327                 case 0x1c:
 328                         return 1;
 329                 case 0x1d:
 330                         switch ((cmd >> 16) & 0xff) {
 331                         case 0x3:
 332                                 return (cmd & 0x1f) + 2;
 333                         case 0x4:
 334                                 return (cmd & 0xf) + 2;
 335                         default:
 336                                 return (cmd & 0xffff) + 2;
 337                         }
 338                 case 0x1e:
 339                         if (cmd & (1 << 23))
 340                                 return (cmd & 0xffff) + 1;
 341                         else
 342                                 return 1;
 343                 case 0x1f:
 344                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 345                                 return (cmd & 0x1ffff) + 2;
 346                         else if (cmd & (1 << 17))       /* indirect random */
 347                                 if ((cmd & 0xffff) == 0)
 348                                         return 0;       /* unknown length, too hard */
 349                                 else
 350                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 351                         else
 352                                 return 2;       /* indirect sequential */
 353                 default:
 354                         return 0;
 355                 }
 356         default:
 357                 return 0;
 358         }
 359
 360         return 0;
 361 }
 362
 363 static int i915_emit_cmds(struct drm_device *dev, int *buffer, int dwords)
 364 {
 365         struct drm_i915_private *dev_priv = dev->dev_private;
 366         int i, ret;
 367
 368         if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->buffer->size - 8)
 369                 return -EINVAL;
 370
 371         for (i = 0; i < dwords;) {
 372                 int sz = validate_cmd(buffer[i]);
 373
 374                 if (sz == 0 || i + sz > dwords)
 375                         return -EINVAL;
 376                 i += sz;
 377         }
 378
 379         ret = BEGIN_LP_RING((dwords+1)&~1);
 380         if (ret)
 381                 return ret;
 382
 383         for (i = 0; i < dwords; i++)
 384                 OUT_RING(buffer[i]);
 385         if (dwords & 1)
 386                 OUT_RING(0);
 387
 388         ADVANCE_LP_RING();
 389
 390         return 0;
 391 }
 392
 393 int
 394 i915_emit_box(struct drm_device *dev,
 395               struct drm_clip_rect *box,
 396               int DR1, int DR4)
 397 {
 398         struct drm_i915_private *dev_priv = dev->dev_private;
 399         int ret;
 400
 401         if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
 402             box->y2 <= 0 || box->x2 <= 0) {
 403                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 404                           box->x1, box->y1, box->x2, box->y2);
 405                 return -EINVAL;
 406         }
 407
 408         if (INTEL_INFO(dev)->gen >= 4) {
 409                 ret = BEGIN_LP_RING(4);
 410                 if (ret)
 411                         return ret;
 412
 413                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 414                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 415                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 416                 OUT_RING(DR4);
 417         } else {
 418                 ret = BEGIN_LP_RING(6);
 419                 if (ret)
 420                         return ret;
 421
 422                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 423                 OUT_RING(DR1);
 424                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 425                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 426                 OUT_RING(DR4);
 427                 OUT_RING(0);
 428         }
 429         ADVANCE_LP_RING();
 430
 431         return 0;
 432 }
 433
 434 /* XXX: Emitting the counter should really be moved to part of the IRQ
 435  * emit. For now, do it in both places:
 436  */
 437
 438 static void i915_emit_breadcrumb(struct drm_device *dev)
 439 {
 440         struct drm_i915_private *dev_priv = dev->dev_private;
 441         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 442
 443         dev_priv->dri1.counter++;
 444         if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
 445                 dev_priv->dri1.counter = 0;
 446         if (master_priv->sarea_priv)
 447                 master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
 448
 449         if (BEGIN_LP_RING(4) == 0) {
 450                 OUT_RING(MI_STORE_DWORD_INDEX);
 451                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 452                 OUT_RING(dev_priv->dri1.counter);
 453                 OUT_RING(0);
 454                 ADVANCE_LP_RING();
 455         }
 456 }
 457
 458 static int i915_dispatch_cmdbuffer(struct drm_device *dev,
 459                                    drm_i915_cmdbuffer_t *cmd,
 460                                    struct drm_clip_rect *cliprects,
 461                                    void *cmdbuf)
 462 {
 463         int nbox = cmd->num_cliprects;
 464         int i = 0, count, ret;
 465
 466         if (cmd->sz & 0x3) {
 467                 DRM_ERROR("alignment");
 468                 return -EINVAL;
 469         }
 470
 471         i915_kernel_lost_context(dev);
 472
 473         count = nbox ? nbox : 1;
 474
 475         for (i = 0; i < count; i++) {
 476                 if (i < nbox) {
 477                         ret = i915_emit_box(dev, &cliprects[i],
 478                                             cmd->DR1, cmd->DR4);
 479                         if (ret)
 480                                 return ret;
 481                 }
 482
 483                 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
 484                 if (ret)
 485                         return ret;
 486         }
 487
 488         i915_emit_breadcrumb(dev);
 489         return 0;
 490 }
 491
 492 static int i915_dispatch_batchbuffer(struct drm_device *dev,
 493                                      drm_i915_batchbuffer_t *batch,
 494                                      struct drm_clip_rect *cliprects)
 495 {
 496         struct drm_i915_private *dev_priv = dev->dev_private;
 497         int nbox = batch->num_cliprects;
 498         int i, count, ret;
 499
 500         if ((batch->start | batch->used) & 0x7) {
 501                 DRM_ERROR("alignment");
 502                 return -EINVAL;
 503         }
 504
 505         i915_kernel_lost_context(dev);
 506
 507         count = nbox ? nbox : 1;
 508         for (i = 0; i < count; i++) {
 509                 if (i < nbox) {
 510                         ret = i915_emit_box(dev, &cliprects[i],
 511                                             batch->DR1, batch->DR4);
 512                         if (ret)
 513                                 return ret;
 514                 }
 515
 516                 if (!IS_I830(dev) && !IS_845G(dev)) {
 517                         ret = BEGIN_LP_RING(2);
 518                         if (ret)
 519                                 return ret;
 520
 521                         if (INTEL_INFO(dev)->gen >= 4) {
 522                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
 523                                 OUT_RING(batch->start);
 524                         } else {
 525                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 526                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 527                         }
 528                 } else {
 529                         ret = BEGIN_LP_RING(4);
 530                         if (ret)
 531                                 return ret;
 532
 533                         OUT_RING(MI_BATCH_BUFFER);
 534                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 535                         OUT_RING(batch->start + batch->used - 4);
 536                         OUT_RING(0);
 537                 }
 538                 ADVANCE_LP_RING();
 539         }
 540
 541
 542         if (IS_G4X(dev) || IS_GEN5(dev)) {
 543                 if (BEGIN_LP_RING(2) == 0) {
 544                         OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
 545                         OUT_RING(MI_NOOP);
 546                         ADVANCE_LP_RING();
 547                 }
 548         }
 549
 550         i915_emit_breadcrumb(dev);
 551         return 0;
 552 }
 553
 554 static int i915_dispatch_flip(struct drm_device *dev)
 555 {
 556         struct drm_i915_private *dev_priv = dev->dev_private;
 557         struct drm_i915_master_private *master_priv =
 558                 dev->primary->master->driver_priv;
 559         int ret;
 560
 561         if (!master_priv->sarea_priv)
 562                 return -EINVAL;
 563
 564         DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
 565                           __func__,
 566                          dev_priv->dri1.current_page,
 567                          master_priv->sarea_priv->pf_current_page);
 568
 569         i915_kernel_lost_context(dev);
 570
 571         ret = BEGIN_LP_RING(10);
 572         if (ret)
 573                 return ret;
 574
 575         OUT_RING(MI_FLUSH | MI_READ_FLUSH);
 576         OUT_RING(0);
 577
 578         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
 579         OUT_RING(0);
 580         if (dev_priv->dri1.current_page == 0) {
 581                 OUT_RING(dev_priv->dri1.back_offset);
 582                 dev_priv->dri1.current_page = 1;
 583         } else {
 584                 OUT_RING(dev_priv->dri1.front_offset);
 585                 dev_priv->dri1.current_page = 0;
 586         }
 587         OUT_RING(0);
 588
 589         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
 590         OUT_RING(0);
 591
 592         ADVANCE_LP_RING();
 593
 594         master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter++;
 595
 596         if (BEGIN_LP_RING(4) == 0) {
 597                 OUT_RING(MI_STORE_DWORD_INDEX);
 598                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 599                 OUT_RING(dev_priv->dri1.counter);
 600                 OUT_RING(0);
 601                 ADVANCE_LP_RING();
 602         }
 603
 604         master_priv->sarea_priv->pf_current_page = dev_priv->dri1.current_page;
 605         return 0;
 606 }
 607
 608 static int i915_quiescent(struct drm_device *dev)
 609 {
 610         i915_kernel_lost_context(dev);
 611         return intel_ring_idle(LP_RING(dev->dev_private));
 612 }
 613
 614 static int i915_flush_ioctl(struct drm_device *dev, void *data,
 615                             struct drm_file *file_priv)
 616 {
 617         int ret;
 618
 619         if (drm_core_check_feature(dev, DRIVER_MODESET))
 620                 return -ENODEV;
 621
 622         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 623
 624         mutex_lock(&dev->struct_mutex);
 625         ret = i915_quiescent(dev);
 626         mutex_unlock(&dev->struct_mutex);
 627
 628         return ret;
 629 }
 630
 631 static int i915_batchbuffer(struct drm_device *dev, void *data,
 632                             struct drm_file *file_priv)
 633 {
 634         struct drm_i915_private *dev_priv = dev->dev_private;
 635         struct drm_i915_master_private *master_priv;
 636         drm_i915_sarea_t *sarea_priv;
 637         drm_i915_batchbuffer_t *batch = data;
 638         int ret;
 639         struct drm_clip_rect *cliprects = NULL;
 640
 641         if (drm_core_check_feature(dev, DRIVER_MODESET))
 642                 return -ENODEV;
 643
 644         master_priv = dev->primary->master->driver_priv;
 645         sarea_priv = (drm_i915_sarea_t *) master_priv->sarea_priv;
 646
 647         if (!dev_priv->dri1.allow_batchbuffer) {
 648                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 649                 return -EINVAL;
 650         }
 651
 652         DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
 653                         batch->start, batch->used, batch->num_cliprects);
 654
 655         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 656
 657         if (batch->num_cliprects < 0)
 658                 return -EINVAL;
 659
 660         if (batch->num_cliprects) {
 661                 cliprects = kcalloc(batch->num_cliprects,
 662                                     sizeof(*cliprects),
 663                                     GFP_KERNEL);
 664                 if (cliprects == NULL)
 665                         return -ENOMEM;
 666
 667                 ret = copy_from_user(cliprects, batch->cliprects,
 668                                      batch->num_cliprects *
 669                                      sizeof(struct drm_clip_rect));
 670                 if (ret != 0) {
 671                         ret = -EFAULT;
 672                         goto fail_free;
 673                 }
 674         }
 675
 676         mutex_lock(&dev->struct_mutex);
 677         ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
 678         mutex_unlock(&dev->struct_mutex);
 679
 680         if (sarea_priv)
 681                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 682
 683 fail_free:
 684         kfree(cliprects);
 685
 686         return ret;
 687 }
 688
 689 static int i915_cmdbuffer(struct drm_device *dev, void *data,
 690                           struct drm_file *file_priv)
 691 {
 692         struct drm_i915_private *dev_priv = dev->dev_private;
 693         struct drm_i915_master_private *master_priv;
 694         drm_i915_sarea_t *sarea_priv;
 695         drm_i915_cmdbuffer_t *cmdbuf = data;
 696         struct drm_clip_rect *cliprects = NULL;
 697         void *batch_data;
 698         int ret;
 699
 700         DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 701                         cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 702
 703         if (drm_core_check_feature(dev, DRIVER_MODESET))
 704                 return -ENODEV;
 705
 706         master_priv = dev->primary->master->driver_priv;
 707         sarea_priv = (drm_i915_sarea_t *) master_priv->sarea_priv;
 708
 709         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 710
 711         if (cmdbuf->num_cliprects < 0)
 712                 return -EINVAL;
 713
 714         batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
 715         if (batch_data == NULL)
 716                 return -ENOMEM;
 717
 718         ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
 719         if (ret != 0) {
 720                 ret = -EFAULT;
 721                 goto fail_batch_free;
 722         }
 723
 724         if (cmdbuf->num_cliprects) {
 725                 cliprects = kcalloc(cmdbuf->num_cliprects,
 726                                     sizeof(*cliprects), GFP_KERNEL);
 727                 if (cliprects == NULL) {
 728                         ret = -ENOMEM;
 729                         goto fail_batch_free;
 730                 }
 731
 732                 ret = copy_from_user(cliprects, cmdbuf->cliprects,
 733                                      cmdbuf->num_cliprects *
 734                                      sizeof(struct drm_clip_rect));
 735                 if (ret != 0) {
 736                         ret = -EFAULT;
 737                         goto fail_clip_free;
 738                 }
 739         }
 740
 741         mutex_lock(&dev->struct_mutex);
 742         ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
 743         mutex_unlock(&dev->struct_mutex);
 744         if (ret) {
 745                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 746                 goto fail_clip_free;
 747         }
 748
 749         if (sarea_priv)
 750                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 751
 752 fail_clip_free:
 753         kfree(cliprects);
 754 fail_batch_free:
 755         kfree(batch_data);
 756
 757         return ret;
 758 }
 759
 760 static int i915_emit_irq(struct drm_device *dev)
 761 {
 762         struct drm_i915_private *dev_priv = dev->dev_private;
 763         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 764
 765         i915_kernel_lost_context(dev);
 766
 767         DRM_DEBUG_DRIVER("\n");
 768
 769         dev_priv->dri1.counter++;
 770         if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
 771                 dev_priv->dri1.counter = 1;
 772         if (master_priv->sarea_priv)
 773                 master_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
 774
 775         if (BEGIN_LP_RING(4) == 0) {
 776                 OUT_RING(MI_STORE_DWORD_INDEX);
 777                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 778                 OUT_RING(dev_priv->dri1.counter);
 779                 OUT_RING(MI_USER_INTERRUPT);
 780                 ADVANCE_LP_RING();
 781         }
 782
 783         return dev_priv->dri1.counter;
 784 }
 785
 786 static int i915_wait_irq(struct drm_device *dev, int irq_nr)
 787 {
 788         struct drm_i915_private *dev_priv = dev->dev_private;
 789         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 790         int ret = 0;
 791         struct intel_engine_cs *ring = LP_RING(dev_priv);
 792
 793         DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
 794                   READ_BREADCRUMB(dev_priv));
 795
 796         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
 797                 if (master_priv->sarea_priv)
 798                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 799                 return 0;
 800         }
 801
 802         if (master_priv->sarea_priv)
 803                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
 804
 805         if (ring->irq_get(ring)) {
 806                 DRM_WAIT_ON(ret, ring->irq_queue, 3 * HZ,
 807                             READ_BREADCRUMB(dev_priv) >= irq_nr);
 808                 ring->irq_put(ring);
 809         } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
 810                 ret = -EBUSY;
 811
 812         if (ret == -EBUSY) {
 813                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
 814                           READ_BREADCRUMB(dev_priv), (int)dev_priv->dri1.counter);
 815         }
 816
 817         return ret;
 818 }
 819
 820 /* Needs the lock as it touches the ring.
 821  */
 822 static int i915_irq_emit(struct drm_device *dev, void *data,
 823                          struct drm_file *file_priv)
 824 {
 825         struct drm_i915_private *dev_priv = dev->dev_private;
 826         drm_i915_irq_emit_t *emit = data;
 827         int result;
 828
 829         if (drm_core_check_feature(dev, DRIVER_MODESET))
 830                 return -ENODEV;
 831
 832         if (!dev_priv || !LP_RING(dev_priv)->buffer->virtual_start) {
 833                 DRM_ERROR("called with no initialization\n");
 834                 return -EINVAL;
 835         }
 836
 837         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 838
 839         mutex_lock(&dev->struct_mutex);
 840         result = i915_emit_irq(dev);
 841         mutex_unlock(&dev->struct_mutex);
 842
 843         if (copy_to_user(emit->irq_seq, &result, sizeof(int))) {
 844                 DRM_ERROR("copy_to_user\n");
 845                 return -EFAULT;
 846         }
 847
 848         return 0;
 849 }
 850
 851 /* Doesn't need the hardware lock.
 852  */
 853 static int i915_irq_wait(struct drm_device *dev, void *data,
 854                          struct drm_file *file_priv)
 855 {
 856         struct drm_i915_private *dev_priv = dev->dev_private;
 857         drm_i915_irq_wait_t *irqwait = data;
 858
 859         if (drm_core_check_feature(dev, DRIVER_MODESET))
 860                 return -ENODEV;
 861
 862         if (!dev_priv) {
 863                 DRM_ERROR("called with no initialization\n");
 864                 return -EINVAL;
 865         }
 866
 867         return i915_wait_irq(dev, irqwait->irq_seq);
 868 }
 869
 870 static int i915_vblank_pipe_get(struct drm_device *dev, void *data,
 871                          struct drm_file *file_priv)
 872 {
 873         struct drm_i915_private *dev_priv = dev->dev_private;
 874         drm_i915_vblank_pipe_t *pipe = data;
 875
 876         if (drm_core_check_feature(dev, DRIVER_MODESET))
 877                 return -ENODEV;
 878
 879         if (!dev_priv) {
 880                 DRM_ERROR("called with no initialization\n");
 881                 return -EINVAL;
 882         }
 883
 884         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
 885
 886         return 0;
 887 }
 888
 889 /**
 890  * Schedule buffer swap at given vertical blank.
 891  */
 892 static int i915_vblank_swap(struct drm_device *dev, void *data,
 893                      struct drm_file *file_priv)
 894 {
 895         /* The delayed swap mechanism was fundamentally racy, and has been
 896          * removed.  The model was that the client requested a delayed flip/swap
 897          * from the kernel, then waited for vblank before continuing to perform
 898          * rendering.  The problem was that the kernel might wake the client
 899          * up before it dispatched the vblank swap (since the lock has to be
 900          * held while touching the ringbuffer), in which case the client would
 901          * clear and start the next frame before the swap occurred, and
 902          * flicker would occur in addition to likely missing the vblank.
 903          *
 904          * In the absence of this ioctl, userland falls back to a correct path
 905          * of waiting for a vblank, then dispatching the swap on its own.
 906          * Context switching to userland and back is plenty fast enough for
 907          * meeting the requirements of vblank swapping.
 908          */
 909         return -EINVAL;
 910 }
 911
 912 static int i915_flip_bufs(struct drm_device *dev, void *data,
 913                           struct drm_file *file_priv)
 914 {
 915         int ret;
 916
 917         if (drm_core_check_feature(dev, DRIVER_MODESET))
 918                 return -ENODEV;
 919
 920         DRM_DEBUG_DRIVER("%s\n", __func__);
 921
 922         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 923
 924         mutex_lock(&dev->struct_mutex);
 925         ret = i915_dispatch_flip(dev);
 926         mutex_unlock(&dev->struct_mutex);
 927
 928         return ret;
 929 }
 930
 931 static int i915_getparam(struct drm_device *dev, void *data,
 932                          struct drm_file *file_priv)
 933 {
 934         struct drm_i915_private *dev_priv = dev->dev_private;
 935         drm_i915_getparam_t *param = data;
 936         int value;
 937
 938         if (!dev_priv) {
 939                 DRM_ERROR("called with no initialization\n");
 940                 return -EINVAL;
 941         }
 942
 943         switch (param->param) {
 944         case I915_PARAM_IRQ_ACTIVE:
 945                 value = dev->pdev->irq ? 1 : 0;
 946                 break;
 947         case I915_PARAM_ALLOW_BATCHBUFFER:
 948                 value = dev_priv->dri1.allow_batchbuffer ? 1 : 0;
 949                 break;
 950         case I915_PARAM_LAST_DISPATCH:
 951                 value = READ_BREADCRUMB(dev_priv);
 952                 break;
 953         case I915_PARAM_CHIPSET_ID:
 954                 value = dev->pdev->device;
 955                 break;
 956         case I915_PARAM_HAS_GEM:
 957                 value = 1;
 958                 break;
 959         case I915_PARAM_NUM_FENCES_AVAIL:
 960                 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
 961                 break;
 962         case I915_PARAM_HAS_OVERLAY:
 963                 value = dev_priv->overlay ? 1 : 0;
 964                 break;
 965         case I915_PARAM_HAS_PAGEFLIPPING:
 966                 value = 1;
 967                 break;
 968         case I915_PARAM_HAS_EXECBUF2:
 969                 /* depends on GEM */
 970                 value = 1;
 971                 break;
 972         case I915_PARAM_HAS_BSD:
 973                 value = intel_ring_initialized(&dev_priv->ring[VCS]);
 974                 break;
 975         case I915_PARAM_HAS_BLT:
 976                 value = intel_ring_initialized(&dev_priv->ring[BCS]);
 977                 break;
 978         case I915_PARAM_HAS_VEBOX:
 979                 value = intel_ring_initialized(&dev_priv->ring[VECS]);
 980                 break;
 981         case I915_PARAM_HAS_RELAXED_FENCING:
 982                 value = 1;
 983                 break;
 984         case I915_PARAM_HAS_COHERENT_RINGS:
 985                 value = 1;
 986                 break;
 987         case I915_PARAM_HAS_EXEC_CONSTANTS:
 988                 value = INTEL_INFO(dev)->gen >= 4;
 989                 break;
 990         case I915_PARAM_HAS_RELAXED_DELTA:
 991                 value = 1;
 992                 break;
 993         case I915_PARAM_HAS_GEN7_SOL_RESET:
 994                 value = 1;
 995                 break;
 996         case I915_PARAM_HAS_LLC:
 997                 value = HAS_LLC(dev);
 998                 break;
 999         case I915_PARAM_HAS_WT:
1000                 value = HAS_WT(dev);
1001                 break;
1002         case I915_PARAM_HAS_ALIASING_PPGTT:
1003                 value = USES_PPGTT(dev);
1004                 break;
1005         case I915_PARAM_HAS_WAIT_TIMEOUT:
1006                 value = 1;
1007                 break;
1008         case I915_PARAM_HAS_SEMAPHORES:
1009                 value = i915_semaphore_is_enabled(dev);
1010                 break;
1011         case I915_PARAM_HAS_PRIME_VMAP_FLUSH:
1012                 value = 1;
1013                 break;
1014         case I915_PARAM_HAS_SECURE_BATCHES:
1015                 value = capable(CAP_SYS_ADMIN);
1016                 break;
1017         case I915_PARAM_HAS_PINNED_BATCHES:
1018                 value = 1;
1019                 break;
1020         case I915_PARAM_HAS_EXEC_NO_RELOC:
1021                 value = 1;
1022                 break;
1023         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
1024                 value = 1;
1025                 break;
1026         case I915_PARAM_CMD_PARSER_VERSION:
1027                 value = i915_cmd_parser_get_version();
1028                 break;
1029         default:
1030                 DRM_DEBUG("Unknown parameter %d\n", param->param);
1031                 return -EINVAL;
1032         }
1033
1034         if (copy_to_user(param->value, &value, sizeof(int))) {
1035                 DRM_ERROR("copy_to_user failed\n");
1036                 return -EFAULT;
1037         }
1038
1039         return 0;
1040 }
1041
1042 static int i915_setparam(struct drm_device *dev, void *data,
1043                          struct drm_file *file_priv)
1044 {
1045         struct drm_i915_private *dev_priv = dev->dev_private;
1046         drm_i915_setparam_t *param = data;
1047
1048         if (!dev_priv) {
1049                 DRM_ERROR("called with no initialization\n");
1050                 return -EINVAL;
1051         }
1052
1053         switch (param->param) {
1054         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
1055                 break;
1056         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
1057                 break;
1058         case I915_SETPARAM_ALLOW_BATCHBUFFER:
1059                 dev_priv->dri1.allow_batchbuffer = param->value ? 1 : 0;
1060                 break;
1061         case I915_SETPARAM_NUM_USED_FENCES:
1062                 if (param->value > dev_priv->num_fence_regs ||
1063                     param->value < 0)
1064                         return -EINVAL;
1065                 /* Userspace can use first N regs */
1066                 dev_priv->fence_reg_start = param->value;
1067                 break;
1068         default:
1069                 DRM_DEBUG_DRIVER("unknown parameter %d\n",
1070                                         param->param);
1071                 return -EINVAL;
1072         }
1073
1074         return 0;
1075 }
1076
1077 static int i915_set_status_page(struct drm_device *dev, void *data,
1078                                 struct drm_file *file_priv)
1079 {
1080         struct drm_i915_private *dev_priv = dev->dev_private;
1081         drm_i915_hws_addr_t *hws = data;
1082         struct intel_engine_cs *ring;
1083
1084         if (drm_core_check_feature(dev, DRIVER_MODESET))
1085                 return -ENODEV;
1086
1087         if (!I915_NEED_GFX_HWS(dev))
1088                 return -EINVAL;
1089
1090         if (!dev_priv) {
1091                 DRM_ERROR("called with no initialization\n");
1092                 return -EINVAL;
1093         }
1094
1095         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1096                 WARN(1, "tried to set status page when mode setting active\n");
1097                 return 0;
1098         }
1099
1100         DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
1101
1102         ring = LP_RING(dev_priv);
1103         ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
1104
1105         dev_priv->dri1.gfx_hws_cpu_addr =
1106                 ioremap_wc(dev_priv->gtt.mappable_base + hws->addr, 4096);
1107         if (dev_priv->dri1.gfx_hws_cpu_addr == NULL) {
1108                 i915_dma_cleanup(dev);
1109                 ring->status_page.gfx_addr = 0;
1110                 DRM_ERROR("can not ioremap virtual address for"
1111                                 " G33 hw status page\n");
1112                 return -ENOMEM;
1113         }
1114
1115         memset_io(dev_priv->dri1.gfx_hws_cpu_addr, 0, PAGE_SIZE);
1116         I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
1117
1118         DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
1119                          ring->status_page.gfx_addr);
1120         DRM_DEBUG_DRIVER("load hws at %p\n",
1121                          ring->status_page.page_addr);
1122         return 0;
1123 }
1124
1125 static int i915_get_bridge_dev(struct drm_device *dev)
1126 {
1127         struct drm_i915_private *dev_priv = dev->dev_private;
1128
1129         dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
1130         if (!dev_priv->bridge_dev) {
1131                 DRM_ERROR("bridge device not found\n");
1132                 return -1;
1133         }
1134         return 0;
1135 }
1136
1137 #define MCHBAR_I915 0x44
1138 #define MCHBAR_I965 0x48
1139 #define MCHBAR_SIZE (4*4096)
1140
1141 #define DEVEN_REG 0x54
1142 #define   DEVEN_MCHBAR_EN (1 << 28)
1143
1144 /* Allocate space for the MCH regs if needed, return nonzero on error */
1145 static int
1146 intel_alloc_mchbar_resource(struct drm_device *dev)
1147 {
1148         struct drm_i915_private *dev_priv = dev->dev_private;
1149         int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1150         u32 temp_lo, temp_hi = 0;
1151         u64 mchbar_addr;
1152         int ret;
1153
1154         if (INTEL_INFO(dev)->gen >= 4)
1155                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
1156         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
1157         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
1158
1159         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
1160 #ifdef CONFIG_PNP
1161         if (mchbar_addr &&
1162             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
1163                 return 0;
1164 #endif
1165
1166         /* Get some space for it */
1167         dev_priv->mch_res.name = "i915 MCHBAR";
1168         dev_priv->mch_res.flags = IORESOURCE_MEM;
1169         ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
1170                                      &dev_priv->mch_res,
1171                                      MCHBAR_SIZE, MCHBAR_SIZE,
1172                                      PCIBIOS_MIN_MEM,
1173                                      0, pcibios_align_resource,
1174                                      dev_priv->bridge_dev);
1175         if (ret) {
1176                 DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
1177                 dev_priv->mch_res.start = 0;
1178                 return ret;
1179         }
1180
1181         if (INTEL_INFO(dev)->gen >= 4)
1182                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
1183                                        upper_32_bits(dev_priv->mch_res.start));
1184
1185         pci_write_config_dword(dev_priv->bridge_dev, reg,
1186                                lower_32_bits(dev_priv->mch_res.start));
1187         return 0;
1188 }
1189
1190 /* Setup MCHBAR if possible, return true if we should disable it again */
1191 static void
1192 intel_setup_mchbar(struct drm_device *dev)
1193 {
1194         struct drm_i915_private *dev_priv = dev->dev_private;
1195         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1196         u32 temp;
1197         bool enabled;
1198
1199         if (IS_VALLEYVIEW(dev))
1200                 return;
1201
1202         dev_priv->mchbar_need_disable = false;
1203
1204         if (IS_I915G(dev) || IS_I915GM(dev)) {
1205                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1206                 enabled = !!(temp & DEVEN_MCHBAR_EN);
1207         } else {
1208                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1209                 enabled = temp & 1;
1210         }
1211
1212         /* If it's already enabled, don't have to do anything */
1213         if (enabled)
1214                 return;
1215
1216         if (intel_alloc_mchbar_resource(dev))
1217                 return;
1218
1219         dev_priv->mchbar_need_disable = true;
1220
1221         /* Space is allocated or reserved, so enable it. */
1222         if (IS_I915G(dev) || IS_I915GM(dev)) {
1223                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
1224                                        temp | DEVEN_MCHBAR_EN);
1225         } else {
1226                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1227                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
1228         }
1229 }
1230
1231 static void
1232 intel_teardown_mchbar(struct drm_device *dev)
1233 {
1234         struct drm_i915_private *dev_priv = dev->dev_private;
1235         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1236         u32 temp;
1237
1238         if (dev_priv->mchbar_need_disable) {
1239                 if (IS_I915G(dev) || IS_I915GM(dev)) {
1240                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
1241                         temp &= ~DEVEN_MCHBAR_EN;
1242                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
1243                 } else {
1244                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
1245                         temp &= ~1;
1246                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
1247                 }
1248         }
1249
1250         if (dev_priv->mch_res.start)
1251                 release_resource(&dev_priv->mch_res);
1252 }
1253
1254 /* true = enable decode, false = disable decoder */
1255 static unsigned int i915_vga_set_decode(void *cookie, bool state)
1256 {
1257         struct drm_device *dev = cookie;
1258
1259         intel_modeset_vga_set_state(dev, state);
1260         if (state)
1261                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1262                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1263         else
1264                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1265 }
1266
1267 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1268 {
1269         struct drm_device *dev = pci_get_drvdata(pdev);
1270         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
1271
1272         if (state == VGA_SWITCHEROO_ON) {
1273                 pr_info("switched on\n");
1274                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1275                 /* i915 resume handler doesn't set to D0 */
1276                 pci_set_power_state(dev->pdev, PCI_D0);
1277                 i915_resume(dev);
1278                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1279         } else {
1280                 pr_err("switched off\n");
1281                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1282                 i915_suspend(dev, pmm);
1283                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1284         }
1285 }
1286
1287 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
1288 {
1289         struct drm_device *dev = pci_get_drvdata(pdev);
1290
1291         /*
1292          * FIXME: open_count is protected by drm_global_mutex but that would lead to
1293          * locking inversion with the driver load path. And the access here is
1294          * completely racy anyway. So don't bother with locking for now.
1295          */
1296         return dev->open_count == 0;
1297 }
1298
1299 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
1300         .set_gpu_state = i915_switcheroo_set_state,
1301         .reprobe = NULL,
1302         .can_switch = i915_switcheroo_can_switch,
1303 };
1304
1305 static int i915_load_modeset_init(struct drm_device *dev)
1306 {
1307         struct drm_i915_private *dev_priv = dev->dev_private;
1308         int ret;
1309
1310         ret = intel_parse_bios(dev);
1311         if (ret)
1312                 DRM_INFO("failed to find VBIOS tables\n");
1313
1314         /* If we have > 1 VGA cards, then we need to arbitrate access
1315          * to the common VGA resources.
1316          *
1317          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
1318          * then we do not take part in VGA arbitration and the
1319          * vga_client_register() fails with -ENODEV.
1320          */
1321         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1322         if (ret && ret != -ENODEV)
1323                 goto out;
1324
1325         intel_register_dsm_handler();
1326
1327         ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops, false);
1328         if (ret)
1329                 goto cleanup_vga_client;
1330
1331         /* Initialise stolen first so that we may reserve preallocated
1332          * objects for the BIOS to KMS transition.
1333          */
1334         ret = i915_gem_init_stolen(dev);
1335         if (ret)
1336                 goto cleanup_vga_switcheroo;
1337
1338         intel_power_domains_init_hw(dev_priv);
1339
1340         /*
1341          * We enable some interrupt sources in our postinstall hooks, so mark
1342          * interrupts as enabled _before_ actually enabling them to avoid
1343          * special cases in our ordering checks.
1344          */
1345         dev_priv->pm._irqs_disabled = false;
1346
1347         ret = drm_irq_install(dev, dev->pdev->irq);
1348         if (ret)
1349                 goto cleanup_gem_stolen;
1350
1351         /* Important: The output setup functions called by modeset_init need
1352          * working irqs for e.g. gmbus and dp aux transfers. */
1353         intel_modeset_init(dev);
1354
1355         ret = i915_gem_init(dev);
1356         if (ret)
1357                 goto cleanup_irq;
1358
1359         intel_modeset_gem_init(dev);
1360
1361         /* Always safe in the mode setting case. */
1362         /* FIXME: do pre/post-mode set stuff in core KMS code */
1363         dev->vblank_disable_allowed = true;
1364         if (INTEL_INFO(dev)->num_pipes == 0)
1365                 return 0;
1366
1367         ret = intel_fbdev_init(dev);
1368         if (ret)
1369                 goto cleanup_gem;
1370
1371         /* Only enable hotplug handling once the fbdev is fully set up. */
1372         intel_hpd_init(dev);
1373
1374         /*
1375          * Some ports require correctly set-up hpd registers for detection to
1376          * work properly (leading to ghost connected connector status), e.g. VGA
1377          * on gm45.  Hence we can only set up the initial fbdev config after hpd
1378          * irqs are fully enabled. Now we should scan for the initial config
1379          * only once hotplug handling is enabled, but due to screwed-up locking
1380          * around kms/fbdev init we can't protect the fdbev initial config
1381          * scanning against hotplug events. Hence do this first and ignore the
1382          * tiny window where we will loose hotplug notifactions.
1383          */
1384         intel_fbdev_initial_config(dev);
1385
1386         drm_kms_helper_poll_init(dev);
1387
1388         return 0;
1389
1390 cleanup_gem:
1391         mutex_lock(&dev->struct_mutex);
1392         i915_gem_cleanup_ringbuffer(dev);
1393         i915_gem_context_fini(dev);
1394         mutex_unlock(&dev->struct_mutex);
1395 cleanup_irq:
1396         drm_irq_uninstall(dev);
1397 cleanup_gem_stolen:
1398         i915_gem_cleanup_stolen(dev);
1399 cleanup_vga_switcheroo:
1400         vga_switcheroo_unregister_client(dev->pdev);
1401 cleanup_vga_client:
1402         vga_client_register(dev->pdev, NULL, NULL, NULL);
1403 out:
1404         return ret;
1405 }
1406
1407 int i915_master_create(struct drm_device *dev, struct drm_master *master)
1408 {
1409         struct drm_i915_master_private *master_priv;
1410
1411         master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
1412         if (!master_priv)
1413                 return -ENOMEM;
1414
1415         master->driver_priv = master_priv;
1416         return 0;
1417 }
1418
1419 void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
1420 {
1421         struct drm_i915_master_private *master_priv = master->driver_priv;
1422
1423         if (!master_priv)
1424                 return;
1425
1426         kfree(master_priv);
1427
1428         master->driver_priv = NULL;
1429 }
1430
1431 #if IS_ENABLED(CONFIG_FB)
1432 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
1433 {
1434         struct apertures_struct *ap;
1435         struct pci_dev *pdev = dev_priv->dev->pdev;
1436         bool primary;
1437         int ret;
1438
1439         ap = alloc_apertures(1);
1440         if (!ap)
1441                 return -ENOMEM;
1442
1443         ap->ranges[0].base = dev_priv->gtt.mappable_base;
1444         ap->ranges[0].size = dev_priv->gtt.mappable_end;
1445
1446         primary =
1447                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
1448
1449         ret = remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
1450
1451         kfree(ap);
1452
1453         return ret;
1454 }
1455 #else
1456 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
1457 {
1458         return 0;
1459 }
1460 #endif
1461
1462 #if !defined(CONFIG_VGA_CONSOLE)
1463 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
1464 {
1465         return 0;
1466 }
1467 #elif !defined(CONFIG_DUMMY_CONSOLE)
1468 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
1469 {
1470         return -ENODEV;
1471 }
1472 #else
1473 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
1474 {
1475         int ret = 0;
1476
1477         DRM_INFO("Replacing VGA console driver\n");
1478
1479         console_lock();
1480         if (con_is_bound(&vga_con))
1481                 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
1482         if (ret == 0) {
1483                 ret = do_unregister_con_driver(&vga_con);
1484
1485                 /* Ignore "already unregistered". */
1486                 if (ret == -ENODEV)
1487                         ret = 0;
1488         }
1489         console_unlock();
1490
1491         return ret;
1492 }
1493 #endif
1494
1495 static void i915_dump_device_info(struct drm_i915_private *dev_priv)
1496 {
1497         const struct intel_device_info *info = &dev_priv->info;
1498
1499 #define PRINT_S(name) "%s"
1500 #define SEP_EMPTY
1501 #define PRINT_FLAG(name) info->name ? #name "," : ""
1502 #define SEP_COMMA ,
1503         DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x rev=0x%02x flags="
1504                          DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY),
1505                          info->gen,
1506                          dev_priv->dev->pdev->device,
1507                          dev_priv->dev->pdev->revision,
1508                          DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA));
1509 #undef PRINT_S
1510 #undef SEP_EMPTY
1511 #undef PRINT_FLAG
1512 #undef SEP_COMMA
1513 }
1514
1515 /*
1516  * Determine various intel_device_info fields at runtime.
1517  *
1518  * Use it when either:
1519  *   - it's judged too laborious to fill n static structures with the limit
1520  *     when a simple if statement does the job,
1521  *   - run-time checks (eg read fuse/strap registers) are needed.
1522  *
1523  * This function needs to be called:
1524  *   - after the MMIO has been setup as we are reading registers,
1525  *   - after the PCH has been detected,
1526  *   - before the first usage of the fields it can tweak.
1527  */
1528 static void intel_device_info_runtime_init(struct drm_device *dev)
1529 {
1530         struct drm_i915_private *dev_priv = dev->dev_private;
1531         struct intel_device_info *info;
1532         enum pipe pipe;
1533
1534         info = (struct intel_device_info *)&dev_priv->info;
1535
1536         if (IS_VALLEYVIEW(dev))
1537                 for_each_pipe(pipe)
1538                         info->num_sprites[pipe] = 2;
1539         else
1540                 for_each_pipe(pipe)
1541                         info->num_sprites[pipe] = 1;
1542
1543         if (i915.disable_display) {
1544                 DRM_INFO("Display disabled (module parameter)\n");
1545                 info->num_pipes = 0;
1546         } else if (info->num_pipes > 0 &&
1547                    (INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) &&
1548                    !IS_VALLEYVIEW(dev)) {
1549                 u32 fuse_strap = I915_READ(FUSE_STRAP);
1550                 u32 sfuse_strap = I915_READ(SFUSE_STRAP);
1551
1552                 /*
1553                  * SFUSE_STRAP is supposed to have a bit signalling the display
1554                  * is fused off. Unfortunately it seems that, at least in
1555                  * certain cases, fused off display means that PCH display
1556                  * reads don't land anywhere. In that case, we read 0s.
1557                  *
1558                  * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
1559                  * should be set when taking over after the firmware.
1560                  */
1561                 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
1562                     sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
1563                     (dev_priv->pch_type == PCH_CPT &&
1564                      !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
1565                         DRM_INFO("Display fused off, disabling\n");
1566                         info->num_pipes = 0;
1567                 }
1568         }
1569 }
1570
1571 /**
1572  * i915_driver_load - setup chip and create an initial config
1573  * @dev: DRM device
1574  * @flags: startup flags
1575  *
1576  * The driver load routine has to do several things:
1577  *   - drive output discovery via intel_modeset_init()
1578  *   - initialize the memory manager
1579  *   - allocate initial config memory
1580  *   - setup the DRM framebuffer with the allocated memory
1581  */
1582 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1583 {
1584         struct drm_i915_private *dev_priv;
1585         struct intel_device_info *info, *device_info;
1586         int ret = 0, mmio_bar, mmio_size;
1587         uint32_t aperture_size;
1588
1589         info = (struct intel_device_info *) flags;
1590
1591         /* Refuse to load on gen6+ without kms enabled. */
1592         if (info->gen >= 6 && !drm_core_check_feature(dev, DRIVER_MODESET)) {
1593                 DRM_INFO("Your hardware requires kernel modesetting (KMS)\n");
1594                 DRM_INFO("See CONFIG_DRM_I915_KMS, nomodeset, and i915.modeset parameters\n");
1595                 return -ENODEV;
1596         }
1597
1598         /* UMS needs agp support. */
1599         if (!drm_core_check_feature(dev, DRIVER_MODESET) && !dev->agp)
1600                 return -EINVAL;
1601
1602         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
1603         if (dev_priv == NULL)
1604                 return -ENOMEM;
1605
1606         dev->dev_private = dev_priv;
1607         dev_priv->dev = dev;
1608
1609         /* Setup the write-once "constant" device info */
1610         device_info = (struct intel_device_info *)&dev_priv->info;
1611         memcpy(device_info, info, sizeof(dev_priv->info));
1612         device_info->device_id = dev->pdev->device;
1613
1614         spin_lock_init(&dev_priv->irq_lock);
1615         spin_lock_init(&dev_priv->gpu_error.lock);
1616         spin_lock_init(&dev_priv->backlight_lock);
1617         spin_lock_init(&dev_priv->uncore.lock);
1618         spin_lock_init(&dev_priv->mm.object_stat_lock);
1619         spin_lock_init(&dev_priv->mmio_flip_lock);
1620         mutex_init(&dev_priv->dpio_lock);
1621         mutex_init(&dev_priv->modeset_restore_lock);
1622
1623         intel_pm_setup(dev);
1624
1625         intel_display_crc_init(dev);
1626
1627         i915_dump_device_info(dev_priv);
1628
1629         /* Not all pre-production machines fall into this category, only the
1630          * very first ones. Almost everything should work, except for maybe
1631          * suspend/resume. And we don't implement workarounds that affect only
1632          * pre-production machines. */
1633         if (IS_HSW_EARLY_SDV(dev))
1634                 DRM_INFO("This is an early pre-production Haswell machine. "
1635                          "It may not be fully functional.\n");
1636
1637         if (i915_get_bridge_dev(dev)) {
1638                 ret = -EIO;
1639                 goto free_priv;
1640         }
1641
1642         mmio_bar = IS_GEN2(dev) ? 1 : 0;
1643         /* Before gen4, the registers and the GTT are behind different BARs.
1644          * However, from gen4 onwards, the registers and the GTT are shared
1645          * in the same BAR, so we want to restrict this ioremap from
1646          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
1647          * the register BAR remains the same size for all the earlier
1648          * generations up to Ironlake.
1649          */
1650         if (info->gen < 5)
1651                 mmio_size = 512*1024;
1652         else
1653                 mmio_size = 2*1024*1024;
1654
1655         dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
1656         if (!dev_priv->regs) {
1657                 DRM_ERROR("failed to map registers\n");
1658                 ret = -EIO;
1659                 goto put_bridge;
1660         }
1661
1662         /* This must be called before any calls to HAS_PCH_* */
1663         intel_detect_pch(dev);
1664
1665         intel_uncore_init(dev);
1666
1667         ret = i915_gem_gtt_init(dev);
1668         if (ret)
1669                 goto out_regs;
1670
1671         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1672                 ret = i915_kick_out_vgacon(dev_priv);
1673                 if (ret) {
1674                         DRM_ERROR("failed to remove conflicting VGA console\n");
1675                         goto out_gtt;
1676                 }
1677
1678                 ret = i915_kick_out_firmware_fb(dev_priv);
1679                 if (ret) {
1680                         DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
1681                         goto out_gtt;
1682                 }
1683         }
1684
1685         pci_set_master(dev->pdev);
1686
1687         /* overlay on gen2 is broken and can't address above 1G */
1688         if (IS_GEN2(dev))
1689                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
1690
1691         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
1692          * using 32bit addressing, overwriting memory if HWS is located
1693          * above 4GB.
1694          *
1695          * The documentation also mentions an issue with undefined
1696          * behaviour if any general state is accessed within a page above 4GB,
1697          * which also needs to be handled carefully.
1698          */
1699         if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1700                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
1701
1702         aperture_size = dev_priv->gtt.mappable_end;
1703
1704         dev_priv->gtt.mappable =
1705                 io_mapping_create_wc(dev_priv->gtt.mappable_base,
1706                                      aperture_size);
1707         if (dev_priv->gtt.mappable == NULL) {
1708                 ret = -EIO;
1709                 goto out_gtt;
1710         }
1711
1712         dev_priv->gtt.mtrr = arch_phys_wc_add(dev_priv->gtt.mappable_base,
1713                                               aperture_size);
1714
1715         /* The i915 workqueue is primarily used for batched retirement of
1716          * requests (and thus managing bo) once the task has been completed
1717          * by the GPU. i915_gem_retire_requests() is called directly when we
1718          * need high-priority retirement, such as waiting for an explicit
1719          * bo.
1720          *
1721          * It is also used for periodic low-priority events, such as
1722          * idle-timers and recording error state.
1723          *
1724          * All tasks on the workqueue are expected to acquire the dev mutex
1725          * so there is no point in running more than one instance of the
1726          * workqueue at any time.  Use an ordered one.
1727          */
1728         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
1729         if (dev_priv->wq == NULL) {
1730                 DRM_ERROR("Failed to create our workqueue.\n");
1731                 ret = -ENOMEM;
1732                 goto out_mtrrfree;
1733         }
1734
1735         dev_priv->dp_wq = alloc_ordered_workqueue("i915-dp", 0);
1736         if (dev_priv->dp_wq == NULL) {
1737                 DRM_ERROR("Failed to create our dp workqueue.\n");
1738                 ret = -ENOMEM;
1739                 goto out_freewq;
1740         }
1741
1742         intel_irq_init(dev);
1743         intel_uncore_sanitize(dev);
1744
1745         /* Try to make sure MCHBAR is enabled before poking at it */
1746         intel_setup_mchbar(dev);
1747         intel_setup_gmbus(dev);
1748         intel_opregion_setup(dev);
1749
1750         intel_setup_bios(dev);
1751
1752         i915_gem_load(dev);
1753
1754         /* On the 945G/GM, the chipset reports the MSI capability on the
1755          * integrated graphics even though the support isn't actually there
1756          * according to the published specs.  It doesn't appear to function
1757          * correctly in testing on 945G.
1758          * This may be a side effect of MSI having been made available for PEG
1759          * and the registers being closely associated.
1760          *
1761          * According to chipset errata, on the 965GM, MSI interrupts may
1762          * be lost or delayed, but we use them anyways to avoid
1763          * stuck interrupts on some machines.
1764          */
1765         if (!IS_I945G(dev) && !IS_I945GM(dev))
1766                 pci_enable_msi(dev->pdev);
1767
1768         intel_device_info_runtime_init(dev);
1769
1770         if (INTEL_INFO(dev)->num_pipes) {
1771                 ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
1772                 if (ret)
1773                         goto out_gem_unload;
1774         }
1775
1776         intel_power_domains_init(dev_priv);
1777
1778         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1779                 ret = i915_load_modeset_init(dev);
1780                 if (ret < 0) {
1781                         DRM_ERROR("failed to init modeset\n");
1782                         goto out_power_well;
1783                 }
1784         } else {
1785                 /* Start out suspended in ums mode. */
1786                 dev_priv->ums.mm_suspended = 1;
1787         }
1788
1789         i915_setup_sysfs(dev);
1790
1791         if (INTEL_INFO(dev)->num_pipes) {
1792                 /* Must be done after probing outputs */
1793                 intel_opregion_init(dev);
1794                 acpi_video_register();
1795         }
1796
1797         if (IS_GEN5(dev))
1798                 intel_gpu_ips_init(dev_priv);
1799
1800         intel_init_runtime_pm(dev_priv);
1801
1802         return 0;
1803
1804 out_power_well:
1805         intel_power_domains_remove(dev_priv);
1806         drm_vblank_cleanup(dev);
1807 out_gem_unload:
1808         WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier));
1809         unregister_shrinker(&dev_priv->mm.shrinker);
1810
1811         if (dev->pdev->msi_enabled)
1812                 pci_disable_msi(dev->pdev);
1813
1814         intel_teardown_gmbus(dev);
1815         intel_teardown_mchbar(dev);
1816         pm_qos_remove_request(&dev_priv->pm_qos);
1817         destroy_workqueue(dev_priv->dp_wq);
1818 out_freewq:
1819         destroy_workqueue(dev_priv->wq);
1820 out_mtrrfree:
1821         arch_phys_wc_del(dev_priv->gtt.mtrr);
1822         io_mapping_free(dev_priv->gtt.mappable);
1823 out_gtt:
1824         i915_global_gtt_cleanup(dev);
1825 out_regs:
1826         intel_uncore_fini(dev);
1827         pci_iounmap(dev->pdev, dev_priv->regs);
1828 put_bridge:
1829         pci_dev_put(dev_priv->bridge_dev);
1830 free_priv:
1831         if (dev_priv->slab)
1832                 kmem_cache_destroy(dev_priv->slab);
1833         kfree(dev_priv);
1834         return ret;
1835 }
1836
1837 int i915_driver_unload(struct drm_device *dev)
1838 {
1839         struct drm_i915_private *dev_priv = dev->dev_private;
1840         int ret;
1841
1842         ret = i915_gem_suspend(dev);
1843         if (ret) {
1844                 DRM_ERROR("failed to idle hardware: %d\n", ret);
1845                 return ret;
1846         }
1847
1848         intel_fini_runtime_pm(dev_priv);
1849
1850         intel_gpu_ips_teardown();
1851
1852         /* The i915.ko module is still not prepared to be loaded when
1853          * the power well is not enabled, so just enable it in case
1854          * we're going to unload/reload. */
1855         intel_display_set_init_power(dev_priv, true);
1856         intel_power_domains_remove(dev_priv);
1857
1858         i915_teardown_sysfs(dev);
1859
1860         WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier));
1861         unregister_shrinker(&dev_priv->mm.shrinker);
1862
1863         io_mapping_free(dev_priv->gtt.mappable);
1864         arch_phys_wc_del(dev_priv->gtt.mtrr);
1865
1866         acpi_video_unregister();
1867
1868         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1869                 intel_fbdev_fini(dev);
1870                 intel_modeset_cleanup(dev);
1871
1872                 /*
1873                  * free the memory space allocated for the child device
1874                  * config parsed from VBT
1875                  */
1876                 if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1877                         kfree(dev_priv->vbt.child_dev);
1878                         dev_priv->vbt.child_dev = NULL;
1879                         dev_priv->vbt.child_dev_num = 0;
1880                 }
1881
1882                 vga_switcheroo_unregister_client(dev->pdev);
1883                 vga_client_register(dev->pdev, NULL, NULL, NULL);
1884         }
1885
1886         /* Free error state after interrupts are fully disabled. */
1887         del_timer_sync(&dev_priv->gpu_error.hangcheck_timer);
1888         cancel_work_sync(&dev_priv->gpu_error.work);
1889         i915_destroy_error_state(dev);
1890
1891         if (dev->pdev->msi_enabled)
1892                 pci_disable_msi(dev->pdev);
1893
1894         intel_opregion_fini(dev);
1895
1896         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1897                 /* Flush any outstanding unpin_work. */
1898                 flush_workqueue(dev_priv->wq);
1899
1900                 mutex_lock(&dev->struct_mutex);
1901                 i915_gem_cleanup_ringbuffer(dev);
1902                 i915_gem_context_fini(dev);
1903                 mutex_unlock(&dev->struct_mutex);
1904                 i915_gem_cleanup_stolen(dev);
1905
1906                 if (!I915_NEED_GFX_HWS(dev))
1907                         i915_free_hws(dev);
1908         }
1909
1910         drm_vblank_cleanup(dev);
1911
1912         intel_teardown_gmbus(dev);
1913         intel_teardown_mchbar(dev);
1914
1915         destroy_workqueue(dev_priv->dp_wq);
1916         destroy_workqueue(dev_priv->wq);
1917         pm_qos_remove_request(&dev_priv->pm_qos);
1918
1919         i915_global_gtt_cleanup(dev);
1920
1921         intel_uncore_fini(dev);
1922         if (dev_priv->regs != NULL)
1923                 pci_iounmap(dev->pdev, dev_priv->regs);
1924
1925         if (dev_priv->slab)
1926                 kmem_cache_destroy(dev_priv->slab);
1927
1928         pci_dev_put(dev_priv->bridge_dev);
1929         kfree(dev_priv);
1930
1931         return 0;
1932 }
1933
1934 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1935 {
1936         int ret;
1937
1938         ret = i915_gem_open(dev, file);
1939         if (ret)
1940                 return ret;
1941
1942         return 0;
1943 }
1944
1945 /**
1946  * i915_driver_lastclose - clean up after all DRM clients have exited
1947  * @dev: DRM device
1948  *
1949  * Take care of cleaning up after all DRM clients have exited.  In the
1950  * mode setting case, we want to restore the kernel's initial mode (just
1951  * in case the last client left us in a bad state).
1952  *
1953  * Additionally, in the non-mode setting case, we'll tear down the GTT
1954  * and DMA structures, since the kernel won't be using them, and clea
1955  * up any GEM state.
1956  */
1957 void i915_driver_lastclose(struct drm_device *dev)
1958 {
1959         struct drm_i915_private *dev_priv = dev->dev_private;
1960
1961         /* On gen6+ we refuse to init without kms enabled, but then the drm core
1962          * goes right around and calls lastclose. Check for this and don't clean
1963          * up anything. */
1964         if (!dev_priv)
1965                 return;
1966
1967         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1968                 intel_fbdev_restore_mode(dev);
1969                 vga_switcheroo_process_delayed_switch();
1970                 return;
1971         }
1972
1973         i915_gem_lastclose(dev);
1974
1975         i915_dma_cleanup(dev);
1976 }
1977
1978 void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
1979 {
1980         mutex_lock(&dev->struct_mutex);
1981         i915_gem_context_close(dev, file);
1982         i915_gem_release(dev, file);
1983         mutex_unlock(&dev->struct_mutex);
1984
1985         if (drm_core_check_feature(dev, DRIVER_MODESET))
1986                 intel_modeset_preclose(dev, file);
1987 }
1988
1989 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1990 {
1991         struct drm_i915_file_private *file_priv = file->driver_priv;
1992
1993         if (file_priv && file_priv->bsd_ring)
1994                 file_priv->bsd_ring = NULL;
1995         kfree(file_priv);
1996 }
1997
1998 const struct drm_ioctl_desc i915_ioctls[] = {
1999         DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2000         DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
2001         DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
2002         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
2003         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
2004         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
2005         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
2006         DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2007         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
2008         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
2009         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2010         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
2011         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2012         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2013         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH),
2014         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
2015         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
2016         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2017         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
2018         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
2019         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2020         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
2021         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
2022         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2023         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2024         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
2025         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2026         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
2027         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2028         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2029         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2030         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2031         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2032         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2033         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2034         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2035         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2036         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2037         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
2038         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2039         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2040         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2041         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2042         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
2043         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
2044         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2045         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2046         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2047         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_get_reset_stats_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2048         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
2049 };
2050
2051 int i915_max_ioctl = ARRAY_SIZE(i915_ioctls);
2052
2053 /*
2054  * This is really ugly: Because old userspace abused the linux agp interface to
2055  * manage the gtt, we need to claim that all intel devices are agp.  For
2056  * otherwise the drm core refuses to initialize the agp support code.
2057  */
2058 int i915_driver_device_is_agp(struct drm_device *dev)
2059 {
2060         return 1;
2061 }